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ae09e9a3 | 1 | /* Compute register class preferences for pseudo-registers. |
0b387d23 | 2 | Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 |
1a6a0f2a | 3 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
0364c2b4 | 4 | Free Software Foundation, Inc. |
ae09e9a3 | 5 | |
f12b58b3 | 6 | This file is part of GCC. |
ae09e9a3 | 7 | |
f12b58b3 | 8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 2, or (at your option) any later | |
11 | version. | |
ae09e9a3 | 12 | |
f12b58b3 | 13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
ae09e9a3 | 17 | |
18 | You should have received a copy of the GNU General Public License | |
f12b58b3 | 19 | along with GCC; see the file COPYING. If not, write to the Free |
67ce556b | 20 | Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
ae09e9a3 | 22 | |
23 | ||
24 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
25 | It also defines some tables of information about the hardware registers | |
26 | and a function init_reg_sets to initialize the tables. */ | |
27 | ||
28 | #include "config.h" | |
405711de | 29 | #include "system.h" |
805e22b2 | 30 | #include "coretypes.h" |
31 | #include "tm.h" | |
897118e8 | 32 | #include "hard-reg-set.h" |
ae09e9a3 | 33 | #include "rtl.h" |
ee0548e9 | 34 | #include "expr.h" |
7953c610 | 35 | #include "tm_p.h" |
ae09e9a3 | 36 | #include "flags.h" |
37 | #include "basic-block.h" | |
38 | #include "regs.h" | |
00cb30dc | 39 | #include "addresses.h" |
0a893c29 | 40 | #include "function.h" |
ae09e9a3 | 41 | #include "insn-config.h" |
42 | #include "recog.h" | |
4023cea7 | 43 | #include "reload.h" |
44 | #include "real.h" | |
12874aaf | 45 | #include "toplev.h" |
cd03a192 | 46 | #include "output.h" |
0dddbcb3 | 47 | #include "ggc.h" |
376c21d1 | 48 | #include "timevar.h" |
3dc77328 | 49 | #include "hashtab.h" |
4d58fa46 | 50 | #include "target.h" |
3072d30e | 51 | #include "tree-pass.h" |
52 | #include "df.h" | |
53 | ||
54 | /* Maximum register number used in this function, plus one. */ | |
55 | ||
56 | int max_regno; | |
ae09e9a3 | 57 | |
3ad4992f | 58 | static void init_reg_sets_1 (void); |
3ad4992f | 59 | static void init_reg_autoinc (void); |
18525f1f | 60 | |
3d46a046 | 61 | /* If we have auto-increment or auto-decrement and we can have secondary |
62 | reloads, we are not allowed to use classes requiring secondary | |
c3418f42 | 63 | reloads for pseudos auto-incremented since reload can't handle it. */ |
4d58fa46 | 64 | /* We leave it to target hooks to decide if we have secondary reloads, so |
65 | assume that we might have them. */ | |
66 | #if defined(AUTO_INC_DEC) /* */ | |
3d46a046 | 67 | #define FORBIDDEN_INC_DEC_CLASSES |
68 | #endif | |
ae09e9a3 | 69 | \f |
70 | /* Register tables used by many passes. */ | |
71 | ||
72 | /* Indexed by hard register number, contains 1 for registers | |
73 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
74 | These are the registers that cannot be used to allocate | |
fc242db3 | 75 | a pseudo reg for general use. */ |
ae09e9a3 | 76 | |
77 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
78 | ||
79 | /* Same info as a HARD_REG_SET. */ | |
80 | ||
81 | HARD_REG_SET fixed_reg_set; | |
82 | ||
83 | /* Data for initializing the above. */ | |
84 | ||
e99c3a1d | 85 | static const char initial_fixed_regs[] = FIXED_REGISTERS; |
ae09e9a3 | 86 | |
87 | /* Indexed by hard register number, contains 1 for registers | |
88 | that are fixed use or are clobbered by function calls. | |
89 | These are the registers that cannot be used to allocate | |
fc242db3 | 90 | a pseudo reg whose life crosses calls unless we are able |
91 | to save/restore them across the calls. */ | |
ae09e9a3 | 92 | |
93 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
94 | ||
95 | /* Same info as a HARD_REG_SET. */ | |
96 | ||
97 | HARD_REG_SET call_used_reg_set; | |
98 | ||
2836f006 | 99 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
100 | HARD_REG_SET losing_caller_save_reg_set; | |
101 | ||
ae09e9a3 | 102 | /* Data for initializing the above. */ |
103 | ||
e99c3a1d | 104 | static const char initial_call_used_regs[] = CALL_USED_REGISTERS; |
d2d242b4 | 105 | |
106 | /* This is much like call_used_regs, except it doesn't have to | |
107 | be a superset of FIXED_REGISTERS. This vector indicates | |
2617fe26 | 108 | what is really call clobbered, and is used when defining |
d2d242b4 | 109 | regs_invalidated_by_call. */ |
110 | ||
d2d242b4 | 111 | #ifdef CALL_REALLY_USED_REGISTERS |
556ba85f | 112 | char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; |
d2d242b4 | 113 | #endif |
2617fe26 | 114 | |
1fbc37ff | 115 | #ifdef CALL_REALLY_USED_REGISTERS |
116 | #define CALL_REALLY_USED_REGNO_P(X) call_really_used_regs[X] | |
117 | #else | |
118 | #define CALL_REALLY_USED_REGNO_P(X) call_used_regs[X] | |
119 | #endif | |
120 | ||
121 | ||
ae09e9a3 | 122 | /* Indexed by hard register number, contains 1 for registers that are |
fc242db3 | 123 | fixed use or call used registers that cannot hold quantities across |
124 | calls even if we are willing to save and restore them. call fixed | |
125 | registers are a subset of call used registers. */ | |
ae09e9a3 | 126 | |
127 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
128 | ||
129 | /* The same info as a HARD_REG_SET. */ | |
130 | ||
131 | HARD_REG_SET call_fixed_reg_set; | |
132 | ||
ae09e9a3 | 133 | /* Indexed by hard register number, contains 1 for registers |
134 | that are being used for global register decls. | |
135 | These must be exempt from ordinary flow analysis | |
136 | and are also considered fixed. */ | |
137 | ||
138 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
546edcaa | 139 | |
140 | /* Contains 1 for registers that are set or clobbered by calls. */ | |
141 | /* ??? Ideally, this would be just call_used_regs plus global_regs, but | |
142 | for someone's bright idea to have call_used_regs strictly include | |
143 | fixed_regs. Which leaves us guessing as to the set of fixed_regs | |
144 | that are actually preserved. We know for sure that those associated | |
145 | with the local stack frame are safe, but scant others. */ | |
146 | ||
147 | HARD_REG_SET regs_invalidated_by_call; | |
148 | ||
ae09e9a3 | 149 | /* Table of register numbers in the order in which to try to use them. */ |
150 | #ifdef REG_ALLOC_ORDER | |
151 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
fbf51e51 | 152 | |
153 | /* The inverse of reg_alloc_order. */ | |
154 | int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; | |
ae09e9a3 | 155 | #endif |
156 | ||
157 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
158 | ||
0aab1048 | 159 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
160 | ||
545740b7 | 161 | /* The same information, but as an array of unsigned ints. We copy from |
162 | these unsigned ints to the table above. We do this so the tm.h files | |
fad8575f | 163 | do not have to be aware of the wordsize for machines with <= 64 regs. |
164 | Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ | |
0aab1048 | 165 | |
166 | #define N_REG_INTS \ | |
fad8575f | 167 | ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) |
0aab1048 | 168 | |
2617fe26 | 169 | static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
0aab1048 | 170 | = REG_CLASS_CONTENTS; |
ae09e9a3 | 171 | |
172 | /* For each reg class, number of regs it contains. */ | |
173 | ||
02e7a332 | 174 | unsigned int reg_class_size[N_REG_CLASSES]; |
ae09e9a3 | 175 | |
176 | /* For each reg class, table listing all the containing classes. */ | |
177 | ||
a792c500 | 178 | static enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; |
ae09e9a3 | 179 | |
180 | /* For each reg class, table listing all the classes contained in it. */ | |
181 | ||
a792c500 | 182 | static enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; |
ae09e9a3 | 183 | |
184 | /* For each pair of reg classes, | |
185 | a largest reg class contained in their union. */ | |
186 | ||
187 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
188 | ||
189 | /* For each pair of reg classes, | |
190 | the smallest reg class containing their union. */ | |
191 | ||
192 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
193 | ||
15460c97 | 194 | /* Array containing all of the register names. */ |
6fe96dec | 195 | |
da0930ba | 196 | const char * reg_names[] = REGISTER_NAMES; |
6fe96dec | 197 | |
ada8adad | 198 | /* Array containing all of the register class names. */ |
199 | ||
200 | const char * reg_class_names[] = REG_CLASS_NAMES; | |
201 | ||
d2b04fb8 | 202 | /* For each hard register, the widest mode object that it can contain. |
203 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
204 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
205 | register. */ | |
206 | ||
207 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
208 | ||
83e2a11b | 209 | /* 1 if there is a register of given mode. */ |
210 | ||
211 | bool have_regs_of_mode [MAX_MACHINE_MODE]; | |
212 | ||
0279c35a | 213 | /* 1 if class does contain register of given mode. */ |
214 | ||
215 | static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; | |
216 | ||
4023cea7 | 217 | /* Maximum cost of moving from a register in one class to a register in |
218 | another class. Based on REGISTER_MOVE_COST. */ | |
219 | ||
0ac516dc | 220 | static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
4023cea7 | 221 | |
222 | /* Similar, but here we don't have to move if the first index is a subset | |
223 | of the second so in that case the cost is zero. */ | |
224 | ||
0ac516dc | 225 | static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
f5a540b9 | 226 | |
227 | /* Similar, but here we don't have to move if the first index is a superset | |
228 | of the second so in that case the cost is zero. */ | |
229 | ||
0ac516dc | 230 | static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
4023cea7 | 231 | |
3d46a046 | 232 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
233 | ||
234 | /* These are the classes that regs which are auto-incremented or decremented | |
235 | cannot be put in. */ | |
236 | ||
237 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
238 | ||
7fd957fe | 239 | /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec |
3d46a046 | 240 | context. */ |
241 | ||
242 | static char *in_inc_dec; | |
243 | ||
313fe4bc | 244 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
3d46a046 | 245 | |
4c685015 | 246 | /* Sample MEM values for use by memory_move_secondary_cost. */ |
247 | ||
1f3233d1 | 248 | static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE]; |
4c685015 | 249 | |
7d0e67ac | 250 | /* No more global register variables may be declared; true once |
aa40f561 | 251 | regclass has been initialized. */ |
f18e6699 | 252 | |
253 | static int no_global_reg_vars = 0; | |
254 | ||
67d6c12b | 255 | /* Specify number of hard registers given machine mode occupy. */ |
256 | unsigned char hard_regno_nregs[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE]; | |
d6ff8d83 | 257 | |
3072d30e | 258 | /* Given a register bitmap, turn on the bits in a HARD_REG_SET that |
259 | correspond to the hard registers, if any, set in that map. This | |
260 | could be done far more efficiently by having all sorts of special-cases | |
261 | with moving single words, but probably isn't worth the trouble. */ | |
262 | ||
263 | void | |
264 | reg_set_to_hard_reg_set (HARD_REG_SET *to, bitmap from) | |
265 | { | |
266 | unsigned i; | |
267 | bitmap_iterator bi; | |
268 | ||
269 | EXECUTE_IF_SET_IN_BITMAP (from, 0, i, bi) | |
270 | { | |
271 | if (i >= FIRST_PSEUDO_REGISTER) | |
272 | return; | |
273 | SET_HARD_REG_BIT (*to, i); | |
274 | } | |
275 | } | |
276 | ||
277 | ||
ae09e9a3 | 278 | /* Function called only once to initialize the above data on reg usage. |
279 | Once this is done, various switches may override. */ | |
280 | ||
281 | void | |
3ad4992f | 282 | init_reg_sets (void) |
ae09e9a3 | 283 | { |
19cb6b50 | 284 | int i, j; |
ae09e9a3 | 285 | |
0aab1048 | 286 | /* First copy the register information from the initial int form into |
287 | the regsets. */ | |
288 | ||
289 | for (i = 0; i < N_REG_CLASSES; i++) | |
290 | { | |
291 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
292 | ||
81fa5697 | 293 | /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ |
0aab1048 | 294 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
81fa5697 | 295 | if (int_reg_class_contents[i][j / 32] |
296 | & ((unsigned) 1 << (j % 32))) | |
0aab1048 | 297 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
298 | } | |
299 | ||
2fd48995 | 300 | /* Sanity check: make sure the target macros FIXED_REGISTERS and |
301 | CALL_USED_REGISTERS had the right number of initializers. */ | |
04e579b6 | 302 | gcc_assert (sizeof fixed_regs == sizeof initial_fixed_regs); |
303 | gcc_assert (sizeof call_used_regs == sizeof initial_call_used_regs); | |
2fd48995 | 304 | |
b1b63592 | 305 | memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); |
306 | memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); | |
93d3b7de | 307 | memset (global_regs, 0, sizeof global_regs); |
ae09e9a3 | 308 | |
fbf51e51 | 309 | #ifdef REG_ALLOC_ORDER |
310 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
311 | inv_reg_alloc_order[reg_alloc_order[i]] = i; | |
312 | #endif | |
3b28508a | 313 | } |
314 | ||
315 | /* After switches have been processed, which perhaps alter | |
316 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
317 | ||
318 | static void | |
3ad4992f | 319 | init_reg_sets_1 (void) |
3b28508a | 320 | { |
19cb6b50 | 321 | unsigned int i, j; |
322 | unsigned int /* enum machine_mode */ m; | |
3b28508a | 323 | |
324 | /* This macro allows the fixed or call-used registers | |
325 | and the register classes to depend on target flags. */ | |
326 | ||
327 | #ifdef CONDITIONAL_REGISTER_USAGE | |
328 | CONDITIONAL_REGISTER_USAGE; | |
329 | #endif | |
330 | ||
ae09e9a3 | 331 | /* Compute number of hard regs in each class. */ |
332 | ||
f0af5a88 | 333 | memset (reg_class_size, 0, sizeof reg_class_size); |
ae09e9a3 | 334 | for (i = 0; i < N_REG_CLASSES; i++) |
335 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
336 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
337 | reg_class_size[i]++; | |
338 | ||
339 | /* Initialize the table of subunions. | |
340 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
341 | that is contained in the union of classes I and J. */ | |
342 | ||
343 | for (i = 0; i < N_REG_CLASSES; i++) | |
344 | { | |
345 | for (j = 0; j < N_REG_CLASSES; j++) | |
346 | { | |
a00f8533 | 347 | HARD_REG_SET c; |
19cb6b50 | 348 | int k; |
ae09e9a3 | 349 | |
350 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
351 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
352 | for (k = 0; k < N_REG_CLASSES; k++) | |
ddc556d1 | 353 | if (hard_reg_set_subset_p (reg_class_contents[k], c) |
354 | && !hard_reg_set_subset_p (reg_class_contents[k], | |
355 | reg_class_contents | |
356 | [(int) reg_class_subunion[i][j]])) | |
ae09e9a3 | 357 | reg_class_subunion[i][j] = (enum reg_class) k; |
ae09e9a3 | 358 | } |
359 | } | |
360 | ||
361 | /* Initialize the table of superunions. | |
362 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
363 | containing the union of classes I and J. */ | |
364 | ||
365 | for (i = 0; i < N_REG_CLASSES; i++) | |
366 | { | |
367 | for (j = 0; j < N_REG_CLASSES; j++) | |
368 | { | |
a00f8533 | 369 | HARD_REG_SET c; |
19cb6b50 | 370 | int k; |
ae09e9a3 | 371 | |
372 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
373 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
374 | for (k = 0; k < N_REG_CLASSES; k++) | |
ddc556d1 | 375 | if (hard_reg_set_subset_p (c, reg_class_contents[k])) |
376 | break; | |
ae09e9a3 | 377 | |
ae09e9a3 | 378 | reg_class_superunion[i][j] = (enum reg_class) k; |
379 | } | |
380 | } | |
381 | ||
382 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
383 | First clear the whole table, then add the elements as they are found. */ | |
384 | ||
385 | for (i = 0; i < N_REG_CLASSES; i++) | |
386 | { | |
387 | for (j = 0; j < N_REG_CLASSES; j++) | |
388 | { | |
389 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
390 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
391 | } | |
392 | } | |
393 | ||
394 | for (i = 0; i < N_REG_CLASSES; i++) | |
395 | { | |
396 | if (i == (int) NO_REGS) | |
397 | continue; | |
398 | ||
399 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
ddc556d1 | 400 | if (hard_reg_set_subset_p (reg_class_contents[i], |
401 | reg_class_contents[j])) | |
402 | { | |
403 | /* Reg class I is a subclass of J. | |
404 | Add J to the table of superclasses of I. */ | |
405 | enum reg_class *p; | |
406 | ||
407 | p = ®_class_superclasses[i][0]; | |
408 | while (*p != LIM_REG_CLASSES) p++; | |
409 | *p = (enum reg_class) j; | |
410 | /* Add I to the table of superclasses of J. */ | |
411 | p = ®_class_subclasses[j][0]; | |
412 | while (*p != LIM_REG_CLASSES) p++; | |
413 | *p = (enum reg_class) i; | |
414 | } | |
ae09e9a3 | 415 | } |
4023cea7 | 416 | |
ae09e9a3 | 417 | /* Initialize "constant" tables. */ |
418 | ||
419 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
420 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
421 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
546edcaa | 422 | CLEAR_HARD_REG_SET (regs_invalidated_by_call); |
ae09e9a3 | 423 | |
b1b63592 | 424 | memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); |
ae09e9a3 | 425 | |
ae09e9a3 | 426 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
427 | { | |
579bc712 | 428 | /* call_used_regs must include fixed_regs. */ |
04e579b6 | 429 | gcc_assert (!fixed_regs[i] || call_used_regs[i]); |
579bc712 | 430 | #ifdef CALL_REALLY_USED_REGISTERS |
431 | /* call_used_regs must include call_really_used_regs. */ | |
04e579b6 | 432 | gcc_assert (!call_really_used_regs[i] || call_used_regs[i]); |
579bc712 | 433 | #endif |
434 | ||
ae09e9a3 | 435 | if (fixed_regs[i]) |
436 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
ae09e9a3 | 437 | |
438 | if (call_used_regs[i]) | |
439 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
440 | if (call_fixed_regs[i]) | |
441 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
2836f006 | 442 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
443 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
546edcaa | 444 | |
445 | /* There are a couple of fixed registers that we know are safe to | |
446 | exclude from being clobbered by calls: | |
447 | ||
448 | The frame pointer is always preserved across calls. The arg pointer | |
449 | is if it is fixed. The stack pointer usually is, unless | |
450 | RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. | |
451 | If we are generating PIC code, the PIC offset table register is | |
452 | preserved across calls, though the target can override that. */ | |
2617fe26 | 453 | |
1fbc37ff | 454 | if (i == STACK_POINTER_REGNUM) |
455 | ; | |
456 | else if (global_regs[i]) | |
457 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); | |
458 | else if (i == FRAME_POINTER_REGNUM) | |
546edcaa | 459 | ; |
460 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
461 | else if (i == HARD_FRAME_POINTER_REGNUM) | |
462 | ; | |
463 | #endif | |
464 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
465 | else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) | |
466 | ; | |
467 | #endif | |
468 | #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED | |
3473aefe | 469 | else if (i == (unsigned) PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) |
546edcaa | 470 | ; |
471 | #endif | |
1fbc37ff | 472 | else if (CALL_REALLY_USED_REGNO_P (i)) |
546edcaa | 473 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
ae09e9a3 | 474 | } |
546edcaa | 475 | |
83e2a11b | 476 | memset (have_regs_of_mode, 0, sizeof (have_regs_of_mode)); |
cc693d06 | 477 | memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); |
0fd4500a | 478 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
cc693d06 | 479 | for (i = 0; i < N_REG_CLASSES; i++) |
bb37f971 | 480 | if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) |
0279c35a | 481 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
482 | if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) | |
483 | && HARD_REGNO_MODE_OK (j, m)) | |
484 | { | |
485 | contains_reg_of_mode [i][m] = 1; | |
83e2a11b | 486 | have_regs_of_mode [m] = 1; |
0279c35a | 487 | break; |
488 | } | |
b110f7ec | 489 | |
490 | /* Initialize the move cost table. Find every subset of each class | |
491 | and take the maximum cost of moving any subset to any other. */ | |
492 | ||
0fd4500a | 493 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
83e2a11b | 494 | if (have_regs_of_mode [m]) |
cc693d06 | 495 | { |
496 | for (i = 0; i < N_REG_CLASSES; i++) | |
497 | if (contains_reg_of_mode [i][m]) | |
498 | for (j = 0; j < N_REG_CLASSES; j++) | |
499 | { | |
500 | int cost; | |
501 | enum reg_class *p1, *p2; | |
502 | ||
503 | if (!contains_reg_of_mode [j][m]) | |
504 | { | |
505 | move_cost[m][i][j] = 65536; | |
506 | may_move_in_cost[m][i][j] = 65536; | |
507 | may_move_out_cost[m][i][j] = 65536; | |
508 | } | |
509 | else | |
510 | { | |
bb1892a6 | 511 | cost = REGISTER_MOVE_COST (m, i, j); |
cc693d06 | 512 | |
513 | for (p2 = ®_class_subclasses[j][0]; | |
514 | *p2 != LIM_REG_CLASSES; | |
515 | p2++) | |
516 | if (*p2 != i && contains_reg_of_mode [*p2][m]) | |
517 | cost = MAX (cost, move_cost [m][i][*p2]); | |
518 | ||
519 | for (p1 = ®_class_subclasses[i][0]; | |
520 | *p1 != LIM_REG_CLASSES; | |
521 | p1++) | |
522 | if (*p1 != j && contains_reg_of_mode [*p1][m]) | |
523 | cost = MAX (cost, move_cost [m][*p1][j]); | |
524 | ||
525 | move_cost[m][i][j] = cost; | |
526 | ||
527 | if (reg_class_subset_p (i, j)) | |
528 | may_move_in_cost[m][i][j] = 0; | |
529 | else | |
530 | may_move_in_cost[m][i][j] = cost; | |
531 | ||
532 | if (reg_class_subset_p (j, i)) | |
533 | may_move_out_cost[m][i][j] = 0; | |
534 | else | |
535 | may_move_out_cost[m][i][j] = cost; | |
536 | } | |
537 | } | |
c1cc1ab4 | 538 | else |
cc693d06 | 539 | for (j = 0; j < N_REG_CLASSES; j++) |
540 | { | |
541 | move_cost[m][i][j] = 65536; | |
542 | may_move_in_cost[m][i][j] = 65536; | |
543 | may_move_out_cost[m][i][j] = 65536; | |
544 | } | |
545 | } | |
fc9bfb3a | 546 | } |
547 | ||
548 | /* Compute the table of register modes. | |
549 | These values are used to record death information for individual registers | |
550 | (as opposed to a multi-register mode). */ | |
d2b04fb8 | 551 | |
c235b58a | 552 | void |
553 | init_reg_modes_once (void) | |
fc9bfb3a | 554 | { |
67d6c12b | 555 | int i, j; |
556 | ||
557 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
558 | for (j = 0; j < MAX_MACHINE_MODE; j++) | |
559 | hard_regno_nregs[i][j] = HARD_REGNO_NREGS(i, (enum machine_mode)j); | |
d2b04fb8 | 560 | |
561 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1f902da9 | 562 | { |
b805295e | 563 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1, false); |
1f902da9 | 564 | |
0868ea21 | 565 | /* If we couldn't find a valid mode, just use the previous mode. |
1f902da9 | 566 | ??? One situation in which we need to do this is on the mips where |
567 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
568 | to use DF mode for the even registers and VOIDmode for the odd | |
c3418f42 | 569 | (for the cpu models where the odd ones are inaccessible). */ |
1f902da9 | 570 | if (reg_raw_mode[i] == VOIDmode) |
0868ea21 | 571 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
1f902da9 | 572 | } |
d2b04fb8 | 573 | } |
574 | ||
fc9bfb3a | 575 | /* Finish initializing the register sets and |
576 | initialize the register modes. */ | |
577 | ||
578 | void | |
3ad4992f | 579 | init_regs (void) |
fc9bfb3a | 580 | { |
581 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
582 | until after register usage was specified. */ | |
b54842d8 | 583 | init_reg_sets_1 (); |
fc9bfb3a | 584 | |
c8a9f9bf | 585 | init_reg_autoinc (); |
90295bd2 | 586 | } |
587 | ||
588 | /* Initialize some fake stack-frame MEM references for use in | |
589 | memory_move_secondary_cost. */ | |
4c685015 | 590 | |
90295bd2 | 591 | void |
3ad4992f | 592 | init_fake_stack_mems (void) |
90295bd2 | 593 | { |
4c685015 | 594 | { |
4c685015 | 595 | int i; |
c58d0063 | 596 | |
4c685015 | 597 | for (i = 0; i < MAX_MACHINE_MODE; i++) |
9e042f31 | 598 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
4c685015 | 599 | } |
fc9bfb3a | 600 | } |
601 | ||
4c685015 | 602 | |
3afef759 | 603 | /* Compute extra cost of moving registers to/from memory due to reloads. |
604 | Only needed if secondary reloads are required for memory moves. */ | |
4c685015 | 605 | |
3afef759 | 606 | int |
3ad4992f | 607 | memory_move_secondary_cost (enum machine_mode mode, enum reg_class class, int in) |
3afef759 | 608 | { |
609 | enum reg_class altclass; | |
610 | int partial_cost = 0; | |
3afef759 | 611 | /* We need a memory reference to feed to SECONDARY... macros. */ |
aa40f561 | 612 | /* mem may be unused even if the SECONDARY_ macros are defined. */ |
c5b89159 | 613 | rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; |
614 | ||
3afef759 | 615 | |
4d58fa46 | 616 | altclass = secondary_reload_class (in ? 1 : 0, class, mode, mem); |
4c685015 | 617 | |
3afef759 | 618 | if (altclass == NO_REGS) |
619 | return 0; | |
620 | ||
621 | if (in) | |
0ac516dc | 622 | partial_cost = REGISTER_MOVE_COST (mode, altclass, class); |
3afef759 | 623 | else |
0ac516dc | 624 | partial_cost = REGISTER_MOVE_COST (mode, class, altclass); |
3afef759 | 625 | |
626 | if (class == altclass) | |
627 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
628 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
629 | here in that case. | |
630 | ||
04e579b6 | 631 | I'm tempted to put in an assert here, but returning this will |
3afef759 | 632 | probably only give poor estimates, which is what we would've |
633 | had before this code anyways. */ | |
634 | return partial_cost; | |
635 | ||
636 | /* Check if the secondary reload register will also need a | |
637 | secondary reload. */ | |
638 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
639 | } | |
3afef759 | 640 | |
d2b04fb8 | 641 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
b805295e | 642 | enough to save nregs. If we can't find one, return VOIDmode. |
643 | If CALL_SAVED is true, only consider modes that are call saved. */ | |
d2b04fb8 | 644 | |
645 | enum machine_mode | |
3ad4992f | 646 | choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED, |
b805295e | 647 | unsigned int nregs, bool call_saved) |
d2b04fb8 | 648 | { |
0fd4500a | 649 | unsigned int /* enum machine_mode */ m; |
d2b04fb8 | 650 | enum machine_mode found_mode = VOIDmode, mode; |
651 | ||
652 | /* We first look for the largest integer mode that can be validly | |
653 | held in REGNO. If none, we look for the largest floating-point mode. | |
654 | If we still didn't find a valid mode, try CCmode. */ | |
655 | ||
656 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
657 | mode != VOIDmode; | |
658 | mode = GET_MODE_WIDER_MODE (mode)) | |
67d6c12b | 659 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
b805295e | 660 | && HARD_REGNO_MODE_OK (regno, mode) |
661 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
d2b04fb8 | 662 | found_mode = mode; |
663 | ||
664 | if (found_mode != VOIDmode) | |
665 | return found_mode; | |
666 | ||
667 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
668 | mode != VOIDmode; | |
669 | mode = GET_MODE_WIDER_MODE (mode)) | |
67d6c12b | 670 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
b805295e | 671 | && HARD_REGNO_MODE_OK (regno, mode) |
672 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
d2b04fb8 | 673 | found_mode = mode; |
674 | ||
675 | if (found_mode != VOIDmode) | |
676 | return found_mode; | |
677 | ||
47c327df | 678 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); |
679 | mode != VOIDmode; | |
680 | mode = GET_MODE_WIDER_MODE (mode)) | |
67d6c12b | 681 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
b805295e | 682 | && HARD_REGNO_MODE_OK (regno, mode) |
683 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
47c327df | 684 | found_mode = mode; |
685 | ||
686 | if (found_mode != VOIDmode) | |
687 | return found_mode; | |
688 | ||
689 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); | |
690 | mode != VOIDmode; | |
691 | mode = GET_MODE_WIDER_MODE (mode)) | |
67d6c12b | 692 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
b805295e | 693 | && HARD_REGNO_MODE_OK (regno, mode) |
694 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
47c327df | 695 | found_mode = mode; |
696 | ||
697 | if (found_mode != VOIDmode) | |
698 | return found_mode; | |
699 | ||
595d8922 | 700 | /* Iterate over all of the CCmodes. */ |
0fd4500a | 701 | for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) |
702 | { | |
703 | mode = (enum machine_mode) m; | |
67d6c12b | 704 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
b805295e | 705 | && HARD_REGNO_MODE_OK (regno, mode) |
706 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
0fd4500a | 707 | return mode; |
708 | } | |
d2b04fb8 | 709 | |
710 | /* We can't find a mode valid for this register. */ | |
711 | return VOIDmode; | |
ae09e9a3 | 712 | } |
713 | ||
714 | /* Specify the usage characteristics of the register named NAME. | |
715 | It should be a fixed register if FIXED and a | |
716 | call-used register if CALL_USED. */ | |
717 | ||
718 | void | |
3ad4992f | 719 | fix_register (const char *name, int fixed, int call_used) |
ae09e9a3 | 720 | { |
721 | int i; | |
722 | ||
723 | /* Decode the name and update the primary form of | |
724 | the register info. */ | |
725 | ||
4c0b30a9 | 726 | if ((i = decode_reg_name (name)) >= 0) |
727 | { | |
2c330d86 | 728 | if ((i == STACK_POINTER_REGNUM |
729 | #ifdef HARD_FRAME_POINTER_REGNUM | |
730 | || i == HARD_FRAME_POINTER_REGNUM | |
731 | #else | |
732 | || i == FRAME_POINTER_REGNUM | |
733 | #endif | |
734 | ) | |
735 | && (fixed == 0 || call_used == 0)) | |
736 | { | |
d2ca078f | 737 | static const char * const what_option[2][2] = { |
4063e82c | 738 | { "call-saved", "call-used" }, |
739 | { "no-such-option", "fixed" }}; | |
2617fe26 | 740 | |
741 | error ("can't use '%s' as a %s register", name, | |
2c330d86 | 742 | what_option[fixed][call_used]); |
743 | } | |
744 | else | |
745 | { | |
746 | fixed_regs[i] = fixed; | |
747 | call_used_regs[i] = call_used; | |
e28a648c | 748 | #ifdef CALL_REALLY_USED_REGISTERS |
d2d242b4 | 749 | if (fixed == 0) |
750 | call_really_used_regs[i] = call_used; | |
556ba85f | 751 | #endif |
2c330d86 | 752 | } |
4c0b30a9 | 753 | } |
754 | else | |
ae09e9a3 | 755 | { |
c3ceba8e | 756 | warning (0, "unknown register name: %s", name); |
ae09e9a3 | 757 | } |
758 | } | |
b8f0384b | 759 | |
760 | /* Mark register number I as global. */ | |
761 | ||
762 | void | |
3ad4992f | 763 | globalize_reg (int i) |
b8f0384b | 764 | { |
7d0e67ac | 765 | if (fixed_regs[i] == 0 && no_global_reg_vars) |
f18e6699 | 766 | error ("global register variable follows a function definition"); |
767 | ||
b8f0384b | 768 | if (global_regs[i]) |
769 | { | |
c3ceba8e | 770 | warning (0, "register used for two global register variables"); |
b8f0384b | 771 | return; |
772 | } | |
773 | ||
774 | if (call_used_regs[i] && ! fixed_regs[i]) | |
c3ceba8e | 775 | warning (0, "call-clobbered register used for global register variable"); |
b8f0384b | 776 | |
777 | global_regs[i] = 1; | |
778 | ||
1fbc37ff | 779 | /* If we're globalizing the frame pointer, we need to set the |
780 | appropriate regs_invalidated_by_call bit, even if it's already | |
781 | set in fixed_regs. */ | |
782 | if (i != STACK_POINTER_REGNUM) | |
783 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); | |
784 | ||
b8f0384b | 785 | /* If already fixed, nothing else to do. */ |
786 | if (fixed_regs[i]) | |
787 | return; | |
788 | ||
789 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
170e5ff4 | 790 | #ifdef CALL_REALLY_USED_REGISTERS |
791 | call_really_used_regs[i] = 1; | |
792 | #endif | |
b8f0384b | 793 | |
794 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
795 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
796 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
797 | } | |
ae09e9a3 | 798 | \f |
799 | /* Now the data and code for the `regclass' pass, which happens | |
800 | just before local-alloc. */ | |
801 | ||
4023cea7 | 802 | /* The `costs' struct records the cost of using a hard register of each class |
803 | and of using memory for each pseudo. We use this data to set up | |
804 | register class preferences. */ | |
ae09e9a3 | 805 | |
4023cea7 | 806 | struct costs |
ae09e9a3 | 807 | { |
4023cea7 | 808 | int cost[N_REG_CLASSES]; |
809 | int mem_cost; | |
ae09e9a3 | 810 | }; |
811 | ||
41a6f238 | 812 | /* Structure used to record preferences of given pseudo. */ |
ef776217 | 813 | struct reg_pref |
814 | { | |
8ee7afab | 815 | /* (enum reg_class) prefclass is the preferred class. May be |
816 | NO_REGS if no class is better than memory. */ | |
ef776217 | 817 | char prefclass; |
818 | ||
819 | /* altclass is a register class that we should use for allocating | |
820 | pseudo if no register in the preferred class is available. | |
821 | If no register in this class is available, memory is preferred. | |
822 | ||
823 | It might appear to be more general to have a bitmask of classes here, | |
824 | but since it is recommended that there be a class corresponding to the | |
825 | union of most major pair of classes, that generality is not required. */ | |
826 | char altclass; | |
827 | }; | |
828 | ||
4023cea7 | 829 | /* Record the cost of each class for each pseudo. */ |
830 | ||
831 | static struct costs *costs; | |
832 | ||
c426f6be | 833 | /* Initialized once, and used to initialize cost values for each insn. */ |
834 | ||
835 | static struct costs init_cost; | |
836 | ||
41a6f238 | 837 | /* Record preferences of each pseudo. |
ae09e9a3 | 838 | This is available after `regclass' is run. */ |
839 | ||
ef776217 | 840 | static struct reg_pref *reg_pref; |
66adfeef | 841 | |
8172d01c | 842 | /* Frequency of executions of current insn. */ |
66adfeef | 843 | |
8172d01c | 844 | static int frequency; |
66adfeef | 845 | |
3ad4992f | 846 | static rtx scan_one_insn (rtx, int); |
847 | static void record_operand_costs (rtx, struct costs *, struct reg_pref *); | |
848 | static void dump_regclass (FILE *); | |
849 | static void record_reg_classes (int, int, rtx *, enum machine_mode *, | |
850 | const char **, rtx, struct costs *, | |
851 | struct reg_pref *); | |
4d58fa46 | 852 | static int copy_cost (rtx, enum machine_mode, enum reg_class, int, |
853 | secondary_reload_info *); | |
00cb30dc | 854 | static void record_address_regs (enum machine_mode, rtx, int, enum rtx_code, |
855 | enum rtx_code, int); | |
99c14947 | 856 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
3ad4992f | 857 | static int auto_inc_dec_reg_p (rtx, enum machine_mode); |
99c14947 | 858 | #endif |
3072d30e | 859 | static void reg_scan_mark_refs (rtx, rtx); |
ae09e9a3 | 860 | |
00cb30dc | 861 | /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */ |
862 | ||
863 | static inline bool | |
864 | ok_for_index_p_nonstrict (rtx reg) | |
865 | { | |
866 | unsigned regno = REGNO (reg); | |
867 | return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); | |
868 | } | |
869 | ||
870 | /* A version of regno_ok_for_base_p for use during regclass, when all pseudos | |
871 | should count as OK. Arguments as for regno_ok_for_base_p. */ | |
872 | ||
873 | static inline bool | |
874 | ok_for_base_p_nonstrict (rtx reg, enum machine_mode mode, | |
875 | enum rtx_code outer_code, enum rtx_code index_code) | |
876 | { | |
877 | unsigned regno = REGNO (reg); | |
878 | if (regno >= FIRST_PSEUDO_REGISTER) | |
879 | return true; | |
880 | ||
881 | return ok_for_base_p_1 (regno, mode, outer_code, index_code); | |
882 | } | |
883 | ||
ae09e9a3 | 884 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. |
885 | This function is sometimes called before the info has been computed. | |
886 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
887 | ||
888 | enum reg_class | |
3ad4992f | 889 | reg_preferred_class (int regno) |
ae09e9a3 | 890 | { |
ef776217 | 891 | if (reg_pref == 0) |
ae09e9a3 | 892 | return GENERAL_REGS; |
ef776217 | 893 | return (enum reg_class) reg_pref[regno].prefclass; |
ae09e9a3 | 894 | } |
895 | ||
4023cea7 | 896 | enum reg_class |
3ad4992f | 897 | reg_alternate_class (int regno) |
ae09e9a3 | 898 | { |
ef776217 | 899 | if (reg_pref == 0) |
4023cea7 | 900 | return ALL_REGS; |
901 | ||
ef776217 | 902 | return (enum reg_class) reg_pref[regno].altclass; |
ae09e9a3 | 903 | } |
904 | ||
c426f6be | 905 | /* Initialize some global data for this pass. */ |
ae09e9a3 | 906 | |
3072d30e | 907 | static unsigned int |
3ad4992f | 908 | regclass_init (void) |
ae09e9a3 | 909 | { |
c426f6be | 910 | int i; |
911 | ||
3072d30e | 912 | if (df) |
913 | df_compute_regs_ever_live (true); | |
914 | ||
c426f6be | 915 | init_cost.mem_cost = 10000; |
916 | for (i = 0; i < N_REG_CLASSES; i++) | |
917 | init_cost.cost[i] = 10000; | |
918 | ||
919 | /* This prevents dump_flow_info from losing if called | |
920 | before regclass is run. */ | |
ef776217 | 921 | reg_pref = NULL; |
f18e6699 | 922 | |
aa40f561 | 923 | /* No more global register variables may be declared. */ |
f18e6699 | 924 | no_global_reg_vars = 1; |
3072d30e | 925 | return 1; |
ae09e9a3 | 926 | } |
3072d30e | 927 | |
928 | struct tree_opt_pass pass_regclass_init = | |
929 | { | |
930 | "regclass", /* name */ | |
931 | NULL, /* gate */ | |
932 | regclass_init, /* execute */ | |
933 | NULL, /* sub */ | |
934 | NULL, /* next */ | |
935 | 0, /* static_pass_number */ | |
936 | 0, /* tv_id */ | |
937 | 0, /* properties_required */ | |
938 | 0, /* properties_provided */ | |
939 | 0, /* properties_destroyed */ | |
940 | 0, /* todo_flags_start */ | |
941 | 0, /* todo_flags_finish */ | |
942 | 'k' /* letter */ | |
943 | }; | |
944 | ||
945 | ||
ac147b1a | 946 | \f |
947 | /* Dump register costs. */ | |
20cfb17d | 948 | static void |
3ad4992f | 949 | dump_regclass (FILE *dump) |
ac147b1a | 950 | { |
ac147b1a | 951 | int i; |
952 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
953 | { | |
0fd4500a | 954 | int /* enum reg_class */ class; |
ac147b1a | 955 | if (REG_N_REFS (i)) |
956 | { | |
299a8d4e | 957 | fprintf (dump, " Register %i costs:", i); |
0fd4500a | 958 | for (class = 0; class < (int) N_REG_CLASSES; class++) |
959 | if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] | |
0279c35a | 960 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
0fd4500a | 961 | && (!in_inc_dec[i] |
962 | || !forbidden_inc_dec_class[(enum reg_class) class]) | |
0279c35a | 963 | #endif |
897118e8 | 964 | #ifdef CANNOT_CHANGE_MODE_CLASS |
965 | && ! invalid_mode_change_p (i, (enum reg_class) class, | |
966 | PSEUDO_REGNO_MODE (i)) | |
0279c35a | 967 | #endif |
968 | ) | |
0fd4500a | 969 | fprintf (dump, " %s:%i", reg_class_names[class], |
970 | costs[i].cost[(enum reg_class) class]); | |
299a8d4e | 971 | fprintf (dump, " MEM:%i\n", costs[i].mem_cost); |
ac147b1a | 972 | } |
973 | } | |
974 | } | |
299a8d4e | 975 | \f |
976 | ||
977 | /* Calculate the costs of insn operands. */ | |
978 | ||
979 | static void | |
3ad4992f | 980 | record_operand_costs (rtx insn, struct costs *op_costs, |
981 | struct reg_pref *reg_pref) | |
299a8d4e | 982 | { |
983 | const char *constraints[MAX_RECOG_OPERANDS]; | |
984 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
299a8d4e | 985 | int i; |
986 | ||
987 | for (i = 0; i < recog_data.n_operands; i++) | |
988 | { | |
989 | constraints[i] = recog_data.constraints[i]; | |
990 | modes[i] = recog_data.operand_mode[i]; | |
991 | } | |
299a8d4e | 992 | |
993 | /* If we get here, we are set up to record the costs of all the | |
994 | operands for this insn. Start by initializing the costs. | |
995 | Then handle any address registers. Finally record the desired | |
996 | classes for any pseudos, doing it twice if some pair of | |
997 | operands are commutative. */ | |
2617fe26 | 998 | |
299a8d4e | 999 | for (i = 0; i < recog_data.n_operands; i++) |
1000 | { | |
1001 | op_costs[i] = init_cost; | |
1002 | ||
1003 | if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
897118e8 | 1004 | recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); |
299a8d4e | 1005 | |
e16ceb8e | 1006 | if (MEM_P (recog_data.operand[i])) |
00cb30dc | 1007 | record_address_regs (GET_MODE (recog_data.operand[i]), |
1008 | XEXP (recog_data.operand[i], 0), | |
1009 | 0, MEM, SCRATCH, frequency * 2); | |
a5004c3d | 1010 | else if (constraints[i][0] == 'p' |
48ea5577 | 1011 | || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i])) |
00cb30dc | 1012 | record_address_regs (VOIDmode, recog_data.operand[i], 0, ADDRESS, |
1013 | SCRATCH, frequency * 2); | |
299a8d4e | 1014 | } |
1015 | ||
1016 | /* Check for commutative in a separate loop so everything will | |
1017 | have been initialized. We must do this even if one operand | |
1018 | is a constant--see addsi3 in m68k.md. */ | |
1019 | ||
1020 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
1021 | if (constraints[i][0] == '%') | |
1022 | { | |
1023 | const char *xconstraints[MAX_RECOG_OPERANDS]; | |
1024 | int j; | |
ac147b1a | 1025 | |
299a8d4e | 1026 | /* Handle commutative operands by swapping the constraints. |
1027 | We assume the modes are the same. */ | |
1028 | ||
1029 | for (j = 0; j < recog_data.n_operands; j++) | |
1030 | xconstraints[j] = constraints[j]; | |
1031 | ||
1032 | xconstraints[i] = constraints[i+1]; | |
1033 | xconstraints[i+1] = constraints[i]; | |
1034 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
2617fe26 | 1035 | recog_data.operand, modes, |
299a8d4e | 1036 | xconstraints, insn, op_costs, reg_pref); |
1037 | } | |
1038 | ||
1039 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
2617fe26 | 1040 | recog_data.operand, modes, |
299a8d4e | 1041 | constraints, insn, op_costs, reg_pref); |
1042 | } | |
ae09e9a3 | 1043 | \f |
c426f6be | 1044 | /* Subroutine of regclass, processes one insn INSN. Scan it and record each |
1045 | time it would save code to put a certain register in a certain class. | |
1046 | PASS, when nonzero, inhibits some optimizations which need only be done | |
1047 | once. | |
1048 | Return the last insn processed, so that the scan can be continued from | |
1049 | there. */ | |
1050 | ||
1051 | static rtx | |
8c96295a | 1052 | scan_one_insn (rtx insn, int pass ATTRIBUTE_UNUSED) |
c426f6be | 1053 | { |
c426f6be | 1054 | enum rtx_code pat_code; |
7f82be90 | 1055 | rtx set, note; |
c426f6be | 1056 | int i, j; |
299a8d4e | 1057 | struct costs op_costs[MAX_RECOG_OPERANDS]; |
c426f6be | 1058 | |
6720e96c | 1059 | if (!INSN_P (insn)) |
c426f6be | 1060 | return insn; |
1061 | ||
1062 | pat_code = GET_CODE (PATTERN (insn)); | |
1063 | if (pat_code == USE | |
1064 | || pat_code == CLOBBER | |
1065 | || pat_code == ASM_INPUT | |
1066 | || pat_code == ADDR_VEC | |
1067 | || pat_code == ADDR_DIFF_VEC) | |
1068 | return insn; | |
1069 | ||
7f82be90 | 1070 | set = single_set (insn); |
1071 | extract_insn (insn); | |
1072 | ||
7f82be90 | 1073 | /* If this insn loads a parameter from its stack slot, then |
1074 | it represents a savings, rather than a cost, if the | |
1075 | parameter is stored in memory. Record this fact. */ | |
c426f6be | 1076 | |
8ad4c111 | 1077 | if (set != 0 && REG_P (SET_DEST (set)) |
e16ceb8e | 1078 | && MEM_P (SET_SRC (set)) |
7f82be90 | 1079 | && (note = find_reg_note (insn, REG_EQUIV, |
1080 | NULL_RTX)) != 0 | |
e16ceb8e | 1081 | && MEM_P (XEXP (note, 0))) |
7f82be90 | 1082 | { |
1083 | costs[REGNO (SET_DEST (set))].mem_cost | |
1084 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), | |
1085 | GENERAL_REGS, 1) | |
8172d01c | 1086 | * frequency); |
00cb30dc | 1087 | record_address_regs (GET_MODE (SET_SRC (set)), XEXP (SET_SRC (set), 0), |
1088 | 0, MEM, SCRATCH, frequency * 2); | |
7f82be90 | 1089 | return insn; |
1090 | } | |
c426f6be | 1091 | |
d1c0bcc3 | 1092 | record_operand_costs (insn, op_costs, reg_pref); |
c426f6be | 1093 | |
1094 | /* Now add the cost for each operand to the total costs for | |
1095 | its register. */ | |
1096 | ||
ed420a25 | 1097 | for (i = 0; i < recog_data.n_operands; i++) |
8ad4c111 | 1098 | if (REG_P (recog_data.operand[i]) |
ed420a25 | 1099 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) |
c426f6be | 1100 | { |
ed420a25 | 1101 | int regno = REGNO (recog_data.operand[i]); |
c426f6be | 1102 | struct costs *p = &costs[regno], *q = &op_costs[i]; |
1103 | ||
8172d01c | 1104 | p->mem_cost += q->mem_cost * frequency; |
c426f6be | 1105 | for (j = 0; j < N_REG_CLASSES; j++) |
8172d01c | 1106 | p->cost[j] += q->cost[j] * frequency; |
c426f6be | 1107 | } |
1108 | ||
1109 | return insn; | |
1110 | } | |
1111 | ||
c8a9f9bf | 1112 | /* Initialize information about which register classes can be used for |
1113 | pseudos that are auto-incremented or auto-decremented. */ | |
ae09e9a3 | 1114 | |
c8a9f9bf | 1115 | static void |
3ad4992f | 1116 | init_reg_autoinc (void) |
ae09e9a3 | 1117 | { |
3d46a046 | 1118 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
c8a9f9bf | 1119 | int i; |
3d46a046 | 1120 | |
1121 | for (i = 0; i < N_REG_CLASSES; i++) | |
1122 | { | |
c8a9f9bf | 1123 | rtx r = gen_rtx_raw_REG (VOIDmode, 0); |
3d46a046 | 1124 | enum machine_mode m; |
19cb6b50 | 1125 | int j; |
3d46a046 | 1126 | |
1127 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1128 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
1129 | { | |
3072d30e | 1130 | SET_REGNO (r, j); |
3d46a046 | 1131 | |
1132 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
13df24e3 | 1133 | m = (enum machine_mode) ((int) m + 1)) |
3d46a046 | 1134 | if (HARD_REGNO_MODE_OK (j, m)) |
1135 | { | |
00cb30dc | 1136 | /* ??? There are two assumptions here; that the base class does not |
1137 | depend on the exact outer code (POST_INC vs. PRE_INC etc.), and | |
1138 | that it does not depend on the machine mode of the memory | |
1139 | reference. */ | |
1140 | enum reg_class base_class | |
1141 | = base_reg_class (VOIDmode, POST_INC, SCRATCH); | |
4d58fa46 | 1142 | |
3d46a046 | 1143 | PUT_MODE (r, m); |
4ac7d2be | 1144 | |
1145 | /* If a register is not directly suitable for an | |
1146 | auto-increment or decrement addressing mode and | |
1147 | requires secondary reloads, disallow its class from | |
1148 | being used in such addresses. */ | |
1149 | ||
4d58fa46 | 1150 | if ((secondary_reload_class (1, base_class, m, r) |
1151 | || secondary_reload_class (1, base_class, m, r)) | |
4ac7d2be | 1152 | && ! auto_inc_dec_reg_p (r, m)) |
3d46a046 | 1153 | forbidden_inc_dec_class[i] = 1; |
1154 | } | |
1155 | } | |
1156 | } | |
c8a9f9bf | 1157 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
1158 | } | |
1159 | ||
1160 | /* This is a pass of the compiler that scans all instructions | |
1161 | and calculates the preferred class for each pseudo-register. | |
1162 | This information can be accessed later by calling `reg_preferred_class'. | |
1163 | This pass comes just before local register allocation. */ | |
1164 | ||
1165 | void | |
3f5be5f4 | 1166 | regclass (rtx f, int nregs) |
c8a9f9bf | 1167 | { |
1168 | rtx insn; | |
1169 | int i; | |
1170 | int pass; | |
3072d30e | 1171 | max_regno = max_reg_num (); |
c8a9f9bf | 1172 | |
1173 | init_recog (); | |
1174 | ||
3072d30e | 1175 | reg_renumber = xmalloc (max_regno * sizeof (short)); |
1176 | reg_pref = XCNEWVEC (struct reg_pref, max_regno); | |
1177 | memset (reg_renumber, -1, max_regno * sizeof (short)); | |
1178 | ||
4c36ffe6 | 1179 | costs = XNEWVEC (struct costs, nregs); |
c8a9f9bf | 1180 | |
1181 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1182 | ||
4c36ffe6 | 1183 | in_inc_dec = XNEWVEC (char, nregs); |
c8a9f9bf | 1184 | |
3d46a046 | 1185 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
1186 | ||
4023cea7 | 1187 | /* Normally we scan the insns once and determine the best class to use for |
1188 | each register. However, if -fexpensive_optimizations are on, we do so | |
1189 | twice, the second time using the tentative best classes to guide the | |
1190 | selection. */ | |
ae09e9a3 | 1191 | |
4023cea7 | 1192 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
1193 | { | |
4c26117a | 1194 | basic_block bb; |
299a8d4e | 1195 | |
3f5be5f4 | 1196 | if (dump_file) |
1197 | fprintf (dump_file, "\n\nPass %i\n\n",pass); | |
4023cea7 | 1198 | /* Zero out our accumulation of the cost of each class for each reg. */ |
ae09e9a3 | 1199 | |
f0af5a88 | 1200 | memset (costs, 0, nregs * sizeof (struct costs)); |
ae09e9a3 | 1201 | |
3d46a046 | 1202 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
93d3b7de | 1203 | memset (in_inc_dec, 0, nregs); |
3d46a046 | 1204 | #endif |
1205 | ||
4023cea7 | 1206 | /* Scan the instructions and record each time it would |
1207 | save code to put a certain register in a certain class. */ | |
1208 | ||
d8817c59 | 1209 | if (!optimize) |
ae09e9a3 | 1210 | { |
eefdec48 | 1211 | frequency = REG_FREQ_MAX; |
d8817c59 | 1212 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
1213 | insn = scan_one_insn (insn, pass); | |
ae09e9a3 | 1214 | } |
d8817c59 | 1215 | else |
4c26117a | 1216 | FOR_EACH_BB (bb) |
d8817c59 | 1217 | { |
d8817c59 | 1218 | /* Show that an insn inside a loop is likely to be executed three |
b275aace | 1219 | times more than insns outside a loop. This is much more |
1220 | aggressive than the assumptions made elsewhere and is being | |
1221 | tried as an experiment. */ | |
eefdec48 | 1222 | frequency = REG_FREQ_FROM_BB (bb); |
5496dbfc | 1223 | for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn)) |
d8817c59 | 1224 | { |
1225 | insn = scan_one_insn (insn, pass); | |
5496dbfc | 1226 | if (insn == BB_END (bb)) |
d8817c59 | 1227 | break; |
1228 | } | |
1229 | } | |
2617fe26 | 1230 | |
4023cea7 | 1231 | /* Now for each register look at how desirable each class is |
1232 | and find which class is preferred. Store that in | |
ef776217 | 1233 | `prefclass'. Record in `altclass' the largest register |
4023cea7 | 1234 | class any of whose registers is better than memory. */ |
2617fe26 | 1235 | |
3f5be5f4 | 1236 | if (dump_file) |
2617fe26 | 1237 | { |
3f5be5f4 | 1238 | dump_regclass (dump_file); |
1239 | fprintf (dump_file,"\n"); | |
299a8d4e | 1240 | } |
4023cea7 | 1241 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
ae09e9a3 | 1242 | { |
19cb6b50 | 1243 | int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
4023cea7 | 1244 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1245 | /* This is an enum reg_class, but we call it an int | |
1246 | to save lots of casts. */ | |
19cb6b50 | 1247 | int class; |
1248 | struct costs *p = &costs[i]; | |
4023cea7 | 1249 | |
93340cae | 1250 | if (regno_reg_rtx[i] == NULL) |
1251 | continue; | |
1252 | ||
adf6ebca | 1253 | /* In non-optimizing compilation REG_N_REFS is not initialized |
1254 | yet. */ | |
cb5c5698 | 1255 | if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i)) |
299a8d4e | 1256 | continue; |
1257 | ||
4023cea7 | 1258 | for (class = (int) ALL_REGS - 1; class > 0; class--) |
ae09e9a3 | 1259 | { |
3d46a046 | 1260 | /* Ignore classes that are too small for this operand or |
20dd417a | 1261 | invalid for an operand that was auto-incremented. */ |
0279c35a | 1262 | if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] |
3d46a046 | 1263 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1264 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e8e6034b | 1265 | #endif |
897118e8 | 1266 | #ifdef CANNOT_CHANGE_MODE_CLASS |
1267 | || invalid_mode_change_p (i, (enum reg_class) class, | |
1268 | PSEUDO_REGNO_MODE (i)) | |
3d46a046 | 1269 | #endif |
1270 | ) | |
4023cea7 | 1271 | ; |
1272 | else if (p->cost[class] < best_cost) | |
1273 | { | |
1274 | best_cost = p->cost[class]; | |
1275 | best = (enum reg_class) class; | |
1276 | } | |
1277 | else if (p->cost[class] == best_cost) | |
337d789b | 1278 | best = reg_class_subunion[(int) best][class]; |
ae09e9a3 | 1279 | } |
ae09e9a3 | 1280 | |
8ee7afab | 1281 | /* If no register class is better than memory, use memory. */ |
1282 | if (p->mem_cost < best_cost) | |
1283 | best = NO_REGS; | |
1284 | ||
4023cea7 | 1285 | /* Record the alternate register class; i.e., a class for which |
1286 | every register in it is better than using memory. If adding a | |
1287 | class would make a smaller class (i.e., no union of just those | |
1288 | classes exists), skip that class. The major unions of classes | |
1289 | should be provided as a register class. Don't do this if we | |
1290 | will be doing it again later. */ | |
1291 | ||
3f5be5f4 | 1292 | if ((pass == 1 || dump_file) || ! flag_expensive_optimizations) |
4023cea7 | 1293 | for (class = 0; class < N_REG_CLASSES; class++) |
1294 | if (p->cost[class] < p->mem_cost | |
121f87c5 | 1295 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
3d46a046 | 1296 | > reg_class_size[(int) alt]) |
1297 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1298 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e8e6034b | 1299 | #endif |
897118e8 | 1300 | #ifdef CANNOT_CHANGE_MODE_CLASS |
1301 | && ! invalid_mode_change_p (i, (enum reg_class) class, | |
1302 | PSEUDO_REGNO_MODE (i)) | |
3d46a046 | 1303 | #endif |
1304 | ) | |
4023cea7 | 1305 | alt = reg_class_subunion[(int) alt][class]; |
2617fe26 | 1306 | |
4023cea7 | 1307 | /* If we don't add any classes, nothing to try. */ |
1308 | if (alt == best) | |
4fe44868 | 1309 | alt = NO_REGS; |
4023cea7 | 1310 | |
3f5be5f4 | 1311 | if (dump_file |
299a8d4e | 1312 | && (reg_pref[i].prefclass != (int) best |
1313 | || reg_pref[i].altclass != (int) alt)) | |
1314 | { | |
3f5be5f4 | 1315 | fprintf (dump_file, " Register %i", i); |
299a8d4e | 1316 | if (alt == ALL_REGS || best == ALL_REGS) |
3f5be5f4 | 1317 | fprintf (dump_file, " pref %s\n", reg_class_names[(int) best]); |
299a8d4e | 1318 | else if (alt == NO_REGS) |
3f5be5f4 | 1319 | fprintf (dump_file, " pref %s or none\n", reg_class_names[(int) best]); |
299a8d4e | 1320 | else |
3f5be5f4 | 1321 | fprintf (dump_file, " pref %s, else %s\n", |
299a8d4e | 1322 | reg_class_names[(int) best], |
1323 | reg_class_names[(int) alt]); | |
1324 | } | |
1325 | ||
4023cea7 | 1326 | /* We cast to (int) because (char) hits bugs in some compilers. */ |
ef776217 | 1327 | reg_pref[i].prefclass = (int) best; |
1328 | reg_pref[i].altclass = (int) alt; | |
4023cea7 | 1329 | } |
ae09e9a3 | 1330 | } |
829c0ce9 | 1331 | |
b9cf3f63 | 1332 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1333 | free (in_inc_dec); | |
1334 | #endif | |
829c0ce9 | 1335 | free (costs); |
ae09e9a3 | 1336 | } |
1337 | \f | |
4023cea7 | 1338 | /* Record the cost of using memory or registers of various classes for |
1339 | the operands in INSN. | |
ae09e9a3 | 1340 | |
4023cea7 | 1341 | N_ALTS is the number of alternatives. |
ae09e9a3 | 1342 | |
4023cea7 | 1343 | N_OPS is the number of operands. |
1344 | ||
1345 | OPS is an array of the operands. | |
1346 | ||
1347 | MODES are the modes of the operands, in case any are VOIDmode. | |
1348 | ||
1349 | CONSTRAINTS are the constraints to use for the operands. This array | |
1350 | is modified by this procedure. | |
1351 | ||
1352 | This procedure works alternative by alternative. For each alternative | |
1353 | we assume that we will be able to allocate all pseudos to their ideal | |
1354 | register class and calculate the cost of using that alternative. Then | |
2617fe26 | 1355 | we compute for each operand that is a pseudo-register, the cost of |
4023cea7 | 1356 | having the pseudo allocated to each register class and using it in that |
1357 | alternative. To this cost is added the cost of the alternative. | |
1358 | ||
1359 | The cost of each class for this insn is its lowest cost among all the | |
1360 | alternatives. */ | |
1361 | ||
1362 | static void | |
3ad4992f | 1363 | record_reg_classes (int n_alts, int n_ops, rtx *ops, |
1364 | enum machine_mode *modes, const char **constraints, | |
1365 | rtx insn, struct costs *op_costs, | |
1366 | struct reg_pref *reg_pref) | |
ae09e9a3 | 1367 | { |
4023cea7 | 1368 | int alt; |
4023cea7 | 1369 | int i, j; |
1f8d882f | 1370 | rtx set; |
4023cea7 | 1371 | |
4023cea7 | 1372 | /* Process each alternative, each time minimizing an operand's cost with |
1373 | the cost for each operand in that alternative. */ | |
ae09e9a3 | 1374 | |
4023cea7 | 1375 | for (alt = 0; alt < n_alts; alt++) |
ae09e9a3 | 1376 | { |
4023cea7 | 1377 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1378 | int alt_fail = 0; | |
1379 | int alt_cost = 0; | |
1380 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
2cc205f8 | 1381 | int allows_mem[MAX_RECOG_OPERANDS]; |
4023cea7 | 1382 | int class; |
ae09e9a3 | 1383 | |
4023cea7 | 1384 | for (i = 0; i < n_ops; i++) |
1385 | { | |
a8482e91 | 1386 | const char *p = constraints[i]; |
4023cea7 | 1387 | rtx op = ops[i]; |
1388 | enum machine_mode mode = modes[i]; | |
65678154 | 1389 | int allows_addr = 0; |
4023cea7 | 1390 | int win = 0; |
274c11d8 | 1391 | unsigned char c; |
ae09e9a3 | 1392 | |
e9cda871 | 1393 | /* Initially show we know nothing about the register class. */ |
1394 | classes[i] = NO_REGS; | |
2cc205f8 | 1395 | allows_mem[i] = 0; |
e9cda871 | 1396 | |
2617fe26 | 1397 | /* If this operand has no constraints at all, we can conclude |
4023cea7 | 1398 | nothing about it since anything is valid. */ |
ae09e9a3 | 1399 | |
4023cea7 | 1400 | if (*p == 0) |
1401 | { | |
8ad4c111 | 1402 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) |
f0af5a88 | 1403 | memset (&this_op_costs[i], 0, sizeof this_op_costs[i]); |
ae09e9a3 | 1404 | |
4023cea7 | 1405 | continue; |
1406 | } | |
ae09e9a3 | 1407 | |
e9cda871 | 1408 | /* If this alternative is only relevant when this operand |
1409 | matches a previous operand, we do different things depending | |
1410 | on whether this operand is a pseudo-reg or not. We must process | |
1411 | any modifiers for the operand before we can make this test. */ | |
1412 | ||
9a5e3964 | 1413 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') |
7f82be90 | 1414 | p++; |
9a5e3964 | 1415 | |
4023cea7 | 1416 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1417 | { | |
2cc205f8 | 1418 | /* Copy class and whether memory is allowed from the matching |
1419 | alternative. Then perform any needed cost computations | |
1420 | and/or adjustments. */ | |
4023cea7 | 1421 | j = p[0] - '0'; |
1422 | classes[i] = classes[j]; | |
2cc205f8 | 1423 | allows_mem[i] = allows_mem[j]; |
4023cea7 | 1424 | |
8ad4c111 | 1425 | if (!REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) |
4023cea7 | 1426 | { |
1427 | /* If this matches the other operand, we have no added | |
deff29cb | 1428 | cost and we win. */ |
4023cea7 | 1429 | if (rtx_equal_p (ops[j], op)) |
deff29cb | 1430 | win = 1; |
4023cea7 | 1431 | |
64ff0ff2 | 1432 | /* If we can put the other operand into a register, add to |
1433 | the cost of this alternative the cost to copy this | |
1434 | operand to the register used for the other operand. */ | |
4023cea7 | 1435 | |
deff29cb | 1436 | else if (classes[j] != NO_REGS) |
4d58fa46 | 1437 | { |
1438 | alt_cost += copy_cost (op, mode, classes[j], 1, NULL); | |
1439 | win = 1; | |
1440 | } | |
4023cea7 | 1441 | } |
8ad4c111 | 1442 | else if (!REG_P (ops[j]) |
0c60cf1b | 1443 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) |
1444 | { | |
1445 | /* This op is a pseudo but the one it matches is not. */ | |
2617fe26 | 1446 | |
0c60cf1b | 1447 | /* If we can't put the other operand into a register, this |
1448 | alternative can't be used. */ | |
1449 | ||
1450 | if (classes[j] == NO_REGS) | |
1451 | alt_fail = 1; | |
4023cea7 | 1452 | |
0c60cf1b | 1453 | /* Otherwise, add to the cost of this alternative the cost |
1454 | to copy the other operand to the register used for this | |
1455 | operand. */ | |
1456 | ||
1457 | else | |
4d58fa46 | 1458 | alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL); |
0c60cf1b | 1459 | } |
4023cea7 | 1460 | else |
1461 | { | |
2cc205f8 | 1462 | /* The costs of this operand are not the same as the other |
1463 | operand since move costs are not symmetric. Moreover, | |
1464 | if we cannot tie them, this alternative needs to do a | |
1465 | copy, which is one instruction. */ | |
1466 | ||
1467 | struct costs *pp = &this_op_costs[i]; | |
1468 | ||
1469 | for (class = 0; class < N_REG_CLASSES; class++) | |
1470 | pp->cost[class] | |
8cd81992 | 1471 | = ((recog_data.operand_type[i] != OP_OUT |
0ac516dc | 1472 | ? may_move_in_cost[mode][class][(int) classes[i]] |
8cd81992 | 1473 | : 0) |
1474 | + (recog_data.operand_type[i] != OP_IN | |
0ac516dc | 1475 | ? may_move_out_cost[mode][(int) classes[i]][class] |
8cd81992 | 1476 | : 0)); |
2617fe26 | 1477 | |
2cc205f8 | 1478 | /* If the alternative actually allows memory, make things |
1479 | a bit cheaper since we won't need an extra insn to | |
1480 | load it. */ | |
1481 | ||
1482 | pp->mem_cost | |
8cd81992 | 1483 | = ((recog_data.operand_type[i] != OP_IN |
1484 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1485 | : 0) | |
1486 | + (recog_data.operand_type[i] != OP_OUT | |
1487 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1488 | : 0) - allows_mem[i]); | |
2cc205f8 | 1489 | |
1490 | /* If we have assigned a class to this register in our | |
1491 | first pass, add a cost to this alternative corresponding | |
1492 | to what we would add if this register were not in the | |
1493 | appropriate class. */ | |
1494 | ||
8ee7afab | 1495 | if (reg_pref && reg_pref[REGNO (op)].prefclass != NO_REGS) |
2cc205f8 | 1496 | alt_cost |
0ac516dc | 1497 | += (may_move_in_cost[mode] |
1498 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
2cc205f8 | 1499 | [(int) classes[i]]); |
4023cea7 | 1500 | |
8f03fdc8 | 1501 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1502 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1503 | alt_cost += 2; | |
4023cea7 | 1504 | |
86ff3166 | 1505 | /* This is in place of ordinary cost computation |
cf4b8e5a | 1506 | for this operand, so skip to the end of the |
1507 | alternative (should be just one character). */ | |
1508 | while (*p && *p++ != ',') | |
1509 | ; | |
1510 | ||
1511 | constraints[i] = p; | |
86ff3166 | 1512 | continue; |
1513 | } | |
4023cea7 | 1514 | } |
1515 | ||
1516 | /* Scan all the constraint letters. See if the operand matches | |
1517 | any of the constraints. Collect the valid register classes | |
1518 | and see if this operand accepts memory. */ | |
1519 | ||
48ea5577 | 1520 | while ((c = *p)) |
1521 | { | |
1522 | switch (c) | |
1523 | { | |
1524 | case ',': | |
1525 | break; | |
1526 | case '*': | |
1527 | /* Ignore the next letter for this pass. */ | |
1528 | c = *++p; | |
1529 | break; | |
65678154 | 1530 | |
48ea5577 | 1531 | case '?': |
1532 | alt_cost += 2; | |
1533 | case '!': case '#': case '&': | |
1534 | case '0': case '1': case '2': case '3': case '4': | |
1535 | case '5': case '6': case '7': case '8': case '9': | |
1536 | break; | |
4023cea7 | 1537 | |
48ea5577 | 1538 | case 'p': |
1539 | allows_addr = 1; | |
1540 | win = address_operand (op, GET_MODE (op)); | |
1541 | /* We know this operand is an address, so we want it to be | |
1542 | allocated to a register that can be the base of an | |
0c6d8c36 | 1543 | address, i.e. BASE_REG_CLASS. */ |
48ea5577 | 1544 | classes[i] |
1545 | = reg_class_subunion[(int) classes[i]] | |
00cb30dc | 1546 | [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; |
48ea5577 | 1547 | break; |
4023cea7 | 1548 | |
48ea5577 | 1549 | case 'm': case 'o': case 'V': |
1550 | /* It doesn't seem worth distinguishing between offsettable | |
1551 | and non-offsettable addresses here. */ | |
1552 | allows_mem[i] = 1; | |
e16ceb8e | 1553 | if (MEM_P (op)) |
48ea5577 | 1554 | win = 1; |
1555 | break; | |
4023cea7 | 1556 | |
48ea5577 | 1557 | case '<': |
e16ceb8e | 1558 | if (MEM_P (op) |
48ea5577 | 1559 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC |
1560 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1561 | win = 1; | |
1562 | break; | |
4023cea7 | 1563 | |
48ea5577 | 1564 | case '>': |
e16ceb8e | 1565 | if (MEM_P (op) |
48ea5577 | 1566 | && (GET_CODE (XEXP (op, 0)) == PRE_INC |
1567 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1568 | win = 1; | |
1569 | break; | |
4023cea7 | 1570 | |
48ea5577 | 1571 | case 'E': |
1572 | case 'F': | |
1573 | if (GET_CODE (op) == CONST_DOUBLE | |
1574 | || (GET_CODE (op) == CONST_VECTOR | |
1575 | && (GET_MODE_CLASS (GET_MODE (op)) | |
1576 | == MODE_VECTOR_FLOAT))) | |
1577 | win = 1; | |
1578 | break; | |
4023cea7 | 1579 | |
48ea5577 | 1580 | case 'G': |
1581 | case 'H': | |
1582 | if (GET_CODE (op) == CONST_DOUBLE | |
1583 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) | |
1584 | win = 1; | |
4023cea7 | 1585 | break; |
48ea5577 | 1586 | |
1587 | case 's': | |
1588 | if (GET_CODE (op) == CONST_INT | |
1589 | || (GET_CODE (op) == CONST_DOUBLE | |
1590 | && GET_MODE (op) == VOIDmode)) | |
1591 | break; | |
1592 | case 'i': | |
1593 | if (CONSTANT_P (op) | |
7151fd0e | 1594 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))) |
48ea5577 | 1595 | win = 1; |
1596 | break; | |
4023cea7 | 1597 | |
48ea5577 | 1598 | case 'n': |
1599 | if (GET_CODE (op) == CONST_INT | |
1600 | || (GET_CODE (op) == CONST_DOUBLE | |
1601 | && GET_MODE (op) == VOIDmode)) | |
1602 | win = 1; | |
1603 | break; | |
4023cea7 | 1604 | |
48ea5577 | 1605 | case 'I': |
1606 | case 'J': | |
1607 | case 'K': | |
1608 | case 'L': | |
1609 | case 'M': | |
1610 | case 'N': | |
1611 | case 'O': | |
1612 | case 'P': | |
1613 | if (GET_CODE (op) == CONST_INT | |
1614 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) | |
1615 | win = 1; | |
1616 | break; | |
4023cea7 | 1617 | |
48ea5577 | 1618 | case 'X': |
1619 | win = 1; | |
1620 | break; | |
ae09e9a3 | 1621 | |
48ea5577 | 1622 | case 'g': |
e16ceb8e | 1623 | if (MEM_P (op) |
48ea5577 | 1624 | || (CONSTANT_P (op) |
7151fd0e | 1625 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))) |
48ea5577 | 1626 | win = 1; |
1627 | allows_mem[i] = 1; | |
1628 | case 'r': | |
f3653a64 | 1629 | classes[i] |
48ea5577 | 1630 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; |
1631 | break; | |
a5004c3d | 1632 | |
48ea5577 | 1633 | default: |
1634 | if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS) | |
a5004c3d | 1635 | classes[i] |
1636 | = reg_class_subunion[(int) classes[i]] | |
48ea5577 | 1637 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; |
1638 | #ifdef EXTRA_CONSTRAINT_STR | |
1639 | else if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
1640 | win = 1; | |
1641 | ||
1642 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
1643 | { | |
1644 | /* Every MEM can be reloaded to fit. */ | |
1645 | allows_mem[i] = 1; | |
e16ceb8e | 1646 | if (MEM_P (op)) |
48ea5577 | 1647 | win = 1; |
1648 | } | |
1649 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
1650 | { | |
1651 | /* Every address can be reloaded to fit. */ | |
1652 | allows_addr = 1; | |
1653 | if (address_operand (op, GET_MODE (op))) | |
1654 | win = 1; | |
1655 | /* We know this operand is an address, so we want it to | |
1656 | be allocated to a register that can be the base of an | |
0c6d8c36 | 1657 | address, i.e. BASE_REG_CLASS. */ |
48ea5577 | 1658 | classes[i] |
1659 | = reg_class_subunion[(int) classes[i]] | |
00cb30dc | 1660 | [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; |
48ea5577 | 1661 | } |
f3653a64 | 1662 | #endif |
48ea5577 | 1663 | break; |
1664 | } | |
1665 | p += CONSTRAINT_LEN (c, p); | |
1666 | if (c == ',') | |
f3653a64 | 1667 | break; |
48ea5577 | 1668 | } |
4023cea7 | 1669 | |
1670 | constraints[i] = p; | |
1671 | ||
1672 | /* How we account for this operand now depends on whether it is a | |
1673 | pseudo register or not. If it is, we first check if any | |
1674 | register classes are valid. If not, we ignore this alternative, | |
1675 | since we want to assume that all pseudos get allocated for | |
1676 | register preferencing. If some register class is valid, compute | |
1677 | the costs of moving the pseudo into that class. */ | |
1678 | ||
8ad4c111 | 1679 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) |
8659a89f | 1680 | { |
4023cea7 | 1681 | if (classes[i] == NO_REGS) |
65678154 | 1682 | { |
e8e6034b | 1683 | /* We must always fail if the operand is a REG, but |
1684 | we did not find a suitable class. | |
2617fe26 | 1685 | |
e8e6034b | 1686 | Otherwise we may perform an uninitialized read |
1687 | from this_op_costs after the `continue' statement | |
1688 | below. */ | |
1689 | alt_fail = 1; | |
65678154 | 1690 | } |
4023cea7 | 1691 | else |
1692 | { | |
1693 | struct costs *pp = &this_op_costs[i]; | |
1694 | ||
1695 | for (class = 0; class < N_REG_CLASSES; class++) | |
155b05dc | 1696 | pp->cost[class] |
8cd81992 | 1697 | = ((recog_data.operand_type[i] != OP_OUT |
0ac516dc | 1698 | ? may_move_in_cost[mode][class][(int) classes[i]] |
8cd81992 | 1699 | : 0) |
1700 | + (recog_data.operand_type[i] != OP_IN | |
0ac516dc | 1701 | ? may_move_out_cost[mode][(int) classes[i]][class] |
8cd81992 | 1702 | : 0)); |
4023cea7 | 1703 | |
1704 | /* If the alternative actually allows memory, make things | |
1705 | a bit cheaper since we won't need an extra insn to | |
1706 | load it. */ | |
1707 | ||
155b05dc | 1708 | pp->mem_cost |
8cd81992 | 1709 | = ((recog_data.operand_type[i] != OP_IN |
1710 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1711 | : 0) | |
1712 | + (recog_data.operand_type[i] != OP_OUT | |
1713 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1714 | : 0) - allows_mem[i]); | |
4023cea7 | 1715 | |
1716 | /* If we have assigned a class to this register in our | |
1717 | first pass, add a cost to this alternative corresponding | |
1718 | to what we would add if this register were not in the | |
1719 | appropriate class. */ | |
1720 | ||
8ee7afab | 1721 | if (reg_pref && reg_pref[REGNO (op)].prefclass != NO_REGS) |
4023cea7 | 1722 | alt_cost |
0ac516dc | 1723 | += (may_move_in_cost[mode] |
1724 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
155b05dc | 1725 | [(int) classes[i]]); |
4023cea7 | 1726 | } |
8659a89f | 1727 | } |
ae09e9a3 | 1728 | |
4023cea7 | 1729 | /* Otherwise, if this alternative wins, either because we |
1730 | have already determined that or if we have a hard register of | |
1731 | the proper class, there is no cost for this alternative. */ | |
ae09e9a3 | 1732 | |
4023cea7 | 1733 | else if (win |
8ad4c111 | 1734 | || (REG_P (op) |
40c12d65 | 1735 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
4023cea7 | 1736 | ; |
ae09e9a3 | 1737 | |
4023cea7 | 1738 | /* If registers are valid, the cost of this alternative includes |
1739 | copying the object to and/or from a register. */ | |
ae09e9a3 | 1740 | |
4023cea7 | 1741 | else if (classes[i] != NO_REGS) |
1742 | { | |
ed420a25 | 1743 | if (recog_data.operand_type[i] != OP_OUT) |
4d58fa46 | 1744 | alt_cost += copy_cost (op, mode, classes[i], 1, NULL); |
ae09e9a3 | 1745 | |
ed420a25 | 1746 | if (recog_data.operand_type[i] != OP_IN) |
4d58fa46 | 1747 | alt_cost += copy_cost (op, mode, classes[i], 0, NULL); |
4023cea7 | 1748 | } |
ae09e9a3 | 1749 | |
4023cea7 | 1750 | /* The only other way this alternative can be used is if this is a |
1751 | constant that could be placed into memory. */ | |
1752 | ||
2cc205f8 | 1753 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) |
3afef759 | 1754 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
4023cea7 | 1755 | else |
1756 | alt_fail = 1; | |
1757 | } | |
1758 | ||
1759 | if (alt_fail) | |
1760 | continue; | |
1761 | ||
1762 | /* Finally, update the costs with the information we've calculated | |
1763 | about this alternative. */ | |
1764 | ||
1765 | for (i = 0; i < n_ops; i++) | |
8ad4c111 | 1766 | if (REG_P (ops[i]) |
4023cea7 | 1767 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) |
ae09e9a3 | 1768 | { |
4023cea7 | 1769 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
ed420a25 | 1770 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
ae09e9a3 | 1771 | |
4023cea7 | 1772 | pp->mem_cost = MIN (pp->mem_cost, |
1773 | (qq->mem_cost + alt_cost) * scale); | |
ae09e9a3 | 1774 | |
4023cea7 | 1775 | for (class = 0; class < N_REG_CLASSES; class++) |
1776 | pp->cost[class] = MIN (pp->cost[class], | |
1777 | (qq->cost[class] + alt_cost) * scale); | |
1778 | } | |
1779 | } | |
1f8d882f | 1780 | |
1781 | /* If this insn is a single set copying operand 1 to operand 0 | |
392f94ec | 1782 | and one operand is a pseudo with the other a hard reg or a pseudo |
1783 | that prefers a register that is in its own register class then | |
1784 | we may want to adjust the cost of that register class to -1. | |
2617fe26 | 1785 | |
392f94ec | 1786 | Avoid the adjustment if the source does not die to avoid stressing of |
917bbcab | 1787 | register allocator by preferrencing two colliding registers into single |
392f94ec | 1788 | class. |
1789 | ||
1790 | Also avoid the adjustment if a copy between registers of the class | |
1791 | is expensive (ten times the cost of a default copy is considered | |
1792 | arbitrarily expensive). This avoids losing when the preferred class | |
1793 | is very expensive as the source of a copy instruction. */ | |
1f8d882f | 1794 | |
1795 | if ((set = single_set (insn)) != 0 | |
1796 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
8ad4c111 | 1797 | && REG_P (ops[0]) && REG_P (ops[1]) |
ae150852 | 1798 | && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) |
1f8d882f | 1799 | for (i = 0; i <= 1; i++) |
1800 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1801 | { | |
02e7a332 | 1802 | unsigned int regno = REGNO (ops[!i]); |
1f8d882f | 1803 | enum machine_mode mode = GET_MODE (ops[!i]); |
1804 | int class; | |
1805 | ||
8ee7afab | 1806 | if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0 |
1807 | && reg_pref[regno].prefclass != NO_REGS) | |
392f94ec | 1808 | { |
1809 | enum reg_class pref = reg_pref[regno].prefclass; | |
1810 | ||
1811 | if ((reg_class_size[(unsigned char) pref] | |
bb37f971 | 1812 | == (unsigned) CLASS_MAX_NREGS (pref, mode)) |
0ac516dc | 1813 | && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) |
392f94ec | 1814 | op_costs[i].cost[(unsigned char) pref] = -1; |
1815 | } | |
1f8d882f | 1816 | else if (regno < FIRST_PSEUDO_REGISTER) |
1817 | for (class = 0; class < N_REG_CLASSES; class++) | |
1818 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
bb37f971 | 1819 | && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode)) |
2cff88c1 | 1820 | { |
1821 | if (reg_class_size[class] == 1) | |
1822 | op_costs[i].cost[class] = -1; | |
a2c6f0b7 | 1823 | else if (in_hard_reg_set_p (reg_class_contents[class], |
1824 | mode, regno)) | |
1825 | op_costs[i].cost[class] = -1; | |
2cff88c1 | 1826 | } |
1f8d882f | 1827 | } |
ae09e9a3 | 1828 | } |
4023cea7 | 1829 | \f |
7fd957fe | 1830 | /* Compute the cost of loading X into (if TO_P is nonzero) or from (if |
4023cea7 | 1831 | TO_P is zero) a register of class CLASS in mode MODE. |
1832 | ||
1833 | X must not be a pseudo. */ | |
1834 | ||
1835 | static int | |
4d58fa46 | 1836 | copy_cost (rtx x, enum machine_mode mode, enum reg_class class, int to_p, |
1837 | secondary_reload_info *prev_sri) | |
4023cea7 | 1838 | { |
1839 | enum reg_class secondary_class = NO_REGS; | |
4d58fa46 | 1840 | secondary_reload_info sri; |
4023cea7 | 1841 | |
1842 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1843 | assuming optimal allocation. */ | |
1844 | ||
1845 | if (GET_CODE (x) == SCRATCH) | |
1846 | return 0; | |
1847 | ||
1848 | /* Get the class we will actually use for a reload. */ | |
1849 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1850 | ||
4d58fa46 | 1851 | /* If we need a secondary reload for an intermediate, the |
4023cea7 | 1852 | cost is that to load the input into the intermediate register, then |
4d58fa46 | 1853 | to copy it. */ |
4023cea7 | 1854 | |
4d58fa46 | 1855 | sri.prev_sri = prev_sri; |
1856 | sri.extra_cost = 0; | |
1857 | secondary_class = targetm.secondary_reload (to_p, x, class, mode, &sri); | |
4023cea7 | 1858 | |
1859 | if (secondary_class != NO_REGS) | |
0ac516dc | 1860 | return (move_cost[mode][(int) secondary_class][(int) class] |
4d58fa46 | 1861 | + sri.extra_cost |
1862 | + copy_cost (x, mode, secondary_class, to_p, &sri)); | |
4023cea7 | 1863 | |
1864 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1865 | cost to move between the register classes, and use 2 for everything | |
1866 | else (constants). */ | |
1867 | ||
e16ceb8e | 1868 | if (MEM_P (x) || class == NO_REGS) |
4d58fa46 | 1869 | return sri.extra_cost + MEMORY_MOVE_COST (mode, class, to_p); |
ae09e9a3 | 1870 | |
8ad4c111 | 1871 | else if (REG_P (x)) |
4d58fa46 | 1872 | return (sri.extra_cost |
1873 | + move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]); | |
4023cea7 | 1874 | |
1875 | else | |
1876 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
4d58fa46 | 1877 | return sri.extra_cost + COSTS_N_INSNS (1); |
4023cea7 | 1878 | } |
1879 | \f | |
ae09e9a3 | 1880 | /* Record the pseudo registers we must reload into hard registers |
1881 | in a subexpression of a memory address, X. | |
4023cea7 | 1882 | |
00cb30dc | 1883 | If CONTEXT is 0, we are looking at the base part of an address, otherwise we |
1884 | are looking at the index part. | |
1885 | ||
1886 | MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE | |
1887 | give the context that the rtx appears in. These three arguments are | |
1888 | passed down to base_reg_class. | |
4023cea7 | 1889 | |
1890 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1891 | can represent half-cost adjustments). */ | |
ae09e9a3 | 1892 | |
ade5541e | 1893 | static void |
00cb30dc | 1894 | record_address_regs (enum machine_mode mode, rtx x, int context, |
1895 | enum rtx_code outer_code, enum rtx_code index_code, | |
1896 | int scale) | |
ae09e9a3 | 1897 | { |
19cb6b50 | 1898 | enum rtx_code code = GET_CODE (x); |
00cb30dc | 1899 | enum reg_class class; |
1900 | ||
1901 | if (context == 1) | |
1902 | class = INDEX_REG_CLASS; | |
1903 | else | |
1904 | class = base_reg_class (mode, outer_code, index_code); | |
ae09e9a3 | 1905 | |
1906 | switch (code) | |
1907 | { | |
1908 | case CONST_INT: | |
1909 | case CONST: | |
1910 | case CC0: | |
1911 | case PC: | |
1912 | case SYMBOL_REF: | |
1913 | case LABEL_REF: | |
1914 | return; | |
1915 | ||
1916 | case PLUS: | |
1917 | /* When we have an address that is a sum, | |
1918 | we must determine whether registers are "base" or "index" regs. | |
1919 | If there is a sum of two registers, we must choose one to be | |
e61a0a7f | 1920 | the "base". Luckily, we can use the REG_POINTER to make a good |
1921 | choice most of the time. We only need to do this on machines | |
1922 | that can have two registers in an address and where the base | |
1923 | and index register classes are different. | |
4023cea7 | 1924 | |
1925 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1926 | that seems bogus since it should only be set when we are sure | |
1927 | the register is being used as a pointer. */ | |
1928 | ||
ae09e9a3 | 1929 | { |
1930 | rtx arg0 = XEXP (x, 0); | |
1931 | rtx arg1 = XEXP (x, 1); | |
19cb6b50 | 1932 | enum rtx_code code0 = GET_CODE (arg0); |
1933 | enum rtx_code code1 = GET_CODE (arg1); | |
ae09e9a3 | 1934 | |
1935 | /* Look inside subregs. */ | |
4023cea7 | 1936 | if (code0 == SUBREG) |
ae09e9a3 | 1937 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
4023cea7 | 1938 | if (code1 == SUBREG) |
ae09e9a3 | 1939 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1940 | ||
4023cea7 | 1941 | /* If this machine only allows one register per address, it must |
1942 | be in the first operand. */ | |
1943 | ||
1944 | if (MAX_REGS_PER_ADDRESS == 1) | |
00cb30dc | 1945 | record_address_regs (mode, arg0, 0, PLUS, code1, scale); |
4023cea7 | 1946 | |
1947 | /* If index and base registers are the same on this machine, just | |
1948 | record registers in any non-constant operands. We assume here, | |
2617fe26 | 1949 | as well as in the tests below, that all addresses are in |
4023cea7 | 1950 | canonical form. */ |
1951 | ||
00cb30dc | 1952 | else if (INDEX_REG_CLASS == base_reg_class (VOIDmode, PLUS, SCRATCH)) |
ae09e9a3 | 1953 | { |
00cb30dc | 1954 | record_address_regs (mode, arg0, context, PLUS, code1, scale); |
4023cea7 | 1955 | if (! CONSTANT_P (arg1)) |
00cb30dc | 1956 | record_address_regs (mode, arg1, context, PLUS, code0, scale); |
ae09e9a3 | 1957 | } |
4023cea7 | 1958 | |
1959 | /* If the second operand is a constant integer, it doesn't change | |
1960 | what class the first operand must be. */ | |
1961 | ||
1962 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
00cb30dc | 1963 | record_address_regs (mode, arg0, context, PLUS, code1, scale); |
4023cea7 | 1964 | |
1965 | /* If the second operand is a symbolic constant, the first operand | |
1966 | must be an index register. */ | |
1967 | ||
1968 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
00cb30dc | 1969 | record_address_regs (mode, arg0, 1, PLUS, code1, scale); |
4023cea7 | 1970 | |
ad87de1e | 1971 | /* If both operands are registers but one is already a hard register |
6006f9fd | 1972 | of index or reg-base class, give the other the class that the |
1973 | hard register is not. */ | |
ad87de1e | 1974 | |
1975 | else if (code0 == REG && code1 == REG | |
1976 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
00cb30dc | 1977 | && (ok_for_base_p_nonstrict (arg0, mode, PLUS, REG) |
1978 | || ok_for_index_p_nonstrict (arg0))) | |
1979 | record_address_regs (mode, arg1, | |
1980 | ok_for_base_p_nonstrict (arg0, mode, PLUS, REG) | |
1981 | ? 1 : 0, | |
1982 | PLUS, REG, scale); | |
ad87de1e | 1983 | else if (code0 == REG && code1 == REG |
1984 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
00cb30dc | 1985 | && (ok_for_base_p_nonstrict (arg1, mode, PLUS, REG) |
1986 | || ok_for_index_p_nonstrict (arg1))) | |
1987 | record_address_regs (mode, arg0, | |
1988 | ok_for_base_p_nonstrict (arg1, mode, PLUS, REG) | |
1989 | ? 1 : 0, | |
1990 | PLUS, REG, scale); | |
ad87de1e | 1991 | |
0dbd1c74 | 1992 | /* If one operand is known to be a pointer, it must be the base |
1993 | with the other operand the index. Likewise if the other operand | |
1994 | is a MULT. */ | |
b0f6c01a | 1995 | |
e61a0a7f | 1996 | else if ((code0 == REG && REG_POINTER (arg0)) |
0dbd1c74 | 1997 | || code1 == MULT) |
b0f6c01a | 1998 | { |
00cb30dc | 1999 | record_address_regs (mode, arg0, 0, PLUS, code1, scale); |
2000 | record_address_regs (mode, arg1, 1, PLUS, code0, scale); | |
b0f6c01a | 2001 | } |
e61a0a7f | 2002 | else if ((code1 == REG && REG_POINTER (arg1)) |
0dbd1c74 | 2003 | || code0 == MULT) |
b0f6c01a | 2004 | { |
00cb30dc | 2005 | record_address_regs (mode, arg0, 1, PLUS, code1, scale); |
2006 | record_address_regs (mode, arg1, 0, PLUS, code0, scale); | |
b0f6c01a | 2007 | } |
2008 | ||
0dbd1c74 | 2009 | /* Otherwise, count equal chances that each might be a base |
4023cea7 | 2010 | or index register. This case should be rare. */ |
2011 | ||
0dbd1c74 | 2012 | else |
ae09e9a3 | 2013 | { |
00cb30dc | 2014 | record_address_regs (mode, arg0, 0, PLUS, code1, scale / 2); |
2015 | record_address_regs (mode, arg0, 1, PLUS, code1, scale / 2); | |
2016 | record_address_regs (mode, arg1, 0, PLUS, code0, scale / 2); | |
2017 | record_address_regs (mode, arg1, 1, PLUS, code0, scale / 2); | |
ae09e9a3 | 2018 | } |
ae09e9a3 | 2019 | } |
2020 | break; | |
2021 | ||
40988080 | 2022 | /* Double the importance of a pseudo register that is incremented |
2023 | or decremented, since it would take two extra insns | |
2024 | if it ends up in the wrong place. */ | |
2025 | case POST_MODIFY: | |
2026 | case PRE_MODIFY: | |
00cb30dc | 2027 | record_address_regs (mode, XEXP (x, 0), 0, code, |
2028 | GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale); | |
40988080 | 2029 | if (REG_P (XEXP (XEXP (x, 1), 1))) |
00cb30dc | 2030 | record_address_regs (mode, XEXP (XEXP (x, 1), 1), 1, code, REG, |
2031 | 2 * scale); | |
40988080 | 2032 | break; |
2033 | ||
ae09e9a3 | 2034 | case POST_INC: |
2035 | case PRE_INC: | |
2036 | case POST_DEC: | |
2037 | case PRE_DEC: | |
2038 | /* Double the importance of a pseudo register that is incremented | |
2039 | or decremented, since it would take two extra insns | |
3d46a046 | 2040 | if it ends up in the wrong place. If the operand is a pseudo, |
2041 | show it is being used in an INC_DEC context. */ | |
2042 | ||
2043 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
8ad4c111 | 2044 | if (REG_P (XEXP (x, 0)) |
3d46a046 | 2045 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) |
2046 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
2047 | #endif | |
4023cea7 | 2048 | |
00cb30dc | 2049 | record_address_regs (mode, XEXP (x, 0), 0, code, SCRATCH, 2 * scale); |
ae09e9a3 | 2050 | break; |
2051 | ||
2052 | case REG: | |
2053 | { | |
19cb6b50 | 2054 | struct costs *pp = &costs[REGNO (x)]; |
2055 | int i; | |
ae09e9a3 | 2056 | |
3afef759 | 2057 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
ae09e9a3 | 2058 | |
4023cea7 | 2059 | for (i = 0; i < N_REG_CLASSES; i++) |
0ac516dc | 2060 | pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; |
ae09e9a3 | 2061 | } |
2062 | break; | |
2063 | ||
2064 | default: | |
2065 | { | |
19cb6b50 | 2066 | const char *fmt = GET_RTX_FORMAT (code); |
2067 | int i; | |
ae09e9a3 | 2068 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2069 | if (fmt[i] == 'e') | |
00cb30dc | 2070 | record_address_regs (mode, XEXP (x, i), context, code, SCRATCH, |
2071 | scale); | |
ae09e9a3 | 2072 | } |
2073 | } | |
2074 | } | |
4ac7d2be | 2075 | \f |
2076 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2077 | ||
2078 | /* Return 1 if REG is valid as an auto-increment memory reference | |
2079 | to an object of MODE. */ | |
2080 | ||
99c14947 | 2081 | static int |
3ad4992f | 2082 | auto_inc_dec_reg_p (rtx reg, enum machine_mode mode) |
4ac7d2be | 2083 | { |
e4e498cf | 2084 | if (HAVE_POST_INCREMENT |
2085 | && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) | |
4ac7d2be | 2086 | return 1; |
4ac7d2be | 2087 | |
e4e498cf | 2088 | if (HAVE_POST_DECREMENT |
2089 | && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) | |
4ac7d2be | 2090 | return 1; |
4ac7d2be | 2091 | |
e4e498cf | 2092 | if (HAVE_PRE_INCREMENT |
2093 | && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) | |
4ac7d2be | 2094 | return 1; |
4ac7d2be | 2095 | |
e4e498cf | 2096 | if (HAVE_PRE_DECREMENT |
2097 | && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) | |
4ac7d2be | 2098 | return 1; |
4ac7d2be | 2099 | |
2100 | return 0; | |
2101 | } | |
2102 | #endif | |
394685a4 | 2103 | \f |
1e16645c | 2104 | /* Free up the space allocated by allocate_reg_info. */ |
2105 | void | |
3ad4992f | 2106 | free_reg_info (void) |
1e16645c | 2107 | { |
3072d30e | 2108 | if (reg_pref) |
1e16645c | 2109 | { |
3072d30e | 2110 | free (reg_pref); |
2111 | reg_pref = NULL; | |
2112 | } | |
1e16645c | 2113 | |
3072d30e | 2114 | if (reg_renumber) |
2115 | { | |
2116 | free (reg_renumber); | |
2117 | reg_renumber = NULL; | |
1e16645c | 2118 | } |
1e16645c | 2119 | } |
1a6a0f2a | 2120 | |
ae09e9a3 | 2121 | \f |
3072d30e | 2122 | /* This is the `regscan' pass of the compiler, run just before cse and |
2123 | again just before loop. It finds the first and last use of each | |
2124 | pseudo-register. */ | |
9a504a44 | 2125 | |
ae09e9a3 | 2126 | void |
3072d30e | 2127 | reg_scan (rtx f, unsigned int nregs ATTRIBUTE_UNUSED) |
ae09e9a3 | 2128 | { |
19cb6b50 | 2129 | rtx insn; |
ae09e9a3 | 2130 | |
a66cff91 | 2131 | timevar_push (TV_REG_SCAN); |
2132 | ||
ae09e9a3 | 2133 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
a66cff91 | 2134 | if (INSN_P (insn)) |
ae09e9a3 | 2135 | { |
3072d30e | 2136 | reg_scan_mark_refs (PATTERN (insn), insn); |
25105766 | 2137 | if (REG_NOTES (insn)) |
3072d30e | 2138 | reg_scan_mark_refs (REG_NOTES (insn), insn); |
e4525dfe | 2139 | } |
9a504a44 | 2140 | |
376c21d1 | 2141 | timevar_pop (TV_REG_SCAN); |
e4525dfe | 2142 | } |
2143 | ||
1a6a0f2a | 2144 | |
b1501a29 | 2145 | /* X is the expression to scan. INSN is the insn it appears in. |
1a6a0f2a | 2146 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. |
2147 | We should only record information for REGs with numbers | |
2148 | greater than or equal to MIN_REGNO. */ | |
b1501a29 | 2149 | |
3072d30e | 2150 | extern struct tree_opt_pass *current_pass; |
2151 | ||
4ac7d2be | 2152 | static void |
3072d30e | 2153 | reg_scan_mark_refs (rtx x, rtx insn) |
ae09e9a3 | 2154 | { |
19cb6b50 | 2155 | enum rtx_code code; |
2156 | rtx dest; | |
2157 | rtx note; | |
ae09e9a3 | 2158 | |
cb5c5698 | 2159 | if (!x) |
2160 | return; | |
7968c331 | 2161 | code = GET_CODE (x); |
ae09e9a3 | 2162 | switch (code) |
2163 | { | |
ae09e9a3 | 2164 | case CONST: |
2c776a54 | 2165 | case CONST_INT: |
ae09e9a3 | 2166 | case CONST_DOUBLE: |
886cfd4f | 2167 | case CONST_VECTOR: |
ae09e9a3 | 2168 | case CC0: |
2169 | case PC: | |
2170 | case SYMBOL_REF: | |
2171 | case LABEL_REF: | |
2172 | case ADDR_VEC: | |
2173 | case ADDR_DIFF_VEC: | |
ae09e9a3 | 2174 | case REG: |
3072d30e | 2175 | return; |
ae09e9a3 | 2176 | |
25105766 | 2177 | case EXPR_LIST: |
b4b9ba24 | 2178 | if (XEXP (x, 0)) |
3072d30e | 2179 | reg_scan_mark_refs (XEXP (x, 0), insn); |
25105766 | 2180 | if (XEXP (x, 1)) |
3072d30e | 2181 | reg_scan_mark_refs (XEXP (x, 1), insn); |
25105766 | 2182 | break; |
2183 | ||
2184 | case INSN_LIST: | |
2185 | if (XEXP (x, 1)) | |
3072d30e | 2186 | reg_scan_mark_refs (XEXP (x, 1), insn); |
25105766 | 2187 | break; |
2188 | ||
cb5c5698 | 2189 | case CLOBBER: |
3072d30e | 2190 | if (MEM_P (XEXP (x, 0))) |
2191 | reg_scan_mark_refs (XEXP (XEXP (x, 0), 0), insn); | |
cb5c5698 | 2192 | break; |
2193 | ||
ae09e9a3 | 2194 | case SET: |
2195 | /* Count a set of the destination if it is a register. */ | |
2196 | for (dest = SET_DEST (x); | |
2197 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2198 | || GET_CODE (dest) == ZERO_EXTEND; | |
2199 | dest = XEXP (dest, 0)) | |
2200 | ; | |
2201 | ||
bff0cb47 | 2202 | /* If this is setting a pseudo from another pseudo or the sum of a |
2203 | pseudo and a constant integer and the other pseudo is known to be | |
2204 | a pointer, set the destination to be a pointer as well. | |
2205 | ||
2206 | Likewise if it is setting the destination from an address or from a | |
2207 | value equivalent to an address or to the sum of an address and | |
2208 | something else. | |
2617fe26 | 2209 | |
bff0cb47 | 2210 | But don't do any of this if the pseudo corresponds to a user |
2211 | variable since it should have already been set as a pointer based | |
2212 | on the type. */ | |
2213 | ||
8ad4c111 | 2214 | if (REG_P (SET_DEST (x)) |
bff0cb47 | 2215 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER |
584afdda | 2216 | /* If the destination pseudo is set more than once, then other |
2217 | sets might not be to a pointer value (consider access to a | |
41a6f238 | 2218 | union in two threads of control in the presence of global |
e61a0a7f | 2219 | optimizations). So only set REG_POINTER on the destination |
584afdda | 2220 | pseudo if this is the only set of that pseudo. */ |
3072d30e | 2221 | && DF_REG_DEF_COUNT (REGNO (SET_DEST (x))) == 1 |
bff0cb47 | 2222 | && ! REG_USERVAR_P (SET_DEST (x)) |
e61a0a7f | 2223 | && ! REG_POINTER (SET_DEST (x)) |
8ad4c111 | 2224 | && ((REG_P (SET_SRC (x)) |
e61a0a7f | 2225 | && REG_POINTER (SET_SRC (x))) |
bff0cb47 | 2226 | || ((GET_CODE (SET_SRC (x)) == PLUS |
2227 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2228 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
8ad4c111 | 2229 | && REG_P (XEXP (SET_SRC (x), 0)) |
e61a0a7f | 2230 | && REG_POINTER (XEXP (SET_SRC (x), 0))) |
bff0cb47 | 2231 | || GET_CODE (SET_SRC (x)) == CONST |
2232 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2233 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2234 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2235 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2236 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2237 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2238 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2239 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2240 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2241 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2242 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2243 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2244 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2245 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2246 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
e61a0a7f | 2247 | REG_POINTER (SET_DEST (x)) = 1; |
bff0cb47 | 2248 | |
fcdc122e | 2249 | /* If this is setting a register from a register or from a simple |
ca74b940 | 2250 | conversion of a register, propagate REG_EXPR. */ |
3072d30e | 2251 | if (REG_P (dest) && !REG_ATTRS (dest)) |
fcdc122e | 2252 | { |
2253 | rtx src = SET_SRC (x); | |
2254 | ||
2255 | while (GET_CODE (src) == SIGN_EXTEND | |
2256 | || GET_CODE (src) == ZERO_EXTEND | |
2257 | || GET_CODE (src) == TRUNCATE | |
2258 | || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))) | |
2259 | src = XEXP (src, 0); | |
2260 | ||
3072d30e | 2261 | if (REG_P (src)) |
ca74b940 | 2262 | REG_ATTRS (dest) = REG_ATTRS (src); |
3072d30e | 2263 | if (MEM_P (src)) |
ca74b940 | 2264 | set_reg_attrs_from_mem (dest, src); |
fcdc122e | 2265 | } |
2266 | ||
a92771b8 | 2267 | /* ... fall through ... */ |
ae09e9a3 | 2268 | |
2269 | default: | |
2270 | { | |
19cb6b50 | 2271 | const char *fmt = GET_RTX_FORMAT (code); |
2272 | int i; | |
ae09e9a3 | 2273 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2274 | { | |
2275 | if (fmt[i] == 'e') | |
3072d30e | 2276 | reg_scan_mark_refs (XEXP (x, i), insn); |
ae09e9a3 | 2277 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2278 | { | |
19cb6b50 | 2279 | int j; |
ae09e9a3 | 2280 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
3072d30e | 2281 | reg_scan_mark_refs (XVECEXP (x, i, j), insn); |
ae09e9a3 | 2282 | } |
2283 | } | |
2284 | } | |
2285 | } | |
2286 | } | |
2287 | \f | |
2288 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2289 | is also in C2. */ | |
2290 | ||
2291 | int | |
3ad4992f | 2292 | reg_class_subset_p (enum reg_class c1, enum reg_class c2) |
ae09e9a3 | 2293 | { |
ddc556d1 | 2294 | return (c1 == c2 |
2295 | || c2 == ALL_REGS | |
2296 | || hard_reg_set_subset_p (reg_class_contents[(int) c1], | |
2297 | reg_class_contents[(int) c2])); | |
ae09e9a3 | 2298 | } |
2299 | ||
2300 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2301 | ||
2302 | int | |
3ad4992f | 2303 | reg_classes_intersect_p (enum reg_class c1, enum reg_class c2) |
ae09e9a3 | 2304 | { |
ddc556d1 | 2305 | return (c1 == c2 |
2306 | || c1 == ALL_REGS | |
2307 | || c2 == ALL_REGS | |
2308 | || hard_reg_set_intersect_p (reg_class_contents[(int) c1], | |
2309 | reg_class_contents[(int) c2])); | |
ae09e9a3 | 2310 | } |
2311 | ||
897118e8 | 2312 | #ifdef CANNOT_CHANGE_MODE_CLASS |
3dc77328 | 2313 | |
2314 | struct subregs_of_mode_node | |
2315 | { | |
2316 | unsigned int block; | |
2317 | unsigned char modes[MAX_MACHINE_MODE]; | |
2318 | }; | |
2319 | ||
2320 | static htab_t subregs_of_mode; | |
2321 | ||
2322 | static hashval_t | |
2323 | som_hash (const void *x) | |
2324 | { | |
2325 | const struct subregs_of_mode_node *a = x; | |
2326 | return a->block; | |
2327 | } | |
2328 | ||
2329 | static int | |
2330 | som_eq (const void *x, const void *y) | |
2331 | { | |
2332 | const struct subregs_of_mode_node *a = x; | |
2333 | const struct subregs_of_mode_node *b = y; | |
2334 | return a->block == b->block; | |
2335 | } | |
2336 | ||
3dc77328 | 2337 | |
3072d30e | 2338 | static void |
3dc77328 | 2339 | record_subregs_of_mode (rtx subreg) |
2340 | { | |
2341 | struct subregs_of_mode_node dummy, *node; | |
2342 | enum machine_mode mode; | |
2343 | unsigned int regno; | |
2344 | void **slot; | |
2345 | ||
2346 | if (!REG_P (SUBREG_REG (subreg))) | |
2347 | return; | |
2348 | ||
2349 | regno = REGNO (SUBREG_REG (subreg)); | |
2350 | mode = GET_MODE (subreg); | |
2351 | ||
2352 | if (regno < FIRST_PSEUDO_REGISTER) | |
2353 | return; | |
2354 | ||
2355 | dummy.block = regno & -8; | |
2356 | slot = htab_find_slot_with_hash (subregs_of_mode, &dummy, | |
2357 | dummy.block, INSERT); | |
2358 | node = *slot; | |
2359 | if (node == NULL) | |
2360 | { | |
4c36ffe6 | 2361 | node = XCNEW (struct subregs_of_mode_node); |
3dc77328 | 2362 | node->block = regno & -8; |
2363 | *slot = node; | |
2364 | } | |
2365 | ||
2366 | node->modes[mode] |= 1 << (regno & 7); | |
2367 | } | |
2368 | ||
3072d30e | 2369 | |
2370 | /* Call record_subregs_of_mode for all the subregs in X. */ | |
2371 | ||
2372 | static void | |
2373 | find_subregs_of_mode (rtx x) | |
2374 | { | |
2375 | enum rtx_code code = GET_CODE (x); | |
2376 | const char * const fmt = GET_RTX_FORMAT (code); | |
2377 | int i; | |
2378 | ||
2379 | if (code == SUBREG) | |
2380 | record_subregs_of_mode (x); | |
2381 | ||
2382 | /* Time for some deep diving. */ | |
2383 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2384 | { | |
2385 | if (fmt[i] == 'e') | |
2386 | find_subregs_of_mode (XEXP (x, i)); | |
2387 | else if (fmt[i] == 'E') | |
2388 | { | |
2389 | int j; | |
2390 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2391 | find_subregs_of_mode (XVECEXP (x, i, j)); | |
2392 | } | |
2393 | } | |
2394 | } | |
2395 | ||
2396 | static unsigned int | |
2397 | init_subregs_of_mode (void) | |
2398 | { | |
2399 | basic_block bb; | |
2400 | rtx insn; | |
2401 | ||
2402 | if (subregs_of_mode) | |
2403 | htab_empty (subregs_of_mode); | |
2404 | else | |
2405 | subregs_of_mode = htab_create (100, som_hash, som_eq, free); | |
2406 | ||
2407 | FOR_EACH_BB (bb) | |
2408 | FOR_BB_INSNS (bb, insn) | |
2409 | if (INSN_P (insn)) | |
2410 | find_subregs_of_mode (PATTERN (insn)); | |
2411 | ||
2412 | return 0; | |
2413 | } | |
2414 | ||
2415 | ||
897118e8 | 2416 | /* Set bits in *USED which correspond to registers which can't change |
2417 | their mode from FROM to any mode in which REGNO was encountered. */ | |
2418 | ||
2419 | void | |
3ad4992f | 2420 | cannot_change_mode_set_regs (HARD_REG_SET *used, enum machine_mode from, |
2421 | unsigned int regno) | |
897118e8 | 2422 | { |
3dc77328 | 2423 | struct subregs_of_mode_node dummy, *node; |
897118e8 | 2424 | enum machine_mode to; |
3dc77328 | 2425 | unsigned char mask; |
2426 | unsigned int i; | |
897118e8 | 2427 | |
3072d30e | 2428 | gcc_assert (subregs_of_mode); |
3dc77328 | 2429 | dummy.block = regno & -8; |
2430 | node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block); | |
2431 | if (node == NULL) | |
2432 | return; | |
2433 | ||
2434 | mask = 1 << (regno & 7); | |
2435 | for (to = VOIDmode; to < NUM_MACHINE_MODES; to++) | |
2436 | if (node->modes[to] & mask) | |
2437 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2438 | if (!TEST_HARD_REG_BIT (*used, i) | |
2439 | && REG_CANNOT_CHANGE_MODE_P (i, from, to)) | |
2440 | SET_HARD_REG_BIT (*used, i); | |
897118e8 | 2441 | } |
2442 | ||
2443 | /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM | |
2444 | mode. */ | |
2445 | ||
2446 | bool | |
3ad4992f | 2447 | invalid_mode_change_p (unsigned int regno, enum reg_class class, |
3dc77328 | 2448 | enum machine_mode from) |
897118e8 | 2449 | { |
3dc77328 | 2450 | struct subregs_of_mode_node dummy, *node; |
2451 | enum machine_mode to; | |
2452 | unsigned char mask; | |
2453 | ||
3072d30e | 2454 | gcc_assert (subregs_of_mode); |
3dc77328 | 2455 | dummy.block = regno & -8; |
2456 | node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block); | |
2457 | if (node == NULL) | |
2458 | return false; | |
2459 | ||
2460 | mask = 1 << (regno & 7); | |
2461 | for (to = VOIDmode; to < NUM_MACHINE_MODES; to++) | |
2462 | if (node->modes[to] & mask) | |
2463 | if (CANNOT_CHANGE_MODE_CLASS (from, to, class)) | |
2464 | return true; | |
2465 | ||
2466 | return false; | |
897118e8 | 2467 | } |
3072d30e | 2468 | |
2469 | static unsigned int | |
2470 | finish_subregs_of_mode (void) | |
2471 | { | |
2472 | htab_delete (subregs_of_mode); | |
2473 | subregs_of_mode = 0; | |
2474 | return 0; | |
2475 | } | |
2476 | #else | |
2477 | static unsigned int | |
2478 | init_subregs_of_mode (void) | |
2479 | { | |
2480 | return 0; | |
2481 | } | |
2482 | static unsigned int | |
2483 | finish_subregs_of_mode (void) | |
2484 | { | |
2485 | return 0; | |
2486 | } | |
2487 | ||
897118e8 | 2488 | #endif /* CANNOT_CHANGE_MODE_CLASS */ |
2489 | ||
3072d30e | 2490 | static bool |
2491 | gate_subregs_of_mode_init (void) | |
2492 | { | |
2493 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
2494 | return true; | |
2495 | #else | |
2496 | return false; | |
2497 | #endif | |
2498 | } | |
2499 | ||
2500 | struct tree_opt_pass pass_subregs_of_mode_init = | |
2501 | { | |
2502 | "subregs_of_mode_init", /* name */ | |
2503 | gate_subregs_of_mode_init, /* gate */ | |
2504 | init_subregs_of_mode, /* execute */ | |
2505 | NULL, /* sub */ | |
2506 | NULL, /* next */ | |
2507 | 0, /* static_pass_number */ | |
2508 | 0, /* tv_id */ | |
2509 | 0, /* properties_required */ | |
2510 | 0, /* properties_provided */ | |
2511 | 0, /* properties_destroyed */ | |
2512 | 0, /* todo_flags_start */ | |
2513 | 0, /* todo_flags_finish */ | |
2514 | 0 /* letter */ | |
2515 | }; | |
2516 | ||
2517 | struct tree_opt_pass pass_subregs_of_mode_finish = | |
2518 | { | |
2519 | "subregs_of_mode_finish", /* name */ | |
2520 | gate_subregs_of_mode_init, /* gate */ | |
2521 | finish_subregs_of_mode, /* execute */ | |
2522 | NULL, /* sub */ | |
2523 | NULL, /* next */ | |
2524 | 0, /* static_pass_number */ | |
2525 | 0, /* tv_id */ | |
2526 | 0, /* properties_required */ | |
2527 | 0, /* properties_provided */ | |
2528 | 0, /* properties_destroyed */ | |
2529 | 0, /* todo_flags_start */ | |
2530 | 0, /* todo_flags_finish */ | |
2531 | 0 /* letter */ | |
2532 | }; | |
2533 | ||
2534 | ||
2535 | ||
1f3233d1 | 2536 | #include "gt-regclass.h" |