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ae09e9a3 | 1 | /* Compute register class preferences for pseudo-registers. |
0b387d23 | 2 | Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 |
ada8adad | 3 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
0364c2b4 | 4 | Free Software Foundation, Inc. |
ae09e9a3 | 5 | |
f12b58b3 | 6 | This file is part of GCC. |
ae09e9a3 | 7 | |
f12b58b3 | 8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 2, or (at your option) any later | |
11 | version. | |
ae09e9a3 | 12 | |
f12b58b3 | 13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
ae09e9a3 | 17 | |
18 | You should have received a copy of the GNU General Public License | |
f12b58b3 | 19 | along with GCC; see the file COPYING. If not, write to the Free |
67ce556b | 20 | Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
ae09e9a3 | 22 | |
23 | ||
24 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
25 | It also defines some tables of information about the hardware registers | |
26 | and a function init_reg_sets to initialize the tables. */ | |
27 | ||
28 | #include "config.h" | |
405711de | 29 | #include "system.h" |
805e22b2 | 30 | #include "coretypes.h" |
31 | #include "tm.h" | |
897118e8 | 32 | #include "hard-reg-set.h" |
ae09e9a3 | 33 | #include "rtl.h" |
ee0548e9 | 34 | #include "expr.h" |
7953c610 | 35 | #include "tm_p.h" |
ae09e9a3 | 36 | #include "flags.h" |
37 | #include "basic-block.h" | |
38 | #include "regs.h" | |
0a893c29 | 39 | #include "function.h" |
ae09e9a3 | 40 | #include "insn-config.h" |
41 | #include "recog.h" | |
4023cea7 | 42 | #include "reload.h" |
43 | #include "real.h" | |
12874aaf | 44 | #include "toplev.h" |
cd03a192 | 45 | #include "output.h" |
0dddbcb3 | 46 | #include "ggc.h" |
376c21d1 | 47 | #include "timevar.h" |
3dc77328 | 48 | #include "hashtab.h" |
4d58fa46 | 49 | #include "target.h" |
ae09e9a3 | 50 | |
3ad4992f | 51 | static void init_reg_sets_1 (void); |
3ad4992f | 52 | static void init_reg_autoinc (void); |
18525f1f | 53 | |
3d46a046 | 54 | /* If we have auto-increment or auto-decrement and we can have secondary |
55 | reloads, we are not allowed to use classes requiring secondary | |
c3418f42 | 56 | reloads for pseudos auto-incremented since reload can't handle it. */ |
4d58fa46 | 57 | /* We leave it to target hooks to decide if we have secondary reloads, so |
58 | assume that we might have them. */ | |
59 | #if defined(AUTO_INC_DEC) /* */ | |
3d46a046 | 60 | #define FORBIDDEN_INC_DEC_CLASSES |
61 | #endif | |
ae09e9a3 | 62 | \f |
63 | /* Register tables used by many passes. */ | |
64 | ||
65 | /* Indexed by hard register number, contains 1 for registers | |
66 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
67 | These are the registers that cannot be used to allocate | |
fc242db3 | 68 | a pseudo reg for general use. */ |
ae09e9a3 | 69 | |
70 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
71 | ||
72 | /* Same info as a HARD_REG_SET. */ | |
73 | ||
74 | HARD_REG_SET fixed_reg_set; | |
75 | ||
76 | /* Data for initializing the above. */ | |
77 | ||
e99c3a1d | 78 | static const char initial_fixed_regs[] = FIXED_REGISTERS; |
ae09e9a3 | 79 | |
80 | /* Indexed by hard register number, contains 1 for registers | |
81 | that are fixed use or are clobbered by function calls. | |
82 | These are the registers that cannot be used to allocate | |
fc242db3 | 83 | a pseudo reg whose life crosses calls unless we are able |
84 | to save/restore them across the calls. */ | |
ae09e9a3 | 85 | |
86 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
87 | ||
88 | /* Same info as a HARD_REG_SET. */ | |
89 | ||
90 | HARD_REG_SET call_used_reg_set; | |
91 | ||
2836f006 | 92 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
93 | HARD_REG_SET losing_caller_save_reg_set; | |
94 | ||
ae09e9a3 | 95 | /* Data for initializing the above. */ |
96 | ||
e99c3a1d | 97 | static const char initial_call_used_regs[] = CALL_USED_REGISTERS; |
d2d242b4 | 98 | |
99 | /* This is much like call_used_regs, except it doesn't have to | |
100 | be a superset of FIXED_REGISTERS. This vector indicates | |
2617fe26 | 101 | what is really call clobbered, and is used when defining |
d2d242b4 | 102 | regs_invalidated_by_call. */ |
103 | ||
d2d242b4 | 104 | #ifdef CALL_REALLY_USED_REGISTERS |
556ba85f | 105 | char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; |
d2d242b4 | 106 | #endif |
2617fe26 | 107 | |
1fbc37ff | 108 | #ifdef CALL_REALLY_USED_REGISTERS |
109 | #define CALL_REALLY_USED_REGNO_P(X) call_really_used_regs[X] | |
110 | #else | |
111 | #define CALL_REALLY_USED_REGNO_P(X) call_used_regs[X] | |
112 | #endif | |
113 | ||
114 | ||
ae09e9a3 | 115 | /* Indexed by hard register number, contains 1 for registers that are |
fc242db3 | 116 | fixed use or call used registers that cannot hold quantities across |
117 | calls even if we are willing to save and restore them. call fixed | |
118 | registers are a subset of call used registers. */ | |
ae09e9a3 | 119 | |
120 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
121 | ||
122 | /* The same info as a HARD_REG_SET. */ | |
123 | ||
124 | HARD_REG_SET call_fixed_reg_set; | |
125 | ||
126 | /* Number of non-fixed registers. */ | |
127 | ||
128 | int n_non_fixed_regs; | |
129 | ||
130 | /* Indexed by hard register number, contains 1 for registers | |
131 | that are being used for global register decls. | |
132 | These must be exempt from ordinary flow analysis | |
133 | and are also considered fixed. */ | |
134 | ||
135 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
546edcaa | 136 | |
137 | /* Contains 1 for registers that are set or clobbered by calls. */ | |
138 | /* ??? Ideally, this would be just call_used_regs plus global_regs, but | |
139 | for someone's bright idea to have call_used_regs strictly include | |
140 | fixed_regs. Which leaves us guessing as to the set of fixed_regs | |
141 | that are actually preserved. We know for sure that those associated | |
142 | with the local stack frame are safe, but scant others. */ | |
143 | ||
144 | HARD_REG_SET regs_invalidated_by_call; | |
145 | ||
ae09e9a3 | 146 | /* Table of register numbers in the order in which to try to use them. */ |
147 | #ifdef REG_ALLOC_ORDER | |
148 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
fbf51e51 | 149 | |
150 | /* The inverse of reg_alloc_order. */ | |
151 | int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; | |
ae09e9a3 | 152 | #endif |
153 | ||
154 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
155 | ||
0aab1048 | 156 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
157 | ||
545740b7 | 158 | /* The same information, but as an array of unsigned ints. We copy from |
159 | these unsigned ints to the table above. We do this so the tm.h files | |
fad8575f | 160 | do not have to be aware of the wordsize for machines with <= 64 regs. |
161 | Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ | |
0aab1048 | 162 | |
163 | #define N_REG_INTS \ | |
fad8575f | 164 | ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) |
0aab1048 | 165 | |
2617fe26 | 166 | static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
0aab1048 | 167 | = REG_CLASS_CONTENTS; |
ae09e9a3 | 168 | |
169 | /* For each reg class, number of regs it contains. */ | |
170 | ||
02e7a332 | 171 | unsigned int reg_class_size[N_REG_CLASSES]; |
ae09e9a3 | 172 | |
173 | /* For each reg class, table listing all the containing classes. */ | |
174 | ||
a792c500 | 175 | static enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; |
ae09e9a3 | 176 | |
177 | /* For each reg class, table listing all the classes contained in it. */ | |
178 | ||
a792c500 | 179 | static enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; |
ae09e9a3 | 180 | |
181 | /* For each pair of reg classes, | |
182 | a largest reg class contained in their union. */ | |
183 | ||
184 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
185 | ||
186 | /* For each pair of reg classes, | |
187 | the smallest reg class containing their union. */ | |
188 | ||
189 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
190 | ||
15460c97 | 191 | /* Array containing all of the register names. */ |
6fe96dec | 192 | |
da0930ba | 193 | const char * reg_names[] = REGISTER_NAMES; |
6fe96dec | 194 | |
ada8adad | 195 | /* Array containing all of the register class names. */ |
196 | ||
197 | const char * reg_class_names[] = REG_CLASS_NAMES; | |
198 | ||
d2b04fb8 | 199 | /* For each hard register, the widest mode object that it can contain. |
200 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
201 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
202 | register. */ | |
203 | ||
204 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
205 | ||
83e2a11b | 206 | /* 1 if there is a register of given mode. */ |
207 | ||
208 | bool have_regs_of_mode [MAX_MACHINE_MODE]; | |
209 | ||
0279c35a | 210 | /* 1 if class does contain register of given mode. */ |
211 | ||
212 | static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; | |
213 | ||
4023cea7 | 214 | /* Maximum cost of moving from a register in one class to a register in |
215 | another class. Based on REGISTER_MOVE_COST. */ | |
216 | ||
0ac516dc | 217 | static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
4023cea7 | 218 | |
219 | /* Similar, but here we don't have to move if the first index is a subset | |
220 | of the second so in that case the cost is zero. */ | |
221 | ||
0ac516dc | 222 | static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
f5a540b9 | 223 | |
224 | /* Similar, but here we don't have to move if the first index is a superset | |
225 | of the second so in that case the cost is zero. */ | |
226 | ||
0ac516dc | 227 | static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; |
4023cea7 | 228 | |
3d46a046 | 229 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
230 | ||
231 | /* These are the classes that regs which are auto-incremented or decremented | |
232 | cannot be put in. */ | |
233 | ||
234 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
235 | ||
7fd957fe | 236 | /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec |
3d46a046 | 237 | context. */ |
238 | ||
239 | static char *in_inc_dec; | |
240 | ||
313fe4bc | 241 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
3d46a046 | 242 | |
4c685015 | 243 | /* Sample MEM values for use by memory_move_secondary_cost. */ |
244 | ||
1f3233d1 | 245 | static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE]; |
4c685015 | 246 | |
d6ff8d83 | 247 | /* Linked list of reg_info structures allocated for reg_n_info array. |
248 | Grouping all of the allocated structures together in one lump | |
249 | means only one call to bzero to clear them, rather than n smaller | |
250 | calls. */ | |
251 | struct reg_info_data { | |
252 | struct reg_info_data *next; /* next set of reg_info structures */ | |
253 | size_t min_index; /* minimum index # */ | |
254 | size_t max_index; /* maximum index # */ | |
7fd957fe | 255 | char used_p; /* nonzero if this has been used previously */ |
d6ff8d83 | 256 | reg_info data[1]; /* beginning of the reg_info data */ |
257 | }; | |
258 | ||
259 | static struct reg_info_data *reg_info_head; | |
260 | ||
7d0e67ac | 261 | /* No more global register variables may be declared; true once |
aa40f561 | 262 | regclass has been initialized. */ |
f18e6699 | 263 | |
264 | static int no_global_reg_vars = 0; | |
265 | ||
67d6c12b | 266 | /* Specify number of hard registers given machine mode occupy. */ |
267 | unsigned char hard_regno_nregs[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE]; | |
d6ff8d83 | 268 | |
ae09e9a3 | 269 | /* Function called only once to initialize the above data on reg usage. |
270 | Once this is done, various switches may override. */ | |
271 | ||
272 | void | |
3ad4992f | 273 | init_reg_sets (void) |
ae09e9a3 | 274 | { |
19cb6b50 | 275 | int i, j; |
ae09e9a3 | 276 | |
0aab1048 | 277 | /* First copy the register information from the initial int form into |
278 | the regsets. */ | |
279 | ||
280 | for (i = 0; i < N_REG_CLASSES; i++) | |
281 | { | |
282 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
283 | ||
81fa5697 | 284 | /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ |
0aab1048 | 285 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
81fa5697 | 286 | if (int_reg_class_contents[i][j / 32] |
287 | & ((unsigned) 1 << (j % 32))) | |
0aab1048 | 288 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
289 | } | |
290 | ||
2fd48995 | 291 | /* Sanity check: make sure the target macros FIXED_REGISTERS and |
292 | CALL_USED_REGISTERS had the right number of initializers. */ | |
04e579b6 | 293 | gcc_assert (sizeof fixed_regs == sizeof initial_fixed_regs); |
294 | gcc_assert (sizeof call_used_regs == sizeof initial_call_used_regs); | |
2fd48995 | 295 | |
b1b63592 | 296 | memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); |
297 | memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); | |
93d3b7de | 298 | memset (global_regs, 0, sizeof global_regs); |
ae09e9a3 | 299 | |
fbf51e51 | 300 | #ifdef REG_ALLOC_ORDER |
301 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
302 | inv_reg_alloc_order[reg_alloc_order[i]] = i; | |
303 | #endif | |
3b28508a | 304 | } |
305 | ||
306 | /* After switches have been processed, which perhaps alter | |
307 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
308 | ||
309 | static void | |
3ad4992f | 310 | init_reg_sets_1 (void) |
3b28508a | 311 | { |
19cb6b50 | 312 | unsigned int i, j; |
313 | unsigned int /* enum machine_mode */ m; | |
3b28508a | 314 | |
315 | /* This macro allows the fixed or call-used registers | |
316 | and the register classes to depend on target flags. */ | |
317 | ||
318 | #ifdef CONDITIONAL_REGISTER_USAGE | |
319 | CONDITIONAL_REGISTER_USAGE; | |
320 | #endif | |
321 | ||
ae09e9a3 | 322 | /* Compute number of hard regs in each class. */ |
323 | ||
f0af5a88 | 324 | memset (reg_class_size, 0, sizeof reg_class_size); |
ae09e9a3 | 325 | for (i = 0; i < N_REG_CLASSES; i++) |
326 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
327 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
328 | reg_class_size[i]++; | |
329 | ||
330 | /* Initialize the table of subunions. | |
331 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
332 | that is contained in the union of classes I and J. */ | |
333 | ||
334 | for (i = 0; i < N_REG_CLASSES; i++) | |
335 | { | |
336 | for (j = 0; j < N_REG_CLASSES; j++) | |
337 | { | |
a00f8533 | 338 | HARD_REG_SET c; |
19cb6b50 | 339 | int k; |
ae09e9a3 | 340 | |
341 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
342 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
343 | for (k = 0; k < N_REG_CLASSES; k++) | |
344 | { | |
345 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
346 | subclass1); | |
347 | continue; | |
348 | ||
349 | subclass1: | |
b4b174c3 | 350 | /* Keep the largest subclass. */ /* SPEE 900308 */ |
ae09e9a3 | 351 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], |
352 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
353 | subclass2); | |
354 | reg_class_subunion[i][j] = (enum reg_class) k; | |
355 | subclass2: | |
356 | ; | |
357 | } | |
358 | } | |
359 | } | |
360 | ||
361 | /* Initialize the table of superunions. | |
362 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
363 | containing the union of classes I and J. */ | |
364 | ||
365 | for (i = 0; i < N_REG_CLASSES; i++) | |
366 | { | |
367 | for (j = 0; j < N_REG_CLASSES; j++) | |
368 | { | |
a00f8533 | 369 | HARD_REG_SET c; |
19cb6b50 | 370 | int k; |
ae09e9a3 | 371 | |
372 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
373 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
374 | for (k = 0; k < N_REG_CLASSES; k++) | |
375 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
376 | ||
377 | superclass: | |
378 | reg_class_superunion[i][j] = (enum reg_class) k; | |
379 | } | |
380 | } | |
381 | ||
382 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
383 | First clear the whole table, then add the elements as they are found. */ | |
384 | ||
385 | for (i = 0; i < N_REG_CLASSES; i++) | |
386 | { | |
387 | for (j = 0; j < N_REG_CLASSES; j++) | |
388 | { | |
389 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
390 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
391 | } | |
392 | } | |
393 | ||
394 | for (i = 0; i < N_REG_CLASSES; i++) | |
395 | { | |
396 | if (i == (int) NO_REGS) | |
397 | continue; | |
398 | ||
399 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
400 | { | |
401 | enum reg_class *p; | |
402 | ||
403 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
404 | subclass); | |
405 | continue; | |
406 | subclass: | |
407 | /* Reg class I is a subclass of J. | |
408 | Add J to the table of superclasses of I. */ | |
409 | p = ®_class_superclasses[i][0]; | |
410 | while (*p != LIM_REG_CLASSES) p++; | |
411 | *p = (enum reg_class) j; | |
412 | /* Add I to the table of superclasses of J. */ | |
413 | p = ®_class_subclasses[j][0]; | |
414 | while (*p != LIM_REG_CLASSES) p++; | |
415 | *p = (enum reg_class) i; | |
416 | } | |
417 | } | |
4023cea7 | 418 | |
ae09e9a3 | 419 | /* Initialize "constant" tables. */ |
420 | ||
421 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
422 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
423 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
546edcaa | 424 | CLEAR_HARD_REG_SET (regs_invalidated_by_call); |
ae09e9a3 | 425 | |
b1b63592 | 426 | memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); |
ae09e9a3 | 427 | |
428 | n_non_fixed_regs = 0; | |
429 | ||
430 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
431 | { | |
579bc712 | 432 | /* call_used_regs must include fixed_regs. */ |
04e579b6 | 433 | gcc_assert (!fixed_regs[i] || call_used_regs[i]); |
579bc712 | 434 | #ifdef CALL_REALLY_USED_REGISTERS |
435 | /* call_used_regs must include call_really_used_regs. */ | |
04e579b6 | 436 | gcc_assert (!call_really_used_regs[i] || call_used_regs[i]); |
579bc712 | 437 | #endif |
438 | ||
ae09e9a3 | 439 | if (fixed_regs[i]) |
440 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
441 | else | |
442 | n_non_fixed_regs++; | |
443 | ||
444 | if (call_used_regs[i]) | |
445 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
446 | if (call_fixed_regs[i]) | |
447 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
2836f006 | 448 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
449 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
546edcaa | 450 | |
451 | /* There are a couple of fixed registers that we know are safe to | |
452 | exclude from being clobbered by calls: | |
453 | ||
454 | The frame pointer is always preserved across calls. The arg pointer | |
455 | is if it is fixed. The stack pointer usually is, unless | |
456 | RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. | |
457 | If we are generating PIC code, the PIC offset table register is | |
458 | preserved across calls, though the target can override that. */ | |
2617fe26 | 459 | |
1fbc37ff | 460 | if (i == STACK_POINTER_REGNUM) |
461 | ; | |
462 | else if (global_regs[i]) | |
463 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); | |
464 | else if (i == FRAME_POINTER_REGNUM) | |
546edcaa | 465 | ; |
466 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
467 | else if (i == HARD_FRAME_POINTER_REGNUM) | |
468 | ; | |
469 | #endif | |
470 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
471 | else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) | |
472 | ; | |
473 | #endif | |
474 | #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED | |
3473aefe | 475 | else if (i == (unsigned) PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) |
546edcaa | 476 | ; |
477 | #endif | |
1fbc37ff | 478 | else if (CALL_REALLY_USED_REGNO_P (i)) |
546edcaa | 479 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); |
ae09e9a3 | 480 | } |
546edcaa | 481 | |
83e2a11b | 482 | memset (have_regs_of_mode, 0, sizeof (have_regs_of_mode)); |
cc693d06 | 483 | memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); |
0fd4500a | 484 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
cc693d06 | 485 | for (i = 0; i < N_REG_CLASSES; i++) |
bb37f971 | 486 | if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) |
0279c35a | 487 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
488 | if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) | |
489 | && HARD_REGNO_MODE_OK (j, m)) | |
490 | { | |
491 | contains_reg_of_mode [i][m] = 1; | |
83e2a11b | 492 | have_regs_of_mode [m] = 1; |
0279c35a | 493 | break; |
494 | } | |
b110f7ec | 495 | |
496 | /* Initialize the move cost table. Find every subset of each class | |
497 | and take the maximum cost of moving any subset to any other. */ | |
498 | ||
0fd4500a | 499 | for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) |
83e2a11b | 500 | if (have_regs_of_mode [m]) |
cc693d06 | 501 | { |
502 | for (i = 0; i < N_REG_CLASSES; i++) | |
503 | if (contains_reg_of_mode [i][m]) | |
504 | for (j = 0; j < N_REG_CLASSES; j++) | |
505 | { | |
506 | int cost; | |
507 | enum reg_class *p1, *p2; | |
508 | ||
509 | if (!contains_reg_of_mode [j][m]) | |
510 | { | |
511 | move_cost[m][i][j] = 65536; | |
512 | may_move_in_cost[m][i][j] = 65536; | |
513 | may_move_out_cost[m][i][j] = 65536; | |
514 | } | |
515 | else | |
516 | { | |
bb1892a6 | 517 | cost = REGISTER_MOVE_COST (m, i, j); |
cc693d06 | 518 | |
519 | for (p2 = ®_class_subclasses[j][0]; | |
520 | *p2 != LIM_REG_CLASSES; | |
521 | p2++) | |
522 | if (*p2 != i && contains_reg_of_mode [*p2][m]) | |
523 | cost = MAX (cost, move_cost [m][i][*p2]); | |
524 | ||
525 | for (p1 = ®_class_subclasses[i][0]; | |
526 | *p1 != LIM_REG_CLASSES; | |
527 | p1++) | |
528 | if (*p1 != j && contains_reg_of_mode [*p1][m]) | |
529 | cost = MAX (cost, move_cost [m][*p1][j]); | |
530 | ||
531 | move_cost[m][i][j] = cost; | |
532 | ||
533 | if (reg_class_subset_p (i, j)) | |
534 | may_move_in_cost[m][i][j] = 0; | |
535 | else | |
536 | may_move_in_cost[m][i][j] = cost; | |
537 | ||
538 | if (reg_class_subset_p (j, i)) | |
539 | may_move_out_cost[m][i][j] = 0; | |
540 | else | |
541 | may_move_out_cost[m][i][j] = cost; | |
542 | } | |
543 | } | |
c1cc1ab4 | 544 | else |
cc693d06 | 545 | for (j = 0; j < N_REG_CLASSES; j++) |
546 | { | |
547 | move_cost[m][i][j] = 65536; | |
548 | may_move_in_cost[m][i][j] = 65536; | |
549 | may_move_out_cost[m][i][j] = 65536; | |
550 | } | |
551 | } | |
fc9bfb3a | 552 | } |
553 | ||
554 | /* Compute the table of register modes. | |
555 | These values are used to record death information for individual registers | |
556 | (as opposed to a multi-register mode). */ | |
d2b04fb8 | 557 | |
c235b58a | 558 | void |
559 | init_reg_modes_once (void) | |
fc9bfb3a | 560 | { |
67d6c12b | 561 | int i, j; |
562 | ||
563 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
564 | for (j = 0; j < MAX_MACHINE_MODE; j++) | |
565 | hard_regno_nregs[i][j] = HARD_REGNO_NREGS(i, (enum machine_mode)j); | |
d2b04fb8 | 566 | |
567 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1f902da9 | 568 | { |
b805295e | 569 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1, false); |
1f902da9 | 570 | |
0868ea21 | 571 | /* If we couldn't find a valid mode, just use the previous mode. |
1f902da9 | 572 | ??? One situation in which we need to do this is on the mips where |
573 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
574 | to use DF mode for the even registers and VOIDmode for the odd | |
c3418f42 | 575 | (for the cpu models where the odd ones are inaccessible). */ |
1f902da9 | 576 | if (reg_raw_mode[i] == VOIDmode) |
0868ea21 | 577 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
1f902da9 | 578 | } |
d2b04fb8 | 579 | } |
580 | ||
fc9bfb3a | 581 | /* Finish initializing the register sets and |
582 | initialize the register modes. */ | |
583 | ||
584 | void | |
3ad4992f | 585 | init_regs (void) |
fc9bfb3a | 586 | { |
587 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
588 | until after register usage was specified. */ | |
b54842d8 | 589 | init_reg_sets_1 (); |
fc9bfb3a | 590 | |
c8a9f9bf | 591 | init_reg_autoinc (); |
90295bd2 | 592 | } |
593 | ||
594 | /* Initialize some fake stack-frame MEM references for use in | |
595 | memory_move_secondary_cost. */ | |
4c685015 | 596 | |
90295bd2 | 597 | void |
3ad4992f | 598 | init_fake_stack_mems (void) |
90295bd2 | 599 | { |
4c685015 | 600 | { |
4c685015 | 601 | int i; |
c58d0063 | 602 | |
4c685015 | 603 | for (i = 0; i < MAX_MACHINE_MODE; i++) |
9e042f31 | 604 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
4c685015 | 605 | } |
fc9bfb3a | 606 | } |
607 | ||
4c685015 | 608 | |
3afef759 | 609 | /* Compute extra cost of moving registers to/from memory due to reloads. |
610 | Only needed if secondary reloads are required for memory moves. */ | |
4c685015 | 611 | |
3afef759 | 612 | int |
3ad4992f | 613 | memory_move_secondary_cost (enum machine_mode mode, enum reg_class class, int in) |
3afef759 | 614 | { |
615 | enum reg_class altclass; | |
616 | int partial_cost = 0; | |
3afef759 | 617 | /* We need a memory reference to feed to SECONDARY... macros. */ |
aa40f561 | 618 | /* mem may be unused even if the SECONDARY_ macros are defined. */ |
c5b89159 | 619 | rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; |
620 | ||
3afef759 | 621 | |
4d58fa46 | 622 | altclass = secondary_reload_class (in ? 1 : 0, class, mode, mem); |
4c685015 | 623 | |
3afef759 | 624 | if (altclass == NO_REGS) |
625 | return 0; | |
626 | ||
627 | if (in) | |
0ac516dc | 628 | partial_cost = REGISTER_MOVE_COST (mode, altclass, class); |
3afef759 | 629 | else |
0ac516dc | 630 | partial_cost = REGISTER_MOVE_COST (mode, class, altclass); |
3afef759 | 631 | |
632 | if (class == altclass) | |
633 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
634 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
635 | here in that case. | |
636 | ||
04e579b6 | 637 | I'm tempted to put in an assert here, but returning this will |
3afef759 | 638 | probably only give poor estimates, which is what we would've |
639 | had before this code anyways. */ | |
640 | return partial_cost; | |
641 | ||
642 | /* Check if the secondary reload register will also need a | |
643 | secondary reload. */ | |
644 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
645 | } | |
3afef759 | 646 | |
d2b04fb8 | 647 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
b805295e | 648 | enough to save nregs. If we can't find one, return VOIDmode. |
649 | If CALL_SAVED is true, only consider modes that are call saved. */ | |
d2b04fb8 | 650 | |
651 | enum machine_mode | |
3ad4992f | 652 | choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED, |
b805295e | 653 | unsigned int nregs, bool call_saved) |
d2b04fb8 | 654 | { |
0fd4500a | 655 | unsigned int /* enum machine_mode */ m; |
d2b04fb8 | 656 | enum machine_mode found_mode = VOIDmode, mode; |
657 | ||
658 | /* We first look for the largest integer mode that can be validly | |
659 | held in REGNO. If none, we look for the largest floating-point mode. | |
660 | If we still didn't find a valid mode, try CCmode. */ | |
661 | ||
662 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
663 | mode != VOIDmode; | |
664 | mode = GET_MODE_WIDER_MODE (mode)) | |
67d6c12b | 665 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
b805295e | 666 | && HARD_REGNO_MODE_OK (regno, mode) |
667 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
d2b04fb8 | 668 | found_mode = mode; |
669 | ||
670 | if (found_mode != VOIDmode) | |
671 | return found_mode; | |
672 | ||
673 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
674 | mode != VOIDmode; | |
675 | mode = GET_MODE_WIDER_MODE (mode)) | |
67d6c12b | 676 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
b805295e | 677 | && HARD_REGNO_MODE_OK (regno, mode) |
678 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
d2b04fb8 | 679 | found_mode = mode; |
680 | ||
681 | if (found_mode != VOIDmode) | |
682 | return found_mode; | |
683 | ||
47c327df | 684 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); |
685 | mode != VOIDmode; | |
686 | mode = GET_MODE_WIDER_MODE (mode)) | |
67d6c12b | 687 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
b805295e | 688 | && HARD_REGNO_MODE_OK (regno, mode) |
689 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
47c327df | 690 | found_mode = mode; |
691 | ||
692 | if (found_mode != VOIDmode) | |
693 | return found_mode; | |
694 | ||
695 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); | |
696 | mode != VOIDmode; | |
697 | mode = GET_MODE_WIDER_MODE (mode)) | |
67d6c12b | 698 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
b805295e | 699 | && HARD_REGNO_MODE_OK (regno, mode) |
700 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
47c327df | 701 | found_mode = mode; |
702 | ||
703 | if (found_mode != VOIDmode) | |
704 | return found_mode; | |
705 | ||
595d8922 | 706 | /* Iterate over all of the CCmodes. */ |
0fd4500a | 707 | for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) |
708 | { | |
709 | mode = (enum machine_mode) m; | |
67d6c12b | 710 | if ((unsigned) hard_regno_nregs[regno][mode] == nregs |
b805295e | 711 | && HARD_REGNO_MODE_OK (regno, mode) |
712 | && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) | |
0fd4500a | 713 | return mode; |
714 | } | |
d2b04fb8 | 715 | |
716 | /* We can't find a mode valid for this register. */ | |
717 | return VOIDmode; | |
ae09e9a3 | 718 | } |
719 | ||
720 | /* Specify the usage characteristics of the register named NAME. | |
721 | It should be a fixed register if FIXED and a | |
722 | call-used register if CALL_USED. */ | |
723 | ||
724 | void | |
3ad4992f | 725 | fix_register (const char *name, int fixed, int call_used) |
ae09e9a3 | 726 | { |
727 | int i; | |
728 | ||
729 | /* Decode the name and update the primary form of | |
730 | the register info. */ | |
731 | ||
4c0b30a9 | 732 | if ((i = decode_reg_name (name)) >= 0) |
733 | { | |
2c330d86 | 734 | if ((i == STACK_POINTER_REGNUM |
735 | #ifdef HARD_FRAME_POINTER_REGNUM | |
736 | || i == HARD_FRAME_POINTER_REGNUM | |
737 | #else | |
738 | || i == FRAME_POINTER_REGNUM | |
739 | #endif | |
740 | ) | |
741 | && (fixed == 0 || call_used == 0)) | |
742 | { | |
d2ca078f | 743 | static const char * const what_option[2][2] = { |
4063e82c | 744 | { "call-saved", "call-used" }, |
745 | { "no-such-option", "fixed" }}; | |
2617fe26 | 746 | |
747 | error ("can't use '%s' as a %s register", name, | |
2c330d86 | 748 | what_option[fixed][call_used]); |
749 | } | |
750 | else | |
751 | { | |
752 | fixed_regs[i] = fixed; | |
753 | call_used_regs[i] = call_used; | |
e28a648c | 754 | #ifdef CALL_REALLY_USED_REGISTERS |
d2d242b4 | 755 | if (fixed == 0) |
756 | call_really_used_regs[i] = call_used; | |
556ba85f | 757 | #endif |
2c330d86 | 758 | } |
4c0b30a9 | 759 | } |
760 | else | |
ae09e9a3 | 761 | { |
c3ceba8e | 762 | warning (0, "unknown register name: %s", name); |
ae09e9a3 | 763 | } |
764 | } | |
b8f0384b | 765 | |
766 | /* Mark register number I as global. */ | |
767 | ||
768 | void | |
3ad4992f | 769 | globalize_reg (int i) |
b8f0384b | 770 | { |
7d0e67ac | 771 | if (fixed_regs[i] == 0 && no_global_reg_vars) |
f18e6699 | 772 | error ("global register variable follows a function definition"); |
773 | ||
b8f0384b | 774 | if (global_regs[i]) |
775 | { | |
c3ceba8e | 776 | warning (0, "register used for two global register variables"); |
b8f0384b | 777 | return; |
778 | } | |
779 | ||
780 | if (call_used_regs[i] && ! fixed_regs[i]) | |
c3ceba8e | 781 | warning (0, "call-clobbered register used for global register variable"); |
b8f0384b | 782 | |
783 | global_regs[i] = 1; | |
784 | ||
1fbc37ff | 785 | /* If we're globalizing the frame pointer, we need to set the |
786 | appropriate regs_invalidated_by_call bit, even if it's already | |
787 | set in fixed_regs. */ | |
788 | if (i != STACK_POINTER_REGNUM) | |
789 | SET_HARD_REG_BIT (regs_invalidated_by_call, i); | |
790 | ||
b8f0384b | 791 | /* If already fixed, nothing else to do. */ |
792 | if (fixed_regs[i]) | |
793 | return; | |
794 | ||
795 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
170e5ff4 | 796 | #ifdef CALL_REALLY_USED_REGISTERS |
797 | call_really_used_regs[i] = 1; | |
798 | #endif | |
b8f0384b | 799 | n_non_fixed_regs--; |
800 | ||
801 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
802 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
803 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
804 | } | |
ae09e9a3 | 805 | \f |
806 | /* Now the data and code for the `regclass' pass, which happens | |
807 | just before local-alloc. */ | |
808 | ||
4023cea7 | 809 | /* The `costs' struct records the cost of using a hard register of each class |
810 | and of using memory for each pseudo. We use this data to set up | |
811 | register class preferences. */ | |
ae09e9a3 | 812 | |
4023cea7 | 813 | struct costs |
ae09e9a3 | 814 | { |
4023cea7 | 815 | int cost[N_REG_CLASSES]; |
816 | int mem_cost; | |
ae09e9a3 | 817 | }; |
818 | ||
41a6f238 | 819 | /* Structure used to record preferences of given pseudo. */ |
ef776217 | 820 | struct reg_pref |
821 | { | |
822 | /* (enum reg_class) prefclass is the preferred class. */ | |
823 | char prefclass; | |
824 | ||
825 | /* altclass is a register class that we should use for allocating | |
826 | pseudo if no register in the preferred class is available. | |
827 | If no register in this class is available, memory is preferred. | |
828 | ||
829 | It might appear to be more general to have a bitmask of classes here, | |
830 | but since it is recommended that there be a class corresponding to the | |
831 | union of most major pair of classes, that generality is not required. */ | |
832 | char altclass; | |
833 | }; | |
834 | ||
4023cea7 | 835 | /* Record the cost of each class for each pseudo. */ |
836 | ||
837 | static struct costs *costs; | |
838 | ||
c426f6be | 839 | /* Initialized once, and used to initialize cost values for each insn. */ |
840 | ||
841 | static struct costs init_cost; | |
842 | ||
41a6f238 | 843 | /* Record preferences of each pseudo. |
ae09e9a3 | 844 | This is available after `regclass' is run. */ |
845 | ||
ef776217 | 846 | static struct reg_pref *reg_pref; |
66adfeef | 847 | |
aa40f561 | 848 | /* Allocated buffers for reg_pref. */ |
ae09e9a3 | 849 | |
ef776217 | 850 | static struct reg_pref *reg_pref_buffer; |
d6ff8d83 | 851 | |
8172d01c | 852 | /* Frequency of executions of current insn. */ |
66adfeef | 853 | |
8172d01c | 854 | static int frequency; |
66adfeef | 855 | |
3ad4992f | 856 | static rtx scan_one_insn (rtx, int); |
857 | static void record_operand_costs (rtx, struct costs *, struct reg_pref *); | |
858 | static void dump_regclass (FILE *); | |
859 | static void record_reg_classes (int, int, rtx *, enum machine_mode *, | |
860 | const char **, rtx, struct costs *, | |
861 | struct reg_pref *); | |
4d58fa46 | 862 | static int copy_cost (rtx, enum machine_mode, enum reg_class, int, |
863 | secondary_reload_info *); | |
3ad4992f | 864 | static void record_address_regs (rtx, enum reg_class, int); |
99c14947 | 865 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
3ad4992f | 866 | static int auto_inc_dec_reg_p (rtx, enum machine_mode); |
99c14947 | 867 | #endif |
3ad4992f | 868 | static void reg_scan_mark_refs (rtx, rtx, int, unsigned int); |
ae09e9a3 | 869 | |
870 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
871 | This function is sometimes called before the info has been computed. | |
872 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
873 | ||
874 | enum reg_class | |
3ad4992f | 875 | reg_preferred_class (int regno) |
ae09e9a3 | 876 | { |
ef776217 | 877 | if (reg_pref == 0) |
ae09e9a3 | 878 | return GENERAL_REGS; |
ef776217 | 879 | return (enum reg_class) reg_pref[regno].prefclass; |
ae09e9a3 | 880 | } |
881 | ||
4023cea7 | 882 | enum reg_class |
3ad4992f | 883 | reg_alternate_class (int regno) |
ae09e9a3 | 884 | { |
ef776217 | 885 | if (reg_pref == 0) |
4023cea7 | 886 | return ALL_REGS; |
887 | ||
ef776217 | 888 | return (enum reg_class) reg_pref[regno].altclass; |
ae09e9a3 | 889 | } |
890 | ||
c426f6be | 891 | /* Initialize some global data for this pass. */ |
ae09e9a3 | 892 | |
893 | void | |
3ad4992f | 894 | regclass_init (void) |
ae09e9a3 | 895 | { |
c426f6be | 896 | int i; |
897 | ||
898 | init_cost.mem_cost = 10000; | |
899 | for (i = 0; i < N_REG_CLASSES; i++) | |
900 | init_cost.cost[i] = 10000; | |
901 | ||
902 | /* This prevents dump_flow_info from losing if called | |
903 | before regclass is run. */ | |
ef776217 | 904 | reg_pref = NULL; |
f18e6699 | 905 | |
aa40f561 | 906 | /* No more global register variables may be declared. */ |
f18e6699 | 907 | no_global_reg_vars = 1; |
ae09e9a3 | 908 | } |
ac147b1a | 909 | \f |
910 | /* Dump register costs. */ | |
20cfb17d | 911 | static void |
3ad4992f | 912 | dump_regclass (FILE *dump) |
ac147b1a | 913 | { |
ac147b1a | 914 | int i; |
915 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
916 | { | |
0fd4500a | 917 | int /* enum reg_class */ class; |
ac147b1a | 918 | if (REG_N_REFS (i)) |
919 | { | |
299a8d4e | 920 | fprintf (dump, " Register %i costs:", i); |
0fd4500a | 921 | for (class = 0; class < (int) N_REG_CLASSES; class++) |
922 | if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] | |
0279c35a | 923 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
0fd4500a | 924 | && (!in_inc_dec[i] |
925 | || !forbidden_inc_dec_class[(enum reg_class) class]) | |
0279c35a | 926 | #endif |
897118e8 | 927 | #ifdef CANNOT_CHANGE_MODE_CLASS |
928 | && ! invalid_mode_change_p (i, (enum reg_class) class, | |
929 | PSEUDO_REGNO_MODE (i)) | |
0279c35a | 930 | #endif |
931 | ) | |
0fd4500a | 932 | fprintf (dump, " %s:%i", reg_class_names[class], |
933 | costs[i].cost[(enum reg_class) class]); | |
299a8d4e | 934 | fprintf (dump, " MEM:%i\n", costs[i].mem_cost); |
ac147b1a | 935 | } |
936 | } | |
937 | } | |
299a8d4e | 938 | \f |
939 | ||
940 | /* Calculate the costs of insn operands. */ | |
941 | ||
942 | static void | |
3ad4992f | 943 | record_operand_costs (rtx insn, struct costs *op_costs, |
944 | struct reg_pref *reg_pref) | |
299a8d4e | 945 | { |
946 | const char *constraints[MAX_RECOG_OPERANDS]; | |
947 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
299a8d4e | 948 | int i; |
949 | ||
950 | for (i = 0; i < recog_data.n_operands; i++) | |
951 | { | |
952 | constraints[i] = recog_data.constraints[i]; | |
953 | modes[i] = recog_data.operand_mode[i]; | |
954 | } | |
299a8d4e | 955 | |
956 | /* If we get here, we are set up to record the costs of all the | |
957 | operands for this insn. Start by initializing the costs. | |
958 | Then handle any address registers. Finally record the desired | |
959 | classes for any pseudos, doing it twice if some pair of | |
960 | operands are commutative. */ | |
2617fe26 | 961 | |
299a8d4e | 962 | for (i = 0; i < recog_data.n_operands; i++) |
963 | { | |
964 | op_costs[i] = init_cost; | |
965 | ||
966 | if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
897118e8 | 967 | recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); |
299a8d4e | 968 | |
e16ceb8e | 969 | if (MEM_P (recog_data.operand[i])) |
299a8d4e | 970 | record_address_regs (XEXP (recog_data.operand[i], 0), |
2e6d14e8 | 971 | MODE_BASE_REG_CLASS (modes[i]), frequency * 2); |
a5004c3d | 972 | else if (constraints[i][0] == 'p' |
48ea5577 | 973 | || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i])) |
299a8d4e | 974 | record_address_regs (recog_data.operand[i], |
2e6d14e8 | 975 | MODE_BASE_REG_CLASS (modes[i]), frequency * 2); |
299a8d4e | 976 | } |
977 | ||
978 | /* Check for commutative in a separate loop so everything will | |
979 | have been initialized. We must do this even if one operand | |
980 | is a constant--see addsi3 in m68k.md. */ | |
981 | ||
982 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
983 | if (constraints[i][0] == '%') | |
984 | { | |
985 | const char *xconstraints[MAX_RECOG_OPERANDS]; | |
986 | int j; | |
ac147b1a | 987 | |
299a8d4e | 988 | /* Handle commutative operands by swapping the constraints. |
989 | We assume the modes are the same. */ | |
990 | ||
991 | for (j = 0; j < recog_data.n_operands; j++) | |
992 | xconstraints[j] = constraints[j]; | |
993 | ||
994 | xconstraints[i] = constraints[i+1]; | |
995 | xconstraints[i+1] = constraints[i]; | |
996 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
2617fe26 | 997 | recog_data.operand, modes, |
299a8d4e | 998 | xconstraints, insn, op_costs, reg_pref); |
999 | } | |
1000 | ||
1001 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
2617fe26 | 1002 | recog_data.operand, modes, |
299a8d4e | 1003 | constraints, insn, op_costs, reg_pref); |
1004 | } | |
ae09e9a3 | 1005 | \f |
c426f6be | 1006 | /* Subroutine of regclass, processes one insn INSN. Scan it and record each |
1007 | time it would save code to put a certain register in a certain class. | |
1008 | PASS, when nonzero, inhibits some optimizations which need only be done | |
1009 | once. | |
1010 | Return the last insn processed, so that the scan can be continued from | |
1011 | there. */ | |
1012 | ||
1013 | static rtx | |
3ad4992f | 1014 | scan_one_insn (rtx insn, int pass) |
c426f6be | 1015 | { |
c426f6be | 1016 | enum rtx_code pat_code; |
7f82be90 | 1017 | rtx set, note; |
c426f6be | 1018 | int i, j; |
299a8d4e | 1019 | struct costs op_costs[MAX_RECOG_OPERANDS]; |
c426f6be | 1020 | |
6720e96c | 1021 | if (!INSN_P (insn)) |
c426f6be | 1022 | return insn; |
1023 | ||
1024 | pat_code = GET_CODE (PATTERN (insn)); | |
1025 | if (pat_code == USE | |
1026 | || pat_code == CLOBBER | |
1027 | || pat_code == ASM_INPUT | |
1028 | || pat_code == ADDR_VEC | |
1029 | || pat_code == ADDR_DIFF_VEC) | |
1030 | return insn; | |
1031 | ||
7f82be90 | 1032 | set = single_set (insn); |
1033 | extract_insn (insn); | |
1034 | ||
7f82be90 | 1035 | /* If this insn loads a parameter from its stack slot, then |
1036 | it represents a savings, rather than a cost, if the | |
1037 | parameter is stored in memory. Record this fact. */ | |
c426f6be | 1038 | |
8ad4c111 | 1039 | if (set != 0 && REG_P (SET_DEST (set)) |
e16ceb8e | 1040 | && MEM_P (SET_SRC (set)) |
7f82be90 | 1041 | && (note = find_reg_note (insn, REG_EQUIV, |
1042 | NULL_RTX)) != 0 | |
e16ceb8e | 1043 | && MEM_P (XEXP (note, 0))) |
7f82be90 | 1044 | { |
1045 | costs[REGNO (SET_DEST (set))].mem_cost | |
1046 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), | |
1047 | GENERAL_REGS, 1) | |
8172d01c | 1048 | * frequency); |
7f82be90 | 1049 | record_address_regs (XEXP (SET_SRC (set), 0), |
2e6d14e8 | 1050 | MODE_BASE_REG_CLASS (VOIDmode), frequency * 2); |
7f82be90 | 1051 | return insn; |
1052 | } | |
c426f6be | 1053 | |
7f82be90 | 1054 | /* Improve handling of two-address insns such as |
1055 | (set X (ashift CONST Y)) where CONST must be made to | |
1056 | match X. Change it into two insns: (set X CONST) | |
1057 | (set X (ashift X Y)). If we left this for reloading, it | |
1058 | would probably get three insns because X and Y might go | |
1059 | in the same place. This prevents X and Y from receiving | |
1060 | the same hard reg. | |
1061 | ||
1062 | We can only do this if the modes of operands 0 and 1 | |
1063 | (which might not be the same) are tieable and we only need | |
1064 | do this during our first pass. */ | |
1065 | ||
1066 | if (pass == 0 && optimize | |
ed420a25 | 1067 | && recog_data.n_operands >= 3 |
1068 | && recog_data.constraints[1][0] == '0' | |
1069 | && recog_data.constraints[1][1] == 0 | |
1070 | && CONSTANT_P (recog_data.operand[1]) | |
1071 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) | |
1072 | && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) | |
8ad4c111 | 1073 | && REG_P (recog_data.operand[0]) |
ed420a25 | 1074 | && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), |
1075 | recog_data.operand_mode[1])) | |
7f82be90 | 1076 | { |
1077 | rtx previnsn = prev_real_insn (insn); | |
1078 | rtx dest | |
ed420a25 | 1079 | = gen_lowpart (recog_data.operand_mode[1], |
1080 | recog_data.operand[0]); | |
7f82be90 | 1081 | rtx newinsn |
ed420a25 | 1082 | = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); |
c426f6be | 1083 | |
7f82be90 | 1084 | /* If this insn was the start of a basic block, |
1085 | include the new insn in that block. | |
1086 | We need not check for code_label here; | |
1087 | while a basic block can start with a code_label, | |
1088 | INSN could not be at the beginning of that block. */ | |
6d7dc5b9 | 1089 | if (previnsn == 0 || JUMP_P (previnsn)) |
c426f6be | 1090 | { |
4c26117a | 1091 | basic_block b; |
1092 | FOR_EACH_BB (b) | |
5496dbfc | 1093 | if (insn == BB_HEAD (b)) |
1094 | BB_HEAD (b) = newinsn; | |
c426f6be | 1095 | } |
1096 | ||
7f82be90 | 1097 | /* This makes one more setting of new insns's dest. */ |
ed420a25 | 1098 | REG_N_SETS (REGNO (recog_data.operand[0]))++; |
d95244df | 1099 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
8172d01c | 1100 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
c426f6be | 1101 | |
ed420a25 | 1102 | *recog_data.operand_loc[1] = recog_data.operand[0]; |
d95244df | 1103 | REG_N_REFS (REGNO (recog_data.operand[0]))++; |
8172d01c | 1104 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
ed420a25 | 1105 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
1106 | if (recog_data.dup_num[i] == 1) | |
d95244df | 1107 | { |
1108 | *recog_data.dup_loc[i] = recog_data.operand[0]; | |
1109 | REG_N_REFS (REGNO (recog_data.operand[0]))++; | |
8172d01c | 1110 | REG_FREQ (REGNO (recog_data.operand[0])) += frequency; |
d95244df | 1111 | } |
c426f6be | 1112 | |
7f82be90 | 1113 | return PREV_INSN (newinsn); |
c426f6be | 1114 | } |
1115 | ||
d1c0bcc3 | 1116 | record_operand_costs (insn, op_costs, reg_pref); |
c426f6be | 1117 | |
1118 | /* Now add the cost for each operand to the total costs for | |
1119 | its register. */ | |
1120 | ||
ed420a25 | 1121 | for (i = 0; i < recog_data.n_operands; i++) |
8ad4c111 | 1122 | if (REG_P (recog_data.operand[i]) |
ed420a25 | 1123 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) |
c426f6be | 1124 | { |
ed420a25 | 1125 | int regno = REGNO (recog_data.operand[i]); |
c426f6be | 1126 | struct costs *p = &costs[regno], *q = &op_costs[i]; |
1127 | ||
8172d01c | 1128 | p->mem_cost += q->mem_cost * frequency; |
c426f6be | 1129 | for (j = 0; j < N_REG_CLASSES; j++) |
8172d01c | 1130 | p->cost[j] += q->cost[j] * frequency; |
c426f6be | 1131 | } |
1132 | ||
1133 | return insn; | |
1134 | } | |
1135 | ||
c8a9f9bf | 1136 | /* Initialize information about which register classes can be used for |
1137 | pseudos that are auto-incremented or auto-decremented. */ | |
ae09e9a3 | 1138 | |
c8a9f9bf | 1139 | static void |
3ad4992f | 1140 | init_reg_autoinc (void) |
ae09e9a3 | 1141 | { |
3d46a046 | 1142 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
c8a9f9bf | 1143 | int i; |
3d46a046 | 1144 | |
1145 | for (i = 0; i < N_REG_CLASSES; i++) | |
1146 | { | |
c8a9f9bf | 1147 | rtx r = gen_rtx_raw_REG (VOIDmode, 0); |
3d46a046 | 1148 | enum machine_mode m; |
19cb6b50 | 1149 | int j; |
3d46a046 | 1150 | |
1151 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1152 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
1153 | { | |
1154 | REGNO (r) = j; | |
1155 | ||
1156 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
13df24e3 | 1157 | m = (enum machine_mode) ((int) m + 1)) |
3d46a046 | 1158 | if (HARD_REGNO_MODE_OK (j, m)) |
1159 | { | |
4d58fa46 | 1160 | enum reg_class base_class = MODE_BASE_REG_CLASS (VOIDmode); |
1161 | ||
3d46a046 | 1162 | PUT_MODE (r, m); |
4ac7d2be | 1163 | |
1164 | /* If a register is not directly suitable for an | |
1165 | auto-increment or decrement addressing mode and | |
1166 | requires secondary reloads, disallow its class from | |
1167 | being used in such addresses. */ | |
1168 | ||
4d58fa46 | 1169 | if ((secondary_reload_class (1, base_class, m, r) |
1170 | || secondary_reload_class (1, base_class, m, r)) | |
4ac7d2be | 1171 | && ! auto_inc_dec_reg_p (r, m)) |
3d46a046 | 1172 | forbidden_inc_dec_class[i] = 1; |
1173 | } | |
1174 | } | |
1175 | } | |
c8a9f9bf | 1176 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
1177 | } | |
1178 | ||
1179 | /* This is a pass of the compiler that scans all instructions | |
1180 | and calculates the preferred class for each pseudo-register. | |
1181 | This information can be accessed later by calling `reg_preferred_class'. | |
1182 | This pass comes just before local register allocation. */ | |
1183 | ||
1184 | void | |
3f5be5f4 | 1185 | regclass (rtx f, int nregs) |
c8a9f9bf | 1186 | { |
1187 | rtx insn; | |
1188 | int i; | |
1189 | int pass; | |
1190 | ||
1191 | init_recog (); | |
1192 | ||
4c36ffe6 | 1193 | costs = XNEWVEC (struct costs, nregs); |
c8a9f9bf | 1194 | |
1195 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1196 | ||
4c36ffe6 | 1197 | in_inc_dec = XNEWVEC (char, nregs); |
c8a9f9bf | 1198 | |
3d46a046 | 1199 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
1200 | ||
4023cea7 | 1201 | /* Normally we scan the insns once and determine the best class to use for |
1202 | each register. However, if -fexpensive_optimizations are on, we do so | |
1203 | twice, the second time using the tentative best classes to guide the | |
1204 | selection. */ | |
ae09e9a3 | 1205 | |
4023cea7 | 1206 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
1207 | { | |
4c26117a | 1208 | basic_block bb; |
299a8d4e | 1209 | |
3f5be5f4 | 1210 | if (dump_file) |
1211 | fprintf (dump_file, "\n\nPass %i\n\n",pass); | |
4023cea7 | 1212 | /* Zero out our accumulation of the cost of each class for each reg. */ |
ae09e9a3 | 1213 | |
f0af5a88 | 1214 | memset (costs, 0, nregs * sizeof (struct costs)); |
ae09e9a3 | 1215 | |
3d46a046 | 1216 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
93d3b7de | 1217 | memset (in_inc_dec, 0, nregs); |
3d46a046 | 1218 | #endif |
1219 | ||
4023cea7 | 1220 | /* Scan the instructions and record each time it would |
1221 | save code to put a certain register in a certain class. */ | |
1222 | ||
d8817c59 | 1223 | if (!optimize) |
ae09e9a3 | 1224 | { |
eefdec48 | 1225 | frequency = REG_FREQ_MAX; |
d8817c59 | 1226 | for (insn = f; insn; insn = NEXT_INSN (insn)) |
1227 | insn = scan_one_insn (insn, pass); | |
ae09e9a3 | 1228 | } |
d8817c59 | 1229 | else |
4c26117a | 1230 | FOR_EACH_BB (bb) |
d8817c59 | 1231 | { |
d8817c59 | 1232 | /* Show that an insn inside a loop is likely to be executed three |
b275aace | 1233 | times more than insns outside a loop. This is much more |
1234 | aggressive than the assumptions made elsewhere and is being | |
1235 | tried as an experiment. */ | |
eefdec48 | 1236 | frequency = REG_FREQ_FROM_BB (bb); |
5496dbfc | 1237 | for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn)) |
d8817c59 | 1238 | { |
1239 | insn = scan_one_insn (insn, pass); | |
5496dbfc | 1240 | if (insn == BB_END (bb)) |
d8817c59 | 1241 | break; |
1242 | } | |
1243 | } | |
2617fe26 | 1244 | |
4023cea7 | 1245 | /* Now for each register look at how desirable each class is |
1246 | and find which class is preferred. Store that in | |
ef776217 | 1247 | `prefclass'. Record in `altclass' the largest register |
4023cea7 | 1248 | class any of whose registers is better than memory. */ |
2617fe26 | 1249 | |
4023cea7 | 1250 | if (pass == 0) |
ef776217 | 1251 | reg_pref = reg_pref_buffer; |
ae09e9a3 | 1252 | |
3f5be5f4 | 1253 | if (dump_file) |
2617fe26 | 1254 | { |
3f5be5f4 | 1255 | dump_regclass (dump_file); |
1256 | fprintf (dump_file,"\n"); | |
299a8d4e | 1257 | } |
4023cea7 | 1258 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
ae09e9a3 | 1259 | { |
19cb6b50 | 1260 | int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
4023cea7 | 1261 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1262 | /* This is an enum reg_class, but we call it an int | |
1263 | to save lots of casts. */ | |
19cb6b50 | 1264 | int class; |
1265 | struct costs *p = &costs[i]; | |
4023cea7 | 1266 | |
adf6ebca | 1267 | /* In non-optimizing compilation REG_N_REFS is not initialized |
1268 | yet. */ | |
cb5c5698 | 1269 | if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i)) |
299a8d4e | 1270 | continue; |
1271 | ||
4023cea7 | 1272 | for (class = (int) ALL_REGS - 1; class > 0; class--) |
ae09e9a3 | 1273 | { |
3d46a046 | 1274 | /* Ignore classes that are too small for this operand or |
20dd417a | 1275 | invalid for an operand that was auto-incremented. */ |
0279c35a | 1276 | if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] |
3d46a046 | 1277 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1278 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e8e6034b | 1279 | #endif |
897118e8 | 1280 | #ifdef CANNOT_CHANGE_MODE_CLASS |
1281 | || invalid_mode_change_p (i, (enum reg_class) class, | |
1282 | PSEUDO_REGNO_MODE (i)) | |
3d46a046 | 1283 | #endif |
1284 | ) | |
4023cea7 | 1285 | ; |
1286 | else if (p->cost[class] < best_cost) | |
1287 | { | |
1288 | best_cost = p->cost[class]; | |
1289 | best = (enum reg_class) class; | |
1290 | } | |
1291 | else if (p->cost[class] == best_cost) | |
337d789b | 1292 | best = reg_class_subunion[(int) best][class]; |
ae09e9a3 | 1293 | } |
ae09e9a3 | 1294 | |
4023cea7 | 1295 | /* Record the alternate register class; i.e., a class for which |
1296 | every register in it is better than using memory. If adding a | |
1297 | class would make a smaller class (i.e., no union of just those | |
1298 | classes exists), skip that class. The major unions of classes | |
1299 | should be provided as a register class. Don't do this if we | |
1300 | will be doing it again later. */ | |
1301 | ||
3f5be5f4 | 1302 | if ((pass == 1 || dump_file) || ! flag_expensive_optimizations) |
4023cea7 | 1303 | for (class = 0; class < N_REG_CLASSES; class++) |
1304 | if (p->cost[class] < p->mem_cost | |
121f87c5 | 1305 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
3d46a046 | 1306 | > reg_class_size[(int) alt]) |
1307 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1308 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
e8e6034b | 1309 | #endif |
897118e8 | 1310 | #ifdef CANNOT_CHANGE_MODE_CLASS |
1311 | && ! invalid_mode_change_p (i, (enum reg_class) class, | |
1312 | PSEUDO_REGNO_MODE (i)) | |
3d46a046 | 1313 | #endif |
1314 | ) | |
4023cea7 | 1315 | alt = reg_class_subunion[(int) alt][class]; |
2617fe26 | 1316 | |
4023cea7 | 1317 | /* If we don't add any classes, nothing to try. */ |
1318 | if (alt == best) | |
4fe44868 | 1319 | alt = NO_REGS; |
4023cea7 | 1320 | |
3f5be5f4 | 1321 | if (dump_file |
299a8d4e | 1322 | && (reg_pref[i].prefclass != (int) best |
1323 | || reg_pref[i].altclass != (int) alt)) | |
1324 | { | |
3f5be5f4 | 1325 | fprintf (dump_file, " Register %i", i); |
299a8d4e | 1326 | if (alt == ALL_REGS || best == ALL_REGS) |
3f5be5f4 | 1327 | fprintf (dump_file, " pref %s\n", reg_class_names[(int) best]); |
299a8d4e | 1328 | else if (alt == NO_REGS) |
3f5be5f4 | 1329 | fprintf (dump_file, " pref %s or none\n", reg_class_names[(int) best]); |
299a8d4e | 1330 | else |
3f5be5f4 | 1331 | fprintf (dump_file, " pref %s, else %s\n", |
299a8d4e | 1332 | reg_class_names[(int) best], |
1333 | reg_class_names[(int) alt]); | |
1334 | } | |
1335 | ||
4023cea7 | 1336 | /* We cast to (int) because (char) hits bugs in some compilers. */ |
ef776217 | 1337 | reg_pref[i].prefclass = (int) best; |
1338 | reg_pref[i].altclass = (int) alt; | |
4023cea7 | 1339 | } |
ae09e9a3 | 1340 | } |
829c0ce9 | 1341 | |
b9cf3f63 | 1342 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
1343 | free (in_inc_dec); | |
1344 | #endif | |
829c0ce9 | 1345 | free (costs); |
ae09e9a3 | 1346 | } |
1347 | \f | |
4023cea7 | 1348 | /* Record the cost of using memory or registers of various classes for |
1349 | the operands in INSN. | |
ae09e9a3 | 1350 | |
4023cea7 | 1351 | N_ALTS is the number of alternatives. |
ae09e9a3 | 1352 | |
4023cea7 | 1353 | N_OPS is the number of operands. |
1354 | ||
1355 | OPS is an array of the operands. | |
1356 | ||
1357 | MODES are the modes of the operands, in case any are VOIDmode. | |
1358 | ||
1359 | CONSTRAINTS are the constraints to use for the operands. This array | |
1360 | is modified by this procedure. | |
1361 | ||
1362 | This procedure works alternative by alternative. For each alternative | |
1363 | we assume that we will be able to allocate all pseudos to their ideal | |
1364 | register class and calculate the cost of using that alternative. Then | |
2617fe26 | 1365 | we compute for each operand that is a pseudo-register, the cost of |
4023cea7 | 1366 | having the pseudo allocated to each register class and using it in that |
1367 | alternative. To this cost is added the cost of the alternative. | |
1368 | ||
1369 | The cost of each class for this insn is its lowest cost among all the | |
1370 | alternatives. */ | |
1371 | ||
1372 | static void | |
3ad4992f | 1373 | record_reg_classes (int n_alts, int n_ops, rtx *ops, |
1374 | enum machine_mode *modes, const char **constraints, | |
1375 | rtx insn, struct costs *op_costs, | |
1376 | struct reg_pref *reg_pref) | |
ae09e9a3 | 1377 | { |
4023cea7 | 1378 | int alt; |
4023cea7 | 1379 | int i, j; |
1f8d882f | 1380 | rtx set; |
4023cea7 | 1381 | |
4023cea7 | 1382 | /* Process each alternative, each time minimizing an operand's cost with |
1383 | the cost for each operand in that alternative. */ | |
ae09e9a3 | 1384 | |
4023cea7 | 1385 | for (alt = 0; alt < n_alts; alt++) |
ae09e9a3 | 1386 | { |
4023cea7 | 1387 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1388 | int alt_fail = 0; | |
1389 | int alt_cost = 0; | |
1390 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
2cc205f8 | 1391 | int allows_mem[MAX_RECOG_OPERANDS]; |
4023cea7 | 1392 | int class; |
ae09e9a3 | 1393 | |
4023cea7 | 1394 | for (i = 0; i < n_ops; i++) |
1395 | { | |
a8482e91 | 1396 | const char *p = constraints[i]; |
4023cea7 | 1397 | rtx op = ops[i]; |
1398 | enum machine_mode mode = modes[i]; | |
65678154 | 1399 | int allows_addr = 0; |
4023cea7 | 1400 | int win = 0; |
274c11d8 | 1401 | unsigned char c; |
ae09e9a3 | 1402 | |
e9cda871 | 1403 | /* Initially show we know nothing about the register class. */ |
1404 | classes[i] = NO_REGS; | |
2cc205f8 | 1405 | allows_mem[i] = 0; |
e9cda871 | 1406 | |
2617fe26 | 1407 | /* If this operand has no constraints at all, we can conclude |
4023cea7 | 1408 | nothing about it since anything is valid. */ |
ae09e9a3 | 1409 | |
4023cea7 | 1410 | if (*p == 0) |
1411 | { | |
8ad4c111 | 1412 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) |
f0af5a88 | 1413 | memset (&this_op_costs[i], 0, sizeof this_op_costs[i]); |
ae09e9a3 | 1414 | |
4023cea7 | 1415 | continue; |
1416 | } | |
ae09e9a3 | 1417 | |
e9cda871 | 1418 | /* If this alternative is only relevant when this operand |
1419 | matches a previous operand, we do different things depending | |
1420 | on whether this operand is a pseudo-reg or not. We must process | |
1421 | any modifiers for the operand before we can make this test. */ | |
1422 | ||
9a5e3964 | 1423 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') |
7f82be90 | 1424 | p++; |
9a5e3964 | 1425 | |
4023cea7 | 1426 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1427 | { | |
2cc205f8 | 1428 | /* Copy class and whether memory is allowed from the matching |
1429 | alternative. Then perform any needed cost computations | |
1430 | and/or adjustments. */ | |
4023cea7 | 1431 | j = p[0] - '0'; |
1432 | classes[i] = classes[j]; | |
2cc205f8 | 1433 | allows_mem[i] = allows_mem[j]; |
4023cea7 | 1434 | |
8ad4c111 | 1435 | if (!REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) |
4023cea7 | 1436 | { |
1437 | /* If this matches the other operand, we have no added | |
deff29cb | 1438 | cost and we win. */ |
4023cea7 | 1439 | if (rtx_equal_p (ops[j], op)) |
deff29cb | 1440 | win = 1; |
4023cea7 | 1441 | |
64ff0ff2 | 1442 | /* If we can put the other operand into a register, add to |
1443 | the cost of this alternative the cost to copy this | |
1444 | operand to the register used for the other operand. */ | |
4023cea7 | 1445 | |
deff29cb | 1446 | else if (classes[j] != NO_REGS) |
4d58fa46 | 1447 | { |
1448 | alt_cost += copy_cost (op, mode, classes[j], 1, NULL); | |
1449 | win = 1; | |
1450 | } | |
4023cea7 | 1451 | } |
8ad4c111 | 1452 | else if (!REG_P (ops[j]) |
0c60cf1b | 1453 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) |
1454 | { | |
1455 | /* This op is a pseudo but the one it matches is not. */ | |
2617fe26 | 1456 | |
0c60cf1b | 1457 | /* If we can't put the other operand into a register, this |
1458 | alternative can't be used. */ | |
1459 | ||
1460 | if (classes[j] == NO_REGS) | |
1461 | alt_fail = 1; | |
4023cea7 | 1462 | |
0c60cf1b | 1463 | /* Otherwise, add to the cost of this alternative the cost |
1464 | to copy the other operand to the register used for this | |
1465 | operand. */ | |
1466 | ||
1467 | else | |
4d58fa46 | 1468 | alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL); |
0c60cf1b | 1469 | } |
4023cea7 | 1470 | else |
1471 | { | |
2cc205f8 | 1472 | /* The costs of this operand are not the same as the other |
1473 | operand since move costs are not symmetric. Moreover, | |
1474 | if we cannot tie them, this alternative needs to do a | |
1475 | copy, which is one instruction. */ | |
1476 | ||
1477 | struct costs *pp = &this_op_costs[i]; | |
1478 | ||
1479 | for (class = 0; class < N_REG_CLASSES; class++) | |
1480 | pp->cost[class] | |
8cd81992 | 1481 | = ((recog_data.operand_type[i] != OP_OUT |
0ac516dc | 1482 | ? may_move_in_cost[mode][class][(int) classes[i]] |
8cd81992 | 1483 | : 0) |
1484 | + (recog_data.operand_type[i] != OP_IN | |
0ac516dc | 1485 | ? may_move_out_cost[mode][(int) classes[i]][class] |
8cd81992 | 1486 | : 0)); |
2617fe26 | 1487 | |
2cc205f8 | 1488 | /* If the alternative actually allows memory, make things |
1489 | a bit cheaper since we won't need an extra insn to | |
1490 | load it. */ | |
1491 | ||
1492 | pp->mem_cost | |
8cd81992 | 1493 | = ((recog_data.operand_type[i] != OP_IN |
1494 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1495 | : 0) | |
1496 | + (recog_data.operand_type[i] != OP_OUT | |
1497 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1498 | : 0) - allows_mem[i]); | |
2cc205f8 | 1499 | |
1500 | /* If we have assigned a class to this register in our | |
1501 | first pass, add a cost to this alternative corresponding | |
1502 | to what we would add if this register were not in the | |
1503 | appropriate class. */ | |
1504 | ||
ef776217 | 1505 | if (reg_pref) |
2cc205f8 | 1506 | alt_cost |
0ac516dc | 1507 | += (may_move_in_cost[mode] |
1508 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
2cc205f8 | 1509 | [(int) classes[i]]); |
4023cea7 | 1510 | |
8f03fdc8 | 1511 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1512 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1513 | alt_cost += 2; | |
4023cea7 | 1514 | |
86ff3166 | 1515 | /* This is in place of ordinary cost computation |
cf4b8e5a | 1516 | for this operand, so skip to the end of the |
1517 | alternative (should be just one character). */ | |
1518 | while (*p && *p++ != ',') | |
1519 | ; | |
1520 | ||
1521 | constraints[i] = p; | |
86ff3166 | 1522 | continue; |
1523 | } | |
4023cea7 | 1524 | } |
1525 | ||
1526 | /* Scan all the constraint letters. See if the operand matches | |
1527 | any of the constraints. Collect the valid register classes | |
1528 | and see if this operand accepts memory. */ | |
1529 | ||
48ea5577 | 1530 | while ((c = *p)) |
1531 | { | |
1532 | switch (c) | |
1533 | { | |
1534 | case ',': | |
1535 | break; | |
1536 | case '*': | |
1537 | /* Ignore the next letter for this pass. */ | |
1538 | c = *++p; | |
1539 | break; | |
65678154 | 1540 | |
48ea5577 | 1541 | case '?': |
1542 | alt_cost += 2; | |
1543 | case '!': case '#': case '&': | |
1544 | case '0': case '1': case '2': case '3': case '4': | |
1545 | case '5': case '6': case '7': case '8': case '9': | |
1546 | break; | |
4023cea7 | 1547 | |
48ea5577 | 1548 | case 'p': |
1549 | allows_addr = 1; | |
1550 | win = address_operand (op, GET_MODE (op)); | |
1551 | /* We know this operand is an address, so we want it to be | |
1552 | allocated to a register that can be the base of an | |
0c6d8c36 | 1553 | address, i.e. BASE_REG_CLASS. */ |
48ea5577 | 1554 | classes[i] |
1555 | = reg_class_subunion[(int) classes[i]] | |
1556 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
1557 | break; | |
4023cea7 | 1558 | |
48ea5577 | 1559 | case 'm': case 'o': case 'V': |
1560 | /* It doesn't seem worth distinguishing between offsettable | |
1561 | and non-offsettable addresses here. */ | |
1562 | allows_mem[i] = 1; | |
e16ceb8e | 1563 | if (MEM_P (op)) |
48ea5577 | 1564 | win = 1; |
1565 | break; | |
4023cea7 | 1566 | |
48ea5577 | 1567 | case '<': |
e16ceb8e | 1568 | if (MEM_P (op) |
48ea5577 | 1569 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC |
1570 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1571 | win = 1; | |
1572 | break; | |
4023cea7 | 1573 | |
48ea5577 | 1574 | case '>': |
e16ceb8e | 1575 | if (MEM_P (op) |
48ea5577 | 1576 | && (GET_CODE (XEXP (op, 0)) == PRE_INC |
1577 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1578 | win = 1; | |
1579 | break; | |
4023cea7 | 1580 | |
48ea5577 | 1581 | case 'E': |
1582 | case 'F': | |
1583 | if (GET_CODE (op) == CONST_DOUBLE | |
1584 | || (GET_CODE (op) == CONST_VECTOR | |
1585 | && (GET_MODE_CLASS (GET_MODE (op)) | |
1586 | == MODE_VECTOR_FLOAT))) | |
1587 | win = 1; | |
1588 | break; | |
4023cea7 | 1589 | |
48ea5577 | 1590 | case 'G': |
1591 | case 'H': | |
1592 | if (GET_CODE (op) == CONST_DOUBLE | |
1593 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) | |
1594 | win = 1; | |
4023cea7 | 1595 | break; |
48ea5577 | 1596 | |
1597 | case 's': | |
1598 | if (GET_CODE (op) == CONST_INT | |
1599 | || (GET_CODE (op) == CONST_DOUBLE | |
1600 | && GET_MODE (op) == VOIDmode)) | |
1601 | break; | |
1602 | case 'i': | |
1603 | if (CONSTANT_P (op) | |
7151fd0e | 1604 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))) |
48ea5577 | 1605 | win = 1; |
1606 | break; | |
4023cea7 | 1607 | |
48ea5577 | 1608 | case 'n': |
1609 | if (GET_CODE (op) == CONST_INT | |
1610 | || (GET_CODE (op) == CONST_DOUBLE | |
1611 | && GET_MODE (op) == VOIDmode)) | |
1612 | win = 1; | |
1613 | break; | |
4023cea7 | 1614 | |
48ea5577 | 1615 | case 'I': |
1616 | case 'J': | |
1617 | case 'K': | |
1618 | case 'L': | |
1619 | case 'M': | |
1620 | case 'N': | |
1621 | case 'O': | |
1622 | case 'P': | |
1623 | if (GET_CODE (op) == CONST_INT | |
1624 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) | |
1625 | win = 1; | |
1626 | break; | |
4023cea7 | 1627 | |
48ea5577 | 1628 | case 'X': |
1629 | win = 1; | |
1630 | break; | |
ae09e9a3 | 1631 | |
48ea5577 | 1632 | case 'g': |
e16ceb8e | 1633 | if (MEM_P (op) |
48ea5577 | 1634 | || (CONSTANT_P (op) |
7151fd0e | 1635 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))) |
48ea5577 | 1636 | win = 1; |
1637 | allows_mem[i] = 1; | |
1638 | case 'r': | |
f3653a64 | 1639 | classes[i] |
48ea5577 | 1640 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; |
1641 | break; | |
a5004c3d | 1642 | |
48ea5577 | 1643 | default: |
1644 | if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS) | |
a5004c3d | 1645 | classes[i] |
1646 | = reg_class_subunion[(int) classes[i]] | |
48ea5577 | 1647 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; |
1648 | #ifdef EXTRA_CONSTRAINT_STR | |
1649 | else if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
1650 | win = 1; | |
1651 | ||
1652 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
1653 | { | |
1654 | /* Every MEM can be reloaded to fit. */ | |
1655 | allows_mem[i] = 1; | |
e16ceb8e | 1656 | if (MEM_P (op)) |
48ea5577 | 1657 | win = 1; |
1658 | } | |
1659 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
1660 | { | |
1661 | /* Every address can be reloaded to fit. */ | |
1662 | allows_addr = 1; | |
1663 | if (address_operand (op, GET_MODE (op))) | |
1664 | win = 1; | |
1665 | /* We know this operand is an address, so we want it to | |
1666 | be allocated to a register that can be the base of an | |
0c6d8c36 | 1667 | address, i.e. BASE_REG_CLASS. */ |
48ea5577 | 1668 | classes[i] |
1669 | = reg_class_subunion[(int) classes[i]] | |
1670 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
1671 | } | |
f3653a64 | 1672 | #endif |
48ea5577 | 1673 | break; |
1674 | } | |
1675 | p += CONSTRAINT_LEN (c, p); | |
1676 | if (c == ',') | |
f3653a64 | 1677 | break; |
48ea5577 | 1678 | } |
4023cea7 | 1679 | |
1680 | constraints[i] = p; | |
1681 | ||
1682 | /* How we account for this operand now depends on whether it is a | |
1683 | pseudo register or not. If it is, we first check if any | |
1684 | register classes are valid. If not, we ignore this alternative, | |
1685 | since we want to assume that all pseudos get allocated for | |
1686 | register preferencing. If some register class is valid, compute | |
1687 | the costs of moving the pseudo into that class. */ | |
1688 | ||
8ad4c111 | 1689 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) |
8659a89f | 1690 | { |
4023cea7 | 1691 | if (classes[i] == NO_REGS) |
65678154 | 1692 | { |
e8e6034b | 1693 | /* We must always fail if the operand is a REG, but |
1694 | we did not find a suitable class. | |
2617fe26 | 1695 | |
e8e6034b | 1696 | Otherwise we may perform an uninitialized read |
1697 | from this_op_costs after the `continue' statement | |
1698 | below. */ | |
1699 | alt_fail = 1; | |
65678154 | 1700 | } |
4023cea7 | 1701 | else |
1702 | { | |
1703 | struct costs *pp = &this_op_costs[i]; | |
1704 | ||
1705 | for (class = 0; class < N_REG_CLASSES; class++) | |
155b05dc | 1706 | pp->cost[class] |
8cd81992 | 1707 | = ((recog_data.operand_type[i] != OP_OUT |
0ac516dc | 1708 | ? may_move_in_cost[mode][class][(int) classes[i]] |
8cd81992 | 1709 | : 0) |
1710 | + (recog_data.operand_type[i] != OP_IN | |
0ac516dc | 1711 | ? may_move_out_cost[mode][(int) classes[i]][class] |
8cd81992 | 1712 | : 0)); |
4023cea7 | 1713 | |
1714 | /* If the alternative actually allows memory, make things | |
1715 | a bit cheaper since we won't need an extra insn to | |
1716 | load it. */ | |
1717 | ||
155b05dc | 1718 | pp->mem_cost |
8cd81992 | 1719 | = ((recog_data.operand_type[i] != OP_IN |
1720 | ? MEMORY_MOVE_COST (mode, classes[i], 0) | |
1721 | : 0) | |
1722 | + (recog_data.operand_type[i] != OP_OUT | |
1723 | ? MEMORY_MOVE_COST (mode, classes[i], 1) | |
1724 | : 0) - allows_mem[i]); | |
4023cea7 | 1725 | |
1726 | /* If we have assigned a class to this register in our | |
1727 | first pass, add a cost to this alternative corresponding | |
1728 | to what we would add if this register were not in the | |
1729 | appropriate class. */ | |
1730 | ||
ef776217 | 1731 | if (reg_pref) |
4023cea7 | 1732 | alt_cost |
0ac516dc | 1733 | += (may_move_in_cost[mode] |
1734 | [(unsigned char) reg_pref[REGNO (op)].prefclass] | |
155b05dc | 1735 | [(int) classes[i]]); |
4023cea7 | 1736 | } |
8659a89f | 1737 | } |
ae09e9a3 | 1738 | |
4023cea7 | 1739 | /* Otherwise, if this alternative wins, either because we |
1740 | have already determined that or if we have a hard register of | |
1741 | the proper class, there is no cost for this alternative. */ | |
ae09e9a3 | 1742 | |
4023cea7 | 1743 | else if (win |
8ad4c111 | 1744 | || (REG_P (op) |
40c12d65 | 1745 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
4023cea7 | 1746 | ; |
ae09e9a3 | 1747 | |
4023cea7 | 1748 | /* If registers are valid, the cost of this alternative includes |
1749 | copying the object to and/or from a register. */ | |
ae09e9a3 | 1750 | |
4023cea7 | 1751 | else if (classes[i] != NO_REGS) |
1752 | { | |
ed420a25 | 1753 | if (recog_data.operand_type[i] != OP_OUT) |
4d58fa46 | 1754 | alt_cost += copy_cost (op, mode, classes[i], 1, NULL); |
ae09e9a3 | 1755 | |
ed420a25 | 1756 | if (recog_data.operand_type[i] != OP_IN) |
4d58fa46 | 1757 | alt_cost += copy_cost (op, mode, classes[i], 0, NULL); |
4023cea7 | 1758 | } |
ae09e9a3 | 1759 | |
4023cea7 | 1760 | /* The only other way this alternative can be used is if this is a |
1761 | constant that could be placed into memory. */ | |
1762 | ||
2cc205f8 | 1763 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) |
3afef759 | 1764 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
4023cea7 | 1765 | else |
1766 | alt_fail = 1; | |
1767 | } | |
1768 | ||
1769 | if (alt_fail) | |
1770 | continue; | |
1771 | ||
1772 | /* Finally, update the costs with the information we've calculated | |
1773 | about this alternative. */ | |
1774 | ||
1775 | for (i = 0; i < n_ops; i++) | |
8ad4c111 | 1776 | if (REG_P (ops[i]) |
4023cea7 | 1777 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) |
ae09e9a3 | 1778 | { |
4023cea7 | 1779 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
ed420a25 | 1780 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
ae09e9a3 | 1781 | |
4023cea7 | 1782 | pp->mem_cost = MIN (pp->mem_cost, |
1783 | (qq->mem_cost + alt_cost) * scale); | |
ae09e9a3 | 1784 | |
4023cea7 | 1785 | for (class = 0; class < N_REG_CLASSES; class++) |
1786 | pp->cost[class] = MIN (pp->cost[class], | |
1787 | (qq->cost[class] + alt_cost) * scale); | |
1788 | } | |
1789 | } | |
1f8d882f | 1790 | |
1791 | /* If this insn is a single set copying operand 1 to operand 0 | |
392f94ec | 1792 | and one operand is a pseudo with the other a hard reg or a pseudo |
1793 | that prefers a register that is in its own register class then | |
1794 | we may want to adjust the cost of that register class to -1. | |
2617fe26 | 1795 | |
392f94ec | 1796 | Avoid the adjustment if the source does not die to avoid stressing of |
917bbcab | 1797 | register allocator by preferrencing two colliding registers into single |
392f94ec | 1798 | class. |
1799 | ||
1800 | Also avoid the adjustment if a copy between registers of the class | |
1801 | is expensive (ten times the cost of a default copy is considered | |
1802 | arbitrarily expensive). This avoids losing when the preferred class | |
1803 | is very expensive as the source of a copy instruction. */ | |
1f8d882f | 1804 | |
1805 | if ((set = single_set (insn)) != 0 | |
1806 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
8ad4c111 | 1807 | && REG_P (ops[0]) && REG_P (ops[1]) |
ae150852 | 1808 | && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) |
1f8d882f | 1809 | for (i = 0; i <= 1; i++) |
1810 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1811 | { | |
02e7a332 | 1812 | unsigned int regno = REGNO (ops[!i]); |
1f8d882f | 1813 | enum machine_mode mode = GET_MODE (ops[!i]); |
1814 | int class; | |
02e7a332 | 1815 | unsigned int nr; |
1f8d882f | 1816 | |
392f94ec | 1817 | if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0) |
1818 | { | |
1819 | enum reg_class pref = reg_pref[regno].prefclass; | |
1820 | ||
1821 | if ((reg_class_size[(unsigned char) pref] | |
bb37f971 | 1822 | == (unsigned) CLASS_MAX_NREGS (pref, mode)) |
0ac516dc | 1823 | && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) |
392f94ec | 1824 | op_costs[i].cost[(unsigned char) pref] = -1; |
1825 | } | |
1f8d882f | 1826 | else if (regno < FIRST_PSEUDO_REGISTER) |
1827 | for (class = 0; class < N_REG_CLASSES; class++) | |
1828 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
bb37f971 | 1829 | && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode)) |
2cff88c1 | 1830 | { |
1831 | if (reg_class_size[class] == 1) | |
1832 | op_costs[i].cost[class] = -1; | |
1833 | else | |
1834 | { | |
67d6c12b | 1835 | for (nr = 0; nr < (unsigned) hard_regno_nregs[regno][mode]; nr++) |
2cff88c1 | 1836 | { |
02e7a332 | 1837 | if (! TEST_HARD_REG_BIT (reg_class_contents[class], |
1838 | regno + nr)) | |
2cff88c1 | 1839 | break; |
1840 | } | |
1841 | ||
67d6c12b | 1842 | if (nr == (unsigned) hard_regno_nregs[regno][mode]) |
2cff88c1 | 1843 | op_costs[i].cost[class] = -1; |
1844 | } | |
1845 | } | |
1f8d882f | 1846 | } |
ae09e9a3 | 1847 | } |
4023cea7 | 1848 | \f |
7fd957fe | 1849 | /* Compute the cost of loading X into (if TO_P is nonzero) or from (if |
4023cea7 | 1850 | TO_P is zero) a register of class CLASS in mode MODE. |
1851 | ||
1852 | X must not be a pseudo. */ | |
1853 | ||
1854 | static int | |
4d58fa46 | 1855 | copy_cost (rtx x, enum machine_mode mode, enum reg_class class, int to_p, |
1856 | secondary_reload_info *prev_sri) | |
4023cea7 | 1857 | { |
1858 | enum reg_class secondary_class = NO_REGS; | |
4d58fa46 | 1859 | secondary_reload_info sri; |
4023cea7 | 1860 | |
1861 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1862 | assuming optimal allocation. */ | |
1863 | ||
1864 | if (GET_CODE (x) == SCRATCH) | |
1865 | return 0; | |
1866 | ||
1867 | /* Get the class we will actually use for a reload. */ | |
1868 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1869 | ||
4d58fa46 | 1870 | /* If we need a secondary reload for an intermediate, the |
4023cea7 | 1871 | cost is that to load the input into the intermediate register, then |
4d58fa46 | 1872 | to copy it. */ |
4023cea7 | 1873 | |
4d58fa46 | 1874 | sri.prev_sri = prev_sri; |
1875 | sri.extra_cost = 0; | |
1876 | secondary_class = targetm.secondary_reload (to_p, x, class, mode, &sri); | |
4023cea7 | 1877 | |
1878 | if (secondary_class != NO_REGS) | |
0ac516dc | 1879 | return (move_cost[mode][(int) secondary_class][(int) class] |
4d58fa46 | 1880 | + sri.extra_cost |
1881 | + copy_cost (x, mode, secondary_class, to_p, &sri)); | |
4023cea7 | 1882 | |
1883 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1884 | cost to move between the register classes, and use 2 for everything | |
1885 | else (constants). */ | |
1886 | ||
e16ceb8e | 1887 | if (MEM_P (x) || class == NO_REGS) |
4d58fa46 | 1888 | return sri.extra_cost + MEMORY_MOVE_COST (mode, class, to_p); |
ae09e9a3 | 1889 | |
8ad4c111 | 1890 | else if (REG_P (x)) |
4d58fa46 | 1891 | return (sri.extra_cost |
1892 | + move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]); | |
4023cea7 | 1893 | |
1894 | else | |
1895 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
4d58fa46 | 1896 | return sri.extra_cost + COSTS_N_INSNS (1); |
4023cea7 | 1897 | } |
1898 | \f | |
ae09e9a3 | 1899 | /* Record the pseudo registers we must reload into hard registers |
1900 | in a subexpression of a memory address, X. | |
4023cea7 | 1901 | |
1902 | CLASS is the class that the register needs to be in and is either | |
1903 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1904 | ||
1905 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1906 | can represent half-cost adjustments). */ | |
ae09e9a3 | 1907 | |
ade5541e | 1908 | static void |
3ad4992f | 1909 | record_address_regs (rtx x, enum reg_class class, int scale) |
ae09e9a3 | 1910 | { |
19cb6b50 | 1911 | enum rtx_code code = GET_CODE (x); |
ae09e9a3 | 1912 | |
1913 | switch (code) | |
1914 | { | |
1915 | case CONST_INT: | |
1916 | case CONST: | |
1917 | case CC0: | |
1918 | case PC: | |
1919 | case SYMBOL_REF: | |
1920 | case LABEL_REF: | |
1921 | return; | |
1922 | ||
1923 | case PLUS: | |
1924 | /* When we have an address that is a sum, | |
1925 | we must determine whether registers are "base" or "index" regs. | |
1926 | If there is a sum of two registers, we must choose one to be | |
e61a0a7f | 1927 | the "base". Luckily, we can use the REG_POINTER to make a good |
1928 | choice most of the time. We only need to do this on machines | |
1929 | that can have two registers in an address and where the base | |
1930 | and index register classes are different. | |
4023cea7 | 1931 | |
1932 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1933 | that seems bogus since it should only be set when we are sure | |
1934 | the register is being used as a pointer. */ | |
1935 | ||
ae09e9a3 | 1936 | { |
1937 | rtx arg0 = XEXP (x, 0); | |
1938 | rtx arg1 = XEXP (x, 1); | |
19cb6b50 | 1939 | enum rtx_code code0 = GET_CODE (arg0); |
1940 | enum rtx_code code1 = GET_CODE (arg1); | |
ae09e9a3 | 1941 | |
1942 | /* Look inside subregs. */ | |
4023cea7 | 1943 | if (code0 == SUBREG) |
ae09e9a3 | 1944 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
4023cea7 | 1945 | if (code1 == SUBREG) |
ae09e9a3 | 1946 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1947 | ||
4023cea7 | 1948 | /* If this machine only allows one register per address, it must |
1949 | be in the first operand. */ | |
1950 | ||
1951 | if (MAX_REGS_PER_ADDRESS == 1) | |
1952 | record_address_regs (arg0, class, scale); | |
1953 | ||
1954 | /* If index and base registers are the same on this machine, just | |
1955 | record registers in any non-constant operands. We assume here, | |
2617fe26 | 1956 | as well as in the tests below, that all addresses are in |
4023cea7 | 1957 | canonical form. */ |
1958 | ||
2e6d14e8 | 1959 | else if (INDEX_REG_CLASS == MODE_BASE_REG_CLASS (VOIDmode)) |
ae09e9a3 | 1960 | { |
4023cea7 | 1961 | record_address_regs (arg0, class, scale); |
1962 | if (! CONSTANT_P (arg1)) | |
1963 | record_address_regs (arg1, class, scale); | |
ae09e9a3 | 1964 | } |
4023cea7 | 1965 | |
1966 | /* If the second operand is a constant integer, it doesn't change | |
1967 | what class the first operand must be. */ | |
1968 | ||
1969 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
1970 | record_address_regs (arg0, class, scale); | |
1971 | ||
1972 | /* If the second operand is a symbolic constant, the first operand | |
1973 | must be an index register. */ | |
1974 | ||
1975 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
1976 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1977 | ||
ad87de1e | 1978 | /* If both operands are registers but one is already a hard register |
6006f9fd | 1979 | of index or reg-base class, give the other the class that the |
1980 | hard register is not. */ | |
ad87de1e | 1981 | |
1982 | else if (code0 == REG && code1 == REG | |
1983 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
6006f9fd | 1984 | && (REG_MODE_OK_FOR_REG_BASE_P (arg0, VOIDmode) |
1985 | || REG_OK_FOR_INDEX_P (arg0))) | |
ad87de1e | 1986 | record_address_regs (arg1, |
6006f9fd | 1987 | REG_MODE_OK_FOR_REG_BASE_P (arg0, VOIDmode) |
1988 | ? INDEX_REG_CLASS | |
1989 | : MODE_BASE_REG_REG_CLASS (VOIDmode), | |
ad87de1e | 1990 | scale); |
1991 | else if (code0 == REG && code1 == REG | |
1992 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
6006f9fd | 1993 | && (REG_MODE_OK_FOR_REG_BASE_P (arg1, VOIDmode) |
1994 | || REG_OK_FOR_INDEX_P (arg1))) | |
ad87de1e | 1995 | record_address_regs (arg0, |
6006f9fd | 1996 | REG_MODE_OK_FOR_REG_BASE_P (arg1, VOIDmode) |
1997 | ? INDEX_REG_CLASS | |
1998 | : MODE_BASE_REG_REG_CLASS (VOIDmode), | |
ad87de1e | 1999 | scale); |
2000 | ||
0dbd1c74 | 2001 | /* If one operand is known to be a pointer, it must be the base |
2002 | with the other operand the index. Likewise if the other operand | |
2003 | is a MULT. */ | |
b0f6c01a | 2004 | |
e61a0a7f | 2005 | else if ((code0 == REG && REG_POINTER (arg0)) |
0dbd1c74 | 2006 | || code1 == MULT) |
b0f6c01a | 2007 | { |
6006f9fd | 2008 | record_address_regs (arg0, MODE_BASE_REG_REG_CLASS (VOIDmode), |
2009 | scale); | |
b0f6c01a | 2010 | record_address_regs (arg1, INDEX_REG_CLASS, scale); |
2011 | } | |
e61a0a7f | 2012 | else if ((code1 == REG && REG_POINTER (arg1)) |
0dbd1c74 | 2013 | || code0 == MULT) |
b0f6c01a | 2014 | { |
2015 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
6006f9fd | 2016 | record_address_regs (arg1, MODE_BASE_REG_REG_CLASS (VOIDmode), |
2017 | scale); | |
b0f6c01a | 2018 | } |
2019 | ||
0dbd1c74 | 2020 | /* Otherwise, count equal chances that each might be a base |
4023cea7 | 2021 | or index register. This case should be rare. */ |
2022 | ||
0dbd1c74 | 2023 | else |
ae09e9a3 | 2024 | { |
6006f9fd | 2025 | record_address_regs (arg0, MODE_BASE_REG_REG_CLASS (VOIDmode), |
2e6d14e8 | 2026 | scale / 2); |
4023cea7 | 2027 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); |
6006f9fd | 2028 | record_address_regs (arg1, MODE_BASE_REG_REG_CLASS (VOIDmode), |
2e6d14e8 | 2029 | scale / 2); |
4023cea7 | 2030 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); |
ae09e9a3 | 2031 | } |
ae09e9a3 | 2032 | } |
2033 | break; | |
2034 | ||
40988080 | 2035 | /* Double the importance of a pseudo register that is incremented |
2036 | or decremented, since it would take two extra insns | |
2037 | if it ends up in the wrong place. */ | |
2038 | case POST_MODIFY: | |
2039 | case PRE_MODIFY: | |
2e6d14e8 | 2040 | record_address_regs (XEXP (x, 0), MODE_BASE_REG_CLASS (VOIDmode), |
2041 | 2 * scale); | |
40988080 | 2042 | if (REG_P (XEXP (XEXP (x, 1), 1))) |
2043 | record_address_regs (XEXP (XEXP (x, 1), 1), | |
2044 | INDEX_REG_CLASS, 2 * scale); | |
2045 | break; | |
2046 | ||
ae09e9a3 | 2047 | case POST_INC: |
2048 | case PRE_INC: | |
2049 | case POST_DEC: | |
2050 | case PRE_DEC: | |
2051 | /* Double the importance of a pseudo register that is incremented | |
2052 | or decremented, since it would take two extra insns | |
3d46a046 | 2053 | if it ends up in the wrong place. If the operand is a pseudo, |
2054 | show it is being used in an INC_DEC context. */ | |
2055 | ||
2056 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
8ad4c111 | 2057 | if (REG_P (XEXP (x, 0)) |
3d46a046 | 2058 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) |
2059 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
2060 | #endif | |
4023cea7 | 2061 | |
2062 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
ae09e9a3 | 2063 | break; |
2064 | ||
2065 | case REG: | |
2066 | { | |
19cb6b50 | 2067 | struct costs *pp = &costs[REGNO (x)]; |
2068 | int i; | |
ae09e9a3 | 2069 | |
3afef759 | 2070 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
ae09e9a3 | 2071 | |
4023cea7 | 2072 | for (i = 0; i < N_REG_CLASSES; i++) |
0ac516dc | 2073 | pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; |
ae09e9a3 | 2074 | } |
2075 | break; | |
2076 | ||
2077 | default: | |
2078 | { | |
19cb6b50 | 2079 | const char *fmt = GET_RTX_FORMAT (code); |
2080 | int i; | |
ae09e9a3 | 2081 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2082 | if (fmt[i] == 'e') | |
4023cea7 | 2083 | record_address_regs (XEXP (x, i), class, scale); |
ae09e9a3 | 2084 | } |
2085 | } | |
2086 | } | |
4ac7d2be | 2087 | \f |
2088 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
2089 | ||
2090 | /* Return 1 if REG is valid as an auto-increment memory reference | |
2091 | to an object of MODE. */ | |
2092 | ||
99c14947 | 2093 | static int |
3ad4992f | 2094 | auto_inc_dec_reg_p (rtx reg, enum machine_mode mode) |
4ac7d2be | 2095 | { |
e4e498cf | 2096 | if (HAVE_POST_INCREMENT |
2097 | && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) | |
4ac7d2be | 2098 | return 1; |
4ac7d2be | 2099 | |
e4e498cf | 2100 | if (HAVE_POST_DECREMENT |
2101 | && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) | |
4ac7d2be | 2102 | return 1; |
4ac7d2be | 2103 | |
e4e498cf | 2104 | if (HAVE_PRE_INCREMENT |
2105 | && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) | |
4ac7d2be | 2106 | return 1; |
4ac7d2be | 2107 | |
e4e498cf | 2108 | if (HAVE_PRE_DECREMENT |
2109 | && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) | |
4ac7d2be | 2110 | return 1; |
4ac7d2be | 2111 | |
2112 | return 0; | |
2113 | } | |
2114 | #endif | |
394685a4 | 2115 | \f |
f3fe93b0 | 2116 | static short *renumber; |
2117 | static size_t regno_allocated; | |
2118 | static unsigned int reg_n_max; | |
1e16645c | 2119 | |
394685a4 | 2120 | /* Allocate enough space to hold NUM_REGS registers for the tables used for |
2121 | reg_scan and flow_analysis that are indexed by the register number. If | |
c8515df4 | 2122 | NEW_P is nonzero, initialize all of the registers, otherwise only |
e5f994bf | 2123 | initialize the new registers allocated. The same table is kept from |
2124 | function to function, only reallocating it when we need more room. If | |
c8515df4 | 2125 | RENUMBER_P is nonzero, allocate the reg_renumber array also. */ |
394685a4 | 2126 | |
2127 | void | |
3ad4992f | 2128 | allocate_reg_info (size_t num_regs, int new_p, int renumber_p) |
394685a4 | 2129 | { |
d6ff8d83 | 2130 | size_t size_info; |
2131 | size_t size_renumber; | |
2132 | size_t min = (new_p) ? 0 : reg_n_max; | |
2133 | struct reg_info_data *reg_data; | |
e5f994bf | 2134 | |
394685a4 | 2135 | if (num_regs > regno_allocated) |
2136 | { | |
d6ff8d83 | 2137 | size_t old_allocated = regno_allocated; |
2138 | ||
b4b174c3 | 2139 | regno_allocated = num_regs + (num_regs / 20); /* Add some slop space. */ |
e5f994bf | 2140 | size_renumber = regno_allocated * sizeof (short); |
2141 | ||
2142 | if (!reg_n_info) | |
2143 | { | |
d6ff8d83 | 2144 | VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); |
f0af5a88 | 2145 | renumber = xmalloc (size_renumber); |
4c36ffe6 | 2146 | reg_pref_buffer = XNEWVEC (struct reg_pref, regno_allocated); |
e5f994bf | 2147 | } |
e5f994bf | 2148 | else |
2149 | { | |
d6ff8d83 | 2150 | VARRAY_GROW (reg_n_info, regno_allocated); |
2151 | ||
b4b174c3 | 2152 | if (new_p) /* If we're zapping everything, no need to realloc. */ |
d6ff8d83 | 2153 | { |
337d789b | 2154 | free ((char *) renumber); |
2155 | free ((char *) reg_pref); | |
f0af5a88 | 2156 | renumber = xmalloc (size_renumber); |
4c36ffe6 | 2157 | reg_pref_buffer = XNEWVEC (struct reg_pref, regno_allocated); |
d6ff8d83 | 2158 | } |
2159 | ||
2160 | else | |
2161 | { | |
f0af5a88 | 2162 | renumber = xrealloc (renumber, size_renumber); |
4c36ffe6 | 2163 | reg_pref_buffer = (struct reg_pref *) xrealloc (reg_pref_buffer, |
f0af5a88 | 2164 | regno_allocated |
2165 | * sizeof (struct reg_pref)); | |
d6ff8d83 | 2166 | } |
e5f994bf | 2167 | } |
d6ff8d83 | 2168 | |
2169 | size_info = (regno_allocated - old_allocated) * sizeof (reg_info) | |
2170 | + sizeof (struct reg_info_data) - sizeof (reg_info); | |
f0af5a88 | 2171 | reg_data = xcalloc (size_info, 1); |
d6ff8d83 | 2172 | reg_data->min_index = old_allocated; |
2173 | reg_data->max_index = regno_allocated - 1; | |
2174 | reg_data->next = reg_info_head; | |
2175 | reg_info_head = reg_data; | |
394685a4 | 2176 | } |
2177 | ||
d6ff8d83 | 2178 | reg_n_max = num_regs; |
394685a4 | 2179 | if (min < num_regs) |
2180 | { | |
d6ff8d83 | 2181 | /* Loop through each of the segments allocated for the actual |
2182 | reg_info pages, and set up the pointers, zero the pages, etc. */ | |
2617fe26 | 2183 | for (reg_data = reg_info_head; |
f3fe93b0 | 2184 | reg_data && reg_data->max_index >= min; |
2185 | reg_data = reg_data->next) | |
e5f994bf | 2186 | { |
d6ff8d83 | 2187 | size_t min_index = reg_data->min_index; |
2188 | size_t max_index = reg_data->max_index; | |
f3fe93b0 | 2189 | size_t max = MIN (max_index, num_regs); |
2190 | size_t local_min = min - min_index; | |
2191 | size_t i; | |
d6ff8d83 | 2192 | |
f3fe93b0 | 2193 | if (reg_data->min_index > num_regs) |
2194 | continue; | |
d6ff8d83 | 2195 | |
f3fe93b0 | 2196 | if (min < min_index) |
2197 | local_min = 0; | |
2198 | if (!reg_data->used_p) /* page just allocated with calloc */ | |
2199 | reg_data->used_p = 1; /* no need to zero */ | |
2200 | else | |
f0af5a88 | 2201 | memset (®_data->data[local_min], 0, |
2202 | sizeof (reg_info) * (max - min_index - local_min + 1)); | |
f3fe93b0 | 2203 | |
2204 | for (i = min_index+local_min; i <= max; i++) | |
2205 | { | |
2206 | VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; | |
2207 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
2208 | renumber[i] = -1; | |
2209 | reg_pref_buffer[i].prefclass = (char) NO_REGS; | |
2210 | reg_pref_buffer[i].altclass = (char) NO_REGS; | |
d6ff8d83 | 2211 | } |
e5f994bf | 2212 | } |
394685a4 | 2213 | } |
2214 | ||
d6ff8d83 | 2215 | /* If {pref,alt}class have already been allocated, update the pointers to |
2216 | the newly realloced ones. */ | |
ef776217 | 2217 | if (reg_pref) |
2218 | reg_pref = reg_pref_buffer; | |
d6ff8d83 | 2219 | |
e5f994bf | 2220 | if (renumber_p) |
2221 | reg_renumber = renumber; | |
394685a4 | 2222 | } |
2223 | ||
1e16645c | 2224 | /* Free up the space allocated by allocate_reg_info. */ |
2225 | void | |
3ad4992f | 2226 | free_reg_info (void) |
1e16645c | 2227 | { |
2228 | if (reg_n_info) | |
2229 | { | |
2230 | struct reg_info_data *reg_data; | |
2231 | struct reg_info_data *reg_next; | |
2232 | ||
2233 | VARRAY_FREE (reg_n_info); | |
2234 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
2235 | { | |
2236 | reg_next = reg_data->next; | |
337d789b | 2237 | free ((char *) reg_data); |
1e16645c | 2238 | } |
2239 | ||
ef776217 | 2240 | free (reg_pref_buffer); |
33181afc | 2241 | reg_pref_buffer = (struct reg_pref *) 0; |
2242 | reg_info_head = (struct reg_info_data *) 0; | |
2243 | renumber = (short *) 0; | |
1e16645c | 2244 | } |
2245 | regno_allocated = 0; | |
2246 | reg_n_max = 0; | |
2247 | } | |
ae09e9a3 | 2248 | \f |
2249 | /* This is the `regscan' pass of the compiler, run just before cse | |
2250 | and again just before loop. | |
2251 | ||
2252 | It finds the first and last use of each pseudo-register | |
2253 | and records them in the vectors regno_first_uid, regno_last_uid | |
2254 | and counts the number of sets in the vector reg_n_sets. | |
2255 | ||
2256 | REPEAT is nonzero the second time this is called. */ | |
2257 | ||
ae09e9a3 | 2258 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
155b92bf | 2259 | Always at least 3, since the combiner could put that many together |
9a504a44 | 2260 | and we want this to remain correct for all the remaining passes. |
2261 | This corresponds to the maximum number of times note_stores will call | |
2262 | a function for any insn. */ | |
ae09e9a3 | 2263 | |
2264 | int max_parallel; | |
2265 | ||
2617fe26 | 2266 | /* Used as a temporary to record the largest number of registers in |
9a504a44 | 2267 | PARALLEL in a SET_DEST. This is added to max_parallel. */ |
2268 | ||
2269 | static int max_set_parallel; | |
2270 | ||
ae09e9a3 | 2271 | void |
283a0d5c | 2272 | reg_scan (rtx f, unsigned int nregs) |
ae09e9a3 | 2273 | { |
19cb6b50 | 2274 | rtx insn; |
ae09e9a3 | 2275 | |
a66cff91 | 2276 | timevar_push (TV_REG_SCAN); |
2277 | ||
e5f994bf | 2278 | allocate_reg_info (nregs, TRUE, FALSE); |
ae09e9a3 | 2279 | max_parallel = 3; |
9a504a44 | 2280 | max_set_parallel = 0; |
ae09e9a3 | 2281 | |
2282 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
a66cff91 | 2283 | if (INSN_P (insn)) |
ae09e9a3 | 2284 | { |
a66cff91 | 2285 | rtx pat = PATTERN (insn); |
2286 | if (GET_CODE (pat) == PARALLEL | |
2287 | && XVECLEN (pat, 0) > max_parallel) | |
2288 | max_parallel = XVECLEN (pat, 0); | |
2289 | reg_scan_mark_refs (pat, insn, 0, 0); | |
25105766 | 2290 | |
2291 | if (REG_NOTES (insn)) | |
e4525dfe | 2292 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); |
2293 | } | |
9a504a44 | 2294 | |
2295 | max_parallel += max_set_parallel; | |
376c21d1 | 2296 | |
2297 | timevar_pop (TV_REG_SCAN); | |
e4525dfe | 2298 | } |
2299 | ||
2300 | /* Update 'regscan' information by looking at the insns | |
2301 | from FIRST to LAST. Some new REGs have been created, | |
2302 | and any REG with number greater than OLD_MAX_REGNO is | |
2303 | such a REG. We only update information for those. */ | |
2304 | ||
2305 | void | |
3ad4992f | 2306 | reg_scan_update (rtx first, rtx last, unsigned int old_max_regno) |
e4525dfe | 2307 | { |
19cb6b50 | 2308 | rtx insn; |
e4525dfe | 2309 | |
2310 | allocate_reg_info (max_reg_num (), FALSE, FALSE); | |
2311 | ||
2312 | for (insn = first; insn != last; insn = NEXT_INSN (insn)) | |
a66cff91 | 2313 | if (INSN_P (insn)) |
e4525dfe | 2314 | { |
a66cff91 | 2315 | rtx pat = PATTERN (insn); |
2316 | if (GET_CODE (pat) == PARALLEL | |
2317 | && XVECLEN (pat, 0) > max_parallel) | |
2318 | max_parallel = XVECLEN (pat, 0); | |
2319 | reg_scan_mark_refs (pat, insn, 0, old_max_regno); | |
e4525dfe | 2320 | |
2321 | if (REG_NOTES (insn)) | |
2322 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); | |
ae09e9a3 | 2323 | } |
2324 | } | |
2325 | ||
b1501a29 | 2326 | /* X is the expression to scan. INSN is the insn it appears in. |
e4525dfe | 2327 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. |
2328 | We should only record information for REGs with numbers | |
2329 | greater than or equal to MIN_REGNO. */ | |
b1501a29 | 2330 | |
4ac7d2be | 2331 | static void |
3ad4992f | 2332 | reg_scan_mark_refs (rtx x, rtx insn, int note_flag, unsigned int min_regno) |
ae09e9a3 | 2333 | { |
19cb6b50 | 2334 | enum rtx_code code; |
2335 | rtx dest; | |
2336 | rtx note; | |
ae09e9a3 | 2337 | |
cb5c5698 | 2338 | if (!x) |
2339 | return; | |
7968c331 | 2340 | code = GET_CODE (x); |
ae09e9a3 | 2341 | switch (code) |
2342 | { | |
ae09e9a3 | 2343 | case CONST: |
2c776a54 | 2344 | case CONST_INT: |
ae09e9a3 | 2345 | case CONST_DOUBLE: |
886cfd4f | 2346 | case CONST_VECTOR: |
ae09e9a3 | 2347 | case CC0: |
2348 | case PC: | |
2349 | case SYMBOL_REF: | |
2350 | case LABEL_REF: | |
2351 | case ADDR_VEC: | |
2352 | case ADDR_DIFF_VEC: | |
2353 | return; | |
2354 | ||
2355 | case REG: | |
2356 | { | |
02e7a332 | 2357 | unsigned int regno = REGNO (x); |
ae09e9a3 | 2358 | |
e4525dfe | 2359 | if (regno >= min_regno) |
2360 | { | |
e4525dfe | 2361 | if (!note_flag) |
2362 | REGNO_LAST_UID (regno) = INSN_UID (insn); | |
2363 | if (REGNO_FIRST_UID (regno) == 0) | |
2364 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
cb5c5698 | 2365 | /* If we are called by reg_scan_update() (indicated by min_regno |
2366 | being set), we also need to update the reference count. */ | |
2367 | if (min_regno) | |
2368 | REG_N_REFS (regno)++; | |
e4525dfe | 2369 | } |
ae09e9a3 | 2370 | } |
2371 | break; | |
2372 | ||
25105766 | 2373 | case EXPR_LIST: |
b4b9ba24 | 2374 | if (XEXP (x, 0)) |
e4525dfe | 2375 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); |
25105766 | 2376 | if (XEXP (x, 1)) |
e4525dfe | 2377 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
25105766 | 2378 | break; |
2379 | ||
2380 | case INSN_LIST: | |
2381 | if (XEXP (x, 1)) | |
e4525dfe | 2382 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
25105766 | 2383 | break; |
2384 | ||
cb5c5698 | 2385 | case CLOBBER: |
2386 | { | |
2387 | rtx reg = XEXP (x, 0); | |
2388 | if (REG_P (reg) | |
2389 | && REGNO (reg) >= min_regno) | |
2390 | { | |
2391 | REG_N_SETS (REGNO (reg))++; | |
2392 | REG_N_REFS (REGNO (reg))++; | |
2393 | } | |
e16ceb8e | 2394 | else if (MEM_P (reg)) |
39fd0bce | 2395 | reg_scan_mark_refs (XEXP (reg, 0), insn, note_flag, min_regno); |
cb5c5698 | 2396 | } |
2397 | break; | |
2398 | ||
ae09e9a3 | 2399 | case SET: |
2400 | /* Count a set of the destination if it is a register. */ | |
2401 | for (dest = SET_DEST (x); | |
2402 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2403 | || GET_CODE (dest) == ZERO_EXTEND; | |
2404 | dest = XEXP (dest, 0)) | |
2405 | ; | |
2406 | ||
9a504a44 | 2407 | /* For a PARALLEL, record the number of things (less the usual one for a |
2408 | SET) that are set. */ | |
2409 | if (GET_CODE (dest) == PARALLEL) | |
2410 | max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1); | |
2411 | ||
8ad4c111 | 2412 | if (REG_P (dest) |
e4525dfe | 2413 | && REGNO (dest) >= min_regno) |
e0d1ffe3 | 2414 | { |
2415 | REG_N_SETS (REGNO (dest))++; | |
2416 | REG_N_REFS (REGNO (dest))++; | |
2417 | } | |
ae09e9a3 | 2418 | |
bff0cb47 | 2419 | /* If this is setting a pseudo from another pseudo or the sum of a |
2420 | pseudo and a constant integer and the other pseudo is known to be | |
2421 | a pointer, set the destination to be a pointer as well. | |
2422 | ||
2423 | Likewise if it is setting the destination from an address or from a | |
2424 | value equivalent to an address or to the sum of an address and | |
2425 | something else. | |
2617fe26 | 2426 | |
bff0cb47 | 2427 | But don't do any of this if the pseudo corresponds to a user |
2428 | variable since it should have already been set as a pointer based | |
2429 | on the type. */ | |
2430 | ||
8ad4c111 | 2431 | if (REG_P (SET_DEST (x)) |
bff0cb47 | 2432 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER |
e4525dfe | 2433 | && REGNO (SET_DEST (x)) >= min_regno |
584afdda | 2434 | /* If the destination pseudo is set more than once, then other |
2435 | sets might not be to a pointer value (consider access to a | |
41a6f238 | 2436 | union in two threads of control in the presence of global |
e61a0a7f | 2437 | optimizations). So only set REG_POINTER on the destination |
584afdda | 2438 | pseudo if this is the only set of that pseudo. */ |
2439 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
bff0cb47 | 2440 | && ! REG_USERVAR_P (SET_DEST (x)) |
e61a0a7f | 2441 | && ! REG_POINTER (SET_DEST (x)) |
8ad4c111 | 2442 | && ((REG_P (SET_SRC (x)) |
e61a0a7f | 2443 | && REG_POINTER (SET_SRC (x))) |
bff0cb47 | 2444 | || ((GET_CODE (SET_SRC (x)) == PLUS |
2445 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2446 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
8ad4c111 | 2447 | && REG_P (XEXP (SET_SRC (x), 0)) |
e61a0a7f | 2448 | && REG_POINTER (XEXP (SET_SRC (x), 0))) |
bff0cb47 | 2449 | || GET_CODE (SET_SRC (x)) == CONST |
2450 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2451 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2452 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2453 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2454 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2455 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2456 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2457 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2458 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2459 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2460 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2461 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2462 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2463 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2464 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
e61a0a7f | 2465 | REG_POINTER (SET_DEST (x)) = 1; |
bff0cb47 | 2466 | |
fcdc122e | 2467 | /* If this is setting a register from a register or from a simple |
ca74b940 | 2468 | conversion of a register, propagate REG_EXPR. */ |
8ad4c111 | 2469 | if (REG_P (dest)) |
fcdc122e | 2470 | { |
2471 | rtx src = SET_SRC (x); | |
2472 | ||
2473 | while (GET_CODE (src) == SIGN_EXTEND | |
2474 | || GET_CODE (src) == ZERO_EXTEND | |
2475 | || GET_CODE (src) == TRUNCATE | |
2476 | || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))) | |
2477 | src = XEXP (src, 0); | |
2478 | ||
ca74b940 | 2479 | if (!REG_ATTRS (dest) && REG_P (src)) |
2480 | REG_ATTRS (dest) = REG_ATTRS (src); | |
e16ceb8e | 2481 | if (!REG_ATTRS (dest) && MEM_P (src)) |
ca74b940 | 2482 | set_reg_attrs_from_mem (dest, src); |
fcdc122e | 2483 | } |
2484 | ||
a92771b8 | 2485 | /* ... fall through ... */ |
ae09e9a3 | 2486 | |
2487 | default: | |
2488 | { | |
19cb6b50 | 2489 | const char *fmt = GET_RTX_FORMAT (code); |
2490 | int i; | |
ae09e9a3 | 2491 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
2492 | { | |
2493 | if (fmt[i] == 'e') | |
e4525dfe | 2494 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); |
ae09e9a3 | 2495 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2496 | { | |
19cb6b50 | 2497 | int j; |
ae09e9a3 | 2498 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
e4525dfe | 2499 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); |
ae09e9a3 | 2500 | } |
2501 | } | |
2502 | } | |
2503 | } | |
2504 | } | |
2505 | \f | |
2506 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2507 | is also in C2. */ | |
2508 | ||
2509 | int | |
3ad4992f | 2510 | reg_class_subset_p (enum reg_class c1, enum reg_class c2) |
ae09e9a3 | 2511 | { |
2512 | if (c1 == c2) return 1; | |
2513 | ||
2514 | if (c2 == ALL_REGS) | |
2515 | win: | |
2516 | return 1; | |
337d789b | 2517 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1], |
2518 | reg_class_contents[(int) c2], | |
ae09e9a3 | 2519 | win); |
2520 | return 0; | |
2521 | } | |
2522 | ||
2523 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2524 | ||
2525 | int | |
3ad4992f | 2526 | reg_classes_intersect_p (enum reg_class c1, enum reg_class c2) |
ae09e9a3 | 2527 | { |
a00f8533 | 2528 | HARD_REG_SET c; |
ae09e9a3 | 2529 | |
2530 | if (c1 == c2) return 1; | |
2531 | ||
2532 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2533 | return 1; | |
2534 | ||
2535 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2536 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2537 | ||
2538 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2539 | return 1; | |
2540 | ||
2541 | lose: | |
2542 | return 0; | |
2543 | } | |
2544 | ||
897118e8 | 2545 | #ifdef CANNOT_CHANGE_MODE_CLASS |
3dc77328 | 2546 | |
2547 | struct subregs_of_mode_node | |
2548 | { | |
2549 | unsigned int block; | |
2550 | unsigned char modes[MAX_MACHINE_MODE]; | |
2551 | }; | |
2552 | ||
2553 | static htab_t subregs_of_mode; | |
2554 | ||
2555 | static hashval_t | |
2556 | som_hash (const void *x) | |
2557 | { | |
2558 | const struct subregs_of_mode_node *a = x; | |
2559 | return a->block; | |
2560 | } | |
2561 | ||
2562 | static int | |
2563 | som_eq (const void *x, const void *y) | |
2564 | { | |
2565 | const struct subregs_of_mode_node *a = x; | |
2566 | const struct subregs_of_mode_node *b = y; | |
2567 | return a->block == b->block; | |
2568 | } | |
2569 | ||
2570 | void | |
2571 | init_subregs_of_mode (void) | |
2572 | { | |
2573 | if (subregs_of_mode) | |
2574 | htab_empty (subregs_of_mode); | |
2575 | else | |
2576 | subregs_of_mode = htab_create (100, som_hash, som_eq, free); | |
2577 | } | |
2578 | ||
2579 | void | |
2580 | record_subregs_of_mode (rtx subreg) | |
2581 | { | |
2582 | struct subregs_of_mode_node dummy, *node; | |
2583 | enum machine_mode mode; | |
2584 | unsigned int regno; | |
2585 | void **slot; | |
2586 | ||
2587 | if (!REG_P (SUBREG_REG (subreg))) | |
2588 | return; | |
2589 | ||
2590 | regno = REGNO (SUBREG_REG (subreg)); | |
2591 | mode = GET_MODE (subreg); | |
2592 | ||
2593 | if (regno < FIRST_PSEUDO_REGISTER) | |
2594 | return; | |
2595 | ||
2596 | dummy.block = regno & -8; | |
2597 | slot = htab_find_slot_with_hash (subregs_of_mode, &dummy, | |
2598 | dummy.block, INSERT); | |
2599 | node = *slot; | |
2600 | if (node == NULL) | |
2601 | { | |
4c36ffe6 | 2602 | node = XCNEW (struct subregs_of_mode_node); |
3dc77328 | 2603 | node->block = regno & -8; |
2604 | *slot = node; | |
2605 | } | |
2606 | ||
2607 | node->modes[mode] |= 1 << (regno & 7); | |
2608 | } | |
2609 | ||
897118e8 | 2610 | /* Set bits in *USED which correspond to registers which can't change |
2611 | their mode from FROM to any mode in which REGNO was encountered. */ | |
2612 | ||
2613 | void | |
3ad4992f | 2614 | cannot_change_mode_set_regs (HARD_REG_SET *used, enum machine_mode from, |
2615 | unsigned int regno) | |
897118e8 | 2616 | { |
3dc77328 | 2617 | struct subregs_of_mode_node dummy, *node; |
897118e8 | 2618 | enum machine_mode to; |
3dc77328 | 2619 | unsigned char mask; |
2620 | unsigned int i; | |
897118e8 | 2621 | |
3dc77328 | 2622 | dummy.block = regno & -8; |
2623 | node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block); | |
2624 | if (node == NULL) | |
2625 | return; | |
2626 | ||
2627 | mask = 1 << (regno & 7); | |
2628 | for (to = VOIDmode; to < NUM_MACHINE_MODES; to++) | |
2629 | if (node->modes[to] & mask) | |
2630 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2631 | if (!TEST_HARD_REG_BIT (*used, i) | |
2632 | && REG_CANNOT_CHANGE_MODE_P (i, from, to)) | |
2633 | SET_HARD_REG_BIT (*used, i); | |
897118e8 | 2634 | } |
2635 | ||
2636 | /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM | |
2637 | mode. */ | |
2638 | ||
2639 | bool | |
3ad4992f | 2640 | invalid_mode_change_p (unsigned int regno, enum reg_class class, |
3dc77328 | 2641 | enum machine_mode from) |
897118e8 | 2642 | { |
3dc77328 | 2643 | struct subregs_of_mode_node dummy, *node; |
2644 | enum machine_mode to; | |
2645 | unsigned char mask; | |
2646 | ||
2647 | dummy.block = regno & -8; | |
2648 | node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block); | |
2649 | if (node == NULL) | |
2650 | return false; | |
2651 | ||
2652 | mask = 1 << (regno & 7); | |
2653 | for (to = VOIDmode; to < NUM_MACHINE_MODES; to++) | |
2654 | if (node->modes[to] & mask) | |
2655 | if (CANNOT_CHANGE_MODE_CLASS (from, to, class)) | |
2656 | return true; | |
2657 | ||
2658 | return false; | |
897118e8 | 2659 | } |
2660 | #endif /* CANNOT_CHANGE_MODE_CLASS */ | |
2661 | ||
1f3233d1 | 2662 | #include "gt-regclass.h" |