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54dac99e | 1 | /* Compute register class preferences for pseudo-registers. |
29a82058 | 2 | Copyright (C) 1987, 88, 91-97, 1998 Free Software Foundation, Inc. |
54dac99e RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
54dac99e RK |
20 | |
21 | ||
22 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
23 | It also defines some tables of information about the hardware registers | |
24 | and a function init_reg_sets to initialize the tables. */ | |
25 | ||
26 | #include "config.h" | |
670ee920 | 27 | #include "system.h" |
54dac99e RK |
28 | #include "rtl.h" |
29 | #include "hard-reg-set.h" | |
30 | #include "flags.h" | |
31 | #include "basic-block.h" | |
32 | #include "regs.h" | |
33 | #include "insn-config.h" | |
34 | #include "recog.h" | |
e4600702 RK |
35 | #include "reload.h" |
36 | #include "real.h" | |
10f0ad3d | 37 | #include "toplev.h" |
d6f4ec51 | 38 | #include "output.h" |
54dac99e RK |
39 | |
40 | #ifndef REGISTER_MOVE_COST | |
41 | #define REGISTER_MOVE_COST(x, y) 2 | |
42 | #endif | |
43 | ||
533d0835 RK |
44 | /* If we have auto-increment or auto-decrement and we can have secondary |
45 | reloads, we are not allowed to use classes requiring secondary | |
9faa82d8 | 46 | reloads for pseudos auto-incremented since reload can't handle it. */ |
533d0835 RK |
47 | |
48 | #ifdef AUTO_INC_DEC | |
dd9f0e8f | 49 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) |
533d0835 RK |
50 | #define FORBIDDEN_INC_DEC_CLASSES |
51 | #endif | |
52 | #endif | |
54dac99e RK |
53 | \f |
54 | /* Register tables used by many passes. */ | |
55 | ||
56 | /* Indexed by hard register number, contains 1 for registers | |
57 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
58 | These are the registers that cannot be used to allocate | |
252f342a | 59 | a pseudo reg for general use. */ |
54dac99e RK |
60 | |
61 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
62 | ||
63 | /* Same info as a HARD_REG_SET. */ | |
64 | ||
65 | HARD_REG_SET fixed_reg_set; | |
66 | ||
67 | /* Data for initializing the above. */ | |
68 | ||
69 | static char initial_fixed_regs[] = FIXED_REGISTERS; | |
70 | ||
71 | /* Indexed by hard register number, contains 1 for registers | |
72 | that are fixed use or are clobbered by function calls. | |
73 | These are the registers that cannot be used to allocate | |
252f342a MH |
74 | a pseudo reg whose life crosses calls unless we are able |
75 | to save/restore them across the calls. */ | |
54dac99e RK |
76 | |
77 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
78 | ||
79 | /* Same info as a HARD_REG_SET. */ | |
80 | ||
81 | HARD_REG_SET call_used_reg_set; | |
82 | ||
6cad67d2 JL |
83 | /* HARD_REG_SET of registers we want to avoid caller saving. */ |
84 | HARD_REG_SET losing_caller_save_reg_set; | |
85 | ||
54dac99e RK |
86 | /* Data for initializing the above. */ |
87 | ||
88 | static char initial_call_used_regs[] = CALL_USED_REGISTERS; | |
89 | ||
90 | /* Indexed by hard register number, contains 1 for registers that are | |
252f342a MH |
91 | fixed use or call used registers that cannot hold quantities across |
92 | calls even if we are willing to save and restore them. call fixed | |
93 | registers are a subset of call used registers. */ | |
54dac99e RK |
94 | |
95 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
96 | ||
97 | /* The same info as a HARD_REG_SET. */ | |
98 | ||
99 | HARD_REG_SET call_fixed_reg_set; | |
100 | ||
101 | /* Number of non-fixed registers. */ | |
102 | ||
103 | int n_non_fixed_regs; | |
104 | ||
105 | /* Indexed by hard register number, contains 1 for registers | |
106 | that are being used for global register decls. | |
107 | These must be exempt from ordinary flow analysis | |
108 | and are also considered fixed. */ | |
109 | ||
110 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
111 | ||
112 | /* Table of register numbers in the order in which to try to use them. */ | |
113 | #ifdef REG_ALLOC_ORDER | |
114 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
115 | #endif | |
116 | ||
117 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
118 | ||
2e0e2b76 CH |
119 | HARD_REG_SET reg_class_contents[N_REG_CLASSES]; |
120 | ||
089e575b RS |
121 | /* The same information, but as an array of unsigned ints. We copy from |
122 | these unsigned ints to the table above. We do this so the tm.h files | |
123 | do not have to be aware of the wordsize for machines with <= 64 regs. */ | |
2e0e2b76 CH |
124 | |
125 | #define N_REG_INTS \ | |
126 | ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) | |
127 | ||
089e575b | 128 | static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] |
2e0e2b76 | 129 | = REG_CLASS_CONTENTS; |
54dac99e RK |
130 | |
131 | /* For each reg class, number of regs it contains. */ | |
132 | ||
133 | int reg_class_size[N_REG_CLASSES]; | |
134 | ||
135 | /* For each reg class, table listing all the containing classes. */ | |
136 | ||
137 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
138 | ||
139 | /* For each reg class, table listing all the classes contained in it. */ | |
140 | ||
141 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
142 | ||
143 | /* For each pair of reg classes, | |
144 | a largest reg class contained in their union. */ | |
145 | ||
146 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
147 | ||
148 | /* For each pair of reg classes, | |
149 | the smallest reg class containing their union. */ | |
150 | ||
151 | enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
152 | ||
d05c8ee7 RS |
153 | /* Array containing all of the register names */ |
154 | ||
155 | char *reg_names[] = REGISTER_NAMES; | |
156 | ||
ca4aac00 DE |
157 | /* For each hard register, the widest mode object that it can contain. |
158 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
159 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
160 | register. */ | |
161 | ||
162 | enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; | |
163 | ||
e4600702 RK |
164 | /* Maximum cost of moving from a register in one class to a register in |
165 | another class. Based on REGISTER_MOVE_COST. */ | |
166 | ||
167 | static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
168 | ||
169 | /* Similar, but here we don't have to move if the first index is a subset | |
170 | of the second so in that case the cost is zero. */ | |
171 | ||
172 | static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
173 | ||
533d0835 RK |
174 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
175 | ||
176 | /* These are the classes that regs which are auto-incremented or decremented | |
177 | cannot be put in. */ | |
178 | ||
179 | static int forbidden_inc_dec_class[N_REG_CLASSES]; | |
180 | ||
181 | /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec | |
182 | context. */ | |
183 | ||
184 | static char *in_inc_dec; | |
185 | ||
5fcb671c | 186 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
533d0835 | 187 | |
473fe49b KR |
188 | #ifdef HAVE_SECONDARY_RELOADS |
189 | ||
190 | /* Sample MEM values for use by memory_move_secondary_cost. */ | |
191 | ||
192 | static rtx top_of_stack[MAX_MACHINE_MODE]; | |
193 | ||
194 | #endif /* HAVE_SECONDARY_RELOADS */ | |
195 | ||
6feacd09 MM |
196 | /* Linked list of reg_info structures allocated for reg_n_info array. |
197 | Grouping all of the allocated structures together in one lump | |
198 | means only one call to bzero to clear them, rather than n smaller | |
199 | calls. */ | |
200 | struct reg_info_data { | |
201 | struct reg_info_data *next; /* next set of reg_info structures */ | |
202 | size_t min_index; /* minimum index # */ | |
203 | size_t max_index; /* maximum index # */ | |
204 | char used_p; /* non-zero if this has been used previously */ | |
205 | reg_info data[1]; /* beginning of the reg_info data */ | |
206 | }; | |
207 | ||
208 | static struct reg_info_data *reg_info_head; | |
209 | ||
210 | ||
54dac99e RK |
211 | /* Function called only once to initialize the above data on reg usage. |
212 | Once this is done, various switches may override. */ | |
213 | ||
214 | void | |
215 | init_reg_sets () | |
216 | { | |
217 | register int i, j; | |
218 | ||
2e0e2b76 CH |
219 | /* First copy the register information from the initial int form into |
220 | the regsets. */ | |
221 | ||
222 | for (i = 0; i < N_REG_CLASSES; i++) | |
223 | { | |
224 | CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
225 | ||
226 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
227 | if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] | |
089e575b | 228 | & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) |
2e0e2b76 CH |
229 | SET_HARD_REG_BIT (reg_class_contents[i], j); |
230 | } | |
231 | ||
54dac99e RK |
232 | bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); |
233 | bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); | |
234 | bzero (global_regs, sizeof global_regs); | |
235 | ||
236 | /* Compute number of hard regs in each class. */ | |
237 | ||
4c9a05bc | 238 | bzero ((char *) reg_class_size, sizeof reg_class_size); |
54dac99e RK |
239 | for (i = 0; i < N_REG_CLASSES; i++) |
240 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
241 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
242 | reg_class_size[i]++; | |
243 | ||
244 | /* Initialize the table of subunions. | |
245 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
246 | that is contained in the union of classes I and J. */ | |
247 | ||
248 | for (i = 0; i < N_REG_CLASSES; i++) | |
249 | { | |
250 | for (j = 0; j < N_REG_CLASSES; j++) | |
251 | { | |
252 | #ifdef HARD_REG_SET | |
253 | register /* Declare it register if it's a scalar. */ | |
254 | #endif | |
255 | HARD_REG_SET c; | |
256 | register int k; | |
257 | ||
258 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
259 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
260 | for (k = 0; k < N_REG_CLASSES; k++) | |
261 | { | |
262 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
263 | subclass1); | |
264 | continue; | |
265 | ||
266 | subclass1: | |
267 | /* keep the largest subclass */ /* SPEE 900308 */ | |
268 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], | |
269 | reg_class_contents[(int) reg_class_subunion[i][j]], | |
270 | subclass2); | |
271 | reg_class_subunion[i][j] = (enum reg_class) k; | |
272 | subclass2: | |
273 | ; | |
274 | } | |
275 | } | |
276 | } | |
277 | ||
278 | /* Initialize the table of superunions. | |
279 | reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
280 | containing the union of classes I and J. */ | |
281 | ||
282 | for (i = 0; i < N_REG_CLASSES; i++) | |
283 | { | |
284 | for (j = 0; j < N_REG_CLASSES; j++) | |
285 | { | |
286 | #ifdef HARD_REG_SET | |
287 | register /* Declare it register if it's a scalar. */ | |
288 | #endif | |
289 | HARD_REG_SET c; | |
290 | register int k; | |
291 | ||
292 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
293 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
294 | for (k = 0; k < N_REG_CLASSES; k++) | |
295 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); | |
296 | ||
297 | superclass: | |
298 | reg_class_superunion[i][j] = (enum reg_class) k; | |
299 | } | |
300 | } | |
301 | ||
302 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
303 | First clear the whole table, then add the elements as they are found. */ | |
304 | ||
305 | for (i = 0; i < N_REG_CLASSES; i++) | |
306 | { | |
307 | for (j = 0; j < N_REG_CLASSES; j++) | |
308 | { | |
309 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
310 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
311 | } | |
312 | } | |
313 | ||
314 | for (i = 0; i < N_REG_CLASSES; i++) | |
315 | { | |
316 | if (i == (int) NO_REGS) | |
317 | continue; | |
318 | ||
319 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
320 | { | |
321 | enum reg_class *p; | |
322 | ||
323 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
324 | subclass); | |
325 | continue; | |
326 | subclass: | |
327 | /* Reg class I is a subclass of J. | |
328 | Add J to the table of superclasses of I. */ | |
329 | p = ®_class_superclasses[i][0]; | |
330 | while (*p != LIM_REG_CLASSES) p++; | |
331 | *p = (enum reg_class) j; | |
332 | /* Add I to the table of superclasses of J. */ | |
333 | p = ®_class_subclasses[j][0]; | |
334 | while (*p != LIM_REG_CLASSES) p++; | |
335 | *p = (enum reg_class) i; | |
336 | } | |
337 | } | |
e4600702 | 338 | |
73b76448 RK |
339 | /* Do any additional initialization regsets may need */ |
340 | INIT_ONCE_REG_SET (); | |
54dac99e RK |
341 | } |
342 | ||
343 | /* After switches have been processed, which perhaps alter | |
344 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
345 | ||
c27c5281 | 346 | static void |
54dac99e RK |
347 | init_reg_sets_1 () |
348 | { | |
f8344bea | 349 | register unsigned int i, j; |
54dac99e RK |
350 | |
351 | /* This macro allows the fixed or call-used registers | |
352 | to depend on target flags. */ | |
353 | ||
354 | #ifdef CONDITIONAL_REGISTER_USAGE | |
355 | CONDITIONAL_REGISTER_USAGE; | |
356 | #endif | |
357 | ||
54dac99e RK |
358 | /* Initialize "constant" tables. */ |
359 | ||
360 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
361 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
362 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
363 | ||
364 | bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); | |
54dac99e RK |
365 | |
366 | n_non_fixed_regs = 0; | |
367 | ||
368 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
369 | { | |
54dac99e RK |
370 | if (fixed_regs[i]) |
371 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
372 | else | |
373 | n_non_fixed_regs++; | |
374 | ||
375 | if (call_used_regs[i]) | |
376 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
377 | if (call_fixed_regs[i]) | |
378 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
6cad67d2 JL |
379 | if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) |
380 | SET_HARD_REG_BIT (losing_caller_save_reg_set, i); | |
54dac99e | 381 | } |
acbce667 KR |
382 | |
383 | /* Initialize the move cost table. Find every subset of each class | |
384 | and take the maximum cost of moving any subset to any other. */ | |
385 | ||
386 | for (i = 0; i < N_REG_CLASSES; i++) | |
387 | for (j = 0; j < N_REG_CLASSES; j++) | |
388 | { | |
389 | int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); | |
390 | enum reg_class *p1, *p2; | |
391 | ||
392 | for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) | |
393 | if (*p2 != i) | |
394 | cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); | |
395 | ||
396 | for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) | |
397 | { | |
398 | if (*p1 != j) | |
399 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); | |
400 | ||
401 | for (p2 = ®_class_subclasses[j][0]; | |
402 | *p2 != LIM_REG_CLASSES; p2++) | |
403 | if (*p1 != *p2) | |
404 | cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); | |
405 | } | |
406 | ||
407 | move_cost[i][j] = cost; | |
408 | ||
409 | if (reg_class_subset_p (i, j)) | |
410 | cost = 0; | |
411 | ||
412 | may_move_cost[i][j] = cost; | |
413 | } | |
c27c5281 DE |
414 | } |
415 | ||
416 | /* Compute the table of register modes. | |
417 | These values are used to record death information for individual registers | |
418 | (as opposed to a multi-register mode). */ | |
ca4aac00 | 419 | |
c27c5281 DE |
420 | static void |
421 | init_reg_modes () | |
422 | { | |
423 | register int i; | |
ca4aac00 DE |
424 | |
425 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7f21d440 DE |
426 | { |
427 | reg_raw_mode[i] = choose_hard_reg_mode (i, 1); | |
428 | ||
066c2fea | 429 | /* If we couldn't find a valid mode, just use the previous mode. |
7f21d440 DE |
430 | ??? One situation in which we need to do this is on the mips where |
431 | HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like | |
432 | to use DF mode for the even registers and VOIDmode for the odd | |
9faa82d8 | 433 | (for the cpu models where the odd ones are inaccessible). */ |
7f21d440 | 434 | if (reg_raw_mode[i] == VOIDmode) |
066c2fea | 435 | reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; |
7f21d440 | 436 | } |
ca4aac00 DE |
437 | } |
438 | ||
c27c5281 DE |
439 | /* Finish initializing the register sets and |
440 | initialize the register modes. */ | |
441 | ||
442 | void | |
443 | init_regs () | |
444 | { | |
445 | /* This finishes what was started by init_reg_sets, but couldn't be done | |
446 | until after register usage was specified. */ | |
b93a436e | 447 | init_reg_sets_1 (); |
c27c5281 DE |
448 | |
449 | init_reg_modes (); | |
473fe49b KR |
450 | |
451 | #ifdef HAVE_SECONDARY_RELOADS | |
452 | { | |
453 | /* Make some fake stack-frame MEM references for use in | |
454 | memory_move_secondary_cost. */ | |
455 | int i; | |
456 | for (i = 0; i < MAX_MACHINE_MODE; i++) | |
9ec36da5 | 457 | top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); |
473fe49b KR |
458 | } |
459 | #endif | |
c27c5281 DE |
460 | } |
461 | ||
cbd5b9a2 | 462 | #ifdef HAVE_SECONDARY_RELOADS |
473fe49b | 463 | |
cbd5b9a2 KR |
464 | /* Compute extra cost of moving registers to/from memory due to reloads. |
465 | Only needed if secondary reloads are required for memory moves. */ | |
473fe49b | 466 | |
cbd5b9a2 KR |
467 | int |
468 | memory_move_secondary_cost (mode, class, in) | |
469 | enum machine_mode mode; | |
470 | enum reg_class class; | |
471 | int in; | |
472 | { | |
473 | enum reg_class altclass; | |
474 | int partial_cost = 0; | |
cbd5b9a2 | 475 | /* We need a memory reference to feed to SECONDARY... macros. */ |
473fe49b | 476 | rtx mem = top_of_stack[(int) mode]; |
cbd5b9a2 KR |
477 | |
478 | if (in) | |
473fe49b | 479 | { |
321c0828 | 480 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
473fe49b | 481 | altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 482 | #else |
473fe49b | 483 | altclass = NO_REGS; |
321c0828 | 484 | #endif |
473fe49b | 485 | } |
cbd5b9a2 | 486 | else |
473fe49b | 487 | { |
321c0828 | 488 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
473fe49b | 489 | altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); |
321c0828 | 490 | #else |
473fe49b | 491 | altclass = NO_REGS; |
321c0828 | 492 | #endif |
473fe49b KR |
493 | } |
494 | ||
cbd5b9a2 KR |
495 | if (altclass == NO_REGS) |
496 | return 0; | |
497 | ||
498 | if (in) | |
499 | partial_cost = REGISTER_MOVE_COST (altclass, class); | |
500 | else | |
501 | partial_cost = REGISTER_MOVE_COST (class, altclass); | |
502 | ||
503 | if (class == altclass) | |
504 | /* This isn't simply a copy-to-temporary situation. Can't guess | |
505 | what it is, so MEMORY_MOVE_COST really ought not to be calling | |
506 | here in that case. | |
507 | ||
508 | I'm tempted to put in an abort here, but returning this will | |
509 | probably only give poor estimates, which is what we would've | |
510 | had before this code anyways. */ | |
511 | return partial_cost; | |
512 | ||
513 | /* Check if the secondary reload register will also need a | |
514 | secondary reload. */ | |
515 | return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
516 | } | |
517 | #endif | |
518 | ||
ca4aac00 DE |
519 | /* Return a machine mode that is legitimate for hard reg REGNO and large |
520 | enough to save nregs. If we can't find one, return VOIDmode. */ | |
521 | ||
522 | enum machine_mode | |
523 | choose_hard_reg_mode (regno, nregs) | |
524 | int regno; | |
525 | int nregs; | |
526 | { | |
527 | enum machine_mode found_mode = VOIDmode, mode; | |
528 | ||
529 | /* We first look for the largest integer mode that can be validly | |
530 | held in REGNO. If none, we look for the largest floating-point mode. | |
531 | If we still didn't find a valid mode, try CCmode. */ | |
532 | ||
533 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
534 | mode != VOIDmode; | |
535 | mode = GET_MODE_WIDER_MODE (mode)) | |
536 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
537 | && HARD_REGNO_MODE_OK (regno, mode)) | |
538 | found_mode = mode; | |
539 | ||
540 | if (found_mode != VOIDmode) | |
541 | return found_mode; | |
542 | ||
543 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); | |
544 | mode != VOIDmode; | |
545 | mode = GET_MODE_WIDER_MODE (mode)) | |
546 | if (HARD_REGNO_NREGS (regno, mode) == nregs | |
547 | && HARD_REGNO_MODE_OK (regno, mode)) | |
548 | found_mode = mode; | |
549 | ||
550 | if (found_mode != VOIDmode) | |
551 | return found_mode; | |
552 | ||
553 | if (HARD_REGNO_NREGS (regno, CCmode) == nregs | |
554 | && HARD_REGNO_MODE_OK (regno, CCmode)) | |
555 | return CCmode; | |
556 | ||
557 | /* We can't find a mode valid for this register. */ | |
558 | return VOIDmode; | |
54dac99e RK |
559 | } |
560 | ||
561 | /* Specify the usage characteristics of the register named NAME. | |
562 | It should be a fixed register if FIXED and a | |
563 | call-used register if CALL_USED. */ | |
564 | ||
565 | void | |
566 | fix_register (name, fixed, call_used) | |
567 | char *name; | |
568 | int fixed, call_used; | |
569 | { | |
570 | int i; | |
571 | ||
572 | /* Decode the name and update the primary form of | |
573 | the register info. */ | |
574 | ||
e5c90c23 TW |
575 | if ((i = decode_reg_name (name)) >= 0) |
576 | { | |
577 | fixed_regs[i] = fixed; | |
578 | call_used_regs[i] = call_used; | |
579 | } | |
580 | else | |
54dac99e RK |
581 | { |
582 | warning ("unknown register name: %s", name); | |
54dac99e RK |
583 | } |
584 | } | |
614f68e2 RK |
585 | |
586 | /* Mark register number I as global. */ | |
587 | ||
588 | void | |
589 | globalize_reg (i) | |
590 | int i; | |
591 | { | |
592 | if (global_regs[i]) | |
593 | { | |
594 | warning ("register used for two global register variables"); | |
595 | return; | |
596 | } | |
597 | ||
598 | if (call_used_regs[i] && ! fixed_regs[i]) | |
599 | warning ("call-clobbered register used for global register variable"); | |
600 | ||
601 | global_regs[i] = 1; | |
602 | ||
603 | /* If already fixed, nothing else to do. */ | |
604 | if (fixed_regs[i]) | |
605 | return; | |
606 | ||
607 | fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; | |
608 | n_non_fixed_regs--; | |
609 | ||
610 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
611 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
612 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
613 | } | |
54dac99e RK |
614 | \f |
615 | /* Now the data and code for the `regclass' pass, which happens | |
616 | just before local-alloc. */ | |
617 | ||
e4600702 RK |
618 | /* The `costs' struct records the cost of using a hard register of each class |
619 | and of using memory for each pseudo. We use this data to set up | |
620 | register class preferences. */ | |
54dac99e | 621 | |
e4600702 | 622 | struct costs |
54dac99e | 623 | { |
e4600702 RK |
624 | int cost[N_REG_CLASSES]; |
625 | int mem_cost; | |
54dac99e RK |
626 | }; |
627 | ||
e4600702 RK |
628 | /* Record the cost of each class for each pseudo. */ |
629 | ||
630 | static struct costs *costs; | |
631 | ||
632 | /* Record the same data by operand number, accumulated for each alternative | |
633 | in an insn. The contribution to a pseudo is that of the minimum-cost | |
634 | alternative. */ | |
635 | ||
636 | static struct costs op_costs[MAX_RECOG_OPERANDS]; | |
54dac99e RK |
637 | |
638 | /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. | |
639 | This is available after `regclass' is run. */ | |
640 | ||
641 | static char *prefclass; | |
642 | ||
54d23420 RK |
643 | /* altclass[R] is a register class that we should use for allocating |
644 | pseudo number R if no register in the preferred class is available. | |
645 | If no register in this class is available, memory is preferred. | |
646 | ||
647 | It might appear to be more general to have a bitmask of classes here, | |
648 | but since it is recommended that there be a class corresponding to the | |
649 | union of most major pair of classes, that generality is not required. | |
650 | ||
54dac99e RK |
651 | This is available after `regclass' is run. */ |
652 | ||
54d23420 | 653 | static char *altclass; |
54dac99e | 654 | |
6feacd09 MM |
655 | /* Allocated buffers for prefclass and altclass. */ |
656 | static char *prefclass_buffer; | |
657 | static char *altclass_buffer; | |
658 | ||
54d23420 | 659 | /* Record the depth of loops that we are in. */ |
54dac99e RK |
660 | |
661 | static int loop_depth; | |
662 | ||
54d23420 RK |
663 | /* Account for the fact that insns within a loop are executed very commonly, |
664 | but don't keep doing this as loops go too deep. */ | |
665 | ||
666 | static int loop_cost; | |
667 | ||
08d95f91 RK |
668 | static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *, |
669 | char **, rtx)); | |
670 | static int copy_cost PROTO((rtx, enum machine_mode, | |
671 | enum reg_class, int)); | |
672 | static void record_address_regs PROTO((rtx, enum reg_class, int)); | |
1d300e19 KG |
673 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
674 | static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode)); | |
675 | #endif | |
f903b91f | 676 | static void reg_scan_mark_refs PROTO((rtx, rtx, int, int)); |
54dac99e RK |
677 | |
678 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
679 | This function is sometimes called before the info has been computed. | |
680 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
681 | ||
682 | enum reg_class | |
683 | reg_preferred_class (regno) | |
684 | int regno; | |
685 | { | |
686 | if (prefclass == 0) | |
687 | return GENERAL_REGS; | |
688 | return (enum reg_class) prefclass[regno]; | |
689 | } | |
690 | ||
e4600702 RK |
691 | enum reg_class |
692 | reg_alternate_class (regno) | |
b729186a | 693 | int regno; |
54dac99e RK |
694 | { |
695 | if (prefclass == 0) | |
e4600702 RK |
696 | return ALL_REGS; |
697 | ||
698 | return (enum reg_class) altclass[regno]; | |
54dac99e RK |
699 | } |
700 | ||
701 | /* This prevents dump_flow_info from losing if called | |
702 | before regclass is run. */ | |
703 | ||
704 | void | |
705 | regclass_init () | |
706 | { | |
707 | prefclass = 0; | |
708 | } | |
709 | \f | |
710 | /* This is a pass of the compiler that scans all instructions | |
711 | and calculates the preferred class for each pseudo-register. | |
712 | This information can be accessed later by calling `reg_preferred_class'. | |
713 | This pass comes just before local register allocation. */ | |
714 | ||
715 | void | |
716 | regclass (f, nregs) | |
717 | rtx f; | |
718 | int nregs; | |
719 | { | |
720 | #ifdef REGISTER_CONSTRAINTS | |
721 | register rtx insn; | |
e4600702 RK |
722 | register int i, j; |
723 | struct costs init_cost; | |
724 | rtx set; | |
725 | int pass; | |
54dac99e RK |
726 | |
727 | init_recog (); | |
728 | ||
56a65848 | 729 | costs = (struct costs *) xmalloc (nregs * sizeof (struct costs)); |
533d0835 RK |
730 | |
731 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
732 | ||
733 | in_inc_dec = (char *) alloca (nregs); | |
734 | ||
735 | /* Initialize information about which register classes can be used for | |
736 | pseudos that are auto-incremented or auto-decremented. It would | |
737 | seem better to put this in init_reg_sets, but we need to be able | |
738 | to allocate rtx, which we can't do that early. */ | |
739 | ||
740 | for (i = 0; i < N_REG_CLASSES; i++) | |
741 | { | |
38a448ca | 742 | rtx r = gen_rtx_REG (VOIDmode, 0); |
533d0835 RK |
743 | enum machine_mode m; |
744 | ||
745 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
746 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
747 | { | |
748 | REGNO (r) = j; | |
749 | ||
750 | for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; | |
808043ed | 751 | m = (enum machine_mode) ((int) m + 1)) |
533d0835 RK |
752 | if (HARD_REGNO_MODE_OK (j, m)) |
753 | { | |
754 | PUT_MODE (r, m); | |
08d95f91 RK |
755 | |
756 | /* If a register is not directly suitable for an | |
757 | auto-increment or decrement addressing mode and | |
758 | requires secondary reloads, disallow its class from | |
759 | being used in such addresses. */ | |
760 | ||
761 | if ((0 | |
041d7180 JL |
762 | #ifdef SECONDARY_RELOAD_CLASS |
763 | || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r) | |
764 | != NO_REGS) | |
765 | #else | |
533d0835 | 766 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
08d95f91 RK |
767 | || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
768 | != NO_REGS) | |
533d0835 RK |
769 | #endif |
770 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
08d95f91 RK |
771 | || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) |
772 | != NO_REGS) | |
041d7180 | 773 | #endif |
533d0835 | 774 | #endif |
08d95f91 RK |
775 | ) |
776 | && ! auto_inc_dec_reg_p (r, m)) | |
533d0835 RK |
777 | forbidden_inc_dec_class[i] = 1; |
778 | } | |
779 | } | |
780 | } | |
781 | #endif /* FORBIDDEN_INC_DEC_CLASSES */ | |
782 | ||
e4600702 RK |
783 | init_cost.mem_cost = 10000; |
784 | for (i = 0; i < N_REG_CLASSES; i++) | |
785 | init_cost.cost[i] = 10000; | |
54dac99e | 786 | |
e4600702 RK |
787 | /* Normally we scan the insns once and determine the best class to use for |
788 | each register. However, if -fexpensive_optimizations are on, we do so | |
789 | twice, the second time using the tentative best classes to guide the | |
790 | selection. */ | |
54dac99e | 791 | |
e4600702 RK |
792 | for (pass = 0; pass <= flag_expensive_optimizations; pass++) |
793 | { | |
794 | /* Zero out our accumulation of the cost of each class for each reg. */ | |
54dac99e | 795 | |
4c9a05bc | 796 | bzero ((char *) costs, nregs * sizeof (struct costs)); |
54dac99e | 797 | |
533d0835 RK |
798 | #ifdef FORBIDDEN_INC_DEC_CLASSES |
799 | bzero (in_inc_dec, nregs); | |
800 | #endif | |
801 | ||
e4600702 RK |
802 | loop_depth = 0, loop_cost = 1; |
803 | ||
804 | /* Scan the instructions and record each time it would | |
805 | save code to put a certain register in a certain class. */ | |
806 | ||
807 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
54dac99e | 808 | { |
e4600702 RK |
809 | char *constraints[MAX_RECOG_OPERANDS]; |
810 | enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
811 | int nalternatives; | |
812 | int noperands; | |
813 | ||
814 | /* Show that an insn inside a loop is likely to be executed three | |
ac2a9454 | 815 | times more than insns outside a loop. This is much more aggressive |
e4600702 RK |
816 | than the assumptions made elsewhere and is being tried as an |
817 | experiment. */ | |
818 | ||
819 | if (GET_CODE (insn) == NOTE | |
820 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) | |
821 | loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
822 | else if (GET_CODE (insn) == NOTE | |
823 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) | |
824 | loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); | |
825 | ||
826 | else if ((GET_CODE (insn) == INSN | |
827 | && GET_CODE (PATTERN (insn)) != USE | |
828 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
829 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) | |
830 | || (GET_CODE (insn) == JUMP_INSN | |
831 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
832 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) | |
833 | || GET_CODE (insn) == CALL_INSN) | |
54dac99e | 834 | { |
e4600702 RK |
835 | if (GET_CODE (insn) == INSN |
836 | && (noperands = asm_noperands (PATTERN (insn))) >= 0) | |
837 | { | |
37366632 | 838 | decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR, |
e4600702 | 839 | constraints, modes); |
e5ed2155 TW |
840 | nalternatives = (noperands == 0 ? 0 |
841 | : n_occurrences (',', constraints[0]) + 1); | |
e4600702 RK |
842 | } |
843 | else | |
844 | { | |
845 | int insn_code_number = recog_memoized (insn); | |
846 | rtx note; | |
54dac99e | 847 | |
e4600702 RK |
848 | set = single_set (insn); |
849 | insn_extract (insn); | |
54dac99e | 850 | |
e4600702 RK |
851 | nalternatives = insn_n_alternatives[insn_code_number]; |
852 | noperands = insn_n_operands[insn_code_number]; | |
54dac99e | 853 | |
e4600702 RK |
854 | /* If this insn loads a parameter from its stack slot, then |
855 | it represents a savings, rather than a cost, if the | |
856 | parameter is stored in memory. Record this fact. */ | |
54dac99e | 857 | |
e4600702 RK |
858 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG |
859 | && GET_CODE (SET_SRC (set)) == MEM | |
37366632 RK |
860 | && (note = find_reg_note (insn, REG_EQUIV, |
861 | NULL_RTX)) != 0 | |
e4600702 RK |
862 | && GET_CODE (XEXP (note, 0)) == MEM) |
863 | { | |
864 | costs[REGNO (SET_DEST (set))].mem_cost | |
cbd5b9a2 KR |
865 | -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), |
866 | GENERAL_REGS, 1) | |
e4600702 RK |
867 | * loop_cost); |
868 | record_address_regs (XEXP (SET_SRC (set), 0), | |
869 | BASE_REG_CLASS, loop_cost * 2); | |
870 | continue; | |
871 | } | |
872 | ||
873 | /* Improve handling of two-address insns such as | |
874 | (set X (ashift CONST Y)) where CONST must be made to | |
875 | match X. Change it into two insns: (set X CONST) | |
876 | (set X (ashift X Y)). If we left this for reloading, it | |
877 | would probably get three insns because X and Y might go | |
878 | in the same place. This prevents X and Y from receiving | |
879 | the same hard reg. | |
880 | ||
881 | We can only do this if the modes of operands 0 and 1 | |
882 | (which might not be the same) are tieable and we only need | |
883 | do this during our first pass. */ | |
884 | ||
885 | if (pass == 0 && optimize | |
886 | && noperands >= 3 | |
887 | && insn_operand_constraint[insn_code_number][1][0] == '0' | |
888 | && insn_operand_constraint[insn_code_number][1][1] == 0 | |
889 | && CONSTANT_P (recog_operand[1]) | |
890 | && ! rtx_equal_p (recog_operand[0], recog_operand[1]) | |
891 | && ! rtx_equal_p (recog_operand[0], recog_operand[2]) | |
892 | && GET_CODE (recog_operand[0]) == REG | |
893 | && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), | |
894 | insn_operand_mode[insn_code_number][1])) | |
895 | { | |
896 | rtx previnsn = prev_real_insn (insn); | |
897 | rtx dest | |
898 | = gen_lowpart (insn_operand_mode[insn_code_number][1], | |
899 | recog_operand[0]); | |
900 | rtx newinsn | |
901 | = emit_insn_before (gen_move_insn (dest, | |
902 | recog_operand[1]), | |
903 | insn); | |
904 | ||
905 | /* If this insn was the start of a basic block, | |
61b01243 RS |
906 | include the new insn in that block. |
907 | We need not check for code_label here; | |
908 | while a basic block can start with a code_label, | |
909 | INSN could not be at the beginning of that block. */ | |
e4600702 RK |
910 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) |
911 | { | |
912 | int b; | |
913 | for (b = 0; b < n_basic_blocks; b++) | |
914 | if (insn == basic_block_head[b]) | |
915 | basic_block_head[b] = newinsn; | |
916 | } | |
917 | ||
0f41302f | 918 | /* This makes one more setting of new insns's dest. */ |
b1f21e0a | 919 | REG_N_SETS (REGNO (recog_operand[0]))++; |
e4600702 | 920 | |
20912ad0 RK |
921 | *recog_operand_loc[1] = recog_operand[0]; |
922 | for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) | |
923 | if (recog_dup_num[i] == 1) | |
924 | *recog_dup_loc[i] = recog_operand[0]; | |
925 | ||
e4600702 RK |
926 | insn = PREV_INSN (newinsn); |
927 | continue; | |
928 | } | |
54dac99e | 929 | |
e4600702 RK |
930 | for (i = 0; i < noperands; i++) |
931 | { | |
932 | constraints[i] | |
933 | = insn_operand_constraint[insn_code_number][i]; | |
934 | modes[i] = insn_operand_mode[insn_code_number][i]; | |
935 | } | |
936 | } | |
54dac99e | 937 | |
e4600702 RK |
938 | /* If we get here, we are set up to record the costs of all the |
939 | operands for this insn. Start by initializing the costs. | |
940 | Then handle any address registers. Finally record the desired | |
941 | classes for any pseudos, doing it twice if some pair of | |
942 | operands are commutative. */ | |
943 | ||
944 | for (i = 0; i < noperands; i++) | |
54dac99e | 945 | { |
e4600702 RK |
946 | op_costs[i] = init_cost; |
947 | ||
948 | if (GET_CODE (recog_operand[i]) == SUBREG) | |
949 | recog_operand[i] = SUBREG_REG (recog_operand[i]); | |
950 | ||
951 | if (GET_CODE (recog_operand[i]) == MEM) | |
952 | record_address_regs (XEXP (recog_operand[i], 0), | |
953 | BASE_REG_CLASS, loop_cost * 2); | |
954 | else if (constraints[i][0] == 'p') | |
955 | record_address_regs (recog_operand[i], | |
956 | BASE_REG_CLASS, loop_cost * 2); | |
54dac99e | 957 | } |
e4600702 RK |
958 | |
959 | /* Check for commutative in a separate loop so everything will | |
cc4c133a RS |
960 | have been initialized. We must do this even if one operand |
961 | is a constant--see addsi3 in m68k.md. */ | |
54dac99e | 962 | |
e5ed2155 | 963 | for (i = 0; i < noperands - 1; i++) |
cc4c133a | 964 | if (constraints[i][0] == '%') |
e4600702 RK |
965 | { |
966 | char *xconstraints[MAX_RECOG_OPERANDS]; | |
967 | int j; | |
968 | ||
969 | /* Handle commutative operands by swapping the constraints. | |
970 | We assume the modes are the same. */ | |
971 | ||
972 | for (j = 0; j < noperands; j++) | |
973 | xconstraints[j] = constraints[j]; | |
974 | ||
975 | xconstraints[i] = constraints[i+1]; | |
976 | xconstraints[i+1] = constraints[i]; | |
977 | record_reg_classes (nalternatives, noperands, | |
978 | recog_operand, modes, xconstraints, | |
54dac99e | 979 | insn); |
e4600702 | 980 | } |
54dac99e | 981 | |
e4600702 RK |
982 | record_reg_classes (nalternatives, noperands, recog_operand, |
983 | modes, constraints, insn); | |
54dac99e | 984 | |
e4600702 RK |
985 | /* Now add the cost for each operand to the total costs for |
986 | its register. */ | |
54dac99e | 987 | |
e4600702 RK |
988 | for (i = 0; i < noperands; i++) |
989 | if (GET_CODE (recog_operand[i]) == REG | |
990 | && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) | |
991 | { | |
992 | int regno = REGNO (recog_operand[i]); | |
993 | struct costs *p = &costs[regno], *q = &op_costs[i]; | |
994 | ||
995 | p->mem_cost += q->mem_cost * loop_cost; | |
996 | for (j = 0; j < N_REG_CLASSES; j++) | |
997 | p->cost[j] += q->cost[j] * loop_cost; | |
998 | } | |
54dac99e RK |
999 | } |
1000 | } | |
54dac99e | 1001 | |
e4600702 RK |
1002 | /* Now for each register look at how desirable each class is |
1003 | and find which class is preferred. Store that in | |
1004 | `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register | |
1005 | class any of whose registers is better than memory. */ | |
54dac99e | 1006 | |
e4600702 RK |
1007 | if (pass == 0) |
1008 | { | |
6feacd09 MM |
1009 | prefclass = prefclass_buffer; |
1010 | altclass = altclass_buffer; | |
e4600702 | 1011 | } |
54dac99e | 1012 | |
e4600702 | 1013 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) |
54dac99e | 1014 | { |
ca3c6eae | 1015 | register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
e4600702 RK |
1016 | enum reg_class best = ALL_REGS, alt = NO_REGS; |
1017 | /* This is an enum reg_class, but we call it an int | |
1018 | to save lots of casts. */ | |
1019 | register int class; | |
1020 | register struct costs *p = &costs[i]; | |
1021 | ||
1022 | for (class = (int) ALL_REGS - 1; class > 0; class--) | |
54dac99e | 1023 | { |
533d0835 RK |
1024 | /* Ignore classes that are too small for this operand or |
1025 | invalid for a operand that was auto-incremented. */ | |
e4600702 | 1026 | if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) |
533d0835 RK |
1027 | > reg_class_size[class] |
1028 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1029 | || (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
1030 | #endif | |
1031 | ) | |
e4600702 RK |
1032 | ; |
1033 | else if (p->cost[class] < best_cost) | |
1034 | { | |
1035 | best_cost = p->cost[class]; | |
1036 | best = (enum reg_class) class; | |
1037 | } | |
1038 | else if (p->cost[class] == best_cost) | |
1039 | best = reg_class_subunion[(int)best][class]; | |
54dac99e | 1040 | } |
54dac99e | 1041 | |
e4600702 RK |
1042 | /* Record the alternate register class; i.e., a class for which |
1043 | every register in it is better than using memory. If adding a | |
1044 | class would make a smaller class (i.e., no union of just those | |
1045 | classes exists), skip that class. The major unions of classes | |
1046 | should be provided as a register class. Don't do this if we | |
1047 | will be doing it again later. */ | |
1048 | ||
1049 | if (pass == 1 || ! flag_expensive_optimizations) | |
1050 | for (class = 0; class < N_REG_CLASSES; class++) | |
1051 | if (p->cost[class] < p->mem_cost | |
77edb222 | 1052 | && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] |
533d0835 RK |
1053 | > reg_class_size[(int) alt]) |
1054 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1055 | && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) | |
1056 | #endif | |
1057 | ) | |
e4600702 RK |
1058 | alt = reg_class_subunion[(int) alt][class]; |
1059 | ||
1060 | /* If we don't add any classes, nothing to try. */ | |
1061 | if (alt == best) | |
995d54dd | 1062 | alt = NO_REGS; |
e4600702 RK |
1063 | |
1064 | /* We cast to (int) because (char) hits bugs in some compilers. */ | |
1065 | prefclass[i] = (int) best; | |
1066 | altclass[i] = (int) alt; | |
1067 | } | |
54dac99e RK |
1068 | } |
1069 | #endif /* REGISTER_CONSTRAINTS */ | |
56a65848 DB |
1070 | |
1071 | free (costs); | |
54dac99e RK |
1072 | } |
1073 | \f | |
1074 | #ifdef REGISTER_CONSTRAINTS | |
1075 | ||
e4600702 RK |
1076 | /* Record the cost of using memory or registers of various classes for |
1077 | the operands in INSN. | |
54dac99e | 1078 | |
e4600702 | 1079 | N_ALTS is the number of alternatives. |
54dac99e | 1080 | |
e4600702 RK |
1081 | N_OPS is the number of operands. |
1082 | ||
1083 | OPS is an array of the operands. | |
1084 | ||
1085 | MODES are the modes of the operands, in case any are VOIDmode. | |
1086 | ||
1087 | CONSTRAINTS are the constraints to use for the operands. This array | |
1088 | is modified by this procedure. | |
1089 | ||
1090 | This procedure works alternative by alternative. For each alternative | |
1091 | we assume that we will be able to allocate all pseudos to their ideal | |
1092 | register class and calculate the cost of using that alternative. Then | |
1093 | we compute for each operand that is a pseudo-register, the cost of | |
1094 | having the pseudo allocated to each register class and using it in that | |
1095 | alternative. To this cost is added the cost of the alternative. | |
1096 | ||
1097 | The cost of each class for this insn is its lowest cost among all the | |
1098 | alternatives. */ | |
1099 | ||
1100 | static void | |
1101 | record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn) | |
1102 | int n_alts; | |
1103 | int n_ops; | |
1104 | rtx *ops; | |
1105 | enum machine_mode *modes; | |
54dac99e | 1106 | char **constraints; |
e4600702 | 1107 | rtx insn; |
54dac99e | 1108 | { |
e4600702 RK |
1109 | int alt; |
1110 | enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS]; | |
1111 | int i, j; | |
ec2d92af | 1112 | rtx set; |
e4600702 RK |
1113 | |
1114 | /* By default, each operand is an input operand. */ | |
1115 | ||
1116 | for (i = 0; i < n_ops; i++) | |
1117 | op_types[i] = OP_READ; | |
54dac99e | 1118 | |
e4600702 RK |
1119 | /* Process each alternative, each time minimizing an operand's cost with |
1120 | the cost for each operand in that alternative. */ | |
54dac99e | 1121 | |
e4600702 | 1122 | for (alt = 0; alt < n_alts; alt++) |
54dac99e | 1123 | { |
e4600702 RK |
1124 | struct costs this_op_costs[MAX_RECOG_OPERANDS]; |
1125 | int alt_fail = 0; | |
1126 | int alt_cost = 0; | |
1127 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
1128 | int class; | |
54dac99e | 1129 | |
e4600702 RK |
1130 | for (i = 0; i < n_ops; i++) |
1131 | { | |
1132 | char *p = constraints[i]; | |
1133 | rtx op = ops[i]; | |
1134 | enum machine_mode mode = modes[i]; | |
1135 | int allows_mem = 0; | |
1136 | int win = 0; | |
e51712db | 1137 | unsigned char c; |
54dac99e | 1138 | |
e4600702 RK |
1139 | /* If this operand has no constraints at all, we can conclude |
1140 | nothing about it since anything is valid. */ | |
54dac99e | 1141 | |
e4600702 RK |
1142 | if (*p == 0) |
1143 | { | |
1144 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
1145 | bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); | |
54dac99e | 1146 | |
e4600702 RK |
1147 | continue; |
1148 | } | |
54dac99e | 1149 | |
347099d6 RS |
1150 | if (*p == '%') |
1151 | p++; | |
1152 | ||
e4600702 RK |
1153 | /* If this alternative is only relevant when this operand |
1154 | matches a previous operand, we do different things depending | |
1155 | on whether this operand is a pseudo-reg or not. */ | |
54dac99e | 1156 | |
e4600702 RK |
1157 | if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) |
1158 | { | |
1159 | j = p[0] - '0'; | |
1160 | classes[i] = classes[j]; | |
1161 | ||
1162 | if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1163 | { | |
1164 | /* If this matches the other operand, we have no added | |
dc903608 | 1165 | cost and we win. */ |
e4600702 | 1166 | if (rtx_equal_p (ops[j], op)) |
dc903608 | 1167 | win = 1; |
e4600702 | 1168 | |
77e67eac RK |
1169 | /* If we can put the other operand into a register, add to |
1170 | the cost of this alternative the cost to copy this | |
1171 | operand to the register used for the other operand. */ | |
e4600702 | 1172 | |
dc903608 | 1173 | else if (classes[j] != NO_REGS) |
77e67eac | 1174 | alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; |
e4600702 | 1175 | } |
07d8ca2d RS |
1176 | else if (GET_CODE (ops[j]) != REG |
1177 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
1178 | { | |
1179 | /* This op is a pseudo but the one it matches is not. */ | |
1180 | ||
1181 | /* If we can't put the other operand into a register, this | |
1182 | alternative can't be used. */ | |
1183 | ||
1184 | if (classes[j] == NO_REGS) | |
1185 | alt_fail = 1; | |
e4600702 | 1186 | |
07d8ca2d RS |
1187 | /* Otherwise, add to the cost of this alternative the cost |
1188 | to copy the other operand to the register used for this | |
1189 | operand. */ | |
1190 | ||
1191 | else | |
1192 | alt_cost += copy_cost (ops[j], mode, classes[j], 1); | |
1193 | } | |
e4600702 RK |
1194 | else |
1195 | { | |
1196 | /* The costs of this operand are the same as that of the | |
1197 | other operand. However, if we cannot tie them, this | |
1198 | alternative needs to do a copy, which is one | |
1199 | instruction. */ | |
1200 | ||
1201 | this_op_costs[i] = this_op_costs[j]; | |
37747c82 RK |
1202 | if (REGNO (ops[i]) != REGNO (ops[j]) |
1203 | && ! find_reg_note (insn, REG_DEAD, op)) | |
1204 | alt_cost += 2; | |
e4600702 | 1205 | |
347099d6 | 1206 | /* This is in place of ordinary cost computation |
1ddb342a RK |
1207 | for this operand, so skip to the end of the |
1208 | alternative (should be just one character). */ | |
1209 | while (*p && *p++ != ',') | |
1210 | ; | |
1211 | ||
1212 | constraints[i] = p; | |
347099d6 RS |
1213 | continue; |
1214 | } | |
e4600702 RK |
1215 | } |
1216 | ||
1217 | /* Scan all the constraint letters. See if the operand matches | |
1218 | any of the constraints. Collect the valid register classes | |
1219 | and see if this operand accepts memory. */ | |
1220 | ||
1221 | classes[i] = NO_REGS; | |
1222 | while (*p && (c = *p++) != ',') | |
1223 | switch (c) | |
1224 | { | |
1225 | case '=': | |
1226 | op_types[i] = OP_WRITE; | |
1227 | break; | |
1228 | ||
1229 | case '+': | |
1230 | op_types[i] = OP_READ_WRITE; | |
1231 | break; | |
1232 | ||
1233 | case '*': | |
1234 | /* Ignore the next letter for this pass. */ | |
1235 | p++; | |
1236 | break; | |
1237 | ||
812f2051 R |
1238 | case '?': |
1239 | alt_cost += 2; | |
e4600702 | 1240 | case '%': |
812f2051 | 1241 | case '!': case '#': |
e4600702 RK |
1242 | case '&': |
1243 | case '0': case '1': case '2': case '3': case '4': | |
1244 | case 'p': | |
1245 | break; | |
1246 | ||
1247 | case 'm': case 'o': case 'V': | |
ac2a9454 | 1248 | /* It doesn't seem worth distinguishing between offsettable |
e4600702 RK |
1249 | and non-offsettable addresses here. */ |
1250 | allows_mem = 1; | |
1251 | if (GET_CODE (op) == MEM) | |
1252 | win = 1; | |
1253 | break; | |
1254 | ||
1255 | case '<': | |
1256 | if (GET_CODE (op) == MEM | |
1257 | && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
1258 | || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
1259 | win = 1; | |
1260 | break; | |
1261 | ||
1262 | case '>': | |
1263 | if (GET_CODE (op) == MEM | |
1264 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
1265 | || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
1266 | win = 1; | |
1267 | break; | |
1268 | ||
1269 | case 'E': | |
7ac2547f | 1270 | #ifndef REAL_ARITHMETIC |
e4600702 RK |
1271 | /* Match any floating double constant, but only if |
1272 | we can examine the bits of it reliably. */ | |
1273 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
37366632 | 1274 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
e4600702 RK |
1275 | && GET_MODE (op) != VOIDmode && ! flag_pretend_float) |
1276 | break; | |
7ac2547f | 1277 | #endif |
e4600702 RK |
1278 | if (GET_CODE (op) == CONST_DOUBLE) |
1279 | win = 1; | |
1280 | break; | |
1281 | ||
1282 | case 'F': | |
1283 | if (GET_CODE (op) == CONST_DOUBLE) | |
1284 | win = 1; | |
1285 | break; | |
1286 | ||
1287 | case 'G': | |
1288 | case 'H': | |
1289 | if (GET_CODE (op) == CONST_DOUBLE | |
1290 | && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) | |
1291 | win = 1; | |
1292 | break; | |
1293 | ||
1294 | case 's': | |
1295 | if (GET_CODE (op) == CONST_INT | |
1296 | || (GET_CODE (op) == CONST_DOUBLE | |
1297 | && GET_MODE (op) == VOIDmode)) | |
1298 | break; | |
1299 | case 'i': | |
1300 | if (CONSTANT_P (op) | |
1301 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1302 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
1303 | #endif | |
1304 | ) | |
1305 | win = 1; | |
1306 | break; | |
1307 | ||
1308 | case 'n': | |
1309 | if (GET_CODE (op) == CONST_INT | |
1310 | || (GET_CODE (op) == CONST_DOUBLE | |
1311 | && GET_MODE (op) == VOIDmode)) | |
1312 | win = 1; | |
1313 | break; | |
1314 | ||
1315 | case 'I': | |
1316 | case 'J': | |
1317 | case 'K': | |
1318 | case 'L': | |
1319 | case 'M': | |
1320 | case 'N': | |
1321 | case 'O': | |
1322 | case 'P': | |
1323 | if (GET_CODE (op) == CONST_INT | |
1324 | && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) | |
1325 | win = 1; | |
1326 | break; | |
1327 | ||
1328 | case 'X': | |
1329 | win = 1; | |
1330 | break; | |
54dac99e | 1331 | |
54dac99e | 1332 | #ifdef EXTRA_CONSTRAINT |
e4600702 RK |
1333 | case 'Q': |
1334 | case 'R': | |
1335 | case 'S': | |
1336 | case 'T': | |
1337 | case 'U': | |
1338 | if (EXTRA_CONSTRAINT (op, c)) | |
1339 | win = 1; | |
1340 | break; | |
1341 | #endif | |
1342 | ||
1343 | case 'g': | |
1344 | if (GET_CODE (op) == MEM | |
1345 | || (CONSTANT_P (op) | |
1346 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
1347 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | |
54dac99e | 1348 | #endif |
e4600702 RK |
1349 | )) |
1350 | win = 1; | |
1351 | allows_mem = 1; | |
1352 | case 'r': | |
1353 | classes[i] | |
1354 | = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; | |
1355 | break; | |
1356 | ||
1357 | default: | |
1358 | classes[i] | |
1359 | = reg_class_subunion[(int) classes[i]] | |
1360 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
1361 | } | |
1362 | ||
1363 | constraints[i] = p; | |
1364 | ||
1365 | /* How we account for this operand now depends on whether it is a | |
1366 | pseudo register or not. If it is, we first check if any | |
1367 | register classes are valid. If not, we ignore this alternative, | |
1368 | since we want to assume that all pseudos get allocated for | |
1369 | register preferencing. If some register class is valid, compute | |
1370 | the costs of moving the pseudo into that class. */ | |
1371 | ||
1372 | if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
4db18574 | 1373 | { |
e4600702 RK |
1374 | if (classes[i] == NO_REGS) |
1375 | alt_fail = 1; | |
1376 | else | |
1377 | { | |
1378 | struct costs *pp = &this_op_costs[i]; | |
1379 | ||
1380 | for (class = 0; class < N_REG_CLASSES; class++) | |
1381 | pp->cost[class] = may_move_cost[class][(int) classes[i]]; | |
1382 | ||
1383 | /* If the alternative actually allows memory, make things | |
1384 | a bit cheaper since we won't need an extra insn to | |
1385 | load it. */ | |
1386 | ||
cbd5b9a2 KR |
1387 | pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1) |
1388 | - allows_mem); | |
e4600702 RK |
1389 | |
1390 | /* If we have assigned a class to this register in our | |
1391 | first pass, add a cost to this alternative corresponding | |
1392 | to what we would add if this register were not in the | |
1393 | appropriate class. */ | |
1394 | ||
1395 | if (prefclass) | |
1396 | alt_cost | |
e51712db | 1397 | += may_move_cost[(unsigned char)prefclass[REGNO (op)]][(int) classes[i]]; |
e4600702 | 1398 | } |
4db18574 | 1399 | } |
54dac99e | 1400 | |
e4600702 RK |
1401 | /* Otherwise, if this alternative wins, either because we |
1402 | have already determined that or if we have a hard register of | |
1403 | the proper class, there is no cost for this alternative. */ | |
54dac99e | 1404 | |
e4600702 RK |
1405 | else if (win |
1406 | || (GET_CODE (op) == REG | |
6f654776 | 1407 | && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) |
e4600702 | 1408 | ; |
54dac99e | 1409 | |
e4600702 RK |
1410 | /* If registers are valid, the cost of this alternative includes |
1411 | copying the object to and/or from a register. */ | |
54dac99e | 1412 | |
e4600702 RK |
1413 | else if (classes[i] != NO_REGS) |
1414 | { | |
1415 | if (op_types[i] != OP_WRITE) | |
1416 | alt_cost += copy_cost (op, mode, classes[i], 1); | |
54dac99e | 1417 | |
e4600702 RK |
1418 | if (op_types[i] != OP_READ) |
1419 | alt_cost += copy_cost (op, mode, classes[i], 0); | |
1420 | } | |
54dac99e | 1421 | |
e4600702 RK |
1422 | /* The only other way this alternative can be used is if this is a |
1423 | constant that could be placed into memory. */ | |
1424 | ||
1425 | else if (CONSTANT_P (op) && allows_mem) | |
cbd5b9a2 | 1426 | alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); |
e4600702 RK |
1427 | else |
1428 | alt_fail = 1; | |
1429 | } | |
1430 | ||
1431 | if (alt_fail) | |
1432 | continue; | |
1433 | ||
1434 | /* Finally, update the costs with the information we've calculated | |
1435 | about this alternative. */ | |
1436 | ||
1437 | for (i = 0; i < n_ops; i++) | |
1438 | if (GET_CODE (ops[i]) == REG | |
1439 | && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
54dac99e | 1440 | { |
e4600702 RK |
1441 | struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; |
1442 | int scale = 1 + (op_types[i] == OP_READ_WRITE); | |
54dac99e | 1443 | |
e4600702 RK |
1444 | pp->mem_cost = MIN (pp->mem_cost, |
1445 | (qq->mem_cost + alt_cost) * scale); | |
54dac99e | 1446 | |
e4600702 RK |
1447 | for (class = 0; class < N_REG_CLASSES; class++) |
1448 | pp->cost[class] = MIN (pp->cost[class], | |
1449 | (qq->cost[class] + alt_cost) * scale); | |
1450 | } | |
1451 | } | |
ec2d92af RK |
1452 | |
1453 | /* If this insn is a single set copying operand 1 to operand 0 | |
1454 | and one is a pseudo with the other a hard reg that is in its | |
1455 | own register class, set the cost of that register class to -1. */ | |
1456 | ||
1457 | if ((set = single_set (insn)) != 0 | |
1458 | && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
1459 | && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG) | |
1460 | for (i = 0; i <= 1; i++) | |
1461 | if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1462 | { | |
1463 | int regno = REGNO (ops[!i]); | |
1464 | enum machine_mode mode = GET_MODE (ops[!i]); | |
1465 | int class; | |
4841ba4b | 1466 | int nr; |
ec2d92af RK |
1467 | |
1468 | if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0 | |
e51712db | 1469 | && (reg_class_size[(unsigned char)prefclass[regno]] |
ec2d92af | 1470 | == CLASS_MAX_NREGS (prefclass[regno], mode))) |
e51712db | 1471 | op_costs[i].cost[(unsigned char)prefclass[regno]] = -1; |
ec2d92af RK |
1472 | else if (regno < FIRST_PSEUDO_REGISTER) |
1473 | for (class = 0; class < N_REG_CLASSES; class++) | |
1474 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
1475 | && reg_class_size[class] == CLASS_MAX_NREGS (class, mode)) | |
4841ba4b RK |
1476 | { |
1477 | if (reg_class_size[class] == 1) | |
1478 | op_costs[i].cost[class] = -1; | |
1479 | else | |
1480 | { | |
1481 | for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++) | |
1482 | { | |
1483 | if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr)) | |
1484 | break; | |
1485 | } | |
1486 | ||
1487 | if (nr == HARD_REGNO_NREGS(regno,mode)) | |
1488 | op_costs[i].cost[class] = -1; | |
1489 | } | |
1490 | } | |
ec2d92af | 1491 | } |
54dac99e | 1492 | } |
e4600702 RK |
1493 | \f |
1494 | /* Compute the cost of loading X into (if TO_P is non-zero) or from (if | |
1495 | TO_P is zero) a register of class CLASS in mode MODE. | |
1496 | ||
1497 | X must not be a pseudo. */ | |
1498 | ||
1499 | static int | |
1500 | copy_cost (x, mode, class, to_p) | |
1501 | rtx x; | |
1502 | enum machine_mode mode; | |
1503 | enum reg_class class; | |
1504 | int to_p; | |
1505 | { | |
29a82058 | 1506 | #ifdef HAVE_SECONDARY_RELOADS |
e4600702 | 1507 | enum reg_class secondary_class = NO_REGS; |
29a82058 | 1508 | #endif |
e4600702 RK |
1509 | |
1510 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
1511 | assuming optimal allocation. */ | |
1512 | ||
1513 | if (GET_CODE (x) == SCRATCH) | |
1514 | return 0; | |
1515 | ||
1516 | /* Get the class we will actually use for a reload. */ | |
1517 | class = PREFERRED_RELOAD_CLASS (x, class); | |
1518 | ||
1519 | #ifdef HAVE_SECONDARY_RELOADS | |
1520 | /* If we need a secondary reload (we assume here that we are using | |
1521 | the secondary reload as an intermediate, not a scratch register), the | |
1522 | cost is that to load the input into the intermediate register, then | |
1523 | to copy them. We use a special value of TO_P to avoid recursion. */ | |
1524 | ||
1525 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1526 | if (to_p == 1) | |
1527 | secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); | |
1528 | #endif | |
1529 | ||
dd9f0e8f | 1530 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
e4600702 RK |
1531 | if (! to_p) |
1532 | secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); | |
1533 | #endif | |
1534 | ||
1535 | if (secondary_class != NO_REGS) | |
1536 | return (move_cost[(int) secondary_class][(int) class] | |
1537 | + copy_cost (x, mode, secondary_class, 2)); | |
dd9f0e8f | 1538 | #endif /* HAVE_SECONDARY_RELOADS */ |
e4600702 RK |
1539 | |
1540 | /* For memory, use the memory move cost, for (hard) registers, use the | |
1541 | cost to move between the register classes, and use 2 for everything | |
1542 | else (constants). */ | |
1543 | ||
1544 | if (GET_CODE (x) == MEM || class == NO_REGS) | |
cbd5b9a2 | 1545 | return MEMORY_MOVE_COST (mode, class, to_p); |
54dac99e | 1546 | |
e4600702 RK |
1547 | else if (GET_CODE (x) == REG) |
1548 | return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; | |
1549 | ||
1550 | else | |
1551 | /* If this is a constant, we may eventually want to call rtx_cost here. */ | |
1552 | return 2; | |
1553 | } | |
1554 | \f | |
54dac99e RK |
1555 | /* Record the pseudo registers we must reload into hard registers |
1556 | in a subexpression of a memory address, X. | |
e4600702 RK |
1557 | |
1558 | CLASS is the class that the register needs to be in and is either | |
1559 | BASE_REG_CLASS or INDEX_REG_CLASS. | |
1560 | ||
1561 | SCALE is twice the amount to multiply the cost by (it is twice so we | |
1562 | can represent half-cost adjustments). */ | |
54dac99e | 1563 | |
197d6480 | 1564 | static void |
e4600702 | 1565 | record_address_regs (x, class, scale) |
54dac99e | 1566 | rtx x; |
e4600702 RK |
1567 | enum reg_class class; |
1568 | int scale; | |
54dac99e RK |
1569 | { |
1570 | register enum rtx_code code = GET_CODE (x); | |
1571 | ||
1572 | switch (code) | |
1573 | { | |
1574 | case CONST_INT: | |
1575 | case CONST: | |
1576 | case CC0: | |
1577 | case PC: | |
1578 | case SYMBOL_REF: | |
1579 | case LABEL_REF: | |
1580 | return; | |
1581 | ||
1582 | case PLUS: | |
1583 | /* When we have an address that is a sum, | |
1584 | we must determine whether registers are "base" or "index" regs. | |
1585 | If there is a sum of two registers, we must choose one to be | |
1586 | the "base". Luckily, we can use the REGNO_POINTER_FLAG | |
e4600702 RK |
1587 | to make a good choice most of the time. We only need to do this |
1588 | on machines that can have two registers in an address and where | |
1589 | the base and index register classes are different. | |
1590 | ||
1591 | ??? This code used to set REGNO_POINTER_FLAG in some cases, but | |
1592 | that seems bogus since it should only be set when we are sure | |
1593 | the register is being used as a pointer. */ | |
1594 | ||
54dac99e RK |
1595 | { |
1596 | rtx arg0 = XEXP (x, 0); | |
1597 | rtx arg1 = XEXP (x, 1); | |
1598 | register enum rtx_code code0 = GET_CODE (arg0); | |
1599 | register enum rtx_code code1 = GET_CODE (arg1); | |
54dac99e RK |
1600 | |
1601 | /* Look inside subregs. */ | |
e4600702 | 1602 | if (code0 == SUBREG) |
54dac99e | 1603 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); |
e4600702 | 1604 | if (code1 == SUBREG) |
54dac99e RK |
1605 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); |
1606 | ||
e4600702 RK |
1607 | /* If this machine only allows one register per address, it must |
1608 | be in the first operand. */ | |
1609 | ||
1610 | if (MAX_REGS_PER_ADDRESS == 1) | |
1611 | record_address_regs (arg0, class, scale); | |
1612 | ||
1613 | /* If index and base registers are the same on this machine, just | |
1614 | record registers in any non-constant operands. We assume here, | |
1615 | as well as in the tests below, that all addresses are in | |
1616 | canonical form. */ | |
1617 | ||
1618 | else if (INDEX_REG_CLASS == BASE_REG_CLASS) | |
54dac99e | 1619 | { |
e4600702 RK |
1620 | record_address_regs (arg0, class, scale); |
1621 | if (! CONSTANT_P (arg1)) | |
1622 | record_address_regs (arg1, class, scale); | |
54dac99e | 1623 | } |
e4600702 RK |
1624 | |
1625 | /* If the second operand is a constant integer, it doesn't change | |
1626 | what class the first operand must be. */ | |
1627 | ||
1628 | else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
1629 | record_address_regs (arg0, class, scale); | |
1630 | ||
1631 | /* If the second operand is a symbolic constant, the first operand | |
1632 | must be an index register. */ | |
1633 | ||
1634 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
1635 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1636 | ||
956d6950 JL |
1637 | /* If both operands are registers but one is already a hard register |
1638 | of index or base class, give the other the class that the hard | |
1639 | register is not. */ | |
1640 | ||
3f9e9508 | 1641 | #ifdef REG_OK_FOR_BASE_P |
956d6950 JL |
1642 | else if (code0 == REG && code1 == REG |
1643 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
1644 | && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0))) | |
1645 | record_address_regs (arg1, | |
1646 | REG_OK_FOR_BASE_P (arg0) | |
1647 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1648 | scale); | |
1649 | else if (code0 == REG && code1 == REG | |
1650 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
1651 | && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1))) | |
1652 | record_address_regs (arg0, | |
1653 | REG_OK_FOR_BASE_P (arg1) | |
1654 | ? INDEX_REG_CLASS : BASE_REG_CLASS, | |
1655 | scale); | |
3f9e9508 | 1656 | #endif |
956d6950 | 1657 | |
e9a25f70 JL |
1658 | /* If one operand is known to be a pointer, it must be the base |
1659 | with the other operand the index. Likewise if the other operand | |
1660 | is a MULT. */ | |
f22376c7 | 1661 | |
e9a25f70 JL |
1662 | else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0))) |
1663 | || code1 == MULT) | |
f22376c7 CI |
1664 | { |
1665 | record_address_regs (arg0, BASE_REG_CLASS, scale); | |
1666 | record_address_regs (arg1, INDEX_REG_CLASS, scale); | |
1667 | } | |
e9a25f70 JL |
1668 | else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1))) |
1669 | || code0 == MULT) | |
f22376c7 CI |
1670 | { |
1671 | record_address_regs (arg0, INDEX_REG_CLASS, scale); | |
1672 | record_address_regs (arg1, BASE_REG_CLASS, scale); | |
1673 | } | |
1674 | ||
e9a25f70 | 1675 | /* Otherwise, count equal chances that each might be a base |
e4600702 RK |
1676 | or index register. This case should be rare. */ |
1677 | ||
e9a25f70 | 1678 | else |
54dac99e | 1679 | { |
e4600702 RK |
1680 | record_address_regs (arg0, BASE_REG_CLASS, scale / 2); |
1681 | record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); | |
1682 | record_address_regs (arg1, BASE_REG_CLASS, scale / 2); | |
1683 | record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); | |
54dac99e | 1684 | } |
54dac99e RK |
1685 | } |
1686 | break; | |
1687 | ||
1688 | case POST_INC: | |
1689 | case PRE_INC: | |
1690 | case POST_DEC: | |
1691 | case PRE_DEC: | |
1692 | /* Double the importance of a pseudo register that is incremented | |
1693 | or decremented, since it would take two extra insns | |
533d0835 RK |
1694 | if it ends up in the wrong place. If the operand is a pseudo, |
1695 | show it is being used in an INC_DEC context. */ | |
1696 | ||
1697 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1698 | if (GET_CODE (XEXP (x, 0)) == REG | |
1699 | && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
1700 | in_inc_dec[REGNO (XEXP (x, 0))] = 1; | |
1701 | #endif | |
e4600702 RK |
1702 | |
1703 | record_address_regs (XEXP (x, 0), class, 2 * scale); | |
54dac99e RK |
1704 | break; |
1705 | ||
1706 | case REG: | |
1707 | { | |
e4600702 RK |
1708 | register struct costs *pp = &costs[REGNO (x)]; |
1709 | register int i; | |
54dac99e | 1710 | |
cbd5b9a2 | 1711 | pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; |
54dac99e | 1712 | |
e4600702 RK |
1713 | for (i = 0; i < N_REG_CLASSES; i++) |
1714 | pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; | |
54dac99e RK |
1715 | } |
1716 | break; | |
1717 | ||
1718 | default: | |
1719 | { | |
1720 | register char *fmt = GET_RTX_FORMAT (code); | |
1721 | register int i; | |
1722 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1723 | if (fmt[i] == 'e') | |
e4600702 | 1724 | record_address_regs (XEXP (x, i), class, scale); |
54dac99e RK |
1725 | } |
1726 | } | |
1727 | } | |
08d95f91 RK |
1728 | \f |
1729 | #ifdef FORBIDDEN_INC_DEC_CLASSES | |
1730 | ||
1731 | /* Return 1 if REG is valid as an auto-increment memory reference | |
1732 | to an object of MODE. */ | |
1733 | ||
1d300e19 | 1734 | static int |
08d95f91 RK |
1735 | auto_inc_dec_reg_p (reg, mode) |
1736 | rtx reg; | |
1737 | enum machine_mode mode; | |
1738 | { | |
1739 | #ifdef HAVE_POST_INCREMENT | |
38a448ca | 1740 | if (memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) |
08d95f91 RK |
1741 | return 1; |
1742 | #endif | |
1743 | ||
1744 | #ifdef HAVE_POST_DECREMENT | |
38a448ca | 1745 | if (memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) |
08d95f91 RK |
1746 | return 1; |
1747 | #endif | |
1748 | ||
1749 | #ifdef HAVE_PRE_INCREMENT | |
38a448ca | 1750 | if (memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) |
08d95f91 RK |
1751 | return 1; |
1752 | #endif | |
1753 | ||
1754 | #ifdef HAVE_PRE_DECREMENT | |
38a448ca | 1755 | if (memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) |
08d95f91 RK |
1756 | return 1; |
1757 | #endif | |
1758 | ||
1759 | return 0; | |
1760 | } | |
1761 | #endif | |
1762 | ||
54dac99e | 1763 | #endif /* REGISTER_CONSTRAINTS */ |
b1f21e0a MM |
1764 | \f |
1765 | /* Allocate enough space to hold NUM_REGS registers for the tables used for | |
1766 | reg_scan and flow_analysis that are indexed by the register number. If | |
39379e67 MM |
1767 | NEW_P is non zero, initialize all of the registers, otherwise only |
1768 | initialize the new registers allocated. The same table is kept from | |
1769 | function to function, only reallocating it when we need more room. If | |
1770 | RENUMBER_P is non zero, allocate the reg_renumber array also. */ | |
b1f21e0a MM |
1771 | |
1772 | void | |
39379e67 | 1773 | allocate_reg_info (num_regs, new_p, renumber_p) |
6feacd09 | 1774 | size_t num_regs; |
b1f21e0a | 1775 | int new_p; |
39379e67 | 1776 | int renumber_p; |
b1f21e0a | 1777 | { |
6feacd09 | 1778 | static size_t regno_allocated = 0; |
39379e67 | 1779 | static short *renumber = (short *)0; |
b1f21e0a | 1780 | int i; |
6feacd09 MM |
1781 | size_t size_info; |
1782 | size_t size_renumber; | |
1783 | size_t min = (new_p) ? 0 : reg_n_max; | |
1784 | struct reg_info_data *reg_data; | |
1785 | struct reg_info_data *reg_next; | |
39379e67 MM |
1786 | |
1787 | /* Free up all storage allocated */ | |
1788 | if (num_regs < 0) | |
1789 | { | |
1790 | if (reg_n_info) | |
1791 | { | |
6feacd09 MM |
1792 | VARRAY_FREE (reg_n_info); |
1793 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
1794 | { | |
1795 | reg_next = reg_data->next; | |
1796 | free ((char *)reg_data); | |
1797 | } | |
1798 | ||
1799 | free (prefclass_buffer); | |
1800 | free (altclass_buffer); | |
1801 | prefclass_buffer = (char *)0; | |
1802 | altclass_buffer = (char *)0; | |
1803 | reg_info_head = (struct reg_info_data *)0; | |
39379e67 MM |
1804 | renumber = (short *)0; |
1805 | } | |
1806 | regno_allocated = 0; | |
a494747c | 1807 | reg_n_max = 0; |
39379e67 MM |
1808 | return; |
1809 | } | |
1810 | ||
b1f21e0a MM |
1811 | if (num_regs > regno_allocated) |
1812 | { | |
6feacd09 MM |
1813 | size_t old_allocated = regno_allocated; |
1814 | ||
b1f21e0a | 1815 | regno_allocated = num_regs + (num_regs / 20); /* add some slop space */ |
39379e67 MM |
1816 | size_renumber = regno_allocated * sizeof (short); |
1817 | ||
1818 | if (!reg_n_info) | |
1819 | { | |
6feacd09 | 1820 | VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); |
39379e67 | 1821 | renumber = (short *) xmalloc (size_renumber); |
6feacd09 MM |
1822 | prefclass_buffer = (char *) xmalloc (regno_allocated); |
1823 | altclass_buffer = (char *) xmalloc (regno_allocated); | |
39379e67 MM |
1824 | } |
1825 | ||
1826 | else | |
1827 | { | |
6feacd09 MM |
1828 | VARRAY_GROW (reg_n_info, regno_allocated); |
1829 | ||
1830 | if (new_p) /* if we're zapping everything, no need to realloc */ | |
1831 | { | |
1832 | free ((char *)renumber); | |
1833 | free ((char *)prefclass_buffer); | |
1834 | free ((char *)altclass_buffer); | |
1835 | renumber = (short *) xmalloc (size_renumber); | |
1836 | prefclass_buffer = (char *) xmalloc (regno_allocated); | |
1837 | altclass_buffer = (char *) xmalloc (regno_allocated); | |
1838 | } | |
1839 | ||
1840 | else | |
1841 | { | |
1842 | renumber = (short *) xrealloc ((char *)renumber, size_renumber); | |
1843 | prefclass_buffer = (char *) xrealloc ((char *)prefclass_buffer, | |
1844 | regno_allocated); | |
1845 | ||
1846 | altclass_buffer = (char *) xrealloc ((char *)altclass_buffer, | |
1847 | regno_allocated); | |
1848 | } | |
39379e67 | 1849 | } |
6feacd09 MM |
1850 | |
1851 | size_info = (regno_allocated - old_allocated) * sizeof (reg_info) | |
1852 | + sizeof (struct reg_info_data) - sizeof (reg_info); | |
1853 | reg_data = (struct reg_info_data *) xcalloc (size_info, 1); | |
1854 | reg_data->min_index = old_allocated; | |
1855 | reg_data->max_index = regno_allocated - 1; | |
1856 | reg_data->next = reg_info_head; | |
1857 | reg_info_head = reg_data; | |
b1f21e0a MM |
1858 | } |
1859 | ||
6feacd09 | 1860 | reg_n_max = num_regs; |
b1f21e0a MM |
1861 | if (min < num_regs) |
1862 | { | |
6feacd09 MM |
1863 | /* Loop through each of the segments allocated for the actual |
1864 | reg_info pages, and set up the pointers, zero the pages, etc. */ | |
1865 | for (reg_data = reg_info_head; reg_data; reg_data = reg_next) | |
39379e67 | 1866 | { |
6feacd09 MM |
1867 | size_t min_index = reg_data->min_index; |
1868 | size_t max_index = reg_data->max_index; | |
1869 | ||
1870 | reg_next = reg_data->next; | |
29f63881 | 1871 | if (min <= max_index) |
6feacd09 | 1872 | { |
eafdfea8 | 1873 | size_t max = max_index; |
29f63881 RH |
1874 | size_t local_min = min - min_index; |
1875 | if (min < min_index) | |
1876 | local_min = 0; | |
6feacd09 MM |
1877 | if (!reg_data->used_p) /* page just allocated with calloc */ |
1878 | reg_data->used_p = 1; /* no need to zero */ | |
1879 | else | |
29f63881 RH |
1880 | bzero ((char *) ®_data->data[local_min], |
1881 | sizeof (reg_info) * (max - min_index - local_min + 1)); | |
6feacd09 | 1882 | |
29f63881 | 1883 | for (i = min_index+local_min; i <= max; i++) |
6feacd09 MM |
1884 | { |
1885 | VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; | |
1886 | REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; | |
1887 | renumber[i] = -1; | |
1888 | prefclass_buffer[i] = (char) NO_REGS; | |
1889 | altclass_buffer[i] = (char) NO_REGS; | |
1890 | } | |
1891 | } | |
39379e67 | 1892 | } |
b1f21e0a MM |
1893 | } |
1894 | ||
6feacd09 MM |
1895 | /* If {pref,alt}class have already been allocated, update the pointers to |
1896 | the newly realloced ones. */ | |
1897 | if (prefclass) | |
1898 | { | |
1899 | prefclass = prefclass_buffer; | |
1900 | altclass = altclass_buffer; | |
1901 | } | |
1902 | ||
39379e67 MM |
1903 | if (renumber_p) |
1904 | reg_renumber = renumber; | |
1905 | ||
73b76448 RK |
1906 | /* Tell the regset code about the new number of registers */ |
1907 | MAX_REGNO_REG_SET (num_regs, new_p, renumber_p); | |
b1f21e0a MM |
1908 | } |
1909 | ||
54dac99e RK |
1910 | \f |
1911 | /* This is the `regscan' pass of the compiler, run just before cse | |
1912 | and again just before loop. | |
1913 | ||
1914 | It finds the first and last use of each pseudo-register | |
1915 | and records them in the vectors regno_first_uid, regno_last_uid | |
1916 | and counts the number of sets in the vector reg_n_sets. | |
1917 | ||
1918 | REPEAT is nonzero the second time this is called. */ | |
1919 | ||
54dac99e | 1920 | /* Maximum number of parallel sets and clobbers in any insn in this fn. |
d22d5f34 | 1921 | Always at least 3, since the combiner could put that many together |
54dac99e RK |
1922 | and we want this to remain correct for all the remaining passes. */ |
1923 | ||
1924 | int max_parallel; | |
1925 | ||
54dac99e RK |
1926 | void |
1927 | reg_scan (f, nregs, repeat) | |
1928 | rtx f; | |
1929 | int nregs; | |
1930 | int repeat; | |
1931 | { | |
1932 | register rtx insn; | |
1933 | ||
39379e67 | 1934 | allocate_reg_info (nregs, TRUE, FALSE); |
54dac99e RK |
1935 | max_parallel = 3; |
1936 | ||
1937 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
1938 | if (GET_CODE (insn) == INSN | |
1939 | || GET_CODE (insn) == CALL_INSN | |
1940 | || GET_CODE (insn) == JUMP_INSN) | |
1941 | { | |
1942 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1943 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
1944 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
f903b91f | 1945 | reg_scan_mark_refs (PATTERN (insn), insn, 0, 0); |
01565a55 RK |
1946 | |
1947 | if (REG_NOTES (insn)) | |
f903b91f DM |
1948 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); |
1949 | } | |
1950 | } | |
1951 | ||
1952 | /* Update 'regscan' information by looking at the insns | |
1953 | from FIRST to LAST. Some new REGs have been created, | |
1954 | and any REG with number greater than OLD_MAX_REGNO is | |
1955 | such a REG. We only update information for those. */ | |
1956 | ||
1957 | void | |
1958 | reg_scan_update(first, last, old_max_regno) | |
1959 | rtx first; | |
1960 | rtx last; | |
1961 | int old_max_regno; | |
1962 | { | |
1963 | register rtx insn; | |
1964 | ||
1965 | allocate_reg_info (max_reg_num (), FALSE, FALSE); | |
1966 | ||
1967 | for (insn = first; insn != last; insn = NEXT_INSN (insn)) | |
1968 | if (GET_CODE (insn) == INSN | |
1969 | || GET_CODE (insn) == CALL_INSN | |
1970 | || GET_CODE (insn) == JUMP_INSN) | |
1971 | { | |
1972 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1973 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
1974 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
1975 | reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno); | |
1976 | ||
1977 | if (REG_NOTES (insn)) | |
1978 | reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); | |
54dac99e RK |
1979 | } |
1980 | } | |
1981 | ||
1ebecb64 | 1982 | /* X is the expression to scan. INSN is the insn it appears in. |
f903b91f DM |
1983 | NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. |
1984 | We should only record information for REGs with numbers | |
1985 | greater than or equal to MIN_REGNO. */ | |
1ebecb64 | 1986 | |
08d95f91 | 1987 | static void |
f903b91f | 1988 | reg_scan_mark_refs (x, insn, note_flag, min_regno) |
54dac99e | 1989 | rtx x; |
be8dcd74 | 1990 | rtx insn; |
1ebecb64 | 1991 | int note_flag; |
f903b91f | 1992 | int min_regno; |
54dac99e | 1993 | { |
fa23c636 | 1994 | register enum rtx_code code; |
54dac99e | 1995 | register rtx dest; |
be8dcd74 | 1996 | register rtx note; |
54dac99e | 1997 | |
fa23c636 | 1998 | code = GET_CODE (x); |
54dac99e RK |
1999 | switch (code) |
2000 | { | |
2001 | case CONST_INT: | |
2002 | case CONST: | |
2003 | case CONST_DOUBLE: | |
2004 | case CC0: | |
2005 | case PC: | |
2006 | case SYMBOL_REF: | |
2007 | case LABEL_REF: | |
2008 | case ADDR_VEC: | |
2009 | case ADDR_DIFF_VEC: | |
2010 | return; | |
2011 | ||
2012 | case REG: | |
2013 | { | |
2014 | register int regno = REGNO (x); | |
2015 | ||
f903b91f DM |
2016 | if (regno >= min_regno) |
2017 | { | |
2018 | REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn); | |
2019 | if (!note_flag) | |
2020 | REGNO_LAST_UID (regno) = INSN_UID (insn); | |
2021 | if (REGNO_FIRST_UID (regno) == 0) | |
2022 | REGNO_FIRST_UID (regno) = INSN_UID (insn); | |
2023 | } | |
54dac99e RK |
2024 | } |
2025 | break; | |
2026 | ||
01565a55 | 2027 | case EXPR_LIST: |
7b18c3db | 2028 | if (XEXP (x, 0)) |
f903b91f | 2029 | reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); |
01565a55 | 2030 | if (XEXP (x, 1)) |
f903b91f | 2031 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2032 | break; |
2033 | ||
2034 | case INSN_LIST: | |
2035 | if (XEXP (x, 1)) | |
f903b91f | 2036 | reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); |
01565a55 RK |
2037 | break; |
2038 | ||
54dac99e RK |
2039 | case SET: |
2040 | /* Count a set of the destination if it is a register. */ | |
2041 | for (dest = SET_DEST (x); | |
2042 | GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
2043 | || GET_CODE (dest) == ZERO_EXTEND; | |
2044 | dest = XEXP (dest, 0)) | |
2045 | ; | |
2046 | ||
f903b91f DM |
2047 | if (GET_CODE (dest) == REG |
2048 | && REGNO (dest) >= min_regno) | |
b1f21e0a | 2049 | REG_N_SETS (REGNO (dest))++; |
54dac99e | 2050 | |
be8dcd74 RK |
2051 | /* If this is setting a pseudo from another pseudo or the sum of a |
2052 | pseudo and a constant integer and the other pseudo is known to be | |
2053 | a pointer, set the destination to be a pointer as well. | |
2054 | ||
2055 | Likewise if it is setting the destination from an address or from a | |
2056 | value equivalent to an address or to the sum of an address and | |
2057 | something else. | |
2058 | ||
2059 | But don't do any of this if the pseudo corresponds to a user | |
2060 | variable since it should have already been set as a pointer based | |
2061 | on the type. */ | |
2062 | ||
2063 | if (GET_CODE (SET_DEST (x)) == REG | |
2064 | && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
f903b91f | 2065 | && REGNO (SET_DEST (x)) >= min_regno |
64d3b4ca JL |
2066 | /* If the destination pseudo is set more than once, then other |
2067 | sets might not be to a pointer value (consider access to a | |
2068 | union in two threads of control in the presense of global | |
2069 | optimizations). So only set REGNO_POINTER_FLAG on the destination | |
2070 | pseudo if this is the only set of that pseudo. */ | |
2071 | && REG_N_SETS (REGNO (SET_DEST (x))) == 1 | |
be8dcd74 RK |
2072 | && ! REG_USERVAR_P (SET_DEST (x)) |
2073 | && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) | |
2074 | && ((GET_CODE (SET_SRC (x)) == REG | |
2075 | && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) | |
2076 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2077 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2078 | && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
2079 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
2080 | && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) | |
2081 | || GET_CODE (SET_SRC (x)) == CONST | |
2082 | || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
2083 | || GET_CODE (SET_SRC (x)) == LABEL_REF | |
2084 | || (GET_CODE (SET_SRC (x)) == HIGH | |
2085 | && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
2086 | || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
2087 | || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
2088 | || ((GET_CODE (SET_SRC (x)) == PLUS | |
2089 | || GET_CODE (SET_SRC (x)) == LO_SUM) | |
2090 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
2091 | || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
2092 | || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
2093 | || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
2094 | && (GET_CODE (XEXP (note, 0)) == CONST | |
2095 | || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
2096 | || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
2097 | REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; | |
2098 | ||
0f41302f | 2099 | /* ... fall through ... */ |
54dac99e RK |
2100 | |
2101 | default: | |
2102 | { | |
2103 | register char *fmt = GET_RTX_FORMAT (code); | |
2104 | register int i; | |
2105 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2106 | { | |
2107 | if (fmt[i] == 'e') | |
f903b91f | 2108 | reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); |
54dac99e RK |
2109 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) |
2110 | { | |
2111 | register int j; | |
2112 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
f903b91f | 2113 | reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); |
54dac99e RK |
2114 | } |
2115 | } | |
2116 | } | |
2117 | } | |
2118 | } | |
2119 | \f | |
2120 | /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
2121 | is also in C2. */ | |
2122 | ||
2123 | int | |
2124 | reg_class_subset_p (c1, c2) | |
2125 | register enum reg_class c1; | |
2126 | register enum reg_class c2; | |
2127 | { | |
2128 | if (c1 == c2) return 1; | |
2129 | ||
2130 | if (c2 == ALL_REGS) | |
2131 | win: | |
2132 | return 1; | |
2133 | GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], | |
2134 | reg_class_contents[(int)c2], | |
2135 | win); | |
2136 | return 0; | |
2137 | } | |
2138 | ||
2139 | /* Return nonzero if there is a register that is in both C1 and C2. */ | |
2140 | ||
2141 | int | |
2142 | reg_classes_intersect_p (c1, c2) | |
2143 | register enum reg_class c1; | |
2144 | register enum reg_class c2; | |
2145 | { | |
2146 | #ifdef HARD_REG_SET | |
2147 | register | |
2148 | #endif | |
2149 | HARD_REG_SET c; | |
2150 | ||
2151 | if (c1 == c2) return 1; | |
2152 | ||
2153 | if (c1 == ALL_REGS || c2 == ALL_REGS) | |
2154 | return 1; | |
2155 | ||
2156 | COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); | |
2157 | AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); | |
2158 | ||
2159 | GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); | |
2160 | return 1; | |
2161 | ||
2162 | lose: | |
2163 | return 0; | |
2164 | } | |
2165 | ||
73b76448 RK |
2166 | /* Release any memory allocated by register sets. */ |
2167 | ||
2168 | void | |
2169 | regset_release_memory () | |
2170 | { | |
2171 | if (basic_block_live_at_start) | |
2172 | { | |
2173 | free_regset_vector (basic_block_live_at_start, n_basic_blocks); | |
2174 | basic_block_live_at_start = 0; | |
2175 | } | |
2176 | ||
2177 | FREE_REG_SET (regs_live_at_setjmp); | |
2178 | bitmap_release_memory (); | |
2179 | } |