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Commit | Line | Data |
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8c660648 | 1 | /* Move registers around to reduce number of move instructions needed. |
af841dbd | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
2cc2d4bb | 3 | 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
8c660648 | 4 | |
1322177d | 5 | This file is part of GCC. |
8c660648 | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
8c660648 | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
8c660648 JL |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
8c660648 JL |
21 | |
22 | ||
23 | /* This module looks for cases where matching constraints would force | |
24 | an instruction to need a reload, and this reload would be a register | |
25 | to register move. It then attempts to change the registers used by the | |
26 | instruction to avoid the move instruction. */ | |
27 | ||
28 | #include "config.h" | |
670ee920 | 29 | #include "system.h" |
789f983a | 30 | #include "rtl.h" /* stdio.h must precede rtl.h for FFS. */ |
6baf1cc8 | 31 | #include "tm_p.h" |
8c660648 JL |
32 | #include "insn-config.h" |
33 | #include "recog.h" | |
34 | #include "output.h" | |
8c660648 | 35 | #include "regs.h" |
184bb750 R |
36 | #include "hard-reg-set.h" |
37 | #include "flags.h" | |
49ad7cfa | 38 | #include "function.h" |
184bb750 | 39 | #include "expr.h" |
ddc8bed2 | 40 | #include "basic-block.h" |
1a5428f7 | 41 | #include "except.h" |
2e107e9e | 42 | #include "toplev.h" |
8461e984 | 43 | #include "reload.h" |
184bb750 | 44 | |
595c2290 JH |
45 | |
46 | /* Turn STACK_GROWS_DOWNWARD into a boolean. */ | |
47 | #ifdef STACK_GROWS_DOWNWARD | |
48 | #undef STACK_GROWS_DOWNWARD | |
49 | #define STACK_GROWS_DOWNWARD 1 | |
50 | #else | |
51 | #define STACK_GROWS_DOWNWARD 0 | |
52 | #endif | |
53 | ||
a1c1fdd0 | 54 | static int perhaps_ends_bb_p PARAMS ((rtx)); |
13536812 KG |
55 | static int optimize_reg_copy_1 PARAMS ((rtx, rtx, rtx)); |
56 | static void optimize_reg_copy_2 PARAMS ((rtx, rtx, rtx)); | |
57 | static void optimize_reg_copy_3 PARAMS ((rtx, rtx, rtx)); | |
13536812 | 58 | static void copy_src_to_dest PARAMS ((rtx, rtx, rtx, int)); |
ddc8bed2 | 59 | static int *regmove_bb_head; |
8c660648 | 60 | |
184bb750 R |
61 | struct match { |
62 | int with[MAX_RECOG_OPERANDS]; | |
63 | enum { READ, WRITE, READWRITE } use[MAX_RECOG_OPERANDS]; | |
64 | int commutative[MAX_RECOG_OPERANDS]; | |
65 | int early_clobber[MAX_RECOG_OPERANDS]; | |
66 | }; | |
67 | ||
13536812 KG |
68 | static rtx discover_flags_reg PARAMS ((void)); |
69 | static void mark_flags_life_zones PARAMS ((rtx)); | |
70 | static void flags_set_1 PARAMS ((rtx, rtx, void *)); | |
dc2cb191 | 71 | |
13536812 KG |
72 | static int try_auto_increment PARAMS ((rtx, rtx, rtx, rtx, HOST_WIDE_INT, int)); |
73 | static int find_matches PARAMS ((rtx, struct match *)); | |
ae0ed63a | 74 | static void replace_in_call_usage PARAMS ((rtx *, unsigned int, rtx, rtx)); |
13536812 | 75 | static int fixup_match_1 PARAMS ((rtx, rtx, rtx, rtx, rtx, int, int, int, FILE *)) |
184bb750 | 76 | ; |
13536812 KG |
77 | static int reg_is_remote_constant_p PARAMS ((rtx, rtx, rtx)); |
78 | static int stable_and_no_regs_but_for_p PARAMS ((rtx, rtx, rtx)); | |
79 | static int regclass_compatible_p PARAMS ((int, int)); | |
80 | static int replacement_quality PARAMS ((rtx)); | |
81 | static int fixup_match_2 PARAMS ((rtx, rtx, rtx, rtx, FILE *)); | |
8c660648 | 82 | |
3bb806ed R |
83 | /* Return non-zero if registers with CLASS1 and CLASS2 can be merged without |
84 | causing too much register allocation problems. */ | |
85 | static int | |
86 | regclass_compatible_p (class0, class1) | |
87 | int class0, class1; | |
88 | { | |
89 | return (class0 == class1 | |
90 | || (reg_class_subset_p (class0, class1) | |
91 | && ! CLASS_LIKELY_SPILLED_P (class0)) | |
92 | || (reg_class_subset_p (class1, class0) | |
93 | && ! CLASS_LIKELY_SPILLED_P (class1))); | |
94 | } | |
95 | ||
8c660648 JL |
96 | /* INC_INSN is an instruction that adds INCREMENT to REG. |
97 | Try to fold INC_INSN as a post/pre in/decrement into INSN. | |
98 | Iff INC_INSN_SET is nonzero, inc_insn has a destination different from src. | |
99 | Return nonzero for success. */ | |
100 | static int | |
101 | try_auto_increment (insn, inc_insn, inc_insn_set, reg, increment, pre) | |
102 | rtx reg, insn, inc_insn ,inc_insn_set; | |
103 | HOST_WIDE_INT increment; | |
104 | int pre; | |
105 | { | |
106 | enum rtx_code inc_code; | |
107 | ||
108 | rtx pset = single_set (insn); | |
109 | if (pset) | |
110 | { | |
111 | /* Can't use the size of SET_SRC, we might have something like | |
112 | (sign_extend:SI (mem:QI ... */ | |
113 | rtx use = find_use_as_address (pset, reg, 0); | |
60e8b9f0 | 114 | if (use != 0 && use != (rtx) (size_t) 1) |
8c660648 JL |
115 | { |
116 | int size = GET_MODE_SIZE (GET_MODE (use)); | |
117 | if (0 | |
940da324 JL |
118 | || (HAVE_POST_INCREMENT |
119 | && pre == 0 && (inc_code = POST_INC, increment == size)) | |
120 | || (HAVE_PRE_INCREMENT | |
121 | && pre == 1 && (inc_code = PRE_INC, increment == size)) | |
122 | || (HAVE_POST_DECREMENT | |
123 | && pre == 0 && (inc_code = POST_DEC, increment == -size)) | |
124 | || (HAVE_PRE_DECREMENT | |
125 | && pre == 1 && (inc_code = PRE_DEC, increment == -size)) | |
184bb750 R |
126 | ) |
127 | { | |
128 | if (inc_insn_set) | |
129 | validate_change | |
174fa2c4 | 130 | (inc_insn, |
184bb750 | 131 | &SET_SRC (inc_insn_set), |
8c660648 | 132 | XEXP (SET_SRC (inc_insn_set), 0), 1); |
184bb750 | 133 | validate_change (insn, &XEXP (use, 0), |
38a448ca | 134 | gen_rtx_fmt_e (inc_code, Pmode, reg), 1); |
184bb750 R |
135 | if (apply_change_group ()) |
136 | { | |
2f33c635 HB |
137 | /* If there is a REG_DEAD note on this insn, we must |
138 | change this not to REG_UNUSED meaning that the register | |
139 | is set, but the value is dead. Failure to do so will | |
140 | result in a sched1 abort -- when it recomputes lifetime | |
141 | information, the number of REG_DEAD notes will have | |
142 | changed. */ | |
143 | rtx note = find_reg_note (insn, REG_DEAD, reg); | |
144 | if (note) | |
145 | PUT_MODE (note, REG_UNUSED); | |
146 | ||
184bb750 | 147 | REG_NOTES (insn) |
38a448ca RH |
148 | = gen_rtx_EXPR_LIST (REG_INC, |
149 | reg, REG_NOTES (insn)); | |
184bb750 | 150 | if (! inc_insn_set) |
ca6c03ca | 151 | delete_insn (inc_insn); |
8c660648 | 152 | return 1; |
184bb750 R |
153 | } |
154 | } | |
155 | } | |
156 | } | |
157 | return 0; | |
158 | } | |
dc2cb191 RH |
159 | \f |
160 | /* Determine if the pattern generated by add_optab has a clobber, | |
161 | such as might be issued for a flags hard register. To make the | |
162 | code elsewhere simpler, we handle cc0 in this same framework. | |
163 | ||
164 | Return the register if one was discovered. Return NULL_RTX if | |
165 | if no flags were found. Return pc_rtx if we got confused. */ | |
166 | ||
167 | static rtx | |
168 | discover_flags_reg () | |
169 | { | |
170 | rtx tmp; | |
cd4b3546 | 171 | tmp = gen_rtx_REG (word_mode, 10000); |
dc2cb191 RH |
172 | tmp = gen_add3_insn (tmp, tmp, GEN_INT (2)); |
173 | ||
174fa2c4 | 174 | /* If we get something that isn't a simple set, or a |
dc2cb191 RH |
175 | [(set ..) (clobber ..)], this whole function will go wrong. */ |
176 | if (GET_CODE (tmp) == SET) | |
177 | return NULL_RTX; | |
178 | else if (GET_CODE (tmp) == PARALLEL) | |
179 | { | |
180 | int found; | |
181 | ||
182 | if (XVECLEN (tmp, 0) != 2) | |
183 | return pc_rtx; | |
184 | tmp = XVECEXP (tmp, 0, 1); | |
185 | if (GET_CODE (tmp) != CLOBBER) | |
186 | return pc_rtx; | |
187 | tmp = XEXP (tmp, 0); | |
188 | ||
189 | /* Don't do anything foolish if the md wanted to clobber a | |
190 | scratch or something. We only care about hard regs. | |
191 | Moreover we don't like the notion of subregs of hard regs. */ | |
192 | if (GET_CODE (tmp) == SUBREG | |
193 | && GET_CODE (SUBREG_REG (tmp)) == REG | |
194 | && REGNO (SUBREG_REG (tmp)) < FIRST_PSEUDO_REGISTER) | |
195 | return pc_rtx; | |
196 | found = (GET_CODE (tmp) == REG && REGNO (tmp) < FIRST_PSEUDO_REGISTER); | |
197 | ||
dc2cb191 | 198 | return (found ? tmp : NULL_RTX); |
dc2cb191 RH |
199 | } |
200 | ||
201 | return pc_rtx; | |
202 | } | |
203 | ||
204 | /* It is a tedious task identifying when the flags register is live and | |
205 | when it is safe to optimize. Since we process the instruction stream | |
206 | multiple times, locate and record these live zones by marking the | |
174fa2c4 | 207 | mode of the instructions -- |
dc2cb191 RH |
208 | |
209 | QImode is used on the instruction at which the flags becomes live. | |
210 | ||
211 | HImode is used within the range (exclusive) that the flags are | |
212 | live. Thus the user of the flags is not marked. | |
213 | ||
214 | All other instructions are cleared to VOIDmode. */ | |
215 | ||
216 | /* Used to communicate with flags_set_1. */ | |
217 | static rtx flags_set_1_rtx; | |
218 | static int flags_set_1_set; | |
219 | ||
220 | static void | |
221 | mark_flags_life_zones (flags) | |
222 | rtx flags; | |
223 | { | |
224 | int flags_regno; | |
225 | int flags_nregs; | |
e0082a72 | 226 | basic_block block; |
dc2cb191 | 227 | |
e7f5b971 RH |
228 | #ifdef HAVE_cc0 |
229 | /* If we found a flags register on a cc0 host, bail. */ | |
230 | if (flags == NULL_RTX) | |
231 | flags = cc0_rtx; | |
232 | else if (flags != cc0_rtx) | |
233 | flags = pc_rtx; | |
234 | #endif | |
174fa2c4 | 235 | |
dc2cb191 RH |
236 | /* Simple cases first: if no flags, clear all modes. If confusing, |
237 | mark the entire function as being in a flags shadow. */ | |
238 | if (flags == NULL_RTX || flags == pc_rtx) | |
239 | { | |
240 | enum machine_mode mode = (flags ? HImode : VOIDmode); | |
241 | rtx insn; | |
8e2e89f7 | 242 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
dc2cb191 RH |
243 | PUT_MODE (insn, mode); |
244 | return; | |
245 | } | |
246 | ||
247 | #ifdef HAVE_cc0 | |
248 | flags_regno = -1; | |
249 | flags_nregs = 1; | |
250 | #else | |
251 | flags_regno = REGNO (flags); | |
252 | flags_nregs = HARD_REGNO_NREGS (flags_regno, GET_MODE (flags)); | |
253 | #endif | |
254 | flags_set_1_rtx = flags; | |
184bb750 | 255 | |
dc2cb191 | 256 | /* Process each basic block. */ |
e0082a72 | 257 | FOR_EACH_BB_REVERSE (block) |
dc2cb191 RH |
258 | { |
259 | rtx insn, end; | |
260 | int live; | |
261 | ||
e0082a72 ZD |
262 | insn = block->head; |
263 | end = block->end; | |
dc2cb191 RH |
264 | |
265 | /* Look out for the (unlikely) case of flags being live across | |
266 | basic block boundaries. */ | |
267 | live = 0; | |
268 | #ifndef HAVE_cc0 | |
269 | { | |
270 | int i; | |
271 | for (i = 0; i < flags_nregs; ++i) | |
e0082a72 | 272 | live |= REGNO_REG_SET_P (block->global_live_at_start, |
dc2cb191 RH |
273 | flags_regno + i); |
274 | } | |
275 | #endif | |
276 | ||
277 | while (1) | |
278 | { | |
279 | /* Process liveness in reverse order of importance -- | |
280 | alive, death, birth. This lets more important info | |
281 | overwrite the mode of lesser info. */ | |
282 | ||
2c3c49de | 283 | if (INSN_P (insn)) |
dc2cb191 RH |
284 | { |
285 | #ifdef HAVE_cc0 | |
286 | /* In the cc0 case, death is not marked in reg notes, | |
287 | but is instead the mere use of cc0 when it is alive. */ | |
288 | if (live && reg_mentioned_p (cc0_rtx, PATTERN (insn))) | |
289 | live = 0; | |
290 | #else | |
291 | /* In the hard reg case, we watch death notes. */ | |
292 | if (live && find_regno_note (insn, REG_DEAD, flags_regno)) | |
293 | live = 0; | |
294 | #endif | |
295 | PUT_MODE (insn, (live ? HImode : VOIDmode)); | |
296 | ||
297 | /* In either case, birth is denoted simply by it's presence | |
298 | as the destination of a set. */ | |
299 | flags_set_1_set = 0; | |
84832317 | 300 | note_stores (PATTERN (insn), flags_set_1, NULL); |
dc2cb191 RH |
301 | if (flags_set_1_set) |
302 | { | |
303 | live = 1; | |
304 | PUT_MODE (insn, QImode); | |
305 | } | |
306 | } | |
307 | else | |
308 | PUT_MODE (insn, (live ? HImode : VOIDmode)); | |
309 | ||
310 | if (insn == end) | |
311 | break; | |
312 | insn = NEXT_INSN (insn); | |
313 | } | |
314 | } | |
315 | } | |
316 | ||
317 | /* A subroutine of mark_flags_life_zones, called through note_stores. */ | |
318 | ||
319 | static void | |
84832317 | 320 | flags_set_1 (x, pat, data) |
dc2cb191 | 321 | rtx x, pat; |
84832317 | 322 | void *data ATTRIBUTE_UNUSED; |
dc2cb191 RH |
323 | { |
324 | if (GET_CODE (pat) == SET | |
325 | && reg_overlap_mentioned_p (x, flags_set_1_rtx)) | |
326 | flags_set_1_set = 1; | |
327 | } | |
328 | \f | |
184bb750 R |
329 | static int *regno_src_regno; |
330 | ||
331 | /* Indicate how good a choice REG (which appears as a source) is to replace | |
332 | a destination register with. The higher the returned value, the better | |
333 | the choice. The main objective is to avoid using a register that is | |
334 | a candidate for tying to a hard register, since the output might in | |
335 | turn be a candidate to be tied to a different hard register. */ | |
95d75019 | 336 | static int |
8e2e89f7 | 337 | replacement_quality (reg) |
184bb750 R |
338 | rtx reg; |
339 | { | |
340 | int src_regno; | |
341 | ||
342 | /* Bad if this isn't a register at all. */ | |
343 | if (GET_CODE (reg) != REG) | |
344 | return 0; | |
345 | ||
346 | /* If this register is not meant to get a hard register, | |
347 | it is a poor choice. */ | |
348 | if (REG_LIVE_LENGTH (REGNO (reg)) < 0) | |
349 | return 0; | |
350 | ||
351 | src_regno = regno_src_regno[REGNO (reg)]; | |
352 | ||
353 | /* If it was not copied from another register, it is fine. */ | |
354 | if (src_regno < 0) | |
355 | return 3; | |
356 | ||
357 | /* Copied from a hard register? */ | |
358 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
359 | return 1; | |
360 | ||
361 | /* Copied from a pseudo register - not as bad as from a hard register, | |
362 | yet still cumbersome, since the register live length will be lengthened | |
363 | when the registers get tied. */ | |
364 | return 2; | |
365 | } | |
a1c1fdd0 RK |
366 | \f |
367 | /* Return 1 if INSN might end a basic block. */ | |
368 | ||
369 | static int perhaps_ends_bb_p (insn) | |
370 | rtx insn; | |
371 | { | |
372 | switch (GET_CODE (insn)) | |
373 | { | |
374 | case CODE_LABEL: | |
375 | case JUMP_INSN: | |
376 | /* These always end a basic block. */ | |
377 | return 1; | |
184bb750 | 378 | |
a1c1fdd0 RK |
379 | case CALL_INSN: |
380 | /* A CALL_INSN might be the last insn of a basic block, if it is inside | |
381 | an EH region or if there are nonlocal gotos. Note that this test is | |
382 | very conservative. */ | |
a614d82e RH |
383 | if (nonlocal_goto_handler_labels) |
384 | return 1; | |
385 | /* FALLTHRU */ | |
a1c1fdd0 | 386 | default: |
a614d82e | 387 | return can_throw_internal (insn); |
a1c1fdd0 RK |
388 | } |
389 | } | |
390 | \f | |
1230327b R |
391 | /* INSN is a copy from SRC to DEST, both registers, and SRC does not die |
392 | in INSN. | |
393 | ||
394 | Search forward to see if SRC dies before either it or DEST is modified, | |
395 | but don't scan past the end of a basic block. If so, we can replace SRC | |
174fa2c4 | 396 | with DEST and let SRC die in INSN. |
1230327b R |
397 | |
398 | This will reduce the number of registers live in that range and may enable | |
399 | DEST to be tied to SRC, thus often saving one register in addition to a | |
400 | register-register copy. */ | |
401 | ||
402 | static int | |
403 | optimize_reg_copy_1 (insn, dest, src) | |
404 | rtx insn; | |
405 | rtx dest; | |
406 | rtx src; | |
407 | { | |
408 | rtx p, q; | |
409 | rtx note; | |
410 | rtx dest_death = 0; | |
411 | int sregno = REGNO (src); | |
412 | int dregno = REGNO (dest); | |
413 | ||
dc297297 | 414 | /* We don't want to mess with hard regs if register classes are small. */ |
1230327b R |
415 | if (sregno == dregno |
416 | || (SMALL_REGISTER_CLASSES | |
417 | && (sregno < FIRST_PSEUDO_REGISTER | |
418 | || dregno < FIRST_PSEUDO_REGISTER)) | |
419 | /* We don't see all updates to SP if they are in an auto-inc memory | |
420 | reference, so we must disallow this optimization on them. */ | |
421 | || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM) | |
422 | return 0; | |
423 | ||
424 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
425 | { | |
7bf825d2 | 426 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 RK |
427 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
428 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 429 | break; |
a1c1fdd0 | 430 | else if (! INSN_P (p)) |
1230327b R |
431 | continue; |
432 | ||
433 | if (reg_set_p (src, p) || reg_set_p (dest, p) | |
434 | /* Don't change a USE of a register. */ | |
435 | || (GET_CODE (PATTERN (p)) == USE | |
436 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
437 | break; | |
438 | ||
439 | /* See if all of SRC dies in P. This test is slightly more | |
440 | conservative than it needs to be. */ | |
441 | if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0 | |
442 | && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) | |
443 | { | |
444 | int failed = 0; | |
1230327b | 445 | int d_length = 0; |
89098dc1 | 446 | int s_length = 0; |
1230327b | 447 | int d_n_calls = 0; |
89098dc1 | 448 | int s_n_calls = 0; |
1230327b R |
449 | |
450 | /* We can do the optimization. Scan forward from INSN again, | |
451 | replacing regs as we go. Set FAILED if a replacement can't | |
452 | be done. In that case, we can't move the death note for SRC. | |
453 | This should be rare. */ | |
454 | ||
455 | /* Set to stop at next insn. */ | |
456 | for (q = next_real_insn (insn); | |
457 | q != next_real_insn (p); | |
458 | q = next_real_insn (q)) | |
459 | { | |
460 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
461 | { | |
462 | /* If SRC is a hard register, we might miss some | |
463 | overlapping registers with validate_replace_rtx, | |
464 | so we would have to undo it. We can't if DEST is | |
465 | present in the insn, so fail in that combination | |
466 | of cases. */ | |
467 | if (sregno < FIRST_PSEUDO_REGISTER | |
468 | && reg_mentioned_p (dest, PATTERN (q))) | |
469 | failed = 1; | |
470 | ||
471 | /* Replace all uses and make sure that the register | |
472 | isn't still present. */ | |
473 | else if (validate_replace_rtx (src, dest, q) | |
474 | && (sregno >= FIRST_PSEUDO_REGISTER | |
475 | || ! reg_overlap_mentioned_p (src, | |
476 | PATTERN (q)))) | |
1b7c4a37 | 477 | ; |
1230327b R |
478 | else |
479 | { | |
480 | validate_replace_rtx (dest, src, q); | |
481 | failed = 1; | |
482 | } | |
483 | } | |
484 | ||
89098dc1 JL |
485 | /* For SREGNO, count the total number of insns scanned. |
486 | For DREGNO, count the total number of insns scanned after | |
487 | passing the death note for DREGNO. */ | |
488 | s_length++; | |
1230327b R |
489 | if (dest_death) |
490 | d_length++; | |
491 | ||
492 | /* If the insn in which SRC dies is a CALL_INSN, don't count it | |
493 | as a call that has been crossed. Otherwise, count it. */ | |
494 | if (q != p && GET_CODE (q) == CALL_INSN) | |
495 | { | |
89098dc1 JL |
496 | /* Similarly, total calls for SREGNO, total calls beyond |
497 | the death note for DREGNO. */ | |
498 | s_n_calls++; | |
1230327b R |
499 | if (dest_death) |
500 | d_n_calls++; | |
501 | } | |
502 | ||
503 | /* If DEST dies here, remove the death note and save it for | |
504 | later. Make sure ALL of DEST dies here; again, this is | |
505 | overly conservative. */ | |
506 | if (dest_death == 0 | |
507 | && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0) | |
508 | { | |
509 | if (GET_MODE (XEXP (dest_death, 0)) != GET_MODE (dest)) | |
510 | failed = 1, dest_death = 0; | |
511 | else | |
512 | remove_note (q, dest_death); | |
513 | } | |
514 | } | |
515 | ||
516 | if (! failed) | |
517 | { | |
89098dc1 JL |
518 | /* These counters need to be updated if and only if we are |
519 | going to move the REG_DEAD note. */ | |
1230327b R |
520 | if (sregno >= FIRST_PSEUDO_REGISTER) |
521 | { | |
522 | if (REG_LIVE_LENGTH (sregno) >= 0) | |
523 | { | |
89098dc1 | 524 | REG_LIVE_LENGTH (sregno) -= s_length; |
1230327b R |
525 | /* REG_LIVE_LENGTH is only an approximation after |
526 | combine if sched is not run, so make sure that we | |
527 | still have a reasonable value. */ | |
528 | if (REG_LIVE_LENGTH (sregno) < 2) | |
529 | REG_LIVE_LENGTH (sregno) = 2; | |
530 | } | |
531 | ||
89098dc1 | 532 | REG_N_CALLS_CROSSED (sregno) -= s_n_calls; |
1230327b R |
533 | } |
534 | ||
535 | /* Move death note of SRC from P to INSN. */ | |
536 | remove_note (p, note); | |
537 | XEXP (note, 1) = REG_NOTES (insn); | |
538 | REG_NOTES (insn) = note; | |
539 | } | |
540 | ||
124d535f JW |
541 | /* DEST is also dead if INSN has a REG_UNUSED note for DEST. */ |
542 | if (! dest_death | |
543 | && (dest_death = find_regno_note (insn, REG_UNUSED, dregno))) | |
544 | { | |
545 | PUT_REG_NOTE_KIND (dest_death, REG_DEAD); | |
546 | remove_note (insn, dest_death); | |
547 | } | |
548 | ||
1230327b R |
549 | /* Put death note of DEST on P if we saw it die. */ |
550 | if (dest_death) | |
551 | { | |
552 | XEXP (dest_death, 1) = REG_NOTES (p); | |
553 | REG_NOTES (p) = dest_death; | |
89098dc1 JL |
554 | |
555 | if (dregno >= FIRST_PSEUDO_REGISTER) | |
556 | { | |
557 | /* If and only if we are moving the death note for DREGNO, | |
558 | then we need to update its counters. */ | |
559 | if (REG_LIVE_LENGTH (dregno) >= 0) | |
560 | REG_LIVE_LENGTH (dregno) += d_length; | |
561 | REG_N_CALLS_CROSSED (dregno) += d_n_calls; | |
562 | } | |
1230327b R |
563 | } |
564 | ||
565 | return ! failed; | |
566 | } | |
567 | ||
568 | /* If SRC is a hard register which is set or killed in some other | |
569 | way, we can't do this optimization. */ | |
570 | else if (sregno < FIRST_PSEUDO_REGISTER | |
571 | && dead_or_set_p (p, src)) | |
572 | break; | |
573 | } | |
574 | return 0; | |
575 | } | |
576 | \f | |
577 | /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have | |
578 | a sequence of insns that modify DEST followed by an insn that sets | |
579 | SRC to DEST in which DEST dies, with no prior modification of DEST. | |
580 | (There is no need to check if the insns in between actually modify | |
581 | DEST. We should not have cases where DEST is not modified, but | |
582 | the optimization is safe if no such modification is detected.) | |
583 | In that case, we can replace all uses of DEST, starting with INSN and | |
584 | ending with the set of SRC to DEST, with SRC. We do not do this | |
585 | optimization if a CALL_INSN is crossed unless SRC already crosses a | |
586 | call or if DEST dies before the copy back to SRC. | |
587 | ||
588 | It is assumed that DEST and SRC are pseudos; it is too complicated to do | |
589 | this for hard registers since the substitutions we may make might fail. */ | |
590 | ||
591 | static void | |
592 | optimize_reg_copy_2 (insn, dest, src) | |
593 | rtx insn; | |
594 | rtx dest; | |
595 | rtx src; | |
596 | { | |
597 | rtx p, q; | |
598 | rtx set; | |
599 | int sregno = REGNO (src); | |
600 | int dregno = REGNO (dest); | |
601 | ||
602 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
603 | { | |
7bf825d2 | 604 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 RK |
605 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
606 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 607 | break; |
a1c1fdd0 | 608 | else if (! INSN_P (p)) |
1230327b R |
609 | continue; |
610 | ||
611 | set = single_set (p); | |
612 | if (set && SET_SRC (set) == dest && SET_DEST (set) == src | |
613 | && find_reg_note (p, REG_DEAD, dest)) | |
614 | { | |
615 | /* We can do the optimization. Scan forward from INSN again, | |
616 | replacing regs as we go. */ | |
617 | ||
618 | /* Set to stop at next insn. */ | |
619 | for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q)) | |
2c3c49de | 620 | if (INSN_P (q)) |
1230327b R |
621 | { |
622 | if (reg_mentioned_p (dest, PATTERN (q))) | |
1b7c4a37 | 623 | PATTERN (q) = replace_rtx (PATTERN (q), dest, src); |
1230327b R |
624 | |
625 | ||
626 | if (GET_CODE (q) == CALL_INSN) | |
627 | { | |
628 | REG_N_CALLS_CROSSED (dregno)--; | |
629 | REG_N_CALLS_CROSSED (sregno)++; | |
630 | } | |
631 | } | |
632 | ||
633 | remove_note (p, find_reg_note (p, REG_DEAD, dest)); | |
634 | REG_N_DEATHS (dregno)--; | |
635 | remove_note (insn, find_reg_note (insn, REG_DEAD, src)); | |
636 | REG_N_DEATHS (sregno)--; | |
637 | return; | |
638 | } | |
639 | ||
640 | if (reg_set_p (src, p) | |
641 | || find_reg_note (p, REG_DEAD, dest) | |
642 | || (GET_CODE (p) == CALL_INSN && REG_N_CALLS_CROSSED (sregno) == 0)) | |
643 | break; | |
644 | } | |
645 | } | |
184bb750 R |
646 | /* INSN is a ZERO_EXTEND or SIGN_EXTEND of SRC to DEST. |
647 | Look if SRC dies there, and if it is only set once, by loading | |
648 | it from memory. If so, try to encorporate the zero/sign extension | |
649 | into the memory read, change SRC to the mode of DEST, and alter | |
650 | the remaining accesses to use the appropriate SUBREG. This allows | |
651 | SRC and DEST to be tied later. */ | |
652 | static void | |
653 | optimize_reg_copy_3 (insn, dest, src) | |
654 | rtx insn; | |
655 | rtx dest; | |
656 | rtx src; | |
657 | { | |
658 | rtx src_reg = XEXP (src, 0); | |
659 | int src_no = REGNO (src_reg); | |
660 | int dst_no = REGNO (dest); | |
661 | rtx p, set, subreg; | |
662 | enum machine_mode old_mode; | |
663 | ||
664 | if (src_no < FIRST_PSEUDO_REGISTER | |
665 | || dst_no < FIRST_PSEUDO_REGISTER | |
666 | || ! find_reg_note (insn, REG_DEAD, src_reg) | |
667 | || REG_N_SETS (src_no) != 1) | |
668 | return; | |
9c07e479 | 669 | for (p = PREV_INSN (insn); p && ! reg_set_p (src_reg, p); p = PREV_INSN (p)) |
a1c1fdd0 RK |
670 | /* ??? We can't scan past the end of a basic block without updating |
671 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ | |
672 | if (perhaps_ends_bb_p (p)) | |
673 | break; | |
7bf825d2 | 674 | |
9c07e479 BK |
675 | if (! p) |
676 | return; | |
677 | ||
184bb750 R |
678 | if (! (set = single_set (p)) |
679 | || GET_CODE (SET_SRC (set)) != MEM | |
4fb3cbd7 BS |
680 | /* If there's a REG_EQUIV note, this must be an insn that loads an |
681 | argument. Prefer keeping the note over doing this optimization. */ | |
682 | || find_reg_note (p, REG_EQUIV, NULL_RTX) | |
184bb750 R |
683 | || SET_DEST (set) != src_reg) |
684 | return; | |
937e37cc | 685 | |
972b320c R |
686 | /* Be conserative: although this optimization is also valid for |
687 | volatile memory references, that could cause trouble in later passes. */ | |
688 | if (MEM_VOLATILE_P (SET_SRC (set))) | |
689 | return; | |
690 | ||
937e37cc JL |
691 | /* Do not use a SUBREG to truncate from one mode to another if truncation |
692 | is not a nop. */ | |
693 | if (GET_MODE_BITSIZE (GET_MODE (src_reg)) <= GET_MODE_BITSIZE (GET_MODE (src)) | |
694 | && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (src)), | |
695 | GET_MODE_BITSIZE (GET_MODE (src_reg)))) | |
696 | return; | |
697 | ||
184bb750 R |
698 | old_mode = GET_MODE (src_reg); |
699 | PUT_MODE (src_reg, GET_MODE (src)); | |
700 | XEXP (src, 0) = SET_SRC (set); | |
e757da5e JL |
701 | |
702 | /* Include this change in the group so that it's easily undone if | |
703 | one of the changes in the group is invalid. */ | |
704 | validate_change (p, &SET_SRC (set), src, 1); | |
705 | ||
706 | /* Now walk forward making additional replacements. We want to be able | |
707 | to undo all the changes if a later substitution fails. */ | |
ddef6bc7 | 708 | subreg = gen_lowpart_SUBREG (old_mode, src_reg); |
184bb750 R |
709 | while (p = NEXT_INSN (p), p != insn) |
710 | { | |
2c3c49de | 711 | if (! INSN_P (p)) |
184bb750 | 712 | continue; |
e757da5e JL |
713 | |
714 | /* Make a tenative change. */ | |
715 | validate_replace_rtx_group (src_reg, subreg, p); | |
716 | } | |
717 | ||
718 | validate_replace_rtx_group (src, src_reg, insn); | |
719 | ||
720 | /* Now see if all the changes are valid. */ | |
721 | if (! apply_change_group ()) | |
722 | { | |
723 | /* One or more changes were no good. Back out everything. */ | |
724 | PUT_MODE (src_reg, old_mode); | |
725 | XEXP (src, 0) = src_reg; | |
184bb750 | 726 | } |
4fb3cbd7 BS |
727 | else |
728 | { | |
729 | rtx note = find_reg_note (p, REG_EQUAL, NULL_RTX); | |
730 | if (note) | |
731 | remove_note (p, note); | |
732 | } | |
184bb750 R |
733 | } |
734 | ||
ddc8bed2 MM |
735 | \f |
736 | /* If we were not able to update the users of src to use dest directly, try | |
737 | instead moving the value to dest directly before the operation. */ | |
738 | ||
cab634f2 | 739 | static void |
1b7c4a37 | 740 | copy_src_to_dest (insn, src, dest, old_max_uid) |
ddc8bed2 MM |
741 | rtx insn; |
742 | rtx src; | |
743 | rtx dest; | |
78dd9906 | 744 | int old_max_uid; |
ddc8bed2 MM |
745 | { |
746 | rtx seq; | |
747 | rtx link; | |
748 | rtx next; | |
749 | rtx set; | |
750 | rtx move_insn; | |
751 | rtx *p_insn_notes; | |
752 | rtx *p_move_notes; | |
ddc8bed2 MM |
753 | int src_regno; |
754 | int dest_regno; | |
755 | int bb; | |
756 | int insn_uid; | |
757 | int move_uid; | |
758 | ||
759 | /* A REG_LIVE_LENGTH of -1 indicates the register is equivalent to a constant | |
760 | or memory location and is used infrequently; a REG_LIVE_LENGTH of -2 is | |
761 | parameter when there is no frame pointer that is not allocated a register. | |
762 | For now, we just reject them, rather than incrementing the live length. */ | |
763 | ||
3ac3da71 MM |
764 | if (GET_CODE (src) == REG |
765 | && REG_LIVE_LENGTH (REGNO (src)) > 0 | |
766 | && GET_CODE (dest) == REG | |
40546a78 | 767 | && !RTX_UNCHANGING_P (dest) |
3ac3da71 | 768 | && REG_LIVE_LENGTH (REGNO (dest)) > 0 |
ddc8bed2 | 769 | && (set = single_set (insn)) != NULL_RTX |
9d2106a4 R |
770 | && !reg_mentioned_p (dest, SET_SRC (set)) |
771 | && GET_MODE (src) == GET_MODE (dest)) | |
ddc8bed2 | 772 | { |
1a8fca8a R |
773 | int old_num_regs = reg_rtx_no; |
774 | ||
ddc8bed2 MM |
775 | /* Generate the src->dest move. */ |
776 | start_sequence (); | |
777 | emit_move_insn (dest, src); | |
2f937369 | 778 | seq = get_insns (); |
ddc8bed2 | 779 | end_sequence (); |
1a8fca8a R |
780 | /* If this sequence uses new registers, we may not use it. */ |
781 | if (old_num_regs != reg_rtx_no | |
782 | || ! validate_replace_rtx (src, dest, insn)) | |
783 | { | |
784 | /* We have to restore reg_rtx_no to its old value, lest | |
785 | recompute_reg_usage will try to compute the usage of the | |
786 | new regs, yet reg_n_info is not valid for them. */ | |
787 | reg_rtx_no = old_num_regs; | |
788 | return; | |
789 | } | |
ddc8bed2 MM |
790 | emit_insn_before (seq, insn); |
791 | move_insn = PREV_INSN (insn); | |
792 | p_move_notes = ®_NOTES (move_insn); | |
793 | p_insn_notes = ®_NOTES (insn); | |
794 | ||
795 | /* Move any notes mentioning src to the move instruction */ | |
796 | for (link = REG_NOTES (insn); link != NULL_RTX; link = next) | |
797 | { | |
798 | next = XEXP (link, 1); | |
799 | if (XEXP (link, 0) == src) | |
800 | { | |
801 | *p_move_notes = link; | |
802 | p_move_notes = &XEXP (link, 1); | |
803 | } | |
804 | else | |
805 | { | |
806 | *p_insn_notes = link; | |
807 | p_insn_notes = &XEXP (link, 1); | |
808 | } | |
809 | } | |
810 | ||
811 | *p_move_notes = NULL_RTX; | |
812 | *p_insn_notes = NULL_RTX; | |
813 | ||
814 | /* Is the insn the head of a basic block? If so extend it */ | |
815 | insn_uid = INSN_UID (insn); | |
816 | move_uid = INSN_UID (move_insn); | |
78dd9906 | 817 | if (insn_uid < old_max_uid) |
ddc8bed2 | 818 | { |
78dd9906 R |
819 | bb = regmove_bb_head[insn_uid]; |
820 | if (bb >= 0) | |
821 | { | |
822 | BLOCK_HEAD (bb) = move_insn; | |
823 | regmove_bb_head[insn_uid] = -1; | |
824 | } | |
ddc8bed2 MM |
825 | } |
826 | ||
827 | /* Update the various register tables. */ | |
828 | dest_regno = REGNO (dest); | |
1b7c4a37 | 829 | REG_N_SETS (dest_regno) ++; |
ddc8bed2 MM |
830 | REG_LIVE_LENGTH (dest_regno)++; |
831 | if (REGNO_FIRST_UID (dest_regno) == insn_uid) | |
832 | REGNO_FIRST_UID (dest_regno) = move_uid; | |
833 | ||
834 | src_regno = REGNO (src); | |
835 | if (! find_reg_note (move_insn, REG_DEAD, src)) | |
836 | REG_LIVE_LENGTH (src_regno)++; | |
837 | ||
838 | if (REGNO_FIRST_UID (src_regno) == insn_uid) | |
839 | REGNO_FIRST_UID (src_regno) = move_uid; | |
840 | ||
841 | if (REGNO_LAST_UID (src_regno) == insn_uid) | |
842 | REGNO_LAST_UID (src_regno) = move_uid; | |
843 | ||
844 | if (REGNO_LAST_NOTE_UID (src_regno) == insn_uid) | |
845 | REGNO_LAST_NOTE_UID (src_regno) = move_uid; | |
846 | } | |
847 | } | |
848 | ||
849 | \f | |
184bb750 R |
850 | /* Return whether REG is set in only one location, and is set to a |
851 | constant, but is set in a different basic block from INSN (an | |
852 | instructions which uses REG). In this case REG is equivalent to a | |
853 | constant, and we don't want to break that equivalence, because that | |
854 | may increase register pressure and make reload harder. If REG is | |
855 | set in the same basic block as INSN, we don't worry about it, | |
856 | because we'll probably need a register anyhow (??? but what if REG | |
857 | is used in a different basic block as well as this one?). FIRST is | |
858 | the first insn in the function. */ | |
859 | ||
860 | static int | |
861 | reg_is_remote_constant_p (reg, insn, first) | |
862 | rtx reg; | |
863 | rtx insn; | |
864 | rtx first; | |
865 | { | |
b3694847 | 866 | rtx p; |
184bb750 R |
867 | |
868 | if (REG_N_SETS (REGNO (reg)) != 1) | |
869 | return 0; | |
870 | ||
871 | /* Look for the set. */ | |
872 | for (p = LOG_LINKS (insn); p; p = XEXP (p, 1)) | |
873 | { | |
874 | rtx s; | |
875 | ||
876 | if (REG_NOTE_KIND (p) != 0) | |
877 | continue; | |
878 | s = single_set (XEXP (p, 0)); | |
879 | if (s != 0 | |
880 | && GET_CODE (SET_DEST (s)) == REG | |
881 | && REGNO (SET_DEST (s)) == REGNO (reg)) | |
882 | { | |
883 | /* The register is set in the same basic block. */ | |
884 | return 0; | |
885 | } | |
886 | } | |
887 | ||
888 | for (p = first; p && p != insn; p = NEXT_INSN (p)) | |
889 | { | |
890 | rtx s; | |
891 | ||
2c3c49de | 892 | if (! INSN_P (p)) |
184bb750 R |
893 | continue; |
894 | s = single_set (p); | |
895 | if (s != 0 | |
896 | && GET_CODE (SET_DEST (s)) == REG | |
897 | && REGNO (SET_DEST (s)) == REGNO (reg)) | |
898 | { | |
899 | /* This is the instruction which sets REG. If there is a | |
900 | REG_EQUAL note, then REG is equivalent to a constant. */ | |
901 | if (find_reg_note (p, REG_EQUAL, NULL_RTX)) | |
902 | return 1; | |
903 | return 0; | |
904 | } | |
905 | } | |
906 | ||
907 | return 0; | |
908 | } | |
909 | ||
b1a7d591 JW |
910 | /* INSN is adding a CONST_INT to a REG. We search backwards looking for |
911 | another add immediate instruction with the same source and dest registers, | |
912 | and if we find one, we change INSN to an increment, and return 1. If | |
913 | no changes are made, we return 0. | |
914 | ||
915 | This changes | |
916 | (set (reg100) (plus reg1 offset1)) | |
917 | ... | |
918 | (set (reg100) (plus reg1 offset2)) | |
919 | to | |
920 | (set (reg100) (plus reg1 offset1)) | |
921 | ... | |
922 | (set (reg100) (plus reg100 offset2-offset1)) */ | |
923 | ||
924 | /* ??? What does this comment mean? */ | |
184bb750 R |
925 | /* cse disrupts preincrement / postdecrement squences when it finds a |
926 | hard register as ultimate source, like the frame pointer. */ | |
b1a7d591 | 927 | |
95d75019 | 928 | static int |
7bf825d2 | 929 | fixup_match_2 (insn, dst, src, offset, regmove_dump_file) |
184bb750 R |
930 | rtx insn, dst, src, offset; |
931 | FILE *regmove_dump_file; | |
932 | { | |
933 | rtx p, dst_death = 0; | |
934 | int length, num_calls = 0; | |
935 | ||
936 | /* If SRC dies in INSN, we'd have to move the death note. This is | |
937 | considered to be very unlikely, so we just skip the optimization | |
938 | in this case. */ | |
939 | if (find_regno_note (insn, REG_DEAD, REGNO (src))) | |
940 | return 0; | |
941 | ||
942 | /* Scan backward to find the first instruction that sets DST. */ | |
943 | ||
944 | for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
945 | { | |
946 | rtx pset; | |
947 | ||
7bf825d2 | 948 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 RK |
949 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
950 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 951 | break; |
a1c1fdd0 | 952 | else if (! INSN_P (p)) |
a6a2274a | 953 | continue; |
184bb750 | 954 | |
7bf825d2 JW |
955 | if (find_regno_note (p, REG_DEAD, REGNO (dst))) |
956 | dst_death = p; | |
957 | if (! dst_death) | |
958 | length++; | |
184bb750 R |
959 | |
960 | pset = single_set (p); | |
961 | if (pset && SET_DEST (pset) == dst | |
962 | && GET_CODE (SET_SRC (pset)) == PLUS | |
963 | && XEXP (SET_SRC (pset), 0) == src | |
964 | && GET_CODE (XEXP (SET_SRC (pset), 1)) == CONST_INT) | |
a6a2274a | 965 | { |
184bb750 R |
966 | HOST_WIDE_INT newconst |
967 | = INTVAL (offset) - INTVAL (XEXP (SET_SRC (pset), 1)); | |
1a29f703 R |
968 | rtx add = gen_add3_insn (dst, dst, GEN_INT (newconst)); |
969 | ||
970 | if (add && validate_change (insn, &PATTERN (insn), add, 0)) | |
184bb750 R |
971 | { |
972 | /* Remove the death note for DST from DST_DEATH. */ | |
973 | if (dst_death) | |
974 | { | |
975 | remove_death (REGNO (dst), dst_death); | |
976 | REG_LIVE_LENGTH (REGNO (dst)) += length; | |
977 | REG_N_CALLS_CROSSED (REGNO (dst)) += num_calls; | |
978 | } | |
979 | ||
184bb750 R |
980 | if (regmove_dump_file) |
981 | fprintf (regmove_dump_file, | |
982 | "Fixed operand of insn %d.\n", | |
983 | INSN_UID (insn)); | |
984 | ||
985 | #ifdef AUTO_INC_DEC | |
986 | for (p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
987 | { | |
988 | if (GET_CODE (p) == CODE_LABEL | |
07aaad94 | 989 | || GET_CODE (p) == JUMP_INSN) |
184bb750 | 990 | break; |
2c3c49de | 991 | if (! INSN_P (p)) |
e27a5106 | 992 | continue; |
184bb750 R |
993 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) |
994 | { | |
995 | if (try_auto_increment (p, insn, 0, dst, newconst, 0)) | |
996 | return 1; | |
997 | break; | |
998 | } | |
999 | } | |
1000 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
1001 | { | |
1002 | if (GET_CODE (p) == CODE_LABEL | |
07aaad94 | 1003 | || GET_CODE (p) == JUMP_INSN) |
184bb750 | 1004 | break; |
2c3c49de | 1005 | if (! INSN_P (p)) |
8543c01e | 1006 | continue; |
184bb750 R |
1007 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) |
1008 | { | |
1009 | try_auto_increment (p, insn, 0, dst, newconst, 1); | |
1010 | break; | |
1011 | } | |
1012 | } | |
1013 | #endif | |
1014 | return 1; | |
1015 | } | |
a6a2274a | 1016 | } |
184bb750 R |
1017 | |
1018 | if (reg_set_p (dst, PATTERN (p))) | |
a6a2274a | 1019 | break; |
184bb750 R |
1020 | |
1021 | /* If we have passed a call instruction, and the | |
1022 | pseudo-reg SRC is not already live across a call, | |
1023 | then don't perform the optimization. */ | |
1024 | /* reg_set_p is overly conservative for CALL_INSNS, thinks that all | |
1025 | hard regs are clobbered. Thus, we only use it for src for | |
1026 | non-call insns. */ | |
1027 | if (GET_CODE (p) == CALL_INSN) | |
a6a2274a | 1028 | { |
184bb750 R |
1029 | if (! dst_death) |
1030 | num_calls++; | |
1031 | ||
a6a2274a KH |
1032 | if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) |
1033 | break; | |
184bb750 R |
1034 | |
1035 | if (call_used_regs [REGNO (dst)] | |
1036 | || find_reg_fusage (p, CLOBBER, dst)) | |
1037 | break; | |
a6a2274a | 1038 | } |
184bb750 | 1039 | else if (reg_set_p (src, PATTERN (p))) |
a6a2274a | 1040 | break; |
8c660648 | 1041 | } |
184bb750 | 1042 | |
8c660648 JL |
1043 | return 0; |
1044 | } | |
8c660648 | 1045 | |
3721581a JJ |
1046 | /* Main entry for the register move optimization. |
1047 | F is the first instruction. | |
1048 | NREGS is one plus the highest pseudo-reg number used in the instruction. | |
1049 | REGMOVE_DUMP_FILE is a stream for output of a trace of actions taken | |
1050 | (or 0 if none should be output). */ | |
1051 | ||
8c660648 JL |
1052 | void |
1053 | regmove_optimize (f, nregs, regmove_dump_file) | |
1054 | rtx f; | |
1055 | int nregs; | |
1056 | FILE *regmove_dump_file; | |
1057 | { | |
961d4119 | 1058 | int old_max_uid = get_max_uid (); |
8c660648 | 1059 | rtx insn; |
184bb750 | 1060 | struct match match; |
8c660648 | 1061 | int pass; |
3bb806ed | 1062 | int i; |
ddc8bed2 | 1063 | rtx copy_src, copy_dst; |
e0082a72 | 1064 | basic_block bb; |
184bb750 | 1065 | |
a614d82e RH |
1066 | /* ??? Hack. Regmove doesn't examine the CFG, and gets mightily |
1067 | confused by non-call exceptions ending blocks. */ | |
1068 | if (flag_non_call_exceptions) | |
1069 | return; | |
1070 | ||
dc2cb191 RH |
1071 | /* Find out where a potential flags register is live, and so that we |
1072 | can supress some optimizations in those zones. */ | |
1073 | mark_flags_life_zones (discover_flags_reg ()); | |
1074 | ||
4da896b2 | 1075 | regno_src_regno = (int *) xmalloc (sizeof *regno_src_regno * nregs); |
3bb806ed | 1076 | for (i = nregs; --i >= 0; ) regno_src_regno[i] = -1; |
8c660648 | 1077 | |
4da896b2 | 1078 | regmove_bb_head = (int *) xmalloc (sizeof (int) * (old_max_uid + 1)); |
961d4119 | 1079 | for (i = old_max_uid; i >= 0; i--) regmove_bb_head[i] = -1; |
e0082a72 ZD |
1080 | FOR_EACH_BB (bb) |
1081 | regmove_bb_head[INSN_UID (bb->head)] = bb->index; | |
ddc8bed2 | 1082 | |
8c660648 JL |
1083 | /* A forward/backward pass. Replace output operands with input operands. */ |
1084 | ||
184bb750 | 1085 | for (pass = 0; pass <= 2; pass++) |
8c660648 | 1086 | { |
184bb750 | 1087 | if (! flag_regmove && pass >= flag_expensive_optimizations) |
4da896b2 | 1088 | goto done; |
184bb750 | 1089 | |
8c660648 JL |
1090 | if (regmove_dump_file) |
1091 | fprintf (regmove_dump_file, "Starting %s pass...\n", | |
1092 | pass ? "backward" : "forward"); | |
1093 | ||
1094 | for (insn = pass ? get_last_insn () : f; insn; | |
1095 | insn = pass ? PREV_INSN (insn) : NEXT_INSN (insn)) | |
1096 | { | |
184bb750 | 1097 | rtx set; |
0eadeb15 | 1098 | int op_no, match_no; |
184bb750 | 1099 | |
184bb750 R |
1100 | set = single_set (insn); |
1101 | if (! set) | |
1102 | continue; | |
8c660648 | 1103 | |
184bb750 R |
1104 | if (flag_expensive_optimizations && ! pass |
1105 | && (GET_CODE (SET_SRC (set)) == SIGN_EXTEND | |
1106 | || GET_CODE (SET_SRC (set)) == ZERO_EXTEND) | |
1107 | && GET_CODE (XEXP (SET_SRC (set), 0)) == REG | |
8e2e89f7 | 1108 | && GET_CODE (SET_DEST (set)) == REG) |
184bb750 R |
1109 | optimize_reg_copy_3 (insn, SET_DEST (set), SET_SRC (set)); |
1110 | ||
1111 | if (flag_expensive_optimizations && ! pass | |
1112 | && GET_CODE (SET_SRC (set)) == REG | |
8e2e89f7 | 1113 | && GET_CODE (SET_DEST (set)) == REG) |
184bb750 R |
1114 | { |
1115 | /* If this is a register-register copy where SRC is not dead, | |
1116 | see if we can optimize it. If this optimization succeeds, | |
1117 | it will become a copy where SRC is dead. */ | |
1118 | if ((find_reg_note (insn, REG_DEAD, SET_SRC (set)) | |
1119 | || optimize_reg_copy_1 (insn, SET_DEST (set), SET_SRC (set))) | |
1120 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) | |
8c660648 | 1121 | { |
184bb750 R |
1122 | /* Similarly for a pseudo-pseudo copy when SRC is dead. */ |
1123 | if (REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1124 | optimize_reg_copy_2 (insn, SET_DEST (set), SET_SRC (set)); | |
1125 | if (regno_src_regno[REGNO (SET_DEST (set))] < 0 | |
1126 | && SET_SRC (set) != SET_DEST (set)) | |
8c660648 | 1127 | { |
8e2e89f7 | 1128 | int srcregno = REGNO (SET_SRC (set)); |
184bb750 R |
1129 | if (regno_src_regno[srcregno] >= 0) |
1130 | srcregno = regno_src_regno[srcregno]; | |
1131 | regno_src_regno[REGNO (SET_DEST (set))] = srcregno; | |
8c660648 JL |
1132 | } |
1133 | } | |
184bb750 | 1134 | } |
a6a2274a KH |
1135 | if (! flag_regmove) |
1136 | continue; | |
184bb750 | 1137 | |
3363316f | 1138 | if (! find_matches (insn, &match)) |
184bb750 R |
1139 | continue; |
1140 | ||
1141 | /* Now scan through the operands looking for a source operand | |
1142 | which is supposed to match the destination operand. | |
1143 | Then scan forward for an instruction which uses the dest | |
1144 | operand. | |
1145 | If it dies there, then replace the dest in both operands with | |
1146 | the source operand. */ | |
1147 | ||
1ccbefce | 1148 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
184bb750 | 1149 | { |
5e9defae | 1150 | rtx src, dst, src_subreg; |
184bb750 R |
1151 | enum reg_class src_class, dst_class; |
1152 | ||
0eadeb15 | 1153 | match_no = match.with[op_no]; |
184bb750 R |
1154 | |
1155 | /* Nothing to do if the two operands aren't supposed to match. */ | |
0eadeb15 | 1156 | if (match_no < 0) |
184bb750 R |
1157 | continue; |
1158 | ||
1ccbefce RH |
1159 | src = recog_data.operand[op_no]; |
1160 | dst = recog_data.operand[match_no]; | |
184bb750 R |
1161 | |
1162 | if (GET_CODE (src) != REG) | |
1163 | continue; | |
1164 | ||
1165 | src_subreg = src; | |
1166 | if (GET_CODE (dst) == SUBREG | |
1167 | && GET_MODE_SIZE (GET_MODE (dst)) | |
1168 | >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (dst)))) | |
1169 | { | |
1170 | src_subreg | |
38a448ca | 1171 | = gen_rtx_SUBREG (GET_MODE (SUBREG_REG (dst)), |
ddef6bc7 | 1172 | src, SUBREG_BYTE (dst)); |
184bb750 R |
1173 | dst = SUBREG_REG (dst); |
1174 | } | |
1175 | if (GET_CODE (dst) != REG | |
1176 | || REGNO (dst) < FIRST_PSEUDO_REGISTER) | |
1177 | continue; | |
1178 | ||
1179 | if (REGNO (src) < FIRST_PSEUDO_REGISTER) | |
1180 | { | |
0eadeb15 | 1181 | if (match.commutative[op_no] < op_no) |
184bb750 R |
1182 | regno_src_regno[REGNO (dst)] = REGNO (src); |
1183 | continue; | |
1184 | } | |
1185 | ||
1186 | if (REG_LIVE_LENGTH (REGNO (src)) < 0) | |
1187 | continue; | |
1188 | ||
0eadeb15 | 1189 | /* op_no/src must be a read-only operand, and |
184bb750 | 1190 | match_operand/dst must be a write-only operand. */ |
0eadeb15 BS |
1191 | if (match.use[op_no] != READ |
1192 | || match.use[match_no] != WRITE) | |
184bb750 R |
1193 | continue; |
1194 | ||
0eadeb15 | 1195 | if (match.early_clobber[match_no] |
4b983fdc | 1196 | && count_occurrences (PATTERN (insn), src, 0) > 1) |
184bb750 R |
1197 | continue; |
1198 | ||
1199 | /* Make sure match_operand is the destination. */ | |
1ccbefce | 1200 | if (recog_data.operand[match_no] != SET_DEST (set)) |
184bb750 R |
1201 | continue; |
1202 | ||
dc297297 | 1203 | /* If the operands already match, then there is nothing to do. */ |
1ccbefce | 1204 | if (operands_match_p (src, dst)) |
184bb750 R |
1205 | continue; |
1206 | ||
1ccbefce RH |
1207 | /* But in the commutative case, we might find a better match. */ |
1208 | if (match.commutative[op_no] >= 0) | |
1209 | { | |
1210 | rtx comm = recog_data.operand[match.commutative[op_no]]; | |
1211 | if (operands_match_p (comm, dst) | |
1212 | && (replacement_quality (comm) | |
1213 | >= replacement_quality (src))) | |
1214 | continue; | |
1215 | } | |
1216 | ||
184bb750 R |
1217 | src_class = reg_preferred_class (REGNO (src)); |
1218 | dst_class = reg_preferred_class (REGNO (dst)); | |
3bb806ed | 1219 | if (! regclass_compatible_p (src_class, dst_class)) |
184bb750 | 1220 | continue; |
174fa2c4 | 1221 | |
f3029065 KH |
1222 | if (GET_MODE (src) != GET_MODE (dst)) |
1223 | continue; | |
1224 | ||
184bb750 | 1225 | if (fixup_match_1 (insn, set, src, src_subreg, dst, pass, |
0eadeb15 | 1226 | op_no, match_no, |
184bb750 R |
1227 | regmove_dump_file)) |
1228 | break; | |
8c660648 JL |
1229 | } |
1230 | } | |
1231 | } | |
1232 | ||
1233 | /* A backward pass. Replace input operands with output operands. */ | |
1234 | ||
1235 | if (regmove_dump_file) | |
1236 | fprintf (regmove_dump_file, "Starting backward pass...\n"); | |
1237 | ||
1238 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
1239 | { | |
2c3c49de | 1240 | if (INSN_P (insn)) |
8c660648 | 1241 | { |
0eadeb15 | 1242 | int op_no, match_no; |
ddc8bed2 | 1243 | int success = 0; |
0eadeb15 | 1244 | |
3363316f | 1245 | if (! find_matches (insn, &match)) |
8c660648 JL |
1246 | continue; |
1247 | ||
8c660648 JL |
1248 | /* Now scan through the operands looking for a destination operand |
1249 | which is supposed to match a source operand. | |
1250 | Then scan backward for an instruction which sets the source | |
1251 | operand. If safe, then replace the source operand with the | |
1252 | dest operand in both instructions. */ | |
1253 | ||
ddc8bed2 MM |
1254 | copy_src = NULL_RTX; |
1255 | copy_dst = NULL_RTX; | |
1ccbefce | 1256 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
8c660648 | 1257 | { |
184bb750 R |
1258 | rtx set, p, src, dst; |
1259 | rtx src_note, dst_note; | |
184bb750 R |
1260 | int num_calls = 0; |
1261 | enum reg_class src_class, dst_class; | |
1262 | int length; | |
8c660648 | 1263 | |
0eadeb15 | 1264 | match_no = match.with[op_no]; |
8c660648 | 1265 | |
184bb750 | 1266 | /* Nothing to do if the two operands aren't supposed to match. */ |
0eadeb15 | 1267 | if (match_no < 0) |
184bb750 | 1268 | continue; |
8c660648 | 1269 | |
1ccbefce RH |
1270 | dst = recog_data.operand[match_no]; |
1271 | src = recog_data.operand[op_no]; | |
8c660648 | 1272 | |
184bb750 R |
1273 | if (GET_CODE (src) != REG) |
1274 | continue; | |
8c660648 | 1275 | |
184bb750 R |
1276 | if (GET_CODE (dst) != REG |
1277 | || REGNO (dst) < FIRST_PSEUDO_REGISTER | |
3721581a JJ |
1278 | || REG_LIVE_LENGTH (REGNO (dst)) < 0 |
1279 | || RTX_UNCHANGING_P (dst)) | |
184bb750 | 1280 | continue; |
8c660648 | 1281 | |
dc297297 | 1282 | /* If the operands already match, then there is nothing to do. */ |
1ccbefce | 1283 | if (operands_match_p (src, dst)) |
184bb750 | 1284 | continue; |
8c660648 | 1285 | |
1ccbefce RH |
1286 | if (match.commutative[op_no] >= 0) |
1287 | { | |
1288 | rtx comm = recog_data.operand[match.commutative[op_no]]; | |
1289 | if (operands_match_p (comm, dst)) | |
1290 | continue; | |
1291 | } | |
1292 | ||
184bb750 R |
1293 | set = single_set (insn); |
1294 | if (! set) | |
1295 | continue; | |
8c660648 | 1296 | |
bb948ad3 RZ |
1297 | /* Note that single_set ignores parts of a parallel set for |
1298 | which one of the destinations is REG_UNUSED. We can't | |
1299 | handle that here, since we can wind up rewriting things | |
1300 | such that a single register is set twice within a single | |
1301 | parallel. */ | |
1302 | if (reg_set_p (src, insn)) | |
1303 | continue; | |
1304 | ||
0eadeb15 | 1305 | /* match_no/dst must be a write-only operand, and |
184bb750 | 1306 | operand_operand/src must be a read-only operand. */ |
0eadeb15 BS |
1307 | if (match.use[op_no] != READ |
1308 | || match.use[match_no] != WRITE) | |
184bb750 | 1309 | continue; |
8c660648 | 1310 | |
0eadeb15 | 1311 | if (match.early_clobber[match_no] |
4b983fdc | 1312 | && count_occurrences (PATTERN (insn), src, 0) > 1) |
184bb750 | 1313 | continue; |
8c660648 | 1314 | |
0eadeb15 | 1315 | /* Make sure match_no is the destination. */ |
1ccbefce | 1316 | if (recog_data.operand[match_no] != SET_DEST (set)) |
184bb750 | 1317 | continue; |
8c660648 | 1318 | |
184bb750 R |
1319 | if (REGNO (src) < FIRST_PSEUDO_REGISTER) |
1320 | { | |
1321 | if (GET_CODE (SET_SRC (set)) == PLUS | |
1322 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT | |
1323 | && XEXP (SET_SRC (set), 0) == src | |
1324 | && fixup_match_2 (insn, dst, src, | |
1325 | XEXP (SET_SRC (set), 1), | |
1326 | regmove_dump_file)) | |
1327 | break; | |
1328 | continue; | |
1329 | } | |
1330 | src_class = reg_preferred_class (REGNO (src)); | |
1331 | dst_class = reg_preferred_class (REGNO (dst)); | |
fd973d56 JH |
1332 | |
1333 | if (! (src_note = find_reg_note (insn, REG_DEAD, src))) | |
ddc8bed2 | 1334 | { |
fd973d56 JH |
1335 | /* We used to force the copy here like in other cases, but |
1336 | it produces worse code, as it eliminates no copy | |
1337 | instructions and the copy emitted will be produced by | |
1338 | reload anyway. On patterns with multiple alternatives, | |
1339 | there may be better sollution availble. | |
1340 | ||
1341 | In particular this change produced slower code for numeric | |
1342 | i387 programs. */ | |
1343 | ||
ddc8bed2 MM |
1344 | continue; |
1345 | } | |
8c660648 | 1346 | |
fd973d56 | 1347 | if (! regclass_compatible_p (src_class, dst_class)) |
ddc8bed2 MM |
1348 | { |
1349 | if (!copy_src) | |
1350 | { | |
1351 | copy_src = src; | |
1352 | copy_dst = dst; | |
1353 | } | |
1354 | continue; | |
1355 | } | |
1356 | ||
fd973d56 JH |
1357 | /* Can not modify an earlier insn to set dst if this insn |
1358 | uses an old value in the source. */ | |
1359 | if (reg_overlap_mentioned_p (dst, SET_SRC (set))) | |
ddc8bed2 MM |
1360 | { |
1361 | if (!copy_src) | |
1362 | { | |
1363 | copy_src = src; | |
1364 | copy_dst = dst; | |
1365 | } | |
1366 | continue; | |
1367 | } | |
8c660648 | 1368 | |
184bb750 R |
1369 | /* If src is set once in a different basic block, |
1370 | and is set equal to a constant, then do not use | |
1371 | it for this optimization, as this would make it | |
1372 | no longer equivalent to a constant. */ | |
ddc8bed2 | 1373 | |
a6a2274a | 1374 | if (reg_is_remote_constant_p (src, insn, f)) |
ddc8bed2 MM |
1375 | { |
1376 | if (!copy_src) | |
1377 | { | |
1378 | copy_src = src; | |
1379 | copy_dst = dst; | |
1380 | } | |
1381 | continue; | |
1382 | } | |
1383 | ||
1384 | ||
1385 | if (regmove_dump_file) | |
1386 | fprintf (regmove_dump_file, | |
1387 | "Could fix operand %d of insn %d matching operand %d.\n", | |
0eadeb15 | 1388 | op_no, INSN_UID (insn), match_no); |
8c660648 | 1389 | |
184bb750 R |
1390 | /* Scan backward to find the first instruction that uses |
1391 | the input operand. If the operand is set here, then | |
0eadeb15 | 1392 | replace it in both instructions with match_no. */ |
184bb750 R |
1393 | |
1394 | for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
1395 | { | |
1396 | rtx pset; | |
1397 | ||
7bf825d2 JW |
1398 | /* ??? We can't scan past the end of a basic block without |
1399 | updating the register lifetime info | |
a1c1fdd0 RK |
1400 | (REG_DEAD/basic_block_live_at_start). */ |
1401 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 1402 | break; |
a1c1fdd0 | 1403 | else if (! INSN_P (p)) |
184bb750 | 1404 | continue; |
8c660648 | 1405 | |
184bb750 | 1406 | length++; |
8c660648 | 1407 | |
184bb750 R |
1408 | /* ??? See if all of SRC is set in P. This test is much |
1409 | more conservative than it needs to be. */ | |
1410 | pset = single_set (p); | |
1411 | if (pset && SET_DEST (pset) == src) | |
1412 | { | |
1413 | /* We use validate_replace_rtx, in case there | |
1414 | are multiple identical source operands. All of | |
1415 | them have to be changed at the same time. */ | |
1416 | if (validate_replace_rtx (src, dst, insn)) | |
8c660648 | 1417 | { |
184bb750 R |
1418 | if (validate_change (p, &SET_DEST (pset), |
1419 | dst, 0)) | |
1420 | success = 1; | |
1421 | else | |
8c660648 | 1422 | { |
184bb750 R |
1423 | /* Change all source operands back. |
1424 | This modifies the dst as a side-effect. */ | |
1425 | validate_replace_rtx (dst, src, insn); | |
1426 | /* Now make sure the dst is right. */ | |
1427 | validate_change (insn, | |
1ccbefce | 1428 | recog_data.operand_loc[match_no], |
184bb750 | 1429 | dst, 0); |
8c660648 | 1430 | } |
8c660648 | 1431 | } |
184bb750 R |
1432 | break; |
1433 | } | |
1434 | ||
1435 | if (reg_overlap_mentioned_p (src, PATTERN (p)) | |
1436 | || reg_overlap_mentioned_p (dst, PATTERN (p))) | |
1437 | break; | |
8c660648 | 1438 | |
184bb750 R |
1439 | /* If we have passed a call instruction, and the |
1440 | pseudo-reg DST is not already live across a call, | |
1441 | then don't perform the optimization. */ | |
1442 | if (GET_CODE (p) == CALL_INSN) | |
1443 | { | |
1444 | num_calls++; | |
1445 | ||
1446 | if (REG_N_CALLS_CROSSED (REGNO (dst)) == 0) | |
8c660648 | 1447 | break; |
184bb750 R |
1448 | } |
1449 | } | |
8c660648 | 1450 | |
184bb750 R |
1451 | if (success) |
1452 | { | |
1453 | int dstno, srcno; | |
8c660648 | 1454 | |
184bb750 R |
1455 | /* Remove the death note for SRC from INSN. */ |
1456 | remove_note (insn, src_note); | |
1457 | /* Move the death note for SRC to P if it is used | |
1458 | there. */ | |
1459 | if (reg_overlap_mentioned_p (src, PATTERN (p))) | |
1460 | { | |
1461 | XEXP (src_note, 1) = REG_NOTES (p); | |
1462 | REG_NOTES (p) = src_note; | |
8c660648 | 1463 | } |
184bb750 R |
1464 | /* If there is a REG_DEAD note for DST on P, then remove |
1465 | it, because DST is now set there. */ | |
5e9defae | 1466 | if ((dst_note = find_reg_note (p, REG_DEAD, dst))) |
184bb750 R |
1467 | remove_note (p, dst_note); |
1468 | ||
1469 | dstno = REGNO (dst); | |
1470 | srcno = REGNO (src); | |
1471 | ||
1472 | REG_N_SETS (dstno)++; | |
1473 | REG_N_SETS (srcno)--; | |
8c660648 | 1474 | |
184bb750 R |
1475 | REG_N_CALLS_CROSSED (dstno) += num_calls; |
1476 | REG_N_CALLS_CROSSED (srcno) -= num_calls; | |
1477 | ||
1478 | REG_LIVE_LENGTH (dstno) += length; | |
1479 | if (REG_LIVE_LENGTH (srcno) >= 0) | |
8c660648 | 1480 | { |
184bb750 R |
1481 | REG_LIVE_LENGTH (srcno) -= length; |
1482 | /* REG_LIVE_LENGTH is only an approximation after | |
1483 | combine if sched is not run, so make sure that we | |
1484 | still have a reasonable value. */ | |
1485 | if (REG_LIVE_LENGTH (srcno) < 2) | |
1486 | REG_LIVE_LENGTH (srcno) = 2; | |
1487 | } | |
8c660648 | 1488 | |
184bb750 R |
1489 | if (regmove_dump_file) |
1490 | fprintf (regmove_dump_file, | |
1491 | "Fixed operand %d of insn %d matching operand %d.\n", | |
0eadeb15 | 1492 | op_no, INSN_UID (insn), match_no); |
8c660648 | 1493 | |
184bb750 | 1494 | break; |
8c660648 JL |
1495 | } |
1496 | } | |
ddc8bed2 MM |
1497 | |
1498 | /* If we weren't able to replace any of the alternatives, try an | |
1499 | alternative appoach of copying the source to the destination. */ | |
1500 | if (!success && copy_src != NULL_RTX) | |
1b7c4a37 | 1501 | copy_src_to_dest (insn, copy_src, copy_dst, old_max_uid); |
ddc8bed2 | 1502 | |
8c660648 JL |
1503 | } |
1504 | } | |
961d4119 BS |
1505 | |
1506 | /* In fixup_match_1, some insns may have been inserted after basic block | |
1507 | ends. Fix that here. */ | |
e0082a72 | 1508 | FOR_EACH_BB (bb) |
961d4119 | 1509 | { |
f6366fc7 | 1510 | rtx end = bb->end; |
961d4119 BS |
1511 | rtx new = end; |
1512 | rtx next = NEXT_INSN (new); | |
1513 | while (next != 0 && INSN_UID (next) >= old_max_uid | |
f6366fc7 | 1514 | && (bb->next_bb == EXIT_BLOCK_PTR || bb->next_bb->head != next)) |
961d4119 | 1515 | new = next, next = NEXT_INSN (new); |
f6366fc7 | 1516 | bb->end = new; |
961d4119 | 1517 | } |
4da896b2 MM |
1518 | |
1519 | done: | |
1520 | /* Clean up. */ | |
1521 | free (regno_src_regno); | |
1522 | free (regmove_bb_head); | |
8c660648 JL |
1523 | } |
1524 | ||
0eadeb15 BS |
1525 | /* Returns nonzero if INSN's pattern has matching constraints for any operand. |
1526 | Returns 0 if INSN can't be recognized, or if the alternative can't be | |
1527 | determined. | |
b1a7d591 JW |
1528 | |
1529 | Initialize the info in MATCHP based on the constraints. */ | |
184bb750 R |
1530 | |
1531 | static int | |
1532 | find_matches (insn, matchp) | |
1533 | rtx insn; | |
1534 | struct match *matchp; | |
1535 | { | |
1536 | int likely_spilled[MAX_RECOG_OPERANDS]; | |
0eadeb15 | 1537 | int op_no; |
184bb750 R |
1538 | int any_matches = 0; |
1539 | ||
0eadeb15 BS |
1540 | extract_insn (insn); |
1541 | if (! constrain_operands (0)) | |
1542 | return 0; | |
184bb750 R |
1543 | |
1544 | /* Must initialize this before main loop, because the code for | |
1545 | the commutative case may set matches for operands other than | |
1546 | the current one. */ | |
1ccbefce | 1547 | for (op_no = recog_data.n_operands; --op_no >= 0; ) |
0eadeb15 | 1548 | matchp->with[op_no] = matchp->commutative[op_no] = -1; |
184bb750 | 1549 | |
1ccbefce | 1550 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
184bb750 | 1551 | { |
9b3142b3 KG |
1552 | const char *p; |
1553 | char c; | |
184bb750 R |
1554 | int i = 0; |
1555 | ||
1ccbefce | 1556 | p = recog_data.constraints[op_no]; |
184bb750 | 1557 | |
0eadeb15 BS |
1558 | likely_spilled[op_no] = 0; |
1559 | matchp->use[op_no] = READ; | |
1560 | matchp->early_clobber[op_no] = 0; | |
184bb750 | 1561 | if (*p == '=') |
0eadeb15 | 1562 | matchp->use[op_no] = WRITE; |
184bb750 | 1563 | else if (*p == '+') |
0eadeb15 | 1564 | matchp->use[op_no] = READWRITE; |
184bb750 R |
1565 | |
1566 | for (;*p && i < which_alternative; p++) | |
1567 | if (*p == ',') | |
1568 | i++; | |
1569 | ||
1570 | while ((c = *p++) != '\0' && c != ',') | |
1571 | switch (c) | |
1572 | { | |
1573 | case '=': | |
1574 | break; | |
1575 | case '+': | |
1576 | break; | |
1577 | case '&': | |
0eadeb15 | 1578 | matchp->early_clobber[op_no] = 1; |
184bb750 R |
1579 | break; |
1580 | case '%': | |
0eadeb15 BS |
1581 | matchp->commutative[op_no] = op_no + 1; |
1582 | matchp->commutative[op_no + 1] = op_no; | |
184bb750 | 1583 | break; |
84b72302 | 1584 | |
184bb750 R |
1585 | case '0': case '1': case '2': case '3': case '4': |
1586 | case '5': case '6': case '7': case '8': case '9': | |
84b72302 RH |
1587 | { |
1588 | char *end; | |
2cc2d4bb RK |
1589 | unsigned long match_ul = strtoul (p - 1, &end, 10); |
1590 | int match = match_ul; | |
1591 | ||
84b72302 RH |
1592 | p = end; |
1593 | ||
1594 | if (match < op_no && likely_spilled[match]) | |
1595 | break; | |
1596 | matchp->with[op_no] = match; | |
1597 | any_matches = 1; | |
1598 | if (matchp->commutative[op_no] >= 0) | |
1599 | matchp->with[matchp->commutative[op_no]] = match; | |
1600 | } | |
184bb750 | 1601 | break; |
84b72302 | 1602 | |
184bb750 R |
1603 | case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'h': |
1604 | case 'j': case 'k': case 'l': case 'p': case 'q': case 't': case 'u': | |
1605 | case 'v': case 'w': case 'x': case 'y': case 'z': case 'A': case 'B': | |
1606 | case 'C': case 'D': case 'W': case 'Y': case 'Z': | |
8e2e89f7 | 1607 | if (CLASS_LIKELY_SPILLED_P (REG_CLASS_FROM_LETTER ((unsigned char) c))) |
0eadeb15 | 1608 | likely_spilled[op_no] = 1; |
184bb750 R |
1609 | break; |
1610 | } | |
1611 | } | |
0eadeb15 | 1612 | return any_matches; |
184bb750 R |
1613 | } |
1614 | ||
ec7c0481 AO |
1615 | /* Try to replace all occurrences of DST_REG with SRC in LOC, that is |
1616 | assumed to be in INSN. */ | |
1617 | ||
1618 | static void | |
1619 | replace_in_call_usage (loc, dst_reg, src, insn) | |
1620 | rtx *loc; | |
ae0ed63a | 1621 | unsigned int dst_reg; |
ec7c0481 AO |
1622 | rtx src; |
1623 | rtx insn; | |
1624 | { | |
1625 | rtx x = *loc; | |
1626 | enum rtx_code code; | |
1627 | const char *fmt; | |
1628 | int i, j; | |
1629 | ||
1630 | if (! x) | |
1631 | return; | |
174fa2c4 | 1632 | |
ec7c0481 AO |
1633 | code = GET_CODE (x); |
1634 | if (code == REG) | |
1635 | { | |
1636 | if (REGNO (x) != dst_reg) | |
1637 | return; | |
174fa2c4 | 1638 | |
ec7c0481 AO |
1639 | validate_change (insn, loc, src, 1); |
1640 | ||
1641 | return; | |
1642 | } | |
174fa2c4 | 1643 | |
ec7c0481 AO |
1644 | /* Process each of our operands recursively. */ |
1645 | fmt = GET_RTX_FORMAT (code); | |
1646 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
1647 | if (*fmt == 'e') | |
1648 | replace_in_call_usage (&XEXP (x, i), dst_reg, src, insn); | |
1649 | else if (*fmt == 'E') | |
1650 | for (j = 0; j < XVECLEN (x, i); j++) | |
1651 | replace_in_call_usage (& XVECEXP (x, i, j), dst_reg, src, insn); | |
1652 | } | |
1653 | ||
184bb750 | 1654 | /* Try to replace output operand DST in SET, with input operand SRC. SET is |
06671717 | 1655 | the only set in INSN. INSN has just been recognized and constrained. |
184bb750 R |
1656 | SRC is operand number OPERAND_NUMBER in INSN. |
1657 | DST is operand number MATCH_NUMBER in INSN. | |
1658 | If BACKWARD is nonzero, we have been called in a backward pass. | |
1659 | Return nonzero for success. */ | |
a1c1fdd0 | 1660 | |
184bb750 R |
1661 | static int |
1662 | fixup_match_1 (insn, set, src, src_subreg, dst, backward, operand_number, | |
1663 | match_number, regmove_dump_file) | |
1664 | rtx insn, set, src, src_subreg, dst; | |
1665 | int backward, operand_number, match_number; | |
1666 | FILE *regmove_dump_file; | |
1667 | { | |
1668 | rtx p; | |
1669 | rtx post_inc = 0, post_inc_set = 0, search_end = 0; | |
1670 | int success = 0; | |
1671 | int num_calls = 0, s_num_calls = 0; | |
1672 | enum rtx_code code = NOTE; | |
a544cfd2 | 1673 | HOST_WIDE_INT insn_const = 0, newconst; |
184bb750 | 1674 | rtx overlap = 0; /* need to move insn ? */ |
a544cfd2 | 1675 | rtx src_note = find_reg_note (insn, REG_DEAD, src), dst_note = NULL_RTX; |
1b7c4a37 | 1676 | int length, s_length; |
184bb750 | 1677 | |
18bf656f R |
1678 | /* If SRC is marked as unchanging, we may not change it. |
1679 | ??? Maybe we could get better code by removing the unchanging bit | |
1680 | instead, and changing it back if we don't succeed? */ | |
1681 | if (RTX_UNCHANGING_P (src)) | |
1682 | return 0; | |
1683 | ||
184bb750 R |
1684 | if (! src_note) |
1685 | { | |
1686 | /* Look for (set (regX) (op regA constX)) | |
1687 | (set (regY) (op regA constY)) | |
1688 | and change that to | |
1689 | (set (regA) (op regA constX)). | |
1690 | (set (regY) (op regA constY-constX)). | |
1691 | This works for add and shift operations, if | |
1692 | regA is dead after or set by the second insn. */ | |
1693 | ||
1694 | code = GET_CODE (SET_SRC (set)); | |
1695 | if ((code == PLUS || code == LSHIFTRT | |
1696 | || code == ASHIFT || code == ASHIFTRT) | |
1697 | && XEXP (SET_SRC (set), 0) == src | |
1698 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) | |
1699 | insn_const = INTVAL (XEXP (SET_SRC (set), 1)); | |
18bf656f | 1700 | else if (! stable_and_no_regs_but_for_p (SET_SRC (set), src, dst)) |
184bb750 R |
1701 | return 0; |
1702 | else | |
1703 | /* We might find a src_note while scanning. */ | |
1704 | code = NOTE; | |
1705 | } | |
1706 | ||
1707 | if (regmove_dump_file) | |
1708 | fprintf (regmove_dump_file, | |
1709 | "Could fix operand %d of insn %d matching operand %d.\n", | |
1710 | operand_number, INSN_UID (insn), match_number); | |
1711 | ||
1712 | /* If SRC is equivalent to a constant set in a different basic block, | |
1713 | then do not use it for this optimization. We want the equivalence | |
1714 | so that if we have to reload this register, we can reload the | |
1715 | constant, rather than extending the lifespan of the register. */ | |
1716 | if (reg_is_remote_constant_p (src, insn, get_insns ())) | |
1717 | return 0; | |
1718 | ||
1719 | /* Scan forward to find the next instruction that | |
1720 | uses the output operand. If the operand dies here, | |
1721 | then replace it in both instructions with | |
1722 | operand_number. */ | |
1723 | ||
1724 | for (length = s_length = 0, p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
1725 | { | |
ec7c0481 AO |
1726 | if (GET_CODE (p) == CALL_INSN) |
1727 | replace_in_call_usage (& CALL_INSN_FUNCTION_USAGE (p), | |
1728 | REGNO (dst), src, p); | |
174fa2c4 | 1729 | |
7bf825d2 | 1730 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 RK |
1731 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
1732 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 1733 | break; |
a1c1fdd0 | 1734 | else if (! INSN_P (p)) |
184bb750 R |
1735 | continue; |
1736 | ||
1737 | length++; | |
1738 | if (src_note) | |
1739 | s_length++; | |
1740 | ||
1741 | if (reg_set_p (src, p) || reg_set_p (dst, p) | |
1742 | || (GET_CODE (PATTERN (p)) == USE | |
1743 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
1744 | break; | |
1745 | ||
1746 | /* See if all of DST dies in P. This test is | |
1747 | slightly more conservative than it needs to be. */ | |
1748 | if ((dst_note = find_regno_note (p, REG_DEAD, REGNO (dst))) | |
1749 | && (GET_MODE (XEXP (dst_note, 0)) == GET_MODE (dst))) | |
1750 | { | |
2219e921 R |
1751 | /* If we would be moving INSN, check that we won't move it |
1752 | into the shadow of a live a live flags register. */ | |
1753 | /* ??? We only try to move it in front of P, although | |
1754 | we could move it anywhere between OVERLAP and P. */ | |
1755 | if (overlap && GET_MODE (PREV_INSN (p)) != VOIDmode) | |
1756 | break; | |
1757 | ||
184bb750 R |
1758 | if (! src_note) |
1759 | { | |
1760 | rtx q; | |
a544cfd2 | 1761 | rtx set2 = NULL_RTX; |
184bb750 R |
1762 | |
1763 | /* If an optimization is done, the value of SRC while P | |
1764 | is executed will be changed. Check that this is OK. */ | |
1765 | if (reg_overlap_mentioned_p (src, PATTERN (p))) | |
1766 | break; | |
1767 | for (q = p; q; q = NEXT_INSN (q)) | |
1768 | { | |
7bf825d2 JW |
1769 | /* ??? We can't scan past the end of a basic block without |
1770 | updating the register lifetime info | |
a1c1fdd0 RK |
1771 | (REG_DEAD/basic_block_live_at_start). */ |
1772 | if (perhaps_ends_bb_p (q)) | |
7bf825d2 JW |
1773 | { |
1774 | q = 0; | |
1775 | break; | |
1776 | } | |
a1c1fdd0 | 1777 | else if (! INSN_P (q)) |
184bb750 | 1778 | continue; |
a1c1fdd0 RK |
1779 | else if (reg_overlap_mentioned_p (src, PATTERN (q)) |
1780 | || reg_set_p (src, q)) | |
184bb750 R |
1781 | break; |
1782 | } | |
1783 | if (q) | |
1784 | set2 = single_set (q); | |
1785 | if (! q || ! set2 || GET_CODE (SET_SRC (set2)) != code | |
1786 | || XEXP (SET_SRC (set2), 0) != src | |
1787 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT | |
1788 | || (SET_DEST (set2) != src | |
1789 | && ! find_reg_note (q, REG_DEAD, src))) | |
1790 | { | |
1791 | /* If this is a PLUS, we can still save a register by doing | |
1792 | src += insn_const; | |
1793 | P; | |
1794 | src -= insn_const; . | |
1795 | This also gives opportunities for subsequent | |
1796 | optimizations in the backward pass, so do it there. */ | |
1797 | if (code == PLUS && backward | |
3bb806ed R |
1798 | /* Don't do this if we can likely tie DST to SET_DEST |
1799 | of P later; we can't do this tying here if we got a | |
1800 | hard register. */ | |
1801 | && ! (dst_note && ! REG_N_CALLS_CROSSED (REGNO (dst)) | |
1802 | && single_set (p) | |
1803 | && GET_CODE (SET_DEST (single_set (p))) == REG | |
1804 | && (REGNO (SET_DEST (single_set (p))) | |
1805 | < FIRST_PSEUDO_REGISTER)) | |
dc2cb191 RH |
1806 | /* We may only emit an insn directly after P if we |
1807 | are not in the shadow of a live flags register. */ | |
1808 | && GET_MODE (p) == VOIDmode) | |
184bb750 R |
1809 | { |
1810 | search_end = q; | |
1811 | q = insn; | |
1812 | set2 = set; | |
1813 | newconst = -insn_const; | |
1814 | code = MINUS; | |
1815 | } | |
1816 | else | |
1817 | break; | |
1818 | } | |
1819 | else | |
1820 | { | |
1821 | newconst = INTVAL (XEXP (SET_SRC (set2), 1)) - insn_const; | |
1822 | /* Reject out of range shifts. */ | |
1823 | if (code != PLUS | |
1824 | && (newconst < 0 | |
a1c1fdd0 RK |
1825 | || ((unsigned HOST_WIDE_INT) newconst |
1826 | >= (GET_MODE_BITSIZE (GET_MODE | |
1827 | (SET_SRC (set2))))))) | |
184bb750 R |
1828 | break; |
1829 | if (code == PLUS) | |
1830 | { | |
1831 | post_inc = q; | |
1832 | if (SET_DEST (set2) != src) | |
1833 | post_inc_set = set2; | |
1834 | } | |
1835 | } | |
1836 | /* We use 1 as last argument to validate_change so that all | |
1837 | changes are accepted or rejected together by apply_change_group | |
1838 | when it is called by validate_replace_rtx . */ | |
1839 | validate_change (q, &XEXP (SET_SRC (set2), 1), | |
1840 | GEN_INT (newconst), 1); | |
1841 | } | |
1ccbefce | 1842 | validate_change (insn, recog_data.operand_loc[match_number], src, 1); |
184bb750 R |
1843 | if (validate_replace_rtx (dst, src_subreg, p)) |
1844 | success = 1; | |
1845 | break; | |
1846 | } | |
1847 | ||
1848 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) | |
1849 | break; | |
1850 | if (! src_note && reg_overlap_mentioned_p (src, PATTERN (p))) | |
1851 | { | |
2219e921 R |
1852 | /* INSN was already checked to be movable wrt. the registers that it |
1853 | sets / uses when we found no REG_DEAD note for src on it, but it | |
1854 | still might clobber the flags register. We'll have to check that | |
1855 | we won't insert it into the shadow of a live flags register when | |
1856 | we finally know where we are to move it. */ | |
184bb750 R |
1857 | overlap = p; |
1858 | src_note = find_reg_note (p, REG_DEAD, src); | |
1859 | } | |
1860 | ||
1861 | /* If we have passed a call instruction, and the pseudo-reg SRC is not | |
1862 | already live across a call, then don't perform the optimization. */ | |
1863 | if (GET_CODE (p) == CALL_INSN) | |
1864 | { | |
1865 | if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) | |
1866 | break; | |
1867 | ||
1868 | num_calls++; | |
1869 | ||
1870 | if (src_note) | |
1871 | s_num_calls++; | |
1872 | ||
1873 | } | |
1874 | } | |
1875 | ||
1876 | if (! success) | |
1877 | return 0; | |
1878 | ||
184bb750 R |
1879 | /* Remove the death note for DST from P. */ |
1880 | remove_note (p, dst_note); | |
1881 | if (code == MINUS) | |
1882 | { | |
1883 | post_inc = emit_insn_after (copy_rtx (PATTERN (insn)), p); | |
940da324 JL |
1884 | if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) |
1885 | && search_end | |
184bb750 R |
1886 | && try_auto_increment (search_end, post_inc, 0, src, newconst, 1)) |
1887 | post_inc = 0; | |
184bb750 R |
1888 | validate_change (insn, &XEXP (SET_SRC (set), 1), GEN_INT (insn_const), 0); |
1889 | REG_N_SETS (REGNO (src))++; | |
184bb750 R |
1890 | REG_LIVE_LENGTH (REGNO (src))++; |
1891 | } | |
1892 | if (overlap) | |
1893 | { | |
1894 | /* The lifetime of src and dest overlap, | |
1895 | but we can change this by moving insn. */ | |
1896 | rtx pat = PATTERN (insn); | |
1897 | if (src_note) | |
1898 | remove_note (overlap, src_note); | |
1ed9faee TM |
1899 | if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT) |
1900 | && code == PLUS | |
184bb750 R |
1901 | && try_auto_increment (overlap, insn, 0, src, insn_const, 0)) |
1902 | insn = overlap; | |
1903 | else | |
184bb750 R |
1904 | { |
1905 | rtx notes = REG_NOTES (insn); | |
1906 | ||
1907 | emit_insn_after_with_line_notes (pat, PREV_INSN (p), insn); | |
ca6c03ca | 1908 | delete_insn (insn); |
184bb750 R |
1909 | /* emit_insn_after_with_line_notes has no |
1910 | return value, so search for the new insn. */ | |
ef178af3 | 1911 | insn = p; |
2c3c49de | 1912 | while (! INSN_P (insn) || PATTERN (insn) != pat) |
184bb750 R |
1913 | insn = PREV_INSN (insn); |
1914 | ||
1915 | REG_NOTES (insn) = notes; | |
1916 | } | |
1917 | } | |
1918 | /* Sometimes we'd generate src = const; src += n; | |
1919 | if so, replace the instruction that set src | |
1920 | in the first place. */ | |
1921 | ||
1922 | if (! overlap && (code == PLUS || code == MINUS)) | |
1923 | { | |
1924 | rtx note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
a544cfd2 | 1925 | rtx q, set2 = NULL_RTX; |
184bb750 R |
1926 | int num_calls2 = 0, s_length2 = 0; |
1927 | ||
1928 | if (note && CONSTANT_P (XEXP (note, 0))) | |
1929 | { | |
8e2e89f7 | 1930 | for (q = PREV_INSN (insn); q; q = PREV_INSN (q)) |
184bb750 | 1931 | { |
7bf825d2 JW |
1932 | /* ??? We can't scan past the end of a basic block without |
1933 | updating the register lifetime info | |
a1c1fdd0 RK |
1934 | (REG_DEAD/basic_block_live_at_start). */ |
1935 | if (perhaps_ends_bb_p (q)) | |
7bf825d2 JW |
1936 | { |
1937 | q = 0; | |
1938 | break; | |
1939 | } | |
a1c1fdd0 | 1940 | else if (! INSN_P (q)) |
184bb750 | 1941 | continue; |
a1c1fdd0 | 1942 | |
184bb750 R |
1943 | s_length2++; |
1944 | if (reg_set_p (src, q)) | |
1945 | { | |
1946 | set2 = single_set (q); | |
1947 | break; | |
1948 | } | |
1949 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
1950 | { | |
1951 | q = 0; | |
1952 | break; | |
1953 | } | |
1954 | if (GET_CODE (p) == CALL_INSN) | |
1955 | num_calls2++; | |
1956 | } | |
1957 | if (q && set2 && SET_DEST (set2) == src && CONSTANT_P (SET_SRC (set2)) | |
1958 | && validate_change (insn, &SET_SRC (set), XEXP (note, 0), 0)) | |
1959 | { | |
ca6c03ca | 1960 | delete_insn (q); |
184bb750 R |
1961 | REG_N_SETS (REGNO (src))--; |
1962 | REG_N_CALLS_CROSSED (REGNO (src)) -= num_calls2; | |
184bb750 R |
1963 | REG_LIVE_LENGTH (REGNO (src)) -= s_length2; |
1964 | insn_const = 0; | |
1965 | } | |
1966 | } | |
1967 | } | |
1a56b81f | 1968 | |
cb084004 | 1969 | if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) |
940da324 | 1970 | && (code == PLUS || code == MINUS) && insn_const |
184bb750 R |
1971 | && try_auto_increment (p, insn, 0, src, insn_const, 1)) |
1972 | insn = p; | |
940da324 JL |
1973 | else if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT) |
1974 | && post_inc | |
184bb750 R |
1975 | && try_auto_increment (p, post_inc, post_inc_set, src, newconst, 0)) |
1976 | post_inc = 0; | |
184bb750 R |
1977 | /* If post_inc still prevails, try to find an |
1978 | insn where it can be used as a pre-in/decrement. | |
1979 | If code is MINUS, this was already tried. */ | |
1980 | if (post_inc && code == PLUS | |
1981 | /* Check that newconst is likely to be usable | |
1982 | in a pre-in/decrement before starting the search. */ | |
940da324 JL |
1983 | && ((HAVE_PRE_INCREMENT && newconst > 0 && newconst <= MOVE_MAX) |
1984 | || (HAVE_PRE_DECREMENT && newconst < 0 && newconst >= -MOVE_MAX)) | |
1985 | && exact_log2 (newconst)) | |
184bb750 R |
1986 | { |
1987 | rtx q, inc_dest; | |
1988 | ||
1989 | inc_dest = post_inc_set ? SET_DEST (post_inc_set) : src; | |
51723711 | 1990 | for (q = post_inc; (q = NEXT_INSN (q)); ) |
184bb750 | 1991 | { |
7bf825d2 | 1992 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 | 1993 | the register lifetime info |
dc297297 | 1994 | (REG_DEAD/basic_block_live_at_start). */ |
a1c1fdd0 | 1995 | if (perhaps_ends_bb_p (q)) |
7bf825d2 | 1996 | break; |
a1c1fdd0 | 1997 | else if (! INSN_P (q)) |
184bb750 | 1998 | continue; |
a1c1fdd0 RK |
1999 | else if (src != inc_dest |
2000 | && (reg_overlap_mentioned_p (src, PATTERN (q)) | |
2001 | || reg_set_p (src, q))) | |
184bb750 | 2002 | break; |
a1c1fdd0 | 2003 | else if (reg_set_p (inc_dest, q)) |
184bb750 | 2004 | break; |
a1c1fdd0 | 2005 | else if (reg_overlap_mentioned_p (inc_dest, PATTERN (q))) |
184bb750 R |
2006 | { |
2007 | try_auto_increment (q, post_inc, | |
2008 | post_inc_set, inc_dest, newconst, 1); | |
2009 | break; | |
2010 | } | |
2011 | } | |
2012 | } | |
a1c1fdd0 | 2013 | |
184bb750 R |
2014 | /* Move the death note for DST to INSN if it is used |
2015 | there. */ | |
2016 | if (reg_overlap_mentioned_p (dst, PATTERN (insn))) | |
2017 | { | |
2018 | XEXP (dst_note, 1) = REG_NOTES (insn); | |
2019 | REG_NOTES (insn) = dst_note; | |
2020 | } | |
2021 | ||
2022 | if (src_note) | |
2023 | { | |
2024 | /* Move the death note for SRC from INSN to P. */ | |
2025 | if (! overlap) | |
2026 | remove_note (insn, src_note); | |
2027 | XEXP (src_note, 1) = REG_NOTES (p); | |
2028 | REG_NOTES (p) = src_note; | |
2029 | ||
2030 | REG_N_CALLS_CROSSED (REGNO (src)) += s_num_calls; | |
2031 | } | |
2032 | ||
2033 | REG_N_SETS (REGNO (src))++; | |
2034 | REG_N_SETS (REGNO (dst))--; | |
2035 | ||
2036 | REG_N_CALLS_CROSSED (REGNO (dst)) -= num_calls; | |
2037 | ||
2038 | REG_LIVE_LENGTH (REGNO (src)) += s_length; | |
2039 | if (REG_LIVE_LENGTH (REGNO (dst)) >= 0) | |
2040 | { | |
2041 | REG_LIVE_LENGTH (REGNO (dst)) -= length; | |
2042 | /* REG_LIVE_LENGTH is only an approximation after | |
2043 | combine if sched is not run, so make sure that we | |
2044 | still have a reasonable value. */ | |
2045 | if (REG_LIVE_LENGTH (REGNO (dst)) < 2) | |
2046 | REG_LIVE_LENGTH (REGNO (dst)) = 2; | |
2047 | } | |
184bb750 R |
2048 | if (regmove_dump_file) |
2049 | fprintf (regmove_dump_file, | |
2050 | "Fixed operand %d of insn %d matching operand %d.\n", | |
2051 | operand_number, INSN_UID (insn), match_number); | |
2052 | return 1; | |
2053 | } | |
2054 | ||
2055 | ||
18bf656f R |
2056 | /* return nonzero if X is stable and mentions no regsiters but for |
2057 | mentioning SRC or mentioning / changing DST . If in doubt, presume | |
2058 | it is unstable. | |
2059 | The rationale is that we want to check if we can move an insn easily | |
2060 | while just paying attention to SRC and DST. A register is considered | |
2061 | stable if it has the RTX_UNCHANGING_P bit set, but that would still | |
2062 | leave the burden to update REG_DEAD / REG_UNUSED notes, so we don't | |
2063 | want any registers but SRC and DST. */ | |
8c660648 | 2064 | static int |
18bf656f | 2065 | stable_and_no_regs_but_for_p (x, src, dst) |
8c660648 JL |
2066 | rtx x, src, dst; |
2067 | { | |
2068 | RTX_CODE code = GET_CODE (x); | |
2069 | switch (GET_RTX_CLASS (code)) | |
2070 | { | |
2071 | case '<': case '1': case 'c': case '2': case 'b': case '3': | |
2072 | { | |
2073 | int i; | |
6f7d635c | 2074 | const char *fmt = GET_RTX_FORMAT (code); |
8c660648 | 2075 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
18bf656f R |
2076 | if (fmt[i] == 'e' |
2077 | && ! stable_and_no_regs_but_for_p (XEXP (x, i), src, dst)) | |
8c660648 JL |
2078 | return 0; |
2079 | return 1; | |
2080 | } | |
2081 | case 'o': | |
18bf656f R |
2082 | if (code == REG) |
2083 | return x == src || x == dst; | |
2084 | /* If this is a MEM, look inside - there might be a register hidden in | |
2085 | the address of an unchanging MEM. */ | |
2086 | if (code == MEM | |
2087 | && ! stable_and_no_regs_but_for_p (XEXP (x, 0), src, dst)) | |
2088 | return 0; | |
8c660648 JL |
2089 | /* fall through */ |
2090 | default: | |
2091 | return ! rtx_unstable_p (x); | |
2092 | } | |
2093 | } | |
1e7f0a48 | 2094 | \f |
174fa2c4 | 2095 | /* Track stack adjustments and stack memory references. Attempt to |
a1f300c0 | 2096 | reduce the number of stack adjustments by back-propagating across |
1e7f0a48 RH |
2097 | the memory references. |
2098 | ||
2099 | This is intended primarily for use with targets that do not define | |
2100 | ACCUMULATE_OUTGOING_ARGS. It is of significantly more value to | |
2101 | targets that define PREFERRED_STACK_BOUNDARY more aligned than | |
2102 | STACK_BOUNDARY (e.g. x86), or if not all registers can be pushed | |
2103 | (e.g. x86 fp regs) which would ordinarily have to be implemented | |
2104 | as a sub/mov pair due to restrictions in calls.c. | |
2105 | ||
a1f300c0 | 2106 | Propagation stops when any of the insns that need adjusting are |
1e7f0a48 RH |
2107 | (a) no longer valid because we've exceeded their range, (b) a |
2108 | non-trivial push instruction, or (c) a call instruction. | |
2109 | ||
2110 | Restriction B is based on the assumption that push instructions | |
2111 | are smaller or faster. If a port really wants to remove all | |
2112 | pushes, it should have defined ACCUMULATE_OUTGOING_ARGS. The | |
2113 | one exception that is made is for an add immediately followed | |
2114 | by a push. */ | |
2115 | ||
2116 | /* This structure records stack memory references between stack adjusting | |
2117 | instructions. */ | |
2118 | ||
2119 | struct csa_memlist | |
2120 | { | |
2121 | HOST_WIDE_INT sp_offset; | |
5a97f7c2 | 2122 | rtx insn, *mem; |
1e7f0a48 RH |
2123 | struct csa_memlist *next; |
2124 | }; | |
2125 | ||
2126 | static int stack_memref_p PARAMS ((rtx)); | |
2127 | static rtx single_set_for_csa PARAMS ((rtx)); | |
2128 | static void free_csa_memlist PARAMS ((struct csa_memlist *)); | |
2129 | static struct csa_memlist *record_one_stack_memref | |
5a97f7c2 | 2130 | PARAMS ((rtx, rtx *, struct csa_memlist *)); |
1e7f0a48 RH |
2131 | static int try_apply_stack_adjustment |
2132 | PARAMS ((rtx, struct csa_memlist *, HOST_WIDE_INT, HOST_WIDE_INT)); | |
2133 | static void combine_stack_adjustments_for_block PARAMS ((basic_block)); | |
174fa2c4 | 2134 | static int record_stack_memrefs PARAMS ((rtx *, void *)); |
1e7f0a48 RH |
2135 | |
2136 | ||
2137 | /* Main entry point for stack adjustment combination. */ | |
2138 | ||
2139 | void | |
2140 | combine_stack_adjustments () | |
2141 | { | |
e0082a72 | 2142 | basic_block bb; |
1e7f0a48 | 2143 | |
e0082a72 ZD |
2144 | FOR_EACH_BB (bb) |
2145 | combine_stack_adjustments_for_block (bb); | |
1e7f0a48 RH |
2146 | } |
2147 | ||
2148 | /* Recognize a MEM of the form (sp) or (plus sp const). */ | |
2149 | ||
2150 | static int | |
9e11785b RH |
2151 | stack_memref_p (x) |
2152 | rtx x; | |
1e7f0a48 | 2153 | { |
9e11785b RH |
2154 | if (GET_CODE (x) != MEM) |
2155 | return 0; | |
2156 | x = XEXP (x, 0); | |
2157 | ||
2158 | if (x == stack_pointer_rtx) | |
2159 | return 1; | |
2160 | if (GET_CODE (x) == PLUS | |
2161 | && XEXP (x, 0) == stack_pointer_rtx | |
2162 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2163 | return 1; | |
2164 | ||
2165 | return 0; | |
1e7f0a48 RH |
2166 | } |
2167 | ||
2168 | /* Recognize either normal single_set or the hack in i386.md for | |
2169 | tying fp and sp adjustments. */ | |
2170 | ||
2171 | static rtx | |
2172 | single_set_for_csa (insn) | |
2173 | rtx insn; | |
2174 | { | |
2175 | int i; | |
2176 | rtx tmp = single_set (insn); | |
2177 | if (tmp) | |
2178 | return tmp; | |
2179 | ||
2180 | if (GET_CODE (insn) != INSN | |
2181 | || GET_CODE (PATTERN (insn)) != PARALLEL) | |
2182 | return NULL_RTX; | |
2183 | ||
2184 | tmp = PATTERN (insn); | |
2185 | if (GET_CODE (XVECEXP (tmp, 0, 0)) != SET) | |
2186 | return NULL_RTX; | |
2187 | ||
2188 | for (i = 1; i < XVECLEN (tmp, 0); ++i) | |
2189 | { | |
2190 | rtx this = XVECEXP (tmp, 0, i); | |
2191 | ||
2192 | /* The special case is allowing a no-op set. */ | |
2193 | if (GET_CODE (this) == SET | |
2194 | && SET_SRC (this) == SET_DEST (this)) | |
2195 | ; | |
2196 | else if (GET_CODE (this) != CLOBBER | |
2197 | && GET_CODE (this) != USE) | |
2198 | return NULL_RTX; | |
2199 | } | |
2200 | ||
2201 | return XVECEXP (tmp, 0, 0); | |
2202 | } | |
2203 | ||
2204 | /* Free the list of csa_memlist nodes. */ | |
2205 | ||
2206 | static void | |
2207 | free_csa_memlist (memlist) | |
2208 | struct csa_memlist *memlist; | |
2209 | { | |
2210 | struct csa_memlist *next; | |
2211 | for (; memlist ; memlist = next) | |
2212 | { | |
2213 | next = memlist->next; | |
2214 | free (memlist); | |
2215 | } | |
2216 | } | |
2217 | ||
2218 | /* Create a new csa_memlist node from the given memory reference. | |
2219 | It is already known that the memory is stack_memref_p. */ | |
2220 | ||
2221 | static struct csa_memlist * | |
2222 | record_one_stack_memref (insn, mem, next_memlist) | |
5a97f7c2 | 2223 | rtx insn, *mem; |
1e7f0a48 RH |
2224 | struct csa_memlist *next_memlist; |
2225 | { | |
2226 | struct csa_memlist *ml; | |
2227 | ||
2228 | ml = (struct csa_memlist *) xmalloc (sizeof (*ml)); | |
2229 | ||
5a97f7c2 | 2230 | if (XEXP (*mem, 0) == stack_pointer_rtx) |
1e7f0a48 RH |
2231 | ml->sp_offset = 0; |
2232 | else | |
5a97f7c2 | 2233 | ml->sp_offset = INTVAL (XEXP (XEXP (*mem, 0), 1)); |
1e7f0a48 RH |
2234 | |
2235 | ml->insn = insn; | |
2236 | ml->mem = mem; | |
2237 | ml->next = next_memlist; | |
2238 | ||
2239 | return ml; | |
2240 | } | |
2241 | ||
2242 | /* Attempt to apply ADJUST to the stack adjusting insn INSN, as well | |
2243 | as each of the memories in MEMLIST. Return true on success. */ | |
2244 | ||
2245 | static int | |
2246 | try_apply_stack_adjustment (insn, memlist, new_adjust, delta) | |
2247 | rtx insn; | |
2248 | struct csa_memlist *memlist; | |
2249 | HOST_WIDE_INT new_adjust, delta; | |
2250 | { | |
2251 | struct csa_memlist *ml; | |
2252 | rtx set; | |
2253 | ||
1e7f0a48 RH |
2254 | set = single_set_for_csa (insn); |
2255 | validate_change (insn, &XEXP (SET_SRC (set), 1), GEN_INT (new_adjust), 1); | |
2256 | ||
2257 | for (ml = memlist; ml ; ml = ml->next) | |
f1ec5147 RK |
2258 | validate_change |
2259 | (ml->insn, ml->mem, | |
2260 | replace_equiv_address_nv (*ml->mem, | |
2261 | plus_constant (stack_pointer_rtx, | |
2262 | ml->sp_offset - delta)), 1); | |
1e7f0a48 RH |
2263 | |
2264 | if (apply_change_group ()) | |
2265 | { | |
2266 | /* Succeeded. Update our knowledge of the memory references. */ | |
2267 | for (ml = memlist; ml ; ml = ml->next) | |
2268 | ml->sp_offset -= delta; | |
2269 | ||
2270 | return 1; | |
2271 | } | |
2272 | else | |
2273 | return 0; | |
2274 | } | |
2275 | ||
a2ee8430 JH |
2276 | /* Called via for_each_rtx and used to record all stack memory references in |
2277 | the insn and discard all other stack pointer references. */ | |
2278 | struct record_stack_memrefs_data | |
2279 | { | |
2280 | rtx insn; | |
2281 | struct csa_memlist *memlist; | |
2282 | }; | |
2283 | ||
2284 | static int | |
2285 | record_stack_memrefs (xp, data) | |
2286 | rtx *xp; | |
2287 | void *data; | |
2288 | { | |
2289 | rtx x = *xp; | |
2290 | struct record_stack_memrefs_data *d = | |
2291 | (struct record_stack_memrefs_data *) data; | |
2292 | if (!x) | |
2293 | return 0; | |
2294 | switch (GET_CODE (x)) | |
2295 | { | |
2296 | case MEM: | |
2297 | if (!reg_mentioned_p (stack_pointer_rtx, x)) | |
2298 | return -1; | |
2299 | /* We are not able to handle correctly all possible memrefs containing | |
f63d1bf7 | 2300 | stack pointer, so this check is necessary. */ |
a2ee8430 JH |
2301 | if (stack_memref_p (x)) |
2302 | { | |
2303 | d->memlist = record_one_stack_memref (d->insn, xp, d->memlist); | |
2304 | return -1; | |
2305 | } | |
2306 | return 1; | |
2307 | case REG: | |
d60e5448 MM |
2308 | /* ??? We want be able to handle non-memory stack pointer |
2309 | references later. For now just discard all insns refering to | |
2310 | stack pointer outside mem expressions. We would probably | |
2311 | want to teach validate_replace to simplify expressions first. | |
2312 | ||
2313 | We can't just compare with STACK_POINTER_RTX because the | |
2314 | reference to the stack pointer might be in some other mode. | |
2315 | In particular, an explict clobber in an asm statement will | |
2316 | result in a QImode clober. */ | |
2317 | if (REGNO (x) == STACK_POINTER_REGNUM) | |
a2ee8430 JH |
2318 | return 1; |
2319 | break; | |
2320 | default: | |
2321 | break; | |
2322 | } | |
2323 | return 0; | |
2324 | } | |
2325 | ||
1e7f0a48 RH |
2326 | /* Subroutine of combine_stack_adjustments, called for each basic block. */ |
2327 | ||
174fa2c4 | 2328 | static void |
1e7f0a48 RH |
2329 | combine_stack_adjustments_for_block (bb) |
2330 | basic_block bb; | |
2331 | { | |
2332 | HOST_WIDE_INT last_sp_adjust = 0; | |
2333 | rtx last_sp_set = NULL_RTX; | |
2334 | struct csa_memlist *memlist = NULL; | |
78414d74 | 2335 | rtx insn, next, set; |
a2ee8430 | 2336 | struct record_stack_memrefs_data data; |
78414d74 | 2337 | bool end_of_block = false; |
1e7f0a48 | 2338 | |
78414d74 | 2339 | for (insn = bb->head; !end_of_block ; insn = next) |
1e7f0a48 | 2340 | { |
78414d74 | 2341 | end_of_block = insn == bb->end; |
1e7f0a48 RH |
2342 | next = NEXT_INSN (insn); |
2343 | ||
a2ee8430 | 2344 | if (! INSN_P (insn)) |
78414d74 | 2345 | continue; |
1e7f0a48 RH |
2346 | |
2347 | set = single_set_for_csa (insn); | |
2348 | if (set) | |
2349 | { | |
2350 | rtx dest = SET_DEST (set); | |
2351 | rtx src = SET_SRC (set); | |
2352 | ||
2353 | /* Find constant additions to the stack pointer. */ | |
2354 | if (dest == stack_pointer_rtx | |
2355 | && GET_CODE (src) == PLUS | |
2356 | && XEXP (src, 0) == stack_pointer_rtx | |
2357 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2358 | { | |
2359 | HOST_WIDE_INT this_adjust = INTVAL (XEXP (src, 1)); | |
2360 | ||
2361 | /* If we've not seen an adjustment previously, record | |
2362 | it now and continue. */ | |
2363 | if (! last_sp_set) | |
2364 | { | |
2365 | last_sp_set = insn; | |
2366 | last_sp_adjust = this_adjust; | |
78414d74 | 2367 | continue; |
1e7f0a48 RH |
2368 | } |
2369 | ||
2370 | /* If not all recorded memrefs can be adjusted, or the | |
2371 | adjustment is now too large for a constant addition, | |
595c2290 JH |
2372 | we cannot merge the two stack adjustments. |
2373 | ||
2374 | Also we need to be carefull to not move stack pointer | |
2375 | such that we create stack accesses outside the allocated | |
2376 | area. We can combine an allocation into the first insn, | |
2377 | or a deallocation into the second insn. We can not | |
2378 | combine an allocation followed by a deallocation. | |
2379 | ||
ff7cc307 | 2380 | The only somewhat frequent occurrence of the later is when |
595c2290 JH |
2381 | a function allocates a stack frame but does not use it. |
2382 | For this case, we would need to analyze rtl stream to be | |
2383 | sure that allocated area is really unused. This means not | |
2384 | only checking the memory references, but also all registers | |
2385 | or global memory references possibly containing a stack | |
2386 | frame address. | |
2387 | ||
2388 | Perhaps the best way to address this problem is to teach | |
2389 | gcc not to allocate stack for objects never used. */ | |
2390 | ||
2391 | /* Combine an allocation into the first instruction. */ | |
2392 | if (STACK_GROWS_DOWNWARD ? this_adjust <= 0 : this_adjust >= 0) | |
1e7f0a48 | 2393 | { |
595c2290 JH |
2394 | if (try_apply_stack_adjustment (last_sp_set, memlist, |
2395 | last_sp_adjust + this_adjust, | |
2396 | this_adjust)) | |
2397 | { | |
2398 | /* It worked! */ | |
78414d74 | 2399 | delete_insn (insn); |
595c2290 | 2400 | last_sp_adjust += this_adjust; |
78414d74 | 2401 | continue; |
595c2290 | 2402 | } |
1e7f0a48 RH |
2403 | } |
2404 | ||
595c2290 JH |
2405 | /* Otherwise we have a deallocation. Do not combine with |
2406 | a previous allocation. Combine into the second insn. */ | |
2407 | else if (STACK_GROWS_DOWNWARD | |
2408 | ? last_sp_adjust >= 0 : last_sp_adjust <= 0) | |
1e7f0a48 | 2409 | { |
595c2290 JH |
2410 | if (try_apply_stack_adjustment (insn, memlist, |
2411 | last_sp_adjust + this_adjust, | |
2412 | -last_sp_adjust)) | |
2413 | { | |
2414 | /* It worked! */ | |
53c17031 | 2415 | delete_insn (last_sp_set); |
595c2290 JH |
2416 | last_sp_set = insn; |
2417 | last_sp_adjust += this_adjust; | |
2418 | free_csa_memlist (memlist); | |
2419 | memlist = NULL; | |
78414d74 | 2420 | continue; |
595c2290 | 2421 | } |
1e7f0a48 RH |
2422 | } |
2423 | ||
78414d74 RS |
2424 | /* Combination failed. Restart processing from here. If |
2425 | deallocation+allocation conspired to cancel, we can | |
2426 | delete the old deallocation insn. */ | |
2427 | if (last_sp_set && last_sp_adjust == 0) | |
2428 | delete_insn (insn); | |
595c2290 JH |
2429 | free_csa_memlist (memlist); |
2430 | memlist = NULL; | |
2431 | last_sp_set = insn; | |
2432 | last_sp_adjust = this_adjust; | |
78414d74 | 2433 | continue; |
1e7f0a48 RH |
2434 | } |
2435 | ||
1e7f0a48 RH |
2436 | /* Find a predecrement of exactly the previous adjustment and |
2437 | turn it into a direct store. Obviously we can't do this if | |
2438 | there were any intervening uses of the stack pointer. */ | |
2439 | if (memlist == NULL | |
1e7f0a48 | 2440 | && GET_CODE (dest) == MEM |
756d6f0c JH |
2441 | && ((GET_CODE (XEXP (dest, 0)) == PRE_DEC |
2442 | && (last_sp_adjust | |
2443 | == (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (dest)))) | |
2444 | || (GET_CODE (XEXP (dest, 0)) == PRE_MODIFY | |
2445 | && GET_CODE (XEXP (XEXP (dest, 0), 1)) == PLUS | |
2446 | && XEXP (XEXP (XEXP (dest, 0), 1), 0) == stack_pointer_rtx | |
2447 | && (GET_CODE (XEXP (XEXP (XEXP (dest, 0), 1), 1)) | |
2448 | == CONST_INT) | |
2449 | && (INTVAL (XEXP (XEXP (XEXP (dest, 0), 1), 1)) | |
2450 | == -last_sp_adjust))) | |
1e7f0a48 | 2451 | && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx |
9e11785b | 2452 | && ! reg_mentioned_p (stack_pointer_rtx, src) |
5d64361b | 2453 | && memory_address_p (GET_MODE (dest), stack_pointer_rtx) |
1e7f0a48 | 2454 | && validate_change (insn, &SET_DEST (set), |
792760b9 RK |
2455 | replace_equiv_address (dest, |
2456 | stack_pointer_rtx), | |
2457 | 0)) | |
1e7f0a48 | 2458 | { |
53c17031 | 2459 | delete_insn (last_sp_set); |
1e7f0a48 RH |
2460 | free_csa_memlist (memlist); |
2461 | memlist = NULL; | |
2462 | last_sp_set = NULL_RTX; | |
2463 | last_sp_adjust = 0; | |
78414d74 | 2464 | continue; |
1e7f0a48 RH |
2465 | } |
2466 | } | |
2467 | ||
a2ee8430 JH |
2468 | data.insn = insn; |
2469 | data.memlist = memlist; | |
2470 | if (GET_CODE (insn) != CALL_INSN && last_sp_set | |
2471 | && !for_each_rtx (&PATTERN (insn), record_stack_memrefs, &data)) | |
2472 | { | |
2473 | memlist = data.memlist; | |
78414d74 | 2474 | continue; |
a2ee8430 JH |
2475 | } |
2476 | memlist = data.memlist; | |
2477 | ||
174fa2c4 | 2478 | /* Otherwise, we were not able to process the instruction. |
1e7f0a48 RH |
2479 | Do not continue collecting data across such a one. */ |
2480 | if (last_sp_set | |
2481 | && (GET_CODE (insn) == CALL_INSN | |
2482 | || reg_mentioned_p (stack_pointer_rtx, PATTERN (insn)))) | |
2483 | { | |
78414d74 RS |
2484 | if (last_sp_set && last_sp_adjust == 0) |
2485 | delete_insn (last_sp_set); | |
1e7f0a48 RH |
2486 | free_csa_memlist (memlist); |
2487 | memlist = NULL; | |
2488 | last_sp_set = NULL_RTX; | |
2489 | last_sp_adjust = 0; | |
2490 | } | |
1e7f0a48 RH |
2491 | } |
2492 | ||
78414d74 RS |
2493 | if (last_sp_set && last_sp_adjust == 0) |
2494 | delete_insn (last_sp_set); | |
1e7f0a48 | 2495 | } |