]>
Commit | Line | Data |
---|---|---|
8c660648 | 1 | /* Move registers around to reduce number of move instructions needed. |
6fb5fa3c DB |
2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, |
3 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
4 | Free Software Foundation, Inc. | |
8c660648 | 5 | |
1322177d | 6 | This file is part of GCC. |
8c660648 | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
8c660648 | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
8c660648 JL |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
8c660648 JL |
21 | |
22 | ||
23 | /* This module looks for cases where matching constraints would force | |
24 | an instruction to need a reload, and this reload would be a register | |
25 | to register move. It then attempts to change the registers used by the | |
26 | instruction to avoid the move instruction. */ | |
27 | ||
28 | #include "config.h" | |
670ee920 | 29 | #include "system.h" |
4977bab6 ZW |
30 | #include "coretypes.h" |
31 | #include "tm.h" | |
789f983a | 32 | #include "rtl.h" /* stdio.h must precede rtl.h for FFS. */ |
6baf1cc8 | 33 | #include "tm_p.h" |
8c660648 JL |
34 | #include "insn-config.h" |
35 | #include "recog.h" | |
36 | #include "output.h" | |
8c660648 | 37 | #include "regs.h" |
184bb750 R |
38 | #include "hard-reg-set.h" |
39 | #include "flags.h" | |
49ad7cfa | 40 | #include "function.h" |
184bb750 | 41 | #include "expr.h" |
ddc8bed2 | 42 | #include "basic-block.h" |
1a5428f7 | 43 | #include "except.h" |
2e107e9e | 44 | #include "toplev.h" |
8461e984 | 45 | #include "reload.h" |
ef330312 PB |
46 | #include "timevar.h" |
47 | #include "tree-pass.h" | |
6fb5fa3c | 48 | #include "df.h" |
595c2290 | 49 | |
0c20a65f AJ |
50 | static int perhaps_ends_bb_p (rtx); |
51 | static int optimize_reg_copy_1 (rtx, rtx, rtx); | |
52 | static void optimize_reg_copy_2 (rtx, rtx, rtx); | |
53 | static void optimize_reg_copy_3 (rtx, rtx, rtx); | |
a78f3e71 | 54 | static void copy_src_to_dest (rtx, rtx, rtx); |
8c660648 | 55 | |
184bb750 R |
56 | struct match { |
57 | int with[MAX_RECOG_OPERANDS]; | |
58 | enum { READ, WRITE, READWRITE } use[MAX_RECOG_OPERANDS]; | |
59 | int commutative[MAX_RECOG_OPERANDS]; | |
60 | int early_clobber[MAX_RECOG_OPERANDS]; | |
61 | }; | |
62 | ||
0c20a65f AJ |
63 | static rtx discover_flags_reg (void); |
64 | static void mark_flags_life_zones (rtx); | |
65 | static void flags_set_1 (rtx, rtx, void *); | |
66 | ||
67 | static int try_auto_increment (rtx, rtx, rtx, rtx, HOST_WIDE_INT, int); | |
68 | static int find_matches (rtx, struct match *); | |
69 | static void replace_in_call_usage (rtx *, unsigned int, rtx, rtx); | |
10d22567 | 70 | static int fixup_match_1 (rtx, rtx, rtx, rtx, rtx, int, int, int); |
0c20a65f AJ |
71 | static int stable_and_no_regs_but_for_p (rtx, rtx, rtx); |
72 | static int regclass_compatible_p (int, int); | |
73 | static int replacement_quality (rtx); | |
10d22567 | 74 | static int fixup_match_2 (rtx, rtx, rtx, rtx); |
8c660648 | 75 | |
40f03658 | 76 | /* Return nonzero if registers with CLASS1 and CLASS2 can be merged without |
3bb806ed R |
77 | causing too much register allocation problems. */ |
78 | static int | |
0c20a65f | 79 | regclass_compatible_p (int class0, int class1) |
3bb806ed R |
80 | { |
81 | return (class0 == class1 | |
82 | || (reg_class_subset_p (class0, class1) | |
83 | && ! CLASS_LIKELY_SPILLED_P (class0)) | |
84 | || (reg_class_subset_p (class1, class0) | |
85 | && ! CLASS_LIKELY_SPILLED_P (class1))); | |
86 | } | |
87 | ||
6fb5fa3c DB |
88 | /* Find the place in the rtx X where REG is used as a memory address. |
89 | Return the MEM rtx that so uses it. | |
90 | If PLUSCONST is nonzero, search instead for a memory address equivalent to | |
91 | (plus REG (const_int PLUSCONST)). | |
92 | ||
93 | If such an address does not appear, return 0. | |
94 | If REG appears more than once, or is used other than in such an address, | |
95 | return (rtx) 1. */ | |
96 | ||
97 | static rtx | |
98 | find_use_as_address (rtx x, rtx reg, HOST_WIDE_INT plusconst) | |
99 | { | |
100 | enum rtx_code code = GET_CODE (x); | |
101 | const char * const fmt = GET_RTX_FORMAT (code); | |
102 | int i; | |
103 | rtx value = 0; | |
104 | rtx tem; | |
105 | ||
106 | if (code == MEM && XEXP (x, 0) == reg && plusconst == 0) | |
107 | return x; | |
108 | ||
109 | if (code == MEM && GET_CODE (XEXP (x, 0)) == PLUS | |
110 | && XEXP (XEXP (x, 0), 0) == reg | |
111 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
112 | && INTVAL (XEXP (XEXP (x, 0), 1)) == plusconst) | |
113 | return x; | |
114 | ||
115 | if (code == SIGN_EXTRACT || code == ZERO_EXTRACT) | |
116 | { | |
117 | /* If REG occurs inside a MEM used in a bit-field reference, | |
118 | that is unacceptable. */ | |
119 | if (find_use_as_address (XEXP (x, 0), reg, 0) != 0) | |
120 | return (rtx) (size_t) 1; | |
121 | } | |
122 | ||
123 | if (x == reg) | |
124 | return (rtx) (size_t) 1; | |
125 | ||
126 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
127 | { | |
128 | if (fmt[i] == 'e') | |
129 | { | |
130 | tem = find_use_as_address (XEXP (x, i), reg, plusconst); | |
131 | if (value == 0) | |
132 | value = tem; | |
133 | else if (tem != 0) | |
134 | return (rtx) (size_t) 1; | |
135 | } | |
136 | else if (fmt[i] == 'E') | |
137 | { | |
138 | int j; | |
139 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
140 | { | |
141 | tem = find_use_as_address (XVECEXP (x, i, j), reg, plusconst); | |
142 | if (value == 0) | |
143 | value = tem; | |
144 | else if (tem != 0) | |
145 | return (rtx) (size_t) 1; | |
146 | } | |
147 | } | |
148 | } | |
149 | ||
150 | return value; | |
151 | } | |
152 | ||
153 | ||
8c660648 JL |
154 | /* INC_INSN is an instruction that adds INCREMENT to REG. |
155 | Try to fold INC_INSN as a post/pre in/decrement into INSN. | |
156 | Iff INC_INSN_SET is nonzero, inc_insn has a destination different from src. | |
157 | Return nonzero for success. */ | |
158 | static int | |
0c20a65f AJ |
159 | try_auto_increment (rtx insn, rtx inc_insn, rtx inc_insn_set, rtx reg, |
160 | HOST_WIDE_INT increment, int pre) | |
8c660648 JL |
161 | { |
162 | enum rtx_code inc_code; | |
163 | ||
164 | rtx pset = single_set (insn); | |
165 | if (pset) | |
166 | { | |
167 | /* Can't use the size of SET_SRC, we might have something like | |
168 | (sign_extend:SI (mem:QI ... */ | |
169 | rtx use = find_use_as_address (pset, reg, 0); | |
60e8b9f0 | 170 | if (use != 0 && use != (rtx) (size_t) 1) |
8c660648 JL |
171 | { |
172 | int size = GET_MODE_SIZE (GET_MODE (use)); | |
173 | if (0 | |
940da324 JL |
174 | || (HAVE_POST_INCREMENT |
175 | && pre == 0 && (inc_code = POST_INC, increment == size)) | |
176 | || (HAVE_PRE_INCREMENT | |
177 | && pre == 1 && (inc_code = PRE_INC, increment == size)) | |
178 | || (HAVE_POST_DECREMENT | |
179 | && pre == 0 && (inc_code = POST_DEC, increment == -size)) | |
180 | || (HAVE_PRE_DECREMENT | |
181 | && pre == 1 && (inc_code = PRE_DEC, increment == -size)) | |
184bb750 R |
182 | ) |
183 | { | |
184 | if (inc_insn_set) | |
185 | validate_change | |
174fa2c4 | 186 | (inc_insn, |
184bb750 | 187 | &SET_SRC (inc_insn_set), |
8c660648 | 188 | XEXP (SET_SRC (inc_insn_set), 0), 1); |
184bb750 | 189 | validate_change (insn, &XEXP (use, 0), |
38a448ca | 190 | gen_rtx_fmt_e (inc_code, Pmode, reg), 1); |
184bb750 R |
191 | if (apply_change_group ()) |
192 | { | |
2f33c635 HB |
193 | /* If there is a REG_DEAD note on this insn, we must |
194 | change this not to REG_UNUSED meaning that the register | |
195 | is set, but the value is dead. Failure to do so will | |
0e61db61 | 196 | result in a sched1 dieing -- when it recomputes lifetime |
2f33c635 HB |
197 | information, the number of REG_DEAD notes will have |
198 | changed. */ | |
199 | rtx note = find_reg_note (insn, REG_DEAD, reg); | |
200 | if (note) | |
201 | PUT_MODE (note, REG_UNUSED); | |
202 | ||
184bb750 | 203 | REG_NOTES (insn) |
38a448ca RH |
204 | = gen_rtx_EXPR_LIST (REG_INC, |
205 | reg, REG_NOTES (insn)); | |
184bb750 | 206 | if (! inc_insn_set) |
ca6c03ca | 207 | delete_insn (inc_insn); |
8c660648 | 208 | return 1; |
184bb750 R |
209 | } |
210 | } | |
211 | } | |
212 | } | |
213 | return 0; | |
214 | } | |
dc2cb191 RH |
215 | \f |
216 | /* Determine if the pattern generated by add_optab has a clobber, | |
217 | such as might be issued for a flags hard register. To make the | |
218 | code elsewhere simpler, we handle cc0 in this same framework. | |
219 | ||
220 | Return the register if one was discovered. Return NULL_RTX if | |
221 | if no flags were found. Return pc_rtx if we got confused. */ | |
222 | ||
223 | static rtx | |
0c20a65f | 224 | discover_flags_reg (void) |
dc2cb191 RH |
225 | { |
226 | rtx tmp; | |
cd4b3546 | 227 | tmp = gen_rtx_REG (word_mode, 10000); |
60c81c89 | 228 | tmp = gen_add3_insn (tmp, tmp, const2_rtx); |
dc2cb191 | 229 | |
174fa2c4 | 230 | /* If we get something that isn't a simple set, or a |
dc2cb191 RH |
231 | [(set ..) (clobber ..)], this whole function will go wrong. */ |
232 | if (GET_CODE (tmp) == SET) | |
233 | return NULL_RTX; | |
234 | else if (GET_CODE (tmp) == PARALLEL) | |
235 | { | |
236 | int found; | |
237 | ||
238 | if (XVECLEN (tmp, 0) != 2) | |
239 | return pc_rtx; | |
240 | tmp = XVECEXP (tmp, 0, 1); | |
241 | if (GET_CODE (tmp) != CLOBBER) | |
242 | return pc_rtx; | |
243 | tmp = XEXP (tmp, 0); | |
244 | ||
245 | /* Don't do anything foolish if the md wanted to clobber a | |
246 | scratch or something. We only care about hard regs. | |
247 | Moreover we don't like the notion of subregs of hard regs. */ | |
248 | if (GET_CODE (tmp) == SUBREG | |
f8cfc6aa | 249 | && REG_P (SUBREG_REG (tmp)) |
dc2cb191 RH |
250 | && REGNO (SUBREG_REG (tmp)) < FIRST_PSEUDO_REGISTER) |
251 | return pc_rtx; | |
f8cfc6aa | 252 | found = (REG_P (tmp) && REGNO (tmp) < FIRST_PSEUDO_REGISTER); |
dc2cb191 | 253 | |
dc2cb191 | 254 | return (found ? tmp : NULL_RTX); |
dc2cb191 RH |
255 | } |
256 | ||
257 | return pc_rtx; | |
258 | } | |
259 | ||
260 | /* It is a tedious task identifying when the flags register is live and | |
261 | when it is safe to optimize. Since we process the instruction stream | |
262 | multiple times, locate and record these live zones by marking the | |
174fa2c4 | 263 | mode of the instructions -- |
dc2cb191 RH |
264 | |
265 | QImode is used on the instruction at which the flags becomes live. | |
266 | ||
267 | HImode is used within the range (exclusive) that the flags are | |
268 | live. Thus the user of the flags is not marked. | |
269 | ||
270 | All other instructions are cleared to VOIDmode. */ | |
271 | ||
272 | /* Used to communicate with flags_set_1. */ | |
273 | static rtx flags_set_1_rtx; | |
274 | static int flags_set_1_set; | |
275 | ||
276 | static void | |
0c20a65f | 277 | mark_flags_life_zones (rtx flags) |
dc2cb191 RH |
278 | { |
279 | int flags_regno; | |
280 | int flags_nregs; | |
e0082a72 | 281 | basic_block block; |
dc2cb191 | 282 | |
e7f5b971 RH |
283 | #ifdef HAVE_cc0 |
284 | /* If we found a flags register on a cc0 host, bail. */ | |
285 | if (flags == NULL_RTX) | |
286 | flags = cc0_rtx; | |
287 | else if (flags != cc0_rtx) | |
288 | flags = pc_rtx; | |
289 | #endif | |
174fa2c4 | 290 | |
dc2cb191 RH |
291 | /* Simple cases first: if no flags, clear all modes. If confusing, |
292 | mark the entire function as being in a flags shadow. */ | |
293 | if (flags == NULL_RTX || flags == pc_rtx) | |
294 | { | |
295 | enum machine_mode mode = (flags ? HImode : VOIDmode); | |
296 | rtx insn; | |
8e2e89f7 | 297 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
dc2cb191 RH |
298 | PUT_MODE (insn, mode); |
299 | return; | |
300 | } | |
301 | ||
302 | #ifdef HAVE_cc0 | |
303 | flags_regno = -1; | |
304 | flags_nregs = 1; | |
305 | #else | |
306 | flags_regno = REGNO (flags); | |
66fd46b6 | 307 | flags_nregs = hard_regno_nregs[flags_regno][GET_MODE (flags)]; |
dc2cb191 RH |
308 | #endif |
309 | flags_set_1_rtx = flags; | |
184bb750 | 310 | |
dc2cb191 | 311 | /* Process each basic block. */ |
e0082a72 | 312 | FOR_EACH_BB_REVERSE (block) |
dc2cb191 RH |
313 | { |
314 | rtx insn, end; | |
315 | int live; | |
316 | ||
a813c111 SB |
317 | insn = BB_HEAD (block); |
318 | end = BB_END (block); | |
dc2cb191 RH |
319 | |
320 | /* Look out for the (unlikely) case of flags being live across | |
321 | basic block boundaries. */ | |
322 | live = 0; | |
323 | #ifndef HAVE_cc0 | |
324 | { | |
325 | int i; | |
326 | for (i = 0; i < flags_nregs; ++i) | |
89a95777 | 327 | live |= REGNO_REG_SET_P (df_get_live_in (block), flags_regno + i); |
dc2cb191 RH |
328 | } |
329 | #endif | |
330 | ||
331 | while (1) | |
332 | { | |
333 | /* Process liveness in reverse order of importance -- | |
334 | alive, death, birth. This lets more important info | |
335 | overwrite the mode of lesser info. */ | |
336 | ||
2c3c49de | 337 | if (INSN_P (insn)) |
dc2cb191 RH |
338 | { |
339 | #ifdef HAVE_cc0 | |
340 | /* In the cc0 case, death is not marked in reg notes, | |
341 | but is instead the mere use of cc0 when it is alive. */ | |
342 | if (live && reg_mentioned_p (cc0_rtx, PATTERN (insn))) | |
343 | live = 0; | |
344 | #else | |
345 | /* In the hard reg case, we watch death notes. */ | |
346 | if (live && find_regno_note (insn, REG_DEAD, flags_regno)) | |
347 | live = 0; | |
348 | #endif | |
349 | PUT_MODE (insn, (live ? HImode : VOIDmode)); | |
350 | ||
d1a6adeb | 351 | /* In either case, birth is denoted simply by its presence |
dc2cb191 RH |
352 | as the destination of a set. */ |
353 | flags_set_1_set = 0; | |
84832317 | 354 | note_stores (PATTERN (insn), flags_set_1, NULL); |
dc2cb191 RH |
355 | if (flags_set_1_set) |
356 | { | |
357 | live = 1; | |
358 | PUT_MODE (insn, QImode); | |
359 | } | |
360 | } | |
361 | else | |
362 | PUT_MODE (insn, (live ? HImode : VOIDmode)); | |
363 | ||
364 | if (insn == end) | |
365 | break; | |
366 | insn = NEXT_INSN (insn); | |
367 | } | |
368 | } | |
369 | } | |
370 | ||
371 | /* A subroutine of mark_flags_life_zones, called through note_stores. */ | |
372 | ||
373 | static void | |
0c20a65f | 374 | flags_set_1 (rtx x, rtx pat, void *data ATTRIBUTE_UNUSED) |
dc2cb191 RH |
375 | { |
376 | if (GET_CODE (pat) == SET | |
377 | && reg_overlap_mentioned_p (x, flags_set_1_rtx)) | |
378 | flags_set_1_set = 1; | |
379 | } | |
380 | \f | |
184bb750 R |
381 | static int *regno_src_regno; |
382 | ||
383 | /* Indicate how good a choice REG (which appears as a source) is to replace | |
384 | a destination register with. The higher the returned value, the better | |
385 | the choice. The main objective is to avoid using a register that is | |
386 | a candidate for tying to a hard register, since the output might in | |
387 | turn be a candidate to be tied to a different hard register. */ | |
95d75019 | 388 | static int |
0c20a65f | 389 | replacement_quality (rtx reg) |
184bb750 R |
390 | { |
391 | int src_regno; | |
392 | ||
393 | /* Bad if this isn't a register at all. */ | |
f8cfc6aa | 394 | if (!REG_P (reg)) |
184bb750 R |
395 | return 0; |
396 | ||
397 | /* If this register is not meant to get a hard register, | |
398 | it is a poor choice. */ | |
399 | if (REG_LIVE_LENGTH (REGNO (reg)) < 0) | |
400 | return 0; | |
401 | ||
402 | src_regno = regno_src_regno[REGNO (reg)]; | |
403 | ||
404 | /* If it was not copied from another register, it is fine. */ | |
405 | if (src_regno < 0) | |
406 | return 3; | |
407 | ||
408 | /* Copied from a hard register? */ | |
409 | if (src_regno < FIRST_PSEUDO_REGISTER) | |
410 | return 1; | |
411 | ||
412 | /* Copied from a pseudo register - not as bad as from a hard register, | |
413 | yet still cumbersome, since the register live length will be lengthened | |
414 | when the registers get tied. */ | |
415 | return 2; | |
416 | } | |
a1c1fdd0 RK |
417 | \f |
418 | /* Return 1 if INSN might end a basic block. */ | |
419 | ||
5671bf27 | 420 | static int perhaps_ends_bb_p (rtx insn) |
a1c1fdd0 RK |
421 | { |
422 | switch (GET_CODE (insn)) | |
423 | { | |
424 | case CODE_LABEL: | |
425 | case JUMP_INSN: | |
426 | /* These always end a basic block. */ | |
427 | return 1; | |
184bb750 | 428 | |
a1c1fdd0 RK |
429 | case CALL_INSN: |
430 | /* A CALL_INSN might be the last insn of a basic block, if it is inside | |
431 | an EH region or if there are nonlocal gotos. Note that this test is | |
432 | very conservative. */ | |
a614d82e RH |
433 | if (nonlocal_goto_handler_labels) |
434 | return 1; | |
5d3cc252 | 435 | /* Fall through. */ |
a1c1fdd0 | 436 | default: |
a614d82e | 437 | return can_throw_internal (insn); |
a1c1fdd0 RK |
438 | } |
439 | } | |
440 | \f | |
1230327b R |
441 | /* INSN is a copy from SRC to DEST, both registers, and SRC does not die |
442 | in INSN. | |
443 | ||
444 | Search forward to see if SRC dies before either it or DEST is modified, | |
445 | but don't scan past the end of a basic block. If so, we can replace SRC | |
174fa2c4 | 446 | with DEST and let SRC die in INSN. |
1230327b R |
447 | |
448 | This will reduce the number of registers live in that range and may enable | |
449 | DEST to be tied to SRC, thus often saving one register in addition to a | |
450 | register-register copy. */ | |
451 | ||
452 | static int | |
0c20a65f | 453 | optimize_reg_copy_1 (rtx insn, rtx dest, rtx src) |
1230327b R |
454 | { |
455 | rtx p, q; | |
456 | rtx note; | |
457 | rtx dest_death = 0; | |
458 | int sregno = REGNO (src); | |
459 | int dregno = REGNO (dest); | |
460 | ||
dc297297 | 461 | /* We don't want to mess with hard regs if register classes are small. */ |
1230327b R |
462 | if (sregno == dregno |
463 | || (SMALL_REGISTER_CLASSES | |
464 | && (sregno < FIRST_PSEUDO_REGISTER | |
465 | || dregno < FIRST_PSEUDO_REGISTER)) | |
466 | /* We don't see all updates to SP if they are in an auto-inc memory | |
467 | reference, so we must disallow this optimization on them. */ | |
468 | || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM) | |
469 | return 0; | |
470 | ||
471 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
472 | { | |
7bf825d2 | 473 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 RK |
474 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
475 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 476 | break; |
a1c1fdd0 | 477 | else if (! INSN_P (p)) |
1230327b R |
478 | continue; |
479 | ||
480 | if (reg_set_p (src, p) || reg_set_p (dest, p) | |
51928907 HPN |
481 | /* If SRC is an asm-declared register, it must not be replaced |
482 | in any asm. Unfortunately, the REG_EXPR tree for the asm | |
483 | variable may be absent in the SRC rtx, so we can't check the | |
484 | actual register declaration easily (the asm operand will have | |
485 | it, though). To avoid complicating the test for a rare case, | |
486 | we just don't perform register replacement for a hard reg | |
487 | mentioned in an asm. */ | |
488 | || (sregno < FIRST_PSEUDO_REGISTER | |
489 | && asm_noperands (PATTERN (p)) >= 0 | |
490 | && reg_overlap_mentioned_p (src, PATTERN (p))) | |
97b69e51 DJ |
491 | /* Don't change hard registers used by a call. */ |
492 | || (CALL_P (p) && sregno < FIRST_PSEUDO_REGISTER | |
493 | && find_reg_fusage (p, USE, src)) | |
1230327b R |
494 | /* Don't change a USE of a register. */ |
495 | || (GET_CODE (PATTERN (p)) == USE | |
496 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
497 | break; | |
498 | ||
499 | /* See if all of SRC dies in P. This test is slightly more | |
500 | conservative than it needs to be. */ | |
501 | if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0 | |
502 | && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) | |
503 | { | |
504 | int failed = 0; | |
1230327b | 505 | int d_length = 0; |
89098dc1 | 506 | int s_length = 0; |
1230327b | 507 | int d_n_calls = 0; |
89098dc1 | 508 | int s_n_calls = 0; |
1230327b R |
509 | |
510 | /* We can do the optimization. Scan forward from INSN again, | |
511 | replacing regs as we go. Set FAILED if a replacement can't | |
512 | be done. In that case, we can't move the death note for SRC. | |
513 | This should be rare. */ | |
514 | ||
515 | /* Set to stop at next insn. */ | |
516 | for (q = next_real_insn (insn); | |
517 | q != next_real_insn (p); | |
518 | q = next_real_insn (q)) | |
519 | { | |
520 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
521 | { | |
522 | /* If SRC is a hard register, we might miss some | |
523 | overlapping registers with validate_replace_rtx, | |
524 | so we would have to undo it. We can't if DEST is | |
525 | present in the insn, so fail in that combination | |
526 | of cases. */ | |
527 | if (sregno < FIRST_PSEUDO_REGISTER | |
528 | && reg_mentioned_p (dest, PATTERN (q))) | |
529 | failed = 1; | |
040f69eb AK |
530 | |
531 | /* Attempt to replace all uses. */ | |
532 | else if (!validate_replace_rtx (src, dest, q)) | |
533 | failed = 1; | |
1230327b | 534 | |
040f69eb AK |
535 | /* If this succeeded, but some part of the register |
536 | is still present, undo the replacement. */ | |
537 | else if (sregno < FIRST_PSEUDO_REGISTER | |
538 | && reg_overlap_mentioned_p (src, PATTERN (q))) | |
1230327b R |
539 | { |
540 | validate_replace_rtx (dest, src, q); | |
541 | failed = 1; | |
542 | } | |
543 | } | |
544 | ||
89098dc1 JL |
545 | /* For SREGNO, count the total number of insns scanned. |
546 | For DREGNO, count the total number of insns scanned after | |
547 | passing the death note for DREGNO. */ | |
548 | s_length++; | |
1230327b R |
549 | if (dest_death) |
550 | d_length++; | |
551 | ||
552 | /* If the insn in which SRC dies is a CALL_INSN, don't count it | |
553 | as a call that has been crossed. Otherwise, count it. */ | |
4b4bf941 | 554 | if (q != p && CALL_P (q)) |
1230327b | 555 | { |
89098dc1 JL |
556 | /* Similarly, total calls for SREGNO, total calls beyond |
557 | the death note for DREGNO. */ | |
558 | s_n_calls++; | |
1230327b R |
559 | if (dest_death) |
560 | d_n_calls++; | |
561 | } | |
562 | ||
563 | /* If DEST dies here, remove the death note and save it for | |
564 | later. Make sure ALL of DEST dies here; again, this is | |
565 | overly conservative. */ | |
566 | if (dest_death == 0 | |
567 | && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0) | |
568 | { | |
569 | if (GET_MODE (XEXP (dest_death, 0)) != GET_MODE (dest)) | |
570 | failed = 1, dest_death = 0; | |
571 | else | |
572 | remove_note (q, dest_death); | |
573 | } | |
574 | } | |
575 | ||
576 | if (! failed) | |
577 | { | |
89098dc1 JL |
578 | /* These counters need to be updated if and only if we are |
579 | going to move the REG_DEAD note. */ | |
1230327b R |
580 | if (sregno >= FIRST_PSEUDO_REGISTER) |
581 | { | |
582 | if (REG_LIVE_LENGTH (sregno) >= 0) | |
583 | { | |
89098dc1 | 584 | REG_LIVE_LENGTH (sregno) -= s_length; |
1230327b R |
585 | /* REG_LIVE_LENGTH is only an approximation after |
586 | combine if sched is not run, so make sure that we | |
587 | still have a reasonable value. */ | |
588 | if (REG_LIVE_LENGTH (sregno) < 2) | |
589 | REG_LIVE_LENGTH (sregno) = 2; | |
590 | } | |
591 | ||
89098dc1 | 592 | REG_N_CALLS_CROSSED (sregno) -= s_n_calls; |
1230327b R |
593 | } |
594 | ||
595 | /* Move death note of SRC from P to INSN. */ | |
596 | remove_note (p, note); | |
597 | XEXP (note, 1) = REG_NOTES (insn); | |
598 | REG_NOTES (insn) = note; | |
599 | } | |
600 | ||
124d535f JW |
601 | /* DEST is also dead if INSN has a REG_UNUSED note for DEST. */ |
602 | if (! dest_death | |
603 | && (dest_death = find_regno_note (insn, REG_UNUSED, dregno))) | |
604 | { | |
605 | PUT_REG_NOTE_KIND (dest_death, REG_DEAD); | |
606 | remove_note (insn, dest_death); | |
607 | } | |
608 | ||
1230327b R |
609 | /* Put death note of DEST on P if we saw it die. */ |
610 | if (dest_death) | |
611 | { | |
612 | XEXP (dest_death, 1) = REG_NOTES (p); | |
613 | REG_NOTES (p) = dest_death; | |
89098dc1 JL |
614 | |
615 | if (dregno >= FIRST_PSEUDO_REGISTER) | |
616 | { | |
617 | /* If and only if we are moving the death note for DREGNO, | |
618 | then we need to update its counters. */ | |
619 | if (REG_LIVE_LENGTH (dregno) >= 0) | |
620 | REG_LIVE_LENGTH (dregno) += d_length; | |
621 | REG_N_CALLS_CROSSED (dregno) += d_n_calls; | |
622 | } | |
1230327b R |
623 | } |
624 | ||
625 | return ! failed; | |
626 | } | |
627 | ||
628 | /* If SRC is a hard register which is set or killed in some other | |
629 | way, we can't do this optimization. */ | |
630 | else if (sregno < FIRST_PSEUDO_REGISTER | |
631 | && dead_or_set_p (p, src)) | |
632 | break; | |
633 | } | |
634 | return 0; | |
635 | } | |
636 | \f | |
637 | /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have | |
638 | a sequence of insns that modify DEST followed by an insn that sets | |
639 | SRC to DEST in which DEST dies, with no prior modification of DEST. | |
640 | (There is no need to check if the insns in between actually modify | |
641 | DEST. We should not have cases where DEST is not modified, but | |
642 | the optimization is safe if no such modification is detected.) | |
643 | In that case, we can replace all uses of DEST, starting with INSN and | |
644 | ending with the set of SRC to DEST, with SRC. We do not do this | |
645 | optimization if a CALL_INSN is crossed unless SRC already crosses a | |
646 | call or if DEST dies before the copy back to SRC. | |
647 | ||
648 | It is assumed that DEST and SRC are pseudos; it is too complicated to do | |
649 | this for hard registers since the substitutions we may make might fail. */ | |
650 | ||
651 | static void | |
0c20a65f | 652 | optimize_reg_copy_2 (rtx insn, rtx dest, rtx src) |
1230327b R |
653 | { |
654 | rtx p, q; | |
655 | rtx set; | |
656 | int sregno = REGNO (src); | |
657 | int dregno = REGNO (dest); | |
658 | ||
659 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
660 | { | |
7bf825d2 | 661 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 RK |
662 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
663 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 664 | break; |
a1c1fdd0 | 665 | else if (! INSN_P (p)) |
1230327b R |
666 | continue; |
667 | ||
668 | set = single_set (p); | |
669 | if (set && SET_SRC (set) == dest && SET_DEST (set) == src | |
670 | && find_reg_note (p, REG_DEAD, dest)) | |
671 | { | |
672 | /* We can do the optimization. Scan forward from INSN again, | |
673 | replacing regs as we go. */ | |
674 | ||
675 | /* Set to stop at next insn. */ | |
676 | for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q)) | |
2c3c49de | 677 | if (INSN_P (q)) |
1230327b R |
678 | { |
679 | if (reg_mentioned_p (dest, PATTERN (q))) | |
6fb5fa3c DB |
680 | { |
681 | PATTERN (q) = replace_rtx (PATTERN (q), dest, src); | |
682 | df_insn_rescan (q); | |
683 | } | |
1230327b | 684 | |
c7a0240a SB |
685 | if (CALL_P (q)) |
686 | { | |
687 | REG_N_CALLS_CROSSED (dregno)--; | |
688 | REG_N_CALLS_CROSSED (sregno)++; | |
689 | } | |
1230327b R |
690 | } |
691 | ||
692 | remove_note (p, find_reg_note (p, REG_DEAD, dest)); | |
693 | REG_N_DEATHS (dregno)--; | |
694 | remove_note (insn, find_reg_note (insn, REG_DEAD, src)); | |
695 | REG_N_DEATHS (sregno)--; | |
696 | return; | |
697 | } | |
698 | ||
699 | if (reg_set_p (src, p) | |
700 | || find_reg_note (p, REG_DEAD, dest) | |
4b4bf941 | 701 | || (CALL_P (p) && REG_N_CALLS_CROSSED (sregno) == 0)) |
1230327b R |
702 | break; |
703 | } | |
704 | } | |
c7a0240a | 705 | |
184bb750 R |
706 | /* INSN is a ZERO_EXTEND or SIGN_EXTEND of SRC to DEST. |
707 | Look if SRC dies there, and if it is only set once, by loading | |
3d042e77 | 708 | it from memory. If so, try to incorporate the zero/sign extension |
184bb750 R |
709 | into the memory read, change SRC to the mode of DEST, and alter |
710 | the remaining accesses to use the appropriate SUBREG. This allows | |
711 | SRC and DEST to be tied later. */ | |
712 | static void | |
0c20a65f | 713 | optimize_reg_copy_3 (rtx insn, rtx dest, rtx src) |
184bb750 R |
714 | { |
715 | rtx src_reg = XEXP (src, 0); | |
716 | int src_no = REGNO (src_reg); | |
717 | int dst_no = REGNO (dest); | |
15ee342b | 718 | rtx p, set; |
184bb750 R |
719 | enum machine_mode old_mode; |
720 | ||
721 | if (src_no < FIRST_PSEUDO_REGISTER | |
722 | || dst_no < FIRST_PSEUDO_REGISTER | |
723 | || ! find_reg_note (insn, REG_DEAD, src_reg) | |
6d80a854 | 724 | || REG_N_DEATHS (src_no) != 1 |
184bb750 R |
725 | || REG_N_SETS (src_no) != 1) |
726 | return; | |
9c07e479 | 727 | for (p = PREV_INSN (insn); p && ! reg_set_p (src_reg, p); p = PREV_INSN (p)) |
a1c1fdd0 RK |
728 | /* ??? We can't scan past the end of a basic block without updating |
729 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ | |
730 | if (perhaps_ends_bb_p (p)) | |
731 | break; | |
7bf825d2 | 732 | |
9c07e479 BK |
733 | if (! p) |
734 | return; | |
735 | ||
184bb750 | 736 | if (! (set = single_set (p)) |
3c0cb5de | 737 | || !MEM_P (SET_SRC (set)) |
4fb3cbd7 BS |
738 | /* If there's a REG_EQUIV note, this must be an insn that loads an |
739 | argument. Prefer keeping the note over doing this optimization. */ | |
740 | || find_reg_note (p, REG_EQUIV, NULL_RTX) | |
184bb750 R |
741 | || SET_DEST (set) != src_reg) |
742 | return; | |
937e37cc | 743 | |
14b493d6 | 744 | /* Be conservative: although this optimization is also valid for |
972b320c R |
745 | volatile memory references, that could cause trouble in later passes. */ |
746 | if (MEM_VOLATILE_P (SET_SRC (set))) | |
747 | return; | |
748 | ||
937e37cc JL |
749 | /* Do not use a SUBREG to truncate from one mode to another if truncation |
750 | is not a nop. */ | |
751 | if (GET_MODE_BITSIZE (GET_MODE (src_reg)) <= GET_MODE_BITSIZE (GET_MODE (src)) | |
752 | && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (src)), | |
753 | GET_MODE_BITSIZE (GET_MODE (src_reg)))) | |
754 | return; | |
755 | ||
184bb750 R |
756 | old_mode = GET_MODE (src_reg); |
757 | PUT_MODE (src_reg, GET_MODE (src)); | |
758 | XEXP (src, 0) = SET_SRC (set); | |
e757da5e JL |
759 | |
760 | /* Include this change in the group so that it's easily undone if | |
761 | one of the changes in the group is invalid. */ | |
762 | validate_change (p, &SET_SRC (set), src, 1); | |
763 | ||
764 | /* Now walk forward making additional replacements. We want to be able | |
765 | to undo all the changes if a later substitution fails. */ | |
184bb750 R |
766 | while (p = NEXT_INSN (p), p != insn) |
767 | { | |
2c3c49de | 768 | if (! INSN_P (p)) |
184bb750 | 769 | continue; |
e757da5e | 770 | |
2067c116 | 771 | /* Make a tentative change. */ |
15ee342b EB |
772 | validate_replace_rtx_group (src_reg, |
773 | gen_lowpart_SUBREG (old_mode, src_reg), | |
774 | p); | |
e757da5e JL |
775 | } |
776 | ||
777 | validate_replace_rtx_group (src, src_reg, insn); | |
778 | ||
779 | /* Now see if all the changes are valid. */ | |
780 | if (! apply_change_group ()) | |
781 | { | |
782 | /* One or more changes were no good. Back out everything. */ | |
783 | PUT_MODE (src_reg, old_mode); | |
784 | XEXP (src, 0) = src_reg; | |
184bb750 | 785 | } |
4fb3cbd7 BS |
786 | else |
787 | { | |
788 | rtx note = find_reg_note (p, REG_EQUAL, NULL_RTX); | |
789 | if (note) | |
790 | remove_note (p, note); | |
791 | } | |
184bb750 R |
792 | } |
793 | ||
ddc8bed2 MM |
794 | \f |
795 | /* If we were not able to update the users of src to use dest directly, try | |
796 | instead moving the value to dest directly before the operation. */ | |
797 | ||
cab634f2 | 798 | static void |
a78f3e71 | 799 | copy_src_to_dest (rtx insn, rtx src, rtx dest) |
ddc8bed2 MM |
800 | { |
801 | rtx seq; | |
802 | rtx link; | |
803 | rtx next; | |
804 | rtx set; | |
805 | rtx move_insn; | |
806 | rtx *p_insn_notes; | |
807 | rtx *p_move_notes; | |
ddc8bed2 MM |
808 | int src_regno; |
809 | int dest_regno; | |
ddc8bed2 MM |
810 | int insn_uid; |
811 | int move_uid; | |
812 | ||
813 | /* A REG_LIVE_LENGTH of -1 indicates the register is equivalent to a constant | |
814 | or memory location and is used infrequently; a REG_LIVE_LENGTH of -2 is | |
815 | parameter when there is no frame pointer that is not allocated a register. | |
816 | For now, we just reject them, rather than incrementing the live length. */ | |
817 | ||
f8cfc6aa | 818 | if (REG_P (src) |
3ac3da71 | 819 | && REG_LIVE_LENGTH (REGNO (src)) > 0 |
f8cfc6aa | 820 | && REG_P (dest) |
3ac3da71 | 821 | && REG_LIVE_LENGTH (REGNO (dest)) > 0 |
ddc8bed2 | 822 | && (set = single_set (insn)) != NULL_RTX |
9d2106a4 R |
823 | && !reg_mentioned_p (dest, SET_SRC (set)) |
824 | && GET_MODE (src) == GET_MODE (dest)) | |
ddc8bed2 | 825 | { |
1a8fca8a R |
826 | int old_num_regs = reg_rtx_no; |
827 | ||
ddc8bed2 MM |
828 | /* Generate the src->dest move. */ |
829 | start_sequence (); | |
830 | emit_move_insn (dest, src); | |
2f937369 | 831 | seq = get_insns (); |
ddc8bed2 | 832 | end_sequence (); |
1a8fca8a R |
833 | /* If this sequence uses new registers, we may not use it. */ |
834 | if (old_num_regs != reg_rtx_no | |
835 | || ! validate_replace_rtx (src, dest, insn)) | |
836 | { | |
837 | /* We have to restore reg_rtx_no to its old value, lest | |
838 | recompute_reg_usage will try to compute the usage of the | |
839 | new regs, yet reg_n_info is not valid for them. */ | |
840 | reg_rtx_no = old_num_regs; | |
841 | return; | |
842 | } | |
ddc8bed2 MM |
843 | emit_insn_before (seq, insn); |
844 | move_insn = PREV_INSN (insn); | |
845 | p_move_notes = ®_NOTES (move_insn); | |
846 | p_insn_notes = ®_NOTES (insn); | |
847 | ||
3eae4643 | 848 | /* Move any notes mentioning src to the move instruction. */ |
ddc8bed2 MM |
849 | for (link = REG_NOTES (insn); link != NULL_RTX; link = next) |
850 | { | |
851 | next = XEXP (link, 1); | |
852 | if (XEXP (link, 0) == src) | |
853 | { | |
854 | *p_move_notes = link; | |
855 | p_move_notes = &XEXP (link, 1); | |
856 | } | |
857 | else | |
858 | { | |
859 | *p_insn_notes = link; | |
860 | p_insn_notes = &XEXP (link, 1); | |
861 | } | |
862 | } | |
863 | ||
864 | *p_move_notes = NULL_RTX; | |
865 | *p_insn_notes = NULL_RTX; | |
866 | ||
ddc8bed2 MM |
867 | insn_uid = INSN_UID (insn); |
868 | move_uid = INSN_UID (move_insn); | |
ddc8bed2 MM |
869 | |
870 | /* Update the various register tables. */ | |
871 | dest_regno = REGNO (dest); | |
6fb5fa3c | 872 | INC_REG_N_SETS (dest_regno, 1); |
ddc8bed2 | 873 | REG_LIVE_LENGTH (dest_regno)++; |
ddc8bed2 MM |
874 | src_regno = REGNO (src); |
875 | if (! find_reg_note (move_insn, REG_DEAD, src)) | |
876 | REG_LIVE_LENGTH (src_regno)++; | |
ddc8bed2 MM |
877 | } |
878 | } | |
879 | ||
65d169d9 JH |
880 | /* reg_set_in_bb[REGNO] points to basic block iff the register is set |
881 | only once in the given block and has REG_EQUAL note. */ | |
882 | ||
883 | basic_block *reg_set_in_bb; | |
884 | ||
885 | /* Size of reg_set_in_bb array. */ | |
886 | static unsigned int max_reg_computed; | |
887 | ||
ddc8bed2 | 888 | \f |
184bb750 R |
889 | /* Return whether REG is set in only one location, and is set to a |
890 | constant, but is set in a different basic block from INSN (an | |
891 | instructions which uses REG). In this case REG is equivalent to a | |
892 | constant, and we don't want to break that equivalence, because that | |
893 | may increase register pressure and make reload harder. If REG is | |
894 | set in the same basic block as INSN, we don't worry about it, | |
895 | because we'll probably need a register anyhow (??? but what if REG | |
a78f3e71 | 896 | is used in a different basic block as well as this one?). */ |
184bb750 | 897 | |
65d169d9 JH |
898 | static bool |
899 | reg_is_remote_constant_p (rtx reg, rtx insn) | |
184bb750 | 900 | { |
65d169d9 | 901 | basic_block bb; |
b3694847 | 902 | rtx p; |
65d169d9 | 903 | int max; |
184bb750 | 904 | |
65d169d9 | 905 | if (!reg_set_in_bb) |
184bb750 | 906 | { |
65d169d9 JH |
907 | max_reg_computed = max = max_reg_num (); |
908 | reg_set_in_bb = xcalloc (max, sizeof (*reg_set_in_bb)); | |
184bb750 | 909 | |
65d169d9 | 910 | FOR_EACH_BB (bb) |
a78f3e71 SB |
911 | FOR_BB_INSNS (bb, p) |
912 | { | |
913 | rtx s; | |
914 | ||
915 | if (!INSN_P (p)) | |
916 | continue; | |
917 | s = single_set (p); | |
918 | /* This is the instruction which sets REG. If there is a | |
919 | REG_EQUAL note, then REG is equivalent to a constant. */ | |
920 | if (s != 0 | |
921 | && REG_P (SET_DEST (s)) | |
922 | && REG_N_SETS (REGNO (SET_DEST (s))) == 1 | |
923 | && find_reg_note (p, REG_EQUAL, NULL_RTX)) | |
924 | reg_set_in_bb[REGNO (SET_DEST (s))] = bb; | |
925 | } | |
184bb750 | 926 | } |
a78f3e71 | 927 | |
65d169d9 JH |
928 | gcc_assert (REGNO (reg) < max_reg_computed); |
929 | if (reg_set_in_bb[REGNO (reg)] == NULL) | |
930 | return false; | |
a78f3e71 | 931 | return (reg_set_in_bb[REGNO (reg)] != BLOCK_FOR_INSN (insn)); |
184bb750 R |
932 | } |
933 | ||
b1a7d591 JW |
934 | /* INSN is adding a CONST_INT to a REG. We search backwards looking for |
935 | another add immediate instruction with the same source and dest registers, | |
936 | and if we find one, we change INSN to an increment, and return 1. If | |
937 | no changes are made, we return 0. | |
938 | ||
939 | This changes | |
940 | (set (reg100) (plus reg1 offset1)) | |
941 | ... | |
942 | (set (reg100) (plus reg1 offset2)) | |
943 | to | |
944 | (set (reg100) (plus reg1 offset1)) | |
945 | ... | |
946 | (set (reg100) (plus reg100 offset2-offset1)) */ | |
947 | ||
948 | /* ??? What does this comment mean? */ | |
14b493d6 | 949 | /* cse disrupts preincrement / postdecrement sequences when it finds a |
184bb750 | 950 | hard register as ultimate source, like the frame pointer. */ |
b1a7d591 | 951 | |
95d75019 | 952 | static int |
10d22567 | 953 | fixup_match_2 (rtx insn, rtx dst, rtx src, rtx offset) |
184bb750 R |
954 | { |
955 | rtx p, dst_death = 0; | |
956 | int length, num_calls = 0; | |
957 | ||
958 | /* If SRC dies in INSN, we'd have to move the death note. This is | |
959 | considered to be very unlikely, so we just skip the optimization | |
960 | in this case. */ | |
961 | if (find_regno_note (insn, REG_DEAD, REGNO (src))) | |
962 | return 0; | |
963 | ||
964 | /* Scan backward to find the first instruction that sets DST. */ | |
965 | ||
966 | for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
967 | { | |
968 | rtx pset; | |
969 | ||
7bf825d2 | 970 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 RK |
971 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
972 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 973 | break; |
a1c1fdd0 | 974 | else if (! INSN_P (p)) |
a6a2274a | 975 | continue; |
184bb750 | 976 | |
7bf825d2 JW |
977 | if (find_regno_note (p, REG_DEAD, REGNO (dst))) |
978 | dst_death = p; | |
979 | if (! dst_death) | |
980 | length++; | |
184bb750 R |
981 | |
982 | pset = single_set (p); | |
983 | if (pset && SET_DEST (pset) == dst | |
984 | && GET_CODE (SET_SRC (pset)) == PLUS | |
985 | && XEXP (SET_SRC (pset), 0) == src | |
986 | && GET_CODE (XEXP (SET_SRC (pset), 1)) == CONST_INT) | |
a6a2274a | 987 | { |
184bb750 R |
988 | HOST_WIDE_INT newconst |
989 | = INTVAL (offset) - INTVAL (XEXP (SET_SRC (pset), 1)); | |
1a29f703 R |
990 | rtx add = gen_add3_insn (dst, dst, GEN_INT (newconst)); |
991 | ||
992 | if (add && validate_change (insn, &PATTERN (insn), add, 0)) | |
184bb750 R |
993 | { |
994 | /* Remove the death note for DST from DST_DEATH. */ | |
995 | if (dst_death) | |
996 | { | |
997 | remove_death (REGNO (dst), dst_death); | |
998 | REG_LIVE_LENGTH (REGNO (dst)) += length; | |
999 | REG_N_CALLS_CROSSED (REGNO (dst)) += num_calls; | |
1000 | } | |
1001 | ||
10d22567 ZD |
1002 | if (dump_file) |
1003 | fprintf (dump_file, | |
184bb750 R |
1004 | "Fixed operand of insn %d.\n", |
1005 | INSN_UID (insn)); | |
1006 | ||
1007 | #ifdef AUTO_INC_DEC | |
1008 | for (p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
1009 | { | |
4b4bf941 JQ |
1010 | if (LABEL_P (p) |
1011 | || JUMP_P (p)) | |
184bb750 | 1012 | break; |
2c3c49de | 1013 | if (! INSN_P (p)) |
e27a5106 | 1014 | continue; |
184bb750 R |
1015 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) |
1016 | { | |
1017 | if (try_auto_increment (p, insn, 0, dst, newconst, 0)) | |
1018 | return 1; | |
1019 | break; | |
1020 | } | |
1021 | } | |
1022 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
1023 | { | |
4b4bf941 JQ |
1024 | if (LABEL_P (p) |
1025 | || JUMP_P (p)) | |
184bb750 | 1026 | break; |
2c3c49de | 1027 | if (! INSN_P (p)) |
8543c01e | 1028 | continue; |
184bb750 R |
1029 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) |
1030 | { | |
1031 | try_auto_increment (p, insn, 0, dst, newconst, 1); | |
1032 | break; | |
1033 | } | |
1034 | } | |
1035 | #endif | |
1036 | return 1; | |
1037 | } | |
a6a2274a | 1038 | } |
184bb750 R |
1039 | |
1040 | if (reg_set_p (dst, PATTERN (p))) | |
a6a2274a | 1041 | break; |
184bb750 R |
1042 | |
1043 | /* If we have passed a call instruction, and the | |
1044 | pseudo-reg SRC is not already live across a call, | |
1045 | then don't perform the optimization. */ | |
1046 | /* reg_set_p is overly conservative for CALL_INSNS, thinks that all | |
1047 | hard regs are clobbered. Thus, we only use it for src for | |
1048 | non-call insns. */ | |
4b4bf941 | 1049 | if (CALL_P (p)) |
a6a2274a | 1050 | { |
184bb750 R |
1051 | if (! dst_death) |
1052 | num_calls++; | |
1053 | ||
a6a2274a KH |
1054 | if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) |
1055 | break; | |
184bb750 R |
1056 | |
1057 | if (call_used_regs [REGNO (dst)] | |
1058 | || find_reg_fusage (p, CLOBBER, dst)) | |
1059 | break; | |
a6a2274a | 1060 | } |
184bb750 | 1061 | else if (reg_set_p (src, PATTERN (p))) |
a6a2274a | 1062 | break; |
8c660648 | 1063 | } |
184bb750 | 1064 | |
8c660648 JL |
1065 | return 0; |
1066 | } | |
8c660648 | 1067 | |
3721581a JJ |
1068 | /* Main entry for the register move optimization. |
1069 | F is the first instruction. | |
1070 | NREGS is one plus the highest pseudo-reg number used in the instruction. | |
1071 | REGMOVE_DUMP_FILE is a stream for output of a trace of actions taken | |
1072 | (or 0 if none should be output). */ | |
1073 | ||
fe3c3571 | 1074 | static void |
10d22567 | 1075 | regmove_optimize (rtx f, int nregs) |
8c660648 | 1076 | { |
8c660648 | 1077 | rtx insn; |
184bb750 | 1078 | struct match match; |
8c660648 | 1079 | int pass; |
3bb806ed | 1080 | int i; |
ddc8bed2 | 1081 | rtx copy_src, copy_dst; |
184bb750 | 1082 | |
a614d82e RH |
1083 | /* ??? Hack. Regmove doesn't examine the CFG, and gets mightily |
1084 | confused by non-call exceptions ending blocks. */ | |
1085 | if (flag_non_call_exceptions) | |
1086 | return; | |
1087 | ||
6fb5fa3c DB |
1088 | df_note_add_problem (); |
1089 | df_analyze (); | |
1090 | ||
1091 | regstat_init_n_sets_and_refs (); | |
1092 | regstat_compute_ri (); | |
1093 | ||
dc2cb191 | 1094 | /* Find out where a potential flags register is live, and so that we |
14b493d6 | 1095 | can suppress some optimizations in those zones. */ |
dc2cb191 RH |
1096 | mark_flags_life_zones (discover_flags_reg ()); |
1097 | ||
5ed6ace5 | 1098 | regno_src_regno = XNEWVEC (int, nregs); |
a78f3e71 SB |
1099 | for (i = nregs; --i >= 0; ) |
1100 | regno_src_regno[i] = -1; | |
ddc8bed2 | 1101 | |
8c660648 JL |
1102 | /* A forward/backward pass. Replace output operands with input operands. */ |
1103 | ||
184bb750 | 1104 | for (pass = 0; pass <= 2; pass++) |
8c660648 | 1105 | { |
184bb750 | 1106 | if (! flag_regmove && pass >= flag_expensive_optimizations) |
4da896b2 | 1107 | goto done; |
184bb750 | 1108 | |
10d22567 ZD |
1109 | if (dump_file) |
1110 | fprintf (dump_file, "Starting %s pass...\n", | |
8c660648 JL |
1111 | pass ? "backward" : "forward"); |
1112 | ||
1113 | for (insn = pass ? get_last_insn () : f; insn; | |
1114 | insn = pass ? PREV_INSN (insn) : NEXT_INSN (insn)) | |
1115 | { | |
184bb750 | 1116 | rtx set; |
0eadeb15 | 1117 | int op_no, match_no; |
184bb750 | 1118 | |
184bb750 R |
1119 | set = single_set (insn); |
1120 | if (! set) | |
1121 | continue; | |
8c660648 | 1122 | |
184bb750 R |
1123 | if (flag_expensive_optimizations && ! pass |
1124 | && (GET_CODE (SET_SRC (set)) == SIGN_EXTEND | |
1125 | || GET_CODE (SET_SRC (set)) == ZERO_EXTEND) | |
f8cfc6aa JQ |
1126 | && REG_P (XEXP (SET_SRC (set), 0)) |
1127 | && REG_P (SET_DEST (set))) | |
184bb750 R |
1128 | optimize_reg_copy_3 (insn, SET_DEST (set), SET_SRC (set)); |
1129 | ||
1130 | if (flag_expensive_optimizations && ! pass | |
f8cfc6aa JQ |
1131 | && REG_P (SET_SRC (set)) |
1132 | && REG_P (SET_DEST (set))) | |
184bb750 R |
1133 | { |
1134 | /* If this is a register-register copy where SRC is not dead, | |
1135 | see if we can optimize it. If this optimization succeeds, | |
1136 | it will become a copy where SRC is dead. */ | |
1137 | if ((find_reg_note (insn, REG_DEAD, SET_SRC (set)) | |
1138 | || optimize_reg_copy_1 (insn, SET_DEST (set), SET_SRC (set))) | |
1139 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) | |
8c660648 | 1140 | { |
184bb750 R |
1141 | /* Similarly for a pseudo-pseudo copy when SRC is dead. */ |
1142 | if (REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1143 | optimize_reg_copy_2 (insn, SET_DEST (set), SET_SRC (set)); | |
1144 | if (regno_src_regno[REGNO (SET_DEST (set))] < 0 | |
1145 | && SET_SRC (set) != SET_DEST (set)) | |
8c660648 | 1146 | { |
8e2e89f7 | 1147 | int srcregno = REGNO (SET_SRC (set)); |
184bb750 R |
1148 | if (regno_src_regno[srcregno] >= 0) |
1149 | srcregno = regno_src_regno[srcregno]; | |
1150 | regno_src_regno[REGNO (SET_DEST (set))] = srcregno; | |
8c660648 JL |
1151 | } |
1152 | } | |
184bb750 | 1153 | } |
a6a2274a KH |
1154 | if (! flag_regmove) |
1155 | continue; | |
184bb750 | 1156 | |
3363316f | 1157 | if (! find_matches (insn, &match)) |
184bb750 R |
1158 | continue; |
1159 | ||
1160 | /* Now scan through the operands looking for a source operand | |
1161 | which is supposed to match the destination operand. | |
1162 | Then scan forward for an instruction which uses the dest | |
1163 | operand. | |
1164 | If it dies there, then replace the dest in both operands with | |
1165 | the source operand. */ | |
1166 | ||
1ccbefce | 1167 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
184bb750 | 1168 | { |
5e9defae | 1169 | rtx src, dst, src_subreg; |
184bb750 R |
1170 | enum reg_class src_class, dst_class; |
1171 | ||
0eadeb15 | 1172 | match_no = match.with[op_no]; |
184bb750 R |
1173 | |
1174 | /* Nothing to do if the two operands aren't supposed to match. */ | |
0eadeb15 | 1175 | if (match_no < 0) |
184bb750 R |
1176 | continue; |
1177 | ||
1ccbefce RH |
1178 | src = recog_data.operand[op_no]; |
1179 | dst = recog_data.operand[match_no]; | |
184bb750 | 1180 | |
f8cfc6aa | 1181 | if (!REG_P (src)) |
184bb750 R |
1182 | continue; |
1183 | ||
1184 | src_subreg = src; | |
1185 | if (GET_CODE (dst) == SUBREG | |
1186 | && GET_MODE_SIZE (GET_MODE (dst)) | |
1187 | >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (dst)))) | |
1188 | { | |
184bb750 | 1189 | dst = SUBREG_REG (dst); |
d281a1f1 UW |
1190 | src_subreg = lowpart_subreg (GET_MODE (dst), |
1191 | src, GET_MODE (src)); | |
1192 | if (!src_subreg) | |
1193 | continue; | |
184bb750 | 1194 | } |
f8cfc6aa | 1195 | if (!REG_P (dst) |
184bb750 R |
1196 | || REGNO (dst) < FIRST_PSEUDO_REGISTER) |
1197 | continue; | |
1198 | ||
1199 | if (REGNO (src) < FIRST_PSEUDO_REGISTER) | |
1200 | { | |
0eadeb15 | 1201 | if (match.commutative[op_no] < op_no) |
184bb750 R |
1202 | regno_src_regno[REGNO (dst)] = REGNO (src); |
1203 | continue; | |
1204 | } | |
1205 | ||
1206 | if (REG_LIVE_LENGTH (REGNO (src)) < 0) | |
1207 | continue; | |
1208 | ||
0eadeb15 | 1209 | /* op_no/src must be a read-only operand, and |
184bb750 | 1210 | match_operand/dst must be a write-only operand. */ |
0eadeb15 BS |
1211 | if (match.use[op_no] != READ |
1212 | || match.use[match_no] != WRITE) | |
184bb750 R |
1213 | continue; |
1214 | ||
0eadeb15 | 1215 | if (match.early_clobber[match_no] |
4b983fdc | 1216 | && count_occurrences (PATTERN (insn), src, 0) > 1) |
184bb750 R |
1217 | continue; |
1218 | ||
1219 | /* Make sure match_operand is the destination. */ | |
1ccbefce | 1220 | if (recog_data.operand[match_no] != SET_DEST (set)) |
184bb750 R |
1221 | continue; |
1222 | ||
dc297297 | 1223 | /* If the operands already match, then there is nothing to do. */ |
1ccbefce | 1224 | if (operands_match_p (src, dst)) |
184bb750 R |
1225 | continue; |
1226 | ||
1ccbefce RH |
1227 | /* But in the commutative case, we might find a better match. */ |
1228 | if (match.commutative[op_no] >= 0) | |
1229 | { | |
1230 | rtx comm = recog_data.operand[match.commutative[op_no]]; | |
1231 | if (operands_match_p (comm, dst) | |
1232 | && (replacement_quality (comm) | |
1233 | >= replacement_quality (src))) | |
1234 | continue; | |
1235 | } | |
1236 | ||
184bb750 R |
1237 | src_class = reg_preferred_class (REGNO (src)); |
1238 | dst_class = reg_preferred_class (REGNO (dst)); | |
3bb806ed | 1239 | if (! regclass_compatible_p (src_class, dst_class)) |
184bb750 | 1240 | continue; |
174fa2c4 | 1241 | |
f3029065 KH |
1242 | if (GET_MODE (src) != GET_MODE (dst)) |
1243 | continue; | |
1244 | ||
184bb750 | 1245 | if (fixup_match_1 (insn, set, src, src_subreg, dst, pass, |
10d22567 | 1246 | op_no, match_no)) |
184bb750 | 1247 | break; |
8c660648 JL |
1248 | } |
1249 | } | |
1250 | } | |
1251 | ||
1252 | /* A backward pass. Replace input operands with output operands. */ | |
1253 | ||
10d22567 ZD |
1254 | if (dump_file) |
1255 | fprintf (dump_file, "Starting backward pass...\n"); | |
8c660648 JL |
1256 | |
1257 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
1258 | { | |
2c3c49de | 1259 | if (INSN_P (insn)) |
8c660648 | 1260 | { |
0eadeb15 | 1261 | int op_no, match_no; |
ddc8bed2 | 1262 | int success = 0; |
0eadeb15 | 1263 | |
3363316f | 1264 | if (! find_matches (insn, &match)) |
8c660648 JL |
1265 | continue; |
1266 | ||
8c660648 JL |
1267 | /* Now scan through the operands looking for a destination operand |
1268 | which is supposed to match a source operand. | |
1269 | Then scan backward for an instruction which sets the source | |
1270 | operand. If safe, then replace the source operand with the | |
1271 | dest operand in both instructions. */ | |
1272 | ||
ddc8bed2 MM |
1273 | copy_src = NULL_RTX; |
1274 | copy_dst = NULL_RTX; | |
1ccbefce | 1275 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
8c660648 | 1276 | { |
184bb750 R |
1277 | rtx set, p, src, dst; |
1278 | rtx src_note, dst_note; | |
184bb750 R |
1279 | int num_calls = 0; |
1280 | enum reg_class src_class, dst_class; | |
1281 | int length; | |
8c660648 | 1282 | |
0eadeb15 | 1283 | match_no = match.with[op_no]; |
8c660648 | 1284 | |
184bb750 | 1285 | /* Nothing to do if the two operands aren't supposed to match. */ |
0eadeb15 | 1286 | if (match_no < 0) |
184bb750 | 1287 | continue; |
8c660648 | 1288 | |
1ccbefce RH |
1289 | dst = recog_data.operand[match_no]; |
1290 | src = recog_data.operand[op_no]; | |
8c660648 | 1291 | |
f8cfc6aa | 1292 | if (!REG_P (src)) |
184bb750 | 1293 | continue; |
8c660648 | 1294 | |
f8cfc6aa | 1295 | if (!REG_P (dst) |
184bb750 | 1296 | || REGNO (dst) < FIRST_PSEUDO_REGISTER |
3721581a | 1297 | || REG_LIVE_LENGTH (REGNO (dst)) < 0 |
41b3243e | 1298 | || GET_MODE (src) != GET_MODE (dst)) |
184bb750 | 1299 | continue; |
8c660648 | 1300 | |
dc297297 | 1301 | /* If the operands already match, then there is nothing to do. */ |
1ccbefce | 1302 | if (operands_match_p (src, dst)) |
184bb750 | 1303 | continue; |
8c660648 | 1304 | |
1ccbefce RH |
1305 | if (match.commutative[op_no] >= 0) |
1306 | { | |
1307 | rtx comm = recog_data.operand[match.commutative[op_no]]; | |
1308 | if (operands_match_p (comm, dst)) | |
1309 | continue; | |
1310 | } | |
1311 | ||
184bb750 R |
1312 | set = single_set (insn); |
1313 | if (! set) | |
1314 | continue; | |
8c660648 | 1315 | |
bb948ad3 RZ |
1316 | /* Note that single_set ignores parts of a parallel set for |
1317 | which one of the destinations is REG_UNUSED. We can't | |
1318 | handle that here, since we can wind up rewriting things | |
1319 | such that a single register is set twice within a single | |
1320 | parallel. */ | |
1321 | if (reg_set_p (src, insn)) | |
1322 | continue; | |
1323 | ||
0eadeb15 | 1324 | /* match_no/dst must be a write-only operand, and |
184bb750 | 1325 | operand_operand/src must be a read-only operand. */ |
0eadeb15 BS |
1326 | if (match.use[op_no] != READ |
1327 | || match.use[match_no] != WRITE) | |
184bb750 | 1328 | continue; |
8c660648 | 1329 | |
0eadeb15 | 1330 | if (match.early_clobber[match_no] |
4b983fdc | 1331 | && count_occurrences (PATTERN (insn), src, 0) > 1) |
184bb750 | 1332 | continue; |
8c660648 | 1333 | |
0eadeb15 | 1334 | /* Make sure match_no is the destination. */ |
1ccbefce | 1335 | if (recog_data.operand[match_no] != SET_DEST (set)) |
184bb750 | 1336 | continue; |
8c660648 | 1337 | |
184bb750 R |
1338 | if (REGNO (src) < FIRST_PSEUDO_REGISTER) |
1339 | { | |
1340 | if (GET_CODE (SET_SRC (set)) == PLUS | |
1341 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT | |
1342 | && XEXP (SET_SRC (set), 0) == src | |
1343 | && fixup_match_2 (insn, dst, src, | |
10d22567 | 1344 | XEXP (SET_SRC (set), 1))) |
184bb750 R |
1345 | break; |
1346 | continue; | |
1347 | } | |
1348 | src_class = reg_preferred_class (REGNO (src)); | |
1349 | dst_class = reg_preferred_class (REGNO (dst)); | |
fd973d56 JH |
1350 | |
1351 | if (! (src_note = find_reg_note (insn, REG_DEAD, src))) | |
ddc8bed2 | 1352 | { |
fd973d56 JH |
1353 | /* We used to force the copy here like in other cases, but |
1354 | it produces worse code, as it eliminates no copy | |
1355 | instructions and the copy emitted will be produced by | |
1356 | reload anyway. On patterns with multiple alternatives, | |
14b493d6 | 1357 | there may be better solution available. |
fd973d56 JH |
1358 | |
1359 | In particular this change produced slower code for numeric | |
1360 | i387 programs. */ | |
1361 | ||
ddc8bed2 MM |
1362 | continue; |
1363 | } | |
8c660648 | 1364 | |
fd973d56 | 1365 | if (! regclass_compatible_p (src_class, dst_class)) |
ddc8bed2 MM |
1366 | { |
1367 | if (!copy_src) | |
1368 | { | |
1369 | copy_src = src; | |
1370 | copy_dst = dst; | |
1371 | } | |
1372 | continue; | |
1373 | } | |
1374 | ||
fd973d56 JH |
1375 | /* Can not modify an earlier insn to set dst if this insn |
1376 | uses an old value in the source. */ | |
1377 | if (reg_overlap_mentioned_p (dst, SET_SRC (set))) | |
ddc8bed2 MM |
1378 | { |
1379 | if (!copy_src) | |
1380 | { | |
1381 | copy_src = src; | |
1382 | copy_dst = dst; | |
1383 | } | |
1384 | continue; | |
1385 | } | |
8c660648 | 1386 | |
184bb750 R |
1387 | /* If src is set once in a different basic block, |
1388 | and is set equal to a constant, then do not use | |
1389 | it for this optimization, as this would make it | |
1390 | no longer equivalent to a constant. */ | |
ddc8bed2 | 1391 | |
65d169d9 | 1392 | if (reg_is_remote_constant_p (src, insn)) |
ddc8bed2 MM |
1393 | { |
1394 | if (!copy_src) | |
1395 | { | |
1396 | copy_src = src; | |
1397 | copy_dst = dst; | |
1398 | } | |
1399 | continue; | |
1400 | } | |
1401 | ||
1402 | ||
10d22567 ZD |
1403 | if (dump_file) |
1404 | fprintf (dump_file, | |
ddc8bed2 | 1405 | "Could fix operand %d of insn %d matching operand %d.\n", |
0eadeb15 | 1406 | op_no, INSN_UID (insn), match_no); |
8c660648 | 1407 | |
184bb750 R |
1408 | /* Scan backward to find the first instruction that uses |
1409 | the input operand. If the operand is set here, then | |
0eadeb15 | 1410 | replace it in both instructions with match_no. */ |
184bb750 R |
1411 | |
1412 | for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) | |
1413 | { | |
1414 | rtx pset; | |
1415 | ||
7bf825d2 JW |
1416 | /* ??? We can't scan past the end of a basic block without |
1417 | updating the register lifetime info | |
a1c1fdd0 RK |
1418 | (REG_DEAD/basic_block_live_at_start). */ |
1419 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 1420 | break; |
a1c1fdd0 | 1421 | else if (! INSN_P (p)) |
184bb750 | 1422 | continue; |
8c660648 | 1423 | |
184bb750 | 1424 | length++; |
8c660648 | 1425 | |
184bb750 R |
1426 | /* ??? See if all of SRC is set in P. This test is much |
1427 | more conservative than it needs to be. */ | |
1428 | pset = single_set (p); | |
1429 | if (pset && SET_DEST (pset) == src) | |
1430 | { | |
1431 | /* We use validate_replace_rtx, in case there | |
1432 | are multiple identical source operands. All of | |
1433 | them have to be changed at the same time. */ | |
1434 | if (validate_replace_rtx (src, dst, insn)) | |
8c660648 | 1435 | { |
184bb750 R |
1436 | if (validate_change (p, &SET_DEST (pset), |
1437 | dst, 0)) | |
1438 | success = 1; | |
1439 | else | |
8c660648 | 1440 | { |
184bb750 R |
1441 | /* Change all source operands back. |
1442 | This modifies the dst as a side-effect. */ | |
1443 | validate_replace_rtx (dst, src, insn); | |
1444 | /* Now make sure the dst is right. */ | |
1445 | validate_change (insn, | |
1ccbefce | 1446 | recog_data.operand_loc[match_no], |
184bb750 | 1447 | dst, 0); |
8c660648 | 1448 | } |
8c660648 | 1449 | } |
184bb750 R |
1450 | break; |
1451 | } | |
1452 | ||
1e4c6dc5 SP |
1453 | /* We can't make this change if SRC is read or |
1454 | partially written in P, since we are going to | |
1455 | eliminate SRC. We can't make this change | |
1456 | if DST is mentioned at all in P, | |
1457 | since we are going to change its value. */ | |
184bb750 | 1458 | if (reg_overlap_mentioned_p (src, PATTERN (p)) |
1e4c6dc5 | 1459 | || reg_mentioned_p (dst, PATTERN (p))) |
184bb750 | 1460 | break; |
8c660648 | 1461 | |
184bb750 R |
1462 | /* If we have passed a call instruction, and the |
1463 | pseudo-reg DST is not already live across a call, | |
1464 | then don't perform the optimization. */ | |
4b4bf941 | 1465 | if (CALL_P (p)) |
184bb750 R |
1466 | { |
1467 | num_calls++; | |
1468 | ||
1469 | if (REG_N_CALLS_CROSSED (REGNO (dst)) == 0) | |
8c660648 | 1470 | break; |
184bb750 R |
1471 | } |
1472 | } | |
8c660648 | 1473 | |
184bb750 R |
1474 | if (success) |
1475 | { | |
1476 | int dstno, srcno; | |
8c660648 | 1477 | |
184bb750 R |
1478 | /* Remove the death note for SRC from INSN. */ |
1479 | remove_note (insn, src_note); | |
1480 | /* Move the death note for SRC to P if it is used | |
1481 | there. */ | |
1482 | if (reg_overlap_mentioned_p (src, PATTERN (p))) | |
1483 | { | |
1484 | XEXP (src_note, 1) = REG_NOTES (p); | |
1485 | REG_NOTES (p) = src_note; | |
8c660648 | 1486 | } |
184bb750 R |
1487 | /* If there is a REG_DEAD note for DST on P, then remove |
1488 | it, because DST is now set there. */ | |
5e9defae | 1489 | if ((dst_note = find_reg_note (p, REG_DEAD, dst))) |
184bb750 R |
1490 | remove_note (p, dst_note); |
1491 | ||
1492 | dstno = REGNO (dst); | |
1493 | srcno = REGNO (src); | |
1494 | ||
6fb5fa3c DB |
1495 | INC_REG_N_SETS (dstno, 1); |
1496 | INC_REG_N_SETS (srcno, -1); | |
8c660648 | 1497 | |
184bb750 R |
1498 | REG_N_CALLS_CROSSED (dstno) += num_calls; |
1499 | REG_N_CALLS_CROSSED (srcno) -= num_calls; | |
1500 | ||
1501 | REG_LIVE_LENGTH (dstno) += length; | |
1502 | if (REG_LIVE_LENGTH (srcno) >= 0) | |
8c660648 | 1503 | { |
184bb750 R |
1504 | REG_LIVE_LENGTH (srcno) -= length; |
1505 | /* REG_LIVE_LENGTH is only an approximation after | |
1506 | combine if sched is not run, so make sure that we | |
1507 | still have a reasonable value. */ | |
1508 | if (REG_LIVE_LENGTH (srcno) < 2) | |
1509 | REG_LIVE_LENGTH (srcno) = 2; | |
1510 | } | |
8c660648 | 1511 | |
10d22567 ZD |
1512 | if (dump_file) |
1513 | fprintf (dump_file, | |
184bb750 | 1514 | "Fixed operand %d of insn %d matching operand %d.\n", |
0eadeb15 | 1515 | op_no, INSN_UID (insn), match_no); |
8c660648 | 1516 | |
184bb750 | 1517 | break; |
8c660648 JL |
1518 | } |
1519 | } | |
ddc8bed2 MM |
1520 | |
1521 | /* If we weren't able to replace any of the alternatives, try an | |
14b493d6 | 1522 | alternative approach of copying the source to the destination. */ |
ddc8bed2 | 1523 | if (!success && copy_src != NULL_RTX) |
a78f3e71 | 1524 | copy_src_to_dest (insn, copy_src, copy_dst); |
8c660648 JL |
1525 | } |
1526 | } | |
961d4119 | 1527 | |
4da896b2 MM |
1528 | done: |
1529 | /* Clean up. */ | |
1530 | free (regno_src_regno); | |
65d169d9 JH |
1531 | if (reg_set_in_bb) |
1532 | { | |
1533 | free (reg_set_in_bb); | |
1534 | reg_set_in_bb = NULL; | |
1535 | } | |
6fb5fa3c DB |
1536 | regstat_free_n_sets_and_refs (); |
1537 | regstat_free_ri (); | |
8c660648 JL |
1538 | } |
1539 | ||
0eadeb15 BS |
1540 | /* Returns nonzero if INSN's pattern has matching constraints for any operand. |
1541 | Returns 0 if INSN can't be recognized, or if the alternative can't be | |
1542 | determined. | |
b1a7d591 JW |
1543 | |
1544 | Initialize the info in MATCHP based on the constraints. */ | |
184bb750 R |
1545 | |
1546 | static int | |
0c20a65f | 1547 | find_matches (rtx insn, struct match *matchp) |
184bb750 R |
1548 | { |
1549 | int likely_spilled[MAX_RECOG_OPERANDS]; | |
0eadeb15 | 1550 | int op_no; |
184bb750 R |
1551 | int any_matches = 0; |
1552 | ||
0eadeb15 BS |
1553 | extract_insn (insn); |
1554 | if (! constrain_operands (0)) | |
1555 | return 0; | |
184bb750 R |
1556 | |
1557 | /* Must initialize this before main loop, because the code for | |
1558 | the commutative case may set matches for operands other than | |
1559 | the current one. */ | |
1ccbefce | 1560 | for (op_no = recog_data.n_operands; --op_no >= 0; ) |
0eadeb15 | 1561 | matchp->with[op_no] = matchp->commutative[op_no] = -1; |
184bb750 | 1562 | |
1ccbefce | 1563 | for (op_no = 0; op_no < recog_data.n_operands; op_no++) |
184bb750 | 1564 | { |
9b3142b3 KG |
1565 | const char *p; |
1566 | char c; | |
184bb750 R |
1567 | int i = 0; |
1568 | ||
1ccbefce | 1569 | p = recog_data.constraints[op_no]; |
184bb750 | 1570 | |
0eadeb15 BS |
1571 | likely_spilled[op_no] = 0; |
1572 | matchp->use[op_no] = READ; | |
1573 | matchp->early_clobber[op_no] = 0; | |
184bb750 | 1574 | if (*p == '=') |
0eadeb15 | 1575 | matchp->use[op_no] = WRITE; |
184bb750 | 1576 | else if (*p == '+') |
0eadeb15 | 1577 | matchp->use[op_no] = READWRITE; |
184bb750 R |
1578 | |
1579 | for (;*p && i < which_alternative; p++) | |
1580 | if (*p == ',') | |
1581 | i++; | |
1582 | ||
97488870 R |
1583 | while ((c = *p) != '\0' && c != ',') |
1584 | { | |
1585 | switch (c) | |
84b72302 | 1586 | { |
97488870 R |
1587 | case '=': |
1588 | break; | |
1589 | case '+': | |
1590 | break; | |
1591 | case '&': | |
1592 | matchp->early_clobber[op_no] = 1; | |
1593 | break; | |
1594 | case '%': | |
1595 | matchp->commutative[op_no] = op_no + 1; | |
1596 | matchp->commutative[op_no + 1] = op_no; | |
1597 | break; | |
1598 | ||
1599 | case '0': case '1': case '2': case '3': case '4': | |
1600 | case '5': case '6': case '7': case '8': case '9': | |
1601 | { | |
1602 | char *end; | |
1603 | unsigned long match_ul = strtoul (p, &end, 10); | |
1604 | int match = match_ul; | |
2cc2d4bb | 1605 | |
97488870 | 1606 | p = end; |
84b72302 | 1607 | |
97488870 R |
1608 | if (match < op_no && likely_spilled[match]) |
1609 | continue; | |
1610 | matchp->with[op_no] = match; | |
1611 | any_matches = 1; | |
1612 | if (matchp->commutative[op_no] >= 0) | |
1613 | matchp->with[matchp->commutative[op_no]] = match; | |
1614 | } | |
1615 | continue; | |
84b72302 | 1616 | |
184bb750 R |
1617 | case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'h': |
1618 | case 'j': case 'k': case 'l': case 'p': case 'q': case 't': case 'u': | |
1619 | case 'v': case 'w': case 'x': case 'y': case 'z': case 'A': case 'B': | |
1620 | case 'C': case 'D': case 'W': case 'Y': case 'Z': | |
97488870 | 1621 | if (CLASS_LIKELY_SPILLED_P (REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p) )) |
0eadeb15 | 1622 | likely_spilled[op_no] = 1; |
184bb750 R |
1623 | break; |
1624 | } | |
97488870 R |
1625 | p += CONSTRAINT_LEN (c, p); |
1626 | } | |
184bb750 | 1627 | } |
0eadeb15 | 1628 | return any_matches; |
184bb750 R |
1629 | } |
1630 | ||
ec7c0481 AO |
1631 | /* Try to replace all occurrences of DST_REG with SRC in LOC, that is |
1632 | assumed to be in INSN. */ | |
1633 | ||
1634 | static void | |
0c20a65f | 1635 | replace_in_call_usage (rtx *loc, unsigned int dst_reg, rtx src, rtx insn) |
ec7c0481 AO |
1636 | { |
1637 | rtx x = *loc; | |
1638 | enum rtx_code code; | |
1639 | const char *fmt; | |
1640 | int i, j; | |
1641 | ||
1642 | if (! x) | |
1643 | return; | |
174fa2c4 | 1644 | |
ec7c0481 AO |
1645 | code = GET_CODE (x); |
1646 | if (code == REG) | |
1647 | { | |
1648 | if (REGNO (x) != dst_reg) | |
1649 | return; | |
174fa2c4 | 1650 | |
ec7c0481 AO |
1651 | validate_change (insn, loc, src, 1); |
1652 | ||
1653 | return; | |
1654 | } | |
174fa2c4 | 1655 | |
ec7c0481 AO |
1656 | /* Process each of our operands recursively. */ |
1657 | fmt = GET_RTX_FORMAT (code); | |
1658 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
1659 | if (*fmt == 'e') | |
1660 | replace_in_call_usage (&XEXP (x, i), dst_reg, src, insn); | |
1661 | else if (*fmt == 'E') | |
1662 | for (j = 0; j < XVECLEN (x, i); j++) | |
1663 | replace_in_call_usage (& XVECEXP (x, i, j), dst_reg, src, insn); | |
1664 | } | |
1665 | ||
184bb750 | 1666 | /* Try to replace output operand DST in SET, with input operand SRC. SET is |
06671717 | 1667 | the only set in INSN. INSN has just been recognized and constrained. |
184bb750 R |
1668 | SRC is operand number OPERAND_NUMBER in INSN. |
1669 | DST is operand number MATCH_NUMBER in INSN. | |
1670 | If BACKWARD is nonzero, we have been called in a backward pass. | |
1671 | Return nonzero for success. */ | |
a1c1fdd0 | 1672 | |
184bb750 | 1673 | static int |
0c20a65f | 1674 | fixup_match_1 (rtx insn, rtx set, rtx src, rtx src_subreg, rtx dst, |
10d22567 | 1675 | int backward, int operand_number, int match_number) |
184bb750 R |
1676 | { |
1677 | rtx p; | |
1678 | rtx post_inc = 0, post_inc_set = 0, search_end = 0; | |
1679 | int success = 0; | |
1680 | int num_calls = 0, s_num_calls = 0; | |
1681 | enum rtx_code code = NOTE; | |
0334ef47 | 1682 | HOST_WIDE_INT insn_const = 0, newconst = 0; |
184bb750 | 1683 | rtx overlap = 0; /* need to move insn ? */ |
a544cfd2 | 1684 | rtx src_note = find_reg_note (insn, REG_DEAD, src), dst_note = NULL_RTX; |
1b7c4a37 | 1685 | int length, s_length; |
184bb750 R |
1686 | |
1687 | if (! src_note) | |
1688 | { | |
1689 | /* Look for (set (regX) (op regA constX)) | |
1690 | (set (regY) (op regA constY)) | |
1691 | and change that to | |
1692 | (set (regA) (op regA constX)). | |
1693 | (set (regY) (op regA constY-constX)). | |
1694 | This works for add and shift operations, if | |
1695 | regA is dead after or set by the second insn. */ | |
1696 | ||
1697 | code = GET_CODE (SET_SRC (set)); | |
1698 | if ((code == PLUS || code == LSHIFTRT | |
1699 | || code == ASHIFT || code == ASHIFTRT) | |
1700 | && XEXP (SET_SRC (set), 0) == src | |
1701 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) | |
1702 | insn_const = INTVAL (XEXP (SET_SRC (set), 1)); | |
18bf656f | 1703 | else if (! stable_and_no_regs_but_for_p (SET_SRC (set), src, dst)) |
184bb750 R |
1704 | return 0; |
1705 | else | |
1706 | /* We might find a src_note while scanning. */ | |
1707 | code = NOTE; | |
1708 | } | |
1709 | ||
10d22567 ZD |
1710 | if (dump_file) |
1711 | fprintf (dump_file, | |
184bb750 R |
1712 | "Could fix operand %d of insn %d matching operand %d.\n", |
1713 | operand_number, INSN_UID (insn), match_number); | |
1714 | ||
1715 | /* If SRC is equivalent to a constant set in a different basic block, | |
1716 | then do not use it for this optimization. We want the equivalence | |
1717 | so that if we have to reload this register, we can reload the | |
1718 | constant, rather than extending the lifespan of the register. */ | |
65d169d9 | 1719 | if (reg_is_remote_constant_p (src, insn)) |
184bb750 R |
1720 | return 0; |
1721 | ||
1722 | /* Scan forward to find the next instruction that | |
1723 | uses the output operand. If the operand dies here, | |
1724 | then replace it in both instructions with | |
1725 | operand_number. */ | |
1726 | ||
1727 | for (length = s_length = 0, p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
1728 | { | |
4b4bf941 | 1729 | if (CALL_P (p)) |
ec7c0481 AO |
1730 | replace_in_call_usage (& CALL_INSN_FUNCTION_USAGE (p), |
1731 | REGNO (dst), src, p); | |
174fa2c4 | 1732 | |
7bf825d2 | 1733 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 RK |
1734 | the register lifetime info (REG_DEAD/basic_block_live_at_start). */ |
1735 | if (perhaps_ends_bb_p (p)) | |
7bf825d2 | 1736 | break; |
a1c1fdd0 | 1737 | else if (! INSN_P (p)) |
184bb750 R |
1738 | continue; |
1739 | ||
1740 | length++; | |
1741 | if (src_note) | |
1742 | s_length++; | |
1743 | ||
1744 | if (reg_set_p (src, p) || reg_set_p (dst, p) | |
1745 | || (GET_CODE (PATTERN (p)) == USE | |
1746 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
1747 | break; | |
1748 | ||
1749 | /* See if all of DST dies in P. This test is | |
1750 | slightly more conservative than it needs to be. */ | |
1751 | if ((dst_note = find_regno_note (p, REG_DEAD, REGNO (dst))) | |
1752 | && (GET_MODE (XEXP (dst_note, 0)) == GET_MODE (dst))) | |
1753 | { | |
2219e921 R |
1754 | /* If we would be moving INSN, check that we won't move it |
1755 | into the shadow of a live a live flags register. */ | |
1756 | /* ??? We only try to move it in front of P, although | |
1757 | we could move it anywhere between OVERLAP and P. */ | |
1758 | if (overlap && GET_MODE (PREV_INSN (p)) != VOIDmode) | |
1759 | break; | |
1760 | ||
184bb750 R |
1761 | if (! src_note) |
1762 | { | |
1763 | rtx q; | |
a544cfd2 | 1764 | rtx set2 = NULL_RTX; |
184bb750 R |
1765 | |
1766 | /* If an optimization is done, the value of SRC while P | |
1767 | is executed will be changed. Check that this is OK. */ | |
1768 | if (reg_overlap_mentioned_p (src, PATTERN (p))) | |
1769 | break; | |
1770 | for (q = p; q; q = NEXT_INSN (q)) | |
1771 | { | |
7bf825d2 JW |
1772 | /* ??? We can't scan past the end of a basic block without |
1773 | updating the register lifetime info | |
a1c1fdd0 RK |
1774 | (REG_DEAD/basic_block_live_at_start). */ |
1775 | if (perhaps_ends_bb_p (q)) | |
7bf825d2 JW |
1776 | { |
1777 | q = 0; | |
1778 | break; | |
1779 | } | |
a1c1fdd0 | 1780 | else if (! INSN_P (q)) |
184bb750 | 1781 | continue; |
a1c1fdd0 RK |
1782 | else if (reg_overlap_mentioned_p (src, PATTERN (q)) |
1783 | || reg_set_p (src, q)) | |
184bb750 R |
1784 | break; |
1785 | } | |
1786 | if (q) | |
1787 | set2 = single_set (q); | |
1788 | if (! q || ! set2 || GET_CODE (SET_SRC (set2)) != code | |
1789 | || XEXP (SET_SRC (set2), 0) != src | |
1790 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT | |
1791 | || (SET_DEST (set2) != src | |
1792 | && ! find_reg_note (q, REG_DEAD, src))) | |
1793 | { | |
1794 | /* If this is a PLUS, we can still save a register by doing | |
1795 | src += insn_const; | |
1796 | P; | |
1797 | src -= insn_const; . | |
1798 | This also gives opportunities for subsequent | |
1799 | optimizations in the backward pass, so do it there. */ | |
1800 | if (code == PLUS && backward | |
3bb806ed R |
1801 | /* Don't do this if we can likely tie DST to SET_DEST |
1802 | of P later; we can't do this tying here if we got a | |
1803 | hard register. */ | |
1804 | && ! (dst_note && ! REG_N_CALLS_CROSSED (REGNO (dst)) | |
1805 | && single_set (p) | |
f8cfc6aa | 1806 | && REG_P (SET_DEST (single_set (p))) |
3bb806ed R |
1807 | && (REGNO (SET_DEST (single_set (p))) |
1808 | < FIRST_PSEUDO_REGISTER)) | |
dc2cb191 RH |
1809 | /* We may only emit an insn directly after P if we |
1810 | are not in the shadow of a live flags register. */ | |
1811 | && GET_MODE (p) == VOIDmode) | |
184bb750 R |
1812 | { |
1813 | search_end = q; | |
1814 | q = insn; | |
1815 | set2 = set; | |
1816 | newconst = -insn_const; | |
1817 | code = MINUS; | |
1818 | } | |
1819 | else | |
1820 | break; | |
1821 | } | |
1822 | else | |
1823 | { | |
1824 | newconst = INTVAL (XEXP (SET_SRC (set2), 1)) - insn_const; | |
1825 | /* Reject out of range shifts. */ | |
1826 | if (code != PLUS | |
1827 | && (newconst < 0 | |
a1c1fdd0 RK |
1828 | || ((unsigned HOST_WIDE_INT) newconst |
1829 | >= (GET_MODE_BITSIZE (GET_MODE | |
1830 | (SET_SRC (set2))))))) | |
184bb750 R |
1831 | break; |
1832 | if (code == PLUS) | |
1833 | { | |
1834 | post_inc = q; | |
1835 | if (SET_DEST (set2) != src) | |
1836 | post_inc_set = set2; | |
1837 | } | |
1838 | } | |
1839 | /* We use 1 as last argument to validate_change so that all | |
1840 | changes are accepted or rejected together by apply_change_group | |
1841 | when it is called by validate_replace_rtx . */ | |
1842 | validate_change (q, &XEXP (SET_SRC (set2), 1), | |
1843 | GEN_INT (newconst), 1); | |
1844 | } | |
1ccbefce | 1845 | validate_change (insn, recog_data.operand_loc[match_number], src, 1); |
184bb750 R |
1846 | if (validate_replace_rtx (dst, src_subreg, p)) |
1847 | success = 1; | |
1848 | break; | |
1849 | } | |
1850 | ||
1851 | if (reg_overlap_mentioned_p (dst, PATTERN (p))) | |
1852 | break; | |
1853 | if (! src_note && reg_overlap_mentioned_p (src, PATTERN (p))) | |
1854 | { | |
2219e921 R |
1855 | /* INSN was already checked to be movable wrt. the registers that it |
1856 | sets / uses when we found no REG_DEAD note for src on it, but it | |
1857 | still might clobber the flags register. We'll have to check that | |
1858 | we won't insert it into the shadow of a live flags register when | |
1859 | we finally know where we are to move it. */ | |
184bb750 R |
1860 | overlap = p; |
1861 | src_note = find_reg_note (p, REG_DEAD, src); | |
1862 | } | |
1863 | ||
1864 | /* If we have passed a call instruction, and the pseudo-reg SRC is not | |
1865 | already live across a call, then don't perform the optimization. */ | |
4b4bf941 | 1866 | if (CALL_P (p)) |
184bb750 R |
1867 | { |
1868 | if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) | |
1869 | break; | |
1870 | ||
1871 | num_calls++; | |
1872 | ||
1873 | if (src_note) | |
1874 | s_num_calls++; | |
1875 | ||
1876 | } | |
1877 | } | |
1878 | ||
1879 | if (! success) | |
1880 | return 0; | |
1881 | ||
184bb750 R |
1882 | /* Remove the death note for DST from P. */ |
1883 | remove_note (p, dst_note); | |
1884 | if (code == MINUS) | |
1885 | { | |
1886 | post_inc = emit_insn_after (copy_rtx (PATTERN (insn)), p); | |
940da324 JL |
1887 | if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) |
1888 | && search_end | |
184bb750 R |
1889 | && try_auto_increment (search_end, post_inc, 0, src, newconst, 1)) |
1890 | post_inc = 0; | |
184bb750 | 1891 | validate_change (insn, &XEXP (SET_SRC (set), 1), GEN_INT (insn_const), 0); |
6fb5fa3c | 1892 | INC_REG_N_SETS (REGNO (src), 1); |
184bb750 R |
1893 | REG_LIVE_LENGTH (REGNO (src))++; |
1894 | } | |
1895 | if (overlap) | |
1896 | { | |
1897 | /* The lifetime of src and dest overlap, | |
1898 | but we can change this by moving insn. */ | |
1899 | rtx pat = PATTERN (insn); | |
1900 | if (src_note) | |
1901 | remove_note (overlap, src_note); | |
1ed9faee TM |
1902 | if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT) |
1903 | && code == PLUS | |
184bb750 R |
1904 | && try_auto_increment (overlap, insn, 0, src, insn_const, 0)) |
1905 | insn = overlap; | |
1906 | else | |
184bb750 R |
1907 | { |
1908 | rtx notes = REG_NOTES (insn); | |
1909 | ||
6039a0c7 | 1910 | p = emit_insn_after_setloc (pat, PREV_INSN (p), INSN_LOCATOR (insn)); |
ca6c03ca | 1911 | delete_insn (insn); |
6039a0c7 | 1912 | REG_NOTES (p) = notes; |
6fb5fa3c | 1913 | df_notes_rescan (p); |
184bb750 R |
1914 | } |
1915 | } | |
1916 | /* Sometimes we'd generate src = const; src += n; | |
1917 | if so, replace the instruction that set src | |
1918 | in the first place. */ | |
1919 | ||
1920 | if (! overlap && (code == PLUS || code == MINUS)) | |
1921 | { | |
1922 | rtx note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
a544cfd2 | 1923 | rtx q, set2 = NULL_RTX; |
184bb750 R |
1924 | int num_calls2 = 0, s_length2 = 0; |
1925 | ||
1926 | if (note && CONSTANT_P (XEXP (note, 0))) | |
1927 | { | |
8e2e89f7 | 1928 | for (q = PREV_INSN (insn); q; q = PREV_INSN (q)) |
184bb750 | 1929 | { |
7bf825d2 JW |
1930 | /* ??? We can't scan past the end of a basic block without |
1931 | updating the register lifetime info | |
a1c1fdd0 RK |
1932 | (REG_DEAD/basic_block_live_at_start). */ |
1933 | if (perhaps_ends_bb_p (q)) | |
7bf825d2 JW |
1934 | { |
1935 | q = 0; | |
1936 | break; | |
1937 | } | |
a1c1fdd0 | 1938 | else if (! INSN_P (q)) |
184bb750 | 1939 | continue; |
a1c1fdd0 | 1940 | |
184bb750 R |
1941 | s_length2++; |
1942 | if (reg_set_p (src, q)) | |
1943 | { | |
1944 | set2 = single_set (q); | |
1945 | break; | |
1946 | } | |
1947 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
1948 | { | |
1949 | q = 0; | |
1950 | break; | |
1951 | } | |
4b4bf941 | 1952 | if (CALL_P (p)) |
184bb750 R |
1953 | num_calls2++; |
1954 | } | |
1955 | if (q && set2 && SET_DEST (set2) == src && CONSTANT_P (SET_SRC (set2)) | |
1956 | && validate_change (insn, &SET_SRC (set), XEXP (note, 0), 0)) | |
1957 | { | |
ca6c03ca | 1958 | delete_insn (q); |
6fb5fa3c | 1959 | INC_REG_N_SETS (REGNO (src), -1); |
184bb750 | 1960 | REG_N_CALLS_CROSSED (REGNO (src)) -= num_calls2; |
184bb750 R |
1961 | REG_LIVE_LENGTH (REGNO (src)) -= s_length2; |
1962 | insn_const = 0; | |
1963 | } | |
1964 | } | |
1965 | } | |
1a56b81f | 1966 | |
cb084004 | 1967 | if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) |
940da324 | 1968 | && (code == PLUS || code == MINUS) && insn_const |
184bb750 R |
1969 | && try_auto_increment (p, insn, 0, src, insn_const, 1)) |
1970 | insn = p; | |
940da324 JL |
1971 | else if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT) |
1972 | && post_inc | |
184bb750 R |
1973 | && try_auto_increment (p, post_inc, post_inc_set, src, newconst, 0)) |
1974 | post_inc = 0; | |
184bb750 R |
1975 | /* If post_inc still prevails, try to find an |
1976 | insn where it can be used as a pre-in/decrement. | |
1977 | If code is MINUS, this was already tried. */ | |
1978 | if (post_inc && code == PLUS | |
1979 | /* Check that newconst is likely to be usable | |
1980 | in a pre-in/decrement before starting the search. */ | |
940da324 JL |
1981 | && ((HAVE_PRE_INCREMENT && newconst > 0 && newconst <= MOVE_MAX) |
1982 | || (HAVE_PRE_DECREMENT && newconst < 0 && newconst >= -MOVE_MAX)) | |
1983 | && exact_log2 (newconst)) | |
184bb750 R |
1984 | { |
1985 | rtx q, inc_dest; | |
1986 | ||
1987 | inc_dest = post_inc_set ? SET_DEST (post_inc_set) : src; | |
51723711 | 1988 | for (q = post_inc; (q = NEXT_INSN (q)); ) |
184bb750 | 1989 | { |
7bf825d2 | 1990 | /* ??? We can't scan past the end of a basic block without updating |
a1c1fdd0 | 1991 | the register lifetime info |
dc297297 | 1992 | (REG_DEAD/basic_block_live_at_start). */ |
a1c1fdd0 | 1993 | if (perhaps_ends_bb_p (q)) |
7bf825d2 | 1994 | break; |
a1c1fdd0 | 1995 | else if (! INSN_P (q)) |
184bb750 | 1996 | continue; |
a1c1fdd0 RK |
1997 | else if (src != inc_dest |
1998 | && (reg_overlap_mentioned_p (src, PATTERN (q)) | |
1999 | || reg_set_p (src, q))) | |
184bb750 | 2000 | break; |
a1c1fdd0 | 2001 | else if (reg_set_p (inc_dest, q)) |
184bb750 | 2002 | break; |
a1c1fdd0 | 2003 | else if (reg_overlap_mentioned_p (inc_dest, PATTERN (q))) |
184bb750 R |
2004 | { |
2005 | try_auto_increment (q, post_inc, | |
2006 | post_inc_set, inc_dest, newconst, 1); | |
2007 | break; | |
2008 | } | |
2009 | } | |
2010 | } | |
a1c1fdd0 | 2011 | |
184bb750 R |
2012 | /* Move the death note for DST to INSN if it is used |
2013 | there. */ | |
2014 | if (reg_overlap_mentioned_p (dst, PATTERN (insn))) | |
2015 | { | |
2016 | XEXP (dst_note, 1) = REG_NOTES (insn); | |
2017 | REG_NOTES (insn) = dst_note; | |
2018 | } | |
2019 | ||
2020 | if (src_note) | |
2021 | { | |
2022 | /* Move the death note for SRC from INSN to P. */ | |
2023 | if (! overlap) | |
2024 | remove_note (insn, src_note); | |
2025 | XEXP (src_note, 1) = REG_NOTES (p); | |
2026 | REG_NOTES (p) = src_note; | |
2027 | ||
2028 | REG_N_CALLS_CROSSED (REGNO (src)) += s_num_calls; | |
2029 | } | |
2030 | ||
6fb5fa3c DB |
2031 | INC_REG_N_SETS (REGNO (src), 1); |
2032 | INC_REG_N_SETS (REGNO (dst), -1); | |
184bb750 R |
2033 | |
2034 | REG_N_CALLS_CROSSED (REGNO (dst)) -= num_calls; | |
2035 | ||
2036 | REG_LIVE_LENGTH (REGNO (src)) += s_length; | |
2037 | if (REG_LIVE_LENGTH (REGNO (dst)) >= 0) | |
2038 | { | |
2039 | REG_LIVE_LENGTH (REGNO (dst)) -= length; | |
2040 | /* REG_LIVE_LENGTH is only an approximation after | |
2041 | combine if sched is not run, so make sure that we | |
2042 | still have a reasonable value. */ | |
2043 | if (REG_LIVE_LENGTH (REGNO (dst)) < 2) | |
2044 | REG_LIVE_LENGTH (REGNO (dst)) = 2; | |
2045 | } | |
10d22567 ZD |
2046 | if (dump_file) |
2047 | fprintf (dump_file, | |
184bb750 R |
2048 | "Fixed operand %d of insn %d matching operand %d.\n", |
2049 | operand_number, INSN_UID (insn), match_number); | |
2050 | return 1; | |
2051 | } | |
2052 | ||
2053 | ||
beb235f8 | 2054 | /* Return nonzero if X is stable and mentions no registers but for |
18bf656f R |
2055 | mentioning SRC or mentioning / changing DST . If in doubt, presume |
2056 | it is unstable. | |
2057 | The rationale is that we want to check if we can move an insn easily | |
389fdba0 | 2058 | while just paying attention to SRC and DST. */ |
8c660648 | 2059 | static int |
0c20a65f | 2060 | stable_and_no_regs_but_for_p (rtx x, rtx src, rtx dst) |
8c660648 JL |
2061 | { |
2062 | RTX_CODE code = GET_CODE (x); | |
2063 | switch (GET_RTX_CLASS (code)) | |
2064 | { | |
ec8e098d PB |
2065 | case RTX_UNARY: |
2066 | case RTX_BIN_ARITH: | |
2067 | case RTX_COMM_ARITH: | |
2068 | case RTX_COMPARE: | |
2069 | case RTX_COMM_COMPARE: | |
2070 | case RTX_TERNARY: | |
2071 | case RTX_BITFIELD_OPS: | |
8c660648 JL |
2072 | { |
2073 | int i; | |
6f7d635c | 2074 | const char *fmt = GET_RTX_FORMAT (code); |
8c660648 | 2075 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
18bf656f R |
2076 | if (fmt[i] == 'e' |
2077 | && ! stable_and_no_regs_but_for_p (XEXP (x, i), src, dst)) | |
8c660648 JL |
2078 | return 0; |
2079 | return 1; | |
2080 | } | |
ec8e098d | 2081 | case RTX_OBJ: |
18bf656f R |
2082 | if (code == REG) |
2083 | return x == src || x == dst; | |
2084 | /* If this is a MEM, look inside - there might be a register hidden in | |
2085 | the address of an unchanging MEM. */ | |
2086 | if (code == MEM | |
2087 | && ! stable_and_no_regs_but_for_p (XEXP (x, 0), src, dst)) | |
2088 | return 0; | |
938d968e | 2089 | /* Fall through. */ |
8c660648 JL |
2090 | default: |
2091 | return ! rtx_unstable_p (x); | |
2092 | } | |
2093 | } | |
1e7f0a48 | 2094 | \f |
1e7f0a48 | 2095 | |
ef330312 PB |
2096 | static bool |
2097 | gate_handle_regmove (void) | |
2098 | { | |
2099 | return (optimize > 0 && flag_regmove); | |
2100 | } | |
2101 | ||
ef330312 PB |
2102 | /* Register allocation pre-pass, to reduce number of moves necessary |
2103 | for two-address machines. */ | |
c2924966 | 2104 | static unsigned int |
ef330312 PB |
2105 | rest_of_handle_regmove (void) |
2106 | { | |
10d22567 | 2107 | regmove_optimize (get_insns (), max_reg_num ()); |
c2924966 | 2108 | return 0; |
ef330312 PB |
2109 | } |
2110 | ||
2111 | struct tree_opt_pass pass_regmove = | |
2112 | { | |
2113 | "regmove", /* name */ | |
2114 | gate_handle_regmove, /* gate */ | |
2115 | rest_of_handle_regmove, /* execute */ | |
2116 | NULL, /* sub */ | |
2117 | NULL, /* next */ | |
2118 | 0, /* static_pass_number */ | |
2119 | TV_REGMOVE, /* tv_id */ | |
2120 | 0, /* properties_required */ | |
2121 | 0, /* properties_provided */ | |
2122 | 0, /* properties_destroyed */ | |
2123 | 0, /* todo_flags_start */ | |
6fb5fa3c | 2124 | TODO_df_finish | |
ef330312 PB |
2125 | TODO_dump_func | |
2126 | TODO_ggc_collect, /* todo_flags_finish */ | |
2127 | 'N' /* letter */ | |
2128 | }; | |
2129 |