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b9a06185 | 1 | /* Register renaming for the GNU compiler. |
3aea1f79 | 2 | Copyright (C) 2000-2014 Free Software Foundation, Inc. |
b9a06185 | 3 | |
f12b58b3 | 4 | This file is part of GCC. |
b9a06185 | 5 | |
f12b58b3 | 6 | GCC is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by | |
8c4c00c1 | 8 | the Free Software Foundation; either version 3, or (at your option) |
b9a06185 | 9 | any later version. |
10 | ||
f12b58b3 | 11 | GCC is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
b9a06185 | 15 | |
16 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
b9a06185 | 19 | |
20 | #include "config.h" | |
21 | #include "system.h" | |
805e22b2 | 22 | #include "coretypes.h" |
23 | #include "tm.h" | |
d7091a76 | 24 | #include "rtl-error.h" |
1140e77e | 25 | #include "tm_p.h" |
b9a06185 | 26 | #include "insn-config.h" |
27 | #include "regs.h" | |
00cb30dc | 28 | #include "addresses.h" |
1140e77e | 29 | #include "hard-reg-set.h" |
94ea8568 | 30 | #include "predict.h" |
31 | #include "vec.h" | |
a3020f2f | 32 | #include "hashtab.h" |
33 | #include "hash-set.h" | |
a3020f2f | 34 | #include "machmode.h" |
35 | #include "input.h" | |
b9a06185 | 36 | #include "function.h" |
94ea8568 | 37 | #include "dominance.h" |
38 | #include "cfg.h" | |
39 | #include "cfganal.h" | |
40 | #include "basic-block.h" | |
41 | #include "reload.h" | |
42 | #include "output.h" | |
b9a06185 | 43 | #include "recog.h" |
1140e77e | 44 | #include "flags.h" |
45 | #include "obstack.h" | |
77fce4cd | 46 | #include "tree-pass.h" |
3072d30e | 47 | #include "df.h" |
d78118a3 | 48 | #include "target.h" |
7de639a2 | 49 | #include "emit-rtl.h" |
50 | #include "regrename.h" | |
1140e77e | 51 | |
9f3e3774 | 52 | /* This file implements the RTL register renaming pass of the compiler. It is |
53 | a semi-local pass whose goal is to maximize the usage of the register file | |
54 | of the processor by substituting registers for others in the solution given | |
55 | by the register allocator. The algorithm is as follows: | |
56 | ||
57 | 1. Local def/use chains are built: within each basic block, chains are | |
58 | opened and closed; if a chain isn't closed at the end of the block, | |
31adcf56 | 59 | it is dropped. We pre-open chains if we have already examined a |
60 | predecessor block and found chains live at the end which match | |
61 | live registers at the start of the new block. | |
9f3e3774 | 62 | |
31adcf56 | 63 | 2. We try to combine the local chains across basic block boundaries by |
64 | comparing chains that were open at the start or end of a block to | |
65 | those in successor/predecessor blocks. | |
66 | ||
67 | 3. For each chain, the set of possible renaming registers is computed. | |
9f3e3774 | 68 | This takes into account the renaming of previously processed chains. |
69 | Optionally, a preferred class is computed for the renaming register. | |
70 | ||
31adcf56 | 71 | 4. The best renaming register is computed for the chain in the above set, |
9f3e3774 | 72 | using a round-robin allocation. If a preferred class exists, then the |
73 | round-robin allocation is done within the class first, if possible. | |
74 | The round-robin allocation of renaming registers itself is global. | |
75 | ||
31adcf56 | 76 | 5. If a renaming register has been found, it is substituted in the chain. |
9f3e3774 | 77 | |
78 | Targets can parameterize the pass by specifying a preferred class for the | |
79 | renaming register for a given (super)class of registers to be renamed. */ | |
80 | ||
c38fa63b | 81 | #if HOST_BITS_PER_WIDE_INT <= MAX_RECOG_OPERANDS |
82 | #error "Use a different bitmap implementation for untracked_operands." | |
83 | #endif | |
9f3e3774 | 84 | |
1140e77e | 85 | enum scan_actions |
86 | { | |
1140e77e | 87 | terminate_write, |
88 | terminate_dead, | |
7197e178 | 89 | mark_all_read, |
1140e77e | 90 | mark_read, |
b9d576f5 | 91 | mark_write, |
92 | /* mark_access is for marking the destination regs in | |
93 | REG_FRAME_RELATED_EXPR notes (as if they were read) so that the | |
94 | note is updated properly. */ | |
95 | mark_access | |
1140e77e | 96 | }; |
97 | ||
98 | static const char * const scan_actions_name[] = | |
99 | { | |
1140e77e | 100 | "terminate_write", |
101 | "terminate_dead", | |
7197e178 | 102 | "mark_all_read", |
1140e77e | 103 | "mark_read", |
b9d576f5 | 104 | "mark_write", |
105 | "mark_access" | |
1140e77e | 106 | }; |
107 | ||
8fe3bc87 | 108 | /* TICK and THIS_TICK are used to record the last time we saw each |
109 | register. */ | |
110 | static int tick[FIRST_PSEUDO_REGISTER]; | |
111 | static int this_tick = 0; | |
112 | ||
1140e77e | 113 | static struct obstack rename_obstack; |
114 | ||
7de639a2 | 115 | /* If nonnull, the code calling into the register renamer requested |
116 | information about insn operands, and we store it here. */ | |
f1f41a6c | 117 | vec<insn_rr_info> insn_rr; |
7de639a2 | 118 | |
05d5500b | 119 | static void scan_rtx (rtx_insn *, rtx *, enum reg_class, enum scan_actions, |
de67d37e | 120 | enum op_type); |
31adcf56 | 121 | static bool build_def_use (basic_block); |
d5dfb455 | 122 | |
8fe3bc87 | 123 | /* The id to be given to the next opened chain. */ |
124 | static unsigned current_id; | |
125 | ||
126 | /* A mapping of unique id numbers to chains. */ | |
f1f41a6c | 127 | static vec<du_head_p> id_to_chain; |
d5dfb455 | 128 | |
31adcf56 | 129 | /* List of currently open chains. */ |
8fe3bc87 | 130 | static struct du_head *open_chains; |
8fe3bc87 | 131 | |
132 | /* Bitmap of open chains. The bits set always match the list found in | |
133 | open_chains. */ | |
134 | static bitmap_head open_chains_set; | |
135 | ||
136 | /* Record the registers being tracked in open_chains. */ | |
137 | static HARD_REG_SET live_in_chains; | |
138 | ||
139 | /* Record the registers that are live but not tracked. The intersection | |
140 | between this and live_in_chains is empty. */ | |
141 | static HARD_REG_SET live_hard_regs; | |
142 | ||
7de639a2 | 143 | /* Set while scanning RTL if INSN_RR is nonnull, i.e. if the current analysis |
144 | is for a caller that requires operand data. Used in | |
145 | record_operand_use. */ | |
146 | static operand_rr_info *cur_operand; | |
147 | ||
31adcf56 | 148 | /* Return the chain corresponding to id number ID. Take into account that |
149 | chains may have been merged. */ | |
7de639a2 | 150 | du_head_p |
151 | regrename_chain_from_id (unsigned int id) | |
31adcf56 | 152 | { |
f1f41a6c | 153 | du_head_p first_chain = id_to_chain[id]; |
31adcf56 | 154 | du_head_p chain = first_chain; |
155 | while (chain->id != id) | |
156 | { | |
157 | id = chain->id; | |
f1f41a6c | 158 | chain = id_to_chain[id]; |
31adcf56 | 159 | } |
160 | first_chain->id = id; | |
161 | return chain; | |
162 | } | |
163 | ||
164 | /* Dump all def/use chains, starting at id FROM. */ | |
8fe3bc87 | 165 | |
166 | static void | |
31adcf56 | 167 | dump_def_use_chain (int from) |
8fe3bc87 | 168 | { |
31adcf56 | 169 | du_head_p head; |
170 | int i; | |
f1f41a6c | 171 | FOR_EACH_VEC_ELT_FROM (id_to_chain, i, head, from) |
8fe3bc87 | 172 | { |
173 | struct du_chain *this_du = head->first; | |
31adcf56 | 174 | |
8fe3bc87 | 175 | fprintf (dump_file, "Register %s (%d):", |
176 | reg_names[head->regno], head->nregs); | |
177 | while (this_du) | |
178 | { | |
179 | fprintf (dump_file, " %d [%s]", INSN_UID (this_du->insn), | |
180 | reg_class_names[this_du->cl]); | |
181 | this_du = this_du->next_use; | |
182 | } | |
183 | fprintf (dump_file, "\n"); | |
184 | head = head->next_chain; | |
185 | } | |
186 | } | |
187 | ||
d5dfb455 | 188 | static void |
7197e178 | 189 | free_chain_data (void) |
d5dfb455 | 190 | { |
7197e178 | 191 | int i; |
192 | du_head_p ptr; | |
f1f41a6c | 193 | for (i = 0; id_to_chain.iterate (i, &ptr); i++) |
7197e178 | 194 | bitmap_clear (&ptr->conflicts); |
feb90512 | 195 | |
f1f41a6c | 196 | id_to_chain.release (); |
d5dfb455 | 197 | } |
198 | ||
92effe69 | 199 | /* Walk all chains starting with CHAINS and record that they conflict with |
200 | another chain whose id is ID. */ | |
201 | ||
202 | static void | |
203 | mark_conflict (struct du_head *chains, unsigned id) | |
204 | { | |
205 | while (chains) | |
206 | { | |
207 | bitmap_set_bit (&chains->conflicts, id); | |
208 | chains = chains->next_chain; | |
209 | } | |
210 | } | |
211 | ||
7de639a2 | 212 | /* Examine cur_operand, and if it is nonnull, record information about the |
213 | use THIS_DU which is part of the chain HEAD. */ | |
214 | ||
215 | static void | |
216 | record_operand_use (struct du_head *head, struct du_chain *this_du) | |
217 | { | |
218 | if (cur_operand == NULL) | |
219 | return; | |
220 | gcc_assert (cur_operand->n_chains < MAX_REGS_PER_ADDRESS); | |
221 | cur_operand->heads[cur_operand->n_chains] = head; | |
222 | cur_operand->chains[cur_operand->n_chains++] = this_du; | |
223 | } | |
224 | ||
92effe69 | 225 | /* Create a new chain for THIS_NREGS registers starting at THIS_REGNO, |
226 | and record its occurrence in *LOC, which is being written to in INSN. | |
227 | This access requires a register of class CL. */ | |
228 | ||
31adcf56 | 229 | static du_head_p |
92effe69 | 230 | create_new_chain (unsigned this_regno, unsigned this_nregs, rtx *loc, |
05d5500b | 231 | rtx_insn *insn, enum reg_class cl) |
92effe69 | 232 | { |
233 | struct du_head *head = XOBNEW (&rename_obstack, struct du_head); | |
234 | struct du_chain *this_du; | |
235 | int nregs; | |
236 | ||
237 | head->next_chain = open_chains; | |
92effe69 | 238 | head->regno = this_regno; |
239 | head->nregs = this_nregs; | |
240 | head->need_caller_save_reg = 0; | |
241 | head->cannot_rename = 0; | |
242 | ||
f1f41a6c | 243 | id_to_chain.safe_push (head); |
92effe69 | 244 | head->id = current_id++; |
245 | ||
246 | bitmap_initialize (&head->conflicts, &bitmap_default_obstack); | |
247 | bitmap_copy (&head->conflicts, &open_chains_set); | |
248 | mark_conflict (open_chains, head->id); | |
249 | ||
250 | /* Since we're tracking this as a chain now, remove it from the | |
251 | list of conflicting live hard registers and track it in | |
252 | live_in_chains instead. */ | |
253 | nregs = head->nregs; | |
254 | while (nregs-- > 0) | |
255 | { | |
256 | SET_HARD_REG_BIT (live_in_chains, head->regno + nregs); | |
257 | CLEAR_HARD_REG_BIT (live_hard_regs, head->regno + nregs); | |
258 | } | |
259 | ||
260 | COPY_HARD_REG_SET (head->hard_conflicts, live_hard_regs); | |
261 | bitmap_set_bit (&open_chains_set, head->id); | |
262 | ||
263 | open_chains = head; | |
264 | ||
265 | if (dump_file) | |
266 | { | |
267 | fprintf (dump_file, "Creating chain %s (%d)", | |
268 | reg_names[head->regno], head->id); | |
269 | if (insn != NULL_RTX) | |
270 | fprintf (dump_file, " at insn %d", INSN_UID (insn)); | |
271 | fprintf (dump_file, "\n"); | |
272 | } | |
273 | ||
274 | if (insn == NULL_RTX) | |
275 | { | |
276 | head->first = head->last = NULL; | |
31adcf56 | 277 | return head; |
92effe69 | 278 | } |
279 | ||
280 | this_du = XOBNEW (&rename_obstack, struct du_chain); | |
281 | head->first = head->last = this_du; | |
282 | ||
283 | this_du->next_use = 0; | |
284 | this_du->loc = loc; | |
285 | this_du->insn = insn; | |
286 | this_du->cl = cl; | |
7de639a2 | 287 | record_operand_use (head, this_du); |
31adcf56 | 288 | return head; |
92effe69 | 289 | } |
290 | ||
7197e178 | 291 | /* For a def-use chain HEAD, find which registers overlap its lifetime and |
292 | set the corresponding bits in *PSET. */ | |
d5dfb455 | 293 | |
294 | static void | |
7197e178 | 295 | merge_overlapping_regs (HARD_REG_SET *pset, struct du_head *head) |
d5dfb455 | 296 | { |
7197e178 | 297 | bitmap_iterator bi; |
298 | unsigned i; | |
299 | IOR_HARD_REG_SET (*pset, head->hard_conflicts); | |
300 | EXECUTE_IF_SET_IN_BITMAP (&head->conflicts, 0, i, bi) | |
98ce3092 | 301 | { |
7de639a2 | 302 | du_head_p other = regrename_chain_from_id (i); |
7197e178 | 303 | unsigned j = other->nregs; |
31adcf56 | 304 | gcc_assert (other != head); |
7197e178 | 305 | while (j-- > 0) |
306 | SET_HARD_REG_BIT (*pset, other->regno + j); | |
d5dfb455 | 307 | } |
308 | } | |
309 | ||
d78118a3 | 310 | /* Check if NEW_REG can be the candidate register to rename for |
311 | REG in THIS_HEAD chain. THIS_UNAVAILABLE is a set of unavailable hard | |
312 | registers. */ | |
313 | ||
314 | static bool | |
57ce0a99 | 315 | check_new_reg_p (int reg ATTRIBUTE_UNUSED, int new_reg, |
316 | struct du_head *this_head, HARD_REG_SET this_unavailable) | |
d78118a3 | 317 | { |
318 | enum machine_mode mode = GET_MODE (*this_head->first->loc); | |
319 | int nregs = hard_regno_nregs[new_reg][mode]; | |
320 | int i; | |
321 | struct du_chain *tmp; | |
322 | ||
323 | for (i = nregs - 1; i >= 0; --i) | |
324 | if (TEST_HARD_REG_BIT (this_unavailable, new_reg + i) | |
325 | || fixed_regs[new_reg + i] | |
326 | || global_regs[new_reg + i] | |
327 | /* Can't use regs which aren't saved by the prologue. */ | |
328 | || (! df_regs_ever_live_p (new_reg + i) | |
329 | && ! call_used_regs[new_reg + i]) | |
330 | #ifdef LEAF_REGISTERS | |
331 | /* We can't use a non-leaf register if we're in a | |
332 | leaf function. */ | |
d5bf7b64 | 333 | || (crtl->is_leaf |
d78118a3 | 334 | && !LEAF_REGISTERS[new_reg + i]) |
335 | #endif | |
336 | #ifdef HARD_REGNO_RENAME_OK | |
337 | || ! HARD_REGNO_RENAME_OK (reg + i, new_reg + i) | |
338 | #endif | |
339 | ) | |
340 | return false; | |
341 | ||
342 | /* See whether it accepts all modes that occur in | |
343 | definition and uses. */ | |
344 | for (tmp = this_head->first; tmp; tmp = tmp->next_use) | |
345 | if ((! HARD_REGNO_MODE_OK (new_reg, GET_MODE (*tmp->loc)) | |
346 | && ! DEBUG_INSN_P (tmp->insn)) | |
347 | || (this_head->need_caller_save_reg | |
348 | && ! (HARD_REGNO_CALL_PART_CLOBBERED | |
349 | (reg, GET_MODE (*tmp->loc))) | |
350 | && (HARD_REGNO_CALL_PART_CLOBBERED | |
351 | (new_reg, GET_MODE (*tmp->loc))))) | |
352 | return false; | |
353 | ||
354 | return true; | |
355 | } | |
356 | ||
7de639a2 | 357 | /* For the chain THIS_HEAD, compute and return the best register to |
358 | rename to. SUPER_CLASS is the superunion of register classes in | |
359 | the chain. UNAVAILABLE is a set of registers that cannot be used. | |
360 | OLD_REG is the register currently used for the chain. */ | |
361 | ||
362 | int | |
363 | find_best_rename_reg (du_head_p this_head, enum reg_class super_class, | |
364 | HARD_REG_SET *unavailable, int old_reg) | |
365 | { | |
366 | bool has_preferred_class; | |
367 | enum reg_class preferred_class; | |
368 | int pass; | |
369 | int best_new_reg = old_reg; | |
370 | ||
371 | /* Further narrow the set of registers we can use for renaming. | |
372 | If the chain needs a call-saved register, mark the call-used | |
373 | registers as unavailable. */ | |
374 | if (this_head->need_caller_save_reg) | |
375 | IOR_HARD_REG_SET (*unavailable, call_used_reg_set); | |
376 | ||
377 | /* Mark registers that overlap this chain's lifetime as unavailable. */ | |
378 | merge_overlapping_regs (unavailable, this_head); | |
379 | ||
380 | /* Compute preferred rename class of super union of all the classes | |
381 | in the chain. */ | |
382 | preferred_class | |
383 | = (enum reg_class) targetm.preferred_rename_class (super_class); | |
384 | ||
385 | /* If PREFERRED_CLASS is not NO_REGS, we iterate in the first pass | |
386 | over registers that belong to PREFERRED_CLASS and try to find the | |
387 | best register within the class. If that failed, we iterate in | |
388 | the second pass over registers that don't belong to the class. | |
389 | If PREFERRED_CLASS is NO_REGS, we iterate over all registers in | |
390 | ascending order without any preference. */ | |
391 | has_preferred_class = (preferred_class != NO_REGS); | |
392 | for (pass = (has_preferred_class ? 0 : 1); pass < 2; pass++) | |
393 | { | |
394 | int new_reg; | |
395 | for (new_reg = 0; new_reg < FIRST_PSEUDO_REGISTER; new_reg++) | |
396 | { | |
397 | if (has_preferred_class | |
398 | && (pass == 0) | |
399 | != TEST_HARD_REG_BIT (reg_class_contents[preferred_class], | |
400 | new_reg)) | |
401 | continue; | |
402 | ||
403 | /* In the first pass, we force the renaming of registers that | |
404 | don't belong to PREFERRED_CLASS to registers that do, even | |
405 | though the latters were used not very long ago. */ | |
406 | if (check_new_reg_p (old_reg, new_reg, this_head, | |
407 | *unavailable) | |
408 | && ((pass == 0 | |
409 | && !TEST_HARD_REG_BIT (reg_class_contents[preferred_class], | |
410 | best_new_reg)) | |
411 | || tick[best_new_reg] > tick[new_reg])) | |
412 | best_new_reg = new_reg; | |
413 | } | |
414 | if (pass == 0 && best_new_reg != old_reg) | |
415 | break; | |
416 | } | |
417 | return best_new_reg; | |
418 | } | |
419 | ||
31adcf56 | 420 | /* Perform register renaming on the current function. */ |
8fe3bc87 | 421 | static void |
31adcf56 | 422 | rename_chains (void) |
8fe3bc87 | 423 | { |
424 | HARD_REG_SET unavailable; | |
31adcf56 | 425 | du_head_p this_head; |
426 | int i; | |
427 | ||
428 | memset (tick, 0, sizeof tick); | |
8fe3bc87 | 429 | |
430 | CLEAR_HARD_REG_SET (unavailable); | |
431 | /* Don't clobber traceback for noreturn functions. */ | |
432 | if (frame_pointer_needed) | |
433 | { | |
434 | add_to_hard_reg_set (&unavailable, Pmode, FRAME_POINTER_REGNUM); | |
435 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER | |
436 | add_to_hard_reg_set (&unavailable, Pmode, HARD_FRAME_POINTER_REGNUM); | |
437 | #endif | |
438 | } | |
439 | ||
f1f41a6c | 440 | FOR_EACH_VEC_ELT (id_to_chain, i, this_head) |
8fe3bc87 | 441 | { |
7de639a2 | 442 | int best_new_reg; |
8fe3bc87 | 443 | int n_uses; |
8fe3bc87 | 444 | struct du_chain *tmp; |
445 | HARD_REG_SET this_unavailable; | |
446 | int reg = this_head->regno; | |
8fe3bc87 | 447 | enum reg_class super_class = NO_REGS; |
8fe3bc87 | 448 | |
8fe3bc87 | 449 | if (this_head->cannot_rename) |
450 | continue; | |
451 | ||
8fe3bc87 | 452 | if (fixed_regs[reg] || global_regs[reg] |
453 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER | |
454 | || (frame_pointer_needed && reg == HARD_FRAME_POINTER_REGNUM) | |
455 | #else | |
456 | || (frame_pointer_needed && reg == FRAME_POINTER_REGNUM) | |
457 | #endif | |
458 | ) | |
459 | continue; | |
460 | ||
461 | COPY_HARD_REG_SET (this_unavailable, unavailable); | |
462 | ||
463 | /* Iterate over elements in the chain in order to: | |
464 | 1. Count number of uses, and narrow the set of registers we can | |
465 | use for renaming. | |
466 | 2. Compute the superunion of register classes in this chain. */ | |
467 | n_uses = 0; | |
468 | super_class = NO_REGS; | |
469 | for (tmp = this_head->first; tmp; tmp = tmp->next_use) | |
470 | { | |
471 | if (DEBUG_INSN_P (tmp->insn)) | |
472 | continue; | |
473 | n_uses++; | |
474 | IOR_COMPL_HARD_REG_SET (this_unavailable, | |
475 | reg_class_contents[tmp->cl]); | |
476 | super_class | |
477 | = reg_class_superunion[(int) super_class][(int) tmp->cl]; | |
478 | } | |
479 | ||
480 | if (n_uses < 2) | |
481 | continue; | |
482 | ||
7de639a2 | 483 | best_new_reg = find_best_rename_reg (this_head, super_class, |
484 | &this_unavailable, reg); | |
8fe3bc87 | 485 | |
486 | if (dump_file) | |
487 | { | |
488 | fprintf (dump_file, "Register %s in insn %d", | |
489 | reg_names[reg], INSN_UID (this_head->first->insn)); | |
490 | if (this_head->need_caller_save_reg) | |
491 | fprintf (dump_file, " crosses a call"); | |
492 | } | |
493 | ||
494 | if (best_new_reg == reg) | |
495 | { | |
496 | tick[reg] = ++this_tick; | |
497 | if (dump_file) | |
498 | fprintf (dump_file, "; no available better choice\n"); | |
499 | continue; | |
500 | } | |
501 | ||
502 | if (dump_file) | |
503 | fprintf (dump_file, ", renamed as %s\n", reg_names[best_new_reg]); | |
504 | ||
7de639a2 | 505 | regrename_do_replace (this_head, best_new_reg); |
8fe3bc87 | 506 | tick[best_new_reg] = ++this_tick; |
507 | df_set_regs_ever_live (best_new_reg, true); | |
508 | } | |
509 | } | |
510 | ||
31adcf56 | 511 | /* A structure to record information for each hard register at the start of |
512 | a basic block. */ | |
513 | struct incoming_reg_info { | |
514 | /* Holds the number of registers used in the chain that gave us information | |
515 | about this register. Zero means no information known yet, while a | |
516 | negative value is used for something that is part of, but not the first | |
517 | register in a multi-register value. */ | |
518 | int nregs; | |
519 | /* Set to true if we have accesses that conflict in the number of registers | |
520 | used. */ | |
521 | bool unusable; | |
522 | }; | |
523 | ||
524 | /* A structure recording information about each basic block. It is saved | |
525 | and restored around basic block boundaries. | |
526 | A pointer to such a structure is stored in each basic block's aux field | |
527 | during regrename_analyze, except for blocks we know can't be optimized | |
528 | (such as entry and exit blocks). */ | |
529 | struct bb_rename_info | |
530 | { | |
531 | /* The basic block corresponding to this structure. */ | |
532 | basic_block bb; | |
533 | /* Copies of the global information. */ | |
534 | bitmap_head open_chains_set; | |
535 | bitmap_head incoming_open_chains_set; | |
536 | struct incoming_reg_info incoming[FIRST_PSEUDO_REGISTER]; | |
537 | }; | |
538 | ||
539 | /* Initialize a rename_info structure P for basic block BB, which starts a new | |
540 | scan. */ | |
541 | static void | |
542 | init_rename_info (struct bb_rename_info *p, basic_block bb) | |
543 | { | |
544 | int i; | |
f1c570a6 | 545 | df_ref def; |
31adcf56 | 546 | HARD_REG_SET start_chains_set; |
547 | ||
548 | p->bb = bb; | |
549 | bitmap_initialize (&p->open_chains_set, &bitmap_default_obstack); | |
550 | bitmap_initialize (&p->incoming_open_chains_set, &bitmap_default_obstack); | |
551 | ||
552 | open_chains = NULL; | |
553 | bitmap_clear (&open_chains_set); | |
554 | ||
555 | CLEAR_HARD_REG_SET (live_in_chains); | |
556 | REG_SET_TO_HARD_REG_SET (live_hard_regs, df_get_live_in (bb)); | |
f1c570a6 | 557 | FOR_EACH_ARTIFICIAL_DEF (def, bb->index) |
558 | if (DF_REF_FLAGS (def) & DF_REF_AT_TOP) | |
559 | SET_HARD_REG_BIT (live_hard_regs, DF_REF_REGNO (def)); | |
31adcf56 | 560 | |
561 | /* Open chains based on information from (at least one) predecessor | |
562 | block. This gives us a chance later on to combine chains across | |
563 | basic block boundaries. Inconsistencies (in access sizes) will | |
564 | be caught normally and dealt with conservatively by disabling the | |
565 | chain for renaming, and there is no risk of losing optimization | |
566 | opportunities by opening chains either: if we did not open the | |
567 | chains, we'd have to track the live register as a hard reg, and | |
568 | we'd be unable to rename it in any case. */ | |
569 | CLEAR_HARD_REG_SET (start_chains_set); | |
570 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
571 | { | |
572 | struct incoming_reg_info *iri = p->incoming + i; | |
573 | if (iri->nregs > 0 && !iri->unusable | |
574 | && range_in_hard_reg_set_p (live_hard_regs, i, iri->nregs)) | |
575 | { | |
576 | SET_HARD_REG_BIT (start_chains_set, i); | |
577 | remove_range_from_hard_reg_set (&live_hard_regs, i, iri->nregs); | |
578 | } | |
579 | } | |
580 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
581 | { | |
582 | struct incoming_reg_info *iri = p->incoming + i; | |
583 | if (TEST_HARD_REG_BIT (start_chains_set, i)) | |
584 | { | |
585 | du_head_p chain; | |
586 | if (dump_file) | |
587 | fprintf (dump_file, "opening incoming chain\n"); | |
05d5500b | 588 | chain = create_new_chain (i, iri->nregs, NULL, NULL, NO_REGS); |
31adcf56 | 589 | bitmap_set_bit (&p->incoming_open_chains_set, chain->id); |
590 | } | |
591 | } | |
592 | } | |
593 | ||
594 | /* Record in RI that the block corresponding to it has an incoming | |
595 | live value, described by CHAIN. */ | |
596 | static void | |
597 | set_incoming_from_chain (struct bb_rename_info *ri, du_head_p chain) | |
598 | { | |
599 | int i; | |
600 | int incoming_nregs = ri->incoming[chain->regno].nregs; | |
601 | int nregs; | |
602 | ||
603 | /* If we've recorded the same information before, everything is fine. */ | |
604 | if (incoming_nregs == chain->nregs) | |
605 | { | |
606 | if (dump_file) | |
607 | fprintf (dump_file, "reg %d/%d already recorded\n", | |
608 | chain->regno, chain->nregs); | |
609 | return; | |
610 | } | |
611 | ||
612 | /* If we have no information for any of the involved registers, update | |
613 | the incoming array. */ | |
614 | nregs = chain->nregs; | |
615 | while (nregs-- > 0) | |
616 | if (ri->incoming[chain->regno + nregs].nregs != 0 | |
617 | || ri->incoming[chain->regno + nregs].unusable) | |
618 | break; | |
619 | if (nregs < 0) | |
620 | { | |
621 | nregs = chain->nregs; | |
622 | ri->incoming[chain->regno].nregs = nregs; | |
623 | while (nregs-- > 1) | |
624 | ri->incoming[chain->regno + nregs].nregs = -nregs; | |
625 | if (dump_file) | |
626 | fprintf (dump_file, "recorded reg %d/%d\n", | |
627 | chain->regno, chain->nregs); | |
628 | return; | |
629 | } | |
630 | ||
631 | /* There must be some kind of conflict. Prevent both the old and | |
632 | new ranges from being used. */ | |
633 | if (incoming_nregs < 0) | |
634 | ri->incoming[chain->regno + incoming_nregs].unusable = true; | |
635 | for (i = 0; i < chain->nregs; i++) | |
636 | ri->incoming[chain->regno + i].unusable = true; | |
637 | } | |
638 | ||
639 | /* Merge the two chains C1 and C2 so that all conflict information is | |
640 | recorded and C1, and the id of C2 is changed to that of C1. */ | |
641 | static void | |
642 | merge_chains (du_head_p c1, du_head_p c2) | |
643 | { | |
644 | if (c1 == c2) | |
645 | return; | |
646 | ||
647 | if (c2->first != NULL) | |
648 | { | |
649 | if (c1->first == NULL) | |
650 | c1->first = c2->first; | |
651 | else | |
652 | c1->last->next_use = c2->first; | |
653 | c1->last = c2->last; | |
654 | } | |
655 | ||
656 | c2->first = c2->last = NULL; | |
657 | c2->id = c1->id; | |
658 | ||
659 | IOR_HARD_REG_SET (c1->hard_conflicts, c2->hard_conflicts); | |
660 | bitmap_ior_into (&c1->conflicts, &c2->conflicts); | |
661 | ||
662 | c1->need_caller_save_reg |= c2->need_caller_save_reg; | |
663 | c1->cannot_rename |= c2->cannot_rename; | |
664 | } | |
665 | ||
666 | /* Analyze the current function and build chains for renaming. */ | |
667 | ||
7de639a2 | 668 | void |
669 | regrename_analyze (bitmap bb_mask) | |
31adcf56 | 670 | { |
671 | struct bb_rename_info *rename_info; | |
672 | int i; | |
673 | basic_block bb; | |
674 | int n_bbs; | |
675 | int *inverse_postorder; | |
676 | ||
fe672ac0 | 677 | inverse_postorder = XNEWVEC (int, last_basic_block_for_fn (cfun)); |
31adcf56 | 678 | n_bbs = pre_and_rev_post_order_compute (NULL, inverse_postorder, false); |
679 | ||
680 | /* Gather some information about the blocks in this function. */ | |
a28770e1 | 681 | rename_info = XCNEWVEC (struct bb_rename_info, n_basic_blocks_for_fn (cfun)); |
31adcf56 | 682 | i = 0; |
fc00614f | 683 | FOR_EACH_BB_FN (bb, cfun) |
31adcf56 | 684 | { |
685 | struct bb_rename_info *ri = rename_info + i; | |
686 | ri->bb = bb; | |
7de639a2 | 687 | if (bb_mask != NULL && !bitmap_bit_p (bb_mask, bb->index)) |
688 | bb->aux = NULL; | |
689 | else | |
690 | bb->aux = ri; | |
31adcf56 | 691 | i++; |
692 | } | |
693 | ||
694 | current_id = 0; | |
f1f41a6c | 695 | id_to_chain.create (0); |
31adcf56 | 696 | bitmap_initialize (&open_chains_set, &bitmap_default_obstack); |
697 | ||
698 | /* The order in which we visit blocks ensures that whenever | |
699 | possible, we only process a block after at least one of its | |
700 | predecessors, which provides a "seeding" effect to make the logic | |
701 | in set_incoming_from_chain and init_rename_info useful. */ | |
702 | ||
703 | for (i = 0; i < n_bbs; i++) | |
704 | { | |
f5a6b05f | 705 | basic_block bb1 = BASIC_BLOCK_FOR_FN (cfun, inverse_postorder[i]); |
31adcf56 | 706 | struct bb_rename_info *this_info; |
707 | bool success; | |
708 | edge e; | |
709 | edge_iterator ei; | |
f1f41a6c | 710 | int old_length = id_to_chain.length (); |
31adcf56 | 711 | |
712 | this_info = (struct bb_rename_info *) bb1->aux; | |
713 | if (this_info == NULL) | |
714 | continue; | |
715 | ||
716 | if (dump_file) | |
717 | fprintf (dump_file, "\nprocessing block %d:\n", bb1->index); | |
718 | ||
719 | init_rename_info (this_info, bb1); | |
720 | ||
721 | success = build_def_use (bb1); | |
722 | if (!success) | |
723 | { | |
724 | if (dump_file) | |
725 | fprintf (dump_file, "failed\n"); | |
726 | bb1->aux = NULL; | |
f1f41a6c | 727 | id_to_chain.truncate (old_length); |
31adcf56 | 728 | current_id = old_length; |
729 | bitmap_clear (&this_info->incoming_open_chains_set); | |
730 | open_chains = NULL; | |
f1f41a6c | 731 | if (insn_rr.exists ()) |
7de639a2 | 732 | { |
05d5500b | 733 | rtx_insn *insn; |
7de639a2 | 734 | FOR_BB_INSNS (bb1, insn) |
735 | { | |
f1f41a6c | 736 | insn_rr_info *p = &insn_rr[INSN_UID (insn)]; |
7de639a2 | 737 | p->op_info = NULL; |
738 | } | |
739 | } | |
31adcf56 | 740 | continue; |
741 | } | |
742 | ||
743 | if (dump_file) | |
744 | dump_def_use_chain (old_length); | |
745 | bitmap_copy (&this_info->open_chains_set, &open_chains_set); | |
746 | ||
747 | /* Add successor blocks to the worklist if necessary, and record | |
748 | data about our own open chains at the end of this block, which | |
749 | will be used to pre-open chains when processing the successors. */ | |
750 | FOR_EACH_EDGE (e, ei, bb1->succs) | |
751 | { | |
752 | struct bb_rename_info *dest_ri; | |
753 | struct du_head *chain; | |
754 | ||
755 | if (dump_file) | |
756 | fprintf (dump_file, "successor block %d\n", e->dest->index); | |
757 | ||
758 | if (e->flags & (EDGE_EH | EDGE_ABNORMAL)) | |
759 | continue; | |
760 | dest_ri = (struct bb_rename_info *)e->dest->aux; | |
761 | if (dest_ri == NULL) | |
762 | continue; | |
763 | for (chain = open_chains; chain; chain = chain->next_chain) | |
764 | set_incoming_from_chain (dest_ri, chain); | |
765 | } | |
766 | } | |
767 | ||
768 | free (inverse_postorder); | |
769 | ||
770 | /* Now, combine the chains data we have gathered across basic block | |
771 | boundaries. | |
772 | ||
773 | For every basic block, there may be chains open at the start, or at the | |
774 | end. Rather than exclude them from renaming, we look for open chains | |
775 | with matching registers at the other side of the CFG edge. | |
776 | ||
777 | For a given chain using register R, open at the start of block B, we | |
778 | must find an open chain using R on the other side of every edge leading | |
779 | to B, if the register is live across this edge. In the code below, | |
780 | N_PREDS_USED counts the number of edges where the register is live, and | |
781 | N_PREDS_JOINED counts those where we found an appropriate chain for | |
782 | joining. | |
783 | ||
784 | We perform the analysis for both incoming and outgoing edges, but we | |
785 | only need to merge once (in the second part, after verifying outgoing | |
786 | edges). */ | |
fc00614f | 787 | FOR_EACH_BB_FN (bb, cfun) |
31adcf56 | 788 | { |
789 | struct bb_rename_info *bb_ri = (struct bb_rename_info *) bb->aux; | |
790 | unsigned j; | |
791 | bitmap_iterator bi; | |
792 | ||
793 | if (bb_ri == NULL) | |
794 | continue; | |
795 | ||
796 | if (dump_file) | |
797 | fprintf (dump_file, "processing bb %d in edges\n", bb->index); | |
798 | ||
799 | EXECUTE_IF_SET_IN_BITMAP (&bb_ri->incoming_open_chains_set, 0, j, bi) | |
800 | { | |
801 | edge e; | |
802 | edge_iterator ei; | |
7de639a2 | 803 | struct du_head *chain = regrename_chain_from_id (j); |
31adcf56 | 804 | int n_preds_used = 0, n_preds_joined = 0; |
805 | ||
806 | FOR_EACH_EDGE (e, ei, bb->preds) | |
807 | { | |
808 | struct bb_rename_info *src_ri; | |
809 | unsigned k; | |
810 | bitmap_iterator bi2; | |
811 | HARD_REG_SET live; | |
812 | bool success = false; | |
813 | ||
814 | REG_SET_TO_HARD_REG_SET (live, df_get_live_out (e->src)); | |
815 | if (!range_overlaps_hard_reg_set_p (live, chain->regno, | |
816 | chain->nregs)) | |
817 | continue; | |
818 | n_preds_used++; | |
819 | ||
820 | if (e->flags & (EDGE_EH | EDGE_ABNORMAL)) | |
821 | continue; | |
822 | ||
823 | src_ri = (struct bb_rename_info *)e->src->aux; | |
824 | if (src_ri == NULL) | |
825 | continue; | |
826 | ||
827 | EXECUTE_IF_SET_IN_BITMAP (&src_ri->open_chains_set, | |
828 | 0, k, bi2) | |
829 | { | |
7de639a2 | 830 | struct du_head *outgoing_chain = regrename_chain_from_id (k); |
31adcf56 | 831 | |
832 | if (outgoing_chain->regno == chain->regno | |
833 | && outgoing_chain->nregs == chain->nregs) | |
834 | { | |
835 | n_preds_joined++; | |
836 | success = true; | |
837 | break; | |
838 | } | |
839 | } | |
840 | if (!success && dump_file) | |
841 | fprintf (dump_file, "failure to match with pred block %d\n", | |
842 | e->src->index); | |
843 | } | |
844 | if (n_preds_joined < n_preds_used) | |
845 | { | |
846 | if (dump_file) | |
847 | fprintf (dump_file, "cannot rename chain %d\n", j); | |
848 | chain->cannot_rename = 1; | |
849 | } | |
850 | } | |
851 | } | |
fc00614f | 852 | FOR_EACH_BB_FN (bb, cfun) |
31adcf56 | 853 | { |
854 | struct bb_rename_info *bb_ri = (struct bb_rename_info *) bb->aux; | |
855 | unsigned j; | |
856 | bitmap_iterator bi; | |
857 | ||
858 | if (bb_ri == NULL) | |
859 | continue; | |
860 | ||
861 | if (dump_file) | |
862 | fprintf (dump_file, "processing bb %d out edges\n", bb->index); | |
863 | ||
864 | EXECUTE_IF_SET_IN_BITMAP (&bb_ri->open_chains_set, 0, j, bi) | |
865 | { | |
866 | edge e; | |
867 | edge_iterator ei; | |
7de639a2 | 868 | struct du_head *chain = regrename_chain_from_id (j); |
31adcf56 | 869 | int n_succs_used = 0, n_succs_joined = 0; |
870 | ||
871 | FOR_EACH_EDGE (e, ei, bb->succs) | |
872 | { | |
873 | bool printed = false; | |
874 | struct bb_rename_info *dest_ri; | |
875 | unsigned k; | |
876 | bitmap_iterator bi2; | |
877 | HARD_REG_SET live; | |
878 | ||
879 | REG_SET_TO_HARD_REG_SET (live, df_get_live_in (e->dest)); | |
880 | if (!range_overlaps_hard_reg_set_p (live, chain->regno, | |
881 | chain->nregs)) | |
882 | continue; | |
883 | ||
884 | n_succs_used++; | |
885 | ||
886 | dest_ri = (struct bb_rename_info *)e->dest->aux; | |
887 | if (dest_ri == NULL) | |
888 | continue; | |
889 | ||
890 | EXECUTE_IF_SET_IN_BITMAP (&dest_ri->incoming_open_chains_set, | |
891 | 0, k, bi2) | |
892 | { | |
7de639a2 | 893 | struct du_head *incoming_chain = regrename_chain_from_id (k); |
31adcf56 | 894 | |
895 | if (incoming_chain->regno == chain->regno | |
896 | && incoming_chain->nregs == chain->nregs) | |
897 | { | |
898 | if (dump_file) | |
899 | { | |
900 | if (!printed) | |
901 | fprintf (dump_file, | |
902 | "merging blocks for edge %d -> %d\n", | |
903 | e->src->index, e->dest->index); | |
904 | printed = true; | |
905 | fprintf (dump_file, | |
906 | " merging chains %d (->%d) and %d (->%d) [%s]\n", | |
907 | k, incoming_chain->id, j, chain->id, | |
908 | reg_names[incoming_chain->regno]); | |
909 | } | |
910 | ||
911 | merge_chains (chain, incoming_chain); | |
912 | n_succs_joined++; | |
913 | break; | |
914 | } | |
915 | } | |
916 | } | |
917 | if (n_succs_joined < n_succs_used) | |
918 | { | |
919 | if (dump_file) | |
920 | fprintf (dump_file, "cannot rename chain %d\n", | |
921 | j); | |
922 | chain->cannot_rename = 1; | |
923 | } | |
924 | } | |
925 | } | |
926 | ||
927 | free (rename_info); | |
928 | ||
fc00614f | 929 | FOR_EACH_BB_FN (bb, cfun) |
31adcf56 | 930 | bb->aux = NULL; |
931 | } | |
932 | ||
7de639a2 | 933 | void |
934 | regrename_do_replace (struct du_head *head, int reg) | |
b9a06185 | 935 | { |
bb6d4603 | 936 | struct du_chain *chain; |
937 | unsigned int base_regno = head->regno; | |
7de639a2 | 938 | enum machine_mode mode; |
9845d120 | 939 | |
bb6d4603 | 940 | for (chain = head->first; chain; chain = chain->next_use) |
b9a06185 | 941 | { |
22cf44bc | 942 | unsigned int regno = ORIGINAL_REGNO (*chain->loc); |
bb6d4603 | 943 | struct reg_attrs *attr = REG_ATTRS (*chain->loc); |
41d261a4 | 944 | int reg_ptr = REG_POINTER (*chain->loc); |
83d9f776 | 945 | |
9845d120 | 946 | if (DEBUG_INSN_P (chain->insn) && REGNO (*chain->loc) != base_regno) |
947 | INSN_VAR_LOCATION_LOC (chain->insn) = gen_rtx_UNKNOWN_VAR_LOC (); | |
948 | else | |
949 | { | |
950 | *chain->loc = gen_raw_REG (GET_MODE (*chain->loc), reg); | |
951 | if (regno >= FIRST_PSEUDO_REGISTER) | |
952 | ORIGINAL_REGNO (*chain->loc) = regno; | |
953 | REG_ATTRS (*chain->loc) = attr; | |
954 | REG_POINTER (*chain->loc) = reg_ptr; | |
955 | } | |
956 | ||
b45b55a5 | 957 | df_insn_rescan (chain->insn); |
b9a06185 | 958 | } |
7de639a2 | 959 | |
960 | mode = GET_MODE (*head->first->loc); | |
961 | head->regno = reg; | |
962 | head->nregs = hard_regno_nregs[reg][mode]; | |
b9a06185 | 963 | } |
964 | ||
b9a06185 | 965 | |
7197e178 | 966 | /* True if we found a register with a size mismatch, which means that we |
967 | can't track its lifetime accurately. If so, we abort the current block | |
968 | without renaming. */ | |
969 | static bool fail_current_block; | |
970 | ||
c38fa63b | 971 | /* Return true if OP is a reg for which all bits are set in PSET, false |
972 | if all bits are clear. | |
973 | In other cases, set fail_current_block and return false. */ | |
83361a4c | 974 | |
975 | static bool | |
c38fa63b | 976 | verify_reg_in_set (rtx op, HARD_REG_SET *pset) |
83361a4c | 977 | { |
978 | unsigned regno, nregs; | |
979 | bool all_live, all_dead; | |
980 | if (!REG_P (op)) | |
981 | return false; | |
982 | ||
983 | regno = REGNO (op); | |
984 | nregs = hard_regno_nregs[regno][GET_MODE (op)]; | |
985 | all_live = all_dead = true; | |
986 | while (nregs-- > 0) | |
c38fa63b | 987 | if (TEST_HARD_REG_BIT (*pset, regno + nregs)) |
83361a4c | 988 | all_dead = false; |
989 | else | |
990 | all_live = false; | |
991 | if (!all_dead && !all_live) | |
992 | { | |
993 | fail_current_block = true; | |
994 | return false; | |
995 | } | |
c38fa63b | 996 | return all_live; |
997 | } | |
83361a4c | 998 | |
c38fa63b | 999 | /* Return true if OP is a reg that is being tracked already in some form. |
1000 | May set fail_current_block if it sees an unhandled case of overlap. */ | |
83361a4c | 1001 | |
c38fa63b | 1002 | static bool |
1003 | verify_reg_tracked (rtx op) | |
1004 | { | |
1005 | return (verify_reg_in_set (op, &live_hard_regs) | |
1006 | || verify_reg_in_set (op, &live_in_chains)); | |
83361a4c | 1007 | } |
1008 | ||
7197e178 | 1009 | /* Called through note_stores. DATA points to a rtx_code, either SET or |
1010 | CLOBBER, which tells us which kind of rtx to look at. If we have a | |
1011 | match, record the set register in live_hard_regs and in the hard_conflicts | |
1012 | bitmap of open chains. */ | |
1013 | ||
1014 | static void | |
1015 | note_sets_clobbers (rtx x, const_rtx set, void *data) | |
1016 | { | |
1017 | enum rtx_code code = *(enum rtx_code *)data; | |
1018 | struct du_head *chain; | |
1019 | ||
1020 | if (GET_CODE (x) == SUBREG) | |
1021 | x = SUBREG_REG (x); | |
1022 | if (!REG_P (x) || GET_CODE (set) != code) | |
1023 | return; | |
1024 | /* There must not be pseudos at this point. */ | |
1025 | gcc_assert (HARD_REGISTER_P (x)); | |
1026 | add_to_hard_reg_set (&live_hard_regs, GET_MODE (x), REGNO (x)); | |
1027 | for (chain = open_chains; chain; chain = chain->next_chain) | |
1028 | add_to_hard_reg_set (&chain->hard_conflicts, GET_MODE (x), REGNO (x)); | |
1029 | } | |
1030 | ||
1140e77e | 1031 | static void |
05d5500b | 1032 | scan_rtx_reg (rtx_insn *insn, rtx *loc, enum reg_class cl, enum scan_actions action, |
de67d37e | 1033 | enum op_type type) |
b9a06185 | 1034 | { |
bb6d4603 | 1035 | struct du_head **p; |
1140e77e | 1036 | rtx x = *loc; |
1037 | enum machine_mode mode = GET_MODE (x); | |
bb6d4603 | 1038 | unsigned this_regno = REGNO (x); |
31adcf56 | 1039 | int this_nregs = hard_regno_nregs[this_regno][mode]; |
1140e77e | 1040 | |
1140e77e | 1041 | if (action == mark_write) |
b9a06185 | 1042 | { |
1140e77e | 1043 | if (type == OP_OUT) |
17db414f | 1044 | create_new_chain (this_regno, this_nregs, loc, insn, cl); |
1140e77e | 1045 | return; |
b9a06185 | 1046 | } |
d98fed9f | 1047 | |
b9d576f5 | 1048 | if ((type == OP_OUT) != (action == terminate_write || action == mark_access)) |
1140e77e | 1049 | return; |
ceba8bb1 | 1050 | |
1140e77e | 1051 | for (p = &open_chains; *p;) |
ceba8bb1 | 1052 | { |
bb6d4603 | 1053 | struct du_head *head = *p; |
7197e178 | 1054 | struct du_head *next = head->next_chain; |
1055 | int exact_match = (head->regno == this_regno | |
1056 | && head->nregs == this_nregs); | |
1057 | int superset = (this_regno <= head->regno | |
1058 | && this_regno + this_nregs >= head->regno + head->nregs); | |
c38fa63b | 1059 | int subset = (this_regno >= head->regno |
1060 | && this_regno + this_nregs <= head->regno + head->nregs); | |
7197e178 | 1061 | |
8fe3bc87 | 1062 | if (!bitmap_bit_p (&open_chains_set, head->id) |
7197e178 | 1063 | || head->regno + head->nregs <= this_regno |
1064 | || this_regno + this_nregs <= head->regno) | |
1065 | { | |
1066 | p = &head->next_chain; | |
1067 | continue; | |
1068 | } | |
1140e77e | 1069 | |
7197e178 | 1070 | if (action == mark_read || action == mark_access) |
709c2f34 | 1071 | { |
7197e178 | 1072 | /* ??? Class NO_REGS can happen if the md file makes use of |
1073 | EXTRA_CONSTRAINTS to match registers. Which is arguably | |
1074 | wrong, but there we are. */ | |
77b2358d | 1075 | |
7197e178 | 1076 | if (cl == NO_REGS || (!exact_match && !DEBUG_INSN_P (insn))) |
a292cb6e | 1077 | { |
7197e178 | 1078 | if (dump_file) |
1079 | fprintf (dump_file, | |
1080 | "Cannot rename chain %s (%d) at insn %d (%s)\n", | |
1081 | reg_names[head->regno], head->id, INSN_UID (insn), | |
1082 | scan_actions_name[(int) action]); | |
1083 | head->cannot_rename = 1; | |
c38fa63b | 1084 | if (superset) |
1085 | { | |
1086 | unsigned nregs = this_nregs; | |
1087 | head->regno = this_regno; | |
1088 | head->nregs = this_nregs; | |
1089 | while (nregs-- > 0) | |
1090 | SET_HARD_REG_BIT (live_in_chains, head->regno + nregs); | |
1091 | if (dump_file) | |
1092 | fprintf (dump_file, | |
1093 | "Widening register in chain %s (%d) at insn %d\n", | |
1094 | reg_names[head->regno], head->id, INSN_UID (insn)); | |
1095 | } | |
1096 | else if (!subset) | |
1097 | { | |
1098 | fail_current_block = true; | |
1099 | if (dump_file) | |
1100 | fprintf (dump_file, | |
1101 | "Failing basic block due to unhandled overlap\n"); | |
1102 | } | |
a292cb6e | 1103 | } |
7197e178 | 1104 | else |
1140e77e | 1105 | { |
7197e178 | 1106 | struct du_chain *this_du; |
1107 | this_du = XOBNEW (&rename_obstack, struct du_chain); | |
1108 | this_du->next_use = 0; | |
1109 | this_du->loc = loc; | |
1110 | this_du->insn = insn; | |
1111 | this_du->cl = cl; | |
17db414f | 1112 | if (head->first == NULL) |
1113 | head->first = this_du; | |
1114 | else | |
1115 | head->last->next_use = this_du; | |
7de639a2 | 1116 | record_operand_use (head, this_du); |
7197e178 | 1117 | head->last = this_du; |
1140e77e | 1118 | } |
7197e178 | 1119 | /* Avoid adding the same location in a DEBUG_INSN multiple times, |
1120 | which could happen with non-exact overlap. */ | |
1121 | if (DEBUG_INSN_P (insn)) | |
1122 | return; | |
1123 | /* Otherwise, find any other chains that do not match exactly; | |
1124 | ensure they all get marked unrenamable. */ | |
1125 | p = &head->next_chain; | |
1126 | continue; | |
1127 | } | |
a292cb6e | 1128 | |
7197e178 | 1129 | /* Whether the terminated chain can be used for renaming |
1130 | depends on the action and this being an exact match. | |
1131 | In either case, we remove this element from open_chains. */ | |
77b2358d | 1132 | |
7197e178 | 1133 | if ((action == terminate_dead || action == terminate_write) |
38e1b753 | 1134 | && (superset || subset)) |
7197e178 | 1135 | { |
83361a4c | 1136 | unsigned nregs; |
1137 | ||
38e1b753 | 1138 | if (subset && !superset) |
1139 | head->cannot_rename = 1; | |
7197e178 | 1140 | bitmap_clear_bit (&open_chains_set, head->id); |
83361a4c | 1141 | |
1142 | nregs = head->nregs; | |
1143 | while (nregs-- > 0) | |
38e1b753 | 1144 | { |
1145 | CLEAR_HARD_REG_BIT (live_in_chains, head->regno + nregs); | |
1146 | if (subset && !superset | |
1147 | && (head->regno + nregs < this_regno | |
1148 | || head->regno + nregs >= this_regno + this_nregs)) | |
1149 | SET_HARD_REG_BIT (live_hard_regs, head->regno + nregs); | |
1150 | } | |
83361a4c | 1151 | |
7197e178 | 1152 | *p = next; |
1153 | if (dump_file) | |
1154 | fprintf (dump_file, | |
38e1b753 | 1155 | "Closing chain %s (%d) at insn %d (%s%s)\n", |
7197e178 | 1156 | reg_names[head->regno], head->id, INSN_UID (insn), |
38e1b753 | 1157 | scan_actions_name[(int) action], |
1158 | superset ? ", superset" : subset ? ", subset" : ""); | |
7197e178 | 1159 | } |
1160 | else if (action == terminate_dead || action == terminate_write) | |
1161 | { | |
1162 | /* In this case, tracking liveness gets too hard. Fail the | |
1163 | entire basic block. */ | |
1164 | if (dump_file) | |
1165 | fprintf (dump_file, | |
1166 | "Failing basic block due to unhandled overlap\n"); | |
1167 | fail_current_block = true; | |
1168 | return; | |
1169 | } | |
1170 | else | |
1171 | { | |
1172 | head->cannot_rename = 1; | |
1173 | if (dump_file) | |
1174 | fprintf (dump_file, | |
1175 | "Cannot rename chain %s (%d) at insn %d (%s)\n", | |
1176 | reg_names[head->regno], head->id, INSN_UID (insn), | |
1177 | scan_actions_name[(int) action]); | |
1178 | p = &head->next_chain; | |
1140e77e | 1179 | } |
1140e77e | 1180 | } |
b9a06185 | 1181 | } |
1182 | ||
e916c70c | 1183 | /* Adapted from find_reloads_address_1. CL is INDEX_REG_CLASS or |
1140e77e | 1184 | BASE_REG_CLASS depending on how the register is being considered. */ |
b9a06185 | 1185 | |
31659b75 | 1186 | static void |
05d5500b | 1187 | scan_rtx_address (rtx_insn *insn, rtx *loc, enum reg_class cl, |
f8a8fc7b | 1188 | enum scan_actions action, enum machine_mode mode, |
1189 | addr_space_t as) | |
b9a06185 | 1190 | { |
1140e77e | 1191 | rtx x = *loc; |
1192 | RTX_CODE code = GET_CODE (x); | |
1193 | const char *fmt; | |
1194 | int i, j; | |
b9a06185 | 1195 | |
b9d576f5 | 1196 | if (action == mark_write || action == mark_access) |
1140e77e | 1197 | return; |
b9a06185 | 1198 | |
1140e77e | 1199 | switch (code) |
b9a06185 | 1200 | { |
1140e77e | 1201 | case PLUS: |
1202 | { | |
1203 | rtx orig_op0 = XEXP (x, 0); | |
1204 | rtx orig_op1 = XEXP (x, 1); | |
1205 | RTX_CODE code0 = GET_CODE (orig_op0); | |
1206 | RTX_CODE code1 = GET_CODE (orig_op1); | |
1207 | rtx op0 = orig_op0; | |
1208 | rtx op1 = orig_op1; | |
1209 | rtx *locI = NULL; | |
1210 | rtx *locB = NULL; | |
260988c8 | 1211 | enum rtx_code index_code = SCRATCH; |
1140e77e | 1212 | |
1213 | if (GET_CODE (op0) == SUBREG) | |
1214 | { | |
1215 | op0 = SUBREG_REG (op0); | |
1216 | code0 = GET_CODE (op0); | |
1217 | } | |
b9a06185 | 1218 | |
1140e77e | 1219 | if (GET_CODE (op1) == SUBREG) |
1220 | { | |
1221 | op1 = SUBREG_REG (op1); | |
1222 | code1 = GET_CODE (op1); | |
1223 | } | |
b9a06185 | 1224 | |
1140e77e | 1225 | if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE |
1226 | || code0 == ZERO_EXTEND || code1 == MEM) | |
1227 | { | |
1228 | locI = &XEXP (x, 0); | |
1229 | locB = &XEXP (x, 1); | |
00cb30dc | 1230 | index_code = GET_CODE (*locI); |
1140e77e | 1231 | } |
1232 | else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE | |
1233 | || code1 == ZERO_EXTEND || code0 == MEM) | |
1234 | { | |
1235 | locI = &XEXP (x, 1); | |
1236 | locB = &XEXP (x, 0); | |
00cb30dc | 1237 | index_code = GET_CODE (*locI); |
1140e77e | 1238 | } |
1239 | else if (code0 == CONST_INT || code0 == CONST | |
1240 | || code0 == SYMBOL_REF || code0 == LABEL_REF) | |
00cb30dc | 1241 | { |
1242 | locB = &XEXP (x, 1); | |
1243 | index_code = GET_CODE (XEXP (x, 0)); | |
1244 | } | |
1140e77e | 1245 | else if (code1 == CONST_INT || code1 == CONST |
1246 | || code1 == SYMBOL_REF || code1 == LABEL_REF) | |
00cb30dc | 1247 | { |
1248 | locB = &XEXP (x, 0); | |
1249 | index_code = GET_CODE (XEXP (x, 1)); | |
1250 | } | |
1140e77e | 1251 | else if (code0 == REG && code1 == REG) |
1252 | { | |
1253 | int index_op; | |
00cb30dc | 1254 | unsigned regno0 = REGNO (op0), regno1 = REGNO (op1); |
1140e77e | 1255 | |
ce0d0c3a | 1256 | if (REGNO_OK_FOR_INDEX_P (regno1) |
f8a8fc7b | 1257 | && regno_ok_for_base_p (regno0, mode, as, PLUS, REG)) |
ce0d0c3a | 1258 | index_op = 1; |
1259 | else if (REGNO_OK_FOR_INDEX_P (regno0) | |
f8a8fc7b | 1260 | && regno_ok_for_base_p (regno1, mode, as, PLUS, REG)) |
1140e77e | 1261 | index_op = 0; |
f8a8fc7b | 1262 | else if (regno_ok_for_base_p (regno0, mode, as, PLUS, REG) |
ce0d0c3a | 1263 | || REGNO_OK_FOR_INDEX_P (regno1)) |
1140e77e | 1264 | index_op = 1; |
f8a8fc7b | 1265 | else if (regno_ok_for_base_p (regno1, mode, as, PLUS, REG)) |
1140e77e | 1266 | index_op = 0; |
1140e77e | 1267 | else |
ce0d0c3a | 1268 | index_op = 1; |
1140e77e | 1269 | |
1270 | locI = &XEXP (x, index_op); | |
00cb30dc | 1271 | locB = &XEXP (x, !index_op); |
1272 | index_code = GET_CODE (*locI); | |
1140e77e | 1273 | } |
1274 | else if (code0 == REG) | |
1275 | { | |
1276 | locI = &XEXP (x, 0); | |
1277 | locB = &XEXP (x, 1); | |
00cb30dc | 1278 | index_code = GET_CODE (*locI); |
1140e77e | 1279 | } |
1280 | else if (code1 == REG) | |
1281 | { | |
1282 | locI = &XEXP (x, 1); | |
1283 | locB = &XEXP (x, 0); | |
00cb30dc | 1284 | index_code = GET_CODE (*locI); |
1140e77e | 1285 | } |
b9a06185 | 1286 | |
1140e77e | 1287 | if (locI) |
f8a8fc7b | 1288 | scan_rtx_address (insn, locI, INDEX_REG_CLASS, action, mode, as); |
1140e77e | 1289 | if (locB) |
f8a8fc7b | 1290 | scan_rtx_address (insn, locB, |
1291 | base_reg_class (mode, as, PLUS, index_code), | |
1292 | action, mode, as); | |
00cb30dc | 1293 | |
1140e77e | 1294 | return; |
1295 | } | |
b9a06185 | 1296 | |
1140e77e | 1297 | case POST_INC: |
1298 | case POST_DEC: | |
1299 | case POST_MODIFY: | |
1300 | case PRE_INC: | |
1301 | case PRE_DEC: | |
1302 | case PRE_MODIFY: | |
1303 | #ifndef AUTO_INC_DEC | |
8f758362 | 1304 | /* If the target doesn't claim to handle autoinc, this must be |
1305 | something special, like a stack push. Kill this chain. */ | |
7197e178 | 1306 | action = mark_all_read; |
1140e77e | 1307 | #endif |
1308 | break; | |
b9a06185 | 1309 | |
1140e77e | 1310 | case MEM: |
2e6d14e8 | 1311 | scan_rtx_address (insn, &XEXP (x, 0), |
f8a8fc7b | 1312 | base_reg_class (GET_MODE (x), MEM_ADDR_SPACE (x), |
1313 | MEM, SCRATCH), | |
1314 | action, GET_MODE (x), MEM_ADDR_SPACE (x)); | |
1140e77e | 1315 | return; |
d98fed9f | 1316 | |
1140e77e | 1317 | case REG: |
de67d37e | 1318 | scan_rtx_reg (insn, loc, cl, action, OP_IN); |
31659b75 | 1319 | return; |
d98fed9f | 1320 | |
1140e77e | 1321 | default: |
1322 | break; | |
31659b75 | 1323 | } |
1140e77e | 1324 | |
1325 | fmt = GET_RTX_FORMAT (code); | |
1326 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
31659b75 | 1327 | { |
1140e77e | 1328 | if (fmt[i] == 'e') |
f8a8fc7b | 1329 | scan_rtx_address (insn, &XEXP (x, i), cl, action, mode, as); |
1140e77e | 1330 | else if (fmt[i] == 'E') |
1331 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
f8a8fc7b | 1332 | scan_rtx_address (insn, &XVECEXP (x, i, j), cl, action, mode, as); |
31659b75 | 1333 | } |
b9a06185 | 1334 | } |
1335 | ||
1140e77e | 1336 | static void |
05d5500b | 1337 | scan_rtx (rtx_insn *insn, rtx *loc, enum reg_class cl, enum scan_actions action, |
de67d37e | 1338 | enum op_type type) |
b9a06185 | 1339 | { |
1140e77e | 1340 | const char *fmt; |
1341 | rtx x = *loc; | |
1342 | enum rtx_code code = GET_CODE (x); | |
1343 | int i, j; | |
b9a06185 | 1344 | |
1140e77e | 1345 | code = GET_CODE (x); |
1346 | switch (code) | |
b9a06185 | 1347 | { |
1140e77e | 1348 | case CONST: |
0349edce | 1349 | CASE_CONST_ANY: |
1140e77e | 1350 | case SYMBOL_REF: |
1351 | case LABEL_REF: | |
1352 | case CC0: | |
1353 | case PC: | |
1354 | return; | |
22d9265e | 1355 | |
1140e77e | 1356 | case REG: |
de67d37e | 1357 | scan_rtx_reg (insn, loc, cl, action, type); |
1140e77e | 1358 | return; |
b9a06185 | 1359 | |
1140e77e | 1360 | case MEM: |
2e6d14e8 | 1361 | scan_rtx_address (insn, &XEXP (x, 0), |
f8a8fc7b | 1362 | base_reg_class (GET_MODE (x), MEM_ADDR_SPACE (x), |
1363 | MEM, SCRATCH), | |
1364 | action, GET_MODE (x), MEM_ADDR_SPACE (x)); | |
1140e77e | 1365 | return; |
b9a06185 | 1366 | |
1140e77e | 1367 | case SET: |
de67d37e | 1368 | scan_rtx (insn, &SET_SRC (x), cl, action, OP_IN); |
72ab6a85 | 1369 | scan_rtx (insn, &SET_DEST (x), cl, action, |
83361a4c | 1370 | (GET_CODE (PATTERN (insn)) == COND_EXEC |
1371 | && verify_reg_tracked (SET_DEST (x))) ? OP_INOUT : OP_OUT); | |
1140e77e | 1372 | return; |
b9a06185 | 1373 | |
1140e77e | 1374 | case STRICT_LOW_PART: |
6581d87d | 1375 | scan_rtx (insn, &XEXP (x, 0), cl, action, |
1376 | verify_reg_tracked (XEXP (x, 0)) ? OP_INOUT : OP_OUT); | |
1140e77e | 1377 | return; |
b9a06185 | 1378 | |
1140e77e | 1379 | case ZERO_EXTRACT: |
709c2f34 | 1380 | case SIGN_EXTRACT: |
e916c70c | 1381 | scan_rtx (insn, &XEXP (x, 0), cl, action, |
6581d87d | 1382 | (type == OP_IN ? OP_IN : |
1383 | verify_reg_tracked (XEXP (x, 0)) ? OP_INOUT : OP_OUT)); | |
de67d37e | 1384 | scan_rtx (insn, &XEXP (x, 1), cl, action, OP_IN); |
1385 | scan_rtx (insn, &XEXP (x, 2), cl, action, OP_IN); | |
1140e77e | 1386 | return; |
b9a06185 | 1387 | |
1140e77e | 1388 | case POST_INC: |
1389 | case PRE_INC: | |
1390 | case POST_DEC: | |
1391 | case PRE_DEC: | |
1392 | case POST_MODIFY: | |
1393 | case PRE_MODIFY: | |
1394 | /* Should only happen inside MEM. */ | |
04e579b6 | 1395 | gcc_unreachable (); |
1140e77e | 1396 | |
1397 | case CLOBBER: | |
72ab6a85 | 1398 | scan_rtx (insn, &SET_DEST (x), cl, action, |
83361a4c | 1399 | (GET_CODE (PATTERN (insn)) == COND_EXEC |
1400 | && verify_reg_tracked (SET_DEST (x))) ? OP_INOUT : OP_OUT); | |
1140e77e | 1401 | return; |
b9a06185 | 1402 | |
1140e77e | 1403 | case EXPR_LIST: |
de67d37e | 1404 | scan_rtx (insn, &XEXP (x, 0), cl, action, type); |
1140e77e | 1405 | if (XEXP (x, 1)) |
de67d37e | 1406 | scan_rtx (insn, &XEXP (x, 1), cl, action, type); |
1140e77e | 1407 | return; |
b9a06185 | 1408 | |
1140e77e | 1409 | default: |
1410 | break; | |
1411 | } | |
b9a06185 | 1412 | |
1140e77e | 1413 | fmt = GET_RTX_FORMAT (code); |
1414 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
b9a06185 | 1415 | { |
1416 | if (fmt[i] == 'e') | |
de67d37e | 1417 | scan_rtx (insn, &XEXP (x, i), cl, action, type); |
b9a06185 | 1418 | else if (fmt[i] == 'E') |
1419 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
de67d37e | 1420 | scan_rtx (insn, &XVECEXP (x, i, j), cl, action, type); |
1421 | } | |
1422 | } | |
1423 | ||
1424 | /* Hide operands of the current insn (of which there are N_OPS) by | |
1425 | substituting cc0 for them. | |
1426 | Previous values are stored in the OLD_OPERANDS and OLD_DUPS. | |
c38fa63b | 1427 | For every bit set in DO_NOT_HIDE, we leave the operand alone. |
7197e178 | 1428 | If INOUT_AND_EC_ONLY is set, we only do this for OP_INOUT type operands |
1429 | and earlyclobbers. */ | |
de67d37e | 1430 | |
1431 | static void | |
1432 | hide_operands (int n_ops, rtx *old_operands, rtx *old_dups, | |
c38fa63b | 1433 | unsigned HOST_WIDE_INT do_not_hide, bool inout_and_ec_only) |
de67d37e | 1434 | { |
1435 | int i; | |
89a7a6a5 | 1436 | const operand_alternative *op_alt = which_op_alt (); |
de67d37e | 1437 | for (i = 0; i < n_ops; i++) |
1438 | { | |
1439 | old_operands[i] = recog_data.operand[i]; | |
1440 | /* Don't squash match_operator or match_parallel here, since | |
1441 | we don't know that all of the contained registers are | |
1442 | reachable by proper operands. */ | |
1443 | if (recog_data.constraints[i][0] == '\0') | |
1444 | continue; | |
c38fa63b | 1445 | if (do_not_hide & (1 << i)) |
1446 | continue; | |
7197e178 | 1447 | if (!inout_and_ec_only || recog_data.operand_type[i] == OP_INOUT |
757fefec | 1448 | || op_alt[i].earlyclobber) |
de67d37e | 1449 | *recog_data.operand_loc[i] = cc0_rtx; |
1450 | } | |
1451 | for (i = 0; i < recog_data.n_dups; i++) | |
1452 | { | |
1453 | int opn = recog_data.dup_num[i]; | |
1454 | old_dups[i] = *recog_data.dup_loc[i]; | |
c38fa63b | 1455 | if (do_not_hide & (1 << opn)) |
1456 | continue; | |
7197e178 | 1457 | if (!inout_and_ec_only || recog_data.operand_type[opn] == OP_INOUT |
757fefec | 1458 | || op_alt[opn].earlyclobber) |
de67d37e | 1459 | *recog_data.dup_loc[i] = cc0_rtx; |
1460 | } | |
1461 | } | |
1462 | ||
1463 | /* Undo the substitution performed by hide_operands. INSN is the insn we | |
1464 | are processing; the arguments are the same as in hide_operands. */ | |
1465 | ||
1466 | static void | |
05d5500b | 1467 | restore_operands (rtx_insn *insn, int n_ops, rtx *old_operands, rtx *old_dups) |
de67d37e | 1468 | { |
1469 | int i; | |
1470 | for (i = 0; i < recog_data.n_dups; i++) | |
1471 | *recog_data.dup_loc[i] = old_dups[i]; | |
1472 | for (i = 0; i < n_ops; i++) | |
1473 | *recog_data.operand_loc[i] = old_operands[i]; | |
1474 | if (recog_data.n_dups) | |
1475 | df_insn_rescan (insn); | |
1476 | } | |
1477 | ||
1478 | /* For each output operand of INSN, call scan_rtx to create a new | |
7197e178 | 1479 | open chain. Do this only for normal or earlyclobber outputs, |
7de639a2 | 1480 | depending on EARLYCLOBBER. If INSN_INFO is nonnull, use it to |
1481 | record information about the operands in the insn. */ | |
de67d37e | 1482 | |
1483 | static void | |
05d5500b | 1484 | record_out_operands (rtx_insn *insn, bool earlyclobber, insn_rr_info *insn_info) |
de67d37e | 1485 | { |
1486 | int n_ops = recog_data.n_operands; | |
89a7a6a5 | 1487 | const operand_alternative *op_alt = which_op_alt (); |
de67d37e | 1488 | |
1489 | int i; | |
1490 | ||
1491 | for (i = 0; i < n_ops + recog_data.n_dups; i++) | |
1492 | { | |
1493 | int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops]; | |
1494 | rtx *loc = (i < n_ops | |
1495 | ? recog_data.operand_loc[opn] | |
1496 | : recog_data.dup_loc[i - n_ops]); | |
1497 | rtx op = *loc; | |
89a7a6a5 | 1498 | enum reg_class cl = alternative_class (op_alt, opn); |
de67d37e | 1499 | |
1500 | struct du_head *prev_open; | |
1501 | ||
7197e178 | 1502 | if (recog_data.operand_type[opn] != OP_OUT |
757fefec | 1503 | || op_alt[opn].earlyclobber != earlyclobber) |
de67d37e | 1504 | continue; |
1505 | ||
7de639a2 | 1506 | if (insn_info) |
1507 | cur_operand = insn_info->op_info + i; | |
1508 | ||
de67d37e | 1509 | prev_open = open_chains; |
1510 | scan_rtx (insn, loc, cl, mark_write, OP_OUT); | |
1511 | ||
1512 | /* ??? Many targets have output constraints on the SET_DEST | |
1513 | of a call insn, which is stupid, since these are certainly | |
1514 | ABI defined hard registers. For these, and for asm operands | |
1515 | that originally referenced hard registers, we must record that | |
1516 | the chain cannot be renamed. */ | |
1517 | if (CALL_P (insn) | |
1518 | || (asm_noperands (PATTERN (insn)) > 0 | |
1519 | && REG_P (op) | |
1520 | && REGNO (op) == ORIGINAL_REGNO (op))) | |
1521 | { | |
1522 | if (prev_open != open_chains) | |
7197e178 | 1523 | open_chains->cannot_rename = 1; |
de67d37e | 1524 | } |
b9a06185 | 1525 | } |
7de639a2 | 1526 | cur_operand = NULL; |
b9a06185 | 1527 | } |
1528 | ||
45498ea1 | 1529 | /* Build def/use chain. */ |
b9a06185 | 1530 | |
31adcf56 | 1531 | static bool |
3ad4992f | 1532 | build_def_use (basic_block bb) |
b9a06185 | 1533 | { |
05d5500b | 1534 | rtx_insn *insn; |
c38fa63b | 1535 | unsigned HOST_WIDE_INT untracked_operands; |
d98fed9f | 1536 | |
7197e178 | 1537 | fail_current_block = false; |
1538 | ||
5496dbfc | 1539 | for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn)) |
1140e77e | 1540 | { |
9845d120 | 1541 | if (NONDEBUG_INSN_P (insn)) |
1140e77e | 1542 | { |
1543 | int n_ops; | |
1544 | rtx note; | |
1545 | rtx old_operands[MAX_RECOG_OPERANDS]; | |
1546 | rtx old_dups[MAX_DUP_OPERANDS]; | |
f018d957 | 1547 | int i; |
1140e77e | 1548 | int predicated; |
7197e178 | 1549 | enum rtx_code set_code = SET; |
1550 | enum rtx_code clobber_code = CLOBBER; | |
7de639a2 | 1551 | insn_rr_info *insn_info = NULL; |
1140e77e | 1552 | |
1140e77e | 1553 | /* Process the insn, determining its effect on the def-use |
7197e178 | 1554 | chains and live hard registers. We perform the following |
1555 | steps with the register references in the insn, simulating | |
1556 | its effect: | |
1557 | (1) Deal with earlyclobber operands and CLOBBERs of non-operands | |
1558 | by creating chains and marking hard regs live. | |
1140e77e | 1559 | (2) Any read outside an operand causes any chain it overlaps |
7197e178 | 1560 | with to be marked unrenamable. |
1140e77e | 1561 | (3) Any read inside an operand is added if there's already |
1562 | an open chain for it. | |
1563 | (4) For any REG_DEAD note we find, close open chains that | |
1564 | overlap it. | |
7197e178 | 1565 | (5) For any non-earlyclobber write we find, close open chains |
1566 | that overlap it. | |
1567 | (6) For any non-earlyclobber write we find in an operand, make | |
1568 | a new chain or mark the hard register as live. | |
1569 | (7) For any REG_UNUSED, close any chains we just opened. | |
1570 | ||
1571 | We cannot deal with situations where we track a reg in one mode | |
1572 | and see a reference in another mode; these will cause the chain | |
1573 | to be marked unrenamable or even cause us to abort the entire | |
1574 | basic block. */ | |
1140e77e | 1575 | |
835b8178 | 1576 | extract_constrain_insn (insn); |
8eaaac4d | 1577 | preprocess_constraints (insn); |
89a7a6a5 | 1578 | const operand_alternative *op_alt = which_op_alt (); |
1140e77e | 1579 | n_ops = recog_data.n_operands; |
c38fa63b | 1580 | untracked_operands = 0; |
1140e77e | 1581 | |
f1f41a6c | 1582 | if (insn_rr.exists ()) |
7de639a2 | 1583 | { |
f1f41a6c | 1584 | insn_info = &insn_rr[INSN_UID (insn)]; |
7de639a2 | 1585 | insn_info->op_info = XOBNEWVEC (&rename_obstack, operand_rr_info, |
1586 | recog_data.n_operands); | |
1587 | memset (insn_info->op_info, 0, | |
1588 | sizeof (operand_rr_info) * recog_data.n_operands); | |
1589 | } | |
1590 | ||
89a7a6a5 | 1591 | /* Simplify the code below by promoting OP_OUT to OP_INOUT in |
83361a4c | 1592 | predicated instructions, but only for register operands |
1593 | that are already tracked, so that we can create a chain | |
1594 | when the first SET makes a register live. */ | |
1140e77e | 1595 | |
1596 | predicated = GET_CODE (PATTERN (insn)) == COND_EXEC; | |
1597 | for (i = 0; i < n_ops; ++i) | |
b9a06185 | 1598 | { |
17db414f | 1599 | rtx op = recog_data.operand[i]; |
757fefec | 1600 | int matches = op_alt[i].matches; |
757fefec | 1601 | if (matches >= 0 || op_alt[i].matched >= 0 |
17db414f | 1602 | || (predicated && recog_data.operand_type[i] == OP_OUT)) |
7197e178 | 1603 | { |
1604 | recog_data.operand_type[i] = OP_INOUT; | |
c38fa63b | 1605 | /* A special case to deal with instruction patterns that |
1606 | have matching operands with different modes. If we're | |
1607 | not already tracking such a reg, we won't start here, | |
1608 | and we must instead make sure to make the operand visible | |
1609 | to the machinery that tracks hard registers. */ | |
7197e178 | 1610 | if (matches >= 0 |
1611 | && (GET_MODE_SIZE (recog_data.operand_mode[i]) | |
c38fa63b | 1612 | != GET_MODE_SIZE (recog_data.operand_mode[matches])) |
1613 | && !verify_reg_in_set (op, &live_in_chains)) | |
1614 | { | |
1615 | untracked_operands |= 1 << i; | |
1616 | untracked_operands |= 1 << matches; | |
1617 | } | |
7197e178 | 1618 | } |
6581d87d | 1619 | /* If there's an in-out operand with a register that is not |
17db414f | 1620 | being tracked at all yet, open a chain. */ |
6581d87d | 1621 | if (recog_data.operand_type[i] == OP_INOUT |
1622 | && !(untracked_operands & (1 << i)) | |
17db414f | 1623 | && REG_P (op) |
1624 | && !verify_reg_tracked (op)) | |
6581d87d | 1625 | { |
17db414f | 1626 | enum machine_mode mode = GET_MODE (op); |
1627 | unsigned this_regno = REGNO (op); | |
1628 | unsigned this_nregs = hard_regno_nregs[this_regno][mode]; | |
05d5500b | 1629 | create_new_chain (this_regno, this_nregs, NULL, NULL, |
17db414f | 1630 | NO_REGS); |
6581d87d | 1631 | } |
b9a06185 | 1632 | } |
d98fed9f | 1633 | |
7197e178 | 1634 | if (fail_current_block) |
1635 | break; | |
1636 | ||
1637 | /* Step 1a: Mark hard registers that are clobbered in this insn, | |
1638 | outside an operand, as live. */ | |
c38fa63b | 1639 | hide_operands (n_ops, old_operands, old_dups, untracked_operands, |
1640 | false); | |
7197e178 | 1641 | note_stores (PATTERN (insn), note_sets_clobbers, &clobber_code); |
1642 | restore_operands (insn, n_ops, old_operands, old_dups); | |
1643 | ||
1644 | /* Step 1b: Begin new chains for earlyclobbered writes inside | |
1645 | operands. */ | |
7de639a2 | 1646 | record_out_operands (insn, true, insn_info); |
d98fed9f | 1647 | |
7197e178 | 1648 | /* Step 2: Mark chains for which we have reads outside operands |
1649 | as unrenamable. | |
709c2f34 | 1650 | We do this by munging all operands into CC0, and closing |
1140e77e | 1651 | everything remaining. */ |
b9a06185 | 1652 | |
c38fa63b | 1653 | hide_operands (n_ops, old_operands, old_dups, untracked_operands, |
1654 | false); | |
7197e178 | 1655 | scan_rtx (insn, &PATTERN (insn), NO_REGS, mark_all_read, OP_IN); |
de67d37e | 1656 | restore_operands (insn, n_ops, old_operands, old_dups); |
b9a06185 | 1657 | |
1140e77e | 1658 | /* Step 2B: Can't rename function call argument registers. */ |
6d7dc5b9 | 1659 | if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn)) |
1140e77e | 1660 | scan_rtx (insn, &CALL_INSN_FUNCTION_USAGE (insn), |
7197e178 | 1661 | NO_REGS, mark_all_read, OP_IN); |
b9a06185 | 1662 | |
a68730c1 | 1663 | /* Step 2C: Can't rename asm operands that were originally |
1664 | hard registers. */ | |
1665 | if (asm_noperands (PATTERN (insn)) > 0) | |
1666 | for (i = 0; i < n_ops; i++) | |
1667 | { | |
1668 | rtx *loc = recog_data.operand_loc[i]; | |
1669 | rtx op = *loc; | |
1670 | ||
8ad4c111 | 1671 | if (REG_P (op) |
a68730c1 | 1672 | && REGNO (op) == ORIGINAL_REGNO (op) |
1673 | && (recog_data.operand_type[i] == OP_IN | |
1674 | || recog_data.operand_type[i] == OP_INOUT)) | |
7197e178 | 1675 | scan_rtx (insn, loc, NO_REGS, mark_all_read, OP_IN); |
a68730c1 | 1676 | } |
1677 | ||
1140e77e | 1678 | /* Step 3: Append to chains for reads inside operands. */ |
1679 | for (i = 0; i < n_ops + recog_data.n_dups; i++) | |
1680 | { | |
1681 | int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops]; | |
1682 | rtx *loc = (i < n_ops | |
1683 | ? recog_data.operand_loc[opn] | |
1684 | : recog_data.dup_loc[i - n_ops]); | |
89a7a6a5 | 1685 | enum reg_class cl = alternative_class (op_alt, opn); |
1140e77e | 1686 | enum op_type type = recog_data.operand_type[opn]; |
1687 | ||
1688 | /* Don't scan match_operand here, since we've no reg class | |
1689 | information to pass down. Any operands that we could | |
1690 | substitute in will be represented elsewhere. */ | |
c38fa63b | 1691 | if (recog_data.constraints[opn][0] == '\0' |
1692 | || untracked_operands & (1 << opn)) | |
1140e77e | 1693 | continue; |
b9a06185 | 1694 | |
7de639a2 | 1695 | if (insn_info) |
1696 | cur_operand = i == opn ? insn_info->op_info + i : NULL; | |
757fefec | 1697 | if (op_alt[opn].is_address) |
f8a8fc7b | 1698 | scan_rtx_address (insn, loc, cl, mark_read, |
1699 | VOIDmode, ADDR_SPACE_GENERIC); | |
1140e77e | 1700 | else |
de67d37e | 1701 | scan_rtx (insn, loc, cl, mark_read, type); |
1140e77e | 1702 | } |
7de639a2 | 1703 | cur_operand = NULL; |
b9a06185 | 1704 | |
b9d576f5 | 1705 | /* Step 3B: Record updates for regs in REG_INC notes, and |
1706 | source regs in REG_FRAME_RELATED_EXPR notes. */ | |
1140e77e | 1707 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
b9d576f5 | 1708 | if (REG_NOTE_KIND (note) == REG_INC |
1709 | || REG_NOTE_KIND (note) == REG_FRAME_RELATED_EXPR) | |
1710 | scan_rtx (insn, &XEXP (note, 0), ALL_REGS, mark_read, | |
de67d37e | 1711 | OP_INOUT); |
b9d576f5 | 1712 | |
1bcf869e | 1713 | /* Step 4: Close chains for registers that die here, unless |
1714 | the register is mentioned in a REG_UNUSED note. In that | |
1715 | case we keep the chain open until step #7 below to ensure | |
1716 | it conflicts with other output operands of this insn. | |
1717 | See PR 52573. Arguably the insn should not have both | |
1718 | notes; it has proven difficult to fix that without | |
1719 | other undesirable side effects. */ | |
b9d576f5 | 1720 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
1bcf869e | 1721 | if (REG_NOTE_KIND (note) == REG_DEAD |
1722 | && !find_regno_note (insn, REG_UNUSED, REGNO (XEXP (note, 0)))) | |
7197e178 | 1723 | { |
1724 | remove_from_hard_reg_set (&live_hard_regs, | |
1725 | GET_MODE (XEXP (note, 0)), | |
1726 | REGNO (XEXP (note, 0))); | |
1727 | scan_rtx (insn, &XEXP (note, 0), NO_REGS, terminate_dead, | |
1728 | OP_IN); | |
1729 | } | |
d98fed9f | 1730 | |
1140e77e | 1731 | /* Step 4B: If this is a call, any chain live at this point |
1732 | requires a caller-saved reg. */ | |
6d7dc5b9 | 1733 | if (CALL_P (insn)) |
1140e77e | 1734 | { |
bb6d4603 | 1735 | struct du_head *p; |
1140e77e | 1736 | for (p = open_chains; p; p = p->next_chain) |
d5dfb455 | 1737 | p->need_caller_save_reg = 1; |
1140e77e | 1738 | } |
b9a06185 | 1739 | |
1140e77e | 1740 | /* Step 5: Close open chains that overlap writes. Similar to |
1741 | step 2, we hide in-out operands, since we do not want to | |
7197e178 | 1742 | close these chains. We also hide earlyclobber operands, |
1743 | since we've opened chains for them in step 1, and earlier | |
1744 | chains they would overlap with must have been closed at | |
1745 | the previous insn at the latest, as such operands cannot | |
1746 | possibly overlap with any input operands. */ | |
b9a06185 | 1747 | |
c38fa63b | 1748 | hide_operands (n_ops, old_operands, old_dups, untracked_operands, |
1749 | true); | |
de67d37e | 1750 | scan_rtx (insn, &PATTERN (insn), NO_REGS, terminate_write, OP_IN); |
1751 | restore_operands (insn, n_ops, old_operands, old_dups); | |
b9a06185 | 1752 | |
7197e178 | 1753 | /* Step 6a: Mark hard registers that are set in this insn, |
1754 | outside an operand, as live. */ | |
c38fa63b | 1755 | hide_operands (n_ops, old_operands, old_dups, untracked_operands, |
1756 | false); | |
7197e178 | 1757 | note_stores (PATTERN (insn), note_sets_clobbers, &set_code); |
1758 | restore_operands (insn, n_ops, old_operands, old_dups); | |
b9a06185 | 1759 | |
7197e178 | 1760 | /* Step 6b: Begin new chains for writes inside operands. */ |
7de639a2 | 1761 | record_out_operands (insn, false, insn_info); |
7197e178 | 1762 | |
1763 | /* Step 6c: Record destination regs in REG_FRAME_RELATED_EXPR | |
b9d576f5 | 1764 | notes for update. */ |
1765 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
1766 | if (REG_NOTE_KIND (note) == REG_FRAME_RELATED_EXPR) | |
1767 | scan_rtx (insn, &XEXP (note, 0), ALL_REGS, mark_access, | |
de67d37e | 1768 | OP_INOUT); |
b9d576f5 | 1769 | |
1140e77e | 1770 | /* Step 7: Close chains for registers that were never |
1771 | really used here. */ | |
1772 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
1773 | if (REG_NOTE_KIND (note) == REG_UNUSED) | |
7197e178 | 1774 | { |
1775 | remove_from_hard_reg_set (&live_hard_regs, | |
1776 | GET_MODE (XEXP (note, 0)), | |
1777 | REGNO (XEXP (note, 0))); | |
1778 | scan_rtx (insn, &XEXP (note, 0), NO_REGS, terminate_dead, | |
1779 | OP_IN); | |
1780 | } | |
1140e77e | 1781 | } |
9845d120 | 1782 | else if (DEBUG_INSN_P (insn) |
1783 | && !VAR_LOC_UNKNOWN_P (INSN_VAR_LOCATION_LOC (insn))) | |
1784 | { | |
1785 | scan_rtx (insn, &INSN_VAR_LOCATION_LOC (insn), | |
de67d37e | 1786 | ALL_REGS, mark_read, OP_IN); |
9845d120 | 1787 | } |
5496dbfc | 1788 | if (insn == BB_END (bb)) |
1140e77e | 1789 | break; |
1790 | } | |
b9a06185 | 1791 | |
7197e178 | 1792 | if (fail_current_block) |
31adcf56 | 1793 | return false; |
7197e178 | 1794 | |
31adcf56 | 1795 | return true; |
1140e77e | 1796 | } |
77fce4cd | 1797 | \f |
7de639a2 | 1798 | /* Initialize the register renamer. If INSN_INFO is true, ensure that |
1799 | insn_rr is nonnull. */ | |
1800 | void | |
1801 | regrename_init (bool insn_info) | |
1802 | { | |
1803 | gcc_obstack_init (&rename_obstack); | |
f1f41a6c | 1804 | insn_rr.create (0); |
7de639a2 | 1805 | if (insn_info) |
f1f41a6c | 1806 | insn_rr.safe_grow_cleared (get_max_uid ()); |
7de639a2 | 1807 | } |
1808 | ||
1809 | /* Free all global data used by the register renamer. */ | |
1810 | void | |
1811 | regrename_finish (void) | |
1812 | { | |
f1f41a6c | 1813 | insn_rr.release (); |
7de639a2 | 1814 | free_chain_data (); |
1815 | obstack_free (&rename_obstack, NULL); | |
1816 | } | |
1817 | ||
92effe69 | 1818 | /* Perform register renaming on the current function. */ |
1819 | ||
1820 | static unsigned int | |
1821 | regrename_optimize (void) | |
1822 | { | |
92effe69 | 1823 | df_set_flags (DF_LR_RUN_DCE); |
1824 | df_note_add_problem (); | |
1825 | df_analyze (); | |
1826 | df_set_flags (DF_DEFER_INSN_RESCAN); | |
1827 | ||
7de639a2 | 1828 | regrename_init (false); |
92effe69 | 1829 | |
7de639a2 | 1830 | regrename_analyze (NULL); |
92effe69 | 1831 | |
31adcf56 | 1832 | rename_chains (); |
92effe69 | 1833 | |
7de639a2 | 1834 | regrename_finish (); |
92effe69 | 1835 | |
92effe69 | 1836 | return 0; |
1837 | } | |
1838 | \f | |
cbe8bda8 | 1839 | namespace { |
1840 | ||
1841 | const pass_data pass_data_regrename = | |
77fce4cd | 1842 | { |
cbe8bda8 | 1843 | RTL_PASS, /* type */ |
1844 | "rnreg", /* name */ | |
1845 | OPTGROUP_NONE, /* optinfo_flags */ | |
cbe8bda8 | 1846 | TV_RENAME_REGISTERS, /* tv_id */ |
1847 | 0, /* properties_required */ | |
1848 | 0, /* properties_provided */ | |
1849 | 0, /* properties_destroyed */ | |
1850 | 0, /* todo_flags_start */ | |
8b88439e | 1851 | TODO_df_finish, /* todo_flags_finish */ |
3072d30e | 1852 | }; |
cbe8bda8 | 1853 | |
1854 | class pass_regrename : public rtl_opt_pass | |
1855 | { | |
1856 | public: | |
9af5ce0c | 1857 | pass_regrename (gcc::context *ctxt) |
1858 | : rtl_opt_pass (pass_data_regrename, ctxt) | |
cbe8bda8 | 1859 | {} |
1860 | ||
1861 | /* opt_pass methods: */ | |
31315c24 | 1862 | virtual bool gate (function *) |
1863 | { | |
1864 | return (optimize > 0 && (flag_rename_registers)); | |
1865 | } | |
1866 | ||
65b0537f | 1867 | virtual unsigned int execute (function *) { return regrename_optimize (); } |
cbe8bda8 | 1868 | |
1869 | }; // class pass_regrename | |
1870 | ||
1871 | } // anon namespace | |
1872 | ||
1873 | rtl_opt_pass * | |
1874 | make_pass_regrename (gcc::context *ctxt) | |
1875 | { | |
1876 | return new pass_regrename (ctxt); | |
1877 | } |