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7b82b5da | 1 | /* Register renaming for the GNU compiler. |
5624e564 | 2 | Copyright (C) 2000-2015 Free Software Foundation, Inc. |
7b82b5da | 3 | |
1322177d | 4 | This file is part of GCC. |
7b82b5da | 5 | |
1322177d LB |
6 | GCC is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by | |
9dcd6f09 | 8 | the Free Software Foundation; either version 3, or (at your option) |
7b82b5da SC |
9 | any later version. |
10 | ||
1322177d LB |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
7b82b5da SC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
7b82b5da SC |
19 | |
20 | #include "config.h" | |
21 | #include "system.h" | |
4977bab6 | 22 | #include "coretypes.h" |
c7131fb2 AM |
23 | #include "backend.h" |
24 | #include "rtl.h" | |
25 | #include "df.h" | |
0cbd9993 | 26 | #include "rtl-error.h" |
541f7d56 | 27 | #include "tm_p.h" |
7b82b5da SC |
28 | #include "insn-config.h" |
29 | #include "regs.h" | |
c4963a0a | 30 | #include "addresses.h" |
60393bbc | 31 | #include "cfganal.h" |
60393bbc AM |
32 | #include "reload.h" |
33 | #include "output.h" | |
7b82b5da | 34 | #include "recog.h" |
541f7d56 BS |
35 | #include "flags.h" |
36 | #include "obstack.h" | |
ef330312 | 37 | #include "tree-pass.h" |
5f286f4a | 38 | #include "target.h" |
1f234b83 BS |
39 | #include "emit-rtl.h" |
40 | #include "regrename.h" | |
541f7d56 | 41 | |
6656b2ac EB |
42 | /* This file implements the RTL register renaming pass of the compiler. It is |
43 | a semi-local pass whose goal is to maximize the usage of the register file | |
44 | of the processor by substituting registers for others in the solution given | |
45 | by the register allocator. The algorithm is as follows: | |
46 | ||
47 | 1. Local def/use chains are built: within each basic block, chains are | |
48 | opened and closed; if a chain isn't closed at the end of the block, | |
8ffa0351 BS |
49 | it is dropped. We pre-open chains if we have already examined a |
50 | predecessor block and found chains live at the end which match | |
51 | live registers at the start of the new block. | |
6656b2ac | 52 | |
8ffa0351 BS |
53 | 2. We try to combine the local chains across basic block boundaries by |
54 | comparing chains that were open at the start or end of a block to | |
55 | those in successor/predecessor blocks. | |
56 | ||
57 | 3. For each chain, the set of possible renaming registers is computed. | |
6656b2ac EB |
58 | This takes into account the renaming of previously processed chains. |
59 | Optionally, a preferred class is computed for the renaming register. | |
60 | ||
8ffa0351 | 61 | 4. The best renaming register is computed for the chain in the above set, |
6656b2ac EB |
62 | using a round-robin allocation. If a preferred class exists, then the |
63 | round-robin allocation is done within the class first, if possible. | |
64 | The round-robin allocation of renaming registers itself is global. | |
65 | ||
8ffa0351 | 66 | 5. If a renaming register has been found, it is substituted in the chain. |
6656b2ac EB |
67 | |
68 | Targets can parameterize the pass by specifying a preferred class for the | |
69 | renaming register for a given (super)class of registers to be renamed. */ | |
70 | ||
d435810e BS |
71 | #if HOST_BITS_PER_WIDE_INT <= MAX_RECOG_OPERANDS |
72 | #error "Use a different bitmap implementation for untracked_operands." | |
73 | #endif | |
6656b2ac | 74 | |
541f7d56 BS |
75 | enum scan_actions |
76 | { | |
541f7d56 BS |
77 | terminate_write, |
78 | terminate_dead, | |
a96caf80 | 79 | mark_all_read, |
541f7d56 | 80 | mark_read, |
cb110f3d AM |
81 | mark_write, |
82 | /* mark_access is for marking the destination regs in | |
83 | REG_FRAME_RELATED_EXPR notes (as if they were read) so that the | |
84 | note is updated properly. */ | |
85 | mark_access | |
541f7d56 BS |
86 | }; |
87 | ||
88 | static const char * const scan_actions_name[] = | |
89 | { | |
541f7d56 BS |
90 | "terminate_write", |
91 | "terminate_dead", | |
a96caf80 | 92 | "mark_all_read", |
541f7d56 | 93 | "mark_read", |
cb110f3d AM |
94 | "mark_write", |
95 | "mark_access" | |
541f7d56 BS |
96 | }; |
97 | ||
d3e80850 BS |
98 | /* TICK and THIS_TICK are used to record the last time we saw each |
99 | register. */ | |
100 | static int tick[FIRST_PSEUDO_REGISTER]; | |
101 | static int this_tick = 0; | |
102 | ||
541f7d56 BS |
103 | static struct obstack rename_obstack; |
104 | ||
1f234b83 BS |
105 | /* If nonnull, the code calling into the register renamer requested |
106 | information about insn operands, and we store it here. */ | |
9771b263 | 107 | vec<insn_rr_info> insn_rr; |
1f234b83 | 108 | |
a755f004 | 109 | static void scan_rtx (rtx_insn *, rtx *, enum reg_class, enum scan_actions, |
6bda9bdf | 110 | enum op_type); |
8ffa0351 | 111 | static bool build_def_use (basic_block); |
fe08a886 | 112 | |
d3e80850 BS |
113 | /* The id to be given to the next opened chain. */ |
114 | static unsigned current_id; | |
115 | ||
116 | /* A mapping of unique id numbers to chains. */ | |
9771b263 | 117 | static vec<du_head_p> id_to_chain; |
fe08a886 | 118 | |
8ffa0351 | 119 | /* List of currently open chains. */ |
d3e80850 | 120 | static struct du_head *open_chains; |
d3e80850 BS |
121 | |
122 | /* Bitmap of open chains. The bits set always match the list found in | |
123 | open_chains. */ | |
124 | static bitmap_head open_chains_set; | |
125 | ||
126 | /* Record the registers being tracked in open_chains. */ | |
127 | static HARD_REG_SET live_in_chains; | |
128 | ||
129 | /* Record the registers that are live but not tracked. The intersection | |
130 | between this and live_in_chains is empty. */ | |
131 | static HARD_REG_SET live_hard_regs; | |
132 | ||
1f234b83 BS |
133 | /* Set while scanning RTL if INSN_RR is nonnull, i.e. if the current analysis |
134 | is for a caller that requires operand data. Used in | |
135 | record_operand_use. */ | |
136 | static operand_rr_info *cur_operand; | |
137 | ||
8ffa0351 BS |
138 | /* Return the chain corresponding to id number ID. Take into account that |
139 | chains may have been merged. */ | |
1f234b83 BS |
140 | du_head_p |
141 | regrename_chain_from_id (unsigned int id) | |
8ffa0351 | 142 | { |
9771b263 | 143 | du_head_p first_chain = id_to_chain[id]; |
8ffa0351 BS |
144 | du_head_p chain = first_chain; |
145 | while (chain->id != id) | |
146 | { | |
147 | id = chain->id; | |
9771b263 | 148 | chain = id_to_chain[id]; |
8ffa0351 BS |
149 | } |
150 | first_chain->id = id; | |
151 | return chain; | |
152 | } | |
153 | ||
154 | /* Dump all def/use chains, starting at id FROM. */ | |
d3e80850 BS |
155 | |
156 | static void | |
8ffa0351 | 157 | dump_def_use_chain (int from) |
d3e80850 | 158 | { |
8ffa0351 BS |
159 | du_head_p head; |
160 | int i; | |
9771b263 | 161 | FOR_EACH_VEC_ELT_FROM (id_to_chain, i, head, from) |
d3e80850 BS |
162 | { |
163 | struct du_chain *this_du = head->first; | |
8ffa0351 | 164 | |
d3e80850 BS |
165 | fprintf (dump_file, "Register %s (%d):", |
166 | reg_names[head->regno], head->nregs); | |
167 | while (this_du) | |
168 | { | |
169 | fprintf (dump_file, " %d [%s]", INSN_UID (this_du->insn), | |
170 | reg_class_names[this_du->cl]); | |
171 | this_du = this_du->next_use; | |
172 | } | |
173 | fprintf (dump_file, "\n"); | |
174 | head = head->next_chain; | |
175 | } | |
176 | } | |
177 | ||
fe08a886 | 178 | static void |
a96caf80 | 179 | free_chain_data (void) |
fe08a886 | 180 | { |
a96caf80 BS |
181 | int i; |
182 | du_head_p ptr; | |
9771b263 | 183 | for (i = 0; id_to_chain.iterate (i, &ptr); i++) |
a96caf80 | 184 | bitmap_clear (&ptr->conflicts); |
226c62c7 | 185 | |
9771b263 | 186 | id_to_chain.release (); |
fe08a886 BS |
187 | } |
188 | ||
f24acbef BS |
189 | /* Walk all chains starting with CHAINS and record that they conflict with |
190 | another chain whose id is ID. */ | |
191 | ||
192 | static void | |
193 | mark_conflict (struct du_head *chains, unsigned id) | |
194 | { | |
195 | while (chains) | |
196 | { | |
197 | bitmap_set_bit (&chains->conflicts, id); | |
198 | chains = chains->next_chain; | |
199 | } | |
200 | } | |
201 | ||
1f234b83 BS |
202 | /* Examine cur_operand, and if it is nonnull, record information about the |
203 | use THIS_DU which is part of the chain HEAD. */ | |
204 | ||
205 | static void | |
206 | record_operand_use (struct du_head *head, struct du_chain *this_du) | |
207 | { | |
208 | if (cur_operand == NULL) | |
209 | return; | |
210 | gcc_assert (cur_operand->n_chains < MAX_REGS_PER_ADDRESS); | |
211 | cur_operand->heads[cur_operand->n_chains] = head; | |
212 | cur_operand->chains[cur_operand->n_chains++] = this_du; | |
213 | } | |
214 | ||
f24acbef BS |
215 | /* Create a new chain for THIS_NREGS registers starting at THIS_REGNO, |
216 | and record its occurrence in *LOC, which is being written to in INSN. | |
217 | This access requires a register of class CL. */ | |
218 | ||
8ffa0351 | 219 | static du_head_p |
f24acbef | 220 | create_new_chain (unsigned this_regno, unsigned this_nregs, rtx *loc, |
a755f004 | 221 | rtx_insn *insn, enum reg_class cl) |
f24acbef BS |
222 | { |
223 | struct du_head *head = XOBNEW (&rename_obstack, struct du_head); | |
224 | struct du_chain *this_du; | |
225 | int nregs; | |
226 | ||
227 | head->next_chain = open_chains; | |
f24acbef BS |
228 | head->regno = this_regno; |
229 | head->nregs = this_nregs; | |
230 | head->need_caller_save_reg = 0; | |
231 | head->cannot_rename = 0; | |
232 | ||
9771b263 | 233 | id_to_chain.safe_push (head); |
f24acbef BS |
234 | head->id = current_id++; |
235 | ||
236 | bitmap_initialize (&head->conflicts, &bitmap_default_obstack); | |
237 | bitmap_copy (&head->conflicts, &open_chains_set); | |
238 | mark_conflict (open_chains, head->id); | |
239 | ||
240 | /* Since we're tracking this as a chain now, remove it from the | |
241 | list of conflicting live hard registers and track it in | |
242 | live_in_chains instead. */ | |
243 | nregs = head->nregs; | |
244 | while (nregs-- > 0) | |
245 | { | |
246 | SET_HARD_REG_BIT (live_in_chains, head->regno + nregs); | |
247 | CLEAR_HARD_REG_BIT (live_hard_regs, head->regno + nregs); | |
248 | } | |
249 | ||
250 | COPY_HARD_REG_SET (head->hard_conflicts, live_hard_regs); | |
251 | bitmap_set_bit (&open_chains_set, head->id); | |
252 | ||
253 | open_chains = head; | |
254 | ||
255 | if (dump_file) | |
256 | { | |
257 | fprintf (dump_file, "Creating chain %s (%d)", | |
258 | reg_names[head->regno], head->id); | |
259 | if (insn != NULL_RTX) | |
260 | fprintf (dump_file, " at insn %d", INSN_UID (insn)); | |
261 | fprintf (dump_file, "\n"); | |
262 | } | |
263 | ||
264 | if (insn == NULL_RTX) | |
265 | { | |
266 | head->first = head->last = NULL; | |
8ffa0351 | 267 | return head; |
f24acbef BS |
268 | } |
269 | ||
270 | this_du = XOBNEW (&rename_obstack, struct du_chain); | |
271 | head->first = head->last = this_du; | |
272 | ||
273 | this_du->next_use = 0; | |
274 | this_du->loc = loc; | |
275 | this_du->insn = insn; | |
276 | this_du->cl = cl; | |
1f234b83 | 277 | record_operand_use (head, this_du); |
8ffa0351 | 278 | return head; |
f24acbef BS |
279 | } |
280 | ||
a96caf80 BS |
281 | /* For a def-use chain HEAD, find which registers overlap its lifetime and |
282 | set the corresponding bits in *PSET. */ | |
fe08a886 BS |
283 | |
284 | static void | |
a96caf80 | 285 | merge_overlapping_regs (HARD_REG_SET *pset, struct du_head *head) |
fe08a886 | 286 | { |
a96caf80 BS |
287 | bitmap_iterator bi; |
288 | unsigned i; | |
289 | IOR_HARD_REG_SET (*pset, head->hard_conflicts); | |
290 | EXECUTE_IF_SET_IN_BITMAP (&head->conflicts, 0, i, bi) | |
32fc3abf | 291 | { |
1f234b83 | 292 | du_head_p other = regrename_chain_from_id (i); |
a96caf80 | 293 | unsigned j = other->nregs; |
8ffa0351 | 294 | gcc_assert (other != head); |
a96caf80 BS |
295 | while (j-- > 0) |
296 | SET_HARD_REG_BIT (*pset, other->regno + j); | |
fe08a886 BS |
297 | } |
298 | } | |
299 | ||
5f286f4a YQ |
300 | /* Check if NEW_REG can be the candidate register to rename for |
301 | REG in THIS_HEAD chain. THIS_UNAVAILABLE is a set of unavailable hard | |
302 | registers. */ | |
303 | ||
304 | static bool | |
6a68a5c3 JJ |
305 | check_new_reg_p (int reg ATTRIBUTE_UNUSED, int new_reg, |
306 | struct du_head *this_head, HARD_REG_SET this_unavailable) | |
5f286f4a | 307 | { |
ef4bddc2 | 308 | machine_mode mode = GET_MODE (*this_head->first->loc); |
5f286f4a YQ |
309 | int nregs = hard_regno_nregs[new_reg][mode]; |
310 | int i; | |
311 | struct du_chain *tmp; | |
312 | ||
313 | for (i = nregs - 1; i >= 0; --i) | |
314 | if (TEST_HARD_REG_BIT (this_unavailable, new_reg + i) | |
315 | || fixed_regs[new_reg + i] | |
316 | || global_regs[new_reg + i] | |
317 | /* Can't use regs which aren't saved by the prologue. */ | |
318 | || (! df_regs_ever_live_p (new_reg + i) | |
319 | && ! call_used_regs[new_reg + i]) | |
320 | #ifdef LEAF_REGISTERS | |
321 | /* We can't use a non-leaf register if we're in a | |
322 | leaf function. */ | |
416ff32e | 323 | || (crtl->is_leaf |
5f286f4a YQ |
324 | && !LEAF_REGISTERS[new_reg + i]) |
325 | #endif | |
aedf2c02 | 326 | || ! HARD_REGNO_RENAME_OK (reg + i, new_reg + i)) |
5f286f4a YQ |
327 | return false; |
328 | ||
329 | /* See whether it accepts all modes that occur in | |
330 | definition and uses. */ | |
331 | for (tmp = this_head->first; tmp; tmp = tmp->next_use) | |
332 | if ((! HARD_REGNO_MODE_OK (new_reg, GET_MODE (*tmp->loc)) | |
333 | && ! DEBUG_INSN_P (tmp->insn)) | |
334 | || (this_head->need_caller_save_reg | |
335 | && ! (HARD_REGNO_CALL_PART_CLOBBERED | |
336 | (reg, GET_MODE (*tmp->loc))) | |
337 | && (HARD_REGNO_CALL_PART_CLOBBERED | |
338 | (new_reg, GET_MODE (*tmp->loc))))) | |
339 | return false; | |
340 | ||
341 | return true; | |
342 | } | |
343 | ||
1f234b83 BS |
344 | /* For the chain THIS_HEAD, compute and return the best register to |
345 | rename to. SUPER_CLASS is the superunion of register classes in | |
346 | the chain. UNAVAILABLE is a set of registers that cannot be used. | |
63edbb04 TP |
347 | OLD_REG is the register currently used for the chain. BEST_RENAME |
348 | controls whether the register chosen must be better than the | |
349 | current one or just respect the given constraint. */ | |
1f234b83 BS |
350 | |
351 | int | |
63edbb04 TP |
352 | find_rename_reg (du_head_p this_head, enum reg_class super_class, |
353 | HARD_REG_SET *unavailable, int old_reg, bool best_rename) | |
1f234b83 BS |
354 | { |
355 | bool has_preferred_class; | |
356 | enum reg_class preferred_class; | |
357 | int pass; | |
358 | int best_new_reg = old_reg; | |
359 | ||
360 | /* Further narrow the set of registers we can use for renaming. | |
361 | If the chain needs a call-saved register, mark the call-used | |
362 | registers as unavailable. */ | |
363 | if (this_head->need_caller_save_reg) | |
364 | IOR_HARD_REG_SET (*unavailable, call_used_reg_set); | |
365 | ||
366 | /* Mark registers that overlap this chain's lifetime as unavailable. */ | |
367 | merge_overlapping_regs (unavailable, this_head); | |
368 | ||
369 | /* Compute preferred rename class of super union of all the classes | |
370 | in the chain. */ | |
371 | preferred_class | |
372 | = (enum reg_class) targetm.preferred_rename_class (super_class); | |
373 | ||
374 | /* If PREFERRED_CLASS is not NO_REGS, we iterate in the first pass | |
375 | over registers that belong to PREFERRED_CLASS and try to find the | |
376 | best register within the class. If that failed, we iterate in | |
377 | the second pass over registers that don't belong to the class. | |
378 | If PREFERRED_CLASS is NO_REGS, we iterate over all registers in | |
379 | ascending order without any preference. */ | |
380 | has_preferred_class = (preferred_class != NO_REGS); | |
381 | for (pass = (has_preferred_class ? 0 : 1); pass < 2; pass++) | |
382 | { | |
383 | int new_reg; | |
384 | for (new_reg = 0; new_reg < FIRST_PSEUDO_REGISTER; new_reg++) | |
385 | { | |
386 | if (has_preferred_class | |
387 | && (pass == 0) | |
388 | != TEST_HARD_REG_BIT (reg_class_contents[preferred_class], | |
389 | new_reg)) | |
390 | continue; | |
391 | ||
63edbb04 TP |
392 | if (!check_new_reg_p (old_reg, new_reg, this_head, *unavailable)) |
393 | continue; | |
394 | ||
395 | if (!best_rename) | |
396 | return new_reg; | |
397 | ||
1f234b83 BS |
398 | /* In the first pass, we force the renaming of registers that |
399 | don't belong to PREFERRED_CLASS to registers that do, even | |
400 | though the latters were used not very long ago. */ | |
63edbb04 TP |
401 | if ((pass == 0 |
402 | && !TEST_HARD_REG_BIT (reg_class_contents[preferred_class], | |
403 | best_new_reg)) | |
404 | || tick[best_new_reg] > tick[new_reg]) | |
1f234b83 BS |
405 | best_new_reg = new_reg; |
406 | } | |
407 | if (pass == 0 && best_new_reg != old_reg) | |
408 | break; | |
409 | } | |
410 | return best_new_reg; | |
411 | } | |
412 | ||
8ffa0351 | 413 | /* Perform register renaming on the current function. */ |
d3e80850 | 414 | static void |
8ffa0351 | 415 | rename_chains (void) |
d3e80850 BS |
416 | { |
417 | HARD_REG_SET unavailable; | |
8ffa0351 BS |
418 | du_head_p this_head; |
419 | int i; | |
420 | ||
421 | memset (tick, 0, sizeof tick); | |
d3e80850 BS |
422 | |
423 | CLEAR_HARD_REG_SET (unavailable); | |
424 | /* Don't clobber traceback for noreturn functions. */ | |
425 | if (frame_pointer_needed) | |
426 | { | |
427 | add_to_hard_reg_set (&unavailable, Pmode, FRAME_POINTER_REGNUM); | |
c3e08036 TS |
428 | if (!HARD_FRAME_POINTER_IS_FRAME_POINTER) |
429 | add_to_hard_reg_set (&unavailable, Pmode, HARD_FRAME_POINTER_REGNUM); | |
d3e80850 BS |
430 | } |
431 | ||
9771b263 | 432 | FOR_EACH_VEC_ELT (id_to_chain, i, this_head) |
d3e80850 | 433 | { |
1f234b83 | 434 | int best_new_reg; |
d3e80850 | 435 | int n_uses; |
d3e80850 BS |
436 | struct du_chain *tmp; |
437 | HARD_REG_SET this_unavailable; | |
438 | int reg = this_head->regno; | |
d3e80850 | 439 | enum reg_class super_class = NO_REGS; |
d3e80850 | 440 | |
d3e80850 BS |
441 | if (this_head->cannot_rename) |
442 | continue; | |
443 | ||
d3e80850 BS |
444 | if (fixed_regs[reg] || global_regs[reg] |
445 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER | |
446 | || (frame_pointer_needed && reg == HARD_FRAME_POINTER_REGNUM) | |
447 | #else | |
448 | || (frame_pointer_needed && reg == FRAME_POINTER_REGNUM) | |
449 | #endif | |
450 | ) | |
451 | continue; | |
452 | ||
453 | COPY_HARD_REG_SET (this_unavailable, unavailable); | |
454 | ||
455 | /* Iterate over elements in the chain in order to: | |
456 | 1. Count number of uses, and narrow the set of registers we can | |
457 | use for renaming. | |
458 | 2. Compute the superunion of register classes in this chain. */ | |
459 | n_uses = 0; | |
460 | super_class = NO_REGS; | |
461 | for (tmp = this_head->first; tmp; tmp = tmp->next_use) | |
462 | { | |
463 | if (DEBUG_INSN_P (tmp->insn)) | |
464 | continue; | |
465 | n_uses++; | |
466 | IOR_COMPL_HARD_REG_SET (this_unavailable, | |
467 | reg_class_contents[tmp->cl]); | |
468 | super_class | |
469 | = reg_class_superunion[(int) super_class][(int) tmp->cl]; | |
470 | } | |
471 | ||
472 | if (n_uses < 2) | |
473 | continue; | |
474 | ||
63edbb04 TP |
475 | best_new_reg = find_rename_reg (this_head, super_class, |
476 | &this_unavailable, reg, true); | |
d3e80850 BS |
477 | |
478 | if (dump_file) | |
479 | { | |
480 | fprintf (dump_file, "Register %s in insn %d", | |
481 | reg_names[reg], INSN_UID (this_head->first->insn)); | |
482 | if (this_head->need_caller_save_reg) | |
483 | fprintf (dump_file, " crosses a call"); | |
484 | } | |
485 | ||
486 | if (best_new_reg == reg) | |
487 | { | |
488 | tick[reg] = ++this_tick; | |
489 | if (dump_file) | |
490 | fprintf (dump_file, "; no available better choice\n"); | |
491 | continue; | |
492 | } | |
493 | ||
17369fbf CLT |
494 | if (regrename_do_replace (this_head, best_new_reg)) |
495 | { | |
496 | if (dump_file) | |
497 | fprintf (dump_file, ", renamed as %s\n", reg_names[best_new_reg]); | |
498 | tick[best_new_reg] = ++this_tick; | |
499 | df_set_regs_ever_live (best_new_reg, true); | |
500 | } | |
501 | else | |
502 | { | |
503 | if (dump_file) | |
504 | fprintf (dump_file, ", renaming as %s failed\n", | |
505 | reg_names[best_new_reg]); | |
506 | tick[reg] = ++this_tick; | |
507 | } | |
d3e80850 BS |
508 | } |
509 | } | |
510 | ||
8ffa0351 BS |
511 | /* A structure to record information for each hard register at the start of |
512 | a basic block. */ | |
513 | struct incoming_reg_info { | |
514 | /* Holds the number of registers used in the chain that gave us information | |
515 | about this register. Zero means no information known yet, while a | |
516 | negative value is used for something that is part of, but not the first | |
517 | register in a multi-register value. */ | |
518 | int nregs; | |
519 | /* Set to true if we have accesses that conflict in the number of registers | |
520 | used. */ | |
521 | bool unusable; | |
522 | }; | |
523 | ||
524 | /* A structure recording information about each basic block. It is saved | |
525 | and restored around basic block boundaries. | |
526 | A pointer to such a structure is stored in each basic block's aux field | |
527 | during regrename_analyze, except for blocks we know can't be optimized | |
528 | (such as entry and exit blocks). */ | |
529 | struct bb_rename_info | |
530 | { | |
531 | /* The basic block corresponding to this structure. */ | |
532 | basic_block bb; | |
533 | /* Copies of the global information. */ | |
534 | bitmap_head open_chains_set; | |
535 | bitmap_head incoming_open_chains_set; | |
536 | struct incoming_reg_info incoming[FIRST_PSEUDO_REGISTER]; | |
537 | }; | |
538 | ||
539 | /* Initialize a rename_info structure P for basic block BB, which starts a new | |
540 | scan. */ | |
541 | static void | |
542 | init_rename_info (struct bb_rename_info *p, basic_block bb) | |
543 | { | |
544 | int i; | |
292321a5 | 545 | df_ref def; |
8ffa0351 BS |
546 | HARD_REG_SET start_chains_set; |
547 | ||
548 | p->bb = bb; | |
549 | bitmap_initialize (&p->open_chains_set, &bitmap_default_obstack); | |
550 | bitmap_initialize (&p->incoming_open_chains_set, &bitmap_default_obstack); | |
551 | ||
552 | open_chains = NULL; | |
553 | bitmap_clear (&open_chains_set); | |
554 | ||
555 | CLEAR_HARD_REG_SET (live_in_chains); | |
556 | REG_SET_TO_HARD_REG_SET (live_hard_regs, df_get_live_in (bb)); | |
292321a5 RS |
557 | FOR_EACH_ARTIFICIAL_DEF (def, bb->index) |
558 | if (DF_REF_FLAGS (def) & DF_REF_AT_TOP) | |
559 | SET_HARD_REG_BIT (live_hard_regs, DF_REF_REGNO (def)); | |
8ffa0351 BS |
560 | |
561 | /* Open chains based on information from (at least one) predecessor | |
562 | block. This gives us a chance later on to combine chains across | |
563 | basic block boundaries. Inconsistencies (in access sizes) will | |
564 | be caught normally and dealt with conservatively by disabling the | |
565 | chain for renaming, and there is no risk of losing optimization | |
566 | opportunities by opening chains either: if we did not open the | |
567 | chains, we'd have to track the live register as a hard reg, and | |
568 | we'd be unable to rename it in any case. */ | |
569 | CLEAR_HARD_REG_SET (start_chains_set); | |
570 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
571 | { | |
572 | struct incoming_reg_info *iri = p->incoming + i; | |
573 | if (iri->nregs > 0 && !iri->unusable | |
574 | && range_in_hard_reg_set_p (live_hard_regs, i, iri->nregs)) | |
575 | { | |
576 | SET_HARD_REG_BIT (start_chains_set, i); | |
577 | remove_range_from_hard_reg_set (&live_hard_regs, i, iri->nregs); | |
578 | } | |
579 | } | |
580 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
581 | { | |
582 | struct incoming_reg_info *iri = p->incoming + i; | |
583 | if (TEST_HARD_REG_BIT (start_chains_set, i)) | |
584 | { | |
585 | du_head_p chain; | |
586 | if (dump_file) | |
587 | fprintf (dump_file, "opening incoming chain\n"); | |
a755f004 | 588 | chain = create_new_chain (i, iri->nregs, NULL, NULL, NO_REGS); |
8ffa0351 BS |
589 | bitmap_set_bit (&p->incoming_open_chains_set, chain->id); |
590 | } | |
591 | } | |
592 | } | |
593 | ||
594 | /* Record in RI that the block corresponding to it has an incoming | |
595 | live value, described by CHAIN. */ | |
596 | static void | |
597 | set_incoming_from_chain (struct bb_rename_info *ri, du_head_p chain) | |
598 | { | |
599 | int i; | |
600 | int incoming_nregs = ri->incoming[chain->regno].nregs; | |
601 | int nregs; | |
602 | ||
603 | /* If we've recorded the same information before, everything is fine. */ | |
604 | if (incoming_nregs == chain->nregs) | |
605 | { | |
606 | if (dump_file) | |
607 | fprintf (dump_file, "reg %d/%d already recorded\n", | |
608 | chain->regno, chain->nregs); | |
609 | return; | |
610 | } | |
611 | ||
612 | /* If we have no information for any of the involved registers, update | |
613 | the incoming array. */ | |
614 | nregs = chain->nregs; | |
615 | while (nregs-- > 0) | |
616 | if (ri->incoming[chain->regno + nregs].nregs != 0 | |
617 | || ri->incoming[chain->regno + nregs].unusable) | |
618 | break; | |
619 | if (nregs < 0) | |
620 | { | |
621 | nregs = chain->nregs; | |
622 | ri->incoming[chain->regno].nregs = nregs; | |
623 | while (nregs-- > 1) | |
624 | ri->incoming[chain->regno + nregs].nregs = -nregs; | |
625 | if (dump_file) | |
626 | fprintf (dump_file, "recorded reg %d/%d\n", | |
627 | chain->regno, chain->nregs); | |
628 | return; | |
629 | } | |
630 | ||
631 | /* There must be some kind of conflict. Prevent both the old and | |
632 | new ranges from being used. */ | |
633 | if (incoming_nregs < 0) | |
634 | ri->incoming[chain->regno + incoming_nregs].unusable = true; | |
635 | for (i = 0; i < chain->nregs; i++) | |
636 | ri->incoming[chain->regno + i].unusable = true; | |
637 | } | |
638 | ||
639 | /* Merge the two chains C1 and C2 so that all conflict information is | |
640 | recorded and C1, and the id of C2 is changed to that of C1. */ | |
641 | static void | |
642 | merge_chains (du_head_p c1, du_head_p c2) | |
643 | { | |
644 | if (c1 == c2) | |
645 | return; | |
646 | ||
647 | if (c2->first != NULL) | |
648 | { | |
649 | if (c1->first == NULL) | |
650 | c1->first = c2->first; | |
651 | else | |
652 | c1->last->next_use = c2->first; | |
653 | c1->last = c2->last; | |
654 | } | |
655 | ||
656 | c2->first = c2->last = NULL; | |
657 | c2->id = c1->id; | |
658 | ||
659 | IOR_HARD_REG_SET (c1->hard_conflicts, c2->hard_conflicts); | |
660 | bitmap_ior_into (&c1->conflicts, &c2->conflicts); | |
661 | ||
662 | c1->need_caller_save_reg |= c2->need_caller_save_reg; | |
663 | c1->cannot_rename |= c2->cannot_rename; | |
664 | } | |
665 | ||
666 | /* Analyze the current function and build chains for renaming. */ | |
667 | ||
1f234b83 BS |
668 | void |
669 | regrename_analyze (bitmap bb_mask) | |
8ffa0351 BS |
670 | { |
671 | struct bb_rename_info *rename_info; | |
672 | int i; | |
673 | basic_block bb; | |
674 | int n_bbs; | |
675 | int *inverse_postorder; | |
676 | ||
8b1c6fd7 | 677 | inverse_postorder = XNEWVEC (int, last_basic_block_for_fn (cfun)); |
8ffa0351 BS |
678 | n_bbs = pre_and_rev_post_order_compute (NULL, inverse_postorder, false); |
679 | ||
680 | /* Gather some information about the blocks in this function. */ | |
0cae8d31 | 681 | rename_info = XCNEWVEC (struct bb_rename_info, n_basic_blocks_for_fn (cfun)); |
8ffa0351 | 682 | i = 0; |
11cd3bed | 683 | FOR_EACH_BB_FN (bb, cfun) |
8ffa0351 BS |
684 | { |
685 | struct bb_rename_info *ri = rename_info + i; | |
686 | ri->bb = bb; | |
1f234b83 BS |
687 | if (bb_mask != NULL && !bitmap_bit_p (bb_mask, bb->index)) |
688 | bb->aux = NULL; | |
689 | else | |
690 | bb->aux = ri; | |
8ffa0351 BS |
691 | i++; |
692 | } | |
693 | ||
694 | current_id = 0; | |
9771b263 | 695 | id_to_chain.create (0); |
8ffa0351 BS |
696 | bitmap_initialize (&open_chains_set, &bitmap_default_obstack); |
697 | ||
698 | /* The order in which we visit blocks ensures that whenever | |
699 | possible, we only process a block after at least one of its | |
700 | predecessors, which provides a "seeding" effect to make the logic | |
701 | in set_incoming_from_chain and init_rename_info useful. */ | |
702 | ||
703 | for (i = 0; i < n_bbs; i++) | |
704 | { | |
06e28de2 | 705 | basic_block bb1 = BASIC_BLOCK_FOR_FN (cfun, inverse_postorder[i]); |
8ffa0351 BS |
706 | struct bb_rename_info *this_info; |
707 | bool success; | |
708 | edge e; | |
709 | edge_iterator ei; | |
9771b263 | 710 | int old_length = id_to_chain.length (); |
8ffa0351 BS |
711 | |
712 | this_info = (struct bb_rename_info *) bb1->aux; | |
713 | if (this_info == NULL) | |
714 | continue; | |
715 | ||
716 | if (dump_file) | |
717 | fprintf (dump_file, "\nprocessing block %d:\n", bb1->index); | |
718 | ||
719 | init_rename_info (this_info, bb1); | |
720 | ||
721 | success = build_def_use (bb1); | |
722 | if (!success) | |
723 | { | |
724 | if (dump_file) | |
725 | fprintf (dump_file, "failed\n"); | |
726 | bb1->aux = NULL; | |
9771b263 | 727 | id_to_chain.truncate (old_length); |
8ffa0351 BS |
728 | current_id = old_length; |
729 | bitmap_clear (&this_info->incoming_open_chains_set); | |
730 | open_chains = NULL; | |
9771b263 | 731 | if (insn_rr.exists ()) |
1f234b83 | 732 | { |
a755f004 | 733 | rtx_insn *insn; |
1f234b83 BS |
734 | FOR_BB_INSNS (bb1, insn) |
735 | { | |
9771b263 | 736 | insn_rr_info *p = &insn_rr[INSN_UID (insn)]; |
1f234b83 BS |
737 | p->op_info = NULL; |
738 | } | |
739 | } | |
8ffa0351 BS |
740 | continue; |
741 | } | |
742 | ||
743 | if (dump_file) | |
744 | dump_def_use_chain (old_length); | |
745 | bitmap_copy (&this_info->open_chains_set, &open_chains_set); | |
746 | ||
747 | /* Add successor blocks to the worklist if necessary, and record | |
748 | data about our own open chains at the end of this block, which | |
749 | will be used to pre-open chains when processing the successors. */ | |
750 | FOR_EACH_EDGE (e, ei, bb1->succs) | |
751 | { | |
752 | struct bb_rename_info *dest_ri; | |
753 | struct du_head *chain; | |
754 | ||
755 | if (dump_file) | |
756 | fprintf (dump_file, "successor block %d\n", e->dest->index); | |
757 | ||
758 | if (e->flags & (EDGE_EH | EDGE_ABNORMAL)) | |
759 | continue; | |
760 | dest_ri = (struct bb_rename_info *)e->dest->aux; | |
761 | if (dest_ri == NULL) | |
762 | continue; | |
763 | for (chain = open_chains; chain; chain = chain->next_chain) | |
764 | set_incoming_from_chain (dest_ri, chain); | |
765 | } | |
766 | } | |
767 | ||
768 | free (inverse_postorder); | |
769 | ||
770 | /* Now, combine the chains data we have gathered across basic block | |
771 | boundaries. | |
772 | ||
773 | For every basic block, there may be chains open at the start, or at the | |
774 | end. Rather than exclude them from renaming, we look for open chains | |
775 | with matching registers at the other side of the CFG edge. | |
776 | ||
777 | For a given chain using register R, open at the start of block B, we | |
778 | must find an open chain using R on the other side of every edge leading | |
779 | to B, if the register is live across this edge. In the code below, | |
780 | N_PREDS_USED counts the number of edges where the register is live, and | |
781 | N_PREDS_JOINED counts those where we found an appropriate chain for | |
782 | joining. | |
783 | ||
784 | We perform the analysis for both incoming and outgoing edges, but we | |
785 | only need to merge once (in the second part, after verifying outgoing | |
786 | edges). */ | |
11cd3bed | 787 | FOR_EACH_BB_FN (bb, cfun) |
8ffa0351 BS |
788 | { |
789 | struct bb_rename_info *bb_ri = (struct bb_rename_info *) bb->aux; | |
790 | unsigned j; | |
791 | bitmap_iterator bi; | |
792 | ||
793 | if (bb_ri == NULL) | |
794 | continue; | |
795 | ||
796 | if (dump_file) | |
797 | fprintf (dump_file, "processing bb %d in edges\n", bb->index); | |
798 | ||
799 | EXECUTE_IF_SET_IN_BITMAP (&bb_ri->incoming_open_chains_set, 0, j, bi) | |
800 | { | |
801 | edge e; | |
802 | edge_iterator ei; | |
1f234b83 | 803 | struct du_head *chain = regrename_chain_from_id (j); |
8ffa0351 BS |
804 | int n_preds_used = 0, n_preds_joined = 0; |
805 | ||
806 | FOR_EACH_EDGE (e, ei, bb->preds) | |
807 | { | |
808 | struct bb_rename_info *src_ri; | |
809 | unsigned k; | |
810 | bitmap_iterator bi2; | |
811 | HARD_REG_SET live; | |
812 | bool success = false; | |
813 | ||
814 | REG_SET_TO_HARD_REG_SET (live, df_get_live_out (e->src)); | |
815 | if (!range_overlaps_hard_reg_set_p (live, chain->regno, | |
816 | chain->nregs)) | |
817 | continue; | |
818 | n_preds_used++; | |
819 | ||
820 | if (e->flags & (EDGE_EH | EDGE_ABNORMAL)) | |
821 | continue; | |
822 | ||
823 | src_ri = (struct bb_rename_info *)e->src->aux; | |
824 | if (src_ri == NULL) | |
825 | continue; | |
826 | ||
827 | EXECUTE_IF_SET_IN_BITMAP (&src_ri->open_chains_set, | |
828 | 0, k, bi2) | |
829 | { | |
1f234b83 | 830 | struct du_head *outgoing_chain = regrename_chain_from_id (k); |
8ffa0351 BS |
831 | |
832 | if (outgoing_chain->regno == chain->regno | |
833 | && outgoing_chain->nregs == chain->nregs) | |
834 | { | |
835 | n_preds_joined++; | |
836 | success = true; | |
837 | break; | |
838 | } | |
839 | } | |
840 | if (!success && dump_file) | |
841 | fprintf (dump_file, "failure to match with pred block %d\n", | |
842 | e->src->index); | |
843 | } | |
844 | if (n_preds_joined < n_preds_used) | |
845 | { | |
846 | if (dump_file) | |
847 | fprintf (dump_file, "cannot rename chain %d\n", j); | |
848 | chain->cannot_rename = 1; | |
849 | } | |
850 | } | |
851 | } | |
11cd3bed | 852 | FOR_EACH_BB_FN (bb, cfun) |
8ffa0351 BS |
853 | { |
854 | struct bb_rename_info *bb_ri = (struct bb_rename_info *) bb->aux; | |
855 | unsigned j; | |
856 | bitmap_iterator bi; | |
857 | ||
858 | if (bb_ri == NULL) | |
859 | continue; | |
860 | ||
861 | if (dump_file) | |
862 | fprintf (dump_file, "processing bb %d out edges\n", bb->index); | |
863 | ||
864 | EXECUTE_IF_SET_IN_BITMAP (&bb_ri->open_chains_set, 0, j, bi) | |
865 | { | |
866 | edge e; | |
867 | edge_iterator ei; | |
1f234b83 | 868 | struct du_head *chain = regrename_chain_from_id (j); |
8ffa0351 BS |
869 | int n_succs_used = 0, n_succs_joined = 0; |
870 | ||
871 | FOR_EACH_EDGE (e, ei, bb->succs) | |
872 | { | |
873 | bool printed = false; | |
874 | struct bb_rename_info *dest_ri; | |
875 | unsigned k; | |
876 | bitmap_iterator bi2; | |
877 | HARD_REG_SET live; | |
878 | ||
879 | REG_SET_TO_HARD_REG_SET (live, df_get_live_in (e->dest)); | |
880 | if (!range_overlaps_hard_reg_set_p (live, chain->regno, | |
881 | chain->nregs)) | |
882 | continue; | |
883 | ||
884 | n_succs_used++; | |
885 | ||
886 | dest_ri = (struct bb_rename_info *)e->dest->aux; | |
887 | if (dest_ri == NULL) | |
888 | continue; | |
889 | ||
890 | EXECUTE_IF_SET_IN_BITMAP (&dest_ri->incoming_open_chains_set, | |
891 | 0, k, bi2) | |
892 | { | |
1f234b83 | 893 | struct du_head *incoming_chain = regrename_chain_from_id (k); |
8ffa0351 BS |
894 | |
895 | if (incoming_chain->regno == chain->regno | |
896 | && incoming_chain->nregs == chain->nregs) | |
897 | { | |
898 | if (dump_file) | |
899 | { | |
900 | if (!printed) | |
901 | fprintf (dump_file, | |
902 | "merging blocks for edge %d -> %d\n", | |
903 | e->src->index, e->dest->index); | |
904 | printed = true; | |
905 | fprintf (dump_file, | |
906 | " merging chains %d (->%d) and %d (->%d) [%s]\n", | |
907 | k, incoming_chain->id, j, chain->id, | |
908 | reg_names[incoming_chain->regno]); | |
909 | } | |
910 | ||
911 | merge_chains (chain, incoming_chain); | |
912 | n_succs_joined++; | |
913 | break; | |
914 | } | |
915 | } | |
916 | } | |
917 | if (n_succs_joined < n_succs_used) | |
918 | { | |
919 | if (dump_file) | |
920 | fprintf (dump_file, "cannot rename chain %d\n", | |
921 | j); | |
922 | chain->cannot_rename = 1; | |
923 | } | |
924 | } | |
925 | } | |
926 | ||
927 | free (rename_info); | |
928 | ||
11cd3bed | 929 | FOR_EACH_BB_FN (bb, cfun) |
8ffa0351 BS |
930 | bb->aux = NULL; |
931 | } | |
932 | ||
17369fbf CLT |
933 | /* Attempt to replace all uses of the register in the chain beginning with |
934 | HEAD with REG. Returns true on success and false if the replacement is | |
935 | rejected because the insns would not validate. The latter can happen | |
936 | e.g. if a match_parallel predicate enforces restrictions on register | |
937 | numbering in its subpatterns. */ | |
938 | ||
939 | bool | |
1f234b83 | 940 | regrename_do_replace (struct du_head *head, int reg) |
7b82b5da | 941 | { |
9d324dde BS |
942 | struct du_chain *chain; |
943 | unsigned int base_regno = head->regno; | |
ef4bddc2 | 944 | machine_mode mode; |
b5b8b0ac | 945 | |
9d324dde | 946 | for (chain = head->first; chain; chain = chain->next_use) |
7b82b5da | 947 | { |
08394eef | 948 | unsigned int regno = ORIGINAL_REGNO (*chain->loc); |
9d324dde | 949 | struct reg_attrs *attr = REG_ATTRS (*chain->loc); |
b41310e2 | 950 | int reg_ptr = REG_POINTER (*chain->loc); |
d1d3c9a6 | 951 | |
b5b8b0ac | 952 | if (DEBUG_INSN_P (chain->insn) && REGNO (*chain->loc) != base_regno) |
17369fbf CLT |
953 | validate_change (chain->insn, &(INSN_VAR_LOCATION_LOC (chain->insn)), |
954 | gen_rtx_UNKNOWN_VAR_LOC (), true); | |
b5b8b0ac AO |
955 | else |
956 | { | |
17369fbf CLT |
957 | validate_change (chain->insn, chain->loc, |
958 | gen_raw_REG (GET_MODE (*chain->loc), reg), true); | |
b5b8b0ac AO |
959 | if (regno >= FIRST_PSEUDO_REGISTER) |
960 | ORIGINAL_REGNO (*chain->loc) = regno; | |
961 | REG_ATTRS (*chain->loc) = attr; | |
962 | REG_POINTER (*chain->loc) = reg_ptr; | |
963 | } | |
7b82b5da | 964 | } |
1f234b83 | 965 | |
17369fbf CLT |
966 | if (!apply_change_group ()) |
967 | return false; | |
968 | ||
1f234b83 BS |
969 | mode = GET_MODE (*head->first->loc); |
970 | head->regno = reg; | |
971 | head->nregs = hard_regno_nregs[reg][mode]; | |
17369fbf | 972 | return true; |
7b82b5da SC |
973 | } |
974 | ||
7b82b5da | 975 | |
a96caf80 BS |
976 | /* True if we found a register with a size mismatch, which means that we |
977 | can't track its lifetime accurately. If so, we abort the current block | |
978 | without renaming. */ | |
979 | static bool fail_current_block; | |
980 | ||
d435810e BS |
981 | /* Return true if OP is a reg for which all bits are set in PSET, false |
982 | if all bits are clear. | |
983 | In other cases, set fail_current_block and return false. */ | |
1f924675 BS |
984 | |
985 | static bool | |
d435810e | 986 | verify_reg_in_set (rtx op, HARD_REG_SET *pset) |
1f924675 BS |
987 | { |
988 | unsigned regno, nregs; | |
989 | bool all_live, all_dead; | |
990 | if (!REG_P (op)) | |
991 | return false; | |
992 | ||
993 | regno = REGNO (op); | |
dc8afb70 | 994 | nregs = REG_NREGS (op); |
1f924675 BS |
995 | all_live = all_dead = true; |
996 | while (nregs-- > 0) | |
d435810e | 997 | if (TEST_HARD_REG_BIT (*pset, regno + nregs)) |
1f924675 BS |
998 | all_dead = false; |
999 | else | |
1000 | all_live = false; | |
1001 | if (!all_dead && !all_live) | |
1002 | { | |
1003 | fail_current_block = true; | |
1004 | return false; | |
1005 | } | |
d435810e BS |
1006 | return all_live; |
1007 | } | |
1f924675 | 1008 | |
d435810e BS |
1009 | /* Return true if OP is a reg that is being tracked already in some form. |
1010 | May set fail_current_block if it sees an unhandled case of overlap. */ | |
1f924675 | 1011 | |
d435810e BS |
1012 | static bool |
1013 | verify_reg_tracked (rtx op) | |
1014 | { | |
1015 | return (verify_reg_in_set (op, &live_hard_regs) | |
1016 | || verify_reg_in_set (op, &live_in_chains)); | |
1f924675 BS |
1017 | } |
1018 | ||
a96caf80 BS |
1019 | /* Called through note_stores. DATA points to a rtx_code, either SET or |
1020 | CLOBBER, which tells us which kind of rtx to look at. If we have a | |
1021 | match, record the set register in live_hard_regs and in the hard_conflicts | |
1022 | bitmap of open chains. */ | |
1023 | ||
1024 | static void | |
1025 | note_sets_clobbers (rtx x, const_rtx set, void *data) | |
1026 | { | |
1027 | enum rtx_code code = *(enum rtx_code *)data; | |
1028 | struct du_head *chain; | |
1029 | ||
1030 | if (GET_CODE (x) == SUBREG) | |
1031 | x = SUBREG_REG (x); | |
1032 | if (!REG_P (x) || GET_CODE (set) != code) | |
1033 | return; | |
1034 | /* There must not be pseudos at this point. */ | |
1035 | gcc_assert (HARD_REGISTER_P (x)); | |
1036 | add_to_hard_reg_set (&live_hard_regs, GET_MODE (x), REGNO (x)); | |
1037 | for (chain = open_chains; chain; chain = chain->next_chain) | |
1038 | add_to_hard_reg_set (&chain->hard_conflicts, GET_MODE (x), REGNO (x)); | |
1039 | } | |
1040 | ||
541f7d56 | 1041 | static void |
a755f004 | 1042 | scan_rtx_reg (rtx_insn *insn, rtx *loc, enum reg_class cl, enum scan_actions action, |
6bda9bdf | 1043 | enum op_type type) |
7b82b5da | 1044 | { |
9d324dde | 1045 | struct du_head **p; |
541f7d56 | 1046 | rtx x = *loc; |
9d324dde | 1047 | unsigned this_regno = REGNO (x); |
dc8afb70 | 1048 | int this_nregs = REG_NREGS (x); |
541f7d56 | 1049 | |
541f7d56 | 1050 | if (action == mark_write) |
7b82b5da | 1051 | { |
541f7d56 | 1052 | if (type == OP_OUT) |
e33c42db | 1053 | create_new_chain (this_regno, this_nregs, loc, insn, cl); |
541f7d56 | 1054 | return; |
7b82b5da | 1055 | } |
1a43c33f | 1056 | |
cb110f3d | 1057 | if ((type == OP_OUT) != (action == terminate_write || action == mark_access)) |
541f7d56 | 1058 | return; |
5fa41e13 | 1059 | |
541f7d56 | 1060 | for (p = &open_chains; *p;) |
5fa41e13 | 1061 | { |
9d324dde | 1062 | struct du_head *head = *p; |
a96caf80 BS |
1063 | struct du_head *next = head->next_chain; |
1064 | int exact_match = (head->regno == this_regno | |
1065 | && head->nregs == this_nregs); | |
1066 | int superset = (this_regno <= head->regno | |
1067 | && this_regno + this_nregs >= head->regno + head->nregs); | |
d435810e BS |
1068 | int subset = (this_regno >= head->regno |
1069 | && this_regno + this_nregs <= head->regno + head->nregs); | |
a96caf80 | 1070 | |
d3e80850 | 1071 | if (!bitmap_bit_p (&open_chains_set, head->id) |
a96caf80 BS |
1072 | || head->regno + head->nregs <= this_regno |
1073 | || this_regno + this_nregs <= head->regno) | |
1074 | { | |
1075 | p = &head->next_chain; | |
1076 | continue; | |
1077 | } | |
541f7d56 | 1078 | |
a96caf80 | 1079 | if (action == mark_read || action == mark_access) |
3b03c671 | 1080 | { |
a96caf80 BS |
1081 | /* ??? Class NO_REGS can happen if the md file makes use of |
1082 | EXTRA_CONSTRAINTS to match registers. Which is arguably | |
1083 | wrong, but there we are. */ | |
695e4773 | 1084 | |
a96caf80 | 1085 | if (cl == NO_REGS || (!exact_match && !DEBUG_INSN_P (insn))) |
a125d855 | 1086 | { |
a96caf80 BS |
1087 | if (dump_file) |
1088 | fprintf (dump_file, | |
1089 | "Cannot rename chain %s (%d) at insn %d (%s)\n", | |
1090 | reg_names[head->regno], head->id, INSN_UID (insn), | |
1091 | scan_actions_name[(int) action]); | |
1092 | head->cannot_rename = 1; | |
d435810e BS |
1093 | if (superset) |
1094 | { | |
1095 | unsigned nregs = this_nregs; | |
1096 | head->regno = this_regno; | |
1097 | head->nregs = this_nregs; | |
1098 | while (nregs-- > 0) | |
1099 | SET_HARD_REG_BIT (live_in_chains, head->regno + nregs); | |
1100 | if (dump_file) | |
1101 | fprintf (dump_file, | |
1102 | "Widening register in chain %s (%d) at insn %d\n", | |
1103 | reg_names[head->regno], head->id, INSN_UID (insn)); | |
1104 | } | |
1105 | else if (!subset) | |
1106 | { | |
1107 | fail_current_block = true; | |
1108 | if (dump_file) | |
1109 | fprintf (dump_file, | |
1110 | "Failing basic block due to unhandled overlap\n"); | |
1111 | } | |
a125d855 | 1112 | } |
a96caf80 | 1113 | else |
541f7d56 | 1114 | { |
a96caf80 BS |
1115 | struct du_chain *this_du; |
1116 | this_du = XOBNEW (&rename_obstack, struct du_chain); | |
1117 | this_du->next_use = 0; | |
1118 | this_du->loc = loc; | |
1119 | this_du->insn = insn; | |
1120 | this_du->cl = cl; | |
e33c42db BS |
1121 | if (head->first == NULL) |
1122 | head->first = this_du; | |
1123 | else | |
1124 | head->last->next_use = this_du; | |
1f234b83 | 1125 | record_operand_use (head, this_du); |
a96caf80 | 1126 | head->last = this_du; |
541f7d56 | 1127 | } |
a96caf80 BS |
1128 | /* Avoid adding the same location in a DEBUG_INSN multiple times, |
1129 | which could happen with non-exact overlap. */ | |
1130 | if (DEBUG_INSN_P (insn)) | |
1131 | return; | |
1132 | /* Otherwise, find any other chains that do not match exactly; | |
1133 | ensure they all get marked unrenamable. */ | |
1134 | p = &head->next_chain; | |
1135 | continue; | |
1136 | } | |
a125d855 | 1137 | |
a96caf80 BS |
1138 | /* Whether the terminated chain can be used for renaming |
1139 | depends on the action and this being an exact match. | |
1140 | In either case, we remove this element from open_chains. */ | |
695e4773 | 1141 | |
a96caf80 | 1142 | if ((action == terminate_dead || action == terminate_write) |
998c75b6 | 1143 | && (superset || subset)) |
a96caf80 | 1144 | { |
1f924675 BS |
1145 | unsigned nregs; |
1146 | ||
998c75b6 BS |
1147 | if (subset && !superset) |
1148 | head->cannot_rename = 1; | |
a96caf80 | 1149 | bitmap_clear_bit (&open_chains_set, head->id); |
1f924675 BS |
1150 | |
1151 | nregs = head->nregs; | |
1152 | while (nregs-- > 0) | |
998c75b6 BS |
1153 | { |
1154 | CLEAR_HARD_REG_BIT (live_in_chains, head->regno + nregs); | |
1155 | if (subset && !superset | |
1156 | && (head->regno + nregs < this_regno | |
1157 | || head->regno + nregs >= this_regno + this_nregs)) | |
1158 | SET_HARD_REG_BIT (live_hard_regs, head->regno + nregs); | |
1159 | } | |
1f924675 | 1160 | |
a96caf80 BS |
1161 | *p = next; |
1162 | if (dump_file) | |
1163 | fprintf (dump_file, | |
998c75b6 | 1164 | "Closing chain %s (%d) at insn %d (%s%s)\n", |
a96caf80 | 1165 | reg_names[head->regno], head->id, INSN_UID (insn), |
998c75b6 BS |
1166 | scan_actions_name[(int) action], |
1167 | superset ? ", superset" : subset ? ", subset" : ""); | |
a96caf80 BS |
1168 | } |
1169 | else if (action == terminate_dead || action == terminate_write) | |
1170 | { | |
1171 | /* In this case, tracking liveness gets too hard. Fail the | |
1172 | entire basic block. */ | |
1173 | if (dump_file) | |
1174 | fprintf (dump_file, | |
1175 | "Failing basic block due to unhandled overlap\n"); | |
1176 | fail_current_block = true; | |
1177 | return; | |
1178 | } | |
1179 | else | |
1180 | { | |
1181 | head->cannot_rename = 1; | |
1182 | if (dump_file) | |
1183 | fprintf (dump_file, | |
1184 | "Cannot rename chain %s (%d) at insn %d (%s)\n", | |
1185 | reg_names[head->regno], head->id, INSN_UID (insn), | |
1186 | scan_actions_name[(int) action]); | |
1187 | p = &head->next_chain; | |
541f7d56 | 1188 | } |
541f7d56 | 1189 | } |
7b82b5da SC |
1190 | } |
1191 | ||
e3a64162 | 1192 | /* Adapted from find_reloads_address_1. CL is INDEX_REG_CLASS or |
541f7d56 | 1193 | BASE_REG_CLASS depending on how the register is being considered. */ |
7b82b5da | 1194 | |
4ca0f257 | 1195 | static void |
a755f004 | 1196 | scan_rtx_address (rtx_insn *insn, rtx *loc, enum reg_class cl, |
ef4bddc2 | 1197 | enum scan_actions action, machine_mode mode, |
86fc3d06 | 1198 | addr_space_t as) |
7b82b5da | 1199 | { |
541f7d56 BS |
1200 | rtx x = *loc; |
1201 | RTX_CODE code = GET_CODE (x); | |
1202 | const char *fmt; | |
1203 | int i, j; | |
7b82b5da | 1204 | |
cb110f3d | 1205 | if (action == mark_write || action == mark_access) |
541f7d56 | 1206 | return; |
7b82b5da | 1207 | |
541f7d56 | 1208 | switch (code) |
7b82b5da | 1209 | { |
541f7d56 BS |
1210 | case PLUS: |
1211 | { | |
1212 | rtx orig_op0 = XEXP (x, 0); | |
1213 | rtx orig_op1 = XEXP (x, 1); | |
1214 | RTX_CODE code0 = GET_CODE (orig_op0); | |
1215 | RTX_CODE code1 = GET_CODE (orig_op1); | |
1216 | rtx op0 = orig_op0; | |
1217 | rtx op1 = orig_op1; | |
1218 | rtx *locI = NULL; | |
1219 | rtx *locB = NULL; | |
84c9cb12 | 1220 | enum rtx_code index_code = SCRATCH; |
541f7d56 BS |
1221 | |
1222 | if (GET_CODE (op0) == SUBREG) | |
1223 | { | |
1224 | op0 = SUBREG_REG (op0); | |
1225 | code0 = GET_CODE (op0); | |
1226 | } | |
7b82b5da | 1227 | |
541f7d56 BS |
1228 | if (GET_CODE (op1) == SUBREG) |
1229 | { | |
1230 | op1 = SUBREG_REG (op1); | |
1231 | code1 = GET_CODE (op1); | |
1232 | } | |
7b82b5da | 1233 | |
541f7d56 BS |
1234 | if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE |
1235 | || code0 == ZERO_EXTEND || code1 == MEM) | |
1236 | { | |
1237 | locI = &XEXP (x, 0); | |
1238 | locB = &XEXP (x, 1); | |
c4963a0a | 1239 | index_code = GET_CODE (*locI); |
541f7d56 BS |
1240 | } |
1241 | else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE | |
1242 | || code1 == ZERO_EXTEND || code0 == MEM) | |
1243 | { | |
1244 | locI = &XEXP (x, 1); | |
1245 | locB = &XEXP (x, 0); | |
c4963a0a | 1246 | index_code = GET_CODE (*locI); |
541f7d56 BS |
1247 | } |
1248 | else if (code0 == CONST_INT || code0 == CONST | |
1249 | || code0 == SYMBOL_REF || code0 == LABEL_REF) | |
c4963a0a BS |
1250 | { |
1251 | locB = &XEXP (x, 1); | |
1252 | index_code = GET_CODE (XEXP (x, 0)); | |
1253 | } | |
541f7d56 BS |
1254 | else if (code1 == CONST_INT || code1 == CONST |
1255 | || code1 == SYMBOL_REF || code1 == LABEL_REF) | |
c4963a0a BS |
1256 | { |
1257 | locB = &XEXP (x, 0); | |
1258 | index_code = GET_CODE (XEXP (x, 1)); | |
1259 | } | |
541f7d56 BS |
1260 | else if (code0 == REG && code1 == REG) |
1261 | { | |
1262 | int index_op; | |
c4963a0a | 1263 | unsigned regno0 = REGNO (op0), regno1 = REGNO (op1); |
541f7d56 | 1264 | |
bd379f73 | 1265 | if (REGNO_OK_FOR_INDEX_P (regno1) |
86fc3d06 | 1266 | && regno_ok_for_base_p (regno0, mode, as, PLUS, REG)) |
bd379f73 PH |
1267 | index_op = 1; |
1268 | else if (REGNO_OK_FOR_INDEX_P (regno0) | |
86fc3d06 | 1269 | && regno_ok_for_base_p (regno1, mode, as, PLUS, REG)) |
541f7d56 | 1270 | index_op = 0; |
86fc3d06 | 1271 | else if (regno_ok_for_base_p (regno0, mode, as, PLUS, REG) |
bd379f73 | 1272 | || REGNO_OK_FOR_INDEX_P (regno1)) |
541f7d56 | 1273 | index_op = 1; |
86fc3d06 | 1274 | else if (regno_ok_for_base_p (regno1, mode, as, PLUS, REG)) |
541f7d56 | 1275 | index_op = 0; |
541f7d56 | 1276 | else |
bd379f73 | 1277 | index_op = 1; |
541f7d56 BS |
1278 | |
1279 | locI = &XEXP (x, index_op); | |
c4963a0a BS |
1280 | locB = &XEXP (x, !index_op); |
1281 | index_code = GET_CODE (*locI); | |
541f7d56 BS |
1282 | } |
1283 | else if (code0 == REG) | |
1284 | { | |
1285 | locI = &XEXP (x, 0); | |
1286 | locB = &XEXP (x, 1); | |
c4963a0a | 1287 | index_code = GET_CODE (*locI); |
541f7d56 BS |
1288 | } |
1289 | else if (code1 == REG) | |
1290 | { | |
1291 | locI = &XEXP (x, 1); | |
1292 | locB = &XEXP (x, 0); | |
c4963a0a | 1293 | index_code = GET_CODE (*locI); |
541f7d56 | 1294 | } |
7b82b5da | 1295 | |
541f7d56 | 1296 | if (locI) |
86fc3d06 | 1297 | scan_rtx_address (insn, locI, INDEX_REG_CLASS, action, mode, as); |
541f7d56 | 1298 | if (locB) |
86fc3d06 UW |
1299 | scan_rtx_address (insn, locB, |
1300 | base_reg_class (mode, as, PLUS, index_code), | |
1301 | action, mode, as); | |
c4963a0a | 1302 | |
541f7d56 BS |
1303 | return; |
1304 | } | |
7b82b5da | 1305 | |
541f7d56 BS |
1306 | case POST_INC: |
1307 | case POST_DEC: | |
1308 | case POST_MODIFY: | |
1309 | case PRE_INC: | |
1310 | case PRE_DEC: | |
1311 | case PRE_MODIFY: | |
1312 | #ifndef AUTO_INC_DEC | |
ce73761f RH |
1313 | /* If the target doesn't claim to handle autoinc, this must be |
1314 | something special, like a stack push. Kill this chain. */ | |
a96caf80 | 1315 | action = mark_all_read; |
541f7d56 BS |
1316 | #endif |
1317 | break; | |
7b82b5da | 1318 | |
541f7d56 | 1319 | case MEM: |
3dcc68a4 | 1320 | scan_rtx_address (insn, &XEXP (x, 0), |
86fc3d06 UW |
1321 | base_reg_class (GET_MODE (x), MEM_ADDR_SPACE (x), |
1322 | MEM, SCRATCH), | |
1323 | action, GET_MODE (x), MEM_ADDR_SPACE (x)); | |
541f7d56 | 1324 | return; |
1a43c33f | 1325 | |
541f7d56 | 1326 | case REG: |
6bda9bdf | 1327 | scan_rtx_reg (insn, loc, cl, action, OP_IN); |
4ca0f257 | 1328 | return; |
1a43c33f | 1329 | |
541f7d56 BS |
1330 | default: |
1331 | break; | |
4ca0f257 | 1332 | } |
541f7d56 BS |
1333 | |
1334 | fmt = GET_RTX_FORMAT (code); | |
1335 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4ca0f257 | 1336 | { |
541f7d56 | 1337 | if (fmt[i] == 'e') |
86fc3d06 | 1338 | scan_rtx_address (insn, &XEXP (x, i), cl, action, mode, as); |
541f7d56 BS |
1339 | else if (fmt[i] == 'E') |
1340 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
86fc3d06 | 1341 | scan_rtx_address (insn, &XVECEXP (x, i, j), cl, action, mode, as); |
4ca0f257 | 1342 | } |
7b82b5da SC |
1343 | } |
1344 | ||
541f7d56 | 1345 | static void |
a755f004 | 1346 | scan_rtx (rtx_insn *insn, rtx *loc, enum reg_class cl, enum scan_actions action, |
6bda9bdf | 1347 | enum op_type type) |
7b82b5da | 1348 | { |
541f7d56 BS |
1349 | const char *fmt; |
1350 | rtx x = *loc; | |
1351 | enum rtx_code code = GET_CODE (x); | |
1352 | int i, j; | |
7b82b5da | 1353 | |
541f7d56 BS |
1354 | code = GET_CODE (x); |
1355 | switch (code) | |
7b82b5da | 1356 | { |
541f7d56 | 1357 | case CONST: |
d8116890 | 1358 | CASE_CONST_ANY: |
541f7d56 BS |
1359 | case SYMBOL_REF: |
1360 | case LABEL_REF: | |
1361 | case CC0: | |
1362 | case PC: | |
1363 | return; | |
055be976 | 1364 | |
541f7d56 | 1365 | case REG: |
6bda9bdf | 1366 | scan_rtx_reg (insn, loc, cl, action, type); |
541f7d56 | 1367 | return; |
7b82b5da | 1368 | |
541f7d56 | 1369 | case MEM: |
3dcc68a4 | 1370 | scan_rtx_address (insn, &XEXP (x, 0), |
86fc3d06 UW |
1371 | base_reg_class (GET_MODE (x), MEM_ADDR_SPACE (x), |
1372 | MEM, SCRATCH), | |
1373 | action, GET_MODE (x), MEM_ADDR_SPACE (x)); | |
541f7d56 | 1374 | return; |
7b82b5da | 1375 | |
541f7d56 | 1376 | case SET: |
6bda9bdf | 1377 | scan_rtx (insn, &SET_SRC (x), cl, action, OP_IN); |
4e5813dd | 1378 | scan_rtx (insn, &SET_DEST (x), cl, action, |
1f924675 BS |
1379 | (GET_CODE (PATTERN (insn)) == COND_EXEC |
1380 | && verify_reg_tracked (SET_DEST (x))) ? OP_INOUT : OP_OUT); | |
541f7d56 | 1381 | return; |
7b82b5da | 1382 | |
541f7d56 | 1383 | case STRICT_LOW_PART: |
c4137918 BS |
1384 | scan_rtx (insn, &XEXP (x, 0), cl, action, |
1385 | verify_reg_tracked (XEXP (x, 0)) ? OP_INOUT : OP_OUT); | |
541f7d56 | 1386 | return; |
7b82b5da | 1387 | |
541f7d56 | 1388 | case ZERO_EXTRACT: |
3b03c671 | 1389 | case SIGN_EXTRACT: |
e3a64162 | 1390 | scan_rtx (insn, &XEXP (x, 0), cl, action, |
c4137918 BS |
1391 | (type == OP_IN ? OP_IN : |
1392 | verify_reg_tracked (XEXP (x, 0)) ? OP_INOUT : OP_OUT)); | |
6bda9bdf BS |
1393 | scan_rtx (insn, &XEXP (x, 1), cl, action, OP_IN); |
1394 | scan_rtx (insn, &XEXP (x, 2), cl, action, OP_IN); | |
541f7d56 | 1395 | return; |
7b82b5da | 1396 | |
541f7d56 BS |
1397 | case POST_INC: |
1398 | case PRE_INC: | |
1399 | case POST_DEC: | |
1400 | case PRE_DEC: | |
1401 | case POST_MODIFY: | |
1402 | case PRE_MODIFY: | |
1403 | /* Should only happen inside MEM. */ | |
41374e13 | 1404 | gcc_unreachable (); |
541f7d56 BS |
1405 | |
1406 | case CLOBBER: | |
4e5813dd | 1407 | scan_rtx (insn, &SET_DEST (x), cl, action, |
1f924675 BS |
1408 | (GET_CODE (PATTERN (insn)) == COND_EXEC |
1409 | && verify_reg_tracked (SET_DEST (x))) ? OP_INOUT : OP_OUT); | |
541f7d56 | 1410 | return; |
7b82b5da | 1411 | |
541f7d56 | 1412 | case EXPR_LIST: |
6bda9bdf | 1413 | scan_rtx (insn, &XEXP (x, 0), cl, action, type); |
541f7d56 | 1414 | if (XEXP (x, 1)) |
6bda9bdf | 1415 | scan_rtx (insn, &XEXP (x, 1), cl, action, type); |
541f7d56 | 1416 | return; |
7b82b5da | 1417 | |
541f7d56 BS |
1418 | default: |
1419 | break; | |
1420 | } | |
7b82b5da | 1421 | |
541f7d56 BS |
1422 | fmt = GET_RTX_FORMAT (code); |
1423 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7b82b5da SC |
1424 | { |
1425 | if (fmt[i] == 'e') | |
6bda9bdf | 1426 | scan_rtx (insn, &XEXP (x, i), cl, action, type); |
7b82b5da SC |
1427 | else if (fmt[i] == 'E') |
1428 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
6bda9bdf BS |
1429 | scan_rtx (insn, &XVECEXP (x, i, j), cl, action, type); |
1430 | } | |
1431 | } | |
1432 | ||
1433 | /* Hide operands of the current insn (of which there are N_OPS) by | |
1434 | substituting cc0 for them. | |
1435 | Previous values are stored in the OLD_OPERANDS and OLD_DUPS. | |
d435810e | 1436 | For every bit set in DO_NOT_HIDE, we leave the operand alone. |
a96caf80 BS |
1437 | If INOUT_AND_EC_ONLY is set, we only do this for OP_INOUT type operands |
1438 | and earlyclobbers. */ | |
6bda9bdf BS |
1439 | |
1440 | static void | |
1441 | hide_operands (int n_ops, rtx *old_operands, rtx *old_dups, | |
d435810e | 1442 | unsigned HOST_WIDE_INT do_not_hide, bool inout_and_ec_only) |
6bda9bdf BS |
1443 | { |
1444 | int i; | |
5efe5dec | 1445 | const operand_alternative *op_alt = which_op_alt (); |
6bda9bdf BS |
1446 | for (i = 0; i < n_ops; i++) |
1447 | { | |
1448 | old_operands[i] = recog_data.operand[i]; | |
1449 | /* Don't squash match_operator or match_parallel here, since | |
1450 | we don't know that all of the contained registers are | |
1451 | reachable by proper operands. */ | |
1452 | if (recog_data.constraints[i][0] == '\0') | |
1453 | continue; | |
d435810e BS |
1454 | if (do_not_hide & (1 << i)) |
1455 | continue; | |
a96caf80 | 1456 | if (!inout_and_ec_only || recog_data.operand_type[i] == OP_INOUT |
29d70a0f | 1457 | || op_alt[i].earlyclobber) |
6bda9bdf BS |
1458 | *recog_data.operand_loc[i] = cc0_rtx; |
1459 | } | |
1460 | for (i = 0; i < recog_data.n_dups; i++) | |
1461 | { | |
1462 | int opn = recog_data.dup_num[i]; | |
1463 | old_dups[i] = *recog_data.dup_loc[i]; | |
d435810e BS |
1464 | if (do_not_hide & (1 << opn)) |
1465 | continue; | |
a96caf80 | 1466 | if (!inout_and_ec_only || recog_data.operand_type[opn] == OP_INOUT |
29d70a0f | 1467 | || op_alt[opn].earlyclobber) |
6bda9bdf BS |
1468 | *recog_data.dup_loc[i] = cc0_rtx; |
1469 | } | |
1470 | } | |
1471 | ||
1472 | /* Undo the substitution performed by hide_operands. INSN is the insn we | |
1473 | are processing; the arguments are the same as in hide_operands. */ | |
1474 | ||
1475 | static void | |
a755f004 | 1476 | restore_operands (rtx_insn *insn, int n_ops, rtx *old_operands, rtx *old_dups) |
6bda9bdf BS |
1477 | { |
1478 | int i; | |
1479 | for (i = 0; i < recog_data.n_dups; i++) | |
1480 | *recog_data.dup_loc[i] = old_dups[i]; | |
1481 | for (i = 0; i < n_ops; i++) | |
1482 | *recog_data.operand_loc[i] = old_operands[i]; | |
1483 | if (recog_data.n_dups) | |
1484 | df_insn_rescan (insn); | |
1485 | } | |
1486 | ||
1487 | /* For each output operand of INSN, call scan_rtx to create a new | |
a96caf80 | 1488 | open chain. Do this only for normal or earlyclobber outputs, |
1f234b83 BS |
1489 | depending on EARLYCLOBBER. If INSN_INFO is nonnull, use it to |
1490 | record information about the operands in the insn. */ | |
6bda9bdf BS |
1491 | |
1492 | static void | |
a755f004 | 1493 | record_out_operands (rtx_insn *insn, bool earlyclobber, insn_rr_info *insn_info) |
6bda9bdf BS |
1494 | { |
1495 | int n_ops = recog_data.n_operands; | |
5efe5dec | 1496 | const operand_alternative *op_alt = which_op_alt (); |
6bda9bdf BS |
1497 | |
1498 | int i; | |
1499 | ||
1500 | for (i = 0; i < n_ops + recog_data.n_dups; i++) | |
1501 | { | |
1502 | int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops]; | |
1503 | rtx *loc = (i < n_ops | |
1504 | ? recog_data.operand_loc[opn] | |
1505 | : recog_data.dup_loc[i - n_ops]); | |
1506 | rtx op = *loc; | |
5efe5dec | 1507 | enum reg_class cl = alternative_class (op_alt, opn); |
6bda9bdf BS |
1508 | |
1509 | struct du_head *prev_open; | |
1510 | ||
a96caf80 | 1511 | if (recog_data.operand_type[opn] != OP_OUT |
29d70a0f | 1512 | || op_alt[opn].earlyclobber != earlyclobber) |
6bda9bdf BS |
1513 | continue; |
1514 | ||
1f234b83 BS |
1515 | if (insn_info) |
1516 | cur_operand = insn_info->op_info + i; | |
1517 | ||
6bda9bdf BS |
1518 | prev_open = open_chains; |
1519 | scan_rtx (insn, loc, cl, mark_write, OP_OUT); | |
1520 | ||
1521 | /* ??? Many targets have output constraints on the SET_DEST | |
1522 | of a call insn, which is stupid, since these are certainly | |
1523 | ABI defined hard registers. For these, and for asm operands | |
1524 | that originally referenced hard registers, we must record that | |
1525 | the chain cannot be renamed. */ | |
1526 | if (CALL_P (insn) | |
1527 | || (asm_noperands (PATTERN (insn)) > 0 | |
1528 | && REG_P (op) | |
1529 | && REGNO (op) == ORIGINAL_REGNO (op))) | |
1530 | { | |
1531 | if (prev_open != open_chains) | |
a96caf80 | 1532 | open_chains->cannot_rename = 1; |
6bda9bdf | 1533 | } |
7b82b5da | 1534 | } |
1f234b83 | 1535 | cur_operand = NULL; |
7b82b5da SC |
1536 | } |
1537 | ||
3eae4643 | 1538 | /* Build def/use chain. */ |
7b82b5da | 1539 | |
8ffa0351 | 1540 | static bool |
0c20a65f | 1541 | build_def_use (basic_block bb) |
7b82b5da | 1542 | { |
a755f004 | 1543 | rtx_insn *insn; |
d435810e | 1544 | unsigned HOST_WIDE_INT untracked_operands; |
1a43c33f | 1545 | |
a96caf80 BS |
1546 | fail_current_block = false; |
1547 | ||
a813c111 | 1548 | for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn)) |
541f7d56 | 1549 | { |
b5b8b0ac | 1550 | if (NONDEBUG_INSN_P (insn)) |
541f7d56 BS |
1551 | { |
1552 | int n_ops; | |
1553 | rtx note; | |
1554 | rtx old_operands[MAX_RECOG_OPERANDS]; | |
1555 | rtx old_dups[MAX_DUP_OPERANDS]; | |
0f900dfa | 1556 | int i; |
541f7d56 | 1557 | int predicated; |
a96caf80 BS |
1558 | enum rtx_code set_code = SET; |
1559 | enum rtx_code clobber_code = CLOBBER; | |
1f234b83 | 1560 | insn_rr_info *insn_info = NULL; |
541f7d56 | 1561 | |
541f7d56 | 1562 | /* Process the insn, determining its effect on the def-use |
a96caf80 BS |
1563 | chains and live hard registers. We perform the following |
1564 | steps with the register references in the insn, simulating | |
1565 | its effect: | |
1566 | (1) Deal with earlyclobber operands and CLOBBERs of non-operands | |
1567 | by creating chains and marking hard regs live. | |
541f7d56 | 1568 | (2) Any read outside an operand causes any chain it overlaps |
a96caf80 | 1569 | with to be marked unrenamable. |
541f7d56 BS |
1570 | (3) Any read inside an operand is added if there's already |
1571 | an open chain for it. | |
1572 | (4) For any REG_DEAD note we find, close open chains that | |
1573 | overlap it. | |
a96caf80 BS |
1574 | (5) For any non-earlyclobber write we find, close open chains |
1575 | that overlap it. | |
1576 | (6) For any non-earlyclobber write we find in an operand, make | |
1577 | a new chain or mark the hard register as live. | |
1578 | (7) For any REG_UNUSED, close any chains we just opened. | |
1579 | ||
1580 | We cannot deal with situations where we track a reg in one mode | |
1581 | and see a reference in another mode; these will cause the chain | |
1582 | to be marked unrenamable or even cause us to abort the entire | |
1583 | basic block. */ | |
541f7d56 | 1584 | |
75d25a02 | 1585 | extract_constrain_insn (insn); |
1145837d | 1586 | preprocess_constraints (insn); |
5efe5dec | 1587 | const operand_alternative *op_alt = which_op_alt (); |
541f7d56 | 1588 | n_ops = recog_data.n_operands; |
d435810e | 1589 | untracked_operands = 0; |
541f7d56 | 1590 | |
9771b263 | 1591 | if (insn_rr.exists ()) |
1f234b83 | 1592 | { |
9771b263 | 1593 | insn_info = &insn_rr[INSN_UID (insn)]; |
1f234b83 BS |
1594 | insn_info->op_info = XOBNEWVEC (&rename_obstack, operand_rr_info, |
1595 | recog_data.n_operands); | |
1596 | memset (insn_info->op_info, 0, | |
1597 | sizeof (operand_rr_info) * recog_data.n_operands); | |
1598 | } | |
1599 | ||
5efe5dec | 1600 | /* Simplify the code below by promoting OP_OUT to OP_INOUT in |
1f924675 BS |
1601 | predicated instructions, but only for register operands |
1602 | that are already tracked, so that we can create a chain | |
1603 | when the first SET makes a register live. */ | |
541f7d56 BS |
1604 | |
1605 | predicated = GET_CODE (PATTERN (insn)) == COND_EXEC; | |
1606 | for (i = 0; i < n_ops; ++i) | |
7b82b5da | 1607 | { |
e33c42db | 1608 | rtx op = recog_data.operand[i]; |
29d70a0f | 1609 | int matches = op_alt[i].matches; |
29d70a0f | 1610 | if (matches >= 0 || op_alt[i].matched >= 0 |
e33c42db | 1611 | || (predicated && recog_data.operand_type[i] == OP_OUT)) |
a96caf80 BS |
1612 | { |
1613 | recog_data.operand_type[i] = OP_INOUT; | |
d435810e BS |
1614 | /* A special case to deal with instruction patterns that |
1615 | have matching operands with different modes. If we're | |
1616 | not already tracking such a reg, we won't start here, | |
1617 | and we must instead make sure to make the operand visible | |
1618 | to the machinery that tracks hard registers. */ | |
a96caf80 BS |
1619 | if (matches >= 0 |
1620 | && (GET_MODE_SIZE (recog_data.operand_mode[i]) | |
d435810e BS |
1621 | != GET_MODE_SIZE (recog_data.operand_mode[matches])) |
1622 | && !verify_reg_in_set (op, &live_in_chains)) | |
1623 | { | |
1624 | untracked_operands |= 1 << i; | |
1625 | untracked_operands |= 1 << matches; | |
1626 | } | |
a96caf80 | 1627 | } |
c4137918 | 1628 | /* If there's an in-out operand with a register that is not |
e33c42db | 1629 | being tracked at all yet, open a chain. */ |
c4137918 BS |
1630 | if (recog_data.operand_type[i] == OP_INOUT |
1631 | && !(untracked_operands & (1 << i)) | |
e33c42db BS |
1632 | && REG_P (op) |
1633 | && !verify_reg_tracked (op)) | |
dc8afb70 RS |
1634 | create_new_chain (REGNO (op), REG_NREGS (op), NULL, NULL, |
1635 | NO_REGS); | |
7b82b5da | 1636 | } |
1a43c33f | 1637 | |
a96caf80 BS |
1638 | if (fail_current_block) |
1639 | break; | |
1640 | ||
1641 | /* Step 1a: Mark hard registers that are clobbered in this insn, | |
1642 | outside an operand, as live. */ | |
d435810e BS |
1643 | hide_operands (n_ops, old_operands, old_dups, untracked_operands, |
1644 | false); | |
a96caf80 BS |
1645 | note_stores (PATTERN (insn), note_sets_clobbers, &clobber_code); |
1646 | restore_operands (insn, n_ops, old_operands, old_dups); | |
1647 | ||
1648 | /* Step 1b: Begin new chains for earlyclobbered writes inside | |
1649 | operands. */ | |
1f234b83 | 1650 | record_out_operands (insn, true, insn_info); |
1a43c33f | 1651 | |
a96caf80 BS |
1652 | /* Step 2: Mark chains for which we have reads outside operands |
1653 | as unrenamable. | |
3b03c671 | 1654 | We do this by munging all operands into CC0, and closing |
541f7d56 | 1655 | everything remaining. */ |
7b82b5da | 1656 | |
d435810e BS |
1657 | hide_operands (n_ops, old_operands, old_dups, untracked_operands, |
1658 | false); | |
a96caf80 | 1659 | scan_rtx (insn, &PATTERN (insn), NO_REGS, mark_all_read, OP_IN); |
6bda9bdf | 1660 | restore_operands (insn, n_ops, old_operands, old_dups); |
7b82b5da | 1661 | |
541f7d56 | 1662 | /* Step 2B: Can't rename function call argument registers. */ |
4b4bf941 | 1663 | if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn)) |
541f7d56 | 1664 | scan_rtx (insn, &CALL_INSN_FUNCTION_USAGE (insn), |
a96caf80 | 1665 | NO_REGS, mark_all_read, OP_IN); |
7b82b5da | 1666 | |
3ada20ee RH |
1667 | /* Step 2C: Can't rename asm operands that were originally |
1668 | hard registers. */ | |
1669 | if (asm_noperands (PATTERN (insn)) > 0) | |
1670 | for (i = 0; i < n_ops; i++) | |
1671 | { | |
1672 | rtx *loc = recog_data.operand_loc[i]; | |
1673 | rtx op = *loc; | |
1674 | ||
f8cfc6aa | 1675 | if (REG_P (op) |
3ada20ee RH |
1676 | && REGNO (op) == ORIGINAL_REGNO (op) |
1677 | && (recog_data.operand_type[i] == OP_IN | |
1678 | || recog_data.operand_type[i] == OP_INOUT)) | |
a96caf80 | 1679 | scan_rtx (insn, loc, NO_REGS, mark_all_read, OP_IN); |
3ada20ee RH |
1680 | } |
1681 | ||
541f7d56 BS |
1682 | /* Step 3: Append to chains for reads inside operands. */ |
1683 | for (i = 0; i < n_ops + recog_data.n_dups; i++) | |
1684 | { | |
1685 | int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops]; | |
1686 | rtx *loc = (i < n_ops | |
1687 | ? recog_data.operand_loc[opn] | |
1688 | : recog_data.dup_loc[i - n_ops]); | |
5efe5dec | 1689 | enum reg_class cl = alternative_class (op_alt, opn); |
541f7d56 BS |
1690 | enum op_type type = recog_data.operand_type[opn]; |
1691 | ||
1692 | /* Don't scan match_operand here, since we've no reg class | |
1693 | information to pass down. Any operands that we could | |
1694 | substitute in will be represented elsewhere. */ | |
d435810e BS |
1695 | if (recog_data.constraints[opn][0] == '\0' |
1696 | || untracked_operands & (1 << opn)) | |
541f7d56 | 1697 | continue; |
7b82b5da | 1698 | |
1f234b83 BS |
1699 | if (insn_info) |
1700 | cur_operand = i == opn ? insn_info->op_info + i : NULL; | |
29d70a0f | 1701 | if (op_alt[opn].is_address) |
86fc3d06 UW |
1702 | scan_rtx_address (insn, loc, cl, mark_read, |
1703 | VOIDmode, ADDR_SPACE_GENERIC); | |
541f7d56 | 1704 | else |
6bda9bdf | 1705 | scan_rtx (insn, loc, cl, mark_read, type); |
541f7d56 | 1706 | } |
1f234b83 | 1707 | cur_operand = NULL; |
7b82b5da | 1708 | |
cb110f3d AM |
1709 | /* Step 3B: Record updates for regs in REG_INC notes, and |
1710 | source regs in REG_FRAME_RELATED_EXPR notes. */ | |
541f7d56 | 1711 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
cb110f3d AM |
1712 | if (REG_NOTE_KIND (note) == REG_INC |
1713 | || REG_NOTE_KIND (note) == REG_FRAME_RELATED_EXPR) | |
1714 | scan_rtx (insn, &XEXP (note, 0), ALL_REGS, mark_read, | |
6bda9bdf | 1715 | OP_INOUT); |
cb110f3d | 1716 | |
c664546f JL |
1717 | /* Step 4: Close chains for registers that die here, unless |
1718 | the register is mentioned in a REG_UNUSED note. In that | |
1719 | case we keep the chain open until step #7 below to ensure | |
1720 | it conflicts with other output operands of this insn. | |
1721 | See PR 52573. Arguably the insn should not have both | |
1722 | notes; it has proven difficult to fix that without | |
1723 | other undesirable side effects. */ | |
cb110f3d | 1724 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
c664546f JL |
1725 | if (REG_NOTE_KIND (note) == REG_DEAD |
1726 | && !find_regno_note (insn, REG_UNUSED, REGNO (XEXP (note, 0)))) | |
a96caf80 BS |
1727 | { |
1728 | remove_from_hard_reg_set (&live_hard_regs, | |
1729 | GET_MODE (XEXP (note, 0)), | |
1730 | REGNO (XEXP (note, 0))); | |
1731 | scan_rtx (insn, &XEXP (note, 0), NO_REGS, terminate_dead, | |
1732 | OP_IN); | |
1733 | } | |
1a43c33f | 1734 | |
541f7d56 BS |
1735 | /* Step 4B: If this is a call, any chain live at this point |
1736 | requires a caller-saved reg. */ | |
4b4bf941 | 1737 | if (CALL_P (insn)) |
541f7d56 | 1738 | { |
9d324dde | 1739 | struct du_head *p; |
541f7d56 | 1740 | for (p = open_chains; p; p = p->next_chain) |
fe08a886 | 1741 | p->need_caller_save_reg = 1; |
541f7d56 | 1742 | } |
7b82b5da | 1743 | |
541f7d56 BS |
1744 | /* Step 5: Close open chains that overlap writes. Similar to |
1745 | step 2, we hide in-out operands, since we do not want to | |
a96caf80 BS |
1746 | close these chains. We also hide earlyclobber operands, |
1747 | since we've opened chains for them in step 1, and earlier | |
1748 | chains they would overlap with must have been closed at | |
1749 | the previous insn at the latest, as such operands cannot | |
1750 | possibly overlap with any input operands. */ | |
7b82b5da | 1751 | |
d435810e BS |
1752 | hide_operands (n_ops, old_operands, old_dups, untracked_operands, |
1753 | true); | |
6bda9bdf BS |
1754 | scan_rtx (insn, &PATTERN (insn), NO_REGS, terminate_write, OP_IN); |
1755 | restore_operands (insn, n_ops, old_operands, old_dups); | |
7b82b5da | 1756 | |
a96caf80 BS |
1757 | /* Step 6a: Mark hard registers that are set in this insn, |
1758 | outside an operand, as live. */ | |
d435810e BS |
1759 | hide_operands (n_ops, old_operands, old_dups, untracked_operands, |
1760 | false); | |
a96caf80 BS |
1761 | note_stores (PATTERN (insn), note_sets_clobbers, &set_code); |
1762 | restore_operands (insn, n_ops, old_operands, old_dups); | |
7b82b5da | 1763 | |
a96caf80 | 1764 | /* Step 6b: Begin new chains for writes inside operands. */ |
1f234b83 | 1765 | record_out_operands (insn, false, insn_info); |
a96caf80 BS |
1766 | |
1767 | /* Step 6c: Record destination regs in REG_FRAME_RELATED_EXPR | |
cb110f3d AM |
1768 | notes for update. */ |
1769 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
1770 | if (REG_NOTE_KIND (note) == REG_FRAME_RELATED_EXPR) | |
1771 | scan_rtx (insn, &XEXP (note, 0), ALL_REGS, mark_access, | |
6bda9bdf | 1772 | OP_INOUT); |
cb110f3d | 1773 | |
541f7d56 BS |
1774 | /* Step 7: Close chains for registers that were never |
1775 | really used here. */ | |
1776 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
1777 | if (REG_NOTE_KIND (note) == REG_UNUSED) | |
a96caf80 BS |
1778 | { |
1779 | remove_from_hard_reg_set (&live_hard_regs, | |
1780 | GET_MODE (XEXP (note, 0)), | |
1781 | REGNO (XEXP (note, 0))); | |
1782 | scan_rtx (insn, &XEXP (note, 0), NO_REGS, terminate_dead, | |
1783 | OP_IN); | |
1784 | } | |
541f7d56 | 1785 | } |
b5b8b0ac AO |
1786 | else if (DEBUG_INSN_P (insn) |
1787 | && !VAR_LOC_UNKNOWN_P (INSN_VAR_LOCATION_LOC (insn))) | |
1788 | { | |
1789 | scan_rtx (insn, &INSN_VAR_LOCATION_LOC (insn), | |
6bda9bdf | 1790 | ALL_REGS, mark_read, OP_IN); |
b5b8b0ac | 1791 | } |
a813c111 | 1792 | if (insn == BB_END (bb)) |
541f7d56 BS |
1793 | break; |
1794 | } | |
7b82b5da | 1795 | |
a96caf80 | 1796 | if (fail_current_block) |
8ffa0351 | 1797 | return false; |
a96caf80 | 1798 | |
8ffa0351 | 1799 | return true; |
541f7d56 | 1800 | } |
ef330312 | 1801 | \f |
1f234b83 BS |
1802 | /* Initialize the register renamer. If INSN_INFO is true, ensure that |
1803 | insn_rr is nonnull. */ | |
1804 | void | |
1805 | regrename_init (bool insn_info) | |
1806 | { | |
1807 | gcc_obstack_init (&rename_obstack); | |
9771b263 | 1808 | insn_rr.create (0); |
1f234b83 | 1809 | if (insn_info) |
9771b263 | 1810 | insn_rr.safe_grow_cleared (get_max_uid ()); |
1f234b83 BS |
1811 | } |
1812 | ||
1813 | /* Free all global data used by the register renamer. */ | |
1814 | void | |
1815 | regrename_finish (void) | |
1816 | { | |
9771b263 | 1817 | insn_rr.release (); |
1f234b83 BS |
1818 | free_chain_data (); |
1819 | obstack_free (&rename_obstack, NULL); | |
1820 | } | |
1821 | ||
f24acbef BS |
1822 | /* Perform register renaming on the current function. */ |
1823 | ||
1824 | static unsigned int | |
1825 | regrename_optimize (void) | |
1826 | { | |
f24acbef BS |
1827 | df_set_flags (DF_LR_RUN_DCE); |
1828 | df_note_add_problem (); | |
1829 | df_analyze (); | |
1830 | df_set_flags (DF_DEFER_INSN_RESCAN); | |
1831 | ||
1f234b83 | 1832 | regrename_init (false); |
f24acbef | 1833 | |
1f234b83 | 1834 | regrename_analyze (NULL); |
f24acbef | 1835 | |
8ffa0351 | 1836 | rename_chains (); |
f24acbef | 1837 | |
1f234b83 | 1838 | regrename_finish (); |
f24acbef | 1839 | |
f24acbef BS |
1840 | return 0; |
1841 | } | |
1842 | \f | |
27a4cd48 DM |
1843 | namespace { |
1844 | ||
1845 | const pass_data pass_data_regrename = | |
ef330312 | 1846 | { |
27a4cd48 DM |
1847 | RTL_PASS, /* type */ |
1848 | "rnreg", /* name */ | |
1849 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
1850 | TV_RENAME_REGISTERS, /* tv_id */ |
1851 | 0, /* properties_required */ | |
1852 | 0, /* properties_provided */ | |
1853 | 0, /* properties_destroyed */ | |
1854 | 0, /* todo_flags_start */ | |
3bea341f | 1855 | TODO_df_finish, /* todo_flags_finish */ |
6fb5fa3c | 1856 | }; |
27a4cd48 DM |
1857 | |
1858 | class pass_regrename : public rtl_opt_pass | |
1859 | { | |
1860 | public: | |
c3284718 RS |
1861 | pass_regrename (gcc::context *ctxt) |
1862 | : rtl_opt_pass (pass_data_regrename, ctxt) | |
27a4cd48 DM |
1863 | {} |
1864 | ||
1865 | /* opt_pass methods: */ | |
1a3d085c TS |
1866 | virtual bool gate (function *) |
1867 | { | |
1868 | return (optimize > 0 && (flag_rename_registers)); | |
1869 | } | |
1870 | ||
be55bfe6 | 1871 | virtual unsigned int execute (function *) { return regrename_optimize (); } |
27a4cd48 DM |
1872 | |
1873 | }; // class pass_regrename | |
1874 | ||
1875 | } // anon namespace | |
1876 | ||
1877 | rtl_opt_pass * | |
1878 | make_pass_regrename (gcc::context *ctxt) | |
1879 | { | |
1880 | return new pass_regrename (ctxt); | |
1881 | } |