]>
Commit | Line | Data |
---|---|---|
b9a06185 | 1 | /* Register renaming for the GNU compiler. |
711789cc | 2 | Copyright (C) 2000-2013 Free Software Foundation, Inc. |
b9a06185 | 3 | |
f12b58b3 | 4 | This file is part of GCC. |
b9a06185 | 5 | |
f12b58b3 | 6 | GCC is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by | |
8c4c00c1 | 8 | the Free Software Foundation; either version 3, or (at your option) |
b9a06185 | 9 | any later version. |
10 | ||
f12b58b3 | 11 | GCC is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
b9a06185 | 15 | |
16 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
b9a06185 | 19 | |
20 | #include "config.h" | |
21 | #include "system.h" | |
805e22b2 | 22 | #include "coretypes.h" |
23 | #include "tm.h" | |
d7091a76 | 24 | #include "rtl-error.h" |
1140e77e | 25 | #include "tm_p.h" |
b9a06185 | 26 | #include "insn-config.h" |
27 | #include "regs.h" | |
00cb30dc | 28 | #include "addresses.h" |
1140e77e | 29 | #include "hard-reg-set.h" |
30 | #include "basic-block.h" | |
31 | #include "reload.h" | |
b9a06185 | 32 | #include "output.h" |
33 | #include "function.h" | |
34 | #include "recog.h" | |
1140e77e | 35 | #include "flags.h" |
36 | #include "obstack.h" | |
77fce4cd | 37 | #include "tree-pass.h" |
3072d30e | 38 | #include "df.h" |
d78118a3 | 39 | #include "target.h" |
7de639a2 | 40 | #include "emit-rtl.h" |
41 | #include "regrename.h" | |
1140e77e | 42 | |
9f3e3774 | 43 | /* This file implements the RTL register renaming pass of the compiler. It is |
44 | a semi-local pass whose goal is to maximize the usage of the register file | |
45 | of the processor by substituting registers for others in the solution given | |
46 | by the register allocator. The algorithm is as follows: | |
47 | ||
48 | 1. Local def/use chains are built: within each basic block, chains are | |
49 | opened and closed; if a chain isn't closed at the end of the block, | |
31adcf56 | 50 | it is dropped. We pre-open chains if we have already examined a |
51 | predecessor block and found chains live at the end which match | |
52 | live registers at the start of the new block. | |
9f3e3774 | 53 | |
31adcf56 | 54 | 2. We try to combine the local chains across basic block boundaries by |
55 | comparing chains that were open at the start or end of a block to | |
56 | those in successor/predecessor blocks. | |
57 | ||
58 | 3. For each chain, the set of possible renaming registers is computed. | |
9f3e3774 | 59 | This takes into account the renaming of previously processed chains. |
60 | Optionally, a preferred class is computed for the renaming register. | |
61 | ||
31adcf56 | 62 | 4. The best renaming register is computed for the chain in the above set, |
9f3e3774 | 63 | using a round-robin allocation. If a preferred class exists, then the |
64 | round-robin allocation is done within the class first, if possible. | |
65 | The round-robin allocation of renaming registers itself is global. | |
66 | ||
31adcf56 | 67 | 5. If a renaming register has been found, it is substituted in the chain. |
9f3e3774 | 68 | |
69 | Targets can parameterize the pass by specifying a preferred class for the | |
70 | renaming register for a given (super)class of registers to be renamed. */ | |
71 | ||
c38fa63b | 72 | #if HOST_BITS_PER_WIDE_INT <= MAX_RECOG_OPERANDS |
73 | #error "Use a different bitmap implementation for untracked_operands." | |
74 | #endif | |
9f3e3774 | 75 | |
1140e77e | 76 | enum scan_actions |
77 | { | |
1140e77e | 78 | terminate_write, |
79 | terminate_dead, | |
7197e178 | 80 | mark_all_read, |
1140e77e | 81 | mark_read, |
b9d576f5 | 82 | mark_write, |
83 | /* mark_access is for marking the destination regs in | |
84 | REG_FRAME_RELATED_EXPR notes (as if they were read) so that the | |
85 | note is updated properly. */ | |
86 | mark_access | |
1140e77e | 87 | }; |
88 | ||
89 | static const char * const scan_actions_name[] = | |
90 | { | |
1140e77e | 91 | "terminate_write", |
92 | "terminate_dead", | |
7197e178 | 93 | "mark_all_read", |
1140e77e | 94 | "mark_read", |
b9d576f5 | 95 | "mark_write", |
96 | "mark_access" | |
1140e77e | 97 | }; |
98 | ||
8fe3bc87 | 99 | /* TICK and THIS_TICK are used to record the last time we saw each |
100 | register. */ | |
101 | static int tick[FIRST_PSEUDO_REGISTER]; | |
102 | static int this_tick = 0; | |
103 | ||
1140e77e | 104 | static struct obstack rename_obstack; |
105 | ||
7de639a2 | 106 | /* If nonnull, the code calling into the register renamer requested |
107 | information about insn operands, and we store it here. */ | |
f1f41a6c | 108 | vec<insn_rr_info> insn_rr; |
7de639a2 | 109 | |
3ad4992f | 110 | static void scan_rtx (rtx, rtx *, enum reg_class, enum scan_actions, |
de67d37e | 111 | enum op_type); |
31adcf56 | 112 | static bool build_def_use (basic_block); |
d5dfb455 | 113 | |
8fe3bc87 | 114 | /* The id to be given to the next opened chain. */ |
115 | static unsigned current_id; | |
116 | ||
117 | /* A mapping of unique id numbers to chains. */ | |
f1f41a6c | 118 | static vec<du_head_p> id_to_chain; |
d5dfb455 | 119 | |
31adcf56 | 120 | /* List of currently open chains. */ |
8fe3bc87 | 121 | static struct du_head *open_chains; |
8fe3bc87 | 122 | |
123 | /* Bitmap of open chains. The bits set always match the list found in | |
124 | open_chains. */ | |
125 | static bitmap_head open_chains_set; | |
126 | ||
127 | /* Record the registers being tracked in open_chains. */ | |
128 | static HARD_REG_SET live_in_chains; | |
129 | ||
130 | /* Record the registers that are live but not tracked. The intersection | |
131 | between this and live_in_chains is empty. */ | |
132 | static HARD_REG_SET live_hard_regs; | |
133 | ||
7de639a2 | 134 | /* Set while scanning RTL if INSN_RR is nonnull, i.e. if the current analysis |
135 | is for a caller that requires operand data. Used in | |
136 | record_operand_use. */ | |
137 | static operand_rr_info *cur_operand; | |
138 | ||
31adcf56 | 139 | /* Return the chain corresponding to id number ID. Take into account that |
140 | chains may have been merged. */ | |
7de639a2 | 141 | du_head_p |
142 | regrename_chain_from_id (unsigned int id) | |
31adcf56 | 143 | { |
f1f41a6c | 144 | du_head_p first_chain = id_to_chain[id]; |
31adcf56 | 145 | du_head_p chain = first_chain; |
146 | while (chain->id != id) | |
147 | { | |
148 | id = chain->id; | |
f1f41a6c | 149 | chain = id_to_chain[id]; |
31adcf56 | 150 | } |
151 | first_chain->id = id; | |
152 | return chain; | |
153 | } | |
154 | ||
155 | /* Dump all def/use chains, starting at id FROM. */ | |
8fe3bc87 | 156 | |
157 | static void | |
31adcf56 | 158 | dump_def_use_chain (int from) |
8fe3bc87 | 159 | { |
31adcf56 | 160 | du_head_p head; |
161 | int i; | |
f1f41a6c | 162 | FOR_EACH_VEC_ELT_FROM (id_to_chain, i, head, from) |
8fe3bc87 | 163 | { |
164 | struct du_chain *this_du = head->first; | |
31adcf56 | 165 | |
8fe3bc87 | 166 | fprintf (dump_file, "Register %s (%d):", |
167 | reg_names[head->regno], head->nregs); | |
168 | while (this_du) | |
169 | { | |
170 | fprintf (dump_file, " %d [%s]", INSN_UID (this_du->insn), | |
171 | reg_class_names[this_du->cl]); | |
172 | this_du = this_du->next_use; | |
173 | } | |
174 | fprintf (dump_file, "\n"); | |
175 | head = head->next_chain; | |
176 | } | |
177 | } | |
178 | ||
d5dfb455 | 179 | static void |
7197e178 | 180 | free_chain_data (void) |
d5dfb455 | 181 | { |
7197e178 | 182 | int i; |
183 | du_head_p ptr; | |
f1f41a6c | 184 | for (i = 0; id_to_chain.iterate (i, &ptr); i++) |
7197e178 | 185 | bitmap_clear (&ptr->conflicts); |
feb90512 | 186 | |
f1f41a6c | 187 | id_to_chain.release (); |
d5dfb455 | 188 | } |
189 | ||
92effe69 | 190 | /* Walk all chains starting with CHAINS and record that they conflict with |
191 | another chain whose id is ID. */ | |
192 | ||
193 | static void | |
194 | mark_conflict (struct du_head *chains, unsigned id) | |
195 | { | |
196 | while (chains) | |
197 | { | |
198 | bitmap_set_bit (&chains->conflicts, id); | |
199 | chains = chains->next_chain; | |
200 | } | |
201 | } | |
202 | ||
7de639a2 | 203 | /* Examine cur_operand, and if it is nonnull, record information about the |
204 | use THIS_DU which is part of the chain HEAD. */ | |
205 | ||
206 | static void | |
207 | record_operand_use (struct du_head *head, struct du_chain *this_du) | |
208 | { | |
209 | if (cur_operand == NULL) | |
210 | return; | |
211 | gcc_assert (cur_operand->n_chains < MAX_REGS_PER_ADDRESS); | |
212 | cur_operand->heads[cur_operand->n_chains] = head; | |
213 | cur_operand->chains[cur_operand->n_chains++] = this_du; | |
214 | } | |
215 | ||
92effe69 | 216 | /* Create a new chain for THIS_NREGS registers starting at THIS_REGNO, |
217 | and record its occurrence in *LOC, which is being written to in INSN. | |
218 | This access requires a register of class CL. */ | |
219 | ||
31adcf56 | 220 | static du_head_p |
92effe69 | 221 | create_new_chain (unsigned this_regno, unsigned this_nregs, rtx *loc, |
222 | rtx insn, enum reg_class cl) | |
223 | { | |
224 | struct du_head *head = XOBNEW (&rename_obstack, struct du_head); | |
225 | struct du_chain *this_du; | |
226 | int nregs; | |
227 | ||
228 | head->next_chain = open_chains; | |
92effe69 | 229 | head->regno = this_regno; |
230 | head->nregs = this_nregs; | |
231 | head->need_caller_save_reg = 0; | |
232 | head->cannot_rename = 0; | |
233 | ||
f1f41a6c | 234 | id_to_chain.safe_push (head); |
92effe69 | 235 | head->id = current_id++; |
236 | ||
237 | bitmap_initialize (&head->conflicts, &bitmap_default_obstack); | |
238 | bitmap_copy (&head->conflicts, &open_chains_set); | |
239 | mark_conflict (open_chains, head->id); | |
240 | ||
241 | /* Since we're tracking this as a chain now, remove it from the | |
242 | list of conflicting live hard registers and track it in | |
243 | live_in_chains instead. */ | |
244 | nregs = head->nregs; | |
245 | while (nregs-- > 0) | |
246 | { | |
247 | SET_HARD_REG_BIT (live_in_chains, head->regno + nregs); | |
248 | CLEAR_HARD_REG_BIT (live_hard_regs, head->regno + nregs); | |
249 | } | |
250 | ||
251 | COPY_HARD_REG_SET (head->hard_conflicts, live_hard_regs); | |
252 | bitmap_set_bit (&open_chains_set, head->id); | |
253 | ||
254 | open_chains = head; | |
255 | ||
256 | if (dump_file) | |
257 | { | |
258 | fprintf (dump_file, "Creating chain %s (%d)", | |
259 | reg_names[head->regno], head->id); | |
260 | if (insn != NULL_RTX) | |
261 | fprintf (dump_file, " at insn %d", INSN_UID (insn)); | |
262 | fprintf (dump_file, "\n"); | |
263 | } | |
264 | ||
265 | if (insn == NULL_RTX) | |
266 | { | |
267 | head->first = head->last = NULL; | |
31adcf56 | 268 | return head; |
92effe69 | 269 | } |
270 | ||
271 | this_du = XOBNEW (&rename_obstack, struct du_chain); | |
272 | head->first = head->last = this_du; | |
273 | ||
274 | this_du->next_use = 0; | |
275 | this_du->loc = loc; | |
276 | this_du->insn = insn; | |
277 | this_du->cl = cl; | |
7de639a2 | 278 | record_operand_use (head, this_du); |
31adcf56 | 279 | return head; |
92effe69 | 280 | } |
281 | ||
7197e178 | 282 | /* For a def-use chain HEAD, find which registers overlap its lifetime and |
283 | set the corresponding bits in *PSET. */ | |
d5dfb455 | 284 | |
285 | static void | |
7197e178 | 286 | merge_overlapping_regs (HARD_REG_SET *pset, struct du_head *head) |
d5dfb455 | 287 | { |
7197e178 | 288 | bitmap_iterator bi; |
289 | unsigned i; | |
290 | IOR_HARD_REG_SET (*pset, head->hard_conflicts); | |
291 | EXECUTE_IF_SET_IN_BITMAP (&head->conflicts, 0, i, bi) | |
98ce3092 | 292 | { |
7de639a2 | 293 | du_head_p other = regrename_chain_from_id (i); |
7197e178 | 294 | unsigned j = other->nregs; |
31adcf56 | 295 | gcc_assert (other != head); |
7197e178 | 296 | while (j-- > 0) |
297 | SET_HARD_REG_BIT (*pset, other->regno + j); | |
d5dfb455 | 298 | } |
299 | } | |
300 | ||
d78118a3 | 301 | /* Check if NEW_REG can be the candidate register to rename for |
302 | REG in THIS_HEAD chain. THIS_UNAVAILABLE is a set of unavailable hard | |
303 | registers. */ | |
304 | ||
305 | static bool | |
57ce0a99 | 306 | check_new_reg_p (int reg ATTRIBUTE_UNUSED, int new_reg, |
307 | struct du_head *this_head, HARD_REG_SET this_unavailable) | |
d78118a3 | 308 | { |
309 | enum machine_mode mode = GET_MODE (*this_head->first->loc); | |
310 | int nregs = hard_regno_nregs[new_reg][mode]; | |
311 | int i; | |
312 | struct du_chain *tmp; | |
313 | ||
314 | for (i = nregs - 1; i >= 0; --i) | |
315 | if (TEST_HARD_REG_BIT (this_unavailable, new_reg + i) | |
316 | || fixed_regs[new_reg + i] | |
317 | || global_regs[new_reg + i] | |
318 | /* Can't use regs which aren't saved by the prologue. */ | |
319 | || (! df_regs_ever_live_p (new_reg + i) | |
320 | && ! call_used_regs[new_reg + i]) | |
321 | #ifdef LEAF_REGISTERS | |
322 | /* We can't use a non-leaf register if we're in a | |
323 | leaf function. */ | |
d5bf7b64 | 324 | || (crtl->is_leaf |
d78118a3 | 325 | && !LEAF_REGISTERS[new_reg + i]) |
326 | #endif | |
327 | #ifdef HARD_REGNO_RENAME_OK | |
328 | || ! HARD_REGNO_RENAME_OK (reg + i, new_reg + i) | |
329 | #endif | |
330 | ) | |
331 | return false; | |
332 | ||
333 | /* See whether it accepts all modes that occur in | |
334 | definition and uses. */ | |
335 | for (tmp = this_head->first; tmp; tmp = tmp->next_use) | |
336 | if ((! HARD_REGNO_MODE_OK (new_reg, GET_MODE (*tmp->loc)) | |
337 | && ! DEBUG_INSN_P (tmp->insn)) | |
338 | || (this_head->need_caller_save_reg | |
339 | && ! (HARD_REGNO_CALL_PART_CLOBBERED | |
340 | (reg, GET_MODE (*tmp->loc))) | |
341 | && (HARD_REGNO_CALL_PART_CLOBBERED | |
342 | (new_reg, GET_MODE (*tmp->loc))))) | |
343 | return false; | |
344 | ||
345 | return true; | |
346 | } | |
347 | ||
7de639a2 | 348 | /* For the chain THIS_HEAD, compute and return the best register to |
349 | rename to. SUPER_CLASS is the superunion of register classes in | |
350 | the chain. UNAVAILABLE is a set of registers that cannot be used. | |
351 | OLD_REG is the register currently used for the chain. */ | |
352 | ||
353 | int | |
354 | find_best_rename_reg (du_head_p this_head, enum reg_class super_class, | |
355 | HARD_REG_SET *unavailable, int old_reg) | |
356 | { | |
357 | bool has_preferred_class; | |
358 | enum reg_class preferred_class; | |
359 | int pass; | |
360 | int best_new_reg = old_reg; | |
361 | ||
362 | /* Further narrow the set of registers we can use for renaming. | |
363 | If the chain needs a call-saved register, mark the call-used | |
364 | registers as unavailable. */ | |
365 | if (this_head->need_caller_save_reg) | |
366 | IOR_HARD_REG_SET (*unavailable, call_used_reg_set); | |
367 | ||
368 | /* Mark registers that overlap this chain's lifetime as unavailable. */ | |
369 | merge_overlapping_regs (unavailable, this_head); | |
370 | ||
371 | /* Compute preferred rename class of super union of all the classes | |
372 | in the chain. */ | |
373 | preferred_class | |
374 | = (enum reg_class) targetm.preferred_rename_class (super_class); | |
375 | ||
376 | /* If PREFERRED_CLASS is not NO_REGS, we iterate in the first pass | |
377 | over registers that belong to PREFERRED_CLASS and try to find the | |
378 | best register within the class. If that failed, we iterate in | |
379 | the second pass over registers that don't belong to the class. | |
380 | If PREFERRED_CLASS is NO_REGS, we iterate over all registers in | |
381 | ascending order without any preference. */ | |
382 | has_preferred_class = (preferred_class != NO_REGS); | |
383 | for (pass = (has_preferred_class ? 0 : 1); pass < 2; pass++) | |
384 | { | |
385 | int new_reg; | |
386 | for (new_reg = 0; new_reg < FIRST_PSEUDO_REGISTER; new_reg++) | |
387 | { | |
388 | if (has_preferred_class | |
389 | && (pass == 0) | |
390 | != TEST_HARD_REG_BIT (reg_class_contents[preferred_class], | |
391 | new_reg)) | |
392 | continue; | |
393 | ||
394 | /* In the first pass, we force the renaming of registers that | |
395 | don't belong to PREFERRED_CLASS to registers that do, even | |
396 | though the latters were used not very long ago. */ | |
397 | if (check_new_reg_p (old_reg, new_reg, this_head, | |
398 | *unavailable) | |
399 | && ((pass == 0 | |
400 | && !TEST_HARD_REG_BIT (reg_class_contents[preferred_class], | |
401 | best_new_reg)) | |
402 | || tick[best_new_reg] > tick[new_reg])) | |
403 | best_new_reg = new_reg; | |
404 | } | |
405 | if (pass == 0 && best_new_reg != old_reg) | |
406 | break; | |
407 | } | |
408 | return best_new_reg; | |
409 | } | |
410 | ||
31adcf56 | 411 | /* Perform register renaming on the current function. */ |
8fe3bc87 | 412 | static void |
31adcf56 | 413 | rename_chains (void) |
8fe3bc87 | 414 | { |
415 | HARD_REG_SET unavailable; | |
31adcf56 | 416 | du_head_p this_head; |
417 | int i; | |
418 | ||
419 | memset (tick, 0, sizeof tick); | |
8fe3bc87 | 420 | |
421 | CLEAR_HARD_REG_SET (unavailable); | |
422 | /* Don't clobber traceback for noreturn functions. */ | |
423 | if (frame_pointer_needed) | |
424 | { | |
425 | add_to_hard_reg_set (&unavailable, Pmode, FRAME_POINTER_REGNUM); | |
426 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER | |
427 | add_to_hard_reg_set (&unavailable, Pmode, HARD_FRAME_POINTER_REGNUM); | |
428 | #endif | |
429 | } | |
430 | ||
f1f41a6c | 431 | FOR_EACH_VEC_ELT (id_to_chain, i, this_head) |
8fe3bc87 | 432 | { |
7de639a2 | 433 | int best_new_reg; |
8fe3bc87 | 434 | int n_uses; |
8fe3bc87 | 435 | struct du_chain *tmp; |
436 | HARD_REG_SET this_unavailable; | |
437 | int reg = this_head->regno; | |
8fe3bc87 | 438 | enum reg_class super_class = NO_REGS; |
8fe3bc87 | 439 | |
8fe3bc87 | 440 | if (this_head->cannot_rename) |
441 | continue; | |
442 | ||
8fe3bc87 | 443 | if (fixed_regs[reg] || global_regs[reg] |
444 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER | |
445 | || (frame_pointer_needed && reg == HARD_FRAME_POINTER_REGNUM) | |
446 | #else | |
447 | || (frame_pointer_needed && reg == FRAME_POINTER_REGNUM) | |
448 | #endif | |
449 | ) | |
450 | continue; | |
451 | ||
452 | COPY_HARD_REG_SET (this_unavailable, unavailable); | |
453 | ||
454 | /* Iterate over elements in the chain in order to: | |
455 | 1. Count number of uses, and narrow the set of registers we can | |
456 | use for renaming. | |
457 | 2. Compute the superunion of register classes in this chain. */ | |
458 | n_uses = 0; | |
459 | super_class = NO_REGS; | |
460 | for (tmp = this_head->first; tmp; tmp = tmp->next_use) | |
461 | { | |
462 | if (DEBUG_INSN_P (tmp->insn)) | |
463 | continue; | |
464 | n_uses++; | |
465 | IOR_COMPL_HARD_REG_SET (this_unavailable, | |
466 | reg_class_contents[tmp->cl]); | |
467 | super_class | |
468 | = reg_class_superunion[(int) super_class][(int) tmp->cl]; | |
469 | } | |
470 | ||
471 | if (n_uses < 2) | |
472 | continue; | |
473 | ||
7de639a2 | 474 | best_new_reg = find_best_rename_reg (this_head, super_class, |
475 | &this_unavailable, reg); | |
8fe3bc87 | 476 | |
477 | if (dump_file) | |
478 | { | |
479 | fprintf (dump_file, "Register %s in insn %d", | |
480 | reg_names[reg], INSN_UID (this_head->first->insn)); | |
481 | if (this_head->need_caller_save_reg) | |
482 | fprintf (dump_file, " crosses a call"); | |
483 | } | |
484 | ||
485 | if (best_new_reg == reg) | |
486 | { | |
487 | tick[reg] = ++this_tick; | |
488 | if (dump_file) | |
489 | fprintf (dump_file, "; no available better choice\n"); | |
490 | continue; | |
491 | } | |
492 | ||
493 | if (dump_file) | |
494 | fprintf (dump_file, ", renamed as %s\n", reg_names[best_new_reg]); | |
495 | ||
7de639a2 | 496 | regrename_do_replace (this_head, best_new_reg); |
8fe3bc87 | 497 | tick[best_new_reg] = ++this_tick; |
498 | df_set_regs_ever_live (best_new_reg, true); | |
499 | } | |
500 | } | |
501 | ||
31adcf56 | 502 | /* A structure to record information for each hard register at the start of |
503 | a basic block. */ | |
504 | struct incoming_reg_info { | |
505 | /* Holds the number of registers used in the chain that gave us information | |
506 | about this register. Zero means no information known yet, while a | |
507 | negative value is used for something that is part of, but not the first | |
508 | register in a multi-register value. */ | |
509 | int nregs; | |
510 | /* Set to true if we have accesses that conflict in the number of registers | |
511 | used. */ | |
512 | bool unusable; | |
513 | }; | |
514 | ||
515 | /* A structure recording information about each basic block. It is saved | |
516 | and restored around basic block boundaries. | |
517 | A pointer to such a structure is stored in each basic block's aux field | |
518 | during regrename_analyze, except for blocks we know can't be optimized | |
519 | (such as entry and exit blocks). */ | |
520 | struct bb_rename_info | |
521 | { | |
522 | /* The basic block corresponding to this structure. */ | |
523 | basic_block bb; | |
524 | /* Copies of the global information. */ | |
525 | bitmap_head open_chains_set; | |
526 | bitmap_head incoming_open_chains_set; | |
527 | struct incoming_reg_info incoming[FIRST_PSEUDO_REGISTER]; | |
528 | }; | |
529 | ||
530 | /* Initialize a rename_info structure P for basic block BB, which starts a new | |
531 | scan. */ | |
532 | static void | |
533 | init_rename_info (struct bb_rename_info *p, basic_block bb) | |
534 | { | |
535 | int i; | |
536 | df_ref *def_rec; | |
537 | HARD_REG_SET start_chains_set; | |
538 | ||
539 | p->bb = bb; | |
540 | bitmap_initialize (&p->open_chains_set, &bitmap_default_obstack); | |
541 | bitmap_initialize (&p->incoming_open_chains_set, &bitmap_default_obstack); | |
542 | ||
543 | open_chains = NULL; | |
544 | bitmap_clear (&open_chains_set); | |
545 | ||
546 | CLEAR_HARD_REG_SET (live_in_chains); | |
547 | REG_SET_TO_HARD_REG_SET (live_hard_regs, df_get_live_in (bb)); | |
548 | for (def_rec = df_get_artificial_defs (bb->index); *def_rec; def_rec++) | |
549 | { | |
550 | df_ref def = *def_rec; | |
551 | if (DF_REF_FLAGS (def) & DF_REF_AT_TOP) | |
552 | SET_HARD_REG_BIT (live_hard_regs, DF_REF_REGNO (def)); | |
553 | } | |
554 | ||
555 | /* Open chains based on information from (at least one) predecessor | |
556 | block. This gives us a chance later on to combine chains across | |
557 | basic block boundaries. Inconsistencies (in access sizes) will | |
558 | be caught normally and dealt with conservatively by disabling the | |
559 | chain for renaming, and there is no risk of losing optimization | |
560 | opportunities by opening chains either: if we did not open the | |
561 | chains, we'd have to track the live register as a hard reg, and | |
562 | we'd be unable to rename it in any case. */ | |
563 | CLEAR_HARD_REG_SET (start_chains_set); | |
564 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
565 | { | |
566 | struct incoming_reg_info *iri = p->incoming + i; | |
567 | if (iri->nregs > 0 && !iri->unusable | |
568 | && range_in_hard_reg_set_p (live_hard_regs, i, iri->nregs)) | |
569 | { | |
570 | SET_HARD_REG_BIT (start_chains_set, i); | |
571 | remove_range_from_hard_reg_set (&live_hard_regs, i, iri->nregs); | |
572 | } | |
573 | } | |
574 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
575 | { | |
576 | struct incoming_reg_info *iri = p->incoming + i; | |
577 | if (TEST_HARD_REG_BIT (start_chains_set, i)) | |
578 | { | |
579 | du_head_p chain; | |
580 | if (dump_file) | |
581 | fprintf (dump_file, "opening incoming chain\n"); | |
582 | chain = create_new_chain (i, iri->nregs, NULL, NULL_RTX, NO_REGS); | |
583 | bitmap_set_bit (&p->incoming_open_chains_set, chain->id); | |
584 | } | |
585 | } | |
586 | } | |
587 | ||
588 | /* Record in RI that the block corresponding to it has an incoming | |
589 | live value, described by CHAIN. */ | |
590 | static void | |
591 | set_incoming_from_chain (struct bb_rename_info *ri, du_head_p chain) | |
592 | { | |
593 | int i; | |
594 | int incoming_nregs = ri->incoming[chain->regno].nregs; | |
595 | int nregs; | |
596 | ||
597 | /* If we've recorded the same information before, everything is fine. */ | |
598 | if (incoming_nregs == chain->nregs) | |
599 | { | |
600 | if (dump_file) | |
601 | fprintf (dump_file, "reg %d/%d already recorded\n", | |
602 | chain->regno, chain->nregs); | |
603 | return; | |
604 | } | |
605 | ||
606 | /* If we have no information for any of the involved registers, update | |
607 | the incoming array. */ | |
608 | nregs = chain->nregs; | |
609 | while (nregs-- > 0) | |
610 | if (ri->incoming[chain->regno + nregs].nregs != 0 | |
611 | || ri->incoming[chain->regno + nregs].unusable) | |
612 | break; | |
613 | if (nregs < 0) | |
614 | { | |
615 | nregs = chain->nregs; | |
616 | ri->incoming[chain->regno].nregs = nregs; | |
617 | while (nregs-- > 1) | |
618 | ri->incoming[chain->regno + nregs].nregs = -nregs; | |
619 | if (dump_file) | |
620 | fprintf (dump_file, "recorded reg %d/%d\n", | |
621 | chain->regno, chain->nregs); | |
622 | return; | |
623 | } | |
624 | ||
625 | /* There must be some kind of conflict. Prevent both the old and | |
626 | new ranges from being used. */ | |
627 | if (incoming_nregs < 0) | |
628 | ri->incoming[chain->regno + incoming_nregs].unusable = true; | |
629 | for (i = 0; i < chain->nregs; i++) | |
630 | ri->incoming[chain->regno + i].unusable = true; | |
631 | } | |
632 | ||
633 | /* Merge the two chains C1 and C2 so that all conflict information is | |
634 | recorded and C1, and the id of C2 is changed to that of C1. */ | |
635 | static void | |
636 | merge_chains (du_head_p c1, du_head_p c2) | |
637 | { | |
638 | if (c1 == c2) | |
639 | return; | |
640 | ||
641 | if (c2->first != NULL) | |
642 | { | |
643 | if (c1->first == NULL) | |
644 | c1->first = c2->first; | |
645 | else | |
646 | c1->last->next_use = c2->first; | |
647 | c1->last = c2->last; | |
648 | } | |
649 | ||
650 | c2->first = c2->last = NULL; | |
651 | c2->id = c1->id; | |
652 | ||
653 | IOR_HARD_REG_SET (c1->hard_conflicts, c2->hard_conflicts); | |
654 | bitmap_ior_into (&c1->conflicts, &c2->conflicts); | |
655 | ||
656 | c1->need_caller_save_reg |= c2->need_caller_save_reg; | |
657 | c1->cannot_rename |= c2->cannot_rename; | |
658 | } | |
659 | ||
660 | /* Analyze the current function and build chains for renaming. */ | |
661 | ||
7de639a2 | 662 | void |
663 | regrename_analyze (bitmap bb_mask) | |
31adcf56 | 664 | { |
665 | struct bb_rename_info *rename_info; | |
666 | int i; | |
667 | basic_block bb; | |
668 | int n_bbs; | |
669 | int *inverse_postorder; | |
670 | ||
fe672ac0 | 671 | inverse_postorder = XNEWVEC (int, last_basic_block_for_fn (cfun)); |
31adcf56 | 672 | n_bbs = pre_and_rev_post_order_compute (NULL, inverse_postorder, false); |
673 | ||
674 | /* Gather some information about the blocks in this function. */ | |
a28770e1 | 675 | rename_info = XCNEWVEC (struct bb_rename_info, n_basic_blocks_for_fn (cfun)); |
31adcf56 | 676 | i = 0; |
fc00614f | 677 | FOR_EACH_BB_FN (bb, cfun) |
31adcf56 | 678 | { |
679 | struct bb_rename_info *ri = rename_info + i; | |
680 | ri->bb = bb; | |
7de639a2 | 681 | if (bb_mask != NULL && !bitmap_bit_p (bb_mask, bb->index)) |
682 | bb->aux = NULL; | |
683 | else | |
684 | bb->aux = ri; | |
31adcf56 | 685 | i++; |
686 | } | |
687 | ||
688 | current_id = 0; | |
f1f41a6c | 689 | id_to_chain.create (0); |
31adcf56 | 690 | bitmap_initialize (&open_chains_set, &bitmap_default_obstack); |
691 | ||
692 | /* The order in which we visit blocks ensures that whenever | |
693 | possible, we only process a block after at least one of its | |
694 | predecessors, which provides a "seeding" effect to make the logic | |
695 | in set_incoming_from_chain and init_rename_info useful. */ | |
696 | ||
697 | for (i = 0; i < n_bbs; i++) | |
698 | { | |
f5a6b05f | 699 | basic_block bb1 = BASIC_BLOCK_FOR_FN (cfun, inverse_postorder[i]); |
31adcf56 | 700 | struct bb_rename_info *this_info; |
701 | bool success; | |
702 | edge e; | |
703 | edge_iterator ei; | |
f1f41a6c | 704 | int old_length = id_to_chain.length (); |
31adcf56 | 705 | |
706 | this_info = (struct bb_rename_info *) bb1->aux; | |
707 | if (this_info == NULL) | |
708 | continue; | |
709 | ||
710 | if (dump_file) | |
711 | fprintf (dump_file, "\nprocessing block %d:\n", bb1->index); | |
712 | ||
713 | init_rename_info (this_info, bb1); | |
714 | ||
715 | success = build_def_use (bb1); | |
716 | if (!success) | |
717 | { | |
718 | if (dump_file) | |
719 | fprintf (dump_file, "failed\n"); | |
720 | bb1->aux = NULL; | |
f1f41a6c | 721 | id_to_chain.truncate (old_length); |
31adcf56 | 722 | current_id = old_length; |
723 | bitmap_clear (&this_info->incoming_open_chains_set); | |
724 | open_chains = NULL; | |
f1f41a6c | 725 | if (insn_rr.exists ()) |
7de639a2 | 726 | { |
727 | rtx insn; | |
728 | FOR_BB_INSNS (bb1, insn) | |
729 | { | |
f1f41a6c | 730 | insn_rr_info *p = &insn_rr[INSN_UID (insn)]; |
7de639a2 | 731 | p->op_info = NULL; |
732 | } | |
733 | } | |
31adcf56 | 734 | continue; |
735 | } | |
736 | ||
737 | if (dump_file) | |
738 | dump_def_use_chain (old_length); | |
739 | bitmap_copy (&this_info->open_chains_set, &open_chains_set); | |
740 | ||
741 | /* Add successor blocks to the worklist if necessary, and record | |
742 | data about our own open chains at the end of this block, which | |
743 | will be used to pre-open chains when processing the successors. */ | |
744 | FOR_EACH_EDGE (e, ei, bb1->succs) | |
745 | { | |
746 | struct bb_rename_info *dest_ri; | |
747 | struct du_head *chain; | |
748 | ||
749 | if (dump_file) | |
750 | fprintf (dump_file, "successor block %d\n", e->dest->index); | |
751 | ||
752 | if (e->flags & (EDGE_EH | EDGE_ABNORMAL)) | |
753 | continue; | |
754 | dest_ri = (struct bb_rename_info *)e->dest->aux; | |
755 | if (dest_ri == NULL) | |
756 | continue; | |
757 | for (chain = open_chains; chain; chain = chain->next_chain) | |
758 | set_incoming_from_chain (dest_ri, chain); | |
759 | } | |
760 | } | |
761 | ||
762 | free (inverse_postorder); | |
763 | ||
764 | /* Now, combine the chains data we have gathered across basic block | |
765 | boundaries. | |
766 | ||
767 | For every basic block, there may be chains open at the start, or at the | |
768 | end. Rather than exclude them from renaming, we look for open chains | |
769 | with matching registers at the other side of the CFG edge. | |
770 | ||
771 | For a given chain using register R, open at the start of block B, we | |
772 | must find an open chain using R on the other side of every edge leading | |
773 | to B, if the register is live across this edge. In the code below, | |
774 | N_PREDS_USED counts the number of edges where the register is live, and | |
775 | N_PREDS_JOINED counts those where we found an appropriate chain for | |
776 | joining. | |
777 | ||
778 | We perform the analysis for both incoming and outgoing edges, but we | |
779 | only need to merge once (in the second part, after verifying outgoing | |
780 | edges). */ | |
fc00614f | 781 | FOR_EACH_BB_FN (bb, cfun) |
31adcf56 | 782 | { |
783 | struct bb_rename_info *bb_ri = (struct bb_rename_info *) bb->aux; | |
784 | unsigned j; | |
785 | bitmap_iterator bi; | |
786 | ||
787 | if (bb_ri == NULL) | |
788 | continue; | |
789 | ||
790 | if (dump_file) | |
791 | fprintf (dump_file, "processing bb %d in edges\n", bb->index); | |
792 | ||
793 | EXECUTE_IF_SET_IN_BITMAP (&bb_ri->incoming_open_chains_set, 0, j, bi) | |
794 | { | |
795 | edge e; | |
796 | edge_iterator ei; | |
7de639a2 | 797 | struct du_head *chain = regrename_chain_from_id (j); |
31adcf56 | 798 | int n_preds_used = 0, n_preds_joined = 0; |
799 | ||
800 | FOR_EACH_EDGE (e, ei, bb->preds) | |
801 | { | |
802 | struct bb_rename_info *src_ri; | |
803 | unsigned k; | |
804 | bitmap_iterator bi2; | |
805 | HARD_REG_SET live; | |
806 | bool success = false; | |
807 | ||
808 | REG_SET_TO_HARD_REG_SET (live, df_get_live_out (e->src)); | |
809 | if (!range_overlaps_hard_reg_set_p (live, chain->regno, | |
810 | chain->nregs)) | |
811 | continue; | |
812 | n_preds_used++; | |
813 | ||
814 | if (e->flags & (EDGE_EH | EDGE_ABNORMAL)) | |
815 | continue; | |
816 | ||
817 | src_ri = (struct bb_rename_info *)e->src->aux; | |
818 | if (src_ri == NULL) | |
819 | continue; | |
820 | ||
821 | EXECUTE_IF_SET_IN_BITMAP (&src_ri->open_chains_set, | |
822 | 0, k, bi2) | |
823 | { | |
7de639a2 | 824 | struct du_head *outgoing_chain = regrename_chain_from_id (k); |
31adcf56 | 825 | |
826 | if (outgoing_chain->regno == chain->regno | |
827 | && outgoing_chain->nregs == chain->nregs) | |
828 | { | |
829 | n_preds_joined++; | |
830 | success = true; | |
831 | break; | |
832 | } | |
833 | } | |
834 | if (!success && dump_file) | |
835 | fprintf (dump_file, "failure to match with pred block %d\n", | |
836 | e->src->index); | |
837 | } | |
838 | if (n_preds_joined < n_preds_used) | |
839 | { | |
840 | if (dump_file) | |
841 | fprintf (dump_file, "cannot rename chain %d\n", j); | |
842 | chain->cannot_rename = 1; | |
843 | } | |
844 | } | |
845 | } | |
fc00614f | 846 | FOR_EACH_BB_FN (bb, cfun) |
31adcf56 | 847 | { |
848 | struct bb_rename_info *bb_ri = (struct bb_rename_info *) bb->aux; | |
849 | unsigned j; | |
850 | bitmap_iterator bi; | |
851 | ||
852 | if (bb_ri == NULL) | |
853 | continue; | |
854 | ||
855 | if (dump_file) | |
856 | fprintf (dump_file, "processing bb %d out edges\n", bb->index); | |
857 | ||
858 | EXECUTE_IF_SET_IN_BITMAP (&bb_ri->open_chains_set, 0, j, bi) | |
859 | { | |
860 | edge e; | |
861 | edge_iterator ei; | |
7de639a2 | 862 | struct du_head *chain = regrename_chain_from_id (j); |
31adcf56 | 863 | int n_succs_used = 0, n_succs_joined = 0; |
864 | ||
865 | FOR_EACH_EDGE (e, ei, bb->succs) | |
866 | { | |
867 | bool printed = false; | |
868 | struct bb_rename_info *dest_ri; | |
869 | unsigned k; | |
870 | bitmap_iterator bi2; | |
871 | HARD_REG_SET live; | |
872 | ||
873 | REG_SET_TO_HARD_REG_SET (live, df_get_live_in (e->dest)); | |
874 | if (!range_overlaps_hard_reg_set_p (live, chain->regno, | |
875 | chain->nregs)) | |
876 | continue; | |
877 | ||
878 | n_succs_used++; | |
879 | ||
880 | dest_ri = (struct bb_rename_info *)e->dest->aux; | |
881 | if (dest_ri == NULL) | |
882 | continue; | |
883 | ||
884 | EXECUTE_IF_SET_IN_BITMAP (&dest_ri->incoming_open_chains_set, | |
885 | 0, k, bi2) | |
886 | { | |
7de639a2 | 887 | struct du_head *incoming_chain = regrename_chain_from_id (k); |
31adcf56 | 888 | |
889 | if (incoming_chain->regno == chain->regno | |
890 | && incoming_chain->nregs == chain->nregs) | |
891 | { | |
892 | if (dump_file) | |
893 | { | |
894 | if (!printed) | |
895 | fprintf (dump_file, | |
896 | "merging blocks for edge %d -> %d\n", | |
897 | e->src->index, e->dest->index); | |
898 | printed = true; | |
899 | fprintf (dump_file, | |
900 | " merging chains %d (->%d) and %d (->%d) [%s]\n", | |
901 | k, incoming_chain->id, j, chain->id, | |
902 | reg_names[incoming_chain->regno]); | |
903 | } | |
904 | ||
905 | merge_chains (chain, incoming_chain); | |
906 | n_succs_joined++; | |
907 | break; | |
908 | } | |
909 | } | |
910 | } | |
911 | if (n_succs_joined < n_succs_used) | |
912 | { | |
913 | if (dump_file) | |
914 | fprintf (dump_file, "cannot rename chain %d\n", | |
915 | j); | |
916 | chain->cannot_rename = 1; | |
917 | } | |
918 | } | |
919 | } | |
920 | ||
921 | free (rename_info); | |
922 | ||
fc00614f | 923 | FOR_EACH_BB_FN (bb, cfun) |
31adcf56 | 924 | bb->aux = NULL; |
925 | } | |
926 | ||
7de639a2 | 927 | void |
928 | regrename_do_replace (struct du_head *head, int reg) | |
b9a06185 | 929 | { |
bb6d4603 | 930 | struct du_chain *chain; |
931 | unsigned int base_regno = head->regno; | |
7de639a2 | 932 | enum machine_mode mode; |
9845d120 | 933 | |
bb6d4603 | 934 | for (chain = head->first; chain; chain = chain->next_use) |
b9a06185 | 935 | { |
22cf44bc | 936 | unsigned int regno = ORIGINAL_REGNO (*chain->loc); |
bb6d4603 | 937 | struct reg_attrs *attr = REG_ATTRS (*chain->loc); |
41d261a4 | 938 | int reg_ptr = REG_POINTER (*chain->loc); |
83d9f776 | 939 | |
9845d120 | 940 | if (DEBUG_INSN_P (chain->insn) && REGNO (*chain->loc) != base_regno) |
941 | INSN_VAR_LOCATION_LOC (chain->insn) = gen_rtx_UNKNOWN_VAR_LOC (); | |
942 | else | |
943 | { | |
944 | *chain->loc = gen_raw_REG (GET_MODE (*chain->loc), reg); | |
945 | if (regno >= FIRST_PSEUDO_REGISTER) | |
946 | ORIGINAL_REGNO (*chain->loc) = regno; | |
947 | REG_ATTRS (*chain->loc) = attr; | |
948 | REG_POINTER (*chain->loc) = reg_ptr; | |
949 | } | |
950 | ||
b45b55a5 | 951 | df_insn_rescan (chain->insn); |
b9a06185 | 952 | } |
7de639a2 | 953 | |
954 | mode = GET_MODE (*head->first->loc); | |
955 | head->regno = reg; | |
956 | head->nregs = hard_regno_nregs[reg][mode]; | |
b9a06185 | 957 | } |
958 | ||
b9a06185 | 959 | |
7197e178 | 960 | /* True if we found a register with a size mismatch, which means that we |
961 | can't track its lifetime accurately. If so, we abort the current block | |
962 | without renaming. */ | |
963 | static bool fail_current_block; | |
964 | ||
c38fa63b | 965 | /* Return true if OP is a reg for which all bits are set in PSET, false |
966 | if all bits are clear. | |
967 | In other cases, set fail_current_block and return false. */ | |
83361a4c | 968 | |
969 | static bool | |
c38fa63b | 970 | verify_reg_in_set (rtx op, HARD_REG_SET *pset) |
83361a4c | 971 | { |
972 | unsigned regno, nregs; | |
973 | bool all_live, all_dead; | |
974 | if (!REG_P (op)) | |
975 | return false; | |
976 | ||
977 | regno = REGNO (op); | |
978 | nregs = hard_regno_nregs[regno][GET_MODE (op)]; | |
979 | all_live = all_dead = true; | |
980 | while (nregs-- > 0) | |
c38fa63b | 981 | if (TEST_HARD_REG_BIT (*pset, regno + nregs)) |
83361a4c | 982 | all_dead = false; |
983 | else | |
984 | all_live = false; | |
985 | if (!all_dead && !all_live) | |
986 | { | |
987 | fail_current_block = true; | |
988 | return false; | |
989 | } | |
c38fa63b | 990 | return all_live; |
991 | } | |
83361a4c | 992 | |
c38fa63b | 993 | /* Return true if OP is a reg that is being tracked already in some form. |
994 | May set fail_current_block if it sees an unhandled case of overlap. */ | |
83361a4c | 995 | |
c38fa63b | 996 | static bool |
997 | verify_reg_tracked (rtx op) | |
998 | { | |
999 | return (verify_reg_in_set (op, &live_hard_regs) | |
1000 | || verify_reg_in_set (op, &live_in_chains)); | |
83361a4c | 1001 | } |
1002 | ||
7197e178 | 1003 | /* Called through note_stores. DATA points to a rtx_code, either SET or |
1004 | CLOBBER, which tells us which kind of rtx to look at. If we have a | |
1005 | match, record the set register in live_hard_regs and in the hard_conflicts | |
1006 | bitmap of open chains. */ | |
1007 | ||
1008 | static void | |
1009 | note_sets_clobbers (rtx x, const_rtx set, void *data) | |
1010 | { | |
1011 | enum rtx_code code = *(enum rtx_code *)data; | |
1012 | struct du_head *chain; | |
1013 | ||
1014 | if (GET_CODE (x) == SUBREG) | |
1015 | x = SUBREG_REG (x); | |
1016 | if (!REG_P (x) || GET_CODE (set) != code) | |
1017 | return; | |
1018 | /* There must not be pseudos at this point. */ | |
1019 | gcc_assert (HARD_REGISTER_P (x)); | |
1020 | add_to_hard_reg_set (&live_hard_regs, GET_MODE (x), REGNO (x)); | |
1021 | for (chain = open_chains; chain; chain = chain->next_chain) | |
1022 | add_to_hard_reg_set (&chain->hard_conflicts, GET_MODE (x), REGNO (x)); | |
1023 | } | |
1024 | ||
1140e77e | 1025 | static void |
de67d37e | 1026 | scan_rtx_reg (rtx insn, rtx *loc, enum reg_class cl, enum scan_actions action, |
1027 | enum op_type type) | |
b9a06185 | 1028 | { |
bb6d4603 | 1029 | struct du_head **p; |
1140e77e | 1030 | rtx x = *loc; |
1031 | enum machine_mode mode = GET_MODE (x); | |
bb6d4603 | 1032 | unsigned this_regno = REGNO (x); |
31adcf56 | 1033 | int this_nregs = hard_regno_nregs[this_regno][mode]; |
1140e77e | 1034 | |
1140e77e | 1035 | if (action == mark_write) |
b9a06185 | 1036 | { |
1140e77e | 1037 | if (type == OP_OUT) |
17db414f | 1038 | create_new_chain (this_regno, this_nregs, loc, insn, cl); |
1140e77e | 1039 | return; |
b9a06185 | 1040 | } |
d98fed9f | 1041 | |
b9d576f5 | 1042 | if ((type == OP_OUT) != (action == terminate_write || action == mark_access)) |
1140e77e | 1043 | return; |
ceba8bb1 | 1044 | |
1140e77e | 1045 | for (p = &open_chains; *p;) |
ceba8bb1 | 1046 | { |
bb6d4603 | 1047 | struct du_head *head = *p; |
7197e178 | 1048 | struct du_head *next = head->next_chain; |
1049 | int exact_match = (head->regno == this_regno | |
1050 | && head->nregs == this_nregs); | |
1051 | int superset = (this_regno <= head->regno | |
1052 | && this_regno + this_nregs >= head->regno + head->nregs); | |
c38fa63b | 1053 | int subset = (this_regno >= head->regno |
1054 | && this_regno + this_nregs <= head->regno + head->nregs); | |
7197e178 | 1055 | |
8fe3bc87 | 1056 | if (!bitmap_bit_p (&open_chains_set, head->id) |
7197e178 | 1057 | || head->regno + head->nregs <= this_regno |
1058 | || this_regno + this_nregs <= head->regno) | |
1059 | { | |
1060 | p = &head->next_chain; | |
1061 | continue; | |
1062 | } | |
1140e77e | 1063 | |
7197e178 | 1064 | if (action == mark_read || action == mark_access) |
709c2f34 | 1065 | { |
7197e178 | 1066 | /* ??? Class NO_REGS can happen if the md file makes use of |
1067 | EXTRA_CONSTRAINTS to match registers. Which is arguably | |
1068 | wrong, but there we are. */ | |
77b2358d | 1069 | |
7197e178 | 1070 | if (cl == NO_REGS || (!exact_match && !DEBUG_INSN_P (insn))) |
a292cb6e | 1071 | { |
7197e178 | 1072 | if (dump_file) |
1073 | fprintf (dump_file, | |
1074 | "Cannot rename chain %s (%d) at insn %d (%s)\n", | |
1075 | reg_names[head->regno], head->id, INSN_UID (insn), | |
1076 | scan_actions_name[(int) action]); | |
1077 | head->cannot_rename = 1; | |
c38fa63b | 1078 | if (superset) |
1079 | { | |
1080 | unsigned nregs = this_nregs; | |
1081 | head->regno = this_regno; | |
1082 | head->nregs = this_nregs; | |
1083 | while (nregs-- > 0) | |
1084 | SET_HARD_REG_BIT (live_in_chains, head->regno + nregs); | |
1085 | if (dump_file) | |
1086 | fprintf (dump_file, | |
1087 | "Widening register in chain %s (%d) at insn %d\n", | |
1088 | reg_names[head->regno], head->id, INSN_UID (insn)); | |
1089 | } | |
1090 | else if (!subset) | |
1091 | { | |
1092 | fail_current_block = true; | |
1093 | if (dump_file) | |
1094 | fprintf (dump_file, | |
1095 | "Failing basic block due to unhandled overlap\n"); | |
1096 | } | |
a292cb6e | 1097 | } |
7197e178 | 1098 | else |
1140e77e | 1099 | { |
7197e178 | 1100 | struct du_chain *this_du; |
1101 | this_du = XOBNEW (&rename_obstack, struct du_chain); | |
1102 | this_du->next_use = 0; | |
1103 | this_du->loc = loc; | |
1104 | this_du->insn = insn; | |
1105 | this_du->cl = cl; | |
17db414f | 1106 | if (head->first == NULL) |
1107 | head->first = this_du; | |
1108 | else | |
1109 | head->last->next_use = this_du; | |
7de639a2 | 1110 | record_operand_use (head, this_du); |
7197e178 | 1111 | head->last = this_du; |
1140e77e | 1112 | } |
7197e178 | 1113 | /* Avoid adding the same location in a DEBUG_INSN multiple times, |
1114 | which could happen with non-exact overlap. */ | |
1115 | if (DEBUG_INSN_P (insn)) | |
1116 | return; | |
1117 | /* Otherwise, find any other chains that do not match exactly; | |
1118 | ensure they all get marked unrenamable. */ | |
1119 | p = &head->next_chain; | |
1120 | continue; | |
1121 | } | |
a292cb6e | 1122 | |
7197e178 | 1123 | /* Whether the terminated chain can be used for renaming |
1124 | depends on the action and this being an exact match. | |
1125 | In either case, we remove this element from open_chains. */ | |
77b2358d | 1126 | |
7197e178 | 1127 | if ((action == terminate_dead || action == terminate_write) |
38e1b753 | 1128 | && (superset || subset)) |
7197e178 | 1129 | { |
83361a4c | 1130 | unsigned nregs; |
1131 | ||
38e1b753 | 1132 | if (subset && !superset) |
1133 | head->cannot_rename = 1; | |
7197e178 | 1134 | bitmap_clear_bit (&open_chains_set, head->id); |
83361a4c | 1135 | |
1136 | nregs = head->nregs; | |
1137 | while (nregs-- > 0) | |
38e1b753 | 1138 | { |
1139 | CLEAR_HARD_REG_BIT (live_in_chains, head->regno + nregs); | |
1140 | if (subset && !superset | |
1141 | && (head->regno + nregs < this_regno | |
1142 | || head->regno + nregs >= this_regno + this_nregs)) | |
1143 | SET_HARD_REG_BIT (live_hard_regs, head->regno + nregs); | |
1144 | } | |
83361a4c | 1145 | |
7197e178 | 1146 | *p = next; |
1147 | if (dump_file) | |
1148 | fprintf (dump_file, | |
38e1b753 | 1149 | "Closing chain %s (%d) at insn %d (%s%s)\n", |
7197e178 | 1150 | reg_names[head->regno], head->id, INSN_UID (insn), |
38e1b753 | 1151 | scan_actions_name[(int) action], |
1152 | superset ? ", superset" : subset ? ", subset" : ""); | |
7197e178 | 1153 | } |
1154 | else if (action == terminate_dead || action == terminate_write) | |
1155 | { | |
1156 | /* In this case, tracking liveness gets too hard. Fail the | |
1157 | entire basic block. */ | |
1158 | if (dump_file) | |
1159 | fprintf (dump_file, | |
1160 | "Failing basic block due to unhandled overlap\n"); | |
1161 | fail_current_block = true; | |
1162 | return; | |
1163 | } | |
1164 | else | |
1165 | { | |
1166 | head->cannot_rename = 1; | |
1167 | if (dump_file) | |
1168 | fprintf (dump_file, | |
1169 | "Cannot rename chain %s (%d) at insn %d (%s)\n", | |
1170 | reg_names[head->regno], head->id, INSN_UID (insn), | |
1171 | scan_actions_name[(int) action]); | |
1172 | p = &head->next_chain; | |
1140e77e | 1173 | } |
1140e77e | 1174 | } |
b9a06185 | 1175 | } |
1176 | ||
e916c70c | 1177 | /* Adapted from find_reloads_address_1. CL is INDEX_REG_CLASS or |
1140e77e | 1178 | BASE_REG_CLASS depending on how the register is being considered. */ |
b9a06185 | 1179 | |
31659b75 | 1180 | static void |
e916c70c | 1181 | scan_rtx_address (rtx insn, rtx *loc, enum reg_class cl, |
f8a8fc7b | 1182 | enum scan_actions action, enum machine_mode mode, |
1183 | addr_space_t as) | |
b9a06185 | 1184 | { |
1140e77e | 1185 | rtx x = *loc; |
1186 | RTX_CODE code = GET_CODE (x); | |
1187 | const char *fmt; | |
1188 | int i, j; | |
b9a06185 | 1189 | |
b9d576f5 | 1190 | if (action == mark_write || action == mark_access) |
1140e77e | 1191 | return; |
b9a06185 | 1192 | |
1140e77e | 1193 | switch (code) |
b9a06185 | 1194 | { |
1140e77e | 1195 | case PLUS: |
1196 | { | |
1197 | rtx orig_op0 = XEXP (x, 0); | |
1198 | rtx orig_op1 = XEXP (x, 1); | |
1199 | RTX_CODE code0 = GET_CODE (orig_op0); | |
1200 | RTX_CODE code1 = GET_CODE (orig_op1); | |
1201 | rtx op0 = orig_op0; | |
1202 | rtx op1 = orig_op1; | |
1203 | rtx *locI = NULL; | |
1204 | rtx *locB = NULL; | |
260988c8 | 1205 | enum rtx_code index_code = SCRATCH; |
1140e77e | 1206 | |
1207 | if (GET_CODE (op0) == SUBREG) | |
1208 | { | |
1209 | op0 = SUBREG_REG (op0); | |
1210 | code0 = GET_CODE (op0); | |
1211 | } | |
b9a06185 | 1212 | |
1140e77e | 1213 | if (GET_CODE (op1) == SUBREG) |
1214 | { | |
1215 | op1 = SUBREG_REG (op1); | |
1216 | code1 = GET_CODE (op1); | |
1217 | } | |
b9a06185 | 1218 | |
1140e77e | 1219 | if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE |
1220 | || code0 == ZERO_EXTEND || code1 == MEM) | |
1221 | { | |
1222 | locI = &XEXP (x, 0); | |
1223 | locB = &XEXP (x, 1); | |
00cb30dc | 1224 | index_code = GET_CODE (*locI); |
1140e77e | 1225 | } |
1226 | else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE | |
1227 | || code1 == ZERO_EXTEND || code0 == MEM) | |
1228 | { | |
1229 | locI = &XEXP (x, 1); | |
1230 | locB = &XEXP (x, 0); | |
00cb30dc | 1231 | index_code = GET_CODE (*locI); |
1140e77e | 1232 | } |
1233 | else if (code0 == CONST_INT || code0 == CONST | |
1234 | || code0 == SYMBOL_REF || code0 == LABEL_REF) | |
00cb30dc | 1235 | { |
1236 | locB = &XEXP (x, 1); | |
1237 | index_code = GET_CODE (XEXP (x, 0)); | |
1238 | } | |
1140e77e | 1239 | else if (code1 == CONST_INT || code1 == CONST |
1240 | || code1 == SYMBOL_REF || code1 == LABEL_REF) | |
00cb30dc | 1241 | { |
1242 | locB = &XEXP (x, 0); | |
1243 | index_code = GET_CODE (XEXP (x, 1)); | |
1244 | } | |
1140e77e | 1245 | else if (code0 == REG && code1 == REG) |
1246 | { | |
1247 | int index_op; | |
00cb30dc | 1248 | unsigned regno0 = REGNO (op0), regno1 = REGNO (op1); |
1140e77e | 1249 | |
ce0d0c3a | 1250 | if (REGNO_OK_FOR_INDEX_P (regno1) |
f8a8fc7b | 1251 | && regno_ok_for_base_p (regno0, mode, as, PLUS, REG)) |
ce0d0c3a | 1252 | index_op = 1; |
1253 | else if (REGNO_OK_FOR_INDEX_P (regno0) | |
f8a8fc7b | 1254 | && regno_ok_for_base_p (regno1, mode, as, PLUS, REG)) |
1140e77e | 1255 | index_op = 0; |
f8a8fc7b | 1256 | else if (regno_ok_for_base_p (regno0, mode, as, PLUS, REG) |
ce0d0c3a | 1257 | || REGNO_OK_FOR_INDEX_P (regno1)) |
1140e77e | 1258 | index_op = 1; |
f8a8fc7b | 1259 | else if (regno_ok_for_base_p (regno1, mode, as, PLUS, REG)) |
1140e77e | 1260 | index_op = 0; |
1140e77e | 1261 | else |
ce0d0c3a | 1262 | index_op = 1; |
1140e77e | 1263 | |
1264 | locI = &XEXP (x, index_op); | |
00cb30dc | 1265 | locB = &XEXP (x, !index_op); |
1266 | index_code = GET_CODE (*locI); | |
1140e77e | 1267 | } |
1268 | else if (code0 == REG) | |
1269 | { | |
1270 | locI = &XEXP (x, 0); | |
1271 | locB = &XEXP (x, 1); | |
00cb30dc | 1272 | index_code = GET_CODE (*locI); |
1140e77e | 1273 | } |
1274 | else if (code1 == REG) | |
1275 | { | |
1276 | locI = &XEXP (x, 1); | |
1277 | locB = &XEXP (x, 0); | |
00cb30dc | 1278 | index_code = GET_CODE (*locI); |
1140e77e | 1279 | } |
b9a06185 | 1280 | |
1140e77e | 1281 | if (locI) |
f8a8fc7b | 1282 | scan_rtx_address (insn, locI, INDEX_REG_CLASS, action, mode, as); |
1140e77e | 1283 | if (locB) |
f8a8fc7b | 1284 | scan_rtx_address (insn, locB, |
1285 | base_reg_class (mode, as, PLUS, index_code), | |
1286 | action, mode, as); | |
00cb30dc | 1287 | |
1140e77e | 1288 | return; |
1289 | } | |
b9a06185 | 1290 | |
1140e77e | 1291 | case POST_INC: |
1292 | case POST_DEC: | |
1293 | case POST_MODIFY: | |
1294 | case PRE_INC: | |
1295 | case PRE_DEC: | |
1296 | case PRE_MODIFY: | |
1297 | #ifndef AUTO_INC_DEC | |
8f758362 | 1298 | /* If the target doesn't claim to handle autoinc, this must be |
1299 | something special, like a stack push. Kill this chain. */ | |
7197e178 | 1300 | action = mark_all_read; |
1140e77e | 1301 | #endif |
1302 | break; | |
b9a06185 | 1303 | |
1140e77e | 1304 | case MEM: |
2e6d14e8 | 1305 | scan_rtx_address (insn, &XEXP (x, 0), |
f8a8fc7b | 1306 | base_reg_class (GET_MODE (x), MEM_ADDR_SPACE (x), |
1307 | MEM, SCRATCH), | |
1308 | action, GET_MODE (x), MEM_ADDR_SPACE (x)); | |
1140e77e | 1309 | return; |
d98fed9f | 1310 | |
1140e77e | 1311 | case REG: |
de67d37e | 1312 | scan_rtx_reg (insn, loc, cl, action, OP_IN); |
31659b75 | 1313 | return; |
d98fed9f | 1314 | |
1140e77e | 1315 | default: |
1316 | break; | |
31659b75 | 1317 | } |
1140e77e | 1318 | |
1319 | fmt = GET_RTX_FORMAT (code); | |
1320 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
31659b75 | 1321 | { |
1140e77e | 1322 | if (fmt[i] == 'e') |
f8a8fc7b | 1323 | scan_rtx_address (insn, &XEXP (x, i), cl, action, mode, as); |
1140e77e | 1324 | else if (fmt[i] == 'E') |
1325 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
f8a8fc7b | 1326 | scan_rtx_address (insn, &XVECEXP (x, i, j), cl, action, mode, as); |
31659b75 | 1327 | } |
b9a06185 | 1328 | } |
1329 | ||
1140e77e | 1330 | static void |
de67d37e | 1331 | scan_rtx (rtx insn, rtx *loc, enum reg_class cl, enum scan_actions action, |
1332 | enum op_type type) | |
b9a06185 | 1333 | { |
1140e77e | 1334 | const char *fmt; |
1335 | rtx x = *loc; | |
1336 | enum rtx_code code = GET_CODE (x); | |
1337 | int i, j; | |
b9a06185 | 1338 | |
1140e77e | 1339 | code = GET_CODE (x); |
1340 | switch (code) | |
b9a06185 | 1341 | { |
1140e77e | 1342 | case CONST: |
0349edce | 1343 | CASE_CONST_ANY: |
1140e77e | 1344 | case SYMBOL_REF: |
1345 | case LABEL_REF: | |
1346 | case CC0: | |
1347 | case PC: | |
1348 | return; | |
22d9265e | 1349 | |
1140e77e | 1350 | case REG: |
de67d37e | 1351 | scan_rtx_reg (insn, loc, cl, action, type); |
1140e77e | 1352 | return; |
b9a06185 | 1353 | |
1140e77e | 1354 | case MEM: |
2e6d14e8 | 1355 | scan_rtx_address (insn, &XEXP (x, 0), |
f8a8fc7b | 1356 | base_reg_class (GET_MODE (x), MEM_ADDR_SPACE (x), |
1357 | MEM, SCRATCH), | |
1358 | action, GET_MODE (x), MEM_ADDR_SPACE (x)); | |
1140e77e | 1359 | return; |
b9a06185 | 1360 | |
1140e77e | 1361 | case SET: |
de67d37e | 1362 | scan_rtx (insn, &SET_SRC (x), cl, action, OP_IN); |
72ab6a85 | 1363 | scan_rtx (insn, &SET_DEST (x), cl, action, |
83361a4c | 1364 | (GET_CODE (PATTERN (insn)) == COND_EXEC |
1365 | && verify_reg_tracked (SET_DEST (x))) ? OP_INOUT : OP_OUT); | |
1140e77e | 1366 | return; |
b9a06185 | 1367 | |
1140e77e | 1368 | case STRICT_LOW_PART: |
6581d87d | 1369 | scan_rtx (insn, &XEXP (x, 0), cl, action, |
1370 | verify_reg_tracked (XEXP (x, 0)) ? OP_INOUT : OP_OUT); | |
1140e77e | 1371 | return; |
b9a06185 | 1372 | |
1140e77e | 1373 | case ZERO_EXTRACT: |
709c2f34 | 1374 | case SIGN_EXTRACT: |
e916c70c | 1375 | scan_rtx (insn, &XEXP (x, 0), cl, action, |
6581d87d | 1376 | (type == OP_IN ? OP_IN : |
1377 | verify_reg_tracked (XEXP (x, 0)) ? OP_INOUT : OP_OUT)); | |
de67d37e | 1378 | scan_rtx (insn, &XEXP (x, 1), cl, action, OP_IN); |
1379 | scan_rtx (insn, &XEXP (x, 2), cl, action, OP_IN); | |
1140e77e | 1380 | return; |
b9a06185 | 1381 | |
1140e77e | 1382 | case POST_INC: |
1383 | case PRE_INC: | |
1384 | case POST_DEC: | |
1385 | case PRE_DEC: | |
1386 | case POST_MODIFY: | |
1387 | case PRE_MODIFY: | |
1388 | /* Should only happen inside MEM. */ | |
04e579b6 | 1389 | gcc_unreachable (); |
1140e77e | 1390 | |
1391 | case CLOBBER: | |
72ab6a85 | 1392 | scan_rtx (insn, &SET_DEST (x), cl, action, |
83361a4c | 1393 | (GET_CODE (PATTERN (insn)) == COND_EXEC |
1394 | && verify_reg_tracked (SET_DEST (x))) ? OP_INOUT : OP_OUT); | |
1140e77e | 1395 | return; |
b9a06185 | 1396 | |
1140e77e | 1397 | case EXPR_LIST: |
de67d37e | 1398 | scan_rtx (insn, &XEXP (x, 0), cl, action, type); |
1140e77e | 1399 | if (XEXP (x, 1)) |
de67d37e | 1400 | scan_rtx (insn, &XEXP (x, 1), cl, action, type); |
1140e77e | 1401 | return; |
b9a06185 | 1402 | |
1140e77e | 1403 | default: |
1404 | break; | |
1405 | } | |
b9a06185 | 1406 | |
1140e77e | 1407 | fmt = GET_RTX_FORMAT (code); |
1408 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
b9a06185 | 1409 | { |
1410 | if (fmt[i] == 'e') | |
de67d37e | 1411 | scan_rtx (insn, &XEXP (x, i), cl, action, type); |
b9a06185 | 1412 | else if (fmt[i] == 'E') |
1413 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
de67d37e | 1414 | scan_rtx (insn, &XVECEXP (x, i, j), cl, action, type); |
1415 | } | |
1416 | } | |
1417 | ||
1418 | /* Hide operands of the current insn (of which there are N_OPS) by | |
1419 | substituting cc0 for them. | |
1420 | Previous values are stored in the OLD_OPERANDS and OLD_DUPS. | |
c38fa63b | 1421 | For every bit set in DO_NOT_HIDE, we leave the operand alone. |
7197e178 | 1422 | If INOUT_AND_EC_ONLY is set, we only do this for OP_INOUT type operands |
1423 | and earlyclobbers. */ | |
de67d37e | 1424 | |
1425 | static void | |
1426 | hide_operands (int n_ops, rtx *old_operands, rtx *old_dups, | |
c38fa63b | 1427 | unsigned HOST_WIDE_INT do_not_hide, bool inout_and_ec_only) |
de67d37e | 1428 | { |
1429 | int i; | |
7197e178 | 1430 | int alt = which_alternative; |
de67d37e | 1431 | for (i = 0; i < n_ops; i++) |
1432 | { | |
1433 | old_operands[i] = recog_data.operand[i]; | |
1434 | /* Don't squash match_operator or match_parallel here, since | |
1435 | we don't know that all of the contained registers are | |
1436 | reachable by proper operands. */ | |
1437 | if (recog_data.constraints[i][0] == '\0') | |
1438 | continue; | |
c38fa63b | 1439 | if (do_not_hide & (1 << i)) |
1440 | continue; | |
7197e178 | 1441 | if (!inout_and_ec_only || recog_data.operand_type[i] == OP_INOUT |
1442 | || recog_op_alt[i][alt].earlyclobber) | |
de67d37e | 1443 | *recog_data.operand_loc[i] = cc0_rtx; |
1444 | } | |
1445 | for (i = 0; i < recog_data.n_dups; i++) | |
1446 | { | |
1447 | int opn = recog_data.dup_num[i]; | |
1448 | old_dups[i] = *recog_data.dup_loc[i]; | |
c38fa63b | 1449 | if (do_not_hide & (1 << opn)) |
1450 | continue; | |
7197e178 | 1451 | if (!inout_and_ec_only || recog_data.operand_type[opn] == OP_INOUT |
1452 | || recog_op_alt[opn][alt].earlyclobber) | |
de67d37e | 1453 | *recog_data.dup_loc[i] = cc0_rtx; |
1454 | } | |
1455 | } | |
1456 | ||
1457 | /* Undo the substitution performed by hide_operands. INSN is the insn we | |
1458 | are processing; the arguments are the same as in hide_operands. */ | |
1459 | ||
1460 | static void | |
1461 | restore_operands (rtx insn, int n_ops, rtx *old_operands, rtx *old_dups) | |
1462 | { | |
1463 | int i; | |
1464 | for (i = 0; i < recog_data.n_dups; i++) | |
1465 | *recog_data.dup_loc[i] = old_dups[i]; | |
1466 | for (i = 0; i < n_ops; i++) | |
1467 | *recog_data.operand_loc[i] = old_operands[i]; | |
1468 | if (recog_data.n_dups) | |
1469 | df_insn_rescan (insn); | |
1470 | } | |
1471 | ||
1472 | /* For each output operand of INSN, call scan_rtx to create a new | |
7197e178 | 1473 | open chain. Do this only for normal or earlyclobber outputs, |
7de639a2 | 1474 | depending on EARLYCLOBBER. If INSN_INFO is nonnull, use it to |
1475 | record information about the operands in the insn. */ | |
de67d37e | 1476 | |
1477 | static void | |
7de639a2 | 1478 | record_out_operands (rtx insn, bool earlyclobber, insn_rr_info *insn_info) |
de67d37e | 1479 | { |
1480 | int n_ops = recog_data.n_operands; | |
1481 | int alt = which_alternative; | |
1482 | ||
1483 | int i; | |
1484 | ||
1485 | for (i = 0; i < n_ops + recog_data.n_dups; i++) | |
1486 | { | |
1487 | int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops]; | |
1488 | rtx *loc = (i < n_ops | |
1489 | ? recog_data.operand_loc[opn] | |
1490 | : recog_data.dup_loc[i - n_ops]); | |
1491 | rtx op = *loc; | |
1492 | enum reg_class cl = recog_op_alt[opn][alt].cl; | |
1493 | ||
1494 | struct du_head *prev_open; | |
1495 | ||
7197e178 | 1496 | if (recog_data.operand_type[opn] != OP_OUT |
1497 | || recog_op_alt[opn][alt].earlyclobber != earlyclobber) | |
de67d37e | 1498 | continue; |
1499 | ||
7de639a2 | 1500 | if (insn_info) |
1501 | cur_operand = insn_info->op_info + i; | |
1502 | ||
de67d37e | 1503 | prev_open = open_chains; |
1504 | scan_rtx (insn, loc, cl, mark_write, OP_OUT); | |
1505 | ||
1506 | /* ??? Many targets have output constraints on the SET_DEST | |
1507 | of a call insn, which is stupid, since these are certainly | |
1508 | ABI defined hard registers. For these, and for asm operands | |
1509 | that originally referenced hard registers, we must record that | |
1510 | the chain cannot be renamed. */ | |
1511 | if (CALL_P (insn) | |
1512 | || (asm_noperands (PATTERN (insn)) > 0 | |
1513 | && REG_P (op) | |
1514 | && REGNO (op) == ORIGINAL_REGNO (op))) | |
1515 | { | |
1516 | if (prev_open != open_chains) | |
7197e178 | 1517 | open_chains->cannot_rename = 1; |
de67d37e | 1518 | } |
b9a06185 | 1519 | } |
7de639a2 | 1520 | cur_operand = NULL; |
b9a06185 | 1521 | } |
1522 | ||
45498ea1 | 1523 | /* Build def/use chain. */ |
b9a06185 | 1524 | |
31adcf56 | 1525 | static bool |
3ad4992f | 1526 | build_def_use (basic_block bb) |
b9a06185 | 1527 | { |
1140e77e | 1528 | rtx insn; |
c38fa63b | 1529 | unsigned HOST_WIDE_INT untracked_operands; |
d98fed9f | 1530 | |
7197e178 | 1531 | fail_current_block = false; |
1532 | ||
5496dbfc | 1533 | for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn)) |
1140e77e | 1534 | { |
9845d120 | 1535 | if (NONDEBUG_INSN_P (insn)) |
1140e77e | 1536 | { |
1537 | int n_ops; | |
1538 | rtx note; | |
1539 | rtx old_operands[MAX_RECOG_OPERANDS]; | |
1540 | rtx old_dups[MAX_DUP_OPERANDS]; | |
f018d957 | 1541 | int i; |
1140e77e | 1542 | int alt; |
1543 | int predicated; | |
7197e178 | 1544 | enum rtx_code set_code = SET; |
1545 | enum rtx_code clobber_code = CLOBBER; | |
7de639a2 | 1546 | insn_rr_info *insn_info = NULL; |
1140e77e | 1547 | |
1140e77e | 1548 | /* Process the insn, determining its effect on the def-use |
7197e178 | 1549 | chains and live hard registers. We perform the following |
1550 | steps with the register references in the insn, simulating | |
1551 | its effect: | |
1552 | (1) Deal with earlyclobber operands and CLOBBERs of non-operands | |
1553 | by creating chains and marking hard regs live. | |
1140e77e | 1554 | (2) Any read outside an operand causes any chain it overlaps |
7197e178 | 1555 | with to be marked unrenamable. |
1140e77e | 1556 | (3) Any read inside an operand is added if there's already |
1557 | an open chain for it. | |
1558 | (4) For any REG_DEAD note we find, close open chains that | |
1559 | overlap it. | |
7197e178 | 1560 | (5) For any non-earlyclobber write we find, close open chains |
1561 | that overlap it. | |
1562 | (6) For any non-earlyclobber write we find in an operand, make | |
1563 | a new chain or mark the hard register as live. | |
1564 | (7) For any REG_UNUSED, close any chains we just opened. | |
1565 | ||
1566 | We cannot deal with situations where we track a reg in one mode | |
1567 | and see a reference in another mode; these will cause the chain | |
1568 | to be marked unrenamable or even cause us to abort the entire | |
1569 | basic block. */ | |
1140e77e | 1570 | |
1571 | extract_insn (insn); | |
caeae6e1 | 1572 | if (! constrain_operands (1)) |
709c2f34 | 1573 | fatal_insn_not_found (insn); |
1140e77e | 1574 | preprocess_constraints (); |
1575 | alt = which_alternative; | |
1576 | n_ops = recog_data.n_operands; | |
c38fa63b | 1577 | untracked_operands = 0; |
1140e77e | 1578 | |
f1f41a6c | 1579 | if (insn_rr.exists ()) |
7de639a2 | 1580 | { |
f1f41a6c | 1581 | insn_info = &insn_rr[INSN_UID (insn)]; |
7de639a2 | 1582 | insn_info->op_info = XOBNEWVEC (&rename_obstack, operand_rr_info, |
1583 | recog_data.n_operands); | |
1584 | memset (insn_info->op_info, 0, | |
1585 | sizeof (operand_rr_info) * recog_data.n_operands); | |
1586 | } | |
1587 | ||
1140e77e | 1588 | /* Simplify the code below by rewriting things to reflect |
83361a4c | 1589 | matching constraints. Also promote OP_OUT to OP_INOUT in |
1590 | predicated instructions, but only for register operands | |
1591 | that are already tracked, so that we can create a chain | |
1592 | when the first SET makes a register live. */ | |
1140e77e | 1593 | |
1594 | predicated = GET_CODE (PATTERN (insn)) == COND_EXEC; | |
1595 | for (i = 0; i < n_ops; ++i) | |
b9a06185 | 1596 | { |
17db414f | 1597 | rtx op = recog_data.operand[i]; |
1140e77e | 1598 | int matches = recog_op_alt[i][alt].matches; |
1599 | if (matches >= 0) | |
e916c70c | 1600 | recog_op_alt[i][alt].cl = recog_op_alt[matches][alt].cl; |
1140e77e | 1601 | if (matches >= 0 || recog_op_alt[i][alt].matched >= 0 |
17db414f | 1602 | || (predicated && recog_data.operand_type[i] == OP_OUT)) |
7197e178 | 1603 | { |
1604 | recog_data.operand_type[i] = OP_INOUT; | |
c38fa63b | 1605 | /* A special case to deal with instruction patterns that |
1606 | have matching operands with different modes. If we're | |
1607 | not already tracking such a reg, we won't start here, | |
1608 | and we must instead make sure to make the operand visible | |
1609 | to the machinery that tracks hard registers. */ | |
7197e178 | 1610 | if (matches >= 0 |
1611 | && (GET_MODE_SIZE (recog_data.operand_mode[i]) | |
c38fa63b | 1612 | != GET_MODE_SIZE (recog_data.operand_mode[matches])) |
1613 | && !verify_reg_in_set (op, &live_in_chains)) | |
1614 | { | |
1615 | untracked_operands |= 1 << i; | |
1616 | untracked_operands |= 1 << matches; | |
1617 | } | |
7197e178 | 1618 | } |
6581d87d | 1619 | /* If there's an in-out operand with a register that is not |
17db414f | 1620 | being tracked at all yet, open a chain. */ |
6581d87d | 1621 | if (recog_data.operand_type[i] == OP_INOUT |
1622 | && !(untracked_operands & (1 << i)) | |
17db414f | 1623 | && REG_P (op) |
1624 | && !verify_reg_tracked (op)) | |
6581d87d | 1625 | { |
17db414f | 1626 | enum machine_mode mode = GET_MODE (op); |
1627 | unsigned this_regno = REGNO (op); | |
1628 | unsigned this_nregs = hard_regno_nregs[this_regno][mode]; | |
1629 | create_new_chain (this_regno, this_nregs, NULL, NULL_RTX, | |
1630 | NO_REGS); | |
6581d87d | 1631 | } |
b9a06185 | 1632 | } |
d98fed9f | 1633 | |
7197e178 | 1634 | if (fail_current_block) |
1635 | break; | |
1636 | ||
1637 | /* Step 1a: Mark hard registers that are clobbered in this insn, | |
1638 | outside an operand, as live. */ | |
c38fa63b | 1639 | hide_operands (n_ops, old_operands, old_dups, untracked_operands, |
1640 | false); | |
7197e178 | 1641 | note_stores (PATTERN (insn), note_sets_clobbers, &clobber_code); |
1642 | restore_operands (insn, n_ops, old_operands, old_dups); | |
1643 | ||
1644 | /* Step 1b: Begin new chains for earlyclobbered writes inside | |
1645 | operands. */ | |
7de639a2 | 1646 | record_out_operands (insn, true, insn_info); |
d98fed9f | 1647 | |
7197e178 | 1648 | /* Step 2: Mark chains for which we have reads outside operands |
1649 | as unrenamable. | |
709c2f34 | 1650 | We do this by munging all operands into CC0, and closing |
1140e77e | 1651 | everything remaining. */ |
b9a06185 | 1652 | |
c38fa63b | 1653 | hide_operands (n_ops, old_operands, old_dups, untracked_operands, |
1654 | false); | |
7197e178 | 1655 | scan_rtx (insn, &PATTERN (insn), NO_REGS, mark_all_read, OP_IN); |
de67d37e | 1656 | restore_operands (insn, n_ops, old_operands, old_dups); |
b9a06185 | 1657 | |
1140e77e | 1658 | /* Step 2B: Can't rename function call argument registers. */ |
6d7dc5b9 | 1659 | if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn)) |
1140e77e | 1660 | scan_rtx (insn, &CALL_INSN_FUNCTION_USAGE (insn), |
7197e178 | 1661 | NO_REGS, mark_all_read, OP_IN); |
b9a06185 | 1662 | |
a68730c1 | 1663 | /* Step 2C: Can't rename asm operands that were originally |
1664 | hard registers. */ | |
1665 | if (asm_noperands (PATTERN (insn)) > 0) | |
1666 | for (i = 0; i < n_ops; i++) | |
1667 | { | |
1668 | rtx *loc = recog_data.operand_loc[i]; | |
1669 | rtx op = *loc; | |
1670 | ||
8ad4c111 | 1671 | if (REG_P (op) |
a68730c1 | 1672 | && REGNO (op) == ORIGINAL_REGNO (op) |
1673 | && (recog_data.operand_type[i] == OP_IN | |
1674 | || recog_data.operand_type[i] == OP_INOUT)) | |
7197e178 | 1675 | scan_rtx (insn, loc, NO_REGS, mark_all_read, OP_IN); |
a68730c1 | 1676 | } |
1677 | ||
1140e77e | 1678 | /* Step 3: Append to chains for reads inside operands. */ |
1679 | for (i = 0; i < n_ops + recog_data.n_dups; i++) | |
1680 | { | |
1681 | int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops]; | |
1682 | rtx *loc = (i < n_ops | |
1683 | ? recog_data.operand_loc[opn] | |
1684 | : recog_data.dup_loc[i - n_ops]); | |
e916c70c | 1685 | enum reg_class cl = recog_op_alt[opn][alt].cl; |
1140e77e | 1686 | enum op_type type = recog_data.operand_type[opn]; |
1687 | ||
1688 | /* Don't scan match_operand here, since we've no reg class | |
1689 | information to pass down. Any operands that we could | |
1690 | substitute in will be represented elsewhere. */ | |
c38fa63b | 1691 | if (recog_data.constraints[opn][0] == '\0' |
1692 | || untracked_operands & (1 << opn)) | |
1140e77e | 1693 | continue; |
b9a06185 | 1694 | |
7de639a2 | 1695 | if (insn_info) |
1696 | cur_operand = i == opn ? insn_info->op_info + i : NULL; | |
1140e77e | 1697 | if (recog_op_alt[opn][alt].is_address) |
f8a8fc7b | 1698 | scan_rtx_address (insn, loc, cl, mark_read, |
1699 | VOIDmode, ADDR_SPACE_GENERIC); | |
1140e77e | 1700 | else |
de67d37e | 1701 | scan_rtx (insn, loc, cl, mark_read, type); |
1140e77e | 1702 | } |
7de639a2 | 1703 | cur_operand = NULL; |
b9a06185 | 1704 | |
b9d576f5 | 1705 | /* Step 3B: Record updates for regs in REG_INC notes, and |
1706 | source regs in REG_FRAME_RELATED_EXPR notes. */ | |
1140e77e | 1707 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
b9d576f5 | 1708 | if (REG_NOTE_KIND (note) == REG_INC |
1709 | || REG_NOTE_KIND (note) == REG_FRAME_RELATED_EXPR) | |
1710 | scan_rtx (insn, &XEXP (note, 0), ALL_REGS, mark_read, | |
de67d37e | 1711 | OP_INOUT); |
b9d576f5 | 1712 | |
1bcf869e | 1713 | /* Step 4: Close chains for registers that die here, unless |
1714 | the register is mentioned in a REG_UNUSED note. In that | |
1715 | case we keep the chain open until step #7 below to ensure | |
1716 | it conflicts with other output operands of this insn. | |
1717 | See PR 52573. Arguably the insn should not have both | |
1718 | notes; it has proven difficult to fix that without | |
1719 | other undesirable side effects. */ | |
b9d576f5 | 1720 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
1bcf869e | 1721 | if (REG_NOTE_KIND (note) == REG_DEAD |
1722 | && !find_regno_note (insn, REG_UNUSED, REGNO (XEXP (note, 0)))) | |
7197e178 | 1723 | { |
1724 | remove_from_hard_reg_set (&live_hard_regs, | |
1725 | GET_MODE (XEXP (note, 0)), | |
1726 | REGNO (XEXP (note, 0))); | |
1727 | scan_rtx (insn, &XEXP (note, 0), NO_REGS, terminate_dead, | |
1728 | OP_IN); | |
1729 | } | |
d98fed9f | 1730 | |
1140e77e | 1731 | /* Step 4B: If this is a call, any chain live at this point |
1732 | requires a caller-saved reg. */ | |
6d7dc5b9 | 1733 | if (CALL_P (insn)) |
1140e77e | 1734 | { |
bb6d4603 | 1735 | struct du_head *p; |
1140e77e | 1736 | for (p = open_chains; p; p = p->next_chain) |
d5dfb455 | 1737 | p->need_caller_save_reg = 1; |
1140e77e | 1738 | } |
b9a06185 | 1739 | |
1140e77e | 1740 | /* Step 5: Close open chains that overlap writes. Similar to |
1741 | step 2, we hide in-out operands, since we do not want to | |
7197e178 | 1742 | close these chains. We also hide earlyclobber operands, |
1743 | since we've opened chains for them in step 1, and earlier | |
1744 | chains they would overlap with must have been closed at | |
1745 | the previous insn at the latest, as such operands cannot | |
1746 | possibly overlap with any input operands. */ | |
b9a06185 | 1747 | |
c38fa63b | 1748 | hide_operands (n_ops, old_operands, old_dups, untracked_operands, |
1749 | true); | |
de67d37e | 1750 | scan_rtx (insn, &PATTERN (insn), NO_REGS, terminate_write, OP_IN); |
1751 | restore_operands (insn, n_ops, old_operands, old_dups); | |
b9a06185 | 1752 | |
7197e178 | 1753 | /* Step 6a: Mark hard registers that are set in this insn, |
1754 | outside an operand, as live. */ | |
c38fa63b | 1755 | hide_operands (n_ops, old_operands, old_dups, untracked_operands, |
1756 | false); | |
7197e178 | 1757 | note_stores (PATTERN (insn), note_sets_clobbers, &set_code); |
1758 | restore_operands (insn, n_ops, old_operands, old_dups); | |
b9a06185 | 1759 | |
7197e178 | 1760 | /* Step 6b: Begin new chains for writes inside operands. */ |
7de639a2 | 1761 | record_out_operands (insn, false, insn_info); |
7197e178 | 1762 | |
1763 | /* Step 6c: Record destination regs in REG_FRAME_RELATED_EXPR | |
b9d576f5 | 1764 | notes for update. */ |
1765 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
1766 | if (REG_NOTE_KIND (note) == REG_FRAME_RELATED_EXPR) | |
1767 | scan_rtx (insn, &XEXP (note, 0), ALL_REGS, mark_access, | |
de67d37e | 1768 | OP_INOUT); |
b9d576f5 | 1769 | |
1140e77e | 1770 | /* Step 7: Close chains for registers that were never |
1771 | really used here. */ | |
1772 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
1773 | if (REG_NOTE_KIND (note) == REG_UNUSED) | |
7197e178 | 1774 | { |
1775 | remove_from_hard_reg_set (&live_hard_regs, | |
1776 | GET_MODE (XEXP (note, 0)), | |
1777 | REGNO (XEXP (note, 0))); | |
1778 | scan_rtx (insn, &XEXP (note, 0), NO_REGS, terminate_dead, | |
1779 | OP_IN); | |
1780 | } | |
1140e77e | 1781 | } |
9845d120 | 1782 | else if (DEBUG_INSN_P (insn) |
1783 | && !VAR_LOC_UNKNOWN_P (INSN_VAR_LOCATION_LOC (insn))) | |
1784 | { | |
1785 | scan_rtx (insn, &INSN_VAR_LOCATION_LOC (insn), | |
de67d37e | 1786 | ALL_REGS, mark_read, OP_IN); |
9845d120 | 1787 | } |
5496dbfc | 1788 | if (insn == BB_END (bb)) |
1140e77e | 1789 | break; |
1790 | } | |
b9a06185 | 1791 | |
7197e178 | 1792 | if (fail_current_block) |
31adcf56 | 1793 | return false; |
7197e178 | 1794 | |
31adcf56 | 1795 | return true; |
1140e77e | 1796 | } |
77fce4cd | 1797 | \f |
7de639a2 | 1798 | /* Initialize the register renamer. If INSN_INFO is true, ensure that |
1799 | insn_rr is nonnull. */ | |
1800 | void | |
1801 | regrename_init (bool insn_info) | |
1802 | { | |
1803 | gcc_obstack_init (&rename_obstack); | |
f1f41a6c | 1804 | insn_rr.create (0); |
7de639a2 | 1805 | if (insn_info) |
f1f41a6c | 1806 | insn_rr.safe_grow_cleared (get_max_uid ()); |
7de639a2 | 1807 | } |
1808 | ||
1809 | /* Free all global data used by the register renamer. */ | |
1810 | void | |
1811 | regrename_finish (void) | |
1812 | { | |
f1f41a6c | 1813 | insn_rr.release (); |
7de639a2 | 1814 | free_chain_data (); |
1815 | obstack_free (&rename_obstack, NULL); | |
1816 | } | |
1817 | ||
92effe69 | 1818 | /* Perform register renaming on the current function. */ |
1819 | ||
1820 | static unsigned int | |
1821 | regrename_optimize (void) | |
1822 | { | |
92effe69 | 1823 | df_set_flags (DF_LR_RUN_DCE); |
1824 | df_note_add_problem (); | |
1825 | df_analyze (); | |
1826 | df_set_flags (DF_DEFER_INSN_RESCAN); | |
1827 | ||
7de639a2 | 1828 | regrename_init (false); |
92effe69 | 1829 | |
7de639a2 | 1830 | regrename_analyze (NULL); |
92effe69 | 1831 | |
31adcf56 | 1832 | rename_chains (); |
92effe69 | 1833 | |
7de639a2 | 1834 | regrename_finish (); |
92effe69 | 1835 | |
92effe69 | 1836 | return 0; |
1837 | } | |
1838 | \f | |
77fce4cd | 1839 | static bool |
1840 | gate_handle_regrename (void) | |
1841 | { | |
3072d30e | 1842 | return (optimize > 0 && (flag_rename_registers)); |
77fce4cd | 1843 | } |
1844 | ||
cbe8bda8 | 1845 | namespace { |
1846 | ||
1847 | const pass_data pass_data_regrename = | |
77fce4cd | 1848 | { |
cbe8bda8 | 1849 | RTL_PASS, /* type */ |
1850 | "rnreg", /* name */ | |
1851 | OPTGROUP_NONE, /* optinfo_flags */ | |
1852 | true, /* has_gate */ | |
1853 | true, /* has_execute */ | |
1854 | TV_RENAME_REGISTERS, /* tv_id */ | |
1855 | 0, /* properties_required */ | |
1856 | 0, /* properties_provided */ | |
1857 | 0, /* properties_destroyed */ | |
1858 | 0, /* todo_flags_start */ | |
1859 | ( TODO_df_finish | TODO_verify_rtl_sharing | 0 ), /* todo_flags_finish */ | |
3072d30e | 1860 | }; |
cbe8bda8 | 1861 | |
1862 | class pass_regrename : public rtl_opt_pass | |
1863 | { | |
1864 | public: | |
9af5ce0c | 1865 | pass_regrename (gcc::context *ctxt) |
1866 | : rtl_opt_pass (pass_data_regrename, ctxt) | |
cbe8bda8 | 1867 | {} |
1868 | ||
1869 | /* opt_pass methods: */ | |
1870 | bool gate () { return gate_handle_regrename (); } | |
1871 | unsigned int execute () { return regrename_optimize (); } | |
1872 | ||
1873 | }; // class pass_regrename | |
1874 | ||
1875 | } // anon namespace | |
1876 | ||
1877 | rtl_opt_pass * | |
1878 | make_pass_regrename (gcc::context *ctxt) | |
1879 | { | |
1880 | return new pass_regrename (ctxt); | |
1881 | } |