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c3bcc836 | 1 | /* Define per-register tables for data flow info and register allocation. |
cbe34bb5 | 2 | Copyright (C) 1987-2017 Free Software Foundation, Inc. |
c3bcc836 | 3 | |
1322177d | 4 | This file is part of GCC. |
c3bcc836 | 5 | |
1322177d LB |
6 | GCC is free software; you can redistribute it and/or modify it under |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 9 | version. |
c3bcc836 | 10 | |
1322177d LB |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
c3bcc836 RK |
15 | |
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
c3bcc836 | 19 | |
6de9cd9a DN |
20 | #ifndef GCC_REGS_H |
21 | #define GCC_REGS_H | |
c3bcc836 | 22 | |
c3bcc836 RK |
23 | #define REG_BYTES(R) mode_size[(int) GET_MODE (R)] |
24 | ||
ddef6bc7 JJ |
25 | /* When you only have the mode of a pseudo register before it has a hard |
26 | register chosen for it, this reports the size of each hard register | |
ec8e621d KG |
27 | a pseudo in such a mode would get allocated to. A target may |
28 | override this. */ | |
ddef6bc7 JJ |
29 | |
30 | #ifndef REGMODE_NATURAL_SIZE | |
31 | #define REGMODE_NATURAL_SIZE(MODE) UNITS_PER_WORD | |
32 | #endif | |
c3bcc836 RK |
33 | |
34 | /* Maximum register number used in this function, plus one. */ | |
35 | ||
36 | extern int max_regno; | |
37 | ||
6fb5fa3c DB |
38 | /* REG_N_REFS and REG_N_SETS are initialized by a call to |
39 | regstat_init_n_sets_and_refs from the current values of | |
40 | DF_REG_DEF_COUNT and DF_REG_USE_COUNT. REG_N_REFS and REG_N_SETS | |
41 | should only be used if a pass need to change these values in some | |
dd5a833e | 42 | magical way or the pass needs to have accurate values for these |
6fb5fa3c DB |
43 | and is not using incremental df scanning. |
44 | ||
45 | At the end of a pass that uses REG_N_REFS and REG_N_SETS, a call | |
b8698a0f | 46 | should be made to regstat_free_n_sets_and_refs. |
6fb5fa3c DB |
47 | |
48 | Local alloc seems to play pretty loose with these values. | |
49 | REG_N_REFS is set to 0 if the register is used in an asm. | |
50 | Furthermore, local_alloc calls regclass to hack both REG_N_REFS and | |
51 | REG_N_SETS for three address insns. Other passes seem to have | |
52 | other special values. */ | |
53 | ||
b1f21e0a | 54 | |
b1f21e0a | 55 | |
6fb5fa3c DB |
56 | /* Structure to hold values for REG_N_SETS (i) and REG_N_REFS (i). */ |
57 | ||
58 | struct regstat_n_sets_and_refs_t | |
59 | { | |
60 | int sets; /* # of times (REG n) is set */ | |
b1f21e0a | 61 | int refs; /* # of times (REG n) is used or set */ |
6fb5fa3c DB |
62 | }; |
63 | ||
64 | extern struct regstat_n_sets_and_refs_t *regstat_n_sets_and_refs; | |
65 | ||
66 | /* Indexed by n, gives number of times (REG n) is used or set. */ | |
67 | static inline int | |
c3284718 | 68 | REG_N_REFS (int regno) |
6fb5fa3c DB |
69 | { |
70 | return regstat_n_sets_and_refs[regno].refs; | |
71 | } | |
72 | ||
73 | /* Indexed by n, gives number of times (REG n) is used or set. */ | |
74 | #define SET_REG_N_REFS(N,V) (regstat_n_sets_and_refs[N].refs = V) | |
75 | #define INC_REG_N_REFS(N,V) (regstat_n_sets_and_refs[N].refs += V) | |
76 | ||
77 | /* Indexed by n, gives number of times (REG n) is set. */ | |
78 | static inline int | |
79 | REG_N_SETS (int regno) | |
80 | { | |
81 | return regstat_n_sets_and_refs[regno].sets; | |
82 | } | |
83 | ||
84 | /* Indexed by n, gives number of times (REG n) is set. */ | |
85 | #define SET_REG_N_SETS(N,V) (regstat_n_sets_and_refs[N].sets = V) | |
86 | #define INC_REG_N_SETS(N,V) (regstat_n_sets_and_refs[N].sets += V) | |
87 | ||
a698cc03 JL |
88 | /* Given a REG, return TRUE if the reg is a PARM_DECL, FALSE otherwise. */ |
89 | extern bool reg_is_parm_p (rtx); | |
6fb5fa3c | 90 | |
532aafad | 91 | /* Functions defined in regstat.c. */ |
6fb5fa3c DB |
92 | extern void regstat_init_n_sets_and_refs (void); |
93 | extern void regstat_free_n_sets_and_refs (void); | |
94 | extern void regstat_compute_ri (void); | |
95 | extern void regstat_free_ri (void); | |
96 | extern bitmap regstat_get_setjmp_crosses (void); | |
97 | extern void regstat_compute_calls_crossed (void); | |
98 | extern void regstat_free_calls_crossed (void); | |
532aafad | 99 | extern void dump_reg_info (FILE *); |
6fb5fa3c DB |
100 | |
101 | /* Register information indexed by register number. This structure is | |
102 | initialized by calling regstat_compute_ri and is destroyed by | |
103 | calling regstat_free_ri. */ | |
104 | struct reg_info_t | |
105 | { | |
b2aec5c0 | 106 | int freq; /* # estimated frequency (REG n) is used or set */ |
b1f21e0a | 107 | int deaths; /* # of times (REG n) dies */ |
b1f21e0a MM |
108 | int calls_crossed; /* # of calls (REG n) is live across */ |
109 | int basic_block; /* # of basic blocks (REG n) is used in */ | |
6fb5fa3c | 110 | }; |
1935e8a8 | 111 | |
6fb5fa3c | 112 | extern struct reg_info_t *reg_info_p; |
1935e8a8 | 113 | |
6fb5fa3c DB |
114 | /* The number allocated elements of reg_info_p. */ |
115 | extern size_t reg_info_p_size; | |
c3bcc836 | 116 | |
b2aec5c0 JH |
117 | /* Estimate frequency of references to register N. */ |
118 | ||
6fb5fa3c | 119 | #define REG_FREQ(N) (reg_info_p[N].freq) |
b2aec5c0 | 120 | |
fa10beec | 121 | /* The weights for each insn varies from 0 to REG_FREQ_BASE. |
a08b2604 JH |
122 | This constant does not need to be high, as in infrequently executed |
123 | regions we want to count instructions equivalently to optimize for | |
124 | size instead of speed. */ | |
125 | #define REG_FREQ_MAX 1000 | |
126 | ||
127 | /* Compute register frequency from the BB frequency. When optimizing for size, | |
128 | or profile driven feedback is available and the function is never executed, | |
129 | frequency is always equivalent. Otherwise rescale the basic block | |
130 | frequency. */ | |
cf40f973 | 131 | #define REG_FREQ_FROM_BB(bb) (optimize_function_for_size_p (cfun) \ |
a08b2604 | 132 | ? REG_FREQ_MAX \ |
e7a74006 JH |
133 | : ((bb)->count.to_frequency (cfun) \ |
134 | * REG_FREQ_MAX / BB_FREQ_MAX) \ | |
135 | ? ((bb)->count.to_frequency (cfun) \ | |
136 | * REG_FREQ_MAX / BB_FREQ_MAX) \ | |
a08b2604 JH |
137 | : 1) |
138 | ||
c3bcc836 RK |
139 | /* Indexed by N, gives number of insns in which register N dies. |
140 | Note that if register N is live around loops, it can die | |
141 | in transitions between basic blocks, and that is not counted here. | |
142 | So this is only a reliable indicator of how many regions of life there are | |
143 | for registers that are contained in one basic block. */ | |
144 | ||
6fb5fa3c | 145 | #define REG_N_DEATHS(N) (reg_info_p[N].deaths) |
c3bcc836 RK |
146 | |
147 | /* Get the number of consecutive words required to hold pseudo-reg N. */ | |
148 | ||
149 | #define PSEUDO_REGNO_SIZE(N) \ | |
150 | ((GET_MODE_SIZE (PSEUDO_REGNO_MODE (N)) + UNITS_PER_WORD - 1) \ | |
151 | / UNITS_PER_WORD) | |
152 | ||
153 | /* Get the number of bytes required to hold pseudo-reg N. */ | |
154 | ||
155 | #define PSEUDO_REGNO_BYTES(N) \ | |
156 | GET_MODE_SIZE (PSEUDO_REGNO_MODE (N)) | |
157 | ||
158 | /* Get the machine mode of pseudo-reg N. */ | |
159 | ||
160 | #define PSEUDO_REGNO_MODE(N) GET_MODE (regno_reg_rtx[N]) | |
161 | ||
162 | /* Indexed by N, gives number of CALL_INSNS across which (REG n) is live. */ | |
163 | ||
6fb5fa3c | 164 | #define REG_N_CALLS_CROSSED(N) (reg_info_p[N].calls_crossed) |
27004606 | 165 | |
6fb5fa3c DB |
166 | /* Indexed by n, gives number of basic block that (REG n) is used in. |
167 | If the value is REG_BLOCK_GLOBAL (-1), | |
168 | it means (REG n) is used in more than one basic block. | |
169 | REG_BLOCK_UNKNOWN (0) means it hasn't been seen yet so we don't know. | |
170 | This information remains valid for the rest of the compilation | |
171 | of the current function; it is used to control register allocation. */ | |
172 | ||
173 | #define REG_BLOCK_UNKNOWN 0 | |
174 | #define REG_BLOCK_GLOBAL -1 | |
175 | ||
176 | #define REG_BASIC_BLOCK(N) (reg_info_p[N].basic_block) | |
c3bcc836 RK |
177 | |
178 | /* Vector of substitutions of register numbers, | |
b1f21e0a MM |
179 | used to map pseudo regs into hardware regs. |
180 | ||
181 | This can't be folded into reg_n_info without changing all of the | |
182 | machine dependent directories, since the reload functions | |
39379e67 | 183 | in the machine dependent files access it. */ |
c3bcc836 RK |
184 | |
185 | extern short *reg_renumber; | |
186 | ||
c3bcc836 RK |
187 | /* Flag set by local-alloc or global-alloc if they decide to allocate |
188 | something in a call-clobbered register. */ | |
189 | ||
190 | extern int caller_save_needed; | |
191 | ||
8d5c8167 JL |
192 | /* Select a register mode required for caller save of hard regno REGNO. */ |
193 | #ifndef HARD_REGNO_CALLER_SAVE_MODE | |
787dc842 | 194 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
fee226d2 | 195 | choose_hard_reg_mode (REGNO, NREGS, false) |
8d5c8167 JL |
196 | #endif |
197 | ||
939dcd0d RS |
198 | /* Target-dependent globals. */ |
199 | struct target_regs { | |
200 | /* For each starting hard register, the number of consecutive hard | |
201 | registers that a given machine mode occupies. */ | |
202 | unsigned char x_hard_regno_nregs[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE]; | |
203 | ||
204 | /* For each hard register, the widest mode object that it can contain. | |
205 | This will be a MODE_INT mode if the register can hold integers. Otherwise | |
206 | it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the | |
207 | register. */ | |
ef4bddc2 | 208 | machine_mode x_reg_raw_mode[FIRST_PSEUDO_REGISTER]; |
55e78c8c RS |
209 | |
210 | /* Vector indexed by machine mode saying whether there are regs of | |
211 | that mode. */ | |
212 | bool x_have_regs_of_mode[MAX_MACHINE_MODE]; | |
213 | ||
214 | /* 1 if the corresponding class contains a register of the given mode. */ | |
215 | char x_contains_reg_of_mode[N_REG_CLASSES][MAX_MACHINE_MODE]; | |
216 | ||
4692943d BS |
217 | /* 1 if the corresponding class contains a register of the given mode |
218 | which is not global and can therefore be allocated. */ | |
219 | char x_contains_allocatable_reg_of_mode[N_REG_CLASSES][MAX_MACHINE_MODE]; | |
220 | ||
9d86796b RS |
221 | /* Record for each mode whether we can move a register directly to or |
222 | from an object of that mode in memory. If we can't, we won't try | |
223 | to use that mode directly when accessing a field of that mode. */ | |
224 | char x_direct_load[NUM_MACHINE_MODES]; | |
225 | char x_direct_store[NUM_MACHINE_MODES]; | |
226 | ||
227 | /* Record for each mode whether we can float-extend from memory. */ | |
228 | bool x_float_extend_from_mem[NUM_MACHINE_MODES][NUM_MACHINE_MODES]; | |
939dcd0d RS |
229 | }; |
230 | ||
231 | extern struct target_regs default_target_regs; | |
232 | #if SWITCHABLE_TARGET | |
233 | extern struct target_regs *this_target_regs; | |
234 | #else | |
235 | #define this_target_regs (&default_target_regs) | |
236 | #endif | |
939dcd0d RS |
237 | #define reg_raw_mode \ |
238 | (this_target_regs->x_reg_raw_mode) | |
55e78c8c RS |
239 | #define have_regs_of_mode \ |
240 | (this_target_regs->x_have_regs_of_mode) | |
241 | #define contains_reg_of_mode \ | |
242 | (this_target_regs->x_contains_reg_of_mode) | |
4692943d BS |
243 | #define contains_allocatable_reg_of_mode \ |
244 | (this_target_regs->x_contains_allocatable_reg_of_mode) | |
9d86796b RS |
245 | #define direct_load \ |
246 | (this_target_regs->x_direct_load) | |
247 | #define direct_store \ | |
248 | (this_target_regs->x_direct_store) | |
249 | #define float_extend_from_mem \ | |
250 | (this_target_regs->x_float_extend_from_mem) | |
939dcd0d | 251 | |
ad474626 RS |
252 | /* Return the number of hard registers in (reg:MODE REGNO). */ |
253 | ||
254 | ALWAYS_INLINE unsigned char | |
255 | hard_regno_nregs (unsigned int regno, machine_mode mode) | |
256 | { | |
257 | return this_target_regs->x_hard_regno_nregs[regno][mode]; | |
258 | } | |
259 | ||
09e18274 RS |
260 | /* Return an exclusive upper bound on the registers occupied by hard |
261 | register (reg:MODE REGNO). */ | |
262 | ||
263 | static inline unsigned int | |
ef4bddc2 | 264 | end_hard_regno (machine_mode mode, unsigned int regno) |
09e18274 | 265 | { |
ad474626 | 266 | return regno + hard_regno_nregs (regno, mode); |
09e18274 RS |
267 | } |
268 | ||
09e18274 RS |
269 | /* Add to REGS all the registers required to store a value of mode MODE |
270 | in register REGNO. */ | |
271 | ||
272 | static inline void | |
ef4bddc2 | 273 | add_to_hard_reg_set (HARD_REG_SET *regs, machine_mode mode, |
09e18274 RS |
274 | unsigned int regno) |
275 | { | |
276 | unsigned int end_regno; | |
277 | ||
278 | end_regno = end_hard_regno (mode, regno); | |
279 | do | |
280 | SET_HARD_REG_BIT (*regs, regno); | |
281 | while (++regno < end_regno); | |
282 | } | |
283 | ||
284 | /* Likewise, but remove the registers. */ | |
285 | ||
286 | static inline void | |
ef4bddc2 | 287 | remove_from_hard_reg_set (HARD_REG_SET *regs, machine_mode mode, |
09e18274 RS |
288 | unsigned int regno) |
289 | { | |
290 | unsigned int end_regno; | |
291 | ||
292 | end_regno = end_hard_regno (mode, regno); | |
293 | do | |
294 | CLEAR_HARD_REG_BIT (*regs, regno); | |
295 | while (++regno < end_regno); | |
296 | } | |
297 | ||
298 | /* Return true if REGS contains the whole of (reg:MODE REGNO). */ | |
299 | ||
300 | static inline bool | |
ef4bddc2 | 301 | in_hard_reg_set_p (const HARD_REG_SET regs, machine_mode mode, |
09e18274 RS |
302 | unsigned int regno) |
303 | { | |
304 | unsigned int end_regno; | |
305 | ||
e7bcc691 JM |
306 | gcc_assert (HARD_REGISTER_NUM_P (regno)); |
307 | ||
09e18274 RS |
308 | if (!TEST_HARD_REG_BIT (regs, regno)) |
309 | return false; | |
310 | ||
311 | end_regno = end_hard_regno (mode, regno); | |
e7bcc691 JM |
312 | |
313 | if (!HARD_REGISTER_NUM_P (end_regno - 1)) | |
314 | return false; | |
315 | ||
09e18274 RS |
316 | while (++regno < end_regno) |
317 | if (!TEST_HARD_REG_BIT (regs, regno)) | |
318 | return false; | |
319 | ||
320 | return true; | |
321 | } | |
322 | ||
323 | /* Return true if (reg:MODE REGNO) includes an element of REGS. */ | |
324 | ||
325 | static inline bool | |
ef4bddc2 | 326 | overlaps_hard_reg_set_p (const HARD_REG_SET regs, machine_mode mode, |
09e18274 RS |
327 | unsigned int regno) |
328 | { | |
329 | unsigned int end_regno; | |
330 | ||
331 | if (TEST_HARD_REG_BIT (regs, regno)) | |
332 | return true; | |
333 | ||
334 | end_regno = end_hard_regno (mode, regno); | |
335 | while (++regno < end_regno) | |
336 | if (TEST_HARD_REG_BIT (regs, regno)) | |
337 | return true; | |
338 | ||
339 | return false; | |
340 | } | |
341 | ||
8ffa0351 BS |
342 | /* Like add_to_hard_reg_set, but use a REGNO/NREGS range instead of |
343 | REGNO and MODE. */ | |
344 | ||
345 | static inline void | |
346 | add_range_to_hard_reg_set (HARD_REG_SET *regs, unsigned int regno, | |
347 | int nregs) | |
348 | { | |
349 | while (nregs-- > 0) | |
350 | SET_HARD_REG_BIT (*regs, regno + nregs); | |
351 | } | |
352 | ||
353 | /* Likewise, but remove the registers. */ | |
354 | ||
355 | static inline void | |
356 | remove_range_from_hard_reg_set (HARD_REG_SET *regs, unsigned int regno, | |
357 | int nregs) | |
358 | { | |
359 | while (nregs-- > 0) | |
360 | CLEAR_HARD_REG_BIT (*regs, regno + nregs); | |
361 | } | |
362 | ||
363 | /* Like overlaps_hard_reg_set_p, but use a REGNO/NREGS range instead of | |
364 | REGNO and MODE. */ | |
365 | static inline bool | |
366 | range_overlaps_hard_reg_set_p (const HARD_REG_SET set, unsigned regno, | |
367 | int nregs) | |
368 | { | |
369 | while (nregs-- > 0) | |
370 | if (TEST_HARD_REG_BIT (set, regno + nregs)) | |
371 | return true; | |
372 | return false; | |
373 | } | |
374 | ||
375 | /* Like in_hard_reg_set_p, but use a REGNO/NREGS range instead of | |
376 | REGNO and MODE. */ | |
377 | static inline bool | |
378 | range_in_hard_reg_set_p (const HARD_REG_SET set, unsigned regno, int nregs) | |
379 | { | |
380 | while (nregs-- > 0) | |
381 | if (!TEST_HARD_REG_BIT (set, regno + nregs)) | |
382 | return false; | |
383 | return true; | |
384 | } | |
385 | ||
27c07cc5 | 386 | /* Get registers used by given function call instruction. */ |
86bf2d46 | 387 | extern bool get_call_reg_set_usage (rtx_insn *insn, HARD_REG_SET *reg_set, |
27c07cc5 RO |
388 | HARD_REG_SET default_set); |
389 | ||
6de9cd9a | 390 | #endif /* GCC_REGS_H */ |