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eab89b90 | 1 | /* Search an insn for pseudo regs that must be in hard regs and are not. |
e5e809f4 | 2 | Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc. |
eab89b90 RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
eab89b90 RK |
20 | |
21 | ||
22 | /* This file contains subroutines used only from the file reload1.c. | |
23 | It knows how to scan one insn for operands and values | |
24 | that need to be copied into registers to make valid code. | |
25 | It also finds other operands and values which are valid | |
26 | but for which equivalent values in registers exist and | |
27 | ought to be used instead. | |
28 | ||
29 | Before processing the first insn of the function, call `init_reload'. | |
30 | ||
31 | To scan an insn, call `find_reloads'. This does two things: | |
32 | 1. sets up tables describing which values must be reloaded | |
33 | for this insn, and what kind of hard regs they must be reloaded into; | |
34 | 2. optionally record the locations where those values appear in | |
35 | the data, so they can be replaced properly later. | |
36 | This is done only if the second arg to `find_reloads' is nonzero. | |
37 | ||
38 | The third arg to `find_reloads' specifies the number of levels | |
39 | of indirect addressing supported by the machine. If it is zero, | |
40 | indirect addressing is not valid. If it is one, (MEM (REG n)) | |
41 | is valid even if (REG n) did not get a hard register; if it is two, | |
42 | (MEM (MEM (REG n))) is also valid even if (REG n) did not get a | |
43 | hard register, and similarly for higher values. | |
44 | ||
45 | Then you must choose the hard regs to reload those pseudo regs into, | |
46 | and generate appropriate load insns before this insn and perhaps | |
47 | also store insns after this insn. Set up the array `reload_reg_rtx' | |
48 | to contain the REG rtx's for the registers you used. In some | |
49 | cases `find_reloads' will return a nonzero value in `reload_reg_rtx' | |
50 | for certain reloads. Then that tells you which register to use, | |
51 | so you do not need to allocate one. But you still do need to add extra | |
52 | instructions to copy the value into and out of that register. | |
53 | ||
54 | Finally you must call `subst_reloads' to substitute the reload reg rtx's | |
55 | into the locations already recorded. | |
56 | ||
57 | NOTE SIDE EFFECTS: | |
58 | ||
59 | find_reloads can alter the operands of the instruction it is called on. | |
60 | ||
61 | 1. Two operands of any sort may be interchanged, if they are in a | |
62 | commutative instruction. | |
63 | This happens only if find_reloads thinks the instruction will compile | |
64 | better that way. | |
65 | ||
66 | 2. Pseudo-registers that are equivalent to constants are replaced | |
67 | with those constants if they are not in hard registers. | |
68 | ||
69 | 1 happens every time find_reloads is called. | |
70 | 2 happens only when REPLACE is 1, which is only when | |
71 | actually doing the reloads, not when just counting them. | |
72 | ||
73 | ||
74 | Using a reload register for several reloads in one insn: | |
75 | ||
76 | When an insn has reloads, it is considered as having three parts: | |
77 | the input reloads, the insn itself after reloading, and the output reloads. | |
78 | Reloads of values used in memory addresses are often needed for only one part. | |
79 | ||
80 | When this is so, reload_when_needed records which part needs the reload. | |
81 | Two reloads for different parts of the insn can share the same reload | |
82 | register. | |
83 | ||
84 | When a reload is used for addresses in multiple parts, or when it is | |
85 | an ordinary operand, it is classified as RELOAD_OTHER, and cannot share | |
86 | a register with any other reload. */ | |
87 | ||
88 | #define REG_OK_STRICT | |
89 | ||
90 | #include "config.h" | |
670ee920 | 91 | #include "system.h" |
eab89b90 RK |
92 | #include "rtl.h" |
93 | #include "insn-config.h" | |
94 | #include "insn-codes.h" | |
95 | #include "recog.h" | |
96 | #include "reload.h" | |
97 | #include "regs.h" | |
98 | #include "hard-reg-set.h" | |
99 | #include "flags.h" | |
100 | #include "real.h" | |
8a840ac9 | 101 | #include "output.h" |
55c22565 | 102 | #include "expr.h" |
10f0ad3d | 103 | #include "toplev.h" |
eab89b90 RK |
104 | |
105 | #ifndef REGISTER_MOVE_COST | |
106 | #define REGISTER_MOVE_COST(x, y) 2 | |
107 | #endif | |
858c3c8c ILT |
108 | |
109 | #ifndef REGNO_MODE_OK_FOR_BASE_P | |
110 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) REGNO_OK_FOR_BASE_P (REGNO) | |
111 | #endif | |
112 | ||
113 | #ifndef REG_MODE_OK_FOR_BASE_P | |
114 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
115 | #endif | |
eab89b90 RK |
116 | \f |
117 | /* The variables set up by `find_reloads' are: | |
118 | ||
119 | n_reloads number of distinct reloads needed; max reload # + 1 | |
120 | tables indexed by reload number | |
121 | reload_in rtx for value to reload from | |
122 | reload_out rtx for where to store reload-reg afterward if nec | |
123 | (often the same as reload_in) | |
124 | reload_reg_class enum reg_class, saying what regs to reload into | |
125 | reload_inmode enum machine_mode; mode this operand should have | |
126 | when reloaded, on input. | |
127 | reload_outmode enum machine_mode; mode this operand should have | |
128 | when reloaded, on output. | |
eab89b90 RK |
129 | reload_optional char, nonzero for an optional reload. |
130 | Optional reloads are ignored unless the | |
131 | value is already sitting in a register. | |
f5963e61 JL |
132 | reload_nongroup char, nonzero when a reload must use a register |
133 | not already allocated to a group. | |
eab89b90 RK |
134 | reload_inc int, positive amount to increment or decrement by if |
135 | reload_in is a PRE_DEC, PRE_INC, POST_DEC, POST_INC. | |
136 | Ignored otherwise (don't assume it is zero). | |
137 | reload_in_reg rtx. A reg for which reload_in is the equivalent. | |
138 | If reload_in is a symbol_ref which came from | |
139 | reg_equiv_constant, then this is the pseudo | |
140 | which has that symbol_ref as equivalent. | |
141 | reload_reg_rtx rtx. This is the register to reload into. | |
142 | If it is zero when `find_reloads' returns, | |
143 | you must find a suitable register in the class | |
144 | specified by reload_reg_class, and store here | |
145 | an rtx for that register with mode from | |
146 | reload_inmode or reload_outmode. | |
147 | reload_nocombine char, nonzero if this reload shouldn't be | |
148 | combined with another reload. | |
a8c9daeb RK |
149 | reload_opnum int, operand number being reloaded. This is |
150 | used to group related reloads and need not always | |
151 | be equal to the actual operand number in the insn, | |
152 | though it current will be; for in-out operands, it | |
153 | is one of the two operand numbers. | |
154 | reload_when_needed enum, classifies reload as needed either for | |
eab89b90 RK |
155 | addressing an input reload, addressing an output, |
156 | for addressing a non-reloaded mem ref, | |
157 | or for unspecified purposes (i.e., more than one | |
158 | of the above). | |
eab89b90 | 159 | reload_secondary_p int, 1 if this is a secondary register for one |
9ec7078b RK |
160 | or more reloads. |
161 | reload_secondary_in_reload | |
162 | reload_secondary_out_reload | |
163 | int, gives the reload number of a secondary | |
164 | reload, when needed; otherwise -1 | |
165 | reload_secondary_in_icode | |
166 | reload_secondary_out_icode | |
167 | enum insn_code, if a secondary reload is required, | |
eab89b90 RK |
168 | gives the INSN_CODE that uses the secondary |
169 | reload as a scratch register, or CODE_FOR_nothing | |
170 | if the secondary reload register is to be an | |
171 | intermediate register. */ | |
172 | int n_reloads; | |
173 | ||
174 | rtx reload_in[MAX_RELOADS]; | |
175 | rtx reload_out[MAX_RELOADS]; | |
176 | enum reg_class reload_reg_class[MAX_RELOADS]; | |
177 | enum machine_mode reload_inmode[MAX_RELOADS]; | |
178 | enum machine_mode reload_outmode[MAX_RELOADS]; | |
eab89b90 RK |
179 | rtx reload_reg_rtx[MAX_RELOADS]; |
180 | char reload_optional[MAX_RELOADS]; | |
f5963e61 | 181 | char reload_nongroup[MAX_RELOADS]; |
eab89b90 RK |
182 | int reload_inc[MAX_RELOADS]; |
183 | rtx reload_in_reg[MAX_RELOADS]; | |
184 | char reload_nocombine[MAX_RELOADS]; | |
a8c9daeb RK |
185 | int reload_opnum[MAX_RELOADS]; |
186 | enum reload_type reload_when_needed[MAX_RELOADS]; | |
eab89b90 | 187 | int reload_secondary_p[MAX_RELOADS]; |
9ec7078b RK |
188 | int reload_secondary_in_reload[MAX_RELOADS]; |
189 | int reload_secondary_out_reload[MAX_RELOADS]; | |
190 | enum insn_code reload_secondary_in_icode[MAX_RELOADS]; | |
191 | enum insn_code reload_secondary_out_icode[MAX_RELOADS]; | |
eab89b90 RK |
192 | |
193 | /* All the "earlyclobber" operands of the current insn | |
194 | are recorded here. */ | |
195 | int n_earlyclobbers; | |
196 | rtx reload_earlyclobbers[MAX_RECOG_OPERANDS]; | |
197 | ||
a8c9daeb RK |
198 | int reload_n_operands; |
199 | ||
eab89b90 RK |
200 | /* Replacing reloads. |
201 | ||
202 | If `replace_reloads' is nonzero, then as each reload is recorded | |
203 | an entry is made for it in the table `replacements'. | |
204 | Then later `subst_reloads' can look through that table and | |
205 | perform all the replacements needed. */ | |
206 | ||
207 | /* Nonzero means record the places to replace. */ | |
208 | static int replace_reloads; | |
209 | ||
210 | /* Each replacement is recorded with a structure like this. */ | |
211 | struct replacement | |
212 | { | |
213 | rtx *where; /* Location to store in */ | |
214 | rtx *subreg_loc; /* Location of SUBREG if WHERE is inside | |
215 | a SUBREG; 0 otherwise. */ | |
216 | int what; /* which reload this is for */ | |
217 | enum machine_mode mode; /* mode it must have */ | |
218 | }; | |
219 | ||
220 | static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; | |
221 | ||
222 | /* Number of replacements currently recorded. */ | |
223 | static int n_replacements; | |
224 | ||
a8c9daeb RK |
225 | /* Used to track what is modified by an operand. */ |
226 | struct decomposition | |
227 | { | |
0f41302f MS |
228 | int reg_flag; /* Nonzero if referencing a register. */ |
229 | int safe; /* Nonzero if this can't conflict with anything. */ | |
230 | rtx base; /* Base address for MEM. */ | |
231 | HOST_WIDE_INT start; /* Starting offset or register number. */ | |
2a6d5ce0 | 232 | HOST_WIDE_INT end; /* Ending offset or register number. */ |
a8c9daeb RK |
233 | }; |
234 | ||
eab89b90 RK |
235 | /* MEM-rtx's created for pseudo-regs in stack slots not directly addressable; |
236 | (see reg_equiv_address). */ | |
237 | static rtx memlocs[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; | |
238 | static int n_memlocs; | |
239 | ||
0dadecf6 RK |
240 | #ifdef SECONDARY_MEMORY_NEEDED |
241 | ||
242 | /* Save MEMs needed to copy from one class of registers to another. One MEM | |
243 | is used per mode, but normally only one or two modes are ever used. | |
244 | ||
a8c9daeb RK |
245 | We keep two versions, before and after register elimination. The one |
246 | after register elimination is record separately for each operand. This | |
247 | is done in case the address is not valid to be sure that we separately | |
248 | reload each. */ | |
0dadecf6 RK |
249 | |
250 | static rtx secondary_memlocs[NUM_MACHINE_MODES]; | |
77545d45 | 251 | static rtx secondary_memlocs_elim[NUM_MACHINE_MODES][MAX_RECOG_OPERANDS]; |
0dadecf6 RK |
252 | #endif |
253 | ||
eab89b90 RK |
254 | /* The instruction we are doing reloads for; |
255 | so we can test whether a register dies in it. */ | |
256 | static rtx this_insn; | |
257 | ||
258 | /* Nonzero if this instruction is a user-specified asm with operands. */ | |
259 | static int this_insn_is_asm; | |
260 | ||
261 | /* If hard_regs_live_known is nonzero, | |
262 | we can tell which hard regs are currently live, | |
263 | at least enough to succeed in choosing dummy reloads. */ | |
264 | static int hard_regs_live_known; | |
265 | ||
266 | /* Indexed by hard reg number, | |
956d6950 | 267 | element is nonnegative if hard reg has been spilled. |
eab89b90 RK |
268 | This vector is passed to `find_reloads' as an argument |
269 | and is not changed here. */ | |
270 | static short *static_reload_reg_p; | |
271 | ||
272 | /* Set to 1 in subst_reg_equivs if it changes anything. */ | |
273 | static int subst_reg_equivs_changed; | |
274 | ||
275 | /* On return from push_reload, holds the reload-number for the OUT | |
276 | operand, which can be different for that from the input operand. */ | |
277 | static int output_reloadnum; | |
278 | ||
9ec7078b RK |
279 | /* Compare two RTX's. */ |
280 | #define MATCHES(x, y) \ | |
281 | (x == y || (x != 0 && (GET_CODE (x) == REG \ | |
282 | ? GET_CODE (y) == REG && REGNO (x) == REGNO (y) \ | |
283 | : rtx_equal_p (x, y) && ! side_effects_p (x)))) | |
284 | ||
285 | /* Indicates if two reloads purposes are for similar enough things that we | |
286 | can merge their reloads. */ | |
287 | #define MERGABLE_RELOADS(when1, when2, op1, op2) \ | |
288 | ((when1) == RELOAD_OTHER || (when2) == RELOAD_OTHER \ | |
289 | || ((when1) == (when2) && (op1) == (op2)) \ | |
290 | || ((when1) == RELOAD_FOR_INPUT && (when2) == RELOAD_FOR_INPUT) \ | |
291 | || ((when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
292 | && (when2) == RELOAD_FOR_OPERAND_ADDRESS) \ | |
293 | || ((when1) == RELOAD_FOR_OTHER_ADDRESS \ | |
294 | && (when2) == RELOAD_FOR_OTHER_ADDRESS)) | |
295 | ||
296 | /* Nonzero if these two reload purposes produce RELOAD_OTHER when merged. */ | |
297 | #define MERGE_TO_OTHER(when1, when2, op1, op2) \ | |
298 | ((when1) != (when2) \ | |
299 | || ! ((op1) == (op2) \ | |
300 | || (when1) == RELOAD_FOR_INPUT \ | |
301 | || (when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
302 | || (when1) == RELOAD_FOR_OTHER_ADDRESS)) | |
303 | ||
47c8cf91 ILT |
304 | /* If we are going to reload an address, compute the reload type to |
305 | use. */ | |
306 | #define ADDR_TYPE(type) \ | |
307 | ((type) == RELOAD_FOR_INPUT_ADDRESS \ | |
308 | ? RELOAD_FOR_INPADDR_ADDRESS \ | |
309 | : ((type) == RELOAD_FOR_OUTPUT_ADDRESS \ | |
310 | ? RELOAD_FOR_OUTADDR_ADDRESS \ | |
311 | : (type))) | |
312 | ||
56c5d8bf | 313 | #ifdef HAVE_SECONDARY_RELOADS |
9ec7078b RK |
314 | static int push_secondary_reload PROTO((int, rtx, int, int, enum reg_class, |
315 | enum machine_mode, enum reload_type, | |
316 | enum insn_code *)); | |
56c5d8bf | 317 | #endif |
c6716840 | 318 | static enum reg_class find_valid_class PROTO((enum machine_mode, int)); |
a8c9daeb RK |
319 | static int push_reload PROTO((rtx, rtx, rtx *, rtx *, enum reg_class, |
320 | enum machine_mode, enum machine_mode, | |
321 | int, int, int, enum reload_type)); | |
322 | static void push_replacement PROTO((rtx *, int, enum machine_mode)); | |
323 | static void combine_reloads PROTO((void)); | |
324 | static rtx find_dummy_reload PROTO((rtx, rtx, rtx *, rtx *, | |
36b50568 | 325 | enum machine_mode, enum machine_mode, |
189086f9 | 326 | enum reg_class, int, int)); |
4644aad4 | 327 | static int earlyclobber_operand_p PROTO((rtx)); |
a8c9daeb RK |
328 | static int hard_reg_set_here_p PROTO((int, int, rtx)); |
329 | static struct decomposition decompose PROTO((rtx)); | |
330 | static int immune_p PROTO((rtx, rtx, struct decomposition)); | |
331 | static int alternative_allows_memconst PROTO((char *, int)); | |
332 | static rtx find_reloads_toplev PROTO((rtx, int, enum reload_type, int, int)); | |
333 | static rtx make_memloc PROTO((rtx, int)); | |
334 | static int find_reloads_address PROTO((enum machine_mode, rtx *, rtx, rtx *, | |
55c22565 | 335 | int, enum reload_type, int, rtx)); |
a8c9daeb RK |
336 | static rtx subst_reg_equivs PROTO((rtx)); |
337 | static rtx subst_indexed_address PROTO((rtx)); | |
858c3c8c | 338 | static int find_reloads_address_1 PROTO((enum machine_mode, rtx, int, rtx *, |
55c22565 | 339 | int, enum reload_type,int, rtx)); |
a8c9daeb RK |
340 | static void find_reloads_address_part PROTO((rtx, rtx *, enum reg_class, |
341 | enum machine_mode, int, | |
342 | enum reload_type, int)); | |
343 | static int find_inc_amount PROTO((rtx, rtx)); | |
eab89b90 RK |
344 | \f |
345 | #ifdef HAVE_SECONDARY_RELOADS | |
346 | ||
347 | /* Determine if any secondary reloads are needed for loading (if IN_P is | |
348 | non-zero) or storing (if IN_P is zero) X to or from a reload register of | |
9ec7078b RK |
349 | register class RELOAD_CLASS in mode RELOAD_MODE. If secondary reloads |
350 | are needed, push them. | |
351 | ||
352 | Return the reload number of the secondary reload we made, or -1 if | |
353 | we didn't need one. *PICODE is set to the insn_code to use if we do | |
354 | need a secondary reload. */ | |
355 | ||
356 | static int | |
357 | push_secondary_reload (in_p, x, opnum, optional, reload_class, reload_mode, | |
358 | type, picode) | |
359 | int in_p; | |
eab89b90 | 360 | rtx x; |
9ec7078b RK |
361 | int opnum; |
362 | int optional; | |
eab89b90 RK |
363 | enum reg_class reload_class; |
364 | enum machine_mode reload_mode; | |
9ec7078b | 365 | enum reload_type type; |
eab89b90 | 366 | enum insn_code *picode; |
eab89b90 RK |
367 | { |
368 | enum reg_class class = NO_REGS; | |
369 | enum machine_mode mode = reload_mode; | |
370 | enum insn_code icode = CODE_FOR_nothing; | |
371 | enum reg_class t_class = NO_REGS; | |
372 | enum machine_mode t_mode = VOIDmode; | |
373 | enum insn_code t_icode = CODE_FOR_nothing; | |
d94d2abc | 374 | enum reload_type secondary_type; |
9ec7078b RK |
375 | int s_reload, t_reload = -1; |
376 | ||
47c8cf91 ILT |
377 | if (type == RELOAD_FOR_INPUT_ADDRESS |
378 | || type == RELOAD_FOR_OUTPUT_ADDRESS | |
379 | || type == RELOAD_FOR_INPADDR_ADDRESS | |
380 | || type == RELOAD_FOR_OUTADDR_ADDRESS) | |
d94d2abc RK |
381 | secondary_type = type; |
382 | else | |
383 | secondary_type = in_p ? RELOAD_FOR_INPUT_ADDRESS : RELOAD_FOR_OUTPUT_ADDRESS; | |
384 | ||
9ec7078b | 385 | *picode = CODE_FOR_nothing; |
eab89b90 | 386 | |
67340b03 RK |
387 | /* If X is a paradoxical SUBREG, use the inner value to determine both the |
388 | mode and object being reloaded. */ | |
389 | if (GET_CODE (x) == SUBREG | |
390 | && (GET_MODE_SIZE (GET_MODE (x)) | |
391 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
392 | { | |
393 | x = SUBREG_REG (x); | |
394 | reload_mode = GET_MODE (x); | |
395 | } | |
396 | ||
d45cf215 RS |
397 | /* If X is a pseudo-register that has an equivalent MEM (actually, if it |
398 | is still a pseudo-register by now, it *must* have an equivalent MEM | |
399 | but we don't want to assume that), use that equivalent when seeing if | |
400 | a secondary reload is needed since whether or not a reload is needed | |
401 | might be sensitive to the form of the MEM. */ | |
402 | ||
403 | if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
404 | && reg_equiv_mem[REGNO (x)] != 0) | |
405 | x = reg_equiv_mem[REGNO (x)]; | |
406 | ||
eab89b90 RK |
407 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
408 | if (in_p) | |
409 | class = SECONDARY_INPUT_RELOAD_CLASS (reload_class, reload_mode, x); | |
410 | #endif | |
411 | ||
412 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
413 | if (! in_p) | |
414 | class = SECONDARY_OUTPUT_RELOAD_CLASS (reload_class, reload_mode, x); | |
415 | #endif | |
416 | ||
9ec7078b | 417 | /* If we don't need any secondary registers, done. */ |
eab89b90 | 418 | if (class == NO_REGS) |
9ec7078b | 419 | return -1; |
eab89b90 RK |
420 | |
421 | /* Get a possible insn to use. If the predicate doesn't accept X, don't | |
422 | use the insn. */ | |
423 | ||
424 | icode = (in_p ? reload_in_optab[(int) reload_mode] | |
425 | : reload_out_optab[(int) reload_mode]); | |
426 | ||
427 | if (icode != CODE_FOR_nothing | |
428 | && insn_operand_predicate[(int) icode][in_p] | |
429 | && (! (insn_operand_predicate[(int) icode][in_p]) (x, reload_mode))) | |
430 | icode = CODE_FOR_nothing; | |
431 | ||
432 | /* If we will be using an insn, see if it can directly handle the reload | |
433 | register we will be using. If it can, the secondary reload is for a | |
434 | scratch register. If it can't, we will use the secondary reload for | |
435 | an intermediate register and require a tertiary reload for the scratch | |
436 | register. */ | |
437 | ||
438 | if (icode != CODE_FOR_nothing) | |
439 | { | |
440 | /* If IN_P is non-zero, the reload register will be the output in | |
441 | operand 0. If IN_P is zero, the reload register will be the input | |
442 | in operand 1. Outputs should have an initial "=", which we must | |
443 | skip. */ | |
444 | ||
d45cf215 | 445 | char insn_letter = insn_operand_constraint[(int) icode][!in_p][in_p]; |
eab89b90 | 446 | enum reg_class insn_class |
d45cf215 RS |
447 | = (insn_letter == 'r' ? GENERAL_REGS |
448 | : REG_CLASS_FROM_LETTER (insn_letter)); | |
eab89b90 RK |
449 | |
450 | if (insn_class == NO_REGS | |
451 | || (in_p && insn_operand_constraint[(int) icode][!in_p][0] != '=') | |
452 | /* The scratch register's constraint must start with "=&". */ | |
453 | || insn_operand_constraint[(int) icode][2][0] != '=' | |
454 | || insn_operand_constraint[(int) icode][2][1] != '&') | |
455 | abort (); | |
456 | ||
457 | if (reg_class_subset_p (reload_class, insn_class)) | |
458 | mode = insn_operand_mode[(int) icode][2]; | |
459 | else | |
460 | { | |
d45cf215 | 461 | char t_letter = insn_operand_constraint[(int) icode][2][2]; |
eab89b90 RK |
462 | class = insn_class; |
463 | t_mode = insn_operand_mode[(int) icode][2]; | |
d45cf215 RS |
464 | t_class = (t_letter == 'r' ? GENERAL_REGS |
465 | : REG_CLASS_FROM_LETTER (t_letter)); | |
eab89b90 RK |
466 | t_icode = icode; |
467 | icode = CODE_FOR_nothing; | |
468 | } | |
469 | } | |
470 | ||
9ec7078b RK |
471 | /* This case isn't valid, so fail. Reload is allowed to use the same |
472 | register for RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT reloads, but | |
473 | in the case of a secondary register, we actually need two different | |
474 | registers for correct code. We fail here to prevent the possibility of | |
475 | silently generating incorrect code later. | |
476 | ||
477 | The convention is that secondary input reloads are valid only if the | |
478 | secondary_class is different from class. If you have such a case, you | |
479 | can not use secondary reloads, you must work around the problem some | |
480 | other way. | |
481 | ||
482 | Allow this when MODE is not reload_mode and assume that the generated | |
483 | code handles this case (it does on the Alpha, which is the only place | |
484 | this currently happens). */ | |
485 | ||
486 | if (in_p && class == reload_class && mode == reload_mode) | |
487 | abort (); | |
488 | ||
489 | /* If we need a tertiary reload, see if we have one we can reuse or else | |
490 | make a new one. */ | |
491 | ||
492 | if (t_class != NO_REGS) | |
493 | { | |
494 | for (t_reload = 0; t_reload < n_reloads; t_reload++) | |
495 | if (reload_secondary_p[t_reload] | |
496 | && (reg_class_subset_p (t_class, reload_reg_class[t_reload]) | |
497 | || reg_class_subset_p (reload_reg_class[t_reload], t_class)) | |
498 | && ((in_p && reload_inmode[t_reload] == t_mode) | |
499 | || (! in_p && reload_outmode[t_reload] == t_mode)) | |
500 | && ((in_p && (reload_secondary_in_icode[t_reload] | |
501 | == CODE_FOR_nothing)) | |
502 | || (! in_p &&(reload_secondary_out_icode[t_reload] | |
503 | == CODE_FOR_nothing))) | |
e9a25f70 | 504 | && (reg_class_size[(int) t_class] == 1 || SMALL_REGISTER_CLASSES) |
9ec7078b RK |
505 | && MERGABLE_RELOADS (secondary_type, |
506 | reload_when_needed[t_reload], | |
507 | opnum, reload_opnum[t_reload])) | |
508 | { | |
509 | if (in_p) | |
510 | reload_inmode[t_reload] = t_mode; | |
511 | if (! in_p) | |
512 | reload_outmode[t_reload] = t_mode; | |
513 | ||
514 | if (reg_class_subset_p (t_class, reload_reg_class[t_reload])) | |
515 | reload_reg_class[t_reload] = t_class; | |
516 | ||
517 | reload_opnum[t_reload] = MIN (reload_opnum[t_reload], opnum); | |
518 | reload_optional[t_reload] &= optional; | |
519 | reload_secondary_p[t_reload] = 1; | |
520 | if (MERGE_TO_OTHER (secondary_type, reload_when_needed[t_reload], | |
521 | opnum, reload_opnum[t_reload])) | |
522 | reload_when_needed[t_reload] = RELOAD_OTHER; | |
523 | } | |
524 | ||
525 | if (t_reload == n_reloads) | |
526 | { | |
527 | /* We need to make a new tertiary reload for this register class. */ | |
528 | reload_in[t_reload] = reload_out[t_reload] = 0; | |
529 | reload_reg_class[t_reload] = t_class; | |
530 | reload_inmode[t_reload] = in_p ? t_mode : VOIDmode; | |
531 | reload_outmode[t_reload] = ! in_p ? t_mode : VOIDmode; | |
532 | reload_reg_rtx[t_reload] = 0; | |
533 | reload_optional[t_reload] = optional; | |
f5963e61 | 534 | reload_nongroup[t_reload] = 0; |
9ec7078b RK |
535 | reload_inc[t_reload] = 0; |
536 | /* Maybe we could combine these, but it seems too tricky. */ | |
537 | reload_nocombine[t_reload] = 1; | |
538 | reload_in_reg[t_reload] = 0; | |
539 | reload_opnum[t_reload] = opnum; | |
540 | reload_when_needed[t_reload] = secondary_type; | |
541 | reload_secondary_in_reload[t_reload] = -1; | |
542 | reload_secondary_out_reload[t_reload] = -1; | |
543 | reload_secondary_in_icode[t_reload] = CODE_FOR_nothing; | |
544 | reload_secondary_out_icode[t_reload] = CODE_FOR_nothing; | |
545 | reload_secondary_p[t_reload] = 1; | |
546 | ||
547 | n_reloads++; | |
548 | } | |
549 | } | |
550 | ||
551 | /* See if we can reuse an existing secondary reload. */ | |
552 | for (s_reload = 0; s_reload < n_reloads; s_reload++) | |
553 | if (reload_secondary_p[s_reload] | |
554 | && (reg_class_subset_p (class, reload_reg_class[s_reload]) | |
555 | || reg_class_subset_p (reload_reg_class[s_reload], class)) | |
556 | && ((in_p && reload_inmode[s_reload] == mode) | |
557 | || (! in_p && reload_outmode[s_reload] == mode)) | |
558 | && ((in_p && reload_secondary_in_reload[s_reload] == t_reload) | |
559 | || (! in_p && reload_secondary_out_reload[s_reload] == t_reload)) | |
560 | && ((in_p && reload_secondary_in_icode[s_reload] == t_icode) | |
561 | || (! in_p && reload_secondary_out_icode[s_reload] == t_icode)) | |
e9a25f70 | 562 | && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES) |
9ec7078b RK |
563 | && MERGABLE_RELOADS (secondary_type, reload_when_needed[s_reload], |
564 | opnum, reload_opnum[s_reload])) | |
565 | { | |
566 | if (in_p) | |
567 | reload_inmode[s_reload] = mode; | |
568 | if (! in_p) | |
569 | reload_outmode[s_reload] = mode; | |
570 | ||
571 | if (reg_class_subset_p (class, reload_reg_class[s_reload])) | |
572 | reload_reg_class[s_reload] = class; | |
573 | ||
574 | reload_opnum[s_reload] = MIN (reload_opnum[s_reload], opnum); | |
575 | reload_optional[s_reload] &= optional; | |
576 | reload_secondary_p[s_reload] = 1; | |
577 | if (MERGE_TO_OTHER (secondary_type, reload_when_needed[s_reload], | |
578 | opnum, reload_opnum[s_reload])) | |
579 | reload_when_needed[s_reload] = RELOAD_OTHER; | |
580 | } | |
eab89b90 | 581 | |
9ec7078b RK |
582 | if (s_reload == n_reloads) |
583 | { | |
e9a25f70 JL |
584 | #ifdef SECONDARY_MEMORY_NEEDED |
585 | /* If we need a memory location to copy between the two reload regs, | |
586 | set it up now. Note that we do the input case before making | |
587 | the reload and the output case after. This is due to the | |
588 | way reloads are output. */ | |
589 | ||
590 | if (in_p && icode == CODE_FOR_nothing | |
591 | && SECONDARY_MEMORY_NEEDED (class, reload_class, mode)) | |
592 | get_secondary_mem (x, reload_mode, opnum, type); | |
593 | #endif | |
594 | ||
9ec7078b RK |
595 | /* We need to make a new secondary reload for this register class. */ |
596 | reload_in[s_reload] = reload_out[s_reload] = 0; | |
597 | reload_reg_class[s_reload] = class; | |
598 | ||
599 | reload_inmode[s_reload] = in_p ? mode : VOIDmode; | |
600 | reload_outmode[s_reload] = ! in_p ? mode : VOIDmode; | |
601 | reload_reg_rtx[s_reload] = 0; | |
602 | reload_optional[s_reload] = optional; | |
f5963e61 | 603 | reload_nongroup[s_reload] = 0; |
9ec7078b RK |
604 | reload_inc[s_reload] = 0; |
605 | /* Maybe we could combine these, but it seems too tricky. */ | |
606 | reload_nocombine[s_reload] = 1; | |
607 | reload_in_reg[s_reload] = 0; | |
608 | reload_opnum[s_reload] = opnum; | |
609 | reload_when_needed[s_reload] = secondary_type; | |
610 | reload_secondary_in_reload[s_reload] = in_p ? t_reload : -1; | |
611 | reload_secondary_out_reload[s_reload] = ! in_p ? t_reload : -1; | |
612 | reload_secondary_in_icode[s_reload] = in_p ? t_icode : CODE_FOR_nothing; | |
613 | reload_secondary_out_icode[s_reload] | |
614 | = ! in_p ? t_icode : CODE_FOR_nothing; | |
615 | reload_secondary_p[s_reload] = 1; | |
616 | ||
617 | n_reloads++; | |
618 | ||
619 | #ifdef SECONDARY_MEMORY_NEEDED | |
9ec7078b | 620 | if (! in_p && icode == CODE_FOR_nothing |
f49e4127 JW |
621 | && SECONDARY_MEMORY_NEEDED (reload_class, class, mode)) |
622 | get_secondary_mem (x, mode, opnum, type); | |
9ec7078b RK |
623 | #endif |
624 | } | |
625 | ||
626 | *picode = icode; | |
627 | return s_reload; | |
eab89b90 RK |
628 | } |
629 | #endif /* HAVE_SECONDARY_RELOADS */ | |
630 | \f | |
0dadecf6 RK |
631 | #ifdef SECONDARY_MEMORY_NEEDED |
632 | ||
633 | /* Return a memory location that will be used to copy X in mode MODE. | |
634 | If we haven't already made a location for this mode in this insn, | |
635 | call find_reloads_address on the location being returned. */ | |
636 | ||
637 | rtx | |
a8c9daeb | 638 | get_secondary_mem (x, mode, opnum, type) |
0dadecf6 RK |
639 | rtx x; |
640 | enum machine_mode mode; | |
a8c9daeb RK |
641 | int opnum; |
642 | enum reload_type type; | |
0dadecf6 RK |
643 | { |
644 | rtx loc; | |
645 | int mem_valid; | |
646 | ||
64609742 RK |
647 | /* By default, if MODE is narrower than a word, widen it to a word. |
648 | This is required because most machines that require these memory | |
649 | locations do not support short load and stores from all registers | |
650 | (e.g., FP registers). */ | |
651 | ||
652 | #ifdef SECONDARY_MEMORY_NEEDED_MODE | |
653 | mode = SECONDARY_MEMORY_NEEDED_MODE (mode); | |
654 | #else | |
0dadecf6 RK |
655 | if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD) |
656 | mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0); | |
64609742 | 657 | #endif |
0dadecf6 | 658 | |
77545d45 RK |
659 | /* If we already have made a MEM for this operand in MODE, return it. */ |
660 | if (secondary_memlocs_elim[(int) mode][opnum] != 0) | |
661 | return secondary_memlocs_elim[(int) mode][opnum]; | |
0dadecf6 RK |
662 | |
663 | /* If this is the first time we've tried to get a MEM for this mode, | |
664 | allocate a new one. `something_changed' in reload will get set | |
665 | by noticing that the frame size has changed. */ | |
666 | ||
667 | if (secondary_memlocs[(int) mode] == 0) | |
b24a53d5 JW |
668 | { |
669 | #ifdef SECONDARY_MEMORY_NEEDED_RTX | |
670 | secondary_memlocs[(int) mode] = SECONDARY_MEMORY_NEEDED_RTX (mode); | |
671 | #else | |
672 | secondary_memlocs[(int) mode] | |
673 | = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); | |
674 | #endif | |
675 | } | |
0dadecf6 RK |
676 | |
677 | /* Get a version of the address doing any eliminations needed. If that | |
678 | didn't give us a new MEM, make a new one if it isn't valid. */ | |
679 | ||
1914f5da | 680 | loc = eliminate_regs (secondary_memlocs[(int) mode], VOIDmode, NULL_RTX); |
0dadecf6 RK |
681 | mem_valid = strict_memory_address_p (mode, XEXP (loc, 0)); |
682 | ||
683 | if (! mem_valid && loc == secondary_memlocs[(int) mode]) | |
684 | loc = copy_rtx (loc); | |
685 | ||
686 | /* The only time the call below will do anything is if the stack | |
687 | offset is too large. In that case IND_LEVELS doesn't matter, so we | |
a8c9daeb RK |
688 | can just pass a zero. Adjust the type to be the address of the |
689 | corresponding object. If the address was valid, save the eliminated | |
690 | address. If it wasn't valid, we need to make a reload each time, so | |
691 | don't save it. */ | |
0dadecf6 | 692 | |
a8c9daeb RK |
693 | if (! mem_valid) |
694 | { | |
695 | type = (type == RELOAD_FOR_INPUT ? RELOAD_FOR_INPUT_ADDRESS | |
696 | : type == RELOAD_FOR_OUTPUT ? RELOAD_FOR_OUTPUT_ADDRESS | |
697 | : RELOAD_OTHER); | |
8d618585 | 698 | |
a8c9daeb | 699 | find_reloads_address (mode, NULL_PTR, XEXP (loc, 0), &XEXP (loc, 0), |
55c22565 | 700 | opnum, type, 0, 0); |
a8c9daeb | 701 | } |
0dadecf6 | 702 | |
77545d45 | 703 | secondary_memlocs_elim[(int) mode][opnum] = loc; |
0dadecf6 RK |
704 | return loc; |
705 | } | |
706 | ||
707 | /* Clear any secondary memory locations we've made. */ | |
708 | ||
709 | void | |
710 | clear_secondary_mem () | |
711 | { | |
4c9a05bc | 712 | bzero ((char *) secondary_memlocs, sizeof secondary_memlocs); |
0dadecf6 RK |
713 | } |
714 | #endif /* SECONDARY_MEMORY_NEEDED */ | |
715 | \f | |
c6716840 RK |
716 | /* Find the largest class for which every register number plus N is valid in |
717 | M1 (if in range). Abort if no such class exists. */ | |
718 | ||
719 | static enum reg_class | |
720 | find_valid_class (m1, n) | |
721 | enum machine_mode m1; | |
722 | int n; | |
723 | { | |
724 | int class; | |
725 | int regno; | |
726 | enum reg_class best_class; | |
727 | int best_size = 0; | |
728 | ||
729 | for (class = 1; class < N_REG_CLASSES; class++) | |
730 | { | |
731 | int bad = 0; | |
732 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER && ! bad; regno++) | |
733 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
734 | && TEST_HARD_REG_BIT (reg_class_contents[class], regno + n) | |
735 | && ! HARD_REGNO_MODE_OK (regno + n, m1)) | |
736 | bad = 1; | |
737 | ||
738 | if (! bad && reg_class_size[class] > best_size) | |
739 | best_class = class, best_size = reg_class_size[class]; | |
740 | } | |
741 | ||
742 | if (best_size == 0) | |
743 | abort (); | |
744 | ||
745 | return best_class; | |
746 | } | |
747 | \f | |
a8c9daeb | 748 | /* Record one reload that needs to be performed. |
eab89b90 RK |
749 | IN is an rtx saying where the data are to be found before this instruction. |
750 | OUT says where they must be stored after the instruction. | |
751 | (IN is zero for data not read, and OUT is zero for data not written.) | |
752 | INLOC and OUTLOC point to the places in the instructions where | |
753 | IN and OUT were found. | |
a8c9daeb RK |
754 | If IN and OUT are both non-zero, it means the same register must be used |
755 | to reload both IN and OUT. | |
756 | ||
eab89b90 RK |
757 | CLASS is a register class required for the reloaded data. |
758 | INMODE is the machine mode that the instruction requires | |
759 | for the reg that replaces IN and OUTMODE is likewise for OUT. | |
760 | ||
761 | If IN is zero, then OUT's location and mode should be passed as | |
762 | INLOC and INMODE. | |
763 | ||
764 | STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx. | |
765 | ||
766 | OPTIONAL nonzero means this reload does not need to be performed: | |
767 | it can be discarded if that is more convenient. | |
768 | ||
a8c9daeb RK |
769 | OPNUM and TYPE say what the purpose of this reload is. |
770 | ||
eab89b90 RK |
771 | The return value is the reload-number for this reload. |
772 | ||
773 | If both IN and OUT are nonzero, in some rare cases we might | |
774 | want to make two separate reloads. (Actually we never do this now.) | |
775 | Therefore, the reload-number for OUT is stored in | |
776 | output_reloadnum when we return; the return value applies to IN. | |
777 | Usually (presently always), when IN and OUT are nonzero, | |
778 | the two reload-numbers are equal, but the caller should be careful to | |
779 | distinguish them. */ | |
780 | ||
781 | static int | |
782 | push_reload (in, out, inloc, outloc, class, | |
a8c9daeb | 783 | inmode, outmode, strict_low, optional, opnum, type) |
eab89b90 RK |
784 | register rtx in, out; |
785 | rtx *inloc, *outloc; | |
786 | enum reg_class class; | |
787 | enum machine_mode inmode, outmode; | |
788 | int strict_low; | |
789 | int optional; | |
a8c9daeb RK |
790 | int opnum; |
791 | enum reload_type type; | |
eab89b90 RK |
792 | { |
793 | register int i; | |
794 | int dont_share = 0; | |
74347d76 | 795 | int dont_remove_subreg = 0; |
eab89b90 | 796 | rtx *in_subreg_loc = 0, *out_subreg_loc = 0; |
9ec7078b | 797 | int secondary_in_reload = -1, secondary_out_reload = -1; |
a229128d RK |
798 | enum insn_code secondary_in_icode = CODE_FOR_nothing; |
799 | enum insn_code secondary_out_icode = CODE_FOR_nothing; | |
a8c9daeb | 800 | |
eab89b90 RK |
801 | /* INMODE and/or OUTMODE could be VOIDmode if no mode |
802 | has been specified for the operand. In that case, | |
803 | use the operand's mode as the mode to reload. */ | |
804 | if (inmode == VOIDmode && in != 0) | |
805 | inmode = GET_MODE (in); | |
806 | if (outmode == VOIDmode && out != 0) | |
807 | outmode = GET_MODE (out); | |
808 | ||
809 | /* If IN is a pseudo register everywhere-equivalent to a constant, and | |
810 | it is not in a hard register, reload straight from the constant, | |
811 | since we want to get rid of such pseudo registers. | |
812 | Often this is done earlier, but not always in find_reloads_address. */ | |
813 | if (in != 0 && GET_CODE (in) == REG) | |
814 | { | |
815 | register int regno = REGNO (in); | |
816 | ||
817 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
818 | && reg_equiv_constant[regno] != 0) | |
819 | in = reg_equiv_constant[regno]; | |
820 | } | |
821 | ||
822 | /* Likewise for OUT. Of course, OUT will never be equivalent to | |
823 | an actual constant, but it might be equivalent to a memory location | |
824 | (in the case of a parameter). */ | |
825 | if (out != 0 && GET_CODE (out) == REG) | |
826 | { | |
827 | register int regno = REGNO (out); | |
828 | ||
829 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
830 | && reg_equiv_constant[regno] != 0) | |
831 | out = reg_equiv_constant[regno]; | |
832 | } | |
833 | ||
834 | /* If we have a read-write operand with an address side-effect, | |
835 | change either IN or OUT so the side-effect happens only once. */ | |
836 | if (in != 0 && out != 0 && GET_CODE (in) == MEM && rtx_equal_p (in, out)) | |
837 | { | |
838 | if (GET_CODE (XEXP (in, 0)) == POST_INC | |
839 | || GET_CODE (XEXP (in, 0)) == POST_DEC) | |
38a448ca | 840 | in = gen_rtx_MEM (GET_MODE (in), XEXP (XEXP (in, 0), 0)); |
eab89b90 RK |
841 | if (GET_CODE (XEXP (in, 0)) == PRE_INC |
842 | || GET_CODE (XEXP (in, 0)) == PRE_DEC) | |
38a448ca | 843 | out = gen_rtx_MEM (GET_MODE (out), XEXP (XEXP (out, 0), 0)); |
eab89b90 RK |
844 | } |
845 | ||
a61c98cf | 846 | /* If we are reloading a (SUBREG constant ...), really reload just the |
ca769828 | 847 | inside expression in its own mode. Similarly for (SUBREG (PLUS ...)). |
a61c98cf RK |
848 | If we have (SUBREG:M1 (MEM:M2 ...) ...) (or an inner REG that is still |
849 | a pseudo and hence will become a MEM) with M1 wider than M2 and the | |
850 | register is a pseudo, also reload the inside expression. | |
f72ccbe6 | 851 | For machines that extend byte loads, do this for any SUBREG of a pseudo |
486d8509 RK |
852 | where both M1 and M2 are a word or smaller, M1 is wider than M2, and |
853 | M2 is an integral mode that gets extended when loaded. | |
86c31b2d | 854 | Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
eab89b90 RK |
855 | either M1 is not valid for R or M2 is wider than a word but we only |
856 | need one word to store an M2-sized quantity in R. | |
86c31b2d RS |
857 | (However, if OUT is nonzero, we need to reload the reg *and* |
858 | the subreg, so do nothing here, and let following statement handle it.) | |
859 | ||
eab89b90 RK |
860 | Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere; |
861 | we can't handle it here because CONST_INT does not indicate a mode. | |
862 | ||
863 | Similarly, we must reload the inside expression if we have a | |
df62f951 RK |
864 | STRICT_LOW_PART (presumably, in == out in the cas). |
865 | ||
866 | Also reload the inner expression if it does not require a secondary | |
486d8509 RK |
867 | reload but the SUBREG does. |
868 | ||
869 | Finally, reload the inner expression if it is a register that is in | |
870 | the class whose registers cannot be referenced in a different size | |
d030f4b2 RK |
871 | and M1 is not the same size as M2. If SUBREG_WORD is nonzero, we |
872 | cannot reload just the inside since we might end up with the wrong | |
0f41302f | 873 | register class. */ |
eab89b90 | 874 | |
d030f4b2 | 875 | if (in != 0 && GET_CODE (in) == SUBREG && SUBREG_WORD (in) == 0 |
94bafba7 RK |
876 | #ifdef CLASS_CANNOT_CHANGE_SIZE |
877 | && class != CLASS_CANNOT_CHANGE_SIZE | |
878 | #endif | |
a61c98cf | 879 | && (CONSTANT_P (SUBREG_REG (in)) |
ca769828 | 880 | || GET_CODE (SUBREG_REG (in)) == PLUS |
eab89b90 | 881 | || strict_low |
a61c98cf RK |
882 | || (((GET_CODE (SUBREG_REG (in)) == REG |
883 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER) | |
884 | || GET_CODE (SUBREG_REG (in)) == MEM) | |
03b72c86 RK |
885 | && ((GET_MODE_SIZE (inmode) |
886 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
09bf0250 | 887 | #ifdef LOAD_EXTEND_OP |
03b72c86 RK |
888 | || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD |
889 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
890 | <= UNITS_PER_WORD) | |
891 | && (GET_MODE_SIZE (inmode) | |
486d8509 RK |
892 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) |
893 | && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in))) | |
894 | && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != NIL) | |
d2c92f5a R |
895 | #endif |
896 | #ifdef WORD_REGISTER_OPERATIONS | |
897 | || ((GET_MODE_SIZE (inmode) | |
898 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
899 | && ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD == | |
900 | ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) - 1) | |
901 | / UNITS_PER_WORD))) | |
f72ccbe6 | 902 | #endif |
03b72c86 | 903 | )) |
a61c98cf RK |
904 | || (GET_CODE (SUBREG_REG (in)) == REG |
905 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER | |
86c31b2d RS |
906 | /* The case where out is nonzero |
907 | is handled differently in the following statement. */ | |
908 | && (out == 0 || SUBREG_WORD (in) == 0) | |
f72ccbe6 RK |
909 | && ((GET_MODE_SIZE (inmode) <= UNITS_PER_WORD |
910 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
911 | > UNITS_PER_WORD) | |
912 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
913 | / UNITS_PER_WORD) | |
914 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)), | |
915 | GET_MODE (SUBREG_REG (in))))) | |
916 | || ! HARD_REGNO_MODE_OK ((REGNO (SUBREG_REG (in)) | |
917 | + SUBREG_WORD (in)), | |
918 | inmode))) | |
df62f951 RK |
919 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
920 | || (SECONDARY_INPUT_RELOAD_CLASS (class, inmode, in) != NO_REGS | |
921 | && (SECONDARY_INPUT_RELOAD_CLASS (class, | |
922 | GET_MODE (SUBREG_REG (in)), | |
923 | SUBREG_REG (in)) | |
924 | == NO_REGS)) | |
486d8509 RK |
925 | #endif |
926 | #ifdef CLASS_CANNOT_CHANGE_SIZE | |
927 | || (GET_CODE (SUBREG_REG (in)) == REG | |
928 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER | |
929 | && (TEST_HARD_REG_BIT | |
930 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], | |
931 | REGNO (SUBREG_REG (in)))) | |
932 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
933 | != GET_MODE_SIZE (inmode))) | |
df62f951 RK |
934 | #endif |
935 | )) | |
eab89b90 RK |
936 | { |
937 | in_subreg_loc = inloc; | |
938 | inloc = &SUBREG_REG (in); | |
939 | in = *inloc; | |
d2c92f5a | 940 | #if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS) |
eab89b90 RK |
941 | if (GET_CODE (in) == MEM) |
942 | /* This is supposed to happen only for paradoxical subregs made by | |
943 | combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */ | |
944 | if (GET_MODE_SIZE (GET_MODE (in)) > GET_MODE_SIZE (inmode)) | |
945 | abort (); | |
e05a9da8 | 946 | #endif |
eab89b90 RK |
947 | inmode = GET_MODE (in); |
948 | } | |
949 | ||
86c31b2d RS |
950 | /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
951 | either M1 is not valid for R or M2 is wider than a word but we only | |
952 | need one word to store an M2-sized quantity in R. | |
953 | ||
954 | However, we must reload the inner reg *as well as* the subreg in | |
955 | that case. */ | |
956 | ||
6fd5ac08 JW |
957 | /* Similar issue for (SUBREG constant ...) if it was not handled by the |
958 | code above. This can happen if SUBREG_WORD != 0. */ | |
959 | ||
86c31b2d | 960 | if (in != 0 && GET_CODE (in) == SUBREG |
6fd5ac08 JW |
961 | && (CONSTANT_P (SUBREG_REG (in)) |
962 | || (GET_CODE (SUBREG_REG (in)) == REG | |
963 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER | |
964 | && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (in)) | |
965 | + SUBREG_WORD (in), | |
966 | inmode) | |
967 | || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD | |
968 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
969 | > UNITS_PER_WORD) | |
970 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
971 | / UNITS_PER_WORD) | |
972 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)), | |
973 | GET_MODE (SUBREG_REG (in))))))))) | |
86c31b2d | 974 | { |
c96d01ab RK |
975 | /* This relies on the fact that emit_reload_insns outputs the |
976 | instructions for input reloads of type RELOAD_OTHER in the same | |
977 | order as the reloads. Thus if the outer reload is also of type | |
978 | RELOAD_OTHER, we are guaranteed that this inner reload will be | |
979 | output before the outer reload. */ | |
86c31b2d | 980 | push_reload (SUBREG_REG (in), NULL_RTX, &SUBREG_REG (in), NULL_PTR, |
c6716840 RK |
981 | find_valid_class (inmode, SUBREG_WORD (in)), |
982 | VOIDmode, VOIDmode, 0, 0, opnum, type); | |
74347d76 | 983 | dont_remove_subreg = 1; |
86c31b2d RS |
984 | } |
985 | ||
eab89b90 RK |
986 | /* Similarly for paradoxical and problematical SUBREGs on the output. |
987 | Note that there is no reason we need worry about the previous value | |
988 | of SUBREG_REG (out); even if wider than out, | |
989 | storing in a subreg is entitled to clobber it all | |
990 | (except in the case of STRICT_LOW_PART, | |
991 | and in that case the constraint should label it input-output.) */ | |
d030f4b2 | 992 | if (out != 0 && GET_CODE (out) == SUBREG && SUBREG_WORD (out) == 0 |
94bafba7 RK |
993 | #ifdef CLASS_CANNOT_CHANGE_SIZE |
994 | && class != CLASS_CANNOT_CHANGE_SIZE | |
995 | #endif | |
a61c98cf | 996 | && (CONSTANT_P (SUBREG_REG (out)) |
eab89b90 | 997 | || strict_low |
a61c98cf RK |
998 | || (((GET_CODE (SUBREG_REG (out)) == REG |
999 | && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER) | |
1000 | || GET_CODE (SUBREG_REG (out)) == MEM) | |
03b72c86 | 1001 | && ((GET_MODE_SIZE (outmode) |
1914f5da RH |
1002 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) |
1003 | #ifdef WORD_REGISTER_OPERATIONS | |
6d49a073 JW |
1004 | || ((GET_MODE_SIZE (outmode) |
1005 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
1006 | && ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD == | |
1007 | ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) - 1) | |
1008 | / UNITS_PER_WORD))) | |
1914f5da RH |
1009 | #endif |
1010 | )) | |
eab89b90 RK |
1011 | || (GET_CODE (SUBREG_REG (out)) == REG |
1012 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER | |
f72ccbe6 RK |
1013 | && ((GET_MODE_SIZE (outmode) <= UNITS_PER_WORD |
1014 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1015 | > UNITS_PER_WORD) | |
1016 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1017 | / UNITS_PER_WORD) | |
1018 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)), | |
1019 | GET_MODE (SUBREG_REG (out))))) | |
1020 | || ! HARD_REGNO_MODE_OK ((REGNO (SUBREG_REG (out)) | |
1021 | + SUBREG_WORD (out)), | |
1022 | outmode))) | |
df62f951 RK |
1023 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
1024 | || (SECONDARY_OUTPUT_RELOAD_CLASS (class, outmode, out) != NO_REGS | |
1025 | && (SECONDARY_OUTPUT_RELOAD_CLASS (class, | |
1026 | GET_MODE (SUBREG_REG (out)), | |
1027 | SUBREG_REG (out)) | |
1028 | == NO_REGS)) | |
486d8509 RK |
1029 | #endif |
1030 | #ifdef CLASS_CANNOT_CHANGE_SIZE | |
1031 | || (GET_CODE (SUBREG_REG (out)) == REG | |
1032 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER | |
1033 | && (TEST_HARD_REG_BIT | |
1034 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], | |
1035 | REGNO (SUBREG_REG (out)))) | |
1036 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1037 | != GET_MODE_SIZE (outmode))) | |
df62f951 RK |
1038 | #endif |
1039 | )) | |
eab89b90 RK |
1040 | { |
1041 | out_subreg_loc = outloc; | |
1042 | outloc = &SUBREG_REG (out); | |
e05a9da8 | 1043 | out = *outloc; |
d2c92f5a | 1044 | #if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS) |
e05a9da8 | 1045 | if (GET_CODE (out) == MEM |
eab89b90 RK |
1046 | && GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode)) |
1047 | abort (); | |
e05a9da8 | 1048 | #endif |
eab89b90 RK |
1049 | outmode = GET_MODE (out); |
1050 | } | |
1051 | ||
74347d76 RK |
1052 | /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
1053 | either M1 is not valid for R or M2 is wider than a word but we only | |
1054 | need one word to store an M2-sized quantity in R. | |
1055 | ||
1056 | However, we must reload the inner reg *as well as* the subreg in | |
1057 | that case. In this case, the inner reg is an in-out reload. */ | |
1058 | ||
1059 | if (out != 0 && GET_CODE (out) == SUBREG | |
1060 | && GET_CODE (SUBREG_REG (out)) == REG | |
1061 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER | |
c6716840 RK |
1062 | && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (out)) + SUBREG_WORD (out), |
1063 | outmode) | |
74347d76 RK |
1064 | || (GET_MODE_SIZE (outmode) <= UNITS_PER_WORD |
1065 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1066 | > UNITS_PER_WORD) | |
1067 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1068 | / UNITS_PER_WORD) | |
1069 | != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)), | |
1070 | GET_MODE (SUBREG_REG (out))))))) | |
1071 | { | |
c96d01ab RK |
1072 | /* This relies on the fact that emit_reload_insns outputs the |
1073 | instructions for output reloads of type RELOAD_OTHER in reverse | |
1074 | order of the reloads. Thus if the outer reload is also of type | |
1075 | RELOAD_OTHER, we are guaranteed that this inner reload will be | |
1076 | output after the outer reload. */ | |
74347d76 RK |
1077 | dont_remove_subreg = 1; |
1078 | push_reload (SUBREG_REG (out), SUBREG_REG (out), &SUBREG_REG (out), | |
c6716840 RK |
1079 | &SUBREG_REG (out), |
1080 | find_valid_class (outmode, SUBREG_WORD (out)), | |
1081 | VOIDmode, VOIDmode, 0, 0, | |
74347d76 RK |
1082 | opnum, RELOAD_OTHER); |
1083 | } | |
1084 | ||
eab89b90 RK |
1085 | /* If IN appears in OUT, we can't share any input-only reload for IN. */ |
1086 | if (in != 0 && out != 0 && GET_CODE (out) == MEM | |
1087 | && (GET_CODE (in) == REG || GET_CODE (in) == MEM) | |
bfa30b22 | 1088 | && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0))) |
eab89b90 RK |
1089 | dont_share = 1; |
1090 | ||
0dadecf6 RK |
1091 | /* If IN is a SUBREG of a hard register, make a new REG. This |
1092 | simplifies some of the cases below. */ | |
1093 | ||
1094 | if (in != 0 && GET_CODE (in) == SUBREG && GET_CODE (SUBREG_REG (in)) == REG | |
74347d76 RK |
1095 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER |
1096 | && ! dont_remove_subreg) | |
38a448ca RH |
1097 | in = gen_rtx_REG (GET_MODE (in), |
1098 | REGNO (SUBREG_REG (in)) + SUBREG_WORD (in)); | |
0dadecf6 RK |
1099 | |
1100 | /* Similarly for OUT. */ | |
1101 | if (out != 0 && GET_CODE (out) == SUBREG | |
1102 | && GET_CODE (SUBREG_REG (out)) == REG | |
74347d76 RK |
1103 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER |
1104 | && ! dont_remove_subreg) | |
38a448ca RH |
1105 | out = gen_rtx_REG (GET_MODE (out), |
1106 | REGNO (SUBREG_REG (out)) + SUBREG_WORD (out)); | |
0dadecf6 | 1107 | |
eab89b90 RK |
1108 | /* Narrow down the class of register wanted if that is |
1109 | desirable on this machine for efficiency. */ | |
1110 | if (in != 0) | |
1111 | class = PREFERRED_RELOAD_CLASS (in, class); | |
1112 | ||
ac2a9454 | 1113 | /* Output reloads may need analogous treatment, different in detail. */ |
18a53b78 RS |
1114 | #ifdef PREFERRED_OUTPUT_RELOAD_CLASS |
1115 | if (out != 0) | |
1116 | class = PREFERRED_OUTPUT_RELOAD_CLASS (out, class); | |
1117 | #endif | |
1118 | ||
eab89b90 RK |
1119 | /* Make sure we use a class that can handle the actual pseudo |
1120 | inside any subreg. For example, on the 386, QImode regs | |
1121 | can appear within SImode subregs. Although GENERAL_REGS | |
1122 | can handle SImode, QImode needs a smaller class. */ | |
1123 | #ifdef LIMIT_RELOAD_CLASS | |
1124 | if (in_subreg_loc) | |
1125 | class = LIMIT_RELOAD_CLASS (inmode, class); | |
1126 | else if (in != 0 && GET_CODE (in) == SUBREG) | |
1127 | class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), class); | |
1128 | ||
1129 | if (out_subreg_loc) | |
1130 | class = LIMIT_RELOAD_CLASS (outmode, class); | |
1131 | if (out != 0 && GET_CODE (out) == SUBREG) | |
1132 | class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), class); | |
1133 | #endif | |
1134 | ||
eab89b90 RK |
1135 | /* Verify that this class is at least possible for the mode that |
1136 | is specified. */ | |
1137 | if (this_insn_is_asm) | |
1138 | { | |
1139 | enum machine_mode mode; | |
1140 | if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) | |
1141 | mode = inmode; | |
1142 | else | |
1143 | mode = outmode; | |
5488078f RS |
1144 | if (mode == VOIDmode) |
1145 | { | |
1146 | error_for_asm (this_insn, "cannot reload integer constant operand in `asm'"); | |
1147 | mode = word_mode; | |
1148 | if (in != 0) | |
1149 | inmode = word_mode; | |
1150 | if (out != 0) | |
1151 | outmode = word_mode; | |
1152 | } | |
eab89b90 RK |
1153 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1154 | if (HARD_REGNO_MODE_OK (i, mode) | |
1155 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)) | |
1156 | { | |
1157 | int nregs = HARD_REGNO_NREGS (i, mode); | |
1158 | ||
1159 | int j; | |
1160 | for (j = 1; j < nregs; j++) | |
1161 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], i + j)) | |
1162 | break; | |
1163 | if (j == nregs) | |
1164 | break; | |
1165 | } | |
1166 | if (i == FIRST_PSEUDO_REGISTER) | |
1167 | { | |
1168 | error_for_asm (this_insn, "impossible register constraint in `asm'"); | |
1169 | class = ALL_REGS; | |
1170 | } | |
1171 | } | |
1172 | ||
5488078f RS |
1173 | if (class == NO_REGS) |
1174 | abort (); | |
1175 | ||
eab89b90 RK |
1176 | /* We can use an existing reload if the class is right |
1177 | and at least one of IN and OUT is a match | |
1178 | and the other is at worst neutral. | |
a8c9daeb RK |
1179 | (A zero compared against anything is neutral.) |
1180 | ||
1181 | If SMALL_REGISTER_CLASSES, don't use existing reloads unless they are | |
1182 | for the same thing since that can cause us to need more reload registers | |
1183 | than we otherwise would. */ | |
1184 | ||
eab89b90 RK |
1185 | for (i = 0; i < n_reloads; i++) |
1186 | if ((reg_class_subset_p (class, reload_reg_class[i]) | |
1187 | || reg_class_subset_p (reload_reg_class[i], class)) | |
eab89b90 RK |
1188 | /* If the existing reload has a register, it must fit our class. */ |
1189 | && (reload_reg_rtx[i] == 0 | |
1190 | || TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1191 | true_regnum (reload_reg_rtx[i]))) | |
1192 | && ((in != 0 && MATCHES (reload_in[i], in) && ! dont_share | |
1193 | && (out == 0 || reload_out[i] == 0 || MATCHES (reload_out[i], out))) | |
1194 | || | |
1195 | (out != 0 && MATCHES (reload_out[i], out) | |
a8c9daeb | 1196 | && (in == 0 || reload_in[i] == 0 || MATCHES (reload_in[i], in)))) |
e9a25f70 | 1197 | && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES) |
a8c9daeb RK |
1198 | && MERGABLE_RELOADS (type, reload_when_needed[i], |
1199 | opnum, reload_opnum[i])) | |
eab89b90 RK |
1200 | break; |
1201 | ||
1202 | /* Reloading a plain reg for input can match a reload to postincrement | |
1203 | that reg, since the postincrement's value is the right value. | |
1204 | Likewise, it can match a preincrement reload, since we regard | |
1205 | the preincrementation as happening before any ref in this insn | |
1206 | to that register. */ | |
1207 | if (i == n_reloads) | |
1208 | for (i = 0; i < n_reloads; i++) | |
1209 | if ((reg_class_subset_p (class, reload_reg_class[i]) | |
1210 | || reg_class_subset_p (reload_reg_class[i], class)) | |
1211 | /* If the existing reload has a register, it must fit our class. */ | |
1212 | && (reload_reg_rtx[i] == 0 | |
1213 | || TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1214 | true_regnum (reload_reg_rtx[i]))) | |
eab89b90 RK |
1215 | && out == 0 && reload_out[i] == 0 && reload_in[i] != 0 |
1216 | && ((GET_CODE (in) == REG | |
1217 | && (GET_CODE (reload_in[i]) == POST_INC | |
1218 | || GET_CODE (reload_in[i]) == POST_DEC | |
1219 | || GET_CODE (reload_in[i]) == PRE_INC | |
1220 | || GET_CODE (reload_in[i]) == PRE_DEC) | |
1221 | && MATCHES (XEXP (reload_in[i], 0), in)) | |
1222 | || | |
1223 | (GET_CODE (reload_in[i]) == REG | |
1224 | && (GET_CODE (in) == POST_INC | |
1225 | || GET_CODE (in) == POST_DEC | |
1226 | || GET_CODE (in) == PRE_INC | |
1227 | || GET_CODE (in) == PRE_DEC) | |
a8c9daeb | 1228 | && MATCHES (XEXP (in, 0), reload_in[i]))) |
e9a25f70 | 1229 | && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES) |
a8c9daeb RK |
1230 | && MERGABLE_RELOADS (type, reload_when_needed[i], |
1231 | opnum, reload_opnum[i])) | |
eab89b90 RK |
1232 | { |
1233 | /* Make sure reload_in ultimately has the increment, | |
1234 | not the plain register. */ | |
1235 | if (GET_CODE (in) == REG) | |
1236 | in = reload_in[i]; | |
1237 | break; | |
1238 | } | |
1239 | ||
1240 | if (i == n_reloads) | |
1241 | { | |
9ec7078b RK |
1242 | /* See if we need a secondary reload register to move between CLASS |
1243 | and IN or CLASS and OUT. Get the icode and push any required reloads | |
1244 | needed for each of them if so. */ | |
eab89b90 RK |
1245 | |
1246 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
1247 | if (in != 0) | |
9ec7078b RK |
1248 | secondary_in_reload |
1249 | = push_secondary_reload (1, in, opnum, optional, class, inmode, type, | |
1250 | &secondary_in_icode); | |
eab89b90 RK |
1251 | #endif |
1252 | ||
1253 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
1254 | if (out != 0 && GET_CODE (out) != SCRATCH) | |
9ec7078b RK |
1255 | secondary_out_reload |
1256 | = push_secondary_reload (0, out, opnum, optional, class, outmode, | |
1257 | type, &secondary_out_icode); | |
eab89b90 RK |
1258 | #endif |
1259 | ||
1260 | /* We found no existing reload suitable for re-use. | |
1261 | So add an additional reload. */ | |
1262 | ||
e9a25f70 JL |
1263 | #ifdef SECONDARY_MEMORY_NEEDED |
1264 | /* If a memory location is needed for the copy, make one. */ | |
1265 | if (in != 0 && GET_CODE (in) == REG | |
1266 | && REGNO (in) < FIRST_PSEUDO_REGISTER | |
1267 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), | |
1268 | class, inmode)) | |
1269 | get_secondary_mem (in, inmode, opnum, type); | |
1270 | #endif | |
1271 | ||
9ec7078b | 1272 | i = n_reloads; |
eab89b90 RK |
1273 | reload_in[i] = in; |
1274 | reload_out[i] = out; | |
1275 | reload_reg_class[i] = class; | |
1276 | reload_inmode[i] = inmode; | |
1277 | reload_outmode[i] = outmode; | |
1278 | reload_reg_rtx[i] = 0; | |
1279 | reload_optional[i] = optional; | |
f5963e61 | 1280 | reload_nongroup[i] = 0; |
eab89b90 | 1281 | reload_inc[i] = 0; |
eab89b90 RK |
1282 | reload_nocombine[i] = 0; |
1283 | reload_in_reg[i] = inloc ? *inloc : 0; | |
a8c9daeb RK |
1284 | reload_opnum[i] = opnum; |
1285 | reload_when_needed[i] = type; | |
9ec7078b RK |
1286 | reload_secondary_in_reload[i] = secondary_in_reload; |
1287 | reload_secondary_out_reload[i] = secondary_out_reload; | |
1288 | reload_secondary_in_icode[i] = secondary_in_icode; | |
1289 | reload_secondary_out_icode[i] = secondary_out_icode; | |
eab89b90 RK |
1290 | reload_secondary_p[i] = 0; |
1291 | ||
1292 | n_reloads++; | |
0dadecf6 RK |
1293 | |
1294 | #ifdef SECONDARY_MEMORY_NEEDED | |
0dadecf6 RK |
1295 | if (out != 0 && GET_CODE (out) == REG |
1296 | && REGNO (out) < FIRST_PSEUDO_REGISTER | |
1297 | && SECONDARY_MEMORY_NEEDED (class, REGNO_REG_CLASS (REGNO (out)), | |
1298 | outmode)) | |
a8c9daeb | 1299 | get_secondary_mem (out, outmode, opnum, type); |
0dadecf6 | 1300 | #endif |
eab89b90 RK |
1301 | } |
1302 | else | |
1303 | { | |
1304 | /* We are reusing an existing reload, | |
1305 | but we may have additional information for it. | |
1306 | For example, we may now have both IN and OUT | |
1307 | while the old one may have just one of them. */ | |
1308 | ||
6fd5ac08 JW |
1309 | /* The modes can be different. If they are, we want to reload in |
1310 | the larger mode, so that the value is valid for both modes. */ | |
1311 | if (inmode != VOIDmode | |
1312 | && GET_MODE_SIZE (inmode) > GET_MODE_SIZE (reload_inmode[i])) | |
eab89b90 | 1313 | reload_inmode[i] = inmode; |
6fd5ac08 JW |
1314 | if (outmode != VOIDmode |
1315 | && GET_MODE_SIZE (outmode) > GET_MODE_SIZE (reload_outmode[i])) | |
eab89b90 RK |
1316 | reload_outmode[i] = outmode; |
1317 | if (in != 0) | |
1318 | reload_in[i] = in; | |
1319 | if (out != 0) | |
1320 | reload_out[i] = out; | |
1321 | if (reg_class_subset_p (class, reload_reg_class[i])) | |
1322 | reload_reg_class[i] = class; | |
1323 | reload_optional[i] &= optional; | |
a8c9daeb RK |
1324 | if (MERGE_TO_OTHER (type, reload_when_needed[i], |
1325 | opnum, reload_opnum[i])) | |
1326 | reload_when_needed[i] = RELOAD_OTHER; | |
1327 | reload_opnum[i] = MIN (reload_opnum[i], opnum); | |
eab89b90 RK |
1328 | } |
1329 | ||
1330 | /* If the ostensible rtx being reload differs from the rtx found | |
1331 | in the location to substitute, this reload is not safe to combine | |
1332 | because we cannot reliably tell whether it appears in the insn. */ | |
1333 | ||
1334 | if (in != 0 && in != *inloc) | |
1335 | reload_nocombine[i] = 1; | |
1336 | ||
1337 | #if 0 | |
1338 | /* This was replaced by changes in find_reloads_address_1 and the new | |
1339 | function inc_for_reload, which go with a new meaning of reload_inc. */ | |
1340 | ||
1341 | /* If this is an IN/OUT reload in an insn that sets the CC, | |
1342 | it must be for an autoincrement. It doesn't work to store | |
1343 | the incremented value after the insn because that would clobber the CC. | |
1344 | So we must do the increment of the value reloaded from, | |
1345 | increment it, store it back, then decrement again. */ | |
1346 | if (out != 0 && sets_cc0_p (PATTERN (this_insn))) | |
1347 | { | |
1348 | out = 0; | |
1349 | reload_out[i] = 0; | |
1350 | reload_inc[i] = find_inc_amount (PATTERN (this_insn), in); | |
1351 | /* If we did not find a nonzero amount-to-increment-by, | |
1352 | that contradicts the belief that IN is being incremented | |
1353 | in an address in this insn. */ | |
1354 | if (reload_inc[i] == 0) | |
1355 | abort (); | |
1356 | } | |
1357 | #endif | |
1358 | ||
1359 | /* If we will replace IN and OUT with the reload-reg, | |
1360 | record where they are located so that substitution need | |
1361 | not do a tree walk. */ | |
1362 | ||
1363 | if (replace_reloads) | |
1364 | { | |
1365 | if (inloc != 0) | |
1366 | { | |
1367 | register struct replacement *r = &replacements[n_replacements++]; | |
1368 | r->what = i; | |
1369 | r->subreg_loc = in_subreg_loc; | |
1370 | r->where = inloc; | |
1371 | r->mode = inmode; | |
1372 | } | |
1373 | if (outloc != 0 && outloc != inloc) | |
1374 | { | |
1375 | register struct replacement *r = &replacements[n_replacements++]; | |
1376 | r->what = i; | |
1377 | r->where = outloc; | |
1378 | r->subreg_loc = out_subreg_loc; | |
1379 | r->mode = outmode; | |
1380 | } | |
1381 | } | |
1382 | ||
1383 | /* If this reload is just being introduced and it has both | |
1384 | an incoming quantity and an outgoing quantity that are | |
1385 | supposed to be made to match, see if either one of the two | |
1386 | can serve as the place to reload into. | |
1387 | ||
1388 | If one of them is acceptable, set reload_reg_rtx[i] | |
1389 | to that one. */ | |
1390 | ||
1391 | if (in != 0 && out != 0 && in != out && reload_reg_rtx[i] == 0) | |
1392 | { | |
1393 | reload_reg_rtx[i] = find_dummy_reload (in, out, inloc, outloc, | |
36b50568 | 1394 | inmode, outmode, |
189086f9 | 1395 | reload_reg_class[i], i, |
31c21e0c | 1396 | earlyclobber_operand_p (out)); |
eab89b90 RK |
1397 | |
1398 | /* If the outgoing register already contains the same value | |
1399 | as the incoming one, we can dispense with loading it. | |
1400 | The easiest way to tell the caller that is to give a phony | |
1401 | value for the incoming operand (same as outgoing one). */ | |
1402 | if (reload_reg_rtx[i] == out | |
1403 | && (GET_CODE (in) == REG || CONSTANT_P (in)) | |
1404 | && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out), | |
1405 | static_reload_reg_p, i, inmode)) | |
1406 | reload_in[i] = out; | |
1407 | } | |
1408 | ||
1409 | /* If this is an input reload and the operand contains a register that | |
1410 | dies in this insn and is used nowhere else, see if it is the right class | |
1411 | to be used for this reload. Use it if so. (This occurs most commonly | |
1412 | in the case of paradoxical SUBREGs and in-out reloads). We cannot do | |
1413 | this if it is also an output reload that mentions the register unless | |
1414 | the output is a SUBREG that clobbers an entire register. | |
1415 | ||
1416 | Note that the operand might be one of the spill regs, if it is a | |
1417 | pseudo reg and we are in a block where spilling has not taken place. | |
1418 | But if there is no spilling in this block, that is OK. | |
1419 | An explicitly used hard reg cannot be a spill reg. */ | |
1420 | ||
1421 | if (reload_reg_rtx[i] == 0 && in != 0) | |
1422 | { | |
1423 | rtx note; | |
1424 | int regno; | |
1425 | ||
1426 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1427 | if (REG_NOTE_KIND (note) == REG_DEAD | |
1428 | && GET_CODE (XEXP (note, 0)) == REG | |
1429 | && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER | |
1430 | && reg_mentioned_p (XEXP (note, 0), in) | |
1431 | && ! refers_to_regno_for_reload_p (regno, | |
1432 | (regno | |
1433 | + HARD_REGNO_NREGS (regno, | |
1434 | inmode)), | |
1435 | PATTERN (this_insn), inloc) | |
05b4ec4f RS |
1436 | /* If this is also an output reload, IN cannot be used as |
1437 | the reload register if it is set in this insn unless IN | |
1438 | is also OUT. */ | |
1439 | && (out == 0 || in == out | |
1440 | || ! hard_reg_set_here_p (regno, | |
1441 | (regno | |
1442 | + HARD_REGNO_NREGS (regno, | |
1443 | inmode)), | |
1444 | PATTERN (this_insn))) | |
1445 | /* ??? Why is this code so different from the previous? | |
1446 | Is there any simple coherent way to describe the two together? | |
1447 | What's going on here. */ | |
eab89b90 RK |
1448 | && (in != out |
1449 | || (GET_CODE (in) == SUBREG | |
1450 | && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1)) | |
1451 | / UNITS_PER_WORD) | |
1452 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1453 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
1454 | /* Make sure the operand fits in the reg that dies. */ | |
1455 | && GET_MODE_SIZE (inmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
1456 | && HARD_REGNO_MODE_OK (regno, inmode) | |
1457 | && GET_MODE_SIZE (outmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
1458 | && HARD_REGNO_MODE_OK (regno, outmode) | |
1459 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno) | |
1460 | && !fixed_regs[regno]) | |
1461 | { | |
38a448ca | 1462 | reload_reg_rtx[i] = gen_rtx_REG (inmode, regno); |
eab89b90 RK |
1463 | break; |
1464 | } | |
1465 | } | |
1466 | ||
1467 | if (out) | |
1468 | output_reloadnum = i; | |
1469 | ||
1470 | return i; | |
1471 | } | |
1472 | ||
1473 | /* Record an additional place we must replace a value | |
1474 | for which we have already recorded a reload. | |
1475 | RELOADNUM is the value returned by push_reload | |
1476 | when the reload was recorded. | |
1477 | This is used in insn patterns that use match_dup. */ | |
1478 | ||
1479 | static void | |
1480 | push_replacement (loc, reloadnum, mode) | |
1481 | rtx *loc; | |
1482 | int reloadnum; | |
1483 | enum machine_mode mode; | |
1484 | { | |
1485 | if (replace_reloads) | |
1486 | { | |
1487 | register struct replacement *r = &replacements[n_replacements++]; | |
1488 | r->what = reloadnum; | |
1489 | r->where = loc; | |
1490 | r->subreg_loc = 0; | |
1491 | r->mode = mode; | |
1492 | } | |
1493 | } | |
1494 | \f | |
a8c9daeb RK |
1495 | /* Transfer all replacements that used to be in reload FROM to be in |
1496 | reload TO. */ | |
1497 | ||
1498 | void | |
1499 | transfer_replacements (to, from) | |
1500 | int to, from; | |
1501 | { | |
1502 | int i; | |
1503 | ||
1504 | for (i = 0; i < n_replacements; i++) | |
1505 | if (replacements[i].what == from) | |
1506 | replacements[i].what = to; | |
1507 | } | |
1508 | \f | |
eab89b90 RK |
1509 | /* If there is only one output reload, and it is not for an earlyclobber |
1510 | operand, try to combine it with a (logically unrelated) input reload | |
1511 | to reduce the number of reload registers needed. | |
1512 | ||
1513 | This is safe if the input reload does not appear in | |
1514 | the value being output-reloaded, because this implies | |
1515 | it is not needed any more once the original insn completes. | |
1516 | ||
1517 | If that doesn't work, see we can use any of the registers that | |
1518 | die in this insn as a reload register. We can if it is of the right | |
1519 | class and does not appear in the value being output-reloaded. */ | |
1520 | ||
1521 | static void | |
1522 | combine_reloads () | |
1523 | { | |
1524 | int i; | |
1525 | int output_reload = -1; | |
8922eb5b | 1526 | int secondary_out = -1; |
eab89b90 RK |
1527 | rtx note; |
1528 | ||
1529 | /* Find the output reload; return unless there is exactly one | |
1530 | and that one is mandatory. */ | |
1531 | ||
1532 | for (i = 0; i < n_reloads; i++) | |
1533 | if (reload_out[i] != 0) | |
1534 | { | |
1535 | if (output_reload >= 0) | |
1536 | return; | |
1537 | output_reload = i; | |
1538 | } | |
1539 | ||
1540 | if (output_reload < 0 || reload_optional[output_reload]) | |
1541 | return; | |
1542 | ||
1543 | /* An input-output reload isn't combinable. */ | |
1544 | ||
1545 | if (reload_in[output_reload] != 0) | |
1546 | return; | |
1547 | ||
6dc42e49 | 1548 | /* If this reload is for an earlyclobber operand, we can't do anything. */ |
4644aad4 RK |
1549 | if (earlyclobber_operand_p (reload_out[output_reload])) |
1550 | return; | |
eab89b90 RK |
1551 | |
1552 | /* Check each input reload; can we combine it? */ | |
1553 | ||
1554 | for (i = 0; i < n_reloads; i++) | |
1555 | if (reload_in[i] && ! reload_optional[i] && ! reload_nocombine[i] | |
1556 | /* Life span of this reload must not extend past main insn. */ | |
a8c9daeb | 1557 | && reload_when_needed[i] != RELOAD_FOR_OUTPUT_ADDRESS |
47c8cf91 | 1558 | && reload_when_needed[i] != RELOAD_FOR_OUTADDR_ADDRESS |
a8c9daeb RK |
1559 | && reload_when_needed[i] != RELOAD_OTHER |
1560 | && (CLASS_MAX_NREGS (reload_reg_class[i], reload_inmode[i]) | |
1561 | == CLASS_MAX_NREGS (reload_reg_class[output_reload], | |
1562 | reload_outmode[output_reload])) | |
eab89b90 RK |
1563 | && reload_inc[i] == 0 |
1564 | && reload_reg_rtx[i] == 0 | |
a8c9daeb | 1565 | #ifdef SECONDARY_MEMORY_NEEDED |
9ec7078b RK |
1566 | /* Don't combine two reloads with different secondary |
1567 | memory locations. */ | |
77545d45 RK |
1568 | && (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]] == 0 |
1569 | || secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]] == 0 | |
1570 | || rtx_equal_p (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]], | |
1571 | secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]])) | |
a8c9daeb | 1572 | #endif |
e9a25f70 JL |
1573 | && (SMALL_REGISTER_CLASSES |
1574 | ? (reload_reg_class[i] == reload_reg_class[output_reload]) | |
1575 | : (reg_class_subset_p (reload_reg_class[i], | |
1576 | reload_reg_class[output_reload]) | |
1577 | || reg_class_subset_p (reload_reg_class[output_reload], | |
1578 | reload_reg_class[i]))) | |
eab89b90 RK |
1579 | && (MATCHES (reload_in[i], reload_out[output_reload]) |
1580 | /* Args reversed because the first arg seems to be | |
1581 | the one that we imagine being modified | |
1582 | while the second is the one that might be affected. */ | |
bfa30b22 RK |
1583 | || (! reg_overlap_mentioned_for_reload_p (reload_out[output_reload], |
1584 | reload_in[i]) | |
eab89b90 RK |
1585 | /* However, if the input is a register that appears inside |
1586 | the output, then we also can't share. | |
1587 | Imagine (set (mem (reg 69)) (plus (reg 69) ...)). | |
1588 | If the same reload reg is used for both reg 69 and the | |
1589 | result to be stored in memory, then that result | |
1590 | will clobber the address of the memory ref. */ | |
1591 | && ! (GET_CODE (reload_in[i]) == REG | |
bfa30b22 | 1592 | && reg_overlap_mentioned_for_reload_p (reload_in[i], |
a8c9daeb RK |
1593 | reload_out[output_reload])))) |
1594 | && (reg_class_size[(int) reload_reg_class[i]] | |
e9a25f70 | 1595 | || SMALL_REGISTER_CLASSES) |
a8c9daeb RK |
1596 | /* We will allow making things slightly worse by combining an |
1597 | input and an output, but no worse than that. */ | |
1598 | && (reload_when_needed[i] == RELOAD_FOR_INPUT | |
1599 | || reload_when_needed[i] == RELOAD_FOR_OUTPUT)) | |
eab89b90 RK |
1600 | { |
1601 | int j; | |
1602 | ||
1603 | /* We have found a reload to combine with! */ | |
1604 | reload_out[i] = reload_out[output_reload]; | |
1605 | reload_outmode[i] = reload_outmode[output_reload]; | |
1606 | /* Mark the old output reload as inoperative. */ | |
1607 | reload_out[output_reload] = 0; | |
1608 | /* The combined reload is needed for the entire insn. */ | |
eab89b90 | 1609 | reload_when_needed[i] = RELOAD_OTHER; |
0f41302f | 1610 | /* If the output reload had a secondary reload, copy it. */ |
9ec7078b RK |
1611 | if (reload_secondary_out_reload[output_reload] != -1) |
1612 | { | |
1613 | reload_secondary_out_reload[i] | |
1614 | = reload_secondary_out_reload[output_reload]; | |
1615 | reload_secondary_out_icode[i] | |
1616 | = reload_secondary_out_icode[output_reload]; | |
1617 | } | |
1618 | ||
a8c9daeb RK |
1619 | #ifdef SECONDARY_MEMORY_NEEDED |
1620 | /* Copy any secondary MEM. */ | |
77545d45 RK |
1621 | if (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]] != 0) |
1622 | secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]] | |
1623 | = secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]]; | |
a8c9daeb | 1624 | #endif |
0f41302f | 1625 | /* If required, minimize the register class. */ |
eab89b90 RK |
1626 | if (reg_class_subset_p (reload_reg_class[output_reload], |
1627 | reload_reg_class[i])) | |
1628 | reload_reg_class[i] = reload_reg_class[output_reload]; | |
1629 | ||
1630 | /* Transfer all replacements from the old reload to the combined. */ | |
1631 | for (j = 0; j < n_replacements; j++) | |
1632 | if (replacements[j].what == output_reload) | |
1633 | replacements[j].what = i; | |
1634 | ||
1635 | return; | |
1636 | } | |
1637 | ||
1638 | /* If this insn has only one operand that is modified or written (assumed | |
1639 | to be the first), it must be the one corresponding to this reload. It | |
1640 | is safe to use anything that dies in this insn for that output provided | |
1641 | that it does not occur in the output (we already know it isn't an | |
1642 | earlyclobber. If this is an asm insn, give up. */ | |
1643 | ||
1644 | if (INSN_CODE (this_insn) == -1) | |
1645 | return; | |
1646 | ||
1647 | for (i = 1; i < insn_n_operands[INSN_CODE (this_insn)]; i++) | |
1648 | if (insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '=' | |
1649 | || insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '+') | |
1650 | return; | |
1651 | ||
1652 | /* See if some hard register that dies in this insn and is not used in | |
1653 | the output is the right class. Only works if the register we pick | |
1654 | up can fully hold our output reload. */ | |
1655 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1656 | if (REG_NOTE_KIND (note) == REG_DEAD | |
1657 | && GET_CODE (XEXP (note, 0)) == REG | |
bfa30b22 RK |
1658 | && ! reg_overlap_mentioned_for_reload_p (XEXP (note, 0), |
1659 | reload_out[output_reload]) | |
eab89b90 RK |
1660 | && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER |
1661 | && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), reload_outmode[output_reload]) | |
1662 | && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[output_reload]], | |
1663 | REGNO (XEXP (note, 0))) | |
1664 | && (HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), reload_outmode[output_reload]) | |
1665 | <= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0)))) | |
8922eb5b RK |
1666 | /* Ensure that a secondary or tertiary reload for this output |
1667 | won't want this register. */ | |
1668 | && ((secondary_out = reload_secondary_out_reload[output_reload]) == -1 | |
1669 | || (! (TEST_HARD_REG_BIT | |
1670 | (reg_class_contents[(int) reload_reg_class[secondary_out]], | |
1671 | REGNO (XEXP (note, 0)))) | |
1672 | && ((secondary_out = reload_secondary_out_reload[secondary_out]) == -1 | |
1673 | || ! (TEST_HARD_REG_BIT | |
1674 | (reg_class_contents[(int) reload_reg_class[secondary_out]], | |
1675 | REGNO (XEXP (note, 0))))))) | |
eab89b90 RK |
1676 | && ! fixed_regs[REGNO (XEXP (note, 0))]) |
1677 | { | |
38a448ca RH |
1678 | reload_reg_rtx[output_reload] |
1679 | = gen_rtx_REG (reload_outmode[output_reload], | |
1680 | REGNO (XEXP (note, 0))); | |
eab89b90 RK |
1681 | return; |
1682 | } | |
1683 | } | |
1684 | \f | |
1685 | /* Try to find a reload register for an in-out reload (expressions IN and OUT). | |
1686 | See if one of IN and OUT is a register that may be used; | |
1687 | this is desirable since a spill-register won't be needed. | |
1688 | If so, return the register rtx that proves acceptable. | |
1689 | ||
1690 | INLOC and OUTLOC are locations where IN and OUT appear in the insn. | |
1691 | CLASS is the register class required for the reload. | |
1692 | ||
1693 | If FOR_REAL is >= 0, it is the number of the reload, | |
1694 | and in some cases when it can be discovered that OUT doesn't need | |
1695 | to be computed, clear out reload_out[FOR_REAL]. | |
1696 | ||
1697 | If FOR_REAL is -1, this should not be done, because this call | |
189086f9 RK |
1698 | is just to see if a register can be found, not to find and install it. |
1699 | ||
1700 | EARLYCLOBBER is non-zero if OUT is an earlyclobber operand. This | |
1701 | puts an additional constraint on being able to use IN for OUT since | |
1702 | IN must not appear elsewhere in the insn (it is assumed that IN itself | |
1703 | is safe from the earlyclobber). */ | |
eab89b90 RK |
1704 | |
1705 | static rtx | |
36b50568 | 1706 | find_dummy_reload (real_in, real_out, inloc, outloc, |
189086f9 | 1707 | inmode, outmode, class, for_real, earlyclobber) |
eab89b90 RK |
1708 | rtx real_in, real_out; |
1709 | rtx *inloc, *outloc; | |
36b50568 | 1710 | enum machine_mode inmode, outmode; |
eab89b90 RK |
1711 | enum reg_class class; |
1712 | int for_real; | |
189086f9 | 1713 | int earlyclobber; |
eab89b90 RK |
1714 | { |
1715 | rtx in = real_in; | |
1716 | rtx out = real_out; | |
1717 | int in_offset = 0; | |
1718 | int out_offset = 0; | |
1719 | rtx value = 0; | |
1720 | ||
1721 | /* If operands exceed a word, we can't use either of them | |
1722 | unless they have the same size. */ | |
36b50568 RS |
1723 | if (GET_MODE_SIZE (outmode) != GET_MODE_SIZE (inmode) |
1724 | && (GET_MODE_SIZE (outmode) > UNITS_PER_WORD | |
1725 | || GET_MODE_SIZE (inmode) > UNITS_PER_WORD)) | |
eab89b90 RK |
1726 | return 0; |
1727 | ||
1728 | /* Find the inside of any subregs. */ | |
1729 | while (GET_CODE (out) == SUBREG) | |
1730 | { | |
1731 | out_offset = SUBREG_WORD (out); | |
1732 | out = SUBREG_REG (out); | |
1733 | } | |
1734 | while (GET_CODE (in) == SUBREG) | |
1735 | { | |
1736 | in_offset = SUBREG_WORD (in); | |
1737 | in = SUBREG_REG (in); | |
1738 | } | |
1739 | ||
1740 | /* Narrow down the reg class, the same way push_reload will; | |
1741 | otherwise we might find a dummy now, but push_reload won't. */ | |
1742 | class = PREFERRED_RELOAD_CLASS (in, class); | |
1743 | ||
1744 | /* See if OUT will do. */ | |
1745 | if (GET_CODE (out) == REG | |
1746 | && REGNO (out) < FIRST_PSEUDO_REGISTER) | |
1747 | { | |
1748 | register int regno = REGNO (out) + out_offset; | |
36b50568 | 1749 | int nwords = HARD_REGNO_NREGS (regno, outmode); |
d3b9996a | 1750 | rtx saved_rtx; |
eab89b90 RK |
1751 | |
1752 | /* When we consider whether the insn uses OUT, | |
1753 | ignore references within IN. They don't prevent us | |
1754 | from copying IN into OUT, because those refs would | |
1755 | move into the insn that reloads IN. | |
1756 | ||
1757 | However, we only ignore IN in its role as this reload. | |
1758 | If the insn uses IN elsewhere and it contains OUT, | |
1759 | that counts. We can't be sure it's the "same" operand | |
1760 | so it might not go through this reload. */ | |
d3b9996a | 1761 | saved_rtx = *inloc; |
eab89b90 RK |
1762 | *inloc = const0_rtx; |
1763 | ||
1764 | if (regno < FIRST_PSEUDO_REGISTER | |
1765 | /* A fixed reg that can overlap other regs better not be used | |
1766 | for reloading in any way. */ | |
1767 | #ifdef OVERLAPPING_REGNO_P | |
1768 | && ! (fixed_regs[regno] && OVERLAPPING_REGNO_P (regno)) | |
1769 | #endif | |
1770 | && ! refers_to_regno_for_reload_p (regno, regno + nwords, | |
1771 | PATTERN (this_insn), outloc)) | |
1772 | { | |
1773 | int i; | |
1774 | for (i = 0; i < nwords; i++) | |
1775 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1776 | regno + i)) | |
1777 | break; | |
1778 | ||
1779 | if (i == nwords) | |
1780 | { | |
1781 | if (GET_CODE (real_out) == REG) | |
1782 | value = real_out; | |
1783 | else | |
38a448ca | 1784 | value = gen_rtx_REG (outmode, regno); |
eab89b90 RK |
1785 | } |
1786 | } | |
1787 | ||
d3b9996a | 1788 | *inloc = saved_rtx; |
eab89b90 RK |
1789 | } |
1790 | ||
1791 | /* Consider using IN if OUT was not acceptable | |
1792 | or if OUT dies in this insn (like the quotient in a divmod insn). | |
1793 | We can't use IN unless it is dies in this insn, | |
1794 | which means we must know accurately which hard regs are live. | |
189086f9 RK |
1795 | Also, the result can't go in IN if IN is used within OUT, |
1796 | or if OUT is an earlyclobber and IN appears elsewhere in the insn. */ | |
eab89b90 RK |
1797 | if (hard_regs_live_known |
1798 | && GET_CODE (in) == REG | |
1799 | && REGNO (in) < FIRST_PSEUDO_REGISTER | |
1800 | && (value == 0 | |
1801 | || find_reg_note (this_insn, REG_UNUSED, real_out)) | |
1802 | && find_reg_note (this_insn, REG_DEAD, real_in) | |
1803 | && !fixed_regs[REGNO (in)] | |
36b50568 RS |
1804 | && HARD_REGNO_MODE_OK (REGNO (in), |
1805 | /* The only case where out and real_out might | |
1806 | have different modes is where real_out | |
1807 | is a subreg, and in that case, out | |
1808 | has a real mode. */ | |
1809 | (GET_MODE (out) != VOIDmode | |
1810 | ? GET_MODE (out) : outmode))) | |
eab89b90 RK |
1811 | { |
1812 | register int regno = REGNO (in) + in_offset; | |
36b50568 | 1813 | int nwords = HARD_REGNO_NREGS (regno, inmode); |
eab89b90 | 1814 | |
fb3821f7 | 1815 | if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, NULL_PTR) |
eab89b90 | 1816 | && ! hard_reg_set_here_p (regno, regno + nwords, |
189086f9 RK |
1817 | PATTERN (this_insn)) |
1818 | && (! earlyclobber | |
1819 | || ! refers_to_regno_for_reload_p (regno, regno + nwords, | |
1820 | PATTERN (this_insn), inloc))) | |
eab89b90 RK |
1821 | { |
1822 | int i; | |
1823 | for (i = 0; i < nwords; i++) | |
1824 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1825 | regno + i)) | |
1826 | break; | |
1827 | ||
1828 | if (i == nwords) | |
1829 | { | |
1830 | /* If we were going to use OUT as the reload reg | |
1831 | and changed our mind, it means OUT is a dummy that | |
1832 | dies here. So don't bother copying value to it. */ | |
1833 | if (for_real >= 0 && value == real_out) | |
1834 | reload_out[for_real] = 0; | |
1835 | if (GET_CODE (real_in) == REG) | |
1836 | value = real_in; | |
1837 | else | |
38a448ca | 1838 | value = gen_rtx_REG (inmode, regno); |
eab89b90 RK |
1839 | } |
1840 | } | |
1841 | } | |
1842 | ||
1843 | return value; | |
1844 | } | |
1845 | \f | |
1846 | /* This page contains subroutines used mainly for determining | |
1847 | whether the IN or an OUT of a reload can serve as the | |
1848 | reload register. */ | |
1849 | ||
4644aad4 RK |
1850 | /* Return 1 if X is an operand of an insn that is being earlyclobbered. */ |
1851 | ||
1852 | static int | |
1853 | earlyclobber_operand_p (x) | |
1854 | rtx x; | |
1855 | { | |
1856 | int i; | |
1857 | ||
1858 | for (i = 0; i < n_earlyclobbers; i++) | |
1859 | if (reload_earlyclobbers[i] == x) | |
1860 | return 1; | |
1861 | ||
1862 | return 0; | |
1863 | } | |
1864 | ||
eab89b90 RK |
1865 | /* Return 1 if expression X alters a hard reg in the range |
1866 | from BEG_REGNO (inclusive) to END_REGNO (exclusive), | |
1867 | either explicitly or in the guise of a pseudo-reg allocated to REGNO. | |
1868 | X should be the body of an instruction. */ | |
1869 | ||
1870 | static int | |
1871 | hard_reg_set_here_p (beg_regno, end_regno, x) | |
1872 | register int beg_regno, end_regno; | |
1873 | rtx x; | |
1874 | { | |
1875 | if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
1876 | { | |
1877 | register rtx op0 = SET_DEST (x); | |
1878 | while (GET_CODE (op0) == SUBREG) | |
1879 | op0 = SUBREG_REG (op0); | |
1880 | if (GET_CODE (op0) == REG) | |
1881 | { | |
1882 | register int r = REGNO (op0); | |
1883 | /* See if this reg overlaps range under consideration. */ | |
1884 | if (r < end_regno | |
1885 | && r + HARD_REGNO_NREGS (r, GET_MODE (op0)) > beg_regno) | |
1886 | return 1; | |
1887 | } | |
1888 | } | |
1889 | else if (GET_CODE (x) == PARALLEL) | |
1890 | { | |
1891 | register int i = XVECLEN (x, 0) - 1; | |
1892 | for (; i >= 0; i--) | |
1893 | if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i))) | |
1894 | return 1; | |
1895 | } | |
1896 | ||
1897 | return 0; | |
1898 | } | |
1899 | ||
1900 | /* Return 1 if ADDR is a valid memory address for mode MODE, | |
1901 | and check that each pseudo reg has the proper kind of | |
1902 | hard reg. */ | |
1903 | ||
1904 | int | |
1905 | strict_memory_address_p (mode, addr) | |
1906 | enum machine_mode mode; | |
1907 | register rtx addr; | |
1908 | { | |
1909 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
1910 | return 0; | |
1911 | ||
1912 | win: | |
1913 | return 1; | |
1914 | } | |
eab89b90 RK |
1915 | \f |
1916 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
1917 | if they are the same hard reg, and has special hacks for | |
1918 | autoincrement and autodecrement. | |
1919 | This is specifically intended for find_reloads to use | |
1920 | in determining whether two operands match. | |
1921 | X is the operand whose number is the lower of the two. | |
1922 | ||
1923 | The value is 2 if Y contains a pre-increment that matches | |
1924 | a non-incrementing address in X. */ | |
1925 | ||
1926 | /* ??? To be completely correct, we should arrange to pass | |
1927 | for X the output operand and for Y the input operand. | |
1928 | For now, we assume that the output operand has the lower number | |
1929 | because that is natural in (SET output (... input ...)). */ | |
1930 | ||
1931 | int | |
1932 | operands_match_p (x, y) | |
1933 | register rtx x, y; | |
1934 | { | |
1935 | register int i; | |
1936 | register RTX_CODE code = GET_CODE (x); | |
1937 | register char *fmt; | |
1938 | int success_2; | |
1939 | ||
1940 | if (x == y) | |
1941 | return 1; | |
1942 | if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)) | |
1943 | && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG | |
1944 | && GET_CODE (SUBREG_REG (y)) == REG))) | |
1945 | { | |
1946 | register int j; | |
1947 | ||
1948 | if (code == SUBREG) | |
1949 | { | |
1950 | i = REGNO (SUBREG_REG (x)); | |
1951 | if (i >= FIRST_PSEUDO_REGISTER) | |
1952 | goto slow; | |
1953 | i += SUBREG_WORD (x); | |
1954 | } | |
1955 | else | |
1956 | i = REGNO (x); | |
1957 | ||
1958 | if (GET_CODE (y) == SUBREG) | |
1959 | { | |
1960 | j = REGNO (SUBREG_REG (y)); | |
1961 | if (j >= FIRST_PSEUDO_REGISTER) | |
1962 | goto slow; | |
1963 | j += SUBREG_WORD (y); | |
1964 | } | |
1965 | else | |
1966 | j = REGNO (y); | |
1967 | ||
dca52d80 JW |
1968 | /* On a WORDS_BIG_ENDIAN machine, point to the last register of a |
1969 | multiple hard register group, so that for example (reg:DI 0) and | |
1970 | (reg:SI 1) will be considered the same register. */ | |
1971 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD | |
1972 | && i < FIRST_PSEUDO_REGISTER) | |
1973 | i += (GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD) - 1; | |
1974 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (y)) > UNITS_PER_WORD | |
1975 | && j < FIRST_PSEUDO_REGISTER) | |
1976 | j += (GET_MODE_SIZE (GET_MODE (y)) / UNITS_PER_WORD) - 1; | |
1977 | ||
eab89b90 RK |
1978 | return i == j; |
1979 | } | |
1980 | /* If two operands must match, because they are really a single | |
1981 | operand of an assembler insn, then two postincrements are invalid | |
1982 | because the assembler insn would increment only once. | |
1983 | On the other hand, an postincrement matches ordinary indexing | |
1984 | if the postincrement is the output operand. */ | |
1985 | if (code == POST_DEC || code == POST_INC) | |
1986 | return operands_match_p (XEXP (x, 0), y); | |
1987 | /* Two preincrements are invalid | |
1988 | because the assembler insn would increment only once. | |
1989 | On the other hand, an preincrement matches ordinary indexing | |
1990 | if the preincrement is the input operand. | |
1991 | In this case, return 2, since some callers need to do special | |
1992 | things when this happens. */ | |
1993 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC) | |
1994 | return operands_match_p (x, XEXP (y, 0)) ? 2 : 0; | |
1995 | ||
1996 | slow: | |
1997 | ||
1998 | /* Now we have disposed of all the cases | |
1999 | in which different rtx codes can match. */ | |
2000 | if (code != GET_CODE (y)) | |
2001 | return 0; | |
2002 | if (code == LABEL_REF) | |
2003 | return XEXP (x, 0) == XEXP (y, 0); | |
2004 | if (code == SYMBOL_REF) | |
2005 | return XSTR (x, 0) == XSTR (y, 0); | |
2006 | ||
2007 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
2008 | ||
2009 | if (GET_MODE (x) != GET_MODE (y)) | |
2010 | return 0; | |
2011 | ||
2012 | /* Compare the elements. If any pair of corresponding elements | |
2013 | fail to match, return 0 for the whole things. */ | |
2014 | ||
2015 | success_2 = 0; | |
2016 | fmt = GET_RTX_FORMAT (code); | |
2017 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2018 | { | |
2019 | int val; | |
2020 | switch (fmt[i]) | |
2021 | { | |
fb3821f7 CH |
2022 | case 'w': |
2023 | if (XWINT (x, i) != XWINT (y, i)) | |
2024 | return 0; | |
2025 | break; | |
2026 | ||
eab89b90 RK |
2027 | case 'i': |
2028 | if (XINT (x, i) != XINT (y, i)) | |
2029 | return 0; | |
2030 | break; | |
2031 | ||
2032 | case 'e': | |
2033 | val = operands_match_p (XEXP (x, i), XEXP (y, i)); | |
2034 | if (val == 0) | |
2035 | return 0; | |
2036 | /* If any subexpression returns 2, | |
2037 | we should return 2 if we are successful. */ | |
2038 | if (val == 2) | |
2039 | success_2 = 1; | |
2040 | break; | |
2041 | ||
2042 | case '0': | |
2043 | break; | |
2044 | ||
2045 | /* It is believed that rtx's at this level will never | |
2046 | contain anything but integers and other rtx's, | |
2047 | except for within LABEL_REFs and SYMBOL_REFs. */ | |
2048 | default: | |
2049 | abort (); | |
2050 | } | |
2051 | } | |
2052 | return 1 + success_2; | |
2053 | } | |
2054 | \f | |
2055 | /* Return the number of times character C occurs in string S. */ | |
2056 | ||
e4600702 | 2057 | int |
eab89b90 | 2058 | n_occurrences (c, s) |
d149d5f5 | 2059 | int c; |
eab89b90 RK |
2060 | char *s; |
2061 | { | |
2062 | int n = 0; | |
2063 | while (*s) | |
2064 | n += (*s++ == c); | |
2065 | return n; | |
2066 | } | |
2067 | \f | |
eab89b90 RK |
2068 | /* Describe the range of registers or memory referenced by X. |
2069 | If X is a register, set REG_FLAG and put the first register | |
2070 | number into START and the last plus one into END. | |
2071 | If X is a memory reference, put a base address into BASE | |
2072 | and a range of integer offsets into START and END. | |
2073 | If X is pushing on the stack, we can assume it causes no trouble, | |
2074 | so we set the SAFE field. */ | |
2075 | ||
2076 | static struct decomposition | |
2077 | decompose (x) | |
2078 | rtx x; | |
2079 | { | |
2080 | struct decomposition val; | |
2081 | int all_const = 0; | |
2082 | ||
2083 | val.reg_flag = 0; | |
2084 | val.safe = 0; | |
43984e29 | 2085 | val.base = 0; |
eab89b90 RK |
2086 | if (GET_CODE (x) == MEM) |
2087 | { | |
2088 | rtx base, offset = 0; | |
2089 | rtx addr = XEXP (x, 0); | |
2090 | ||
2091 | if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC | |
2092 | || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC) | |
2093 | { | |
2094 | val.base = XEXP (addr, 0); | |
2095 | val.start = - GET_MODE_SIZE (GET_MODE (x)); | |
2096 | val.end = GET_MODE_SIZE (GET_MODE (x)); | |
2097 | val.safe = REGNO (val.base) == STACK_POINTER_REGNUM; | |
2098 | return val; | |
2099 | } | |
2100 | ||
2101 | if (GET_CODE (addr) == CONST) | |
2102 | { | |
2103 | addr = XEXP (addr, 0); | |
2104 | all_const = 1; | |
2105 | } | |
2106 | if (GET_CODE (addr) == PLUS) | |
2107 | { | |
2108 | if (CONSTANT_P (XEXP (addr, 0))) | |
2109 | { | |
2110 | base = XEXP (addr, 1); | |
2111 | offset = XEXP (addr, 0); | |
2112 | } | |
2113 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2114 | { | |
2115 | base = XEXP (addr, 0); | |
2116 | offset = XEXP (addr, 1); | |
2117 | } | |
2118 | } | |
2119 | ||
2120 | if (offset == 0) | |
2121 | { | |
2122 | base = addr; | |
2123 | offset = const0_rtx; | |
2124 | } | |
2125 | if (GET_CODE (offset) == CONST) | |
2126 | offset = XEXP (offset, 0); | |
2127 | if (GET_CODE (offset) == PLUS) | |
2128 | { | |
2129 | if (GET_CODE (XEXP (offset, 0)) == CONST_INT) | |
2130 | { | |
38a448ca | 2131 | base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 1)); |
eab89b90 RK |
2132 | offset = XEXP (offset, 0); |
2133 | } | |
2134 | else if (GET_CODE (XEXP (offset, 1)) == CONST_INT) | |
2135 | { | |
38a448ca | 2136 | base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 0)); |
eab89b90 RK |
2137 | offset = XEXP (offset, 1); |
2138 | } | |
2139 | else | |
2140 | { | |
38a448ca | 2141 | base = gen_rtx_PLUS (GET_MODE (base), base, offset); |
eab89b90 RK |
2142 | offset = const0_rtx; |
2143 | } | |
2144 | } | |
2145 | else if (GET_CODE (offset) != CONST_INT) | |
2146 | { | |
38a448ca | 2147 | base = gen_rtx_PLUS (GET_MODE (base), base, offset); |
eab89b90 RK |
2148 | offset = const0_rtx; |
2149 | } | |
2150 | ||
2151 | if (all_const && GET_CODE (base) == PLUS) | |
38a448ca | 2152 | base = gen_rtx_CONST (GET_MODE (base), base); |
eab89b90 RK |
2153 | |
2154 | if (GET_CODE (offset) != CONST_INT) | |
2155 | abort (); | |
2156 | ||
2157 | val.start = INTVAL (offset); | |
2158 | val.end = val.start + GET_MODE_SIZE (GET_MODE (x)); | |
2159 | val.base = base; | |
2160 | return val; | |
2161 | } | |
2162 | else if (GET_CODE (x) == REG) | |
2163 | { | |
2164 | val.reg_flag = 1; | |
2165 | val.start = true_regnum (x); | |
2166 | if (val.start < 0) | |
2167 | { | |
2168 | /* A pseudo with no hard reg. */ | |
2169 | val.start = REGNO (x); | |
2170 | val.end = val.start + 1; | |
2171 | } | |
2172 | else | |
2173 | /* A hard reg. */ | |
2174 | val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); | |
2175 | } | |
2176 | else if (GET_CODE (x) == SUBREG) | |
2177 | { | |
2178 | if (GET_CODE (SUBREG_REG (x)) != REG) | |
2179 | /* This could be more precise, but it's good enough. */ | |
2180 | return decompose (SUBREG_REG (x)); | |
2181 | val.reg_flag = 1; | |
2182 | val.start = true_regnum (x); | |
2183 | if (val.start < 0) | |
2184 | return decompose (SUBREG_REG (x)); | |
2185 | else | |
2186 | /* A hard reg. */ | |
2187 | val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); | |
2188 | } | |
2189 | else if (CONSTANT_P (x) | |
2190 | /* This hasn't been assigned yet, so it can't conflict yet. */ | |
2191 | || GET_CODE (x) == SCRATCH) | |
2192 | val.safe = 1; | |
2193 | else | |
2194 | abort (); | |
2195 | return val; | |
2196 | } | |
2197 | ||
2198 | /* Return 1 if altering Y will not modify the value of X. | |
2199 | Y is also described by YDATA, which should be decompose (Y). */ | |
2200 | ||
2201 | static int | |
2202 | immune_p (x, y, ydata) | |
2203 | rtx x, y; | |
2204 | struct decomposition ydata; | |
2205 | { | |
2206 | struct decomposition xdata; | |
2207 | ||
2208 | if (ydata.reg_flag) | |
fb3821f7 | 2209 | return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, NULL_PTR); |
eab89b90 RK |
2210 | if (ydata.safe) |
2211 | return 1; | |
2212 | ||
2213 | if (GET_CODE (y) != MEM) | |
2214 | abort (); | |
2215 | /* If Y is memory and X is not, Y can't affect X. */ | |
2216 | if (GET_CODE (x) != MEM) | |
2217 | return 1; | |
2218 | ||
2219 | xdata = decompose (x); | |
2220 | ||
2221 | if (! rtx_equal_p (xdata.base, ydata.base)) | |
2222 | { | |
2223 | /* If bases are distinct symbolic constants, there is no overlap. */ | |
2224 | if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base)) | |
2225 | return 1; | |
2226 | /* Constants and stack slots never overlap. */ | |
2227 | if (CONSTANT_P (xdata.base) | |
2228 | && (ydata.base == frame_pointer_rtx | |
a36d4c62 | 2229 | || ydata.base == hard_frame_pointer_rtx |
eab89b90 RK |
2230 | || ydata.base == stack_pointer_rtx)) |
2231 | return 1; | |
2232 | if (CONSTANT_P (ydata.base) | |
2233 | && (xdata.base == frame_pointer_rtx | |
a36d4c62 | 2234 | || xdata.base == hard_frame_pointer_rtx |
eab89b90 RK |
2235 | || xdata.base == stack_pointer_rtx)) |
2236 | return 1; | |
2237 | /* If either base is variable, we don't know anything. */ | |
2238 | return 0; | |
2239 | } | |
2240 | ||
2241 | ||
2242 | return (xdata.start >= ydata.end || ydata.start >= xdata.end); | |
2243 | } | |
44ace968 | 2244 | |
f72aed24 | 2245 | /* Similar, but calls decompose. */ |
44ace968 JW |
2246 | |
2247 | int | |
2248 | safe_from_earlyclobber (op, clobber) | |
2249 | rtx op, clobber; | |
2250 | { | |
2251 | struct decomposition early_data; | |
2252 | ||
2253 | early_data = decompose (clobber); | |
2254 | return immune_p (op, clobber, early_data); | |
2255 | } | |
eab89b90 RK |
2256 | \f |
2257 | /* Main entry point of this file: search the body of INSN | |
2258 | for values that need reloading and record them with push_reload. | |
2259 | REPLACE nonzero means record also where the values occur | |
2260 | so that subst_reloads can be used. | |
2261 | ||
2262 | IND_LEVELS says how many levels of indirection are supported by this | |
2263 | machine; a value of zero means that a memory reference is not a valid | |
2264 | memory address. | |
2265 | ||
2266 | LIVE_KNOWN says we have valid information about which hard | |
2267 | regs are live at each point in the program; this is true when | |
2268 | we are called from global_alloc but false when stupid register | |
2269 | allocation has been done. | |
2270 | ||
2271 | RELOAD_REG_P if nonzero is a vector indexed by hard reg number | |
2272 | which is nonnegative if the reg has been commandeered for reloading into. | |
2273 | It is copied into STATIC_RELOAD_REG_P and referenced from there | |
2274 | by various subroutines. */ | |
2275 | ||
2276 | void | |
2277 | find_reloads (insn, replace, ind_levels, live_known, reload_reg_p) | |
2278 | rtx insn; | |
2279 | int replace, ind_levels; | |
2280 | int live_known; | |
2281 | short *reload_reg_p; | |
2282 | { | |
eab89b90 RK |
2283 | #ifdef REGISTER_CONSTRAINTS |
2284 | ||
eab89b90 | 2285 | register int insn_code_number; |
a8c9daeb | 2286 | register int i, j; |
eab89b90 RK |
2287 | int noperands; |
2288 | /* These are the constraints for the insn. We don't change them. */ | |
2289 | char *constraints1[MAX_RECOG_OPERANDS]; | |
2290 | /* These start out as the constraints for the insn | |
2291 | and they are chewed up as we consider alternatives. */ | |
2292 | char *constraints[MAX_RECOG_OPERANDS]; | |
2293 | /* These are the preferred classes for an operand, or NO_REGS if it isn't | |
2294 | a register. */ | |
2295 | enum reg_class preferred_class[MAX_RECOG_OPERANDS]; | |
2296 | char pref_or_nothing[MAX_RECOG_OPERANDS]; | |
2297 | /* Nonzero for a MEM operand whose entire address needs a reload. */ | |
2298 | int address_reloaded[MAX_RECOG_OPERANDS]; | |
a8c9daeb RK |
2299 | /* Value of enum reload_type to use for operand. */ |
2300 | enum reload_type operand_type[MAX_RECOG_OPERANDS]; | |
2301 | /* Value of enum reload_type to use within address of operand. */ | |
2302 | enum reload_type address_type[MAX_RECOG_OPERANDS]; | |
2303 | /* Save the usage of each operand. */ | |
2304 | enum reload_usage { RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE } modified[MAX_RECOG_OPERANDS]; | |
eab89b90 RK |
2305 | int no_input_reloads = 0, no_output_reloads = 0; |
2306 | int n_alternatives; | |
2307 | int this_alternative[MAX_RECOG_OPERANDS]; | |
2308 | char this_alternative_win[MAX_RECOG_OPERANDS]; | |
2309 | char this_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2310 | char this_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2311 | int this_alternative_matches[MAX_RECOG_OPERANDS]; | |
2312 | int swapped; | |
2313 | int goal_alternative[MAX_RECOG_OPERANDS]; | |
2314 | int this_alternative_number; | |
2315 | int goal_alternative_number; | |
2316 | int operand_reloadnum[MAX_RECOG_OPERANDS]; | |
2317 | int goal_alternative_matches[MAX_RECOG_OPERANDS]; | |
2318 | int goal_alternative_matched[MAX_RECOG_OPERANDS]; | |
2319 | char goal_alternative_win[MAX_RECOG_OPERANDS]; | |
2320 | char goal_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2321 | char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2322 | int goal_alternative_swapped; | |
eab89b90 RK |
2323 | int best; |
2324 | int commutative; | |
f5963e61 | 2325 | int changed; |
eab89b90 RK |
2326 | char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; |
2327 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
2328 | rtx body = PATTERN (insn); | |
2329 | rtx set = single_set (insn); | |
2330 | int goal_earlyclobber, this_earlyclobber; | |
2331 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; | |
2332 | ||
2333 | this_insn = insn; | |
2334 | this_insn_is_asm = 0; /* Tentative. */ | |
2335 | n_reloads = 0; | |
2336 | n_replacements = 0; | |
2337 | n_memlocs = 0; | |
2338 | n_earlyclobbers = 0; | |
2339 | replace_reloads = replace; | |
2340 | hard_regs_live_known = live_known; | |
2341 | static_reload_reg_p = reload_reg_p; | |
2342 | ||
2343 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads; | |
2344 | neither are insns that SET cc0. Insns that use CC0 are not allowed | |
2345 | to have any input reloads. */ | |
2346 | if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN) | |
2347 | no_output_reloads = 1; | |
2348 | ||
2349 | #ifdef HAVE_cc0 | |
2350 | if (reg_referenced_p (cc0_rtx, PATTERN (insn))) | |
2351 | no_input_reloads = 1; | |
2352 | if (reg_set_p (cc0_rtx, PATTERN (insn))) | |
2353 | no_output_reloads = 1; | |
2354 | #endif | |
2355 | ||
0dadecf6 RK |
2356 | #ifdef SECONDARY_MEMORY_NEEDED |
2357 | /* The eliminated forms of any secondary memory locations are per-insn, so | |
2358 | clear them out here. */ | |
2359 | ||
4c9a05bc | 2360 | bzero ((char *) secondary_memlocs_elim, sizeof secondary_memlocs_elim); |
0dadecf6 RK |
2361 | #endif |
2362 | ||
eab89b90 RK |
2363 | /* Find what kind of insn this is. NOPERANDS gets number of operands. |
2364 | Make OPERANDS point to a vector of operand values. | |
2365 | Make OPERAND_LOCS point to a vector of pointers to | |
2366 | where the operands were found. | |
2367 | Fill CONSTRAINTS and CONSTRAINTS1 with pointers to the | |
2368 | constraint-strings for this insn. | |
2369 | Return if the insn needs no reload processing. */ | |
2370 | ||
2371 | switch (GET_CODE (body)) | |
2372 | { | |
2373 | case USE: | |
2374 | case CLOBBER: | |
2375 | case ASM_INPUT: | |
2376 | case ADDR_VEC: | |
2377 | case ADDR_DIFF_VEC: | |
2378 | return; | |
2379 | ||
2380 | case SET: | |
2381 | /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it | |
2382 | is cheap to move between them. If it is not, there may not be an insn | |
2383 | to do the copy, so we may need a reload. */ | |
2384 | if (GET_CODE (SET_DEST (body)) == REG | |
2385 | && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER | |
2386 | && GET_CODE (SET_SRC (body)) == REG | |
2387 | && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER | |
2388 | && REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (SET_SRC (body))), | |
2389 | REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2) | |
2390 | return; | |
2391 | case PARALLEL: | |
2392 | case ASM_OPERANDS: | |
a8c9daeb | 2393 | reload_n_operands = noperands = asm_noperands (body); |
eab89b90 RK |
2394 | if (noperands >= 0) |
2395 | { | |
2396 | /* This insn is an `asm' with operands. */ | |
2397 | ||
2398 | insn_code_number = -1; | |
2399 | this_insn_is_asm = 1; | |
2400 | ||
2401 | /* expand_asm_operands makes sure there aren't too many operands. */ | |
2402 | if (noperands > MAX_RECOG_OPERANDS) | |
2403 | abort (); | |
2404 | ||
2405 | /* Now get the operand values and constraints out of the insn. */ | |
2406 | ||
2407 | decode_asm_operands (body, recog_operand, recog_operand_loc, | |
2408 | constraints, operand_mode); | |
2409 | if (noperands > 0) | |
2410 | { | |
4c9a05bc RK |
2411 | bcopy ((char *) constraints, (char *) constraints1, |
2412 | noperands * sizeof (char *)); | |
eab89b90 RK |
2413 | n_alternatives = n_occurrences (',', constraints[0]) + 1; |
2414 | for (i = 1; i < noperands; i++) | |
d45cf215 | 2415 | if (n_alternatives != n_occurrences (',', constraints[i]) + 1) |
eab89b90 RK |
2416 | { |
2417 | error_for_asm (insn, "operand constraints differ in number of alternatives"); | |
2418 | /* Avoid further trouble with this insn. */ | |
38a448ca | 2419 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
eab89b90 RK |
2420 | n_reloads = 0; |
2421 | return; | |
2422 | } | |
2423 | } | |
2424 | break; | |
2425 | } | |
2426 | ||
2427 | default: | |
2428 | /* Ordinary insn: recognize it, get the operands via insn_extract | |
2429 | and get the constraints. */ | |
2430 | ||
2431 | insn_code_number = recog_memoized (insn); | |
2432 | if (insn_code_number < 0) | |
2433 | fatal_insn_not_found (insn); | |
2434 | ||
a8c9daeb | 2435 | reload_n_operands = noperands = insn_n_operands[insn_code_number]; |
eab89b90 RK |
2436 | n_alternatives = insn_n_alternatives[insn_code_number]; |
2437 | /* Just return "no reloads" if insn has no operands with constraints. */ | |
2438 | if (n_alternatives == 0) | |
2439 | return; | |
2440 | insn_extract (insn); | |
2441 | for (i = 0; i < noperands; i++) | |
2442 | { | |
2443 | constraints[i] = constraints1[i] | |
2444 | = insn_operand_constraint[insn_code_number][i]; | |
2445 | operand_mode[i] = insn_operand_mode[insn_code_number][i]; | |
2446 | } | |
2447 | } | |
2448 | ||
2449 | if (noperands == 0) | |
2450 | return; | |
2451 | ||
2452 | commutative = -1; | |
2453 | ||
2454 | /* If we will need to know, later, whether some pair of operands | |
2455 | are the same, we must compare them now and save the result. | |
2456 | Reloading the base and index registers will clobber them | |
2457 | and afterward they will fail to match. */ | |
2458 | ||
2459 | for (i = 0; i < noperands; i++) | |
2460 | { | |
2461 | register char *p; | |
2462 | register int c; | |
2463 | ||
2464 | substed_operand[i] = recog_operand[i]; | |
2465 | p = constraints[i]; | |
2466 | ||
a8c9daeb RK |
2467 | modified[i] = RELOAD_READ; |
2468 | ||
2469 | /* Scan this operand's constraint to see if it is an output operand, | |
2470 | an in-out operand, is commutative, or should match another. */ | |
eab89b90 | 2471 | |
51723711 | 2472 | while ((c = *p++)) |
a8c9daeb RK |
2473 | { |
2474 | if (c == '=') | |
2475 | modified[i] = RELOAD_WRITE; | |
2476 | else if (c == '+') | |
2477 | modified[i] = RELOAD_READ_WRITE; | |
2478 | else if (c == '%') | |
2479 | { | |
2480 | /* The last operand should not be marked commutative. */ | |
2481 | if (i == noperands - 1) | |
2482 | { | |
2483 | if (this_insn_is_asm) | |
2484 | warning_for_asm (this_insn, | |
2485 | "`%%' constraint used with last operand"); | |
2486 | else | |
2487 | abort (); | |
2488 | } | |
2489 | else | |
2490 | commutative = i; | |
2491 | } | |
2492 | else if (c >= '0' && c <= '9') | |
2493 | { | |
2494 | c -= '0'; | |
2495 | operands_match[c][i] | |
2496 | = operands_match_p (recog_operand[c], recog_operand[i]); | |
ea9c5b9e | 2497 | |
a8c9daeb RK |
2498 | /* An operand may not match itself. */ |
2499 | if (c == i) | |
2500 | { | |
2501 | if (this_insn_is_asm) | |
2502 | warning_for_asm (this_insn, | |
2503 | "operand %d has constraint %d", i, c); | |
2504 | else | |
2505 | abort (); | |
2506 | } | |
ea9c5b9e | 2507 | |
a8c9daeb RK |
2508 | /* If C can be commuted with C+1, and C might need to match I, |
2509 | then C+1 might also need to match I. */ | |
2510 | if (commutative >= 0) | |
2511 | { | |
2512 | if (c == commutative || c == commutative + 1) | |
2513 | { | |
2514 | int other = c + (c == commutative ? 1 : -1); | |
2515 | operands_match[other][i] | |
2516 | = operands_match_p (recog_operand[other], recog_operand[i]); | |
2517 | } | |
2518 | if (i == commutative || i == commutative + 1) | |
2519 | { | |
2520 | int other = i + (i == commutative ? 1 : -1); | |
2521 | operands_match[c][other] | |
2522 | = operands_match_p (recog_operand[c], recog_operand[other]); | |
2523 | } | |
2524 | /* Note that C is supposed to be less than I. | |
2525 | No need to consider altering both C and I because in | |
2526 | that case we would alter one into the other. */ | |
2527 | } | |
2528 | } | |
2529 | } | |
eab89b90 RK |
2530 | } |
2531 | ||
2532 | /* Examine each operand that is a memory reference or memory address | |
2533 | and reload parts of the addresses into index registers. | |
eab89b90 RK |
2534 | Also here any references to pseudo regs that didn't get hard regs |
2535 | but are equivalent to constants get replaced in the insn itself | |
2536 | with those constants. Nobody will ever see them again. | |
2537 | ||
2538 | Finally, set up the preferred classes of each operand. */ | |
2539 | ||
2540 | for (i = 0; i < noperands; i++) | |
2541 | { | |
2542 | register RTX_CODE code = GET_CODE (recog_operand[i]); | |
a8c9daeb | 2543 | |
eab89b90 | 2544 | address_reloaded[i] = 0; |
a8c9daeb RK |
2545 | operand_type[i] = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT |
2546 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT | |
2547 | : RELOAD_OTHER); | |
2548 | address_type[i] | |
2549 | = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT_ADDRESS | |
2550 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT_ADDRESS | |
2551 | : RELOAD_OTHER); | |
eab89b90 | 2552 | |
0d38001f RS |
2553 | if (*constraints[i] == 0) |
2554 | /* Ignore things like match_operator operands. */ | |
2555 | ; | |
2556 | else if (constraints[i][0] == 'p') | |
eab89b90 | 2557 | { |
fb3821f7 | 2558 | find_reloads_address (VOIDmode, NULL_PTR, |
eab89b90 | 2559 | recog_operand[i], recog_operand_loc[i], |
55c22565 | 2560 | i, operand_type[i], ind_levels, insn); |
b685dbae RK |
2561 | |
2562 | /* If we now have a simple operand where we used to have a | |
2563 | PLUS or MULT, re-recognize and try again. */ | |
2564 | if ((GET_RTX_CLASS (GET_CODE (*recog_operand_loc[i])) == 'o' | |
2565 | || GET_CODE (*recog_operand_loc[i]) == SUBREG) | |
2566 | && (GET_CODE (recog_operand[i]) == MULT | |
2567 | || GET_CODE (recog_operand[i]) == PLUS)) | |
2568 | { | |
2569 | INSN_CODE (insn) = -1; | |
2570 | find_reloads (insn, replace, ind_levels, live_known, | |
2571 | reload_reg_p); | |
2572 | return; | |
2573 | } | |
2574 | ||
eab89b90 RK |
2575 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; |
2576 | } | |
2577 | else if (code == MEM) | |
2578 | { | |
2579 | if (find_reloads_address (GET_MODE (recog_operand[i]), | |
2580 | recog_operand_loc[i], | |
2581 | XEXP (recog_operand[i], 0), | |
2582 | &XEXP (recog_operand[i], 0), | |
55c22565 | 2583 | i, address_type[i], ind_levels, insn)) |
eab89b90 RK |
2584 | address_reloaded[i] = 1; |
2585 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; | |
2586 | } | |
2587 | else if (code == SUBREG) | |
b60a8416 R |
2588 | { |
2589 | rtx reg = SUBREG_REG (recog_operand[i]); | |
2590 | rtx op | |
2591 | = find_reloads_toplev (recog_operand[i], i, address_type[i], | |
2592 | ind_levels, | |
2593 | set != 0 | |
2594 | && &SET_DEST (set) == recog_operand_loc[i]); | |
2595 | ||
2596 | /* If we made a MEM to load (a part of) the stackslot of a pseudo | |
2597 | that didn't get a hard register, emit a USE with a REG_EQUAL | |
2598 | note in front so that we might inherit a previous, possibly | |
2599 | wider reload. */ | |
2600 | ||
2601 | if (GET_CODE (op) == MEM | |
2602 | && GET_CODE (reg) == REG | |
2603 | && (GET_MODE_SIZE (GET_MODE (reg)) | |
2604 | >= GET_MODE_SIZE (GET_MODE (op)))) | |
2605 | REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode, reg), insn)) | |
2606 | = gen_rtx_EXPR_LIST (REG_EQUAL, | |
2607 | reg_equiv_memory_loc[REGNO (reg)], NULL_RTX); | |
2608 | ||
2609 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i] = op; | |
2610 | } | |
ff428c90 ILT |
2611 | else if (code == PLUS || GET_RTX_CLASS (code) == '1') |
2612 | /* We can get a PLUS as an "operand" as a result of register | |
2613 | elimination. See eliminate_regs and gen_reload. We handle | |
2614 | a unary operator by reloading the operand. */ | |
944d7b14 RS |
2615 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i] |
2616 | = find_reloads_toplev (recog_operand[i], i, address_type[i], | |
2617 | ind_levels, 0); | |
eab89b90 RK |
2618 | else if (code == REG) |
2619 | { | |
2620 | /* This is equivalent to calling find_reloads_toplev. | |
2621 | The code is duplicated for speed. | |
2622 | When we find a pseudo always equivalent to a constant, | |
2623 | we replace it by the constant. We must be sure, however, | |
2624 | that we don't try to replace it in the insn in which it | |
2625 | is being set. */ | |
2626 | register int regno = REGNO (recog_operand[i]); | |
2627 | if (reg_equiv_constant[regno] != 0 | |
2628 | && (set == 0 || &SET_DEST (set) != recog_operand_loc[i])) | |
2629 | substed_operand[i] = recog_operand[i] | |
2630 | = reg_equiv_constant[regno]; | |
2631 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
2632 | that feeds this insn. */ | |
2633 | if (reg_equiv_mem[regno] != 0) | |
2634 | substed_operand[i] = recog_operand[i] | |
2635 | = reg_equiv_mem[regno]; | |
2636 | #endif | |
2637 | if (reg_equiv_address[regno] != 0) | |
2638 | { | |
2639 | /* If reg_equiv_address is not a constant address, copy it, | |
2640 | since it may be shared. */ | |
4ffeab02 JW |
2641 | /* We must rerun eliminate_regs, in case the elimination |
2642 | offsets have changed. */ | |
2643 | rtx address = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], | |
1914f5da | 2644 | 0, NULL_RTX), |
4ffeab02 | 2645 | 0); |
eab89b90 RK |
2646 | |
2647 | if (rtx_varies_p (address)) | |
2648 | address = copy_rtx (address); | |
2649 | ||
b60a8416 R |
2650 | /* Emit a USE that shows what register is being used/modified. */ |
2651 | REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode, | |
2652 | recog_operand[i]), | |
2653 | insn)) | |
2654 | = gen_rtx_EXPR_LIST (REG_EQUAL, | |
2655 | reg_equiv_memory_loc[regno], | |
2656 | NULL_RTX); | |
eab89b90 RK |
2657 | |
2658 | *recog_operand_loc[i] = recog_operand[i] | |
38a448ca | 2659 | = gen_rtx_MEM (GET_MODE (recog_operand[i]), address); |
eab89b90 RK |
2660 | RTX_UNCHANGING_P (recog_operand[i]) |
2661 | = RTX_UNCHANGING_P (regno_reg_rtx[regno]); | |
2662 | find_reloads_address (GET_MODE (recog_operand[i]), | |
130659a4 | 2663 | recog_operand_loc[i], |
eab89b90 RK |
2664 | XEXP (recog_operand[i], 0), |
2665 | &XEXP (recog_operand[i], 0), | |
55c22565 | 2666 | i, address_type[i], ind_levels, insn); |
eab89b90 RK |
2667 | substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; |
2668 | } | |
2669 | } | |
aaf9712e RS |
2670 | /* If the operand is still a register (we didn't replace it with an |
2671 | equivalent), get the preferred class to reload it into. */ | |
2672 | code = GET_CODE (recog_operand[i]); | |
2673 | preferred_class[i] | |
91f9a6ed | 2674 | = ((code == REG && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) |
aaf9712e RS |
2675 | ? reg_preferred_class (REGNO (recog_operand[i])) : NO_REGS); |
2676 | pref_or_nothing[i] | |
91f9a6ed | 2677 | = (code == REG && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER |
e4600702 | 2678 | && reg_alternate_class (REGNO (recog_operand[i])) == NO_REGS); |
eab89b90 RK |
2679 | } |
2680 | ||
2681 | /* If this is simply a copy from operand 1 to operand 0, merge the | |
2682 | preferred classes for the operands. */ | |
2683 | if (set != 0 && noperands >= 2 && recog_operand[0] == SET_DEST (set) | |
2684 | && recog_operand[1] == SET_SRC (set)) | |
2685 | { | |
2686 | preferred_class[0] = preferred_class[1] | |
2687 | = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]]; | |
2688 | pref_or_nothing[0] |= pref_or_nothing[1]; | |
2689 | pref_or_nothing[1] |= pref_or_nothing[0]; | |
2690 | } | |
2691 | ||
2692 | /* Now see what we need for pseudo-regs that didn't get hard regs | |
2693 | or got the wrong kind of hard reg. For this, we must consider | |
2694 | all the operands together against the register constraints. */ | |
2695 | ||
812f2051 | 2696 | best = MAX_RECOG_OPERANDS * 2 + 600; |
eab89b90 RK |
2697 | |
2698 | swapped = 0; | |
2699 | goal_alternative_swapped = 0; | |
2700 | try_swapped: | |
2701 | ||
2702 | /* The constraints are made of several alternatives. | |
2703 | Each operand's constraint looks like foo,bar,... with commas | |
2704 | separating the alternatives. The first alternatives for all | |
2705 | operands go together, the second alternatives go together, etc. | |
2706 | ||
2707 | First loop over alternatives. */ | |
2708 | ||
2709 | for (this_alternative_number = 0; | |
2710 | this_alternative_number < n_alternatives; | |
2711 | this_alternative_number++) | |
2712 | { | |
2713 | /* Loop over operands for one constraint alternative. */ | |
2714 | /* LOSERS counts those that don't fit this alternative | |
2715 | and would require loading. */ | |
2716 | int losers = 0; | |
2717 | /* BAD is set to 1 if it some operand can't fit this alternative | |
2718 | even after reloading. */ | |
2719 | int bad = 0; | |
2720 | /* REJECT is a count of how undesirable this alternative says it is | |
2721 | if any reloading is required. If the alternative matches exactly | |
2722 | then REJECT is ignored, but otherwise it gets this much | |
2723 | counted against it in addition to the reloading needed. Each | |
2724 | ? counts three times here since we want the disparaging caused by | |
2725 | a bad register class to only count 1/3 as much. */ | |
2726 | int reject = 0; | |
2727 | ||
2728 | this_earlyclobber = 0; | |
2729 | ||
2730 | for (i = 0; i < noperands; i++) | |
2731 | { | |
2732 | register char *p = constraints[i]; | |
2733 | register int win = 0; | |
2734 | /* 0 => this operand can be reloaded somehow for this alternative */ | |
2735 | int badop = 1; | |
2736 | /* 0 => this operand can be reloaded if the alternative allows regs. */ | |
2737 | int winreg = 0; | |
2738 | int c; | |
2739 | register rtx operand = recog_operand[i]; | |
2740 | int offset = 0; | |
2741 | /* Nonzero means this is a MEM that must be reloaded into a reg | |
2742 | regardless of what the constraint says. */ | |
2743 | int force_reload = 0; | |
2744 | int offmemok = 0; | |
9d926da5 RK |
2745 | /* Nonzero if a constant forced into memory would be OK for this |
2746 | operand. */ | |
2747 | int constmemok = 0; | |
eab89b90 RK |
2748 | int earlyclobber = 0; |
2749 | ||
ff428c90 ILT |
2750 | /* If the predicate accepts a unary operator, it means that |
2751 | we need to reload the operand. */ | |
2752 | if (GET_RTX_CLASS (GET_CODE (operand)) == '1') | |
2753 | operand = XEXP (operand, 0); | |
2754 | ||
eab89b90 RK |
2755 | /* If the operand is a SUBREG, extract |
2756 | the REG or MEM (or maybe even a constant) within. | |
2757 | (Constants can occur as a result of reg_equiv_constant.) */ | |
2758 | ||
2759 | while (GET_CODE (operand) == SUBREG) | |
2760 | { | |
2761 | offset += SUBREG_WORD (operand); | |
2762 | operand = SUBREG_REG (operand); | |
38e01259 | 2763 | /* Force reload if this is a constant or PLUS or if there may |
a61c98cf RK |
2764 | be a problem accessing OPERAND in the outer mode. */ |
2765 | if (CONSTANT_P (operand) | |
ca769828 | 2766 | || GET_CODE (operand) == PLUS |
03b72c86 RK |
2767 | /* We must force a reload of paradoxical SUBREGs |
2768 | of a MEM because the alignment of the inner value | |
beb5a9b8 RK |
2769 | may not be enough to do the outer reference. On |
2770 | big-endian machines, it may also reference outside | |
2771 | the object. | |
03b72c86 RK |
2772 | |
2773 | On machines that extend byte operations and we have a | |
486d8509 RK |
2774 | SUBREG where both the inner and outer modes are no wider |
2775 | than a word and the inner mode is narrower, is integral, | |
2776 | and gets extended when loaded from memory, combine.c has | |
2777 | made assumptions about the behavior of the machine in such | |
03b72c86 RK |
2778 | register access. If the data is, in fact, in memory we |
2779 | must always load using the size assumed to be in the | |
2780 | register and let the insn do the different-sized | |
5ec105cd RH |
2781 | accesses. |
2782 | ||
2783 | This is doubly true if WORD_REGISTER_OPERATIONS. In | |
2784 | this case eliminate_regs has left non-paradoxical | |
2785 | subregs for push_reloads to see. Make sure it does | |
2786 | by forcing the reload. | |
2787 | ||
2788 | ??? When is it right at this stage to have a subreg | |
2789 | of a mem that is _not_ to be handled specialy? IMO | |
2790 | those should have been reduced to just a mem. */ | |
a61c98cf RK |
2791 | || ((GET_CODE (operand) == MEM |
2792 | || (GET_CODE (operand)== REG | |
2793 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) | |
5ec105cd | 2794 | #ifndef WORD_REGISTER_OPERATIONS |
03b72c86 RK |
2795 | && (((GET_MODE_BITSIZE (GET_MODE (operand)) |
2796 | < BIGGEST_ALIGNMENT) | |
2797 | && (GET_MODE_SIZE (operand_mode[i]) | |
2798 | > GET_MODE_SIZE (GET_MODE (operand)))) | |
beb5a9b8 | 2799 | || (GET_CODE (operand) == MEM && BYTES_BIG_ENDIAN) |
03b72c86 RK |
2800 | #ifdef LOAD_EXTEND_OP |
2801 | || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD | |
2802 | && (GET_MODE_SIZE (GET_MODE (operand)) | |
2803 | <= UNITS_PER_WORD) | |
2804 | && (GET_MODE_SIZE (operand_mode[i]) | |
486d8509 RK |
2805 | > GET_MODE_SIZE (GET_MODE (operand))) |
2806 | && INTEGRAL_MODE_P (GET_MODE (operand)) | |
2807 | && LOAD_EXTEND_OP (GET_MODE (operand)) != NIL) | |
46da6b3a | 2808 | #endif |
5ec105cd RH |
2809 | ) |
2810 | #endif | |
2811 | ) | |
eab89b90 RK |
2812 | /* Subreg of a hard reg which can't handle the subreg's mode |
2813 | or which would handle that mode in the wrong number of | |
2814 | registers for subregging to work. */ | |
a61c98cf RK |
2815 | || (GET_CODE (operand) == REG |
2816 | && REGNO (operand) < FIRST_PSEUDO_REGISTER | |
f72ccbe6 RK |
2817 | && ((GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD |
2818 | && (GET_MODE_SIZE (GET_MODE (operand)) | |
2819 | > UNITS_PER_WORD) | |
2820 | && ((GET_MODE_SIZE (GET_MODE (operand)) | |
2821 | / UNITS_PER_WORD) | |
2822 | != HARD_REGNO_NREGS (REGNO (operand), | |
2823 | GET_MODE (operand)))) | |
2824 | || ! HARD_REGNO_MODE_OK (REGNO (operand) + offset, | |
2825 | operand_mode[i])))) | |
eab89b90 RK |
2826 | force_reload = 1; |
2827 | } | |
2828 | ||
2829 | this_alternative[i] = (int) NO_REGS; | |
2830 | this_alternative_win[i] = 0; | |
2831 | this_alternative_offmemok[i] = 0; | |
2832 | this_alternative_earlyclobber[i] = 0; | |
2833 | this_alternative_matches[i] = -1; | |
2834 | ||
2835 | /* An empty constraint or empty alternative | |
2836 | allows anything which matched the pattern. */ | |
2837 | if (*p == 0 || *p == ',') | |
2838 | win = 1, badop = 0; | |
2839 | ||
2840 | /* Scan this alternative's specs for this operand; | |
2841 | set WIN if the operand fits any letter in this alternative. | |
2842 | Otherwise, clear BADOP if this operand could | |
2843 | fit some letter after reloads, | |
2844 | or set WINREG if this operand could fit after reloads | |
2845 | provided the constraint allows some registers. */ | |
2846 | ||
2847 | while (*p && (c = *p++) != ',') | |
2848 | switch (c) | |
2849 | { | |
2850 | case '=': | |
eab89b90 | 2851 | case '+': |
eab89b90 RK |
2852 | case '*': |
2853 | break; | |
2854 | ||
2855 | case '%': | |
42add480 TW |
2856 | /* The last operand should not be marked commutative. */ |
2857 | if (i != noperands - 1) | |
2858 | commutative = i; | |
eab89b90 RK |
2859 | break; |
2860 | ||
2861 | case '?': | |
812f2051 | 2862 | reject += 6; |
eab89b90 RK |
2863 | break; |
2864 | ||
2865 | case '!': | |
812f2051 | 2866 | reject = 600; |
eab89b90 RK |
2867 | break; |
2868 | ||
2869 | case '#': | |
2870 | /* Ignore rest of this alternative as far as | |
2871 | reloading is concerned. */ | |
2872 | while (*p && *p != ',') p++; | |
2873 | break; | |
2874 | ||
2875 | case '0': | |
2876 | case '1': | |
2877 | case '2': | |
2878 | case '3': | |
2879 | case '4': | |
2880 | c -= '0'; | |
2881 | this_alternative_matches[i] = c; | |
2882 | /* We are supposed to match a previous operand. | |
2883 | If we do, we win if that one did. | |
2884 | If we do not, count both of the operands as losers. | |
2885 | (This is too conservative, since most of the time | |
2886 | only a single reload insn will be needed to make | |
2887 | the two operands win. As a result, this alternative | |
2888 | may be rejected when it is actually desirable.) */ | |
2889 | if ((swapped && (c != commutative || i != commutative + 1)) | |
2890 | /* If we are matching as if two operands were swapped, | |
2891 | also pretend that operands_match had been computed | |
2892 | with swapped. | |
2893 | But if I is the second of those and C is the first, | |
2894 | don't exchange them, because operands_match is valid | |
2895 | only on one side of its diagonal. */ | |
2896 | ? (operands_match | |
2897 | [(c == commutative || c == commutative + 1) | |
2898 | ? 2*commutative + 1 - c : c] | |
2899 | [(i == commutative || i == commutative + 1) | |
2900 | ? 2*commutative + 1 - i : i]) | |
2901 | : operands_match[c][i]) | |
fc79eafe JW |
2902 | { |
2903 | /* If we are matching a non-offsettable address where an | |
2904 | offsettable address was expected, then we must reject | |
2905 | this combination, because we can't reload it. */ | |
2906 | if (this_alternative_offmemok[c] | |
2907 | && GET_CODE (recog_operand[c]) == MEM | |
2908 | && this_alternative[c] == (int) NO_REGS | |
2909 | && ! this_alternative_win[c]) | |
2910 | bad = 1; | |
2911 | ||
2912 | win = this_alternative_win[c]; | |
2913 | } | |
eab89b90 RK |
2914 | else |
2915 | { | |
2916 | /* Operands don't match. */ | |
2917 | rtx value; | |
2918 | /* Retroactively mark the operand we had to match | |
2919 | as a loser, if it wasn't already. */ | |
2920 | if (this_alternative_win[c]) | |
2921 | losers++; | |
2922 | this_alternative_win[c] = 0; | |
2923 | if (this_alternative[c] == (int) NO_REGS) | |
2924 | bad = 1; | |
2925 | /* But count the pair only once in the total badness of | |
2926 | this alternative, if the pair can be a dummy reload. */ | |
2927 | value | |
2928 | = find_dummy_reload (recog_operand[i], recog_operand[c], | |
2929 | recog_operand_loc[i], recog_operand_loc[c], | |
adb44af8 | 2930 | operand_mode[i], operand_mode[c], |
189086f9 RK |
2931 | this_alternative[c], -1, |
2932 | this_alternative_earlyclobber[c]); | |
eab89b90 RK |
2933 | |
2934 | if (value != 0) | |
2935 | losers--; | |
2936 | } | |
2937 | /* This can be fixed with reloads if the operand | |
2938 | we are supposed to match can be fixed with reloads. */ | |
2939 | badop = 0; | |
2940 | this_alternative[i] = this_alternative[c]; | |
e64c4f9e RK |
2941 | |
2942 | /* If we have to reload this operand and some previous | |
2943 | operand also had to match the same thing as this | |
2944 | operand, we don't know how to do that. So reject this | |
2945 | alternative. */ | |
2946 | if (! win || force_reload) | |
2947 | for (j = 0; j < i; j++) | |
2948 | if (this_alternative_matches[j] | |
2949 | == this_alternative_matches[i]) | |
2950 | badop = 1; | |
2951 | ||
eab89b90 RK |
2952 | break; |
2953 | ||
2954 | case 'p': | |
2955 | /* All necessary reloads for an address_operand | |
2956 | were handled in find_reloads_address. */ | |
5c73e847 | 2957 | this_alternative[i] = (int) BASE_REG_CLASS; |
eab89b90 RK |
2958 | win = 1; |
2959 | break; | |
2960 | ||
2961 | case 'm': | |
2962 | if (force_reload) | |
2963 | break; | |
2964 | if (GET_CODE (operand) == MEM | |
2965 | || (GET_CODE (operand) == REG | |
2966 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
2967 | && reg_renumber[REGNO (operand)] < 0)) | |
2968 | win = 1; | |
3feffdfe JW |
2969 | if (CONSTANT_P (operand) |
2970 | /* force_const_mem does not accept HIGH. */ | |
2971 | && GET_CODE (operand) != HIGH) | |
eab89b90 | 2972 | badop = 0; |
9d926da5 | 2973 | constmemok = 1; |
eab89b90 RK |
2974 | break; |
2975 | ||
2976 | case '<': | |
2977 | if (GET_CODE (operand) == MEM | |
2978 | && ! address_reloaded[i] | |
2979 | && (GET_CODE (XEXP (operand, 0)) == PRE_DEC | |
2980 | || GET_CODE (XEXP (operand, 0)) == POST_DEC)) | |
2981 | win = 1; | |
2982 | break; | |
2983 | ||
2984 | case '>': | |
2985 | if (GET_CODE (operand) == MEM | |
2986 | && ! address_reloaded[i] | |
2987 | && (GET_CODE (XEXP (operand, 0)) == PRE_INC | |
2988 | || GET_CODE (XEXP (operand, 0)) == POST_INC)) | |
2989 | win = 1; | |
2990 | break; | |
2991 | ||
2992 | /* Memory operand whose address is not offsettable. */ | |
2993 | case 'V': | |
2994 | if (force_reload) | |
2995 | break; | |
2996 | if (GET_CODE (operand) == MEM | |
2997 | && ! (ind_levels ? offsettable_memref_p (operand) | |
2998 | : offsettable_nonstrict_memref_p (operand)) | |
2999 | /* Certain mem addresses will become offsettable | |
3000 | after they themselves are reloaded. This is important; | |
3001 | we don't want our own handling of unoffsettables | |
3002 | to override the handling of reg_equiv_address. */ | |
3003 | && !(GET_CODE (XEXP (operand, 0)) == REG | |
3004 | && (ind_levels == 0 | |
3005 | || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0))) | |
3006 | win = 1; | |
3007 | break; | |
3008 | ||
3009 | /* Memory operand whose address is offsettable. */ | |
3010 | case 'o': | |
3011 | if (force_reload) | |
3012 | break; | |
3013 | if ((GET_CODE (operand) == MEM | |
3014 | /* If IND_LEVELS, find_reloads_address won't reload a | |
3015 | pseudo that didn't get a hard reg, so we have to | |
3016 | reject that case. */ | |
3017 | && (ind_levels ? offsettable_memref_p (operand) | |
3018 | : offsettable_nonstrict_memref_p (operand))) | |
26ba4aee JW |
3019 | /* A reloaded auto-increment address is offsettable, |
3020 | because it is now just a simple register indirect. */ | |
3021 | || (GET_CODE (operand) == MEM | |
3022 | && address_reloaded[i] | |
3023 | && (GET_CODE (XEXP (operand, 0)) == PRE_INC | |
3024 | || GET_CODE (XEXP (operand, 0)) == PRE_DEC | |
3025 | || GET_CODE (XEXP (operand, 0)) == POST_INC | |
3026 | || GET_CODE (XEXP (operand, 0)) == POST_DEC)) | |
eab89b90 RK |
3027 | /* Certain mem addresses will become offsettable |
3028 | after they themselves are reloaded. This is important; | |
3029 | we don't want our own handling of unoffsettables | |
3030 | to override the handling of reg_equiv_address. */ | |
3031 | || (GET_CODE (operand) == MEM | |
3032 | && GET_CODE (XEXP (operand, 0)) == REG | |
3033 | && (ind_levels == 0 | |
3034 | || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0)) | |
3035 | || (GET_CODE (operand) == REG | |
3036 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
3a322c50 RK |
3037 | && reg_renumber[REGNO (operand)] < 0 |
3038 | /* If reg_equiv_address is nonzero, we will be | |
3039 | loading it into a register; hence it will be | |
3040 | offsettable, but we cannot say that reg_equiv_mem | |
3041 | is offsettable without checking. */ | |
3042 | && ((reg_equiv_mem[REGNO (operand)] != 0 | |
3043 | && offsettable_memref_p (reg_equiv_mem[REGNO (operand)])) | |
3044 | || (reg_equiv_address[REGNO (operand)] != 0)))) | |
eab89b90 | 3045 | win = 1; |
3feffdfe JW |
3046 | /* force_const_mem does not accept HIGH. */ |
3047 | if ((CONSTANT_P (operand) && GET_CODE (operand) != HIGH) | |
3048 | || GET_CODE (operand) == MEM) | |
eab89b90 | 3049 | badop = 0; |
9d926da5 | 3050 | constmemok = 1; |
eab89b90 RK |
3051 | offmemok = 1; |
3052 | break; | |
3053 | ||
3054 | case '&': | |
3055 | /* Output operand that is stored before the need for the | |
3056 | input operands (and their index registers) is over. */ | |
3057 | earlyclobber = 1, this_earlyclobber = 1; | |
3058 | break; | |
3059 | ||
3060 | case 'E': | |
293166be | 3061 | #ifndef REAL_ARITHMETIC |
eab89b90 RK |
3062 | /* Match any floating double constant, but only if |
3063 | we can examine the bits of it reliably. */ | |
3064 | if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT | |
fb3821f7 | 3065 | || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) |
eab89b90 RK |
3066 | && GET_MODE (operand) != VOIDmode && ! flag_pretend_float) |
3067 | break; | |
293166be | 3068 | #endif |
eab89b90 RK |
3069 | if (GET_CODE (operand) == CONST_DOUBLE) |
3070 | win = 1; | |
3071 | break; | |
3072 | ||
3073 | case 'F': | |
3074 | if (GET_CODE (operand) == CONST_DOUBLE) | |
3075 | win = 1; | |
3076 | break; | |
3077 | ||
3078 | case 'G': | |
3079 | case 'H': | |
3080 | if (GET_CODE (operand) == CONST_DOUBLE | |
3081 | && CONST_DOUBLE_OK_FOR_LETTER_P (operand, c)) | |
3082 | win = 1; | |
3083 | break; | |
3084 | ||
3085 | case 's': | |
3086 | if (GET_CODE (operand) == CONST_INT | |
3087 | || (GET_CODE (operand) == CONST_DOUBLE | |
3088 | && GET_MODE (operand) == VOIDmode)) | |
3089 | break; | |
3090 | case 'i': | |
3091 | if (CONSTANT_P (operand) | |
3092 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
3093 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand)) | |
3094 | #endif | |
3095 | ) | |
3096 | win = 1; | |
3097 | break; | |
3098 | ||
3099 | case 'n': | |
3100 | if (GET_CODE (operand) == CONST_INT | |
3101 | || (GET_CODE (operand) == CONST_DOUBLE | |
3102 | && GET_MODE (operand) == VOIDmode)) | |
3103 | win = 1; | |
3104 | break; | |
3105 | ||
3106 | case 'I': | |
3107 | case 'J': | |
3108 | case 'K': | |
3109 | case 'L': | |
3110 | case 'M': | |
3111 | case 'N': | |
3112 | case 'O': | |
3113 | case 'P': | |
3114 | if (GET_CODE (operand) == CONST_INT | |
3115 | && CONST_OK_FOR_LETTER_P (INTVAL (operand), c)) | |
3116 | win = 1; | |
3117 | break; | |
3118 | ||
3119 | case 'X': | |
3120 | win = 1; | |
3121 | break; | |
3122 | ||
3123 | case 'g': | |
3124 | if (! force_reload | |
3125 | /* A PLUS is never a valid operand, but reload can make | |
3126 | it from a register when eliminating registers. */ | |
3127 | && GET_CODE (operand) != PLUS | |
3128 | /* A SCRATCH is not a valid operand. */ | |
3129 | && GET_CODE (operand) != SCRATCH | |
3130 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
3131 | && (! CONSTANT_P (operand) | |
3132 | || ! flag_pic | |
3133 | || LEGITIMATE_PIC_OPERAND_P (operand)) | |
3134 | #endif | |
3135 | && (GENERAL_REGS == ALL_REGS | |
3136 | || GET_CODE (operand) != REG | |
3137 | || (REGNO (operand) >= FIRST_PSEUDO_REGISTER | |
3138 | && reg_renumber[REGNO (operand)] < 0))) | |
3139 | win = 1; | |
3140 | /* Drop through into 'r' case */ | |
3141 | ||
3142 | case 'r': | |
3143 | this_alternative[i] | |
3144 | = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS]; | |
3145 | goto reg; | |
3146 | ||
3147 | #ifdef EXTRA_CONSTRAINT | |
3148 | case 'Q': | |
3149 | case 'R': | |
3150 | case 'S': | |
3151 | case 'T': | |
3152 | case 'U': | |
3153 | if (EXTRA_CONSTRAINT (operand, c)) | |
3154 | win = 1; | |
3155 | break; | |
3156 | #endif | |
3157 | ||
3158 | default: | |
3159 | this_alternative[i] | |
3160 | = (int) reg_class_subunion[this_alternative[i]][(int) REG_CLASS_FROM_LETTER (c)]; | |
3161 | ||
3162 | reg: | |
3163 | if (GET_MODE (operand) == BLKmode) | |
3164 | break; | |
3165 | winreg = 1; | |
3166 | if (GET_CODE (operand) == REG | |
3167 | && reg_fits_class_p (operand, this_alternative[i], | |
3168 | offset, GET_MODE (recog_operand[i]))) | |
3169 | win = 1; | |
3170 | break; | |
3171 | } | |
3172 | ||
3173 | constraints[i] = p; | |
3174 | ||
3175 | /* If this operand could be handled with a reg, | |
3176 | and some reg is allowed, then this operand can be handled. */ | |
3177 | if (winreg && this_alternative[i] != (int) NO_REGS) | |
3178 | badop = 0; | |
3179 | ||
3180 | /* Record which operands fit this alternative. */ | |
3181 | this_alternative_earlyclobber[i] = earlyclobber; | |
3182 | if (win && ! force_reload) | |
3183 | this_alternative_win[i] = 1; | |
3184 | else | |
3185 | { | |
9d926da5 RK |
3186 | int const_to_mem = 0; |
3187 | ||
eab89b90 RK |
3188 | this_alternative_offmemok[i] = offmemok; |
3189 | losers++; | |
3190 | if (badop) | |
3191 | bad = 1; | |
3192 | /* Alternative loses if it has no regs for a reg operand. */ | |
3193 | if (GET_CODE (operand) == REG | |
3194 | && this_alternative[i] == (int) NO_REGS | |
3195 | && this_alternative_matches[i] < 0) | |
3196 | bad = 1; | |
3197 | ||
3a322c50 RK |
3198 | /* If this is a constant that is reloaded into the desired |
3199 | class by copying it to memory first, count that as another | |
3200 | reload. This is consistent with other code and is | |
293166be | 3201 | required to avoid choosing another alternative when |
3a322c50 RK |
3202 | the constant is moved into memory by this function on |
3203 | an early reload pass. Note that the test here is | |
3204 | precisely the same as in the code below that calls | |
3205 | force_const_mem. */ | |
3206 | if (CONSTANT_P (operand) | |
59f25cf9 RK |
3207 | /* force_const_mem does not accept HIGH. */ |
3208 | && GET_CODE (operand) != HIGH | |
e5e809f4 | 3209 | && ((PREFERRED_RELOAD_CLASS (operand, |
3a322c50 | 3210 | (enum reg_class) this_alternative[i]) |
e5e809f4 JL |
3211 | == NO_REGS) |
3212 | || no_input_reloads) | |
3a322c50 | 3213 | && operand_mode[i] != VOIDmode) |
9d926da5 RK |
3214 | { |
3215 | const_to_mem = 1; | |
3216 | if (this_alternative[i] != (int) NO_REGS) | |
3217 | losers++; | |
3218 | } | |
3a322c50 | 3219 | |
5e6aa513 RK |
3220 | /* If we can't reload this value at all, reject this |
3221 | alternative. Note that we could also lose due to | |
3222 | LIMIT_RELOAD_RELOAD_CLASS, but we don't check that | |
3223 | here. */ | |
3224 | ||
3225 | if (! CONSTANT_P (operand) | |
73b236b5 | 3226 | && (enum reg_class) this_alternative[i] != NO_REGS |
5e6aa513 RK |
3227 | && (PREFERRED_RELOAD_CLASS (operand, |
3228 | (enum reg_class) this_alternative[i]) | |
3229 | == NO_REGS)) | |
3230 | bad = 1; | |
3231 | ||
e5e809f4 JL |
3232 | /* Alternative loses if it requires a type of reload not |
3233 | permitted for this insn. We can always reload SCRATCH | |
3234 | and objects with a REG_UNUSED note. */ | |
3235 | else if (GET_CODE (operand) != SCRATCH | |
3236 | && modified[i] != RELOAD_READ && no_output_reloads | |
3237 | && ! find_reg_note (insn, REG_UNUSED, operand)) | |
3238 | bad = 1; | |
3239 | else if (modified[i] != RELOAD_WRITE && no_input_reloads | |
3240 | && ! const_to_mem) | |
3241 | bad = 1; | |
3242 | ||
3243 | ||
eab89b90 RK |
3244 | /* We prefer to reload pseudos over reloading other things, |
3245 | since such reloads may be able to be eliminated later. | |
3246 | If we are reloading a SCRATCH, we won't be generating any | |
3247 | insns, just using a register, so it is also preferred. | |
9d926da5 RK |
3248 | So bump REJECT in other cases. Don't do this in the |
3249 | case where we are forcing a constant into memory and | |
3250 | it will then win since we don't want to have a different | |
3251 | alternative match then. */ | |
915bb763 RK |
3252 | if (! (GET_CODE (operand) == REG |
3253 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER) | |
9d926da5 RK |
3254 | && GET_CODE (operand) != SCRATCH |
3255 | && ! (const_to_mem && constmemok)) | |
812f2051 R |
3256 | reject += 2; |
3257 | ||
3258 | /* Input reloads can be inherited more often than output | |
3259 | reloads can be removed, so penalize output reloads. */ | |
3260 | if (operand_type[i] != RELOAD_FOR_INPUT) | |
eab89b90 RK |
3261 | reject++; |
3262 | } | |
3263 | ||
3264 | /* If this operand is a pseudo register that didn't get a hard | |
3265 | reg and this alternative accepts some register, see if the | |
3266 | class that we want is a subset of the preferred class for this | |
3267 | register. If not, but it intersects that class, use the | |
3268 | preferred class instead. If it does not intersect the preferred | |
3269 | class, show that usage of this alternative should be discouraged; | |
3270 | it will be discouraged more still if the register is `preferred | |
3271 | or nothing'. We do this because it increases the chance of | |
3272 | reusing our spill register in a later insn and avoiding a pair | |
3273 | of memory stores and loads. | |
3274 | ||
3275 | Don't bother with this if this alternative will accept this | |
3276 | operand. | |
3277 | ||
a2d353e5 RK |
3278 | Don't do this for a multiword operand, since it is only a |
3279 | small win and has the risk of requiring more spill registers, | |
3280 | which could cause a large loss. | |
5aa14fee | 3281 | |
eab89b90 RK |
3282 | Don't do this if the preferred class has only one register |
3283 | because we might otherwise exhaust the class. */ | |
3284 | ||
3285 | ||
3286 | if (! win && this_alternative[i] != (int) NO_REGS | |
5aa14fee | 3287 | && GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD |
eab89b90 RK |
3288 | && reg_class_size[(int) preferred_class[i]] > 1) |
3289 | { | |
3290 | if (! reg_class_subset_p (this_alternative[i], | |
3291 | preferred_class[i])) | |
3292 | { | |
3293 | /* Since we don't have a way of forming the intersection, | |
3294 | we just do something special if the preferred class | |
3295 | is a subset of the class we have; that's the most | |
3296 | common case anyway. */ | |
3297 | if (reg_class_subset_p (preferred_class[i], | |
3298 | this_alternative[i])) | |
3299 | this_alternative[i] = (int) preferred_class[i]; | |
3300 | else | |
812f2051 | 3301 | reject += (2 + 2 * pref_or_nothing[i]); |
eab89b90 RK |
3302 | } |
3303 | } | |
3304 | } | |
3305 | ||
3306 | /* Now see if any output operands that are marked "earlyclobber" | |
3307 | in this alternative conflict with any input operands | |
3308 | or any memory addresses. */ | |
3309 | ||
3310 | for (i = 0; i < noperands; i++) | |
3311 | if (this_alternative_earlyclobber[i] | |
3312 | && this_alternative_win[i]) | |
3313 | { | |
3314 | struct decomposition early_data; | |
eab89b90 RK |
3315 | |
3316 | early_data = decompose (recog_operand[i]); | |
3317 | ||
3318 | if (modified[i] == RELOAD_READ) | |
3319 | { | |
3320 | if (this_insn_is_asm) | |
3321 | warning_for_asm (this_insn, | |
3322 | "`&' constraint used with input operand"); | |
3323 | else | |
3324 | abort (); | |
3325 | continue; | |
3326 | } | |
3327 | ||
3328 | if (this_alternative[i] == NO_REGS) | |
3329 | { | |
3330 | this_alternative_earlyclobber[i] = 0; | |
3331 | if (this_insn_is_asm) | |
3332 | error_for_asm (this_insn, | |
3333 | "`&' constraint used with no register class"); | |
3334 | else | |
3335 | abort (); | |
3336 | } | |
3337 | ||
3338 | for (j = 0; j < noperands; j++) | |
3339 | /* Is this an input operand or a memory ref? */ | |
3340 | if ((GET_CODE (recog_operand[j]) == MEM | |
3341 | || modified[j] != RELOAD_WRITE) | |
3342 | && j != i | |
3343 | /* Ignore things like match_operator operands. */ | |
3344 | && *constraints1[j] != 0 | |
3345 | /* Don't count an input operand that is constrained to match | |
3346 | the early clobber operand. */ | |
3347 | && ! (this_alternative_matches[j] == i | |
3348 | && rtx_equal_p (recog_operand[i], recog_operand[j])) | |
3349 | /* Is it altered by storing the earlyclobber operand? */ | |
3350 | && !immune_p (recog_operand[j], recog_operand[i], early_data)) | |
3351 | { | |
3352 | /* If the output is in a single-reg class, | |
3353 | it's costly to reload it, so reload the input instead. */ | |
3354 | if (reg_class_size[this_alternative[i]] == 1 | |
3355 | && (GET_CODE (recog_operand[j]) == REG | |
3356 | || GET_CODE (recog_operand[j]) == SUBREG)) | |
3357 | { | |
3358 | losers++; | |
3359 | this_alternative_win[j] = 0; | |
3360 | } | |
3361 | else | |
3362 | break; | |
3363 | } | |
3364 | /* If an earlyclobber operand conflicts with something, | |
3365 | it must be reloaded, so request this and count the cost. */ | |
3366 | if (j != noperands) | |
3367 | { | |
3368 | losers++; | |
3369 | this_alternative_win[i] = 0; | |
3370 | for (j = 0; j < noperands; j++) | |
3371 | if (this_alternative_matches[j] == i | |
3372 | && this_alternative_win[j]) | |
3373 | { | |
3374 | this_alternative_win[j] = 0; | |
3375 | losers++; | |
3376 | } | |
3377 | } | |
3378 | } | |
3379 | ||
3380 | /* If one alternative accepts all the operands, no reload required, | |
3381 | choose that alternative; don't consider the remaining ones. */ | |
3382 | if (losers == 0) | |
3383 | { | |
3384 | /* Unswap these so that they are never swapped at `finish'. */ | |
3385 | if (commutative >= 0) | |
3386 | { | |
3387 | recog_operand[commutative] = substed_operand[commutative]; | |
3388 | recog_operand[commutative + 1] | |
3389 | = substed_operand[commutative + 1]; | |
3390 | } | |
3391 | for (i = 0; i < noperands; i++) | |
3392 | { | |
3393 | goal_alternative_win[i] = 1; | |
3394 | goal_alternative[i] = this_alternative[i]; | |
3395 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; | |
3396 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3397 | goal_alternative_earlyclobber[i] | |
3398 | = this_alternative_earlyclobber[i]; | |
3399 | } | |
3400 | goal_alternative_number = this_alternative_number; | |
3401 | goal_alternative_swapped = swapped; | |
3402 | goal_earlyclobber = this_earlyclobber; | |
3403 | goto finish; | |
3404 | } | |
3405 | ||
3406 | /* REJECT, set by the ! and ? constraint characters and when a register | |
3407 | would be reloaded into a non-preferred class, discourages the use of | |
812f2051 R |
3408 | this alternative for a reload goal. REJECT is incremented by six |
3409 | for each ? and two for each non-preferred class. */ | |
3410 | losers = losers * 6 + reject; | |
eab89b90 RK |
3411 | |
3412 | /* If this alternative can be made to work by reloading, | |
3413 | and it needs less reloading than the others checked so far, | |
3414 | record it as the chosen goal for reloading. */ | |
3415 | if (! bad && best > losers) | |
3416 | { | |
3417 | for (i = 0; i < noperands; i++) | |
3418 | { | |
3419 | goal_alternative[i] = this_alternative[i]; | |
3420 | goal_alternative_win[i] = this_alternative_win[i]; | |
3421 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; | |
3422 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3423 | goal_alternative_earlyclobber[i] | |
3424 | = this_alternative_earlyclobber[i]; | |
3425 | } | |
3426 | goal_alternative_swapped = swapped; | |
3427 | best = losers; | |
3428 | goal_alternative_number = this_alternative_number; | |
3429 | goal_earlyclobber = this_earlyclobber; | |
3430 | } | |
3431 | } | |
3432 | ||
3433 | /* If insn is commutative (it's safe to exchange a certain pair of operands) | |
3434 | then we need to try each alternative twice, | |
3435 | the second time matching those two operands | |
3436 | as if we had exchanged them. | |
3437 | To do this, really exchange them in operands. | |
3438 | ||
3439 | If we have just tried the alternatives the second time, | |
3440 | return operands to normal and drop through. */ | |
3441 | ||
3442 | if (commutative >= 0) | |
3443 | { | |
3444 | swapped = !swapped; | |
3445 | if (swapped) | |
3446 | { | |
3447 | register enum reg_class tclass; | |
3448 | register int t; | |
3449 | ||
3450 | recog_operand[commutative] = substed_operand[commutative + 1]; | |
3451 | recog_operand[commutative + 1] = substed_operand[commutative]; | |
3452 | ||
3453 | tclass = preferred_class[commutative]; | |
3454 | preferred_class[commutative] = preferred_class[commutative + 1]; | |
3455 | preferred_class[commutative + 1] = tclass; | |
3456 | ||
3457 | t = pref_or_nothing[commutative]; | |
3458 | pref_or_nothing[commutative] = pref_or_nothing[commutative + 1]; | |
3459 | pref_or_nothing[commutative + 1] = t; | |
3460 | ||
4c9a05bc RK |
3461 | bcopy ((char *) constraints1, (char *) constraints, |
3462 | noperands * sizeof (char *)); | |
eab89b90 RK |
3463 | goto try_swapped; |
3464 | } | |
3465 | else | |
3466 | { | |
3467 | recog_operand[commutative] = substed_operand[commutative]; | |
3468 | recog_operand[commutative + 1] = substed_operand[commutative + 1]; | |
3469 | } | |
3470 | } | |
3471 | ||
3472 | /* The operands don't meet the constraints. | |
3473 | goal_alternative describes the alternative | |
3474 | that we could reach by reloading the fewest operands. | |
3475 | Reload so as to fit it. */ | |
3476 | ||
3477 | if (best == MAX_RECOG_OPERANDS + 300) | |
3478 | { | |
3479 | /* No alternative works with reloads?? */ | |
3480 | if (insn_code_number >= 0) | |
3481 | abort (); | |
3482 | error_for_asm (insn, "inconsistent operand constraints in an `asm'"); | |
3483 | /* Avoid further trouble with this insn. */ | |
38a448ca | 3484 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
eab89b90 RK |
3485 | n_reloads = 0; |
3486 | return; | |
3487 | } | |
3488 | ||
3489 | /* Jump to `finish' from above if all operands are valid already. | |
3490 | In that case, goal_alternative_win is all 1. */ | |
3491 | finish: | |
3492 | ||
3493 | /* Right now, for any pair of operands I and J that are required to match, | |
3494 | with I < J, | |
3495 | goal_alternative_matches[J] is I. | |
3496 | Set up goal_alternative_matched as the inverse function: | |
3497 | goal_alternative_matched[I] = J. */ | |
3498 | ||
3499 | for (i = 0; i < noperands; i++) | |
3500 | goal_alternative_matched[i] = -1; | |
3501 | ||
3502 | for (i = 0; i < noperands; i++) | |
3503 | if (! goal_alternative_win[i] | |
3504 | && goal_alternative_matches[i] >= 0) | |
3505 | goal_alternative_matched[goal_alternative_matches[i]] = i; | |
3506 | ||
3507 | /* If the best alternative is with operands 1 and 2 swapped, | |
a8c9daeb RK |
3508 | consider them swapped before reporting the reloads. Update the |
3509 | operand numbers of any reloads already pushed. */ | |
eab89b90 RK |
3510 | |
3511 | if (goal_alternative_swapped) | |
3512 | { | |
3513 | register rtx tem; | |
3514 | ||
3515 | tem = substed_operand[commutative]; | |
3516 | substed_operand[commutative] = substed_operand[commutative + 1]; | |
3517 | substed_operand[commutative + 1] = tem; | |
3518 | tem = recog_operand[commutative]; | |
3519 | recog_operand[commutative] = recog_operand[commutative + 1]; | |
3520 | recog_operand[commutative + 1] = tem; | |
a8c9daeb RK |
3521 | |
3522 | for (i = 0; i < n_reloads; i++) | |
3523 | { | |
3524 | if (reload_opnum[i] == commutative) | |
3525 | reload_opnum[i] = commutative + 1; | |
3526 | else if (reload_opnum[i] == commutative + 1) | |
3527 | reload_opnum[i] = commutative; | |
3528 | } | |
eab89b90 RK |
3529 | } |
3530 | ||
3531 | /* Perform whatever substitutions on the operands we are supposed | |
3532 | to make due to commutativity or replacement of registers | |
3533 | with equivalent constants or memory slots. */ | |
3534 | ||
3535 | for (i = 0; i < noperands; i++) | |
3536 | { | |
3537 | *recog_operand_loc[i] = substed_operand[i]; | |
3538 | /* While we are looping on operands, initialize this. */ | |
3539 | operand_reloadnum[i] = -1; | |
a8c9daeb RK |
3540 | |
3541 | /* If this is an earlyclobber operand, we need to widen the scope. | |
3542 | The reload must remain valid from the start of the insn being | |
3543 | reloaded until after the operand is stored into its destination. | |
3544 | We approximate this with RELOAD_OTHER even though we know that we | |
3545 | do not conflict with RELOAD_FOR_INPUT_ADDRESS reloads. | |
3546 | ||
3547 | One special case that is worth checking is when we have an | |
3548 | output that is earlyclobber but isn't used past the insn (typically | |
3549 | a SCRATCH). In this case, we only need have the reload live | |
3550 | through the insn itself, but not for any of our input or output | |
3551 | reloads. | |
3552 | ||
3553 | In any case, anything needed to address this operand can remain | |
3554 | however they were previously categorized. */ | |
3555 | ||
3556 | if (goal_alternative_earlyclobber[i]) | |
3557 | operand_type[i] | |
3558 | = (find_reg_note (insn, REG_UNUSED, recog_operand[i]) | |
3559 | ? RELOAD_FOR_INSN : RELOAD_OTHER); | |
eab89b90 RK |
3560 | } |
3561 | ||
3562 | /* Any constants that aren't allowed and can't be reloaded | |
3563 | into registers are here changed into memory references. */ | |
3564 | for (i = 0; i < noperands; i++) | |
3565 | if (! goal_alternative_win[i] | |
3566 | && CONSTANT_P (recog_operand[i]) | |
59f25cf9 RK |
3567 | /* force_const_mem does not accept HIGH. */ |
3568 | && GET_CODE (recog_operand[i]) != HIGH | |
e5e809f4 | 3569 | && ((PREFERRED_RELOAD_CLASS (recog_operand[i], |
eab89b90 | 3570 | (enum reg_class) goal_alternative[i]) |
e5e809f4 JL |
3571 | == NO_REGS) |
3572 | || no_input_reloads) | |
eab89b90 RK |
3573 | && operand_mode[i] != VOIDmode) |
3574 | { | |
3575 | *recog_operand_loc[i] = recog_operand[i] | |
3576 | = find_reloads_toplev (force_const_mem (operand_mode[i], | |
3577 | recog_operand[i]), | |
a8c9daeb | 3578 | i, address_type[i], ind_levels, 0); |
eab89b90 RK |
3579 | if (alternative_allows_memconst (constraints1[i], |
3580 | goal_alternative_number)) | |
3581 | goal_alternative_win[i] = 1; | |
3582 | } | |
3583 | ||
4644aad4 RK |
3584 | /* Record the values of the earlyclobber operands for the caller. */ |
3585 | if (goal_earlyclobber) | |
3586 | for (i = 0; i < noperands; i++) | |
3587 | if (goal_alternative_earlyclobber[i]) | |
3588 | reload_earlyclobbers[n_earlyclobbers++] = recog_operand[i]; | |
3589 | ||
eab89b90 RK |
3590 | /* Now record reloads for all the operands that need them. */ |
3591 | for (i = 0; i < noperands; i++) | |
3592 | if (! goal_alternative_win[i]) | |
3593 | { | |
3594 | /* Operands that match previous ones have already been handled. */ | |
3595 | if (goal_alternative_matches[i] >= 0) | |
3596 | ; | |
3597 | /* Handle an operand with a nonoffsettable address | |
3598 | appearing where an offsettable address will do | |
3a322c50 RK |
3599 | by reloading the address into a base register. |
3600 | ||
3601 | ??? We can also do this when the operand is a register and | |
3602 | reg_equiv_mem is not offsettable, but this is a bit tricky, | |
3603 | so we don't bother with it. It may not be worth doing. */ | |
eab89b90 RK |
3604 | else if (goal_alternative_matched[i] == -1 |
3605 | && goal_alternative_offmemok[i] | |
3606 | && GET_CODE (recog_operand[i]) == MEM) | |
3607 | { | |
3608 | operand_reloadnum[i] | |
fb3821f7 CH |
3609 | = push_reload (XEXP (recog_operand[i], 0), NULL_RTX, |
3610 | &XEXP (recog_operand[i], 0), NULL_PTR, | |
eab89b90 | 3611 | BASE_REG_CLASS, GET_MODE (XEXP (recog_operand[i], 0)), |
a8c9daeb | 3612 | VOIDmode, 0, 0, i, RELOAD_FOR_INPUT); |
eab89b90 RK |
3613 | reload_inc[operand_reloadnum[i]] |
3614 | = GET_MODE_SIZE (GET_MODE (recog_operand[i])); | |
a8c9daeb RK |
3615 | |
3616 | /* If this operand is an output, we will have made any | |
3617 | reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but | |
3618 | now we are treating part of the operand as an input, so | |
3619 | we must change these to RELOAD_FOR_INPUT_ADDRESS. */ | |
3620 | ||
2d55b7e8 | 3621 | if (modified[i] == RELOAD_WRITE) |
47c8cf91 ILT |
3622 | { |
3623 | for (j = 0; j < n_reloads; j++) | |
3624 | { | |
3625 | if (reload_opnum[j] == i) | |
3626 | { | |
3627 | if (reload_when_needed[j] == RELOAD_FOR_OUTPUT_ADDRESS) | |
3628 | reload_when_needed[j] = RELOAD_FOR_INPUT_ADDRESS; | |
3629 | else if (reload_when_needed[j] | |
3630 | == RELOAD_FOR_OUTADDR_ADDRESS) | |
3631 | reload_when_needed[j] = RELOAD_FOR_INPADDR_ADDRESS; | |
3632 | } | |
3633 | } | |
3634 | } | |
eab89b90 RK |
3635 | } |
3636 | else if (goal_alternative_matched[i] == -1) | |
db3cf6fb MS |
3637 | operand_reloadnum[i] |
3638 | = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0, | |
3639 | modified[i] != RELOAD_READ ? recog_operand[i] : 0, | |
3640 | (modified[i] != RELOAD_WRITE | |
3641 | ? recog_operand_loc[i] : 0), | |
3642 | modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0, | |
3643 | (enum reg_class) goal_alternative[i], | |
3644 | (modified[i] == RELOAD_WRITE | |
3645 | ? VOIDmode : operand_mode[i]), | |
3646 | (modified[i] == RELOAD_READ | |
3647 | ? VOIDmode : operand_mode[i]), | |
3648 | (insn_code_number < 0 ? 0 | |
3649 | : insn_operand_strict_low[insn_code_number][i]), | |
3650 | 0, i, operand_type[i]); | |
eab89b90 RK |
3651 | /* In a matching pair of operands, one must be input only |
3652 | and the other must be output only. | |
3653 | Pass the input operand as IN and the other as OUT. */ | |
3654 | else if (modified[i] == RELOAD_READ | |
3655 | && modified[goal_alternative_matched[i]] == RELOAD_WRITE) | |
3656 | { | |
3657 | operand_reloadnum[i] | |
3658 | = push_reload (recog_operand[i], | |
3659 | recog_operand[goal_alternative_matched[i]], | |
3660 | recog_operand_loc[i], | |
3661 | recog_operand_loc[goal_alternative_matched[i]], | |
3662 | (enum reg_class) goal_alternative[i], | |
3663 | operand_mode[i], | |
3664 | operand_mode[goal_alternative_matched[i]], | |
a8c9daeb | 3665 | 0, 0, i, RELOAD_OTHER); |
eab89b90 RK |
3666 | operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum; |
3667 | } | |
3668 | else if (modified[i] == RELOAD_WRITE | |
3669 | && modified[goal_alternative_matched[i]] == RELOAD_READ) | |
3670 | { | |
3671 | operand_reloadnum[goal_alternative_matched[i]] | |
3672 | = push_reload (recog_operand[goal_alternative_matched[i]], | |
3673 | recog_operand[i], | |
3674 | recog_operand_loc[goal_alternative_matched[i]], | |
3675 | recog_operand_loc[i], | |
3676 | (enum reg_class) goal_alternative[i], | |
3677 | operand_mode[goal_alternative_matched[i]], | |
3678 | operand_mode[i], | |
a8c9daeb | 3679 | 0, 0, i, RELOAD_OTHER); |
eab89b90 RK |
3680 | operand_reloadnum[i] = output_reloadnum; |
3681 | } | |
3682 | else if (insn_code_number >= 0) | |
3683 | abort (); | |
3684 | else | |
3685 | { | |
3686 | error_for_asm (insn, "inconsistent operand constraints in an `asm'"); | |
3687 | /* Avoid further trouble with this insn. */ | |
38a448ca | 3688 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
eab89b90 RK |
3689 | n_reloads = 0; |
3690 | return; | |
3691 | } | |
3692 | } | |
3693 | else if (goal_alternative_matched[i] < 0 | |
3694 | && goal_alternative_matches[i] < 0 | |
3695 | && optimize) | |
3696 | { | |
a8c9daeb | 3697 | /* For each non-matching operand that's a MEM or a pseudo-register |
eab89b90 RK |
3698 | that didn't get a hard register, make an optional reload. |
3699 | This may get done even if the insn needs no reloads otherwise. */ | |
a8c9daeb RK |
3700 | |
3701 | rtx operand = recog_operand[i]; | |
3702 | ||
eab89b90 RK |
3703 | while (GET_CODE (operand) == SUBREG) |
3704 | operand = XEXP (operand, 0); | |
a8c9daeb RK |
3705 | if ((GET_CODE (operand) == MEM |
3706 | || (GET_CODE (operand) == REG | |
3707 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) | |
eab89b90 | 3708 | && (enum reg_class) goal_alternative[i] != NO_REGS |
a8c9daeb RK |
3709 | && ! no_input_reloads |
3710 | /* Optional output reloads don't do anything and we mustn't | |
3711 | make in-out reloads on insns that are not permitted output | |
3712 | reloads. */ | |
eab89b90 | 3713 | && (modified[i] == RELOAD_READ |
a8c9daeb | 3714 | || (modified[i] == RELOAD_READ_WRITE && ! no_output_reloads))) |
eab89b90 RK |
3715 | operand_reloadnum[i] |
3716 | = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0, | |
3717 | modified[i] != RELOAD_READ ? recog_operand[i] : 0, | |
a8c9daeb RK |
3718 | (modified[i] != RELOAD_WRITE |
3719 | ? recog_operand_loc[i] : 0), | |
3720 | (modified[i] != RELOAD_READ | |
3721 | ? recog_operand_loc[i] : 0), | |
eab89b90 | 3722 | (enum reg_class) goal_alternative[i], |
a8c9daeb RK |
3723 | (modified[i] == RELOAD_WRITE |
3724 | ? VOIDmode : operand_mode[i]), | |
3725 | (modified[i] == RELOAD_READ | |
3726 | ? VOIDmode : operand_mode[i]), | |
eab89b90 RK |
3727 | (insn_code_number < 0 ? 0 |
3728 | : insn_operand_strict_low[insn_code_number][i]), | |
a8c9daeb | 3729 | 1, i, operand_type[i]); |
eab89b90 | 3730 | } |
a8c9daeb RK |
3731 | else if (goal_alternative_matches[i] >= 0 |
3732 | && goal_alternative_win[goal_alternative_matches[i]] | |
3733 | && modified[i] == RELOAD_READ | |
3734 | && modified[goal_alternative_matches[i]] == RELOAD_WRITE | |
3735 | && ! no_input_reloads && ! no_output_reloads | |
3736 | && optimize) | |
3737 | { | |
3738 | /* Similarly, make an optional reload for a pair of matching | |
3739 | objects that are in MEM or a pseudo that didn't get a hard reg. */ | |
eab89b90 | 3740 | |
a8c9daeb RK |
3741 | rtx operand = recog_operand[i]; |
3742 | ||
3743 | while (GET_CODE (operand) == SUBREG) | |
3744 | operand = XEXP (operand, 0); | |
3745 | if ((GET_CODE (operand) == MEM | |
3746 | || (GET_CODE (operand) == REG | |
3747 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) | |
3748 | && ((enum reg_class) goal_alternative[goal_alternative_matches[i]] | |
3749 | != NO_REGS)) | |
3750 | operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]] | |
3751 | = push_reload (recog_operand[goal_alternative_matches[i]], | |
3752 | recog_operand[i], | |
3753 | recog_operand_loc[goal_alternative_matches[i]], | |
3754 | recog_operand_loc[i], | |
3755 | (enum reg_class) goal_alternative[goal_alternative_matches[i]], | |
3756 | operand_mode[goal_alternative_matches[i]], | |
3757 | operand_mode[i], | |
3758 | 0, 1, goal_alternative_matches[i], RELOAD_OTHER); | |
3759 | } | |
3760 | ||
eab89b90 RK |
3761 | /* If this insn pattern contains any MATCH_DUP's, make sure that |
3762 | they will be substituted if the operands they match are substituted. | |
3763 | Also do now any substitutions we already did on the operands. | |
3764 | ||
3765 | Don't do this if we aren't making replacements because we might be | |
3766 | propagating things allocated by frame pointer elimination into places | |
3767 | it doesn't expect. */ | |
3768 | ||
3769 | if (insn_code_number >= 0 && replace) | |
3770 | for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) | |
3771 | { | |
3772 | int opno = recog_dup_num[i]; | |
3773 | *recog_dup_loc[i] = *recog_operand_loc[opno]; | |
3774 | if (operand_reloadnum[opno] >= 0) | |
3775 | push_replacement (recog_dup_loc[i], operand_reloadnum[opno], | |
3776 | insn_operand_mode[insn_code_number][opno]); | |
3777 | } | |
3778 | ||
3779 | #if 0 | |
3780 | /* This loses because reloading of prior insns can invalidate the equivalence | |
3781 | (or at least find_equiv_reg isn't smart enough to find it any more), | |
3782 | causing this insn to need more reload regs than it needed before. | |
3783 | It may be too late to make the reload regs available. | |
3784 | Now this optimization is done safely in choose_reload_regs. */ | |
3785 | ||
3786 | /* For each reload of a reg into some other class of reg, | |
3787 | search for an existing equivalent reg (same value now) in the right class. | |
3788 | We can use it as long as we don't need to change its contents. */ | |
3789 | for (i = 0; i < n_reloads; i++) | |
3790 | if (reload_reg_rtx[i] == 0 | |
3791 | && reload_in[i] != 0 | |
3792 | && GET_CODE (reload_in[i]) == REG | |
3793 | && reload_out[i] == 0) | |
3794 | { | |
3795 | reload_reg_rtx[i] | |
3796 | = find_equiv_reg (reload_in[i], insn, reload_reg_class[i], -1, | |
3797 | static_reload_reg_p, 0, reload_inmode[i]); | |
3798 | /* Prevent generation of insn to load the value | |
3799 | because the one we found already has the value. */ | |
3800 | if (reload_reg_rtx[i]) | |
3801 | reload_in[i] = reload_reg_rtx[i]; | |
3802 | } | |
3803 | #endif | |
3804 | ||
a8c9daeb RK |
3805 | /* Perhaps an output reload can be combined with another |
3806 | to reduce needs by one. */ | |
3807 | if (!goal_earlyclobber) | |
3808 | combine_reloads (); | |
3809 | ||
3810 | /* If we have a pair of reloads for parts of an address, they are reloading | |
3811 | the same object, the operands themselves were not reloaded, and they | |
3812 | are for two operands that are supposed to match, merge the reloads and | |
0f41302f | 3813 | change the type of the surviving reload to RELOAD_FOR_OPERAND_ADDRESS. */ |
a8c9daeb RK |
3814 | |
3815 | for (i = 0; i < n_reloads; i++) | |
3816 | { | |
3817 | int k; | |
3818 | ||
3819 | for (j = i + 1; j < n_reloads; j++) | |
3820 | if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS | |
47c8cf91 ILT |
3821 | || reload_when_needed[i] == RELOAD_FOR_OUTPUT_ADDRESS |
3822 | || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS | |
3823 | || reload_when_needed[i] == RELOAD_FOR_OUTADDR_ADDRESS) | |
a8c9daeb | 3824 | && (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS |
47c8cf91 ILT |
3825 | || reload_when_needed[j] == RELOAD_FOR_OUTPUT_ADDRESS |
3826 | || reload_when_needed[j] == RELOAD_FOR_INPADDR_ADDRESS | |
3827 | || reload_when_needed[j] == RELOAD_FOR_OUTADDR_ADDRESS) | |
a8c9daeb RK |
3828 | && rtx_equal_p (reload_in[i], reload_in[j]) |
3829 | && (operand_reloadnum[reload_opnum[i]] < 0 | |
3830 | || reload_optional[operand_reloadnum[reload_opnum[i]]]) | |
3831 | && (operand_reloadnum[reload_opnum[j]] < 0 | |
3832 | || reload_optional[operand_reloadnum[reload_opnum[j]]]) | |
3833 | && (goal_alternative_matches[reload_opnum[i]] == reload_opnum[j] | |
3834 | || (goal_alternative_matches[reload_opnum[j]] | |
3835 | == reload_opnum[i]))) | |
3836 | { | |
3837 | for (k = 0; k < n_replacements; k++) | |
3838 | if (replacements[k].what == j) | |
3839 | replacements[k].what = i; | |
3840 | ||
47c8cf91 ILT |
3841 | if (reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS |
3842 | || reload_when_needed[i] == RELOAD_FOR_OUTADDR_ADDRESS) | |
3843 | reload_when_needed[i] = RELOAD_FOR_OPADDR_ADDR; | |
3844 | else | |
3845 | reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS; | |
a8c9daeb RK |
3846 | reload_in[j] = 0; |
3847 | } | |
3848 | } | |
3849 | ||
3850 | /* Scan all the reloads and update their type. | |
3851 | If a reload is for the address of an operand and we didn't reload | |
3852 | that operand, change the type. Similarly, change the operand number | |
3853 | of a reload when two operands match. If a reload is optional, treat it | |
3854 | as though the operand isn't reloaded. | |
3855 | ||
3856 | ??? This latter case is somewhat odd because if we do the optional | |
3857 | reload, it means the object is hanging around. Thus we need only | |
3858 | do the address reload if the optional reload was NOT done. | |
3859 | ||
3860 | Change secondary reloads to be the address type of their operand, not | |
3861 | the normal type. | |
3862 | ||
3863 | If an operand's reload is now RELOAD_OTHER, change any | |
3864 | RELOAD_FOR_INPUT_ADDRESS reloads of that operand to | |
3865 | RELOAD_FOR_OTHER_ADDRESS. */ | |
3866 | ||
3867 | for (i = 0; i < n_reloads; i++) | |
3868 | { | |
3869 | if (reload_secondary_p[i] | |
3870 | && reload_when_needed[i] == operand_type[reload_opnum[i]]) | |
3871 | reload_when_needed[i] = address_type[reload_opnum[i]]; | |
3872 | ||
3873 | if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS | |
47c8cf91 ILT |
3874 | || reload_when_needed[i] == RELOAD_FOR_OUTPUT_ADDRESS |
3875 | || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS | |
3876 | || reload_when_needed[i] == RELOAD_FOR_OUTADDR_ADDRESS) | |
a8c9daeb | 3877 | && (operand_reloadnum[reload_opnum[i]] < 0 |
6ded3228 | 3878 | || reload_optional[operand_reloadnum[reload_opnum[i]]])) |
f98bb7d3 RK |
3879 | { |
3880 | /* If we have a secondary reload to go along with this reload, | |
0f41302f | 3881 | change its type to RELOAD_FOR_OPADDR_ADDR. */ |
f98bb7d3 | 3882 | |
47c8cf91 ILT |
3883 | if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS |
3884 | || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS) | |
f98bb7d3 RK |
3885 | && reload_secondary_in_reload[i] != -1) |
3886 | { | |
3887 | int secondary_in_reload = reload_secondary_in_reload[i]; | |
3888 | ||
db3cf6fb MS |
3889 | reload_when_needed[secondary_in_reload] |
3890 | = RELOAD_FOR_OPADDR_ADDR; | |
f98bb7d3 | 3891 | |
0f41302f | 3892 | /* If there's a tertiary reload we have to change it also. */ |
f98bb7d3 RK |
3893 | if (secondary_in_reload > 0 |
3894 | && reload_secondary_in_reload[secondary_in_reload] != -1) | |
3895 | reload_when_needed[reload_secondary_in_reload[secondary_in_reload]] | |
3896 | = RELOAD_FOR_OPADDR_ADDR; | |
3897 | } | |
3898 | ||
47c8cf91 ILT |
3899 | if ((reload_when_needed[i] == RELOAD_FOR_OUTPUT_ADDRESS |
3900 | || reload_when_needed[i] == RELOAD_FOR_OUTADDR_ADDRESS) | |
f98bb7d3 RK |
3901 | && reload_secondary_out_reload[i] != -1) |
3902 | { | |
3903 | int secondary_out_reload = reload_secondary_out_reload[i]; | |
3904 | ||
db3cf6fb MS |
3905 | reload_when_needed[secondary_out_reload] |
3906 | = RELOAD_FOR_OPADDR_ADDR; | |
f98bb7d3 | 3907 | |
0f41302f | 3908 | /* If there's a tertiary reload we have to change it also. */ |
f98bb7d3 RK |
3909 | if (secondary_out_reload |
3910 | && reload_secondary_out_reload[secondary_out_reload] != -1) | |
3911 | reload_when_needed[reload_secondary_out_reload[secondary_out_reload]] | |
3912 | = RELOAD_FOR_OPADDR_ADDR; | |
3913 | } | |
e5e809f4 JL |
3914 | |
3915 | reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS; | |
f98bb7d3 | 3916 | } |
a8c9daeb | 3917 | |
47c8cf91 ILT |
3918 | if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS |
3919 | || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS) | |
a8c9daeb RK |
3920 | && operand_reloadnum[reload_opnum[i]] >= 0 |
3921 | && (reload_when_needed[operand_reloadnum[reload_opnum[i]]] | |
3922 | == RELOAD_OTHER)) | |
3923 | reload_when_needed[i] = RELOAD_FOR_OTHER_ADDRESS; | |
3924 | ||
3925 | if (goal_alternative_matches[reload_opnum[i]] >= 0) | |
3926 | reload_opnum[i] = goal_alternative_matches[reload_opnum[i]]; | |
3927 | } | |
3928 | ||
a94ce333 JW |
3929 | /* Scan all the reloads, and check for RELOAD_FOR_OPERAND_ADDRESS reloads. |
3930 | If we have more than one, then convert all RELOAD_FOR_OPADDR_ADDR | |
3931 | reloads to RELOAD_FOR_OPERAND_ADDRESS reloads. | |
3932 | ||
3933 | choose_reload_regs assumes that RELOAD_FOR_OPADDR_ADDR reloads never | |
3934 | conflict with RELOAD_FOR_OPERAND_ADDRESS reloads. This is true for a | |
3935 | single pair of RELOAD_FOR_OPADDR_ADDR/RELOAD_FOR_OPERAND_ADDRESS reloads. | |
3936 | However, if there is more than one RELOAD_FOR_OPERAND_ADDRESS reload, | |
3937 | then a RELOAD_FOR_OPADDR_ADDR reload conflicts with all | |
3938 | RELOAD_FOR_OPERAND_ADDRESS reloads other than the one that uses it. | |
3939 | This is complicated by the fact that a single operand can have more | |
3940 | than one RELOAD_FOR_OPERAND_ADDRESS reload. It is very difficult to fix | |
3941 | choose_reload_regs without affecting code quality, and cases that | |
3942 | actually fail are extremely rare, so it turns out to be better to fix | |
3943 | the problem here by not generating cases that choose_reload_regs will | |
3944 | fail for. */ | |
3945 | ||
3946 | { | |
3947 | int op_addr_reloads = 0; | |
3948 | for (i = 0; i < n_reloads; i++) | |
3949 | if (reload_when_needed[i] == RELOAD_FOR_OPERAND_ADDRESS) | |
3950 | op_addr_reloads++; | |
3951 | ||
3952 | if (op_addr_reloads > 1) | |
3953 | for (i = 0; i < n_reloads; i++) | |
3954 | if (reload_when_needed[i] == RELOAD_FOR_OPADDR_ADDR) | |
3955 | reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS; | |
3956 | } | |
3957 | ||
a8c9daeb RK |
3958 | /* See if we have any reloads that are now allowed to be merged |
3959 | because we've changed when the reload is needed to | |
3960 | RELOAD_FOR_OPERAND_ADDRESS or RELOAD_FOR_OTHER_ADDRESS. Only | |
3961 | check for the most common cases. */ | |
3962 | ||
3963 | for (i = 0; i < n_reloads; i++) | |
3964 | if (reload_in[i] != 0 && reload_out[i] == 0 | |
3965 | && (reload_when_needed[i] == RELOAD_FOR_OPERAND_ADDRESS | |
47c8cf91 | 3966 | || reload_when_needed[i] == RELOAD_FOR_OPADDR_ADDR |
a8c9daeb RK |
3967 | || reload_when_needed[i] == RELOAD_FOR_OTHER_ADDRESS)) |
3968 | for (j = 0; j < n_reloads; j++) | |
3969 | if (i != j && reload_in[j] != 0 && reload_out[j] == 0 | |
3970 | && reload_when_needed[j] == reload_when_needed[i] | |
73f67895 RS |
3971 | && MATCHES (reload_in[i], reload_in[j]) |
3972 | && reload_reg_class[i] == reload_reg_class[j] | |
92b37691 RK |
3973 | && !reload_nocombine[i] && !reload_nocombine[j] |
3974 | && reload_reg_rtx[i] == reload_reg_rtx[j]) | |
a8c9daeb RK |
3975 | { |
3976 | reload_opnum[i] = MIN (reload_opnum[i], reload_opnum[j]); | |
3977 | transfer_replacements (i, j); | |
3978 | reload_in[j] = 0; | |
3979 | } | |
3980 | ||
f5963e61 JL |
3981 | /* Set which reloads must use registers not used in any group. Start |
3982 | with those that conflict with a group and then include ones that | |
3983 | conflict with ones that are already known to conflict with a group. */ | |
3984 | ||
3985 | changed = 0; | |
3986 | for (i = 0; i < n_reloads; i++) | |
3987 | { | |
3988 | enum machine_mode mode = reload_inmode[i]; | |
3989 | enum reg_class class = reload_reg_class[i]; | |
3990 | int size; | |
3991 | ||
3992 | if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode)) | |
3993 | mode = reload_outmode[i]; | |
3994 | size = CLASS_MAX_NREGS (class, mode); | |
3995 | ||
3996 | if (size == 1) | |
3997 | for (j = 0; j < n_reloads; j++) | |
3998 | if ((CLASS_MAX_NREGS (reload_reg_class[j], | |
3999 | (GET_MODE_SIZE (reload_outmode[j]) | |
4000 | > GET_MODE_SIZE (reload_inmode[j])) | |
4001 | ? reload_outmode[j] : reload_inmode[j]) | |
4002 | > 1) | |
4003 | && !reload_optional[j] | |
4004 | && (reload_in[j] != 0 || reload_out[j] != 0 | |
4005 | || reload_secondary_p[j]) | |
4006 | && reloads_conflict (i, j) | |
4007 | && reg_classes_intersect_p (class, reload_reg_class[j])) | |
4008 | { | |
4009 | reload_nongroup[i] = 1; | |
4010 | changed = 1; | |
4011 | break; | |
4012 | } | |
4013 | } | |
4014 | ||
4015 | while (changed) | |
4016 | { | |
4017 | changed = 0; | |
4018 | ||
4019 | for (i = 0; i < n_reloads; i++) | |
4020 | { | |
4021 | enum machine_mode mode = reload_inmode[i]; | |
4022 | enum reg_class class = reload_reg_class[i]; | |
4023 | int size; | |
4024 | ||
4025 | if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode)) | |
4026 | mode = reload_outmode[i]; | |
4027 | size = CLASS_MAX_NREGS (class, mode); | |
4028 | ||
4029 | if (! reload_nongroup[i] && size == 1) | |
4030 | for (j = 0; j < n_reloads; j++) | |
4031 | if (reload_nongroup[j] | |
4032 | && reloads_conflict (i, j) | |
4033 | && reg_classes_intersect_p (class, reload_reg_class[j])) | |
4034 | { | |
4035 | reload_nongroup[i] = 1; | |
4036 | changed = 1; | |
4037 | break; | |
4038 | } | |
4039 | } | |
4040 | } | |
4041 | ||
eab89b90 RK |
4042 | #else /* no REGISTER_CONSTRAINTS */ |
4043 | int noperands; | |
4044 | int insn_code_number; | |
4045 | int goal_earlyclobber = 0; /* Always 0, to make combine_reloads happen. */ | |
4046 | register int i; | |
4047 | rtx body = PATTERN (insn); | |
4048 | ||
4049 | n_reloads = 0; | |
4050 | n_replacements = 0; | |
4051 | n_earlyclobbers = 0; | |
4052 | replace_reloads = replace; | |
4053 | this_insn = insn; | |
4054 | ||
4055 | /* Find what kind of insn this is. NOPERANDS gets number of operands. | |
4056 | Store the operand values in RECOG_OPERAND and the locations | |
4057 | of the words in the insn that point to them in RECOG_OPERAND_LOC. | |
4058 | Return if the insn needs no reload processing. */ | |
4059 | ||
4060 | switch (GET_CODE (body)) | |
4061 | { | |
4062 | case USE: | |
4063 | case CLOBBER: | |
4064 | case ASM_INPUT: | |
4065 | case ADDR_VEC: | |
4066 | case ADDR_DIFF_VEC: | |
4067 | return; | |
4068 | ||
4069 | case PARALLEL: | |
4070 | case SET: | |
4071 | noperands = asm_noperands (body); | |
4072 | if (noperands >= 0) | |
4073 | { | |
4074 | /* This insn is an `asm' with operands. | |
4075 | First, find out how many operands, and allocate space. */ | |
4076 | ||
4077 | insn_code_number = -1; | |
4078 | /* ??? This is a bug! ??? | |
4079 | Give up and delete this insn if it has too many operands. */ | |
4080 | if (noperands > MAX_RECOG_OPERANDS) | |
4081 | abort (); | |
4082 | ||
4083 | /* Now get the operand values out of the insn. */ | |
4084 | ||
fb3821f7 CH |
4085 | decode_asm_operands (body, recog_operand, recog_operand_loc, |
4086 | NULL_PTR, NULL_PTR); | |
eab89b90 RK |
4087 | break; |
4088 | } | |
4089 | ||
4090 | default: | |
4091 | /* Ordinary insn: recognize it, allocate space for operands and | |
4092 | constraints, and get them out via insn_extract. */ | |
4093 | ||
4094 | insn_code_number = recog_memoized (insn); | |
4095 | noperands = insn_n_operands[insn_code_number]; | |
4096 | insn_extract (insn); | |
4097 | } | |
4098 | ||
4099 | if (noperands == 0) | |
4100 | return; | |
4101 | ||
4102 | for (i = 0; i < noperands; i++) | |
4103 | { | |
4104 | register RTX_CODE code = GET_CODE (recog_operand[i]); | |
4105 | int is_set_dest = GET_CODE (body) == SET && (i == 0); | |
4106 | ||
4107 | if (insn_code_number >= 0) | |
4108 | if (insn_operand_address_p[insn_code_number][i]) | |
fb3821f7 | 4109 | find_reloads_address (VOIDmode, NULL_PTR, |
eab89b90 | 4110 | recog_operand[i], recog_operand_loc[i], |
55c22565 | 4111 | i, RELOAD_FOR_INPUT, ind_levels, insn); |
a8c9daeb RK |
4112 | |
4113 | /* In these cases, we can't tell if the operand is an input | |
4114 | or an output, so be conservative. In practice it won't be | |
4115 | problem. */ | |
4116 | ||
eab89b90 RK |
4117 | if (code == MEM) |
4118 | find_reloads_address (GET_MODE (recog_operand[i]), | |
4119 | recog_operand_loc[i], | |
4120 | XEXP (recog_operand[i], 0), | |
4121 | &XEXP (recog_operand[i], 0), | |
55c22565 | 4122 | i, RELOAD_OTHER, ind_levels, insn); |
eab89b90 RK |
4123 | if (code == SUBREG) |
4124 | recog_operand[i] = *recog_operand_loc[i] | |
a8c9daeb RK |
4125 | = find_reloads_toplev (recog_operand[i], i, RELOAD_OTHER, |
4126 | ind_levels, is_set_dest); | |
eab89b90 RK |
4127 | if (code == REG) |
4128 | { | |
4129 | register int regno = REGNO (recog_operand[i]); | |
4130 | if (reg_equiv_constant[regno] != 0 && !is_set_dest) | |
4131 | recog_operand[i] = *recog_operand_loc[i] | |
4132 | = reg_equiv_constant[regno]; | |
4133 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
4134 | that feeds this insn. */ | |
4135 | if (reg_equiv_mem[regno] != 0) | |
4136 | recog_operand[i] = *recog_operand_loc[i] | |
4137 | = reg_equiv_mem[regno]; | |
4138 | #endif | |
4139 | } | |
eab89b90 RK |
4140 | } |
4141 | ||
4142 | /* Perhaps an output reload can be combined with another | |
4143 | to reduce needs by one. */ | |
4144 | if (!goal_earlyclobber) | |
4145 | combine_reloads (); | |
a8c9daeb | 4146 | #endif /* no REGISTER_CONSTRAINTS */ |
eab89b90 RK |
4147 | } |
4148 | ||
4149 | /* Return 1 if alternative number ALTNUM in constraint-string CONSTRAINT | |
4150 | accepts a memory operand with constant address. */ | |
4151 | ||
4152 | static int | |
4153 | alternative_allows_memconst (constraint, altnum) | |
4154 | char *constraint; | |
4155 | int altnum; | |
4156 | { | |
4157 | register int c; | |
4158 | /* Skip alternatives before the one requested. */ | |
4159 | while (altnum > 0) | |
4160 | { | |
4161 | while (*constraint++ != ','); | |
4162 | altnum--; | |
4163 | } | |
4164 | /* Scan the requested alternative for 'm' or 'o'. | |
4165 | If one of them is present, this alternative accepts memory constants. */ | |
4166 | while ((c = *constraint++) && c != ',' && c != '#') | |
4167 | if (c == 'm' || c == 'o') | |
4168 | return 1; | |
4169 | return 0; | |
4170 | } | |
4171 | \f | |
4172 | /* Scan X for memory references and scan the addresses for reloading. | |
4173 | Also checks for references to "constant" regs that we want to eliminate | |
4174 | and replaces them with the values they stand for. | |
6dc42e49 | 4175 | We may alter X destructively if it contains a reference to such. |
eab89b90 RK |
4176 | If X is just a constant reg, we return the equivalent value |
4177 | instead of X. | |
4178 | ||
4179 | IND_LEVELS says how many levels of indirect addressing this machine | |
4180 | supports. | |
4181 | ||
a8c9daeb RK |
4182 | OPNUM and TYPE identify the purpose of the reload. |
4183 | ||
eab89b90 RK |
4184 | IS_SET_DEST is true if X is the destination of a SET, which is not |
4185 | appropriate to be replaced by a constant. */ | |
4186 | ||
4187 | static rtx | |
a8c9daeb | 4188 | find_reloads_toplev (x, opnum, type, ind_levels, is_set_dest) |
eab89b90 | 4189 | rtx x; |
a8c9daeb RK |
4190 | int opnum; |
4191 | enum reload_type type; | |
eab89b90 RK |
4192 | int ind_levels; |
4193 | int is_set_dest; | |
4194 | { | |
4195 | register RTX_CODE code = GET_CODE (x); | |
4196 | ||
4197 | register char *fmt = GET_RTX_FORMAT (code); | |
4198 | register int i; | |
4199 | ||
4200 | if (code == REG) | |
4201 | { | |
4202 | /* This code is duplicated for speed in find_reloads. */ | |
4203 | register int regno = REGNO (x); | |
4204 | if (reg_equiv_constant[regno] != 0 && !is_set_dest) | |
4205 | x = reg_equiv_constant[regno]; | |
4206 | #if 0 | |
4207 | /* This creates (subreg (mem...)) which would cause an unnecessary | |
4208 | reload of the mem. */ | |
4209 | else if (reg_equiv_mem[regno] != 0) | |
4210 | x = reg_equiv_mem[regno]; | |
4211 | #endif | |
4212 | else if (reg_equiv_address[regno] != 0) | |
4213 | { | |
4214 | /* If reg_equiv_address varies, it may be shared, so copy it. */ | |
4ffeab02 JW |
4215 | /* We must rerun eliminate_regs, in case the elimination |
4216 | offsets have changed. */ | |
4217 | rtx addr = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], 0, | |
1914f5da | 4218 | NULL_RTX), |
4ffeab02 | 4219 | 0); |
eab89b90 RK |
4220 | |
4221 | if (rtx_varies_p (addr)) | |
4222 | addr = copy_rtx (addr); | |
4223 | ||
38a448ca | 4224 | x = gen_rtx_MEM (GET_MODE (x), addr); |
eab89b90 | 4225 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); |
fb3821f7 | 4226 | find_reloads_address (GET_MODE (x), NULL_PTR, |
eab89b90 | 4227 | XEXP (x, 0), |
55c22565 | 4228 | &XEXP (x, 0), opnum, type, ind_levels, 0); |
eab89b90 RK |
4229 | } |
4230 | return x; | |
4231 | } | |
4232 | if (code == MEM) | |
4233 | { | |
4234 | rtx tem = x; | |
4235 | find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0), | |
55c22565 | 4236 | opnum, type, ind_levels, 0); |
eab89b90 RK |
4237 | return tem; |
4238 | } | |
4239 | ||
4240 | if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG) | |
4241 | { | |
4242 | /* Check for SUBREG containing a REG that's equivalent to a constant. | |
4243 | If the constant has a known value, truncate it right now. | |
4244 | Similarly if we are extracting a single-word of a multi-word | |
4245 | constant. If the constant is symbolic, allow it to be substituted | |
4246 | normally. push_reload will strip the subreg later. If the | |
4247 | constant is VOIDmode, abort because we will lose the mode of | |
4248 | the register (this should never happen because one of the cases | |
4249 | above should handle it). */ | |
4250 | ||
4251 | register int regno = REGNO (SUBREG_REG (x)); | |
4252 | rtx tem; | |
4253 | ||
4254 | if (subreg_lowpart_p (x) | |
4255 | && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
4256 | && reg_equiv_constant[regno] != 0 | |
4257 | && (tem = gen_lowpart_common (GET_MODE (x), | |
4258 | reg_equiv_constant[regno])) != 0) | |
4259 | return tem; | |
4260 | ||
4261 | if (GET_MODE_BITSIZE (GET_MODE (x)) == BITS_PER_WORD | |
4262 | && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
4263 | && reg_equiv_constant[regno] != 0 | |
4264 | && (tem = operand_subword (reg_equiv_constant[regno], | |
4265 | SUBREG_WORD (x), 0, | |
4266 | GET_MODE (SUBREG_REG (x)))) != 0) | |
4267 | return tem; | |
4268 | ||
2fd0af53 R |
4269 | /* If the SUBREG is wider than a word, the above test will fail. |
4270 | For example, we might have a SImode SUBREG of a DImode SUBREG_REG | |
4271 | for a 16 bit target, or a DImode SUBREG of a TImode SUBREG_REG for | |
4272 | a 32 bit target. We still can - and have to - handle this | |
4273 | for non-paradoxical subregs of CONST_INTs. */ | |
4274 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
4275 | && reg_equiv_constant[regno] != 0 | |
4276 | && GET_CODE (reg_equiv_constant[regno]) == CONST_INT | |
4277 | && (GET_MODE_SIZE (GET_MODE (x)) | |
4278 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
4279 | { | |
4280 | int shift = SUBREG_WORD (x) * BITS_PER_WORD; | |
4281 | if (WORDS_BIG_ENDIAN) | |
4282 | shift = (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) | |
4283 | - GET_MODE_BITSIZE (GET_MODE (x)) | |
4284 | - shift); | |
4285 | /* Here we use the knowledge that CONST_INTs have a | |
4286 | HOST_WIDE_INT field. */ | |
4287 | if (shift >= HOST_BITS_PER_WIDE_INT) | |
4288 | shift = HOST_BITS_PER_WIDE_INT - 1; | |
4289 | return GEN_INT (INTVAL (reg_equiv_constant[regno]) >> shift); | |
4290 | } | |
4291 | ||
eab89b90 RK |
4292 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 |
4293 | && reg_equiv_constant[regno] != 0 | |
4294 | && GET_MODE (reg_equiv_constant[regno]) == VOIDmode) | |
4295 | abort (); | |
4296 | ||
4297 | /* If the subreg contains a reg that will be converted to a mem, | |
4298 | convert the subreg to a narrower memref now. | |
4299 | Otherwise, we would get (subreg (mem ...) ...), | |
4300 | which would force reload of the mem. | |
4301 | ||
4302 | We also need to do this if there is an equivalent MEM that is | |
4303 | not offsettable. In that case, alter_subreg would produce an | |
4304 | invalid address on big-endian machines. | |
4305 | ||
46da6b3a | 4306 | For machines that extend byte loads, we must not reload using |
eab89b90 RK |
4307 | a wider mode if we have a paradoxical SUBREG. find_reloads will |
4308 | force a reload in that case. So we should not do anything here. */ | |
4309 | ||
4310 | else if (regno >= FIRST_PSEUDO_REGISTER | |
fd72420f | 4311 | #ifdef LOAD_EXTEND_OP |
eab89b90 RK |
4312 | && (GET_MODE_SIZE (GET_MODE (x)) |
4313 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
4314 | #endif | |
4315 | && (reg_equiv_address[regno] != 0 | |
4316 | || (reg_equiv_mem[regno] != 0 | |
f2fbfe92 JL |
4317 | && (! strict_memory_address_p (GET_MODE (x), |
4318 | XEXP (reg_equiv_mem[regno], 0)) | |
4319 | || ! offsettable_memref_p (reg_equiv_mem[regno]))))) | |
eab89b90 RK |
4320 | { |
4321 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
4ffeab02 JW |
4322 | /* We must rerun eliminate_regs, in case the elimination |
4323 | offsets have changed. */ | |
4324 | rtx addr = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], 0, | |
1914f5da | 4325 | NULL_RTX), |
4ffeab02 | 4326 | 0); |
f76b9db2 ILT |
4327 | if (BYTES_BIG_ENDIAN) |
4328 | { | |
4329 | int size; | |
4330 | size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))); | |
4331 | offset += MIN (size, UNITS_PER_WORD); | |
4332 | size = GET_MODE_SIZE (GET_MODE (x)); | |
4333 | offset -= MIN (size, UNITS_PER_WORD); | |
4334 | } | |
eab89b90 | 4335 | addr = plus_constant (addr, offset); |
38a448ca | 4336 | x = gen_rtx_MEM (GET_MODE (x), addr); |
eab89b90 | 4337 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); |
fb3821f7 | 4338 | find_reloads_address (GET_MODE (x), NULL_PTR, |
eab89b90 | 4339 | XEXP (x, 0), |
55c22565 | 4340 | &XEXP (x, 0), opnum, type, ind_levels, 0); |
eab89b90 RK |
4341 | } |
4342 | ||
4343 | } | |
4344 | ||
4345 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4346 | { | |
4347 | if (fmt[i] == 'e') | |
a8c9daeb | 4348 | XEXP (x, i) = find_reloads_toplev (XEXP (x, i), opnum, type, |
eab89b90 RK |
4349 | ind_levels, is_set_dest); |
4350 | } | |
4351 | return x; | |
4352 | } | |
4353 | ||
dbf85761 RS |
4354 | /* Return a mem ref for the memory equivalent of reg REGNO. |
4355 | This mem ref is not shared with anything. */ | |
4356 | ||
eab89b90 RK |
4357 | static rtx |
4358 | make_memloc (ad, regno) | |
4359 | rtx ad; | |
4360 | int regno; | |
4361 | { | |
29a82058 | 4362 | #if 0 |
eab89b90 | 4363 | register int i; |
29a82058 | 4364 | #endif |
4ffeab02 JW |
4365 | /* We must rerun eliminate_regs, in case the elimination |
4366 | offsets have changed. */ | |
1914f5da | 4367 | rtx tem = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], 0, NULL_RTX), 0); |
dbf85761 RS |
4368 | |
4369 | #if 0 /* We cannot safely reuse a memloc made here; | |
4370 | if the pseudo appears twice, and its mem needs a reload, | |
4371 | it gets two separate reloads assigned, but it only | |
4372 | gets substituted with the second of them; | |
4373 | then it can get used before that reload reg gets loaded up. */ | |
eab89b90 RK |
4374 | for (i = 0; i < n_memlocs; i++) |
4375 | if (rtx_equal_p (tem, XEXP (memlocs[i], 0))) | |
4376 | return memlocs[i]; | |
dbf85761 | 4377 | #endif |
eab89b90 RK |
4378 | |
4379 | /* If TEM might contain a pseudo, we must copy it to avoid | |
4380 | modifying it when we do the substitution for the reload. */ | |
4381 | if (rtx_varies_p (tem)) | |
4382 | tem = copy_rtx (tem); | |
4383 | ||
38a448ca | 4384 | tem = gen_rtx_MEM (GET_MODE (ad), tem); |
eab89b90 RK |
4385 | RTX_UNCHANGING_P (tem) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); |
4386 | memlocs[n_memlocs++] = tem; | |
4387 | return tem; | |
4388 | } | |
4389 | ||
4390 | /* Record all reloads needed for handling memory address AD | |
4391 | which appears in *LOC in a memory reference to mode MODE | |
4392 | which itself is found in location *MEMREFLOC. | |
4393 | Note that we take shortcuts assuming that no multi-reg machine mode | |
4394 | occurs as part of an address. | |
4395 | ||
a8c9daeb | 4396 | OPNUM and TYPE specify the purpose of this reload. |
eab89b90 RK |
4397 | |
4398 | IND_LEVELS says how many levels of indirect addressing this machine | |
4399 | supports. | |
4400 | ||
55c22565 RK |
4401 | INSN, if nonzero, is the insn in which we do the reload. It is used |
4402 | to determine if we may generate output reloads. | |
4403 | ||
eab89b90 RK |
4404 | Value is nonzero if this address is reloaded or replaced as a whole. |
4405 | This is interesting to the caller if the address is an autoincrement. | |
4406 | ||
4407 | Note that there is no verification that the address will be valid after | |
4408 | this routine does its work. Instead, we rely on the fact that the address | |
4409 | was valid when reload started. So we need only undo things that reload | |
4410 | could have broken. These are wrong register types, pseudos not allocated | |
4411 | to a hard register, and frame pointer elimination. */ | |
4412 | ||
4413 | static int | |
55c22565 | 4414 | find_reloads_address (mode, memrefloc, ad, loc, opnum, type, ind_levels, insn) |
eab89b90 RK |
4415 | enum machine_mode mode; |
4416 | rtx *memrefloc; | |
4417 | rtx ad; | |
4418 | rtx *loc; | |
a8c9daeb RK |
4419 | int opnum; |
4420 | enum reload_type type; | |
eab89b90 | 4421 | int ind_levels; |
55c22565 | 4422 | rtx insn; |
eab89b90 RK |
4423 | { |
4424 | register int regno; | |
4425 | rtx tem; | |
4426 | ||
4427 | /* If the address is a register, see if it is a legitimate address and | |
4428 | reload if not. We first handle the cases where we need not reload | |
4429 | or where we must reload in a non-standard way. */ | |
4430 | ||
4431 | if (GET_CODE (ad) == REG) | |
4432 | { | |
4433 | regno = REGNO (ad); | |
4434 | ||
4435 | if (reg_equiv_constant[regno] != 0 | |
4436 | && strict_memory_address_p (mode, reg_equiv_constant[regno])) | |
4437 | { | |
4438 | *loc = ad = reg_equiv_constant[regno]; | |
4439 | return 1; | |
4440 | } | |
4441 | ||
4442 | else if (reg_equiv_address[regno] != 0) | |
4443 | { | |
4444 | tem = make_memloc (ad, regno); | |
fb3821f7 | 4445 | find_reloads_address (GET_MODE (tem), NULL_PTR, XEXP (tem, 0), |
47c8cf91 | 4446 | &XEXP (tem, 0), opnum, ADDR_TYPE (type), |
55c22565 | 4447 | ind_levels, insn); |
1ba61f4e ILT |
4448 | push_reload (tem, NULL_RTX, loc, NULL_PTR, |
4449 | reload_address_base_reg_class, | |
eab89b90 | 4450 | GET_MODE (ad), VOIDmode, 0, 0, |
a8c9daeb | 4451 | opnum, type); |
eab89b90 RK |
4452 | return 1; |
4453 | } | |
4454 | ||
b39555b4 | 4455 | /* We can avoid a reload if the register's equivalent memory expression |
c1875d66 RS |
4456 | is valid as an indirect memory address. |
4457 | But not all addresses are valid in a mem used as an indirect address: | |
4458 | only reg or reg+constant. */ | |
b39555b4 RS |
4459 | |
4460 | else if (reg_equiv_mem[regno] != 0 && ind_levels > 0 | |
c1875d66 RS |
4461 | && strict_memory_address_p (mode, reg_equiv_mem[regno]) |
4462 | && (GET_CODE (XEXP (reg_equiv_mem[regno], 0)) == REG | |
4463 | || (GET_CODE (XEXP (reg_equiv_mem[regno], 0)) == PLUS | |
4464 | && GET_CODE (XEXP (XEXP (reg_equiv_mem[regno], 0), 0)) == REG | |
75301d68 | 4465 | && CONSTANT_P (XEXP (XEXP (reg_equiv_mem[regno], 0), 1))))) |
b39555b4 | 4466 | return 0; |
eab89b90 RK |
4467 | |
4468 | /* The only remaining case where we can avoid a reload is if this is a | |
4469 | hard register that is valid as a base register and which is not the | |
4470 | subject of a CLOBBER in this insn. */ | |
4471 | ||
858c3c8c ILT |
4472 | else if (regno < FIRST_PSEUDO_REGISTER |
4473 | && REGNO_MODE_OK_FOR_BASE_P (regno, mode) | |
eab89b90 RK |
4474 | && ! regno_clobbered_p (regno, this_insn)) |
4475 | return 0; | |
4476 | ||
4477 | /* If we do not have one of the cases above, we must do the reload. */ | |
1ba61f4e | 4478 | push_reload (ad, NULL_RTX, loc, NULL_PTR, reload_address_base_reg_class, |
a8c9daeb | 4479 | GET_MODE (ad), VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
4480 | return 1; |
4481 | } | |
4482 | ||
4483 | if (strict_memory_address_p (mode, ad)) | |
4484 | { | |
4485 | /* The address appears valid, so reloads are not needed. | |
4486 | But the address may contain an eliminable register. | |
4487 | This can happen because a machine with indirect addressing | |
4488 | may consider a pseudo register by itself a valid address even when | |
4489 | it has failed to get a hard reg. | |
4490 | So do a tree-walk to find and eliminate all such regs. */ | |
4491 | ||
4492 | /* But first quickly dispose of a common case. */ | |
4493 | if (GET_CODE (ad) == PLUS | |
4494 | && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
4495 | && GET_CODE (XEXP (ad, 0)) == REG | |
4496 | && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0) | |
4497 | return 0; | |
4498 | ||
4499 | subst_reg_equivs_changed = 0; | |
4500 | *loc = subst_reg_equivs (ad); | |
4501 | ||
4502 | if (! subst_reg_equivs_changed) | |
4503 | return 0; | |
4504 | ||
4505 | /* Check result for validity after substitution. */ | |
4506 | if (strict_memory_address_p (mode, ad)) | |
4507 | return 0; | |
4508 | } | |
4509 | ||
a9a2595b JR |
4510 | #ifdef LEGITIMIZE_RELOAD_ADDRESS |
4511 | do | |
4512 | { | |
4513 | if (memrefloc) | |
4514 | { | |
4515 | LEGITIMIZE_RELOAD_ADDRESS (ad, GET_MODE (*memrefloc), opnum, type, | |
4516 | ind_levels, win); | |
4517 | } | |
4518 | break; | |
4519 | win: | |
4520 | *memrefloc = copy_rtx (*memrefloc); | |
4521 | XEXP (*memrefloc, 0) = ad; | |
4522 | move_replacements (&ad, &XEXP (*memrefloc, 0)); | |
4523 | return 1; | |
4524 | } | |
4525 | while (0); | |
4526 | #endif | |
4527 | ||
eab89b90 RK |
4528 | /* The address is not valid. We have to figure out why. One possibility |
4529 | is that it is itself a MEM. This can happen when the frame pointer is | |
4530 | being eliminated, a pseudo is not allocated to a hard register, and the | |
4531 | offset between the frame and stack pointers is not its initial value. | |
d45cf215 | 4532 | In that case the pseudo will have been replaced by a MEM referring to |
eab89b90 RK |
4533 | the stack pointer. */ |
4534 | if (GET_CODE (ad) == MEM) | |
4535 | { | |
4536 | /* First ensure that the address in this MEM is valid. Then, unless | |
4537 | indirect addresses are valid, reload the MEM into a register. */ | |
4538 | tem = ad; | |
4539 | find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0), | |
47c8cf91 | 4540 | opnum, ADDR_TYPE (type), |
55c22565 | 4541 | ind_levels == 0 ? 0 : ind_levels - 1, insn); |
d2555454 RS |
4542 | |
4543 | /* If tem was changed, then we must create a new memory reference to | |
4544 | hold it and store it back into memrefloc. */ | |
4545 | if (tem != ad && memrefloc) | |
ca3e4a2f | 4546 | { |
ca3e4a2f | 4547 | *memrefloc = copy_rtx (*memrefloc); |
3c80f7ed | 4548 | copy_replacements (tem, XEXP (*memrefloc, 0)); |
ca3e4a2f | 4549 | loc = &XEXP (*memrefloc, 0); |
ca3e4a2f | 4550 | } |
d2555454 | 4551 | |
eab89b90 RK |
4552 | /* Check similar cases as for indirect addresses as above except |
4553 | that we can allow pseudos and a MEM since they should have been | |
4554 | taken care of above. */ | |
4555 | ||
4556 | if (ind_levels == 0 | |
4557 | || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok) | |
4558 | || GET_CODE (XEXP (tem, 0)) == MEM | |
4559 | || ! (GET_CODE (XEXP (tem, 0)) == REG | |
4560 | || (GET_CODE (XEXP (tem, 0)) == PLUS | |
4561 | && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG | |
4562 | && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT))) | |
4563 | { | |
4564 | /* Must use TEM here, not AD, since it is the one that will | |
4565 | have any subexpressions reloaded, if needed. */ | |
fb3821f7 | 4566 | push_reload (tem, NULL_RTX, loc, NULL_PTR, |
1ba61f4e ILT |
4567 | reload_address_base_reg_class, GET_MODE (tem), |
4568 | VOIDmode, 0, | |
a8c9daeb | 4569 | 0, opnum, type); |
eab89b90 RK |
4570 | return 1; |
4571 | } | |
4572 | else | |
4573 | return 0; | |
4574 | } | |
4575 | ||
1b4d2764 RK |
4576 | /* If we have address of a stack slot but it's not valid because the |
4577 | displacement is too large, compute the sum in a register. | |
4578 | Handle all base registers here, not just fp/ap/sp, because on some | |
4579 | targets (namely SH) we can also get too large displacements from | |
4580 | big-endian corrections. */ | |
eab89b90 | 4581 | else if (GET_CODE (ad) == PLUS |
1b4d2764 RK |
4582 | && GET_CODE (XEXP (ad, 0)) == REG |
4583 | && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER | |
858c3c8c | 4584 | && REG_MODE_OK_FOR_BASE_P (XEXP (ad, 0), mode) |
eab89b90 RK |
4585 | && GET_CODE (XEXP (ad, 1)) == CONST_INT) |
4586 | { | |
4587 | /* Unshare the MEM rtx so we can safely alter it. */ | |
4588 | if (memrefloc) | |
4589 | { | |
eab89b90 RK |
4590 | *memrefloc = copy_rtx (*memrefloc); |
4591 | loc = &XEXP (*memrefloc, 0); | |
eab89b90 RK |
4592 | } |
4593 | if (double_reg_address_ok) | |
4594 | { | |
4595 | /* Unshare the sum as well. */ | |
4596 | *loc = ad = copy_rtx (ad); | |
4597 | /* Reload the displacement into an index reg. | |
4598 | We assume the frame pointer or arg pointer is a base reg. */ | |
4599 | find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), | |
1ba61f4e ILT |
4600 | reload_address_index_reg_class, |
4601 | GET_MODE (ad), opnum, type, ind_levels); | |
eab89b90 RK |
4602 | } |
4603 | else | |
4604 | { | |
4605 | /* If the sum of two regs is not necessarily valid, | |
4606 | reload the sum into a base reg. | |
4607 | That will at least work. */ | |
1ba61f4e ILT |
4608 | find_reloads_address_part (ad, loc, reload_address_base_reg_class, |
4609 | Pmode, opnum, type, ind_levels); | |
eab89b90 RK |
4610 | } |
4611 | return 1; | |
4612 | } | |
4613 | ||
4614 | /* If we have an indexed stack slot, there are three possible reasons why | |
4615 | it might be invalid: The index might need to be reloaded, the address | |
4616 | might have been made by frame pointer elimination and hence have a | |
f302eea3 | 4617 | constant out of range, or both reasons might apply. |
eab89b90 RK |
4618 | |
4619 | We can easily check for an index needing reload, but even if that is the | |
4620 | case, we might also have an invalid constant. To avoid making the | |
4621 | conservative assumption and requiring two reloads, we see if this address | |
4622 | is valid when not interpreted strictly. If it is, the only problem is | |
4623 | that the index needs a reload and find_reloads_address_1 will take care | |
4624 | of it. | |
4625 | ||
4626 | There is still a case when we might generate an extra reload, | |
4627 | however. In certain cases eliminate_regs will return a MEM for a REG | |
4628 | (see the code there for details). In those cases, memory_address_p | |
4629 | applied to our address will return 0 so we will think that our offset | |
4630 | must be too large. But it might indeed be valid and the only problem | |
4631 | is that a MEM is present where a REG should be. This case should be | |
4632 | very rare and there doesn't seem to be any way to avoid it. | |
4633 | ||
4634 | If we decide to do something here, it must be that | |
4635 | `double_reg_address_ok' is true and that this address rtl was made by | |
4636 | eliminate_regs. We generate a reload of the fp/sp/ap + constant and | |
4637 | rework the sum so that the reload register will be added to the index. | |
4638 | This is safe because we know the address isn't shared. | |
4639 | ||
4640 | We check for fp/ap/sp as both the first and second operand of the | |
4641 | innermost PLUS. */ | |
4642 | ||
4643 | else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
f302eea3 | 4644 | && GET_CODE (XEXP (ad, 0)) == PLUS |
eab89b90 | 4645 | && (XEXP (XEXP (ad, 0), 0) == frame_pointer_rtx |
a36d4c62 DE |
4646 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM |
4647 | || XEXP (XEXP (ad, 0), 0) == hard_frame_pointer_rtx | |
4648 | #endif | |
eab89b90 RK |
4649 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
4650 | || XEXP (XEXP (ad, 0), 0) == arg_pointer_rtx | |
4651 | #endif | |
4652 | || XEXP (XEXP (ad, 0), 0) == stack_pointer_rtx) | |
4653 | && ! memory_address_p (mode, ad)) | |
4654 | { | |
38a448ca RH |
4655 | *loc = ad = gen_rtx_PLUS (GET_MODE (ad), |
4656 | plus_constant (XEXP (XEXP (ad, 0), 0), | |
4657 | INTVAL (XEXP (ad, 1))), | |
eab89b90 | 4658 | XEXP (XEXP (ad, 0), 1)); |
1ba61f4e ILT |
4659 | find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), |
4660 | reload_address_base_reg_class, | |
a8c9daeb | 4661 | GET_MODE (ad), opnum, type, ind_levels); |
858c3c8c | 4662 | find_reloads_address_1 (mode, XEXP (ad, 1), 1, &XEXP (ad, 1), opnum, |
55c22565 | 4663 | type, 0, insn); |
eab89b90 RK |
4664 | |
4665 | return 1; | |
4666 | } | |
4667 | ||
4668 | else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
4669 | && GET_CODE (XEXP (ad, 0)) == PLUS | |
4670 | && (XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx | |
a36d4c62 DE |
4671 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
4672 | || XEXP (XEXP (ad, 0), 1) == hard_frame_pointer_rtx | |
4673 | #endif | |
eab89b90 RK |
4674 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
4675 | || XEXP (XEXP (ad, 0), 1) == arg_pointer_rtx | |
4676 | #endif | |
4677 | || XEXP (XEXP (ad, 0), 1) == stack_pointer_rtx) | |
4678 | && ! memory_address_p (mode, ad)) | |
4679 | { | |
38a448ca RH |
4680 | *loc = ad = gen_rtx_PLUS (GET_MODE (ad), |
4681 | XEXP (XEXP (ad, 0), 0), | |
4682 | plus_constant (XEXP (XEXP (ad, 0), 1), | |
4683 | INTVAL (XEXP (ad, 1)))); | |
1ba61f4e ILT |
4684 | find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), |
4685 | reload_address_base_reg_class, | |
a8c9daeb | 4686 | GET_MODE (ad), opnum, type, ind_levels); |
858c3c8c | 4687 | find_reloads_address_1 (mode, XEXP (ad, 0), 1, &XEXP (ad, 0), opnum, |
55c22565 | 4688 | type, 0, insn); |
eab89b90 RK |
4689 | |
4690 | return 1; | |
4691 | } | |
4692 | ||
4693 | /* See if address becomes valid when an eliminable register | |
4694 | in a sum is replaced. */ | |
4695 | ||
4696 | tem = ad; | |
4697 | if (GET_CODE (ad) == PLUS) | |
4698 | tem = subst_indexed_address (ad); | |
4699 | if (tem != ad && strict_memory_address_p (mode, tem)) | |
4700 | { | |
4701 | /* Ok, we win that way. Replace any additional eliminable | |
4702 | registers. */ | |
4703 | ||
4704 | subst_reg_equivs_changed = 0; | |
4705 | tem = subst_reg_equivs (tem); | |
4706 | ||
4707 | /* Make sure that didn't make the address invalid again. */ | |
4708 | ||
4709 | if (! subst_reg_equivs_changed || strict_memory_address_p (mode, tem)) | |
4710 | { | |
4711 | *loc = tem; | |
4712 | return 0; | |
4713 | } | |
4714 | } | |
4715 | ||
4716 | /* If constants aren't valid addresses, reload the constant address | |
4717 | into a register. */ | |
191b18e9 | 4718 | if (CONSTANT_P (ad) && ! strict_memory_address_p (mode, ad)) |
eab89b90 RK |
4719 | { |
4720 | /* If AD is in address in the constant pool, the MEM rtx may be shared. | |
4721 | Unshare it so we can safely alter it. */ | |
4722 | if (memrefloc && GET_CODE (ad) == SYMBOL_REF | |
4723 | && CONSTANT_POOL_ADDRESS_P (ad)) | |
4724 | { | |
eab89b90 RK |
4725 | *memrefloc = copy_rtx (*memrefloc); |
4726 | loc = &XEXP (*memrefloc, 0); | |
eab89b90 RK |
4727 | } |
4728 | ||
1ba61f4e ILT |
4729 | find_reloads_address_part (ad, loc, reload_address_base_reg_class, |
4730 | Pmode, opnum, type, | |
eab89b90 RK |
4731 | ind_levels); |
4732 | return 1; | |
4733 | } | |
4734 | ||
55c22565 RK |
4735 | return find_reloads_address_1 (mode, ad, 0, loc, opnum, type, ind_levels, |
4736 | insn); | |
eab89b90 RK |
4737 | } |
4738 | \f | |
4739 | /* Find all pseudo regs appearing in AD | |
4740 | that are eliminable in favor of equivalent values | |
4741 | and do not have hard regs; replace them by their equivalents. */ | |
4742 | ||
4743 | static rtx | |
4744 | subst_reg_equivs (ad) | |
4745 | rtx ad; | |
4746 | { | |
4747 | register RTX_CODE code = GET_CODE (ad); | |
4748 | register int i; | |
4749 | register char *fmt; | |
4750 | ||
4751 | switch (code) | |
4752 | { | |
4753 | case HIGH: | |
4754 | case CONST_INT: | |
4755 | case CONST: | |
4756 | case CONST_DOUBLE: | |
4757 | case SYMBOL_REF: | |
4758 | case LABEL_REF: | |
4759 | case PC: | |
4760 | case CC0: | |
4761 | return ad; | |
4762 | ||
4763 | case REG: | |
4764 | { | |
4765 | register int regno = REGNO (ad); | |
4766 | ||
4767 | if (reg_equiv_constant[regno] != 0) | |
4768 | { | |
4769 | subst_reg_equivs_changed = 1; | |
4770 | return reg_equiv_constant[regno]; | |
4771 | } | |
4772 | } | |
4773 | return ad; | |
4774 | ||
4775 | case PLUS: | |
4776 | /* Quickly dispose of a common case. */ | |
4777 | if (XEXP (ad, 0) == frame_pointer_rtx | |
4778 | && GET_CODE (XEXP (ad, 1)) == CONST_INT) | |
4779 | return ad; | |
e9a25f70 JL |
4780 | break; |
4781 | ||
4782 | default: | |
4783 | break; | |
eab89b90 RK |
4784 | } |
4785 | ||
4786 | fmt = GET_RTX_FORMAT (code); | |
4787 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4788 | if (fmt[i] == 'e') | |
4789 | XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i)); | |
4790 | return ad; | |
4791 | } | |
4792 | \f | |
4793 | /* Compute the sum of X and Y, making canonicalizations assumed in an | |
4794 | address, namely: sum constant integers, surround the sum of two | |
4795 | constants with a CONST, put the constant as the second operand, and | |
4796 | group the constant on the outermost sum. | |
4797 | ||
4798 | This routine assumes both inputs are already in canonical form. */ | |
4799 | ||
4800 | rtx | |
4801 | form_sum (x, y) | |
4802 | rtx x, y; | |
4803 | { | |
4804 | rtx tem; | |
2c0623e8 RK |
4805 | enum machine_mode mode = GET_MODE (x); |
4806 | ||
4807 | if (mode == VOIDmode) | |
4808 | mode = GET_MODE (y); | |
4809 | ||
4810 | if (mode == VOIDmode) | |
4811 | mode = Pmode; | |
eab89b90 RK |
4812 | |
4813 | if (GET_CODE (x) == CONST_INT) | |
4814 | return plus_constant (y, INTVAL (x)); | |
4815 | else if (GET_CODE (y) == CONST_INT) | |
4816 | return plus_constant (x, INTVAL (y)); | |
4817 | else if (CONSTANT_P (x)) | |
4818 | tem = x, x = y, y = tem; | |
4819 | ||
4820 | if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1))) | |
4821 | return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y)); | |
4822 | ||
4823 | /* Note that if the operands of Y are specified in the opposite | |
4824 | order in the recursive calls below, infinite recursion will occur. */ | |
d9771f62 | 4825 | if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1))) |
eab89b90 RK |
4826 | return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1)); |
4827 | ||
4828 | /* If both constant, encapsulate sum. Otherwise, just form sum. A | |
4829 | constant will have been placed second. */ | |
4830 | if (CONSTANT_P (x) && CONSTANT_P (y)) | |
4831 | { | |
4832 | if (GET_CODE (x) == CONST) | |
4833 | x = XEXP (x, 0); | |
4834 | if (GET_CODE (y) == CONST) | |
4835 | y = XEXP (y, 0); | |
4836 | ||
38a448ca | 4837 | return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y)); |
eab89b90 RK |
4838 | } |
4839 | ||
38a448ca | 4840 | return gen_rtx_PLUS (mode, x, y); |
eab89b90 RK |
4841 | } |
4842 | \f | |
4843 | /* If ADDR is a sum containing a pseudo register that should be | |
4844 | replaced with a constant (from reg_equiv_constant), | |
4845 | return the result of doing so, and also apply the associative | |
4846 | law so that the result is more likely to be a valid address. | |
4847 | (But it is not guaranteed to be one.) | |
4848 | ||
4849 | Note that at most one register is replaced, even if more are | |
4850 | replaceable. Also, we try to put the result into a canonical form | |
4851 | so it is more likely to be a valid address. | |
4852 | ||
4853 | In all other cases, return ADDR. */ | |
4854 | ||
4855 | static rtx | |
4856 | subst_indexed_address (addr) | |
4857 | rtx addr; | |
4858 | { | |
4859 | rtx op0 = 0, op1 = 0, op2 = 0; | |
4860 | rtx tem; | |
4861 | int regno; | |
4862 | ||
4863 | if (GET_CODE (addr) == PLUS) | |
4864 | { | |
4865 | /* Try to find a register to replace. */ | |
4866 | op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0; | |
4867 | if (GET_CODE (op0) == REG | |
4868 | && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER | |
4869 | && reg_renumber[regno] < 0 | |
4870 | && reg_equiv_constant[regno] != 0) | |
4871 | op0 = reg_equiv_constant[regno]; | |
4872 | else if (GET_CODE (op1) == REG | |
4873 | && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER | |
4874 | && reg_renumber[regno] < 0 | |
4875 | && reg_equiv_constant[regno] != 0) | |
4876 | op1 = reg_equiv_constant[regno]; | |
4877 | else if (GET_CODE (op0) == PLUS | |
4878 | && (tem = subst_indexed_address (op0)) != op0) | |
4879 | op0 = tem; | |
4880 | else if (GET_CODE (op1) == PLUS | |
4881 | && (tem = subst_indexed_address (op1)) != op1) | |
4882 | op1 = tem; | |
4883 | else | |
4884 | return addr; | |
4885 | ||
4886 | /* Pick out up to three things to add. */ | |
4887 | if (GET_CODE (op1) == PLUS) | |
4888 | op2 = XEXP (op1, 1), op1 = XEXP (op1, 0); | |
4889 | else if (GET_CODE (op0) == PLUS) | |
4890 | op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
4891 | ||
4892 | /* Compute the sum. */ | |
4893 | if (op2 != 0) | |
4894 | op1 = form_sum (op1, op2); | |
4895 | if (op1 != 0) | |
4896 | op0 = form_sum (op0, op1); | |
4897 | ||
4898 | return op0; | |
4899 | } | |
4900 | return addr; | |
4901 | } | |
4902 | \f | |
858c3c8c ILT |
4903 | /* Record the pseudo registers we must reload into hard registers in a |
4904 | subexpression of a would-be memory address, X referring to a value | |
4905 | in mode MODE. (This function is not called if the address we find | |
4906 | is strictly valid.) | |
4907 | ||
eab89b90 RK |
4908 | CONTEXT = 1 means we are considering regs as index regs, |
4909 | = 0 means we are considering them as base regs. | |
4910 | ||
a8c9daeb | 4911 | OPNUM and TYPE specify the purpose of any reloads made. |
eab89b90 RK |
4912 | |
4913 | IND_LEVELS says how many levels of indirect addressing are | |
4914 | supported at this point in the address. | |
4915 | ||
55c22565 RK |
4916 | INSN, if nonzero, is the insn in which we do the reload. It is used |
4917 | to determine if we may generate output reloads. | |
4918 | ||
eab89b90 RK |
4919 | We return nonzero if X, as a whole, is reloaded or replaced. */ |
4920 | ||
4921 | /* Note that we take shortcuts assuming that no multi-reg machine mode | |
4922 | occurs as part of an address. | |
4923 | Also, this is not fully machine-customizable; it works for machines | |
4924 | such as vaxes and 68000's and 32000's, but other possible machines | |
4925 | could have addressing modes that this does not handle right. */ | |
4926 | ||
4927 | static int | |
55c22565 | 4928 | find_reloads_address_1 (mode, x, context, loc, opnum, type, ind_levels, insn) |
858c3c8c | 4929 | enum machine_mode mode; |
eab89b90 RK |
4930 | rtx x; |
4931 | int context; | |
4932 | rtx *loc; | |
a8c9daeb RK |
4933 | int opnum; |
4934 | enum reload_type type; | |
eab89b90 | 4935 | int ind_levels; |
55c22565 | 4936 | rtx insn; |
eab89b90 RK |
4937 | { |
4938 | register RTX_CODE code = GET_CODE (x); | |
4939 | ||
a2d353e5 | 4940 | switch (code) |
eab89b90 | 4941 | { |
a2d353e5 RK |
4942 | case PLUS: |
4943 | { | |
4944 | register rtx orig_op0 = XEXP (x, 0); | |
4945 | register rtx orig_op1 = XEXP (x, 1); | |
4946 | register RTX_CODE code0 = GET_CODE (orig_op0); | |
4947 | register RTX_CODE code1 = GET_CODE (orig_op1); | |
4948 | register rtx op0 = orig_op0; | |
4949 | register rtx op1 = orig_op1; | |
4950 | ||
4951 | if (GET_CODE (op0) == SUBREG) | |
4952 | { | |
4953 | op0 = SUBREG_REG (op0); | |
4954 | code0 = GET_CODE (op0); | |
922db4bb | 4955 | if (code0 == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER) |
38a448ca RH |
4956 | op0 = gen_rtx_REG (word_mode, |
4957 | REGNO (op0) + SUBREG_WORD (orig_op0)); | |
a2d353e5 | 4958 | } |
87935f60 | 4959 | |
a2d353e5 RK |
4960 | if (GET_CODE (op1) == SUBREG) |
4961 | { | |
4962 | op1 = SUBREG_REG (op1); | |
4963 | code1 = GET_CODE (op1); | |
922db4bb | 4964 | if (code1 == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER) |
38a448ca RH |
4965 | op1 = gen_rtx_REG (GET_MODE (op1), |
4966 | REGNO (op1) + SUBREG_WORD (orig_op1)); | |
a2d353e5 RK |
4967 | } |
4968 | ||
5f8997b9 SC |
4969 | if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE |
4970 | || code0 == ZERO_EXTEND || code1 == MEM) | |
a2d353e5 | 4971 | { |
858c3c8c | 4972 | find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum, |
55c22565 | 4973 | type, ind_levels, insn); |
858c3c8c | 4974 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 4975 | type, ind_levels, insn); |
a2d353e5 RK |
4976 | } |
4977 | ||
5f8997b9 SC |
4978 | else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE |
4979 | || code1 == ZERO_EXTEND || code0 == MEM) | |
a2d353e5 | 4980 | { |
858c3c8c | 4981 | find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum, |
55c22565 | 4982 | type, ind_levels, insn); |
858c3c8c | 4983 | find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum, |
55c22565 | 4984 | type, ind_levels, insn); |
a2d353e5 RK |
4985 | } |
4986 | ||
4987 | else if (code0 == CONST_INT || code0 == CONST | |
4988 | || code0 == SYMBOL_REF || code0 == LABEL_REF) | |
858c3c8c | 4989 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 4990 | type, ind_levels, insn); |
a2d353e5 RK |
4991 | |
4992 | else if (code1 == CONST_INT || code1 == CONST | |
4993 | || code1 == SYMBOL_REF || code1 == LABEL_REF) | |
858c3c8c | 4994 | find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum, |
55c22565 | 4995 | type, ind_levels, insn); |
a2d353e5 RK |
4996 | |
4997 | else if (code0 == REG && code1 == REG) | |
4998 | { | |
4999 | if (REG_OK_FOR_INDEX_P (op0) | |
858c3c8c | 5000 | && REG_MODE_OK_FOR_BASE_P (op1, mode)) |
a2d353e5 RK |
5001 | return 0; |
5002 | else if (REG_OK_FOR_INDEX_P (op1) | |
858c3c8c | 5003 | && REG_MODE_OK_FOR_BASE_P (op0, mode)) |
a2d353e5 | 5004 | return 0; |
858c3c8c ILT |
5005 | else if (REG_MODE_OK_FOR_BASE_P (op1, mode)) |
5006 | find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum, | |
55c22565 | 5007 | type, ind_levels, insn); |
858c3c8c ILT |
5008 | else if (REG_MODE_OK_FOR_BASE_P (op0, mode)) |
5009 | find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum, | |
55c22565 | 5010 | type, ind_levels, insn); |
a2d353e5 | 5011 | else if (REG_OK_FOR_INDEX_P (op1)) |
858c3c8c | 5012 | find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum, |
55c22565 | 5013 | type, ind_levels, insn); |
a2d353e5 | 5014 | else if (REG_OK_FOR_INDEX_P (op0)) |
858c3c8c | 5015 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 5016 | type, ind_levels, insn); |
a2d353e5 RK |
5017 | else |
5018 | { | |
858c3c8c | 5019 | find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum, |
55c22565 | 5020 | type, ind_levels, insn); |
858c3c8c | 5021 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 5022 | type, ind_levels, insn); |
a2d353e5 RK |
5023 | } |
5024 | } | |
5025 | ||
5026 | else if (code0 == REG) | |
5027 | { | |
858c3c8c | 5028 | find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum, |
55c22565 | 5029 | type, ind_levels, insn); |
858c3c8c | 5030 | find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum, |
55c22565 | 5031 | type, ind_levels, insn); |
a2d353e5 RK |
5032 | } |
5033 | ||
5034 | else if (code1 == REG) | |
5035 | { | |
858c3c8c | 5036 | find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum, |
55c22565 | 5037 | type, ind_levels, insn); |
858c3c8c | 5038 | find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum, |
55c22565 | 5039 | type, ind_levels, insn); |
a2d353e5 RK |
5040 | } |
5041 | } | |
5042 | ||
5043 | return 0; | |
5044 | ||
5045 | case POST_INC: | |
5046 | case POST_DEC: | |
5047 | case PRE_INC: | |
5048 | case PRE_DEC: | |
eab89b90 RK |
5049 | if (GET_CODE (XEXP (x, 0)) == REG) |
5050 | { | |
5051 | register int regno = REGNO (XEXP (x, 0)); | |
5052 | int value = 0; | |
5053 | rtx x_orig = x; | |
5054 | ||
5055 | /* A register that is incremented cannot be constant! */ | |
5056 | if (regno >= FIRST_PSEUDO_REGISTER | |
5057 | && reg_equiv_constant[regno] != 0) | |
5058 | abort (); | |
5059 | ||
5060 | /* Handle a register that is equivalent to a memory location | |
5061 | which cannot be addressed directly. */ | |
5062 | if (reg_equiv_address[regno] != 0) | |
5063 | { | |
5064 | rtx tem = make_memloc (XEXP (x, 0), regno); | |
4757e6a4 JW |
5065 | /* First reload the memory location's address. |
5066 | We can't use ADDR_TYPE (type) here, because we need to | |
5067 | write back the value after reading it, hence we actually | |
5068 | need two registers. */ | |
eab89b90 | 5069 | find_reloads_address (GET_MODE (tem), 0, XEXP (tem, 0), |
4757e6a4 | 5070 | &XEXP (tem, 0), opnum, type, |
55c22565 | 5071 | ind_levels, insn); |
eab89b90 | 5072 | /* Put this inside a new increment-expression. */ |
38a448ca | 5073 | x = gen_rtx_fmt_e (GET_CODE (x), GET_MODE (x), tem); |
eab89b90 RK |
5074 | /* Proceed to reload that, as if it contained a register. */ |
5075 | } | |
5076 | ||
5077 | /* If we have a hard register that is ok as an index, | |
5078 | don't make a reload. If an autoincrement of a nice register | |
5079 | isn't "valid", it must be that no autoincrement is "valid". | |
5080 | If that is true and something made an autoincrement anyway, | |
5081 | this must be a special context where one is allowed. | |
5082 | (For example, a "push" instruction.) | |
5083 | We can't improve this address, so leave it alone. */ | |
5084 | ||
5085 | /* Otherwise, reload the autoincrement into a suitable hard reg | |
5086 | and record how much to increment by. */ | |
5087 | ||
5088 | if (reg_renumber[regno] >= 0) | |
5089 | regno = reg_renumber[regno]; | |
5090 | if ((regno >= FIRST_PSEUDO_REGISTER | |
5091 | || !(context ? REGNO_OK_FOR_INDEX_P (regno) | |
858c3c8c | 5092 | : REGNO_MODE_OK_FOR_BASE_P (regno, mode)))) |
eab89b90 | 5093 | { |
29a82058 | 5094 | #ifdef AUTO_INC_DEC |
eab89b90 | 5095 | register rtx link; |
29a82058 | 5096 | #endif |
55c22565 RK |
5097 | int reloadnum; |
5098 | ||
5099 | /* If we can output the register afterwards, do so, this | |
5100 | saves the extra update. | |
5101 | We can do so if we have an INSN - i.e. no JUMP_INSN nor | |
5102 | CALL_INSN - and it does not set CC0. | |
5103 | But don't do this if we cannot directly address the | |
5104 | memory location, since this will make it harder to | |
956d6950 | 5105 | reuse address reloads, and increases register pressure. |
55c22565 RK |
5106 | Also don't do this if we can probably update x directly. */ |
5107 | rtx equiv = reg_equiv_mem[regno]; | |
5108 | int icode = (int) add_optab->handlers[(int) Pmode].insn_code; | |
5109 | if (insn && GET_CODE (insn) == INSN && equiv | |
5110 | #ifdef HAVE_cc0 | |
5111 | && ! sets_cc0_p (PATTERN (insn)) | |
5112 | #endif | |
5113 | && ! (icode != CODE_FOR_nothing | |
5114 | && (*insn_operand_predicate[icode][0]) (equiv, Pmode) | |
5115 | && (*insn_operand_predicate[icode][1]) (equiv, Pmode))) | |
5116 | { | |
5117 | loc = &XEXP (x, 0); | |
5118 | x = XEXP (x, 0); | |
5119 | reloadnum | |
5120 | = push_reload (x, x, loc, loc, | |
5121 | (context | |
5122 | ? reload_address_index_reg_class | |
5123 | : reload_address_base_reg_class), | |
e9a25f70 | 5124 | GET_MODE (x), GET_MODE (x), 0, 0, |
55c22565 RK |
5125 | opnum, RELOAD_OTHER); |
5126 | } | |
5127 | else | |
5128 | { | |
5129 | reloadnum | |
5130 | = push_reload (x, NULL_RTX, loc, NULL_PTR, | |
5131 | (context | |
5132 | ? reload_address_index_reg_class | |
5133 | : reload_address_base_reg_class), | |
e9a25f70 | 5134 | GET_MODE (x), GET_MODE (x), 0, 0, |
55c22565 RK |
5135 | opnum, type); |
5136 | reload_inc[reloadnum] | |
5137 | = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0)); | |
5138 | ||
5139 | value = 1; | |
5140 | } | |
eab89b90 RK |
5141 | |
5142 | #ifdef AUTO_INC_DEC | |
5143 | /* Update the REG_INC notes. */ | |
5144 | ||
5145 | for (link = REG_NOTES (this_insn); | |
5146 | link; link = XEXP (link, 1)) | |
5147 | if (REG_NOTE_KIND (link) == REG_INC | |
5148 | && REGNO (XEXP (link, 0)) == REGNO (XEXP (x_orig, 0))) | |
5149 | push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); | |
5150 | #endif | |
5151 | } | |
5152 | return value; | |
5153 | } | |
a2d353e5 | 5154 | |
eab89b90 RK |
5155 | else if (GET_CODE (XEXP (x, 0)) == MEM) |
5156 | { | |
5157 | /* This is probably the result of a substitution, by eliminate_regs, | |
5158 | of an equivalent address for a pseudo that was not allocated to a | |
5159 | hard register. Verify that the specified address is valid and | |
5160 | reload it into a register. */ | |
5161 | rtx tem = XEXP (x, 0); | |
5162 | register rtx link; | |
5163 | int reloadnum; | |
5164 | ||
5165 | /* Since we know we are going to reload this item, don't decrement | |
5166 | for the indirection level. | |
5167 | ||
5168 | Note that this is actually conservative: it would be slightly | |
5169 | more efficient to use the value of SPILL_INDIRECT_LEVELS from | |
5170 | reload1.c here. */ | |
4757e6a4 JW |
5171 | /* We can't use ADDR_TYPE (type) here, because we need to |
5172 | write back the value after reading it, hence we actually | |
5173 | need two registers. */ | |
eab89b90 RK |
5174 | find_reloads_address (GET_MODE (x), &XEXP (x, 0), |
5175 | XEXP (XEXP (x, 0), 0), &XEXP (XEXP (x, 0), 0), | |
55c22565 | 5176 | opnum, type, ind_levels, insn); |
eab89b90 | 5177 | |
fb3821f7 | 5178 | reloadnum = push_reload (x, NULL_RTX, loc, NULL_PTR, |
1ba61f4e ILT |
5179 | (context |
5180 | ? reload_address_index_reg_class | |
5181 | : reload_address_base_reg_class), | |
a8c9daeb | 5182 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
5183 | reload_inc[reloadnum] |
5184 | = find_inc_amount (PATTERN (this_insn), XEXP (x, 0)); | |
5185 | ||
5186 | link = FIND_REG_INC_NOTE (this_insn, tem); | |
5187 | if (link != 0) | |
5188 | push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); | |
5189 | ||
5190 | return 1; | |
5191 | } | |
a2d353e5 RK |
5192 | return 0; |
5193 | ||
5194 | case MEM: | |
5195 | /* This is probably the result of a substitution, by eliminate_regs, of | |
5196 | an equivalent address for a pseudo that was not allocated to a hard | |
5197 | register. Verify that the specified address is valid and reload it | |
5198 | into a register. | |
eab89b90 | 5199 | |
a2d353e5 RK |
5200 | Since we know we are going to reload this item, don't decrement for |
5201 | the indirection level. | |
eab89b90 RK |
5202 | |
5203 | Note that this is actually conservative: it would be slightly more | |
5204 | efficient to use the value of SPILL_INDIRECT_LEVELS from | |
5205 | reload1.c here. */ | |
5206 | ||
5207 | find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0), | |
55c22565 | 5208 | opnum, ADDR_TYPE (type), ind_levels, insn); |
fb3821f7 | 5209 | push_reload (*loc, NULL_RTX, loc, NULL_PTR, |
1ba61f4e ILT |
5210 | (context ? reload_address_index_reg_class |
5211 | : reload_address_base_reg_class), | |
a8c9daeb | 5212 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
eab89b90 | 5213 | return 1; |
eab89b90 | 5214 | |
a2d353e5 RK |
5215 | case REG: |
5216 | { | |
5217 | register int regno = REGNO (x); | |
5218 | ||
5219 | if (reg_equiv_constant[regno] != 0) | |
5220 | { | |
5221 | find_reloads_address_part (reg_equiv_constant[regno], loc, | |
1ba61f4e ILT |
5222 | (context |
5223 | ? reload_address_index_reg_class | |
5224 | : reload_address_base_reg_class), | |
a2d353e5 RK |
5225 | GET_MODE (x), opnum, type, ind_levels); |
5226 | return 1; | |
5227 | } | |
eab89b90 RK |
5228 | |
5229 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
5230 | that feeds this insn. */ | |
a2d353e5 RK |
5231 | if (reg_equiv_mem[regno] != 0) |
5232 | { | |
5233 | push_reload (reg_equiv_mem[regno], NULL_RTX, loc, NULL_PTR, | |
1ba61f4e ILT |
5234 | (context |
5235 | ? reload_address_index_reg_class | |
5236 | : reload_address_base_reg_class), | |
a2d353e5 RK |
5237 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5238 | return 1; | |
5239 | } | |
eab89b90 | 5240 | #endif |
eab89b90 | 5241 | |
a2d353e5 RK |
5242 | if (reg_equiv_address[regno] != 0) |
5243 | { | |
5244 | x = make_memloc (x, regno); | |
5245 | find_reloads_address (GET_MODE (x), 0, XEXP (x, 0), &XEXP (x, 0), | |
55c22565 | 5246 | opnum, ADDR_TYPE (type), ind_levels, insn); |
a2d353e5 | 5247 | } |
eab89b90 | 5248 | |
a2d353e5 RK |
5249 | if (reg_renumber[regno] >= 0) |
5250 | regno = reg_renumber[regno]; | |
5251 | ||
5252 | if ((regno >= FIRST_PSEUDO_REGISTER | |
5253 | || !(context ? REGNO_OK_FOR_INDEX_P (regno) | |
858c3c8c | 5254 | : REGNO_MODE_OK_FOR_BASE_P (regno, mode)))) |
a2d353e5 RK |
5255 | { |
5256 | push_reload (x, NULL_RTX, loc, NULL_PTR, | |
1ba61f4e ILT |
5257 | (context |
5258 | ? reload_address_index_reg_class | |
5259 | : reload_address_base_reg_class), | |
a2d353e5 RK |
5260 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5261 | return 1; | |
5262 | } | |
5263 | ||
5264 | /* If a register appearing in an address is the subject of a CLOBBER | |
5265 | in this insn, reload it into some other register to be safe. | |
5266 | The CLOBBER is supposed to make the register unavailable | |
5267 | from before this insn to after it. */ | |
5268 | if (regno_clobbered_p (regno, this_insn)) | |
5269 | { | |
5270 | push_reload (x, NULL_RTX, loc, NULL_PTR, | |
1ba61f4e ILT |
5271 | (context |
5272 | ? reload_address_index_reg_class | |
5273 | : reload_address_base_reg_class), | |
a2d353e5 RK |
5274 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5275 | return 1; | |
5276 | } | |
5277 | } | |
5278 | return 0; | |
5279 | ||
5280 | case SUBREG: | |
922db4bb | 5281 | if (GET_CODE (SUBREG_REG (x)) == REG) |
eab89b90 | 5282 | { |
922db4bb RK |
5283 | /* If this is a SUBREG of a hard register and the resulting register |
5284 | is of the wrong class, reload the whole SUBREG. This avoids | |
5285 | needless copies if SUBREG_REG is multi-word. */ | |
5286 | if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) | |
5287 | { | |
5288 | int regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x); | |
a2d353e5 | 5289 | |
922db4bb | 5290 | if (! (context ? REGNO_OK_FOR_INDEX_P (regno) |
858c3c8c | 5291 | : REGNO_MODE_OK_FOR_BASE_P (regno, mode))) |
922db4bb RK |
5292 | { |
5293 | push_reload (x, NULL_RTX, loc, NULL_PTR, | |
1ba61f4e ILT |
5294 | (context |
5295 | ? reload_address_index_reg_class | |
5296 | : reload_address_base_reg_class), | |
922db4bb RK |
5297 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5298 | return 1; | |
5299 | } | |
5300 | } | |
abc95ed3 | 5301 | /* If this is a SUBREG of a pseudo-register, and the pseudo-register |
922db4bb RK |
5302 | is larger than the class size, then reload the whole SUBREG. */ |
5303 | else | |
a2d353e5 | 5304 | { |
922db4bb | 5305 | enum reg_class class = (context |
1ba61f4e ILT |
5306 | ? reload_address_index_reg_class |
5307 | : reload_address_base_reg_class); | |
922db4bb RK |
5308 | if (CLASS_MAX_NREGS (class, GET_MODE (SUBREG_REG (x))) |
5309 | > reg_class_size[class]) | |
5310 | { | |
5311 | push_reload (x, NULL_RTX, loc, NULL_PTR, class, | |
5312 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); | |
5313 | return 1; | |
5314 | } | |
a2d353e5 | 5315 | } |
eab89b90 | 5316 | } |
a2d353e5 | 5317 | break; |
e9a25f70 JL |
5318 | |
5319 | default: | |
5320 | break; | |
eab89b90 RK |
5321 | } |
5322 | ||
a2d353e5 RK |
5323 | { |
5324 | register char *fmt = GET_RTX_FORMAT (code); | |
5325 | register int i; | |
5326 | ||
5327 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5328 | { | |
5329 | if (fmt[i] == 'e') | |
858c3c8c | 5330 | find_reloads_address_1 (mode, XEXP (x, i), context, &XEXP (x, i), |
55c22565 | 5331 | opnum, type, ind_levels, insn); |
a2d353e5 RK |
5332 | } |
5333 | } | |
5334 | ||
eab89b90 RK |
5335 | return 0; |
5336 | } | |
5337 | \f | |
5338 | /* X, which is found at *LOC, is a part of an address that needs to be | |
5339 | reloaded into a register of class CLASS. If X is a constant, or if | |
5340 | X is a PLUS that contains a constant, check that the constant is a | |
5341 | legitimate operand and that we are supposed to be able to load | |
5342 | it into the register. | |
5343 | ||
5344 | If not, force the constant into memory and reload the MEM instead. | |
5345 | ||
5346 | MODE is the mode to use, in case X is an integer constant. | |
5347 | ||
a8c9daeb | 5348 | OPNUM and TYPE describe the purpose of any reloads made. |
eab89b90 RK |
5349 | |
5350 | IND_LEVELS says how many levels of indirect addressing this machine | |
5351 | supports. */ | |
5352 | ||
5353 | static void | |
a8c9daeb | 5354 | find_reloads_address_part (x, loc, class, mode, opnum, type, ind_levels) |
eab89b90 RK |
5355 | rtx x; |
5356 | rtx *loc; | |
5357 | enum reg_class class; | |
5358 | enum machine_mode mode; | |
a8c9daeb RK |
5359 | int opnum; |
5360 | enum reload_type type; | |
eab89b90 RK |
5361 | int ind_levels; |
5362 | { | |
5363 | if (CONSTANT_P (x) | |
5364 | && (! LEGITIMATE_CONSTANT_P (x) | |
5365 | || PREFERRED_RELOAD_CLASS (x, class) == NO_REGS)) | |
5366 | { | |
5367 | rtx tem = x = force_const_mem (mode, x); | |
5368 | find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), | |
55c22565 | 5369 | opnum, type, ind_levels, 0); |
eab89b90 RK |
5370 | } |
5371 | ||
5372 | else if (GET_CODE (x) == PLUS | |
5373 | && CONSTANT_P (XEXP (x, 1)) | |
5374 | && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1)) | |
5375 | || PREFERRED_RELOAD_CLASS (XEXP (x, 1), class) == NO_REGS)) | |
5376 | { | |
5377 | rtx tem = force_const_mem (GET_MODE (x), XEXP (x, 1)); | |
5378 | ||
38a448ca | 5379 | x = gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), tem); |
eab89b90 | 5380 | find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), |
55c22565 | 5381 | opnum, type, ind_levels, 0); |
eab89b90 RK |
5382 | } |
5383 | ||
fb3821f7 | 5384 | push_reload (x, NULL_RTX, loc, NULL_PTR, class, |
a8c9daeb | 5385 | mode, VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
5386 | } |
5387 | \f | |
a8c9daeb | 5388 | /* Substitute into the current INSN the registers into which we have reloaded |
eab89b90 RK |
5389 | the things that need reloading. The array `replacements' |
5390 | says contains the locations of all pointers that must be changed | |
5391 | and says what to replace them with. | |
5392 | ||
5393 | Return the rtx that X translates into; usually X, but modified. */ | |
5394 | ||
5395 | void | |
5396 | subst_reloads () | |
5397 | { | |
5398 | register int i; | |
5399 | ||
5400 | for (i = 0; i < n_replacements; i++) | |
5401 | { | |
5402 | register struct replacement *r = &replacements[i]; | |
5403 | register rtx reloadreg = reload_reg_rtx[r->what]; | |
5404 | if (reloadreg) | |
5405 | { | |
5406 | /* Encapsulate RELOADREG so its machine mode matches what | |
26f1a00e RK |
5407 | used to be there. Note that gen_lowpart_common will |
5408 | do the wrong thing if RELOADREG is multi-word. RELOADREG | |
5409 | will always be a REG here. */ | |
eab89b90 | 5410 | if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode) |
38a448ca | 5411 | reloadreg = gen_rtx_REG (r->mode, REGNO (reloadreg)); |
eab89b90 RK |
5412 | |
5413 | /* If we are putting this into a SUBREG and RELOADREG is a | |
5414 | SUBREG, we would be making nested SUBREGs, so we have to fix | |
5415 | this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */ | |
5416 | ||
5417 | if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG) | |
5418 | { | |
5419 | if (GET_MODE (*r->subreg_loc) | |
5420 | == GET_MODE (SUBREG_REG (reloadreg))) | |
5421 | *r->subreg_loc = SUBREG_REG (reloadreg); | |
5422 | else | |
5423 | { | |
5424 | *r->where = SUBREG_REG (reloadreg); | |
5425 | SUBREG_WORD (*r->subreg_loc) += SUBREG_WORD (reloadreg); | |
5426 | } | |
5427 | } | |
5428 | else | |
5429 | *r->where = reloadreg; | |
5430 | } | |
5431 | /* If reload got no reg and isn't optional, something's wrong. */ | |
5432 | else if (! reload_optional[r->what]) | |
5433 | abort (); | |
5434 | } | |
5435 | } | |
5436 | \f | |
5437 | /* Make a copy of any replacements being done into X and move those copies | |
5438 | to locations in Y, a copy of X. We only look at the highest level of | |
5439 | the RTL. */ | |
5440 | ||
5441 | void | |
5442 | copy_replacements (x, y) | |
5443 | rtx x; | |
5444 | rtx y; | |
5445 | { | |
5446 | int i, j; | |
5447 | enum rtx_code code = GET_CODE (x); | |
5448 | char *fmt = GET_RTX_FORMAT (code); | |
5449 | struct replacement *r; | |
5450 | ||
5451 | /* We can't support X being a SUBREG because we might then need to know its | |
5452 | location if something inside it was replaced. */ | |
5453 | if (code == SUBREG) | |
5454 | abort (); | |
5455 | ||
5456 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5457 | if (fmt[i] == 'e') | |
5458 | for (j = 0; j < n_replacements; j++) | |
5459 | { | |
5460 | if (replacements[j].subreg_loc == &XEXP (x, i)) | |
5461 | { | |
5462 | r = &replacements[n_replacements++]; | |
5463 | r->where = replacements[j].where; | |
5464 | r->subreg_loc = &XEXP (y, i); | |
5465 | r->what = replacements[j].what; | |
5466 | r->mode = replacements[j].mode; | |
5467 | } | |
5468 | else if (replacements[j].where == &XEXP (x, i)) | |
5469 | { | |
5470 | r = &replacements[n_replacements++]; | |
5471 | r->where = &XEXP (y, i); | |
5472 | r->subreg_loc = 0; | |
5473 | r->what = replacements[j].what; | |
5474 | r->mode = replacements[j].mode; | |
5475 | } | |
5476 | } | |
5477 | } | |
a9a2595b JR |
5478 | |
5479 | /* Change any replacements being done to *X to be done to *Y */ | |
5480 | ||
5481 | void | |
5482 | move_replacements (x, y) | |
5483 | rtx *x; | |
5484 | rtx *y; | |
5485 | { | |
5486 | int i; | |
5487 | ||
5488 | for (i = 0; i < n_replacements; i++) | |
5489 | if (replacements[i].subreg_loc == x) | |
5490 | replacements[i].subreg_loc = y; | |
5491 | else if (replacements[i].where == x) | |
5492 | { | |
5493 | replacements[i].where = y; | |
5494 | replacements[i].subreg_loc = 0; | |
5495 | } | |
5496 | } | |
eab89b90 | 5497 | \f |
af929c62 RK |
5498 | /* If LOC was scheduled to be replaced by something, return the replacement. |
5499 | Otherwise, return *LOC. */ | |
5500 | ||
5501 | rtx | |
5502 | find_replacement (loc) | |
5503 | rtx *loc; | |
5504 | { | |
5505 | struct replacement *r; | |
5506 | ||
5507 | for (r = &replacements[0]; r < &replacements[n_replacements]; r++) | |
5508 | { | |
5509 | rtx reloadreg = reload_reg_rtx[r->what]; | |
5510 | ||
5511 | if (reloadreg && r->where == loc) | |
5512 | { | |
5513 | if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode) | |
38a448ca | 5514 | reloadreg = gen_rtx_REG (r->mode, REGNO (reloadreg)); |
af929c62 RK |
5515 | |
5516 | return reloadreg; | |
5517 | } | |
5518 | else if (reloadreg && r->subreg_loc == loc) | |
5519 | { | |
5520 | /* RELOADREG must be either a REG or a SUBREG. | |
5521 | ||
5522 | ??? Is it actually still ever a SUBREG? If so, why? */ | |
5523 | ||
5524 | if (GET_CODE (reloadreg) == REG) | |
38a448ca RH |
5525 | return gen_rtx_REG (GET_MODE (*loc), |
5526 | REGNO (reloadreg) + SUBREG_WORD (*loc)); | |
af929c62 RK |
5527 | else if (GET_MODE (reloadreg) == GET_MODE (*loc)) |
5528 | return reloadreg; | |
5529 | else | |
38a448ca RH |
5530 | return gen_rtx_SUBREG (GET_MODE (*loc), SUBREG_REG (reloadreg), |
5531 | SUBREG_WORD (reloadreg) + SUBREG_WORD (*loc)); | |
af929c62 RK |
5532 | } |
5533 | } | |
5534 | ||
956d6950 JL |
5535 | /* If *LOC is a PLUS, MINUS, or MULT, see if a replacement is scheduled for |
5536 | what's inside and make a new rtl if so. */ | |
5537 | if (GET_CODE (*loc) == PLUS || GET_CODE (*loc) == MINUS | |
5538 | || GET_CODE (*loc) == MULT) | |
5539 | { | |
5540 | rtx x = find_replacement (&XEXP (*loc, 0)); | |
5541 | rtx y = find_replacement (&XEXP (*loc, 1)); | |
5542 | ||
5543 | if (x != XEXP (*loc, 0) || y != XEXP (*loc, 1)) | |
38a448ca | 5544 | return gen_rtx_fmt_ee (GET_CODE (*loc), GET_MODE (*loc), x, y); |
956d6950 JL |
5545 | } |
5546 | ||
af929c62 RK |
5547 | return *loc; |
5548 | } | |
5549 | \f | |
eab89b90 RK |
5550 | /* Return nonzero if register in range [REGNO, ENDREGNO) |
5551 | appears either explicitly or implicitly in X | |
4644aad4 | 5552 | other than being stored into (except for earlyclobber operands). |
eab89b90 RK |
5553 | |
5554 | References contained within the substructure at LOC do not count. | |
5555 | LOC may be zero, meaning don't ignore anything. | |
5556 | ||
5557 | This is similar to refers_to_regno_p in rtlanal.c except that we | |
5558 | look at equivalences for pseudos that didn't get hard registers. */ | |
5559 | ||
5560 | int | |
5561 | refers_to_regno_for_reload_p (regno, endregno, x, loc) | |
5562 | int regno, endregno; | |
5563 | rtx x; | |
5564 | rtx *loc; | |
5565 | { | |
5566 | register int i; | |
5567 | register RTX_CODE code; | |
5568 | register char *fmt; | |
5569 | ||
5570 | if (x == 0) | |
5571 | return 0; | |
5572 | ||
5573 | repeat: | |
5574 | code = GET_CODE (x); | |
5575 | ||
5576 | switch (code) | |
5577 | { | |
5578 | case REG: | |
5579 | i = REGNO (x); | |
5580 | ||
4803a34a RK |
5581 | /* If this is a pseudo, a hard register must not have been allocated. |
5582 | X must therefore either be a constant or be in memory. */ | |
5583 | if (i >= FIRST_PSEUDO_REGISTER) | |
5584 | { | |
5585 | if (reg_equiv_memory_loc[i]) | |
5586 | return refers_to_regno_for_reload_p (regno, endregno, | |
fb3821f7 CH |
5587 | reg_equiv_memory_loc[i], |
5588 | NULL_PTR); | |
4803a34a RK |
5589 | |
5590 | if (reg_equiv_constant[i]) | |
5591 | return 0; | |
5592 | ||
5593 | abort (); | |
5594 | } | |
eab89b90 RK |
5595 | |
5596 | return (endregno > i | |
5597 | && regno < i + (i < FIRST_PSEUDO_REGISTER | |
5598 | ? HARD_REGNO_NREGS (i, GET_MODE (x)) | |
5599 | : 1)); | |
5600 | ||
5601 | case SUBREG: | |
5602 | /* If this is a SUBREG of a hard reg, we can see exactly which | |
5603 | registers are being modified. Otherwise, handle normally. */ | |
5604 | if (GET_CODE (SUBREG_REG (x)) == REG | |
5605 | && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) | |
5606 | { | |
5607 | int inner_regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x); | |
5608 | int inner_endregno | |
5609 | = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER | |
5610 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
5611 | ||
5612 | return endregno > inner_regno && regno < inner_endregno; | |
5613 | } | |
5614 | break; | |
5615 | ||
5616 | case CLOBBER: | |
5617 | case SET: | |
5618 | if (&SET_DEST (x) != loc | |
5619 | /* Note setting a SUBREG counts as referring to the REG it is in for | |
5620 | a pseudo but not for hard registers since we can | |
5621 | treat each word individually. */ | |
5622 | && ((GET_CODE (SET_DEST (x)) == SUBREG | |
5623 | && loc != &SUBREG_REG (SET_DEST (x)) | |
5624 | && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG | |
5625 | && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER | |
5626 | && refers_to_regno_for_reload_p (regno, endregno, | |
5627 | SUBREG_REG (SET_DEST (x)), | |
5628 | loc)) | |
abc95ed3 | 5629 | /* If the output is an earlyclobber operand, this is |
4644aad4 RK |
5630 | a conflict. */ |
5631 | || ((GET_CODE (SET_DEST (x)) != REG | |
5632 | || earlyclobber_operand_p (SET_DEST (x))) | |
eab89b90 RK |
5633 | && refers_to_regno_for_reload_p (regno, endregno, |
5634 | SET_DEST (x), loc)))) | |
5635 | return 1; | |
5636 | ||
5637 | if (code == CLOBBER || loc == &SET_SRC (x)) | |
5638 | return 0; | |
5639 | x = SET_SRC (x); | |
5640 | goto repeat; | |
e9a25f70 JL |
5641 | |
5642 | default: | |
5643 | break; | |
eab89b90 RK |
5644 | } |
5645 | ||
5646 | /* X does not match, so try its subexpressions. */ | |
5647 | ||
5648 | fmt = GET_RTX_FORMAT (code); | |
5649 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5650 | { | |
5651 | if (fmt[i] == 'e' && loc != &XEXP (x, i)) | |
5652 | { | |
5653 | if (i == 0) | |
5654 | { | |
5655 | x = XEXP (x, 0); | |
5656 | goto repeat; | |
5657 | } | |
5658 | else | |
5659 | if (refers_to_regno_for_reload_p (regno, endregno, | |
5660 | XEXP (x, i), loc)) | |
5661 | return 1; | |
5662 | } | |
5663 | else if (fmt[i] == 'E') | |
5664 | { | |
5665 | register int j; | |
5666 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
5667 | if (loc != &XVECEXP (x, i, j) | |
5668 | && refers_to_regno_for_reload_p (regno, endregno, | |
5669 | XVECEXP (x, i, j), loc)) | |
5670 | return 1; | |
5671 | } | |
5672 | } | |
5673 | return 0; | |
5674 | } | |
bfa30b22 RK |
5675 | |
5676 | /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG, | |
5677 | we check if any register number in X conflicts with the relevant register | |
5678 | numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN | |
5679 | contains a MEM (we don't bother checking for memory addresses that can't | |
5680 | conflict because we expect this to be a rare case. | |
5681 | ||
5682 | This function is similar to reg_overlap_mention_p in rtlanal.c except | |
5683 | that we look at equivalences for pseudos that didn't get hard registers. */ | |
5684 | ||
5685 | int | |
5686 | reg_overlap_mentioned_for_reload_p (x, in) | |
5687 | rtx x, in; | |
5688 | { | |
5689 | int regno, endregno; | |
5690 | ||
5691 | if (GET_CODE (x) == SUBREG) | |
5692 | { | |
5693 | regno = REGNO (SUBREG_REG (x)); | |
5694 | if (regno < FIRST_PSEUDO_REGISTER) | |
5695 | regno += SUBREG_WORD (x); | |
5696 | } | |
5697 | else if (GET_CODE (x) == REG) | |
5698 | { | |
5699 | regno = REGNO (x); | |
4803a34a RK |
5700 | |
5701 | /* If this is a pseudo, it must not have been assigned a hard register. | |
5702 | Therefore, it must either be in memory or be a constant. */ | |
5703 | ||
5704 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5705 | { | |
5706 | if (reg_equiv_memory_loc[regno]) | |
5707 | return refers_to_mem_for_reload_p (in); | |
5708 | else if (reg_equiv_constant[regno]) | |
5709 | return 0; | |
5710 | abort (); | |
5711 | } | |
bfa30b22 RK |
5712 | } |
5713 | else if (CONSTANT_P (x)) | |
5714 | return 0; | |
5715 | else if (GET_CODE (x) == MEM) | |
4803a34a | 5716 | return refers_to_mem_for_reload_p (in); |
bfa30b22 RK |
5717 | else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC |
5718 | || GET_CODE (x) == CC0) | |
5719 | return reg_mentioned_p (x, in); | |
5720 | else | |
5721 | abort (); | |
5722 | ||
5723 | endregno = regno + (regno < FIRST_PSEUDO_REGISTER | |
5724 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
5725 | ||
fb3821f7 | 5726 | return refers_to_regno_for_reload_p (regno, endregno, in, NULL_PTR); |
bfa30b22 | 5727 | } |
4803a34a RK |
5728 | |
5729 | /* Return nonzero if anything in X contains a MEM. Look also for pseudo | |
5730 | registers. */ | |
5731 | ||
5732 | int | |
5733 | refers_to_mem_for_reload_p (x) | |
5734 | rtx x; | |
5735 | { | |
5736 | char *fmt; | |
5737 | int i; | |
5738 | ||
5739 | if (GET_CODE (x) == MEM) | |
5740 | return 1; | |
5741 | ||
5742 | if (GET_CODE (x) == REG) | |
5743 | return (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
5744 | && reg_equiv_memory_loc[REGNO (x)]); | |
5745 | ||
5746 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
5747 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
5748 | if (fmt[i] == 'e' | |
5749 | && (GET_CODE (XEXP (x, i)) == MEM | |
5750 | || refers_to_mem_for_reload_p (XEXP (x, i)))) | |
5751 | return 1; | |
5752 | ||
5753 | return 0; | |
5754 | } | |
eab89b90 | 5755 | \f |
eab89b90 RK |
5756 | /* Check the insns before INSN to see if there is a suitable register |
5757 | containing the same value as GOAL. | |
5758 | If OTHER is -1, look for a register in class CLASS. | |
5759 | Otherwise, just see if register number OTHER shares GOAL's value. | |
5760 | ||
5761 | Return an rtx for the register found, or zero if none is found. | |
5762 | ||
5763 | If RELOAD_REG_P is (short *)1, | |
5764 | we reject any hard reg that appears in reload_reg_rtx | |
5765 | because such a hard reg is also needed coming into this insn. | |
5766 | ||
5767 | If RELOAD_REG_P is any other nonzero value, | |
5768 | it is a vector indexed by hard reg number | |
5769 | and we reject any hard reg whose element in the vector is nonnegative | |
5770 | as well as any that appears in reload_reg_rtx. | |
5771 | ||
5772 | If GOAL is zero, then GOALREG is a register number; we look | |
5773 | for an equivalent for that register. | |
5774 | ||
5775 | MODE is the machine mode of the value we want an equivalence for. | |
5776 | If GOAL is nonzero and not VOIDmode, then it must have mode MODE. | |
5777 | ||
5778 | This function is used by jump.c as well as in the reload pass. | |
5779 | ||
5780 | If GOAL is the sum of the stack pointer and a constant, we treat it | |
5781 | as if it were a constant except that sp is required to be unchanging. */ | |
5782 | ||
5783 | rtx | |
5784 | find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode) | |
5785 | register rtx goal; | |
5786 | rtx insn; | |
5787 | enum reg_class class; | |
5788 | register int other; | |
5789 | short *reload_reg_p; | |
5790 | int goalreg; | |
5791 | enum machine_mode mode; | |
5792 | { | |
5793 | register rtx p = insn; | |
f55b1d97 | 5794 | rtx goaltry, valtry, value, where; |
eab89b90 RK |
5795 | register rtx pat; |
5796 | register int regno = -1; | |
5797 | int valueno; | |
5798 | int goal_mem = 0; | |
5799 | int goal_const = 0; | |
5800 | int goal_mem_addr_varies = 0; | |
5801 | int need_stable_sp = 0; | |
5802 | int nregs; | |
5803 | int valuenregs; | |
5804 | ||
5805 | if (goal == 0) | |
5806 | regno = goalreg; | |
5807 | else if (GET_CODE (goal) == REG) | |
5808 | regno = REGNO (goal); | |
5809 | else if (GET_CODE (goal) == MEM) | |
5810 | { | |
5811 | enum rtx_code code = GET_CODE (XEXP (goal, 0)); | |
5812 | if (MEM_VOLATILE_P (goal)) | |
5813 | return 0; | |
5814 | if (flag_float_store && GET_MODE_CLASS (GET_MODE (goal)) == MODE_FLOAT) | |
5815 | return 0; | |
5816 | /* An address with side effects must be reexecuted. */ | |
5817 | switch (code) | |
5818 | { | |
5819 | case POST_INC: | |
5820 | case PRE_INC: | |
5821 | case POST_DEC: | |
5822 | case PRE_DEC: | |
5823 | return 0; | |
e9a25f70 JL |
5824 | default: |
5825 | break; | |
eab89b90 RK |
5826 | } |
5827 | goal_mem = 1; | |
5828 | } | |
5829 | else if (CONSTANT_P (goal)) | |
5830 | goal_const = 1; | |
5831 | else if (GET_CODE (goal) == PLUS | |
5832 | && XEXP (goal, 0) == stack_pointer_rtx | |
5833 | && CONSTANT_P (XEXP (goal, 1))) | |
5834 | goal_const = need_stable_sp = 1; | |
812f2051 R |
5835 | else if (GET_CODE (goal) == PLUS |
5836 | && XEXP (goal, 0) == frame_pointer_rtx | |
5837 | && CONSTANT_P (XEXP (goal, 1))) | |
5838 | goal_const = 1; | |
eab89b90 RK |
5839 | else |
5840 | return 0; | |
5841 | ||
5842 | /* On some machines, certain regs must always be rejected | |
5843 | because they don't behave the way ordinary registers do. */ | |
5844 | ||
5845 | #ifdef OVERLAPPING_REGNO_P | |
5846 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
5847 | && OVERLAPPING_REGNO_P (regno)) | |
5848 | return 0; | |
5849 | #endif | |
5850 | ||
5851 | /* Scan insns back from INSN, looking for one that copies | |
5852 | a value into or out of GOAL. | |
5853 | Stop and give up if we reach a label. */ | |
5854 | ||
5855 | while (1) | |
5856 | { | |
5857 | p = PREV_INSN (p); | |
5858 | if (p == 0 || GET_CODE (p) == CODE_LABEL) | |
5859 | return 0; | |
5860 | if (GET_CODE (p) == INSN | |
0f41302f | 5861 | /* If we don't want spill regs ... */ |
a8c9daeb RK |
5862 | && (! (reload_reg_p != 0 |
5863 | && reload_reg_p != (short *) (HOST_WIDE_INT) 1) | |
eab89b90 RK |
5864 | /* ... then ignore insns introduced by reload; they aren't useful |
5865 | and can cause results in reload_as_needed to be different | |
5866 | from what they were when calculating the need for spills. | |
5867 | If we notice an input-reload insn here, we will reject it below, | |
5868 | but it might hide a usable equivalent. That makes bad code. | |
5869 | It may even abort: perhaps no reg was spilled for this insn | |
5870 | because it was assumed we would find that equivalent. */ | |
5871 | || INSN_UID (p) < reload_first_uid)) | |
5872 | { | |
e8094962 | 5873 | rtx tem; |
eab89b90 RK |
5874 | pat = single_set (p); |
5875 | /* First check for something that sets some reg equal to GOAL. */ | |
5876 | if (pat != 0 | |
5877 | && ((regno >= 0 | |
5878 | && true_regnum (SET_SRC (pat)) == regno | |
5879 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
5880 | || | |
5881 | (regno >= 0 | |
5882 | && true_regnum (SET_DEST (pat)) == regno | |
5883 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0) | |
5884 | || | |
5885 | (goal_const && rtx_equal_p (SET_SRC (pat), goal) | |
5886 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
5887 | || (goal_mem | |
5888 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0 | |
5889 | && rtx_renumbered_equal_p (goal, SET_SRC (pat))) | |
5890 | || (goal_mem | |
5891 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0 | |
e8094962 RK |
5892 | && rtx_renumbered_equal_p (goal, SET_DEST (pat))) |
5893 | /* If we are looking for a constant, | |
5894 | and something equivalent to that constant was copied | |
5895 | into a reg, we can use that reg. */ | |
fb3821f7 CH |
5896 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
5897 | NULL_RTX)) | |
e8094962 | 5898 | && rtx_equal_p (XEXP (tem, 0), goal) |
95d3562b | 5899 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) |
fb3821f7 CH |
5900 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
5901 | NULL_RTX)) | |
e8094962 RK |
5902 | && GET_CODE (SET_DEST (pat)) == REG |
5903 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE | |
5904 | && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT | |
5905 | && GET_CODE (goal) == CONST_INT | |
f55b1d97 RK |
5906 | && 0 != (goaltry = operand_subword (XEXP (tem, 0), 0, 0, |
5907 | VOIDmode)) | |
5908 | && rtx_equal_p (goal, goaltry) | |
e8094962 RK |
5909 | && (valtry = operand_subword (SET_DEST (pat), 0, 0, |
5910 | VOIDmode)) | |
95d3562b | 5911 | && (valueno = true_regnum (valtry)) >= 0) |
fb3821f7 CH |
5912 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
5913 | NULL_RTX)) | |
e8094962 RK |
5914 | && GET_CODE (SET_DEST (pat)) == REG |
5915 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE | |
5916 | && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT | |
5917 | && GET_CODE (goal) == CONST_INT | |
f55b1d97 RK |
5918 | && 0 != (goaltry = operand_subword (XEXP (tem, 0), 1, 0, |
5919 | VOIDmode)) | |
5920 | && rtx_equal_p (goal, goaltry) | |
e8094962 RK |
5921 | && (valtry |
5922 | = operand_subword (SET_DEST (pat), 1, 0, VOIDmode)) | |
95d3562b | 5923 | && (valueno = true_regnum (valtry)) >= 0))) |
eab89b90 RK |
5924 | if (other >= 0 |
5925 | ? valueno == other | |
5926 | : ((unsigned) valueno < FIRST_PSEUDO_REGISTER | |
5927 | && TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
5928 | valueno))) | |
5929 | { | |
5930 | value = valtry; | |
5931 | where = p; | |
5932 | break; | |
5933 | } | |
5934 | } | |
5935 | } | |
5936 | ||
5937 | /* We found a previous insn copying GOAL into a suitable other reg VALUE | |
5938 | (or copying VALUE into GOAL, if GOAL is also a register). | |
5939 | Now verify that VALUE is really valid. */ | |
5940 | ||
5941 | /* VALUENO is the register number of VALUE; a hard register. */ | |
5942 | ||
5943 | /* Don't try to re-use something that is killed in this insn. We want | |
5944 | to be able to trust REG_UNUSED notes. */ | |
5945 | if (find_reg_note (where, REG_UNUSED, value)) | |
5946 | return 0; | |
5947 | ||
5948 | /* If we propose to get the value from the stack pointer or if GOAL is | |
5949 | a MEM based on the stack pointer, we need a stable SP. */ | |
d5a1d1c7 | 5950 | if (valueno == STACK_POINTER_REGNUM || regno == STACK_POINTER_REGNUM |
bfa30b22 RK |
5951 | || (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx, |
5952 | goal))) | |
eab89b90 RK |
5953 | need_stable_sp = 1; |
5954 | ||
5955 | /* Reject VALUE if the copy-insn moved the wrong sort of datum. */ | |
5956 | if (GET_MODE (value) != mode) | |
5957 | return 0; | |
5958 | ||
5959 | /* Reject VALUE if it was loaded from GOAL | |
5960 | and is also a register that appears in the address of GOAL. */ | |
5961 | ||
bd5f6d44 | 5962 | if (goal_mem && value == SET_DEST (single_set (where)) |
bfa30b22 RK |
5963 | && refers_to_regno_for_reload_p (valueno, |
5964 | (valueno | |
5965 | + HARD_REGNO_NREGS (valueno, mode)), | |
fb3821f7 | 5966 | goal, NULL_PTR)) |
eab89b90 RK |
5967 | return 0; |
5968 | ||
5969 | /* Reject registers that overlap GOAL. */ | |
5970 | ||
5971 | if (!goal_mem && !goal_const | |
5972 | && regno + HARD_REGNO_NREGS (regno, mode) > valueno | |
5973 | && regno < valueno + HARD_REGNO_NREGS (valueno, mode)) | |
5974 | return 0; | |
5975 | ||
5976 | /* Reject VALUE if it is one of the regs reserved for reloads. | |
5977 | Reload1 knows how to reuse them anyway, and it would get | |
5978 | confused if we allocated one without its knowledge. | |
5979 | (Now that insns introduced by reload are ignored above, | |
5980 | this case shouldn't happen, but I'm not positive.) */ | |
5981 | ||
a8c9daeb | 5982 | if (reload_reg_p != 0 && reload_reg_p != (short *) (HOST_WIDE_INT) 1 |
eab89b90 RK |
5983 | && reload_reg_p[valueno] >= 0) |
5984 | return 0; | |
5985 | ||
5986 | /* On some machines, certain regs must always be rejected | |
5987 | because they don't behave the way ordinary registers do. */ | |
5988 | ||
5989 | #ifdef OVERLAPPING_REGNO_P | |
5990 | if (OVERLAPPING_REGNO_P (valueno)) | |
5991 | return 0; | |
5992 | #endif | |
5993 | ||
5994 | nregs = HARD_REGNO_NREGS (regno, mode); | |
5995 | valuenregs = HARD_REGNO_NREGS (valueno, mode); | |
5996 | ||
5997 | /* Reject VALUE if it is a register being used for an input reload | |
5998 | even if it is not one of those reserved. */ | |
5999 | ||
6000 | if (reload_reg_p != 0) | |
6001 | { | |
6002 | int i; | |
6003 | for (i = 0; i < n_reloads; i++) | |
6004 | if (reload_reg_rtx[i] != 0 && reload_in[i]) | |
6005 | { | |
6006 | int regno1 = REGNO (reload_reg_rtx[i]); | |
6007 | int nregs1 = HARD_REGNO_NREGS (regno1, | |
6008 | GET_MODE (reload_reg_rtx[i])); | |
6009 | if (regno1 < valueno + valuenregs | |
6010 | && regno1 + nregs1 > valueno) | |
6011 | return 0; | |
6012 | } | |
6013 | } | |
6014 | ||
6015 | if (goal_mem) | |
54b5ffe9 RS |
6016 | /* We must treat frame pointer as varying here, |
6017 | since it can vary--in a nonlocal goto as generated by expand_goto. */ | |
6018 | goal_mem_addr_varies = !CONSTANT_ADDRESS_P (XEXP (goal, 0)); | |
eab89b90 RK |
6019 | |
6020 | /* Now verify that the values of GOAL and VALUE remain unaltered | |
6021 | until INSN is reached. */ | |
6022 | ||
6023 | p = insn; | |
6024 | while (1) | |
6025 | { | |
6026 | p = PREV_INSN (p); | |
6027 | if (p == where) | |
6028 | return value; | |
6029 | ||
6030 | /* Don't trust the conversion past a function call | |
6031 | if either of the two is in a call-clobbered register, or memory. */ | |
6032 | if (GET_CODE (p) == CALL_INSN | |
6033 | && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
6034 | && call_used_regs[regno]) | |
6035 | || | |
6036 | (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER | |
6037 | && call_used_regs[valueno]) | |
6038 | || | |
6039 | goal_mem | |
6040 | || need_stable_sp)) | |
6041 | return 0; | |
6042 | ||
41fe17ab RK |
6043 | #ifdef NON_SAVING_SETJMP |
6044 | if (NON_SAVING_SETJMP && GET_CODE (p) == NOTE | |
6045 | && NOTE_LINE_NUMBER (p) == NOTE_INSN_SETJMP) | |
6046 | return 0; | |
6047 | #endif | |
6048 | ||
eab89b90 RK |
6049 | #ifdef INSN_CLOBBERS_REGNO_P |
6050 | if ((valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER | |
6051 | && INSN_CLOBBERS_REGNO_P (p, valueno)) | |
6052 | || (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
6053 | && INSN_CLOBBERS_REGNO_P (p, regno))) | |
6054 | return 0; | |
6055 | #endif | |
6056 | ||
6057 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
6058 | { | |
6059 | /* If this insn P stores in either GOAL or VALUE, return 0. | |
6060 | If GOAL is a memory ref and this insn writes memory, return 0. | |
6061 | If GOAL is a memory ref and its address is not constant, | |
6062 | and this insn P changes a register used in GOAL, return 0. */ | |
6063 | ||
6064 | pat = PATTERN (p); | |
6065 | if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER) | |
6066 | { | |
6067 | register rtx dest = SET_DEST (pat); | |
6068 | while (GET_CODE (dest) == SUBREG | |
6069 | || GET_CODE (dest) == ZERO_EXTRACT | |
6070 | || GET_CODE (dest) == SIGN_EXTRACT | |
6071 | || GET_CODE (dest) == STRICT_LOW_PART) | |
6072 | dest = XEXP (dest, 0); | |
6073 | if (GET_CODE (dest) == REG) | |
6074 | { | |
6075 | register int xregno = REGNO (dest); | |
6076 | int xnregs; | |
6077 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
6078 | xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); | |
6079 | else | |
6080 | xnregs = 1; | |
6081 | if (xregno < regno + nregs && xregno + xnregs > regno) | |
6082 | return 0; | |
6083 | if (xregno < valueno + valuenregs | |
6084 | && xregno + xnregs > valueno) | |
6085 | return 0; | |
6086 | if (goal_mem_addr_varies | |
bfa30b22 | 6087 | && reg_overlap_mentioned_for_reload_p (dest, goal)) |
eab89b90 RK |
6088 | return 0; |
6089 | } | |
6090 | else if (goal_mem && GET_CODE (dest) == MEM | |
6091 | && ! push_operand (dest, GET_MODE (dest))) | |
6092 | return 0; | |
9fac9680 RK |
6093 | else if (GET_CODE (dest) == MEM && regno >= FIRST_PSEUDO_REGISTER |
6094 | && reg_equiv_memory_loc[regno] != 0) | |
6095 | return 0; | |
eab89b90 RK |
6096 | else if (need_stable_sp && push_operand (dest, GET_MODE (dest))) |
6097 | return 0; | |
6098 | } | |
6099 | else if (GET_CODE (pat) == PARALLEL) | |
6100 | { | |
6101 | register int i; | |
6102 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) | |
6103 | { | |
6104 | register rtx v1 = XVECEXP (pat, 0, i); | |
6105 | if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER) | |
6106 | { | |
6107 | register rtx dest = SET_DEST (v1); | |
6108 | while (GET_CODE (dest) == SUBREG | |
6109 | || GET_CODE (dest) == ZERO_EXTRACT | |
6110 | || GET_CODE (dest) == SIGN_EXTRACT | |
6111 | || GET_CODE (dest) == STRICT_LOW_PART) | |
6112 | dest = XEXP (dest, 0); | |
6113 | if (GET_CODE (dest) == REG) | |
6114 | { | |
6115 | register int xregno = REGNO (dest); | |
6116 | int xnregs; | |
6117 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
6118 | xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); | |
6119 | else | |
6120 | xnregs = 1; | |
6121 | if (xregno < regno + nregs | |
6122 | && xregno + xnregs > regno) | |
6123 | return 0; | |
6124 | if (xregno < valueno + valuenregs | |
6125 | && xregno + xnregs > valueno) | |
6126 | return 0; | |
6127 | if (goal_mem_addr_varies | |
bfa30b22 RK |
6128 | && reg_overlap_mentioned_for_reload_p (dest, |
6129 | goal)) | |
eab89b90 RK |
6130 | return 0; |
6131 | } | |
6132 | else if (goal_mem && GET_CODE (dest) == MEM | |
6133 | && ! push_operand (dest, GET_MODE (dest))) | |
6134 | return 0; | |
e9a25f70 JL |
6135 | else if (GET_CODE (dest) == MEM && regno >= FIRST_PSEUDO_REGISTER |
6136 | && reg_equiv_memory_loc[regno] != 0) | |
6137 | return 0; | |
369c7ab6 JW |
6138 | else if (need_stable_sp |
6139 | && push_operand (dest, GET_MODE (dest))) | |
6140 | return 0; | |
6141 | } | |
6142 | } | |
6143 | } | |
6144 | ||
6145 | if (GET_CODE (p) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (p)) | |
6146 | { | |
6147 | rtx link; | |
6148 | ||
6149 | for (link = CALL_INSN_FUNCTION_USAGE (p); XEXP (link, 1) != 0; | |
6150 | link = XEXP (link, 1)) | |
6151 | { | |
6152 | pat = XEXP (link, 0); | |
6153 | if (GET_CODE (pat) == CLOBBER) | |
6154 | { | |
6155 | register rtx dest = SET_DEST (pat); | |
6156 | while (GET_CODE (dest) == SUBREG | |
6157 | || GET_CODE (dest) == ZERO_EXTRACT | |
6158 | || GET_CODE (dest) == SIGN_EXTRACT | |
6159 | || GET_CODE (dest) == STRICT_LOW_PART) | |
6160 | dest = XEXP (dest, 0); | |
6161 | if (GET_CODE (dest) == REG) | |
6162 | { | |
6163 | register int xregno = REGNO (dest); | |
6164 | int xnregs; | |
6165 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
6166 | xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); | |
6167 | else | |
6168 | xnregs = 1; | |
6169 | if (xregno < regno + nregs | |
6170 | && xregno + xnregs > regno) | |
6171 | return 0; | |
6172 | if (xregno < valueno + valuenregs | |
6173 | && xregno + xnregs > valueno) | |
6174 | return 0; | |
6175 | if (goal_mem_addr_varies | |
6176 | && reg_overlap_mentioned_for_reload_p (dest, | |
6177 | goal)) | |
6178 | return 0; | |
6179 | } | |
6180 | else if (goal_mem && GET_CODE (dest) == MEM | |
6181 | && ! push_operand (dest, GET_MODE (dest))) | |
6182 | return 0; | |
eab89b90 RK |
6183 | else if (need_stable_sp |
6184 | && push_operand (dest, GET_MODE (dest))) | |
6185 | return 0; | |
6186 | } | |
6187 | } | |
6188 | } | |
6189 | ||
6190 | #ifdef AUTO_INC_DEC | |
6191 | /* If this insn auto-increments or auto-decrements | |
6192 | either regno or valueno, return 0 now. | |
6193 | If GOAL is a memory ref and its address is not constant, | |
6194 | and this insn P increments a register used in GOAL, return 0. */ | |
6195 | { | |
6196 | register rtx link; | |
6197 | ||
6198 | for (link = REG_NOTES (p); link; link = XEXP (link, 1)) | |
6199 | if (REG_NOTE_KIND (link) == REG_INC | |
6200 | && GET_CODE (XEXP (link, 0)) == REG) | |
6201 | { | |
6202 | register int incno = REGNO (XEXP (link, 0)); | |
6203 | if (incno < regno + nregs && incno >= regno) | |
6204 | return 0; | |
6205 | if (incno < valueno + valuenregs && incno >= valueno) | |
6206 | return 0; | |
6207 | if (goal_mem_addr_varies | |
bfa30b22 RK |
6208 | && reg_overlap_mentioned_for_reload_p (XEXP (link, 0), |
6209 | goal)) | |
eab89b90 RK |
6210 | return 0; |
6211 | } | |
6212 | } | |
6213 | #endif | |
6214 | } | |
6215 | } | |
6216 | } | |
6217 | \f | |
6218 | /* Find a place where INCED appears in an increment or decrement operator | |
6219 | within X, and return the amount INCED is incremented or decremented by. | |
6220 | The value is always positive. */ | |
6221 | ||
6222 | static int | |
6223 | find_inc_amount (x, inced) | |
6224 | rtx x, inced; | |
6225 | { | |
6226 | register enum rtx_code code = GET_CODE (x); | |
6227 | register char *fmt; | |
6228 | register int i; | |
6229 | ||
6230 | if (code == MEM) | |
6231 | { | |
6232 | register rtx addr = XEXP (x, 0); | |
6233 | if ((GET_CODE (addr) == PRE_DEC | |
6234 | || GET_CODE (addr) == POST_DEC | |
6235 | || GET_CODE (addr) == PRE_INC | |
6236 | || GET_CODE (addr) == POST_INC) | |
6237 | && XEXP (addr, 0) == inced) | |
6238 | return GET_MODE_SIZE (GET_MODE (x)); | |
6239 | } | |
6240 | ||
6241 | fmt = GET_RTX_FORMAT (code); | |
6242 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6243 | { | |
6244 | if (fmt[i] == 'e') | |
6245 | { | |
6246 | register int tem = find_inc_amount (XEXP (x, i), inced); | |
6247 | if (tem != 0) | |
6248 | return tem; | |
6249 | } | |
6250 | if (fmt[i] == 'E') | |
6251 | { | |
6252 | register int j; | |
6253 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
6254 | { | |
6255 | register int tem = find_inc_amount (XVECEXP (x, i, j), inced); | |
6256 | if (tem != 0) | |
6257 | return tem; | |
6258 | } | |
6259 | } | |
6260 | } | |
6261 | ||
6262 | return 0; | |
6263 | } | |
6264 | \f | |
6265 | /* Return 1 if register REGNO is the subject of a clobber in insn INSN. */ | |
6266 | ||
6267 | int | |
6268 | regno_clobbered_p (regno, insn) | |
6269 | int regno; | |
6270 | rtx insn; | |
6271 | { | |
6272 | if (GET_CODE (PATTERN (insn)) == CLOBBER | |
6273 | && GET_CODE (XEXP (PATTERN (insn), 0)) == REG) | |
6274 | return REGNO (XEXP (PATTERN (insn), 0)) == regno; | |
6275 | ||
6276 | if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
6277 | { | |
6278 | int i = XVECLEN (PATTERN (insn), 0) - 1; | |
6279 | ||
6280 | for (; i >= 0; i--) | |
6281 | { | |
6282 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
6283 | if (GET_CODE (elt) == CLOBBER && GET_CODE (XEXP (elt, 0)) == REG | |
6284 | && REGNO (XEXP (elt, 0)) == regno) | |
6285 | return 1; | |
6286 | } | |
6287 | } | |
6288 | ||
6289 | return 0; | |
6290 | } | |
10bcde0d RK |
6291 | |
6292 | static char *reload_when_needed_name[] = | |
6293 | { | |
6294 | "RELOAD_FOR_INPUT", | |
6295 | "RELOAD_FOR_OUTPUT", | |
6296 | "RELOAD_FOR_INSN", | |
47c8cf91 ILT |
6297 | "RELOAD_FOR_INPUT_ADDRESS", |
6298 | "RELOAD_FOR_INPADDR_ADDRESS", | |
10bcde0d | 6299 | "RELOAD_FOR_OUTPUT_ADDRESS", |
47c8cf91 | 6300 | "RELOAD_FOR_OUTADDR_ADDRESS", |
10bcde0d RK |
6301 | "RELOAD_FOR_OPERAND_ADDRESS", |
6302 | "RELOAD_FOR_OPADDR_ADDR", | |
6303 | "RELOAD_OTHER", | |
6304 | "RELOAD_FOR_OTHER_ADDRESS" | |
6305 | }; | |
6306 | ||
6307 | static char *reg_class_names[] = REG_CLASS_NAMES; | |
6308 | ||
b8fb2d72 | 6309 | /* These functions are used to print the variables set by 'find_reloads' */ |
10bcde0d RK |
6310 | |
6311 | void | |
b8fb2d72 CI |
6312 | debug_reload_to_stream (f) |
6313 | FILE *f; | |
10bcde0d RK |
6314 | { |
6315 | int r; | |
505923a0 | 6316 | char *prefix; |
10bcde0d | 6317 | |
b8fb2d72 CI |
6318 | if (! f) |
6319 | f = stderr; | |
10bcde0d RK |
6320 | for (r = 0; r < n_reloads; r++) |
6321 | { | |
b8fb2d72 | 6322 | fprintf (f, "Reload %d: ", r); |
10bcde0d | 6323 | |
505923a0 | 6324 | if (reload_in[r] != 0) |
10bcde0d | 6325 | { |
b8fb2d72 | 6326 | fprintf (f, "reload_in (%s) = ", |
f7393e85 | 6327 | GET_MODE_NAME (reload_inmode[r])); |
b8fb2d72 CI |
6328 | print_inline_rtx (f, reload_in[r], 24); |
6329 | fprintf (f, "\n\t"); | |
10bcde0d RK |
6330 | } |
6331 | ||
505923a0 | 6332 | if (reload_out[r] != 0) |
10bcde0d | 6333 | { |
b8fb2d72 | 6334 | fprintf (f, "reload_out (%s) = ", |
f7393e85 | 6335 | GET_MODE_NAME (reload_outmode[r])); |
b8fb2d72 CI |
6336 | print_inline_rtx (f, reload_out[r], 24); |
6337 | fprintf (f, "\n\t"); | |
10bcde0d RK |
6338 | } |
6339 | ||
b8fb2d72 | 6340 | fprintf (f, "%s, ", reg_class_names[(int) reload_reg_class[r]]); |
10bcde0d | 6341 | |
b8fb2d72 | 6342 | fprintf (f, "%s (opnum = %d)", |
505923a0 | 6343 | reload_when_needed_name[(int) reload_when_needed[r]], |
10bcde0d RK |
6344 | reload_opnum[r]); |
6345 | ||
6346 | if (reload_optional[r]) | |
b8fb2d72 | 6347 | fprintf (f, ", optional"); |
10bcde0d | 6348 | |
f5963e61 JL |
6349 | if (reload_nongroup[r]) |
6350 | fprintf (stderr, ", nongroup"); | |
6351 | ||
505923a0 | 6352 | if (reload_inc[r] != 0) |
b8fb2d72 | 6353 | fprintf (f, ", inc by %d", reload_inc[r]); |
10bcde0d RK |
6354 | |
6355 | if (reload_nocombine[r]) | |
b8fb2d72 | 6356 | fprintf (f, ", can't combine"); |
10bcde0d RK |
6357 | |
6358 | if (reload_secondary_p[r]) | |
b8fb2d72 | 6359 | fprintf (f, ", secondary_reload_p"); |
10bcde0d | 6360 | |
505923a0 | 6361 | if (reload_in_reg[r] != 0) |
10bcde0d | 6362 | { |
b8fb2d72 CI |
6363 | fprintf (f, "\n\treload_in_reg: "); |
6364 | print_inline_rtx (f, reload_in_reg[r], 24); | |
10bcde0d RK |
6365 | } |
6366 | ||
505923a0 | 6367 | if (reload_reg_rtx[r] != 0) |
10bcde0d | 6368 | { |
b8fb2d72 CI |
6369 | fprintf (f, "\n\treload_reg_rtx: "); |
6370 | print_inline_rtx (f, reload_reg_rtx[r], 24); | |
10bcde0d RK |
6371 | } |
6372 | ||
505923a0 | 6373 | prefix = "\n\t"; |
10bcde0d RK |
6374 | if (reload_secondary_in_reload[r] != -1) |
6375 | { | |
b8fb2d72 | 6376 | fprintf (f, "%ssecondary_in_reload = %d", |
505923a0 RK |
6377 | prefix, reload_secondary_in_reload[r]); |
6378 | prefix = ", "; | |
10bcde0d RK |
6379 | } |
6380 | ||
6381 | if (reload_secondary_out_reload[r] != -1) | |
b8fb2d72 | 6382 | fprintf (f, "%ssecondary_out_reload = %d\n", |
505923a0 | 6383 | prefix, reload_secondary_out_reload[r]); |
10bcde0d | 6384 | |
505923a0 | 6385 | prefix = "\n\t"; |
10bcde0d RK |
6386 | if (reload_secondary_in_icode[r] != CODE_FOR_nothing) |
6387 | { | |
e5e809f4 JL |
6388 | fprintf (stderr, "%ssecondary_in_icode = %s", prefix, |
6389 | insn_name[reload_secondary_in_icode[r]]); | |
505923a0 | 6390 | prefix = ", "; |
10bcde0d RK |
6391 | } |
6392 | ||
6393 | if (reload_secondary_out_icode[r] != CODE_FOR_nothing) | |
e5e809f4 JL |
6394 | fprintf (stderr, "%ssecondary_out_icode = %s", prefix, |
6395 | insn_name[reload_secondary_out_icode[r]]); | |
10bcde0d | 6396 | |
b8fb2d72 | 6397 | fprintf (f, "\n"); |
10bcde0d | 6398 | } |
10bcde0d | 6399 | } |
b8fb2d72 CI |
6400 | |
6401 | void | |
6402 | debug_reload () | |
6403 | { | |
6404 | debug_reload_to_stream (stderr); | |
6405 | } |