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Commit | Line | Data |
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eab89b90 | 1 | /* Search an insn for pseudo regs that must be in hard regs and are not. |
af841dbd | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
66647d44 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
6fb5fa3c | 4 | Free Software Foundation, Inc. |
eab89b90 | 5 | |
1322177d | 6 | This file is part of GCC. |
eab89b90 | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
eab89b90 | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
eab89b90 RK |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
eab89b90 | 21 | |
eab89b90 RK |
22 | /* This file contains subroutines used only from the file reload1.c. |
23 | It knows how to scan one insn for operands and values | |
24 | that need to be copied into registers to make valid code. | |
25 | It also finds other operands and values which are valid | |
26 | but for which equivalent values in registers exist and | |
27 | ought to be used instead. | |
28 | ||
29 | Before processing the first insn of the function, call `init_reload'. | |
965ccc5a | 30 | init_reload actually has to be called earlier anyway. |
eab89b90 RK |
31 | |
32 | To scan an insn, call `find_reloads'. This does two things: | |
33 | 1. sets up tables describing which values must be reloaded | |
34 | for this insn, and what kind of hard regs they must be reloaded into; | |
35 | 2. optionally record the locations where those values appear in | |
36 | the data, so they can be replaced properly later. | |
37 | This is done only if the second arg to `find_reloads' is nonzero. | |
38 | ||
39 | The third arg to `find_reloads' specifies the number of levels | |
40 | of indirect addressing supported by the machine. If it is zero, | |
41 | indirect addressing is not valid. If it is one, (MEM (REG n)) | |
42 | is valid even if (REG n) did not get a hard register; if it is two, | |
43 | (MEM (MEM (REG n))) is also valid even if (REG n) did not get a | |
44 | hard register, and similarly for higher values. | |
45 | ||
46 | Then you must choose the hard regs to reload those pseudo regs into, | |
47 | and generate appropriate load insns before this insn and perhaps | |
48 | also store insns after this insn. Set up the array `reload_reg_rtx' | |
49 | to contain the REG rtx's for the registers you used. In some | |
50 | cases `find_reloads' will return a nonzero value in `reload_reg_rtx' | |
51 | for certain reloads. Then that tells you which register to use, | |
52 | so you do not need to allocate one. But you still do need to add extra | |
53 | instructions to copy the value into and out of that register. | |
54 | ||
55 | Finally you must call `subst_reloads' to substitute the reload reg rtx's | |
56 | into the locations already recorded. | |
57 | ||
58 | NOTE SIDE EFFECTS: | |
59 | ||
60 | find_reloads can alter the operands of the instruction it is called on. | |
61 | ||
62 | 1. Two operands of any sort may be interchanged, if they are in a | |
63 | commutative instruction. | |
64 | This happens only if find_reloads thinks the instruction will compile | |
65 | better that way. | |
66 | ||
67 | 2. Pseudo-registers that are equivalent to constants are replaced | |
68 | with those constants if they are not in hard registers. | |
69 | ||
70 | 1 happens every time find_reloads is called. | |
71 | 2 happens only when REPLACE is 1, which is only when | |
72 | actually doing the reloads, not when just counting them. | |
73 | ||
eab89b90 RK |
74 | Using a reload register for several reloads in one insn: |
75 | ||
76 | When an insn has reloads, it is considered as having three parts: | |
77 | the input reloads, the insn itself after reloading, and the output reloads. | |
78 | Reloads of values used in memory addresses are often needed for only one part. | |
79 | ||
80 | When this is so, reload_when_needed records which part needs the reload. | |
81 | Two reloads for different parts of the insn can share the same reload | |
82 | register. | |
83 | ||
84 | When a reload is used for addresses in multiple parts, or when it is | |
85 | an ordinary operand, it is classified as RELOAD_OTHER, and cannot share | |
86 | a register with any other reload. */ | |
87 | ||
88 | #define REG_OK_STRICT | |
89 | ||
0fa4cb7d SE |
90 | /* We do not enable this with ENABLE_CHECKING, since it is awfully slow. */ |
91 | #undef DEBUG_RELOAD | |
92 | ||
eab89b90 | 93 | #include "config.h" |
670ee920 | 94 | #include "system.h" |
4977bab6 ZW |
95 | #include "coretypes.h" |
96 | #include "tm.h" | |
eab89b90 | 97 | #include "rtl.h" |
6baf1cc8 | 98 | #include "tm_p.h" |
eab89b90 | 99 | #include "insn-config.h" |
e78d8e51 ZW |
100 | #include "expr.h" |
101 | #include "optabs.h" | |
eab89b90 RK |
102 | #include "recog.h" |
103 | #include "reload.h" | |
104 | #include "regs.h" | |
c4963a0a | 105 | #include "addresses.h" |
eab89b90 RK |
106 | #include "hard-reg-set.h" |
107 | #include "flags.h" | |
108 | #include "real.h" | |
8a840ac9 | 109 | #include "output.h" |
49ad7cfa | 110 | #include "function.h" |
10f0ad3d | 111 | #include "toplev.h" |
0bcf8261 | 112 | #include "params.h" |
34208acf | 113 | #include "target.h" |
6fb5fa3c | 114 | #include "df.h" |
eab89b90 | 115 | |
34208acf AO |
116 | /* True if X is a constant that can be forced into the constant pool. */ |
117 | #define CONST_POOL_OK_P(X) \ | |
118 | (CONSTANT_P (X) \ | |
119 | && GET_CODE (X) != HIGH \ | |
120 | && !targetm.cannot_force_const_mem (X)) | |
e9840398 AO |
121 | |
122 | /* True if C is a non-empty register class that has too few registers | |
123 | to be safely used as a reload target class. */ | |
124 | #define SMALL_REGISTER_CLASS_P(C) \ | |
125 | (reg_class_size [(C)] == 1 \ | |
126 | || (reg_class_size [(C)] >= 1 && CLASS_LIKELY_SPILLED_P (C))) | |
127 | ||
eab89b90 | 128 | \f |
eceef4c9 BS |
129 | /* All reloads of the current insn are recorded here. See reload.h for |
130 | comments. */ | |
eab89b90 | 131 | int n_reloads; |
eceef4c9 | 132 | struct reload rld[MAX_RELOADS]; |
eab89b90 RK |
133 | |
134 | /* All the "earlyclobber" operands of the current insn | |
135 | are recorded here. */ | |
136 | int n_earlyclobbers; | |
137 | rtx reload_earlyclobbers[MAX_RECOG_OPERANDS]; | |
138 | ||
a8c9daeb RK |
139 | int reload_n_operands; |
140 | ||
eab89b90 RK |
141 | /* Replacing reloads. |
142 | ||
143 | If `replace_reloads' is nonzero, then as each reload is recorded | |
144 | an entry is made for it in the table `replacements'. | |
145 | Then later `subst_reloads' can look through that table and | |
146 | perform all the replacements needed. */ | |
147 | ||
148 | /* Nonzero means record the places to replace. */ | |
149 | static int replace_reloads; | |
150 | ||
151 | /* Each replacement is recorded with a structure like this. */ | |
152 | struct replacement | |
153 | { | |
154 | rtx *where; /* Location to store in */ | |
155 | rtx *subreg_loc; /* Location of SUBREG if WHERE is inside | |
156 | a SUBREG; 0 otherwise. */ | |
157 | int what; /* which reload this is for */ | |
158 | enum machine_mode mode; /* mode it must have */ | |
159 | }; | |
160 | ||
161 | static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; | |
162 | ||
163 | /* Number of replacements currently recorded. */ | |
164 | static int n_replacements; | |
165 | ||
a8c9daeb RK |
166 | /* Used to track what is modified by an operand. */ |
167 | struct decomposition | |
168 | { | |
0f41302f MS |
169 | int reg_flag; /* Nonzero if referencing a register. */ |
170 | int safe; /* Nonzero if this can't conflict with anything. */ | |
171 | rtx base; /* Base address for MEM. */ | |
172 | HOST_WIDE_INT start; /* Starting offset or register number. */ | |
2a6d5ce0 | 173 | HOST_WIDE_INT end; /* Ending offset or register number. */ |
a8c9daeb RK |
174 | }; |
175 | ||
0dadecf6 RK |
176 | #ifdef SECONDARY_MEMORY_NEEDED |
177 | ||
178 | /* Save MEMs needed to copy from one class of registers to another. One MEM | |
05d10675 | 179 | is used per mode, but normally only one or two modes are ever used. |
0dadecf6 | 180 | |
05d10675 | 181 | We keep two versions, before and after register elimination. The one |
a8c9daeb RK |
182 | after register elimination is record separately for each operand. This |
183 | is done in case the address is not valid to be sure that we separately | |
184 | reload each. */ | |
0dadecf6 RK |
185 | |
186 | static rtx secondary_memlocs[NUM_MACHINE_MODES]; | |
77545d45 | 187 | static rtx secondary_memlocs_elim[NUM_MACHINE_MODES][MAX_RECOG_OPERANDS]; |
048b0d2e | 188 | static int secondary_memlocs_elim_used = 0; |
0dadecf6 RK |
189 | #endif |
190 | ||
eab89b90 RK |
191 | /* The instruction we are doing reloads for; |
192 | so we can test whether a register dies in it. */ | |
193 | static rtx this_insn; | |
194 | ||
195 | /* Nonzero if this instruction is a user-specified asm with operands. */ | |
196 | static int this_insn_is_asm; | |
197 | ||
198 | /* If hard_regs_live_known is nonzero, | |
199 | we can tell which hard regs are currently live, | |
200 | at least enough to succeed in choosing dummy reloads. */ | |
201 | static int hard_regs_live_known; | |
202 | ||
203 | /* Indexed by hard reg number, | |
956d6950 | 204 | element is nonnegative if hard reg has been spilled. |
eab89b90 RK |
205 | This vector is passed to `find_reloads' as an argument |
206 | and is not changed here. */ | |
207 | static short *static_reload_reg_p; | |
208 | ||
209 | /* Set to 1 in subst_reg_equivs if it changes anything. */ | |
210 | static int subst_reg_equivs_changed; | |
211 | ||
212 | /* On return from push_reload, holds the reload-number for the OUT | |
213 | operand, which can be different for that from the input operand. */ | |
214 | static int output_reloadnum; | |
215 | ||
9ec7078b RK |
216 | /* Compare two RTX's. */ |
217 | #define MATCHES(x, y) \ | |
f8cfc6aa JQ |
218 | (x == y || (x != 0 && (REG_P (x) \ |
219 | ? REG_P (y) && REGNO (x) == REGNO (y) \ | |
9ec7078b RK |
220 | : rtx_equal_p (x, y) && ! side_effects_p (x)))) |
221 | ||
222 | /* Indicates if two reloads purposes are for similar enough things that we | |
223 | can merge their reloads. */ | |
224 | #define MERGABLE_RELOADS(when1, when2, op1, op2) \ | |
225 | ((when1) == RELOAD_OTHER || (when2) == RELOAD_OTHER \ | |
226 | || ((when1) == (when2) && (op1) == (op2)) \ | |
227 | || ((when1) == RELOAD_FOR_INPUT && (when2) == RELOAD_FOR_INPUT) \ | |
228 | || ((when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
229 | && (when2) == RELOAD_FOR_OPERAND_ADDRESS) \ | |
230 | || ((when1) == RELOAD_FOR_OTHER_ADDRESS \ | |
231 | && (when2) == RELOAD_FOR_OTHER_ADDRESS)) | |
232 | ||
233 | /* Nonzero if these two reload purposes produce RELOAD_OTHER when merged. */ | |
234 | #define MERGE_TO_OTHER(when1, when2, op1, op2) \ | |
235 | ((when1) != (when2) \ | |
236 | || ! ((op1) == (op2) \ | |
237 | || (when1) == RELOAD_FOR_INPUT \ | |
238 | || (when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
239 | || (when1) == RELOAD_FOR_OTHER_ADDRESS)) | |
240 | ||
47c8cf91 ILT |
241 | /* If we are going to reload an address, compute the reload type to |
242 | use. */ | |
243 | #define ADDR_TYPE(type) \ | |
244 | ((type) == RELOAD_FOR_INPUT_ADDRESS \ | |
245 | ? RELOAD_FOR_INPADDR_ADDRESS \ | |
246 | : ((type) == RELOAD_FOR_OUTPUT_ADDRESS \ | |
247 | ? RELOAD_FOR_OUTADDR_ADDRESS \ | |
248 | : (type))) | |
249 | ||
0c20a65f AJ |
250 | static int push_secondary_reload (int, rtx, int, int, enum reg_class, |
251 | enum machine_mode, enum reload_type, | |
8a99f6f9 | 252 | enum insn_code *, secondary_reload_info *); |
e11ab33b DD |
253 | static enum reg_class find_valid_class (enum machine_mode, enum machine_mode, |
254 | int, unsigned int); | |
0c20a65f AJ |
255 | static int reload_inner_reg_of_subreg (rtx, enum machine_mode, int); |
256 | static void push_replacement (rtx *, int, enum machine_mode); | |
257 | static void dup_replacements (rtx *, rtx *); | |
258 | static void combine_reloads (void); | |
259 | static int find_reusable_reload (rtx *, rtx, enum reg_class, | |
260 | enum reload_type, int, int); | |
261 | static rtx find_dummy_reload (rtx, rtx, rtx *, rtx *, enum machine_mode, | |
262 | enum machine_mode, enum reg_class, int, int); | |
263 | static int hard_reg_set_here_p (unsigned int, unsigned int, rtx); | |
264 | static struct decomposition decompose (rtx); | |
265 | static int immune_p (rtx, rtx, struct decomposition); | |
1f7f6676 | 266 | static bool alternative_allows_const_pool_ref (rtx, const char *, int); |
0c20a65f AJ |
267 | static rtx find_reloads_toplev (rtx, int, enum reload_type, int, int, rtx, |
268 | int *); | |
269 | static rtx make_memloc (rtx, int); | |
270 | static int maybe_memory_address_p (enum machine_mode, rtx, rtx *); | |
271 | static int find_reloads_address (enum machine_mode, rtx *, rtx, rtx *, | |
272 | int, enum reload_type, int, rtx); | |
273 | static rtx subst_reg_equivs (rtx, rtx); | |
274 | static rtx subst_indexed_address (rtx); | |
275 | static void update_auto_inc_notes (rtx, int, int); | |
c4963a0a BS |
276 | static int find_reloads_address_1 (enum machine_mode, rtx, int, |
277 | enum rtx_code, enum rtx_code, rtx *, | |
0c20a65f AJ |
278 | int, enum reload_type,int, rtx); |
279 | static void find_reloads_address_part (rtx, rtx *, enum reg_class, | |
280 | enum machine_mode, int, | |
281 | enum reload_type, int); | |
282 | static rtx find_reloads_subreg_address (rtx, int, int, enum reload_type, | |
283 | int, rtx); | |
284 | static void copy_replacements_1 (rtx *, rtx *, int); | |
285 | static int find_inc_amount (rtx, rtx); | |
10015a27 KH |
286 | static int refers_to_mem_for_reload_p (rtx); |
287 | static int refers_to_regno_for_reload_p (unsigned int, unsigned int, | |
288 | rtx, rtx *); | |
3f1e3e70 AO |
289 | |
290 | /* Add NEW to reg_equiv_alt_mem_list[REGNO] if it's not present in the | |
291 | list yet. */ | |
292 | ||
293 | static void | |
294 | push_reg_equiv_alt_mem (int regno, rtx mem) | |
295 | { | |
296 | rtx it; | |
297 | ||
298 | for (it = reg_equiv_alt_mem_list [regno]; it; it = XEXP (it, 1)) | |
299 | if (rtx_equal_p (XEXP (it, 0), mem)) | |
300 | return; | |
301 | ||
302 | reg_equiv_alt_mem_list [regno] | |
303 | = alloc_EXPR_LIST (REG_EQUIV, mem, | |
304 | reg_equiv_alt_mem_list [regno]); | |
305 | } | |
eab89b90 | 306 | \f |
eab89b90 | 307 | /* Determine if any secondary reloads are needed for loading (if IN_P is |
40f03658 | 308 | nonzero) or storing (if IN_P is zero) X to or from a reload register of |
9ec7078b RK |
309 | register class RELOAD_CLASS in mode RELOAD_MODE. If secondary reloads |
310 | are needed, push them. | |
311 | ||
312 | Return the reload number of the secondary reload we made, or -1 if | |
313 | we didn't need one. *PICODE is set to the insn_code to use if we do | |
314 | need a secondary reload. */ | |
315 | ||
316 | static int | |
0c20a65f AJ |
317 | push_secondary_reload (int in_p, rtx x, int opnum, int optional, |
318 | enum reg_class reload_class, | |
319 | enum machine_mode reload_mode, enum reload_type type, | |
8a99f6f9 | 320 | enum insn_code *picode, secondary_reload_info *prev_sri) |
eab89b90 | 321 | { |
55d796da | 322 | enum reg_class rclass = NO_REGS; |
8a99f6f9 | 323 | enum reg_class scratch_class; |
eab89b90 RK |
324 | enum machine_mode mode = reload_mode; |
325 | enum insn_code icode = CODE_FOR_nothing; | |
65b4c337 | 326 | enum insn_code t_icode = CODE_FOR_nothing; |
d94d2abc | 327 | enum reload_type secondary_type; |
9ec7078b | 328 | int s_reload, t_reload = -1; |
8a99f6f9 R |
329 | const char *scratch_constraint; |
330 | char letter; | |
331 | secondary_reload_info sri; | |
9ec7078b | 332 | |
47c8cf91 ILT |
333 | if (type == RELOAD_FOR_INPUT_ADDRESS |
334 | || type == RELOAD_FOR_OUTPUT_ADDRESS | |
335 | || type == RELOAD_FOR_INPADDR_ADDRESS | |
336 | || type == RELOAD_FOR_OUTADDR_ADDRESS) | |
d94d2abc RK |
337 | secondary_type = type; |
338 | else | |
339 | secondary_type = in_p ? RELOAD_FOR_INPUT_ADDRESS : RELOAD_FOR_OUTPUT_ADDRESS; | |
340 | ||
9ec7078b | 341 | *picode = CODE_FOR_nothing; |
eab89b90 | 342 | |
67340b03 RK |
343 | /* If X is a paradoxical SUBREG, use the inner value to determine both the |
344 | mode and object being reloaded. */ | |
345 | if (GET_CODE (x) == SUBREG | |
346 | && (GET_MODE_SIZE (GET_MODE (x)) | |
347 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
348 | { | |
349 | x = SUBREG_REG (x); | |
350 | reload_mode = GET_MODE (x); | |
351 | } | |
352 | ||
d45cf215 RS |
353 | /* If X is a pseudo-register that has an equivalent MEM (actually, if it |
354 | is still a pseudo-register by now, it *must* have an equivalent MEM | |
355 | but we don't want to assume that), use that equivalent when seeing if | |
356 | a secondary reload is needed since whether or not a reload is needed | |
357 | might be sensitive to the form of the MEM. */ | |
358 | ||
f8cfc6aa | 359 | if (REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER |
d45cf215 RS |
360 | && reg_equiv_mem[REGNO (x)] != 0) |
361 | x = reg_equiv_mem[REGNO (x)]; | |
362 | ||
8a99f6f9 R |
363 | sri.icode = CODE_FOR_nothing; |
364 | sri.prev_sri = prev_sri; | |
55d796da | 365 | rclass = targetm.secondary_reload (in_p, x, reload_class, reload_mode, &sri); |
32e8bb8e | 366 | icode = (enum insn_code) sri.icode; |
eab89b90 | 367 | |
9ec7078b | 368 | /* If we don't need any secondary registers, done. */ |
55d796da | 369 | if (rclass == NO_REGS && icode == CODE_FOR_nothing) |
9ec7078b | 370 | return -1; |
eab89b90 | 371 | |
55d796da KG |
372 | if (rclass != NO_REGS) |
373 | t_reload = push_secondary_reload (in_p, x, opnum, optional, rclass, | |
8a99f6f9 | 374 | reload_mode, type, &t_icode, &sri); |
eab89b90 | 375 | |
8a99f6f9 R |
376 | /* If we will be using an insn, the secondary reload is for a |
377 | scratch register. */ | |
eab89b90 RK |
378 | |
379 | if (icode != CODE_FOR_nothing) | |
380 | { | |
40f03658 | 381 | /* If IN_P is nonzero, the reload register will be the output in |
eab89b90 RK |
382 | operand 0. If IN_P is zero, the reload register will be the input |
383 | in operand 1. Outputs should have an initial "=", which we must | |
384 | skip. */ | |
385 | ||
8a99f6f9 R |
386 | /* ??? It would be useful to be able to handle only two, or more than |
387 | three, operands, but for now we can only handle the case of having | |
388 | exactly three: output, input and one temp/scratch. */ | |
389 | gcc_assert (insn_data[(int) icode].n_operands == 3); | |
390 | ||
391 | /* ??? We currently have no way to represent a reload that needs | |
6416ae7f | 392 | an icode to reload from an intermediate tertiary reload register. |
8a99f6f9 R |
393 | We should probably have a new field in struct reload to tag a |
394 | chain of scratch operand reloads onto. */ | |
55d796da | 395 | gcc_assert (rclass == NO_REGS); |
8a99f6f9 R |
396 | |
397 | scratch_constraint = insn_data[(int) icode].operand[2].constraint; | |
398 | gcc_assert (*scratch_constraint == '='); | |
399 | scratch_constraint++; | |
400 | if (*scratch_constraint == '&') | |
401 | scratch_constraint++; | |
402 | letter = *scratch_constraint; | |
403 | scratch_class = (letter == 'r' ? GENERAL_REGS | |
404 | : REG_CLASS_FROM_CONSTRAINT ((unsigned char) letter, | |
58477b5d | 405 | scratch_constraint)); |
8a99f6f9 | 406 | |
55d796da | 407 | rclass = scratch_class; |
8a99f6f9 | 408 | mode = insn_data[(int) icode].operand[2].mode; |
eab89b90 RK |
409 | } |
410 | ||
9ec7078b RK |
411 | /* This case isn't valid, so fail. Reload is allowed to use the same |
412 | register for RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT reloads, but | |
413 | in the case of a secondary register, we actually need two different | |
414 | registers for correct code. We fail here to prevent the possibility of | |
415 | silently generating incorrect code later. | |
416 | ||
417 | The convention is that secondary input reloads are valid only if the | |
31989264 RH |
418 | secondary_class is different from class. If you have such a case, you |
419 | can not use secondary reloads, you must work around the problem some | |
420 | other way. | |
9ec7078b | 421 | |
94aaab7a RH |
422 | Allow this when a reload_in/out pattern is being used. I.e. assume |
423 | that the generated code handles this case. */ | |
9ec7078b | 424 | |
55d796da | 425 | gcc_assert (!in_p || rclass != reload_class || icode != CODE_FOR_nothing |
41374e13 | 426 | || t_icode != CODE_FOR_nothing); |
9ec7078b | 427 | |
9ec7078b RK |
428 | /* See if we can reuse an existing secondary reload. */ |
429 | for (s_reload = 0; s_reload < n_reloads; s_reload++) | |
eceef4c9 | 430 | if (rld[s_reload].secondary_p |
48c54229 KG |
431 | && (reg_class_subset_p (rclass, rld[s_reload].rclass) |
432 | || reg_class_subset_p (rld[s_reload].rclass, rclass)) | |
eceef4c9 BS |
433 | && ((in_p && rld[s_reload].inmode == mode) |
434 | || (! in_p && rld[s_reload].outmode == mode)) | |
435 | && ((in_p && rld[s_reload].secondary_in_reload == t_reload) | |
436 | || (! in_p && rld[s_reload].secondary_out_reload == t_reload)) | |
437 | && ((in_p && rld[s_reload].secondary_in_icode == t_icode) | |
438 | || (! in_p && rld[s_reload].secondary_out_icode == t_icode)) | |
55d796da | 439 | && (SMALL_REGISTER_CLASS_P (rclass) || SMALL_REGISTER_CLASSES) |
eceef4c9 BS |
440 | && MERGABLE_RELOADS (secondary_type, rld[s_reload].when_needed, |
441 | opnum, rld[s_reload].opnum)) | |
9ec7078b RK |
442 | { |
443 | if (in_p) | |
eceef4c9 | 444 | rld[s_reload].inmode = mode; |
9ec7078b | 445 | if (! in_p) |
eceef4c9 | 446 | rld[s_reload].outmode = mode; |
9ec7078b | 447 | |
48c54229 KG |
448 | if (reg_class_subset_p (rclass, rld[s_reload].rclass)) |
449 | rld[s_reload].rclass = rclass; | |
9ec7078b | 450 | |
eceef4c9 BS |
451 | rld[s_reload].opnum = MIN (rld[s_reload].opnum, opnum); |
452 | rld[s_reload].optional &= optional; | |
453 | rld[s_reload].secondary_p = 1; | |
454 | if (MERGE_TO_OTHER (secondary_type, rld[s_reload].when_needed, | |
455 | opnum, rld[s_reload].opnum)) | |
456 | rld[s_reload].when_needed = RELOAD_OTHER; | |
c3be2598 JW |
457 | |
458 | break; | |
9ec7078b | 459 | } |
eab89b90 | 460 | |
9ec7078b RK |
461 | if (s_reload == n_reloads) |
462 | { | |
e9a25f70 JL |
463 | #ifdef SECONDARY_MEMORY_NEEDED |
464 | /* If we need a memory location to copy between the two reload regs, | |
465 | set it up now. Note that we do the input case before making | |
05d10675 | 466 | the reload and the output case after. This is due to the |
e9a25f70 JL |
467 | way reloads are output. */ |
468 | ||
469 | if (in_p && icode == CODE_FOR_nothing | |
55d796da | 470 | && SECONDARY_MEMORY_NEEDED (rclass, reload_class, mode)) |
6fe8aebc RH |
471 | { |
472 | get_secondary_mem (x, reload_mode, opnum, type); | |
473 | ||
474 | /* We may have just added new reloads. Make sure we add | |
475 | the new reload at the end. */ | |
476 | s_reload = n_reloads; | |
477 | } | |
e9a25f70 JL |
478 | #endif |
479 | ||
9ec7078b | 480 | /* We need to make a new secondary reload for this register class. */ |
eceef4c9 | 481 | rld[s_reload].in = rld[s_reload].out = 0; |
48c54229 | 482 | rld[s_reload].rclass = rclass; |
eceef4c9 BS |
483 | |
484 | rld[s_reload].inmode = in_p ? mode : VOIDmode; | |
485 | rld[s_reload].outmode = ! in_p ? mode : VOIDmode; | |
486 | rld[s_reload].reg_rtx = 0; | |
487 | rld[s_reload].optional = optional; | |
eceef4c9 | 488 | rld[s_reload].inc = 0; |
9ec7078b | 489 | /* Maybe we could combine these, but it seems too tricky. */ |
eceef4c9 BS |
490 | rld[s_reload].nocombine = 1; |
491 | rld[s_reload].in_reg = 0; | |
492 | rld[s_reload].out_reg = 0; | |
493 | rld[s_reload].opnum = opnum; | |
494 | rld[s_reload].when_needed = secondary_type; | |
495 | rld[s_reload].secondary_in_reload = in_p ? t_reload : -1; | |
496 | rld[s_reload].secondary_out_reload = ! in_p ? t_reload : -1; | |
497 | rld[s_reload].secondary_in_icode = in_p ? t_icode : CODE_FOR_nothing; | |
498 | rld[s_reload].secondary_out_icode | |
9ec7078b | 499 | = ! in_p ? t_icode : CODE_FOR_nothing; |
eceef4c9 | 500 | rld[s_reload].secondary_p = 1; |
9ec7078b RK |
501 | |
502 | n_reloads++; | |
503 | ||
504 | #ifdef SECONDARY_MEMORY_NEEDED | |
9ec7078b | 505 | if (! in_p && icode == CODE_FOR_nothing |
55d796da | 506 | && SECONDARY_MEMORY_NEEDED (reload_class, rclass, mode)) |
f49e4127 | 507 | get_secondary_mem (x, mode, opnum, type); |
9ec7078b RK |
508 | #endif |
509 | } | |
510 | ||
511 | *picode = icode; | |
512 | return s_reload; | |
eab89b90 | 513 | } |
8a99f6f9 R |
514 | |
515 | /* If a secondary reload is needed, return its class. If both an intermediate | |
516 | register and a scratch register is needed, we return the class of the | |
517 | intermediate register. */ | |
518 | enum reg_class | |
55d796da | 519 | secondary_reload_class (bool in_p, enum reg_class rclass, |
8a99f6f9 R |
520 | enum machine_mode mode, rtx x) |
521 | { | |
522 | enum insn_code icode; | |
523 | secondary_reload_info sri; | |
524 | ||
525 | sri.icode = CODE_FOR_nothing; | |
526 | sri.prev_sri = NULL; | |
55d796da | 527 | rclass = targetm.secondary_reload (in_p, x, rclass, mode, &sri); |
32e8bb8e | 528 | icode = (enum insn_code) sri.icode; |
8a99f6f9 R |
529 | |
530 | /* If there are no secondary reloads at all, we return NO_REGS. | |
531 | If an intermediate register is needed, we return its class. */ | |
55d796da KG |
532 | if (icode == CODE_FOR_nothing || rclass != NO_REGS) |
533 | return rclass; | |
8a99f6f9 R |
534 | |
535 | /* No intermediate register is needed, but we have a special reload | |
536 | pattern, which we assume for now needs a scratch register. */ | |
537 | return scratch_reload_class (icode); | |
538 | } | |
539 | ||
540 | /* ICODE is the insn_code of a reload pattern. Check that it has exactly | |
541 | three operands, verify that operand 2 is an output operand, and return | |
542 | its register class. | |
543 | ??? We'd like to be able to handle any pattern with at least 2 operands, | |
544 | for zero or more scratch registers, but that needs more infrastructure. */ | |
545 | enum reg_class | |
546 | scratch_reload_class (enum insn_code icode) | |
547 | { | |
548 | const char *scratch_constraint; | |
549 | char scratch_letter; | |
55d796da | 550 | enum reg_class rclass; |
8a99f6f9 R |
551 | |
552 | gcc_assert (insn_data[(int) icode].n_operands == 3); | |
553 | scratch_constraint = insn_data[(int) icode].operand[2].constraint; | |
554 | gcc_assert (*scratch_constraint == '='); | |
555 | scratch_constraint++; | |
556 | if (*scratch_constraint == '&') | |
557 | scratch_constraint++; | |
558 | scratch_letter = *scratch_constraint; | |
559 | if (scratch_letter == 'r') | |
560 | return GENERAL_REGS; | |
55d796da | 561 | rclass = REG_CLASS_FROM_CONSTRAINT ((unsigned char) scratch_letter, |
8a99f6f9 | 562 | scratch_constraint); |
55d796da KG |
563 | gcc_assert (rclass != NO_REGS); |
564 | return rclass; | |
8a99f6f9 | 565 | } |
eab89b90 | 566 | \f |
0dadecf6 RK |
567 | #ifdef SECONDARY_MEMORY_NEEDED |
568 | ||
05d10675 | 569 | /* Return a memory location that will be used to copy X in mode MODE. |
0dadecf6 RK |
570 | If we haven't already made a location for this mode in this insn, |
571 | call find_reloads_address on the location being returned. */ | |
572 | ||
573 | rtx | |
0c20a65f AJ |
574 | get_secondary_mem (rtx x ATTRIBUTE_UNUSED, enum machine_mode mode, |
575 | int opnum, enum reload_type type) | |
0dadecf6 RK |
576 | { |
577 | rtx loc; | |
578 | int mem_valid; | |
579 | ||
64609742 RK |
580 | /* By default, if MODE is narrower than a word, widen it to a word. |
581 | This is required because most machines that require these memory | |
582 | locations do not support short load and stores from all registers | |
583 | (e.g., FP registers). */ | |
584 | ||
585 | #ifdef SECONDARY_MEMORY_NEEDED_MODE | |
586 | mode = SECONDARY_MEMORY_NEEDED_MODE (mode); | |
587 | #else | |
4f9e0766 | 588 | if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD && INTEGRAL_MODE_P (mode)) |
0dadecf6 | 589 | mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0); |
64609742 | 590 | #endif |
0dadecf6 | 591 | |
77545d45 RK |
592 | /* If we already have made a MEM for this operand in MODE, return it. */ |
593 | if (secondary_memlocs_elim[(int) mode][opnum] != 0) | |
594 | return secondary_memlocs_elim[(int) mode][opnum]; | |
0dadecf6 | 595 | |
05d10675 | 596 | /* If this is the first time we've tried to get a MEM for this mode, |
0dadecf6 RK |
597 | allocate a new one. `something_changed' in reload will get set |
598 | by noticing that the frame size has changed. */ | |
599 | ||
600 | if (secondary_memlocs[(int) mode] == 0) | |
b24a53d5 JW |
601 | { |
602 | #ifdef SECONDARY_MEMORY_NEEDED_RTX | |
603 | secondary_memlocs[(int) mode] = SECONDARY_MEMORY_NEEDED_RTX (mode); | |
604 | #else | |
605 | secondary_memlocs[(int) mode] | |
606 | = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); | |
607 | #endif | |
608 | } | |
0dadecf6 RK |
609 | |
610 | /* Get a version of the address doing any eliminations needed. If that | |
611 | didn't give us a new MEM, make a new one if it isn't valid. */ | |
612 | ||
1914f5da | 613 | loc = eliminate_regs (secondary_memlocs[(int) mode], VOIDmode, NULL_RTX); |
0dadecf6 RK |
614 | mem_valid = strict_memory_address_p (mode, XEXP (loc, 0)); |
615 | ||
616 | if (! mem_valid && loc == secondary_memlocs[(int) mode]) | |
617 | loc = copy_rtx (loc); | |
618 | ||
619 | /* The only time the call below will do anything is if the stack | |
620 | offset is too large. In that case IND_LEVELS doesn't matter, so we | |
a8c9daeb RK |
621 | can just pass a zero. Adjust the type to be the address of the |
622 | corresponding object. If the address was valid, save the eliminated | |
623 | address. If it wasn't valid, we need to make a reload each time, so | |
624 | don't save it. */ | |
0dadecf6 | 625 | |
a8c9daeb RK |
626 | if (! mem_valid) |
627 | { | |
628 | type = (type == RELOAD_FOR_INPUT ? RELOAD_FOR_INPUT_ADDRESS | |
629 | : type == RELOAD_FOR_OUTPUT ? RELOAD_FOR_OUTPUT_ADDRESS | |
630 | : RELOAD_OTHER); | |
8d618585 | 631 | |
57292ec3 | 632 | find_reloads_address (mode, &loc, XEXP (loc, 0), &XEXP (loc, 0), |
55c22565 | 633 | opnum, type, 0, 0); |
a8c9daeb | 634 | } |
0dadecf6 | 635 | |
77545d45 | 636 | secondary_memlocs_elim[(int) mode][opnum] = loc; |
98e5e087 JH |
637 | if (secondary_memlocs_elim_used <= (int)mode) |
638 | secondary_memlocs_elim_used = (int)mode + 1; | |
0dadecf6 RK |
639 | return loc; |
640 | } | |
641 | ||
642 | /* Clear any secondary memory locations we've made. */ | |
643 | ||
644 | void | |
0c20a65f | 645 | clear_secondary_mem (void) |
0dadecf6 | 646 | { |
703ad42b | 647 | memset (secondary_memlocs, 0, sizeof secondary_memlocs); |
0dadecf6 RK |
648 | } |
649 | #endif /* SECONDARY_MEMORY_NEEDED */ | |
650 | \f | |
e11ab33b DD |
651 | |
652 | /* Find the largest class which has at least one register valid in | |
653 | mode INNER, and which for every such register, that register number | |
654 | plus N is also valid in OUTER (if in range) and is cheap to move | |
0e61db61 | 655 | into REGNO. Such a class must exist. */ |
c6716840 RK |
656 | |
657 | static enum reg_class | |
e11ab33b DD |
658 | find_valid_class (enum machine_mode outer ATTRIBUTE_UNUSED, |
659 | enum machine_mode inner ATTRIBUTE_UNUSED, int n, | |
0c20a65f | 660 | unsigned int dest_regno ATTRIBUTE_UNUSED) |
c6716840 | 661 | { |
a65dc37d | 662 | int best_cost = -1; |
55d796da | 663 | int rclass; |
c6716840 | 664 | int regno; |
f428f252 | 665 | enum reg_class best_class = NO_REGS; |
4977bab6 | 666 | enum reg_class dest_class ATTRIBUTE_UNUSED = REGNO_REG_CLASS (dest_regno); |
770ae6cc | 667 | unsigned int best_size = 0; |
b80cb6e2 | 668 | int cost; |
c6716840 | 669 | |
55d796da | 670 | for (rclass = 1; rclass < N_REG_CLASSES; rclass++) |
c6716840 RK |
671 | { |
672 | int bad = 0; | |
e11ab33b DD |
673 | int good = 0; |
674 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER - n && ! bad; regno++) | |
55d796da | 675 | if (TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)) |
e11ab33b DD |
676 | { |
677 | if (HARD_REGNO_MODE_OK (regno, inner)) | |
678 | { | |
679 | good = 1; | |
55d796da | 680 | if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], regno + n) |
e11ab33b DD |
681 | || ! HARD_REGNO_MODE_OK (regno + n, outer)) |
682 | bad = 1; | |
683 | } | |
684 | } | |
c6716840 | 685 | |
e11ab33b | 686 | if (bad || !good) |
b80cb6e2 | 687 | continue; |
bbbbb16a | 688 | cost = REGISTER_MOVE_COST (outer, (enum reg_class) rclass, dest_class); |
b80cb6e2 | 689 | |
55d796da | 690 | if ((reg_class_size[rclass] > best_size |
b80cb6e2 JH |
691 | && (best_cost < 0 || best_cost >= cost)) |
692 | || best_cost > cost) | |
a65dc37d | 693 | { |
32e8bb8e | 694 | best_class = (enum reg_class) rclass; |
55d796da | 695 | best_size = reg_class_size[rclass]; |
bbbbb16a ILT |
696 | best_cost = REGISTER_MOVE_COST (outer, (enum reg_class) rclass, |
697 | dest_class); | |
a65dc37d | 698 | } |
c6716840 RK |
699 | } |
700 | ||
41374e13 | 701 | gcc_assert (best_size != 0); |
c6716840 RK |
702 | |
703 | return best_class; | |
704 | } | |
705 | \f | |
121315ea BS |
706 | /* Return the number of a previously made reload that can be combined with |
707 | a new one, or n_reloads if none of the existing reloads can be used. | |
55d796da | 708 | OUT, RCLASS, TYPE and OPNUM are the same arguments as passed to |
121315ea BS |
709 | push_reload, they determine the kind of the new reload that we try to |
710 | combine. P_IN points to the corresponding value of IN, which can be | |
711 | modified by this function. | |
712 | DONT_SHARE is nonzero if we can't share any input-only reload for IN. */ | |
35fb60c4 | 713 | |
121315ea | 714 | static int |
55d796da | 715 | find_reusable_reload (rtx *p_in, rtx out, enum reg_class rclass, |
0c20a65f | 716 | enum reload_type type, int opnum, int dont_share) |
121315ea BS |
717 | { |
718 | rtx in = *p_in; | |
719 | int i; | |
720 | /* We can't merge two reloads if the output of either one is | |
721 | earlyclobbered. */ | |
722 | ||
723 | if (earlyclobber_operand_p (out)) | |
724 | return n_reloads; | |
725 | ||
726 | /* We can use an existing reload if the class is right | |
727 | and at least one of IN and OUT is a match | |
728 | and the other is at worst neutral. | |
05d10675 | 729 | (A zero compared against anything is neutral.) |
121315ea BS |
730 | |
731 | If SMALL_REGISTER_CLASSES, don't use existing reloads unless they are | |
732 | for the same thing since that can cause us to need more reload registers | |
733 | than we otherwise would. */ | |
05d10675 | 734 | |
121315ea | 735 | for (i = 0; i < n_reloads; i++) |
48c54229 KG |
736 | if ((reg_class_subset_p (rclass, rld[i].rclass) |
737 | || reg_class_subset_p (rld[i].rclass, rclass)) | |
121315ea | 738 | /* If the existing reload has a register, it must fit our class. */ |
eceef4c9 | 739 | && (rld[i].reg_rtx == 0 |
55d796da | 740 | || TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], |
eceef4c9 BS |
741 | true_regnum (rld[i].reg_rtx))) |
742 | && ((in != 0 && MATCHES (rld[i].in, in) && ! dont_share | |
743 | && (out == 0 || rld[i].out == 0 || MATCHES (rld[i].out, out))) | |
744 | || (out != 0 && MATCHES (rld[i].out, out) | |
745 | && (in == 0 || rld[i].in == 0 || MATCHES (rld[i].in, in)))) | |
746 | && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out)) | |
55d796da | 747 | && (SMALL_REGISTER_CLASS_P (rclass) || SMALL_REGISTER_CLASSES) |
eceef4c9 | 748 | && MERGABLE_RELOADS (type, rld[i].when_needed, opnum, rld[i].opnum)) |
121315ea BS |
749 | return i; |
750 | ||
751 | /* Reloading a plain reg for input can match a reload to postincrement | |
752 | that reg, since the postincrement's value is the right value. | |
753 | Likewise, it can match a preincrement reload, since we regard | |
754 | the preincrementation as happening before any ref in this insn | |
755 | to that register. */ | |
756 | for (i = 0; i < n_reloads; i++) | |
48c54229 KG |
757 | if ((reg_class_subset_p (rclass, rld[i].rclass) |
758 | || reg_class_subset_p (rld[i].rclass, rclass)) | |
121315ea BS |
759 | /* If the existing reload has a register, it must fit our |
760 | class. */ | |
eceef4c9 | 761 | && (rld[i].reg_rtx == 0 |
55d796da | 762 | || TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], |
eceef4c9 BS |
763 | true_regnum (rld[i].reg_rtx))) |
764 | && out == 0 && rld[i].out == 0 && rld[i].in != 0 | |
f8cfc6aa | 765 | && ((REG_P (in) |
ec8e098d | 766 | && GET_RTX_CLASS (GET_CODE (rld[i].in)) == RTX_AUTOINC |
eceef4c9 | 767 | && MATCHES (XEXP (rld[i].in, 0), in)) |
f8cfc6aa | 768 | || (REG_P (rld[i].in) |
ec8e098d | 769 | && GET_RTX_CLASS (GET_CODE (in)) == RTX_AUTOINC |
4b983fdc | 770 | && MATCHES (XEXP (in, 0), rld[i].in))) |
eceef4c9 | 771 | && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out)) |
55d796da | 772 | && (SMALL_REGISTER_CLASS_P (rclass) || SMALL_REGISTER_CLASSES) |
eceef4c9 BS |
773 | && MERGABLE_RELOADS (type, rld[i].when_needed, |
774 | opnum, rld[i].opnum)) | |
121315ea BS |
775 | { |
776 | /* Make sure reload_in ultimately has the increment, | |
777 | not the plain register. */ | |
f8cfc6aa | 778 | if (REG_P (in)) |
eceef4c9 | 779 | *p_in = rld[i].in; |
121315ea BS |
780 | return i; |
781 | } | |
782 | return n_reloads; | |
783 | } | |
784 | ||
e6ea3b5f JL |
785 | /* Return nonzero if X is a SUBREG which will require reloading of its |
786 | SUBREG_REG expression. */ | |
787 | ||
788 | static int | |
0c20a65f | 789 | reload_inner_reg_of_subreg (rtx x, enum machine_mode mode, int output) |
e6ea3b5f JL |
790 | { |
791 | rtx inner; | |
792 | ||
793 | /* Only SUBREGs are problematical. */ | |
794 | if (GET_CODE (x) != SUBREG) | |
795 | return 0; | |
796 | ||
797 | inner = SUBREG_REG (x); | |
798 | ||
35fb60c4 RK |
799 | /* If INNER is a constant or PLUS, then INNER must be reloaded. */ |
800 | if (CONSTANT_P (inner) || GET_CODE (inner) == PLUS) | |
e6ea3b5f JL |
801 | return 1; |
802 | ||
803 | /* If INNER is not a hard register, then INNER will not need to | |
804 | be reloaded. */ | |
f8cfc6aa | 805 | if (!REG_P (inner) |
e6ea3b5f JL |
806 | || REGNO (inner) >= FIRST_PSEUDO_REGISTER) |
807 | return 0; | |
808 | ||
809 | /* If INNER is not ok for MODE, then INNER will need reloading. */ | |
ddef6bc7 | 810 | if (! HARD_REGNO_MODE_OK (subreg_regno (x), mode)) |
e6ea3b5f JL |
811 | return 1; |
812 | ||
813 | /* If the outer part is a word or smaller, INNER larger than a | |
814 | word and the number of regs for INNER is not the same as the | |
815 | number of words in INNER, then INNER will need reloading. */ | |
816 | return (GET_MODE_SIZE (mode) <= UNITS_PER_WORD | |
4bf1d92e | 817 | && output |
e6ea3b5f JL |
818 | && GET_MODE_SIZE (GET_MODE (inner)) > UNITS_PER_WORD |
819 | && ((GET_MODE_SIZE (GET_MODE (inner)) / UNITS_PER_WORD) | |
66fd46b6 | 820 | != (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)])); |
e6ea3b5f JL |
821 | } |
822 | ||
35d6034b R |
823 | /* Return nonzero if IN can be reloaded into REGNO with mode MODE without |
824 | requiring an extra reload register. The caller has already found that | |
825 | IN contains some reference to REGNO, so check that we can produce the | |
826 | new value in a single step. E.g. if we have | |
827 | (set (reg r13) (plus (reg r13) (const int 1))), and there is an | |
828 | instruction that adds one to a register, this should succeed. | |
829 | However, if we have something like | |
830 | (set (reg r13) (plus (reg r13) (const int 999))), and the constant 999 | |
831 | needs to be loaded into a register first, we need a separate reload | |
832 | register. | |
833 | Such PLUS reloads are generated by find_reload_address_part. | |
834 | The out-of-range PLUS expressions are usually introduced in the instruction | |
835 | patterns by register elimination and substituting pseudos without a home | |
836 | by their function-invariant equivalences. */ | |
837 | static int | |
838 | can_reload_into (rtx in, int regno, enum machine_mode mode) | |
839 | { | |
840 | rtx dst, test_insn; | |
841 | int r = 0; | |
842 | struct recog_data save_recog_data; | |
843 | ||
844 | /* For matching constraints, we often get notional input reloads where | |
845 | we want to use the original register as the reload register. I.e. | |
846 | technically this is a non-optional input-output reload, but IN is | |
847 | already a valid register, and has been chosen as the reload register. | |
848 | Speed this up, since it trivially works. */ | |
f8cfc6aa | 849 | if (REG_P (in)) |
35d6034b R |
850 | return 1; |
851 | ||
852 | /* To test MEMs properly, we'd have to take into account all the reloads | |
853 | that are already scheduled, which can become quite complicated. | |
854 | And since we've already handled address reloads for this MEM, it | |
855 | should always succeed anyway. */ | |
3c0cb5de | 856 | if (MEM_P (in)) |
35d6034b R |
857 | return 1; |
858 | ||
859 | /* If we can make a simple SET insn that does the job, everything should | |
860 | be fine. */ | |
861 | dst = gen_rtx_REG (mode, regno); | |
862 | test_insn = make_insn_raw (gen_rtx_SET (VOIDmode, dst, in)); | |
863 | save_recog_data = recog_data; | |
864 | if (recog_memoized (test_insn) >= 0) | |
865 | { | |
866 | extract_insn (test_insn); | |
867 | r = constrain_operands (1); | |
868 | } | |
869 | recog_data = save_recog_data; | |
870 | return r; | |
871 | } | |
872 | ||
a8c9daeb | 873 | /* Record one reload that needs to be performed. |
eab89b90 RK |
874 | IN is an rtx saying where the data are to be found before this instruction. |
875 | OUT says where they must be stored after the instruction. | |
876 | (IN is zero for data not read, and OUT is zero for data not written.) | |
877 | INLOC and OUTLOC point to the places in the instructions where | |
878 | IN and OUT were found. | |
40f03658 | 879 | If IN and OUT are both nonzero, it means the same register must be used |
a8c9daeb RK |
880 | to reload both IN and OUT. |
881 | ||
55d796da | 882 | RCLASS is a register class required for the reloaded data. |
eab89b90 RK |
883 | INMODE is the machine mode that the instruction requires |
884 | for the reg that replaces IN and OUTMODE is likewise for OUT. | |
885 | ||
886 | If IN is zero, then OUT's location and mode should be passed as | |
887 | INLOC and INMODE. | |
888 | ||
889 | STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx. | |
890 | ||
891 | OPTIONAL nonzero means this reload does not need to be performed: | |
892 | it can be discarded if that is more convenient. | |
893 | ||
a8c9daeb RK |
894 | OPNUM and TYPE say what the purpose of this reload is. |
895 | ||
eab89b90 RK |
896 | The return value is the reload-number for this reload. |
897 | ||
898 | If both IN and OUT are nonzero, in some rare cases we might | |
899 | want to make two separate reloads. (Actually we never do this now.) | |
900 | Therefore, the reload-number for OUT is stored in | |
901 | output_reloadnum when we return; the return value applies to IN. | |
902 | Usually (presently always), when IN and OUT are nonzero, | |
903 | the two reload-numbers are equal, but the caller should be careful to | |
904 | distinguish them. */ | |
905 | ||
aead1ca3 | 906 | int |
0c20a65f | 907 | push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc, |
55d796da | 908 | enum reg_class rclass, enum machine_mode inmode, |
0c20a65f AJ |
909 | enum machine_mode outmode, int strict_low, int optional, |
910 | int opnum, enum reload_type type) | |
eab89b90 | 911 | { |
b3694847 | 912 | int i; |
eab89b90 | 913 | int dont_share = 0; |
74347d76 | 914 | int dont_remove_subreg = 0; |
eab89b90 | 915 | rtx *in_subreg_loc = 0, *out_subreg_loc = 0; |
9ec7078b | 916 | int secondary_in_reload = -1, secondary_out_reload = -1; |
a229128d RK |
917 | enum insn_code secondary_in_icode = CODE_FOR_nothing; |
918 | enum insn_code secondary_out_icode = CODE_FOR_nothing; | |
a8c9daeb | 919 | |
eab89b90 RK |
920 | /* INMODE and/or OUTMODE could be VOIDmode if no mode |
921 | has been specified for the operand. In that case, | |
922 | use the operand's mode as the mode to reload. */ | |
923 | if (inmode == VOIDmode && in != 0) | |
924 | inmode = GET_MODE (in); | |
925 | if (outmode == VOIDmode && out != 0) | |
926 | outmode = GET_MODE (out); | |
927 | ||
90d12f1f AK |
928 | /* If find_reloads and friends until now missed to replace a pseudo |
929 | with a constant of reg_equiv_constant something went wrong | |
930 | beforehand. | |
931 | Note that it can't simply be done here if we missed it earlier | |
932 | since the constant might need to be pushed into the literal pool | |
933 | and the resulting memref would probably need further | |
934 | reloading. */ | |
f8cfc6aa | 935 | if (in != 0 && REG_P (in)) |
eab89b90 | 936 | { |
b3694847 | 937 | int regno = REGNO (in); |
eab89b90 | 938 | |
90d12f1f AK |
939 | gcc_assert (regno < FIRST_PSEUDO_REGISTER |
940 | || reg_renumber[regno] >= 0 | |
941 | || reg_equiv_constant[regno] == NULL_RTX); | |
eab89b90 RK |
942 | } |
943 | ||
90d12f1f AK |
944 | /* reg_equiv_constant only contains constants which are obviously |
945 | not appropriate as destination. So if we would need to replace | |
946 | the destination pseudo with a constant we are in real | |
947 | trouble. */ | |
f8cfc6aa | 948 | if (out != 0 && REG_P (out)) |
eab89b90 | 949 | { |
b3694847 | 950 | int regno = REGNO (out); |
eab89b90 | 951 | |
90d12f1f AK |
952 | gcc_assert (regno < FIRST_PSEUDO_REGISTER |
953 | || reg_renumber[regno] >= 0 | |
954 | || reg_equiv_constant[regno] == NULL_RTX); | |
eab89b90 RK |
955 | } |
956 | ||
957 | /* If we have a read-write operand with an address side-effect, | |
958 | change either IN or OUT so the side-effect happens only once. */ | |
3c0cb5de | 959 | if (in != 0 && out != 0 && MEM_P (in) && rtx_equal_p (in, out)) |
f1ec5147 RK |
960 | switch (GET_CODE (XEXP (in, 0))) |
961 | { | |
962 | case POST_INC: case POST_DEC: case POST_MODIFY: | |
963 | in = replace_equiv_address_nv (in, XEXP (XEXP (in, 0), 0)); | |
964 | break; | |
3bdf5ad1 | 965 | |
f1ec5147 RK |
966 | case PRE_INC: case PRE_DEC: case PRE_MODIFY: |
967 | out = replace_equiv_address_nv (out, XEXP (XEXP (out, 0), 0)); | |
968 | break; | |
3bdf5ad1 | 969 | |
f1ec5147 RK |
970 | default: |
971 | break; | |
f4f4d0f8 | 972 | } |
eab89b90 | 973 | |
a61c98cf | 974 | /* If we are reloading a (SUBREG constant ...), really reload just the |
ca769828 | 975 | inside expression in its own mode. Similarly for (SUBREG (PLUS ...)). |
a61c98cf RK |
976 | If we have (SUBREG:M1 (MEM:M2 ...) ...) (or an inner REG that is still |
977 | a pseudo and hence will become a MEM) with M1 wider than M2 and the | |
978 | register is a pseudo, also reload the inside expression. | |
f72ccbe6 | 979 | For machines that extend byte loads, do this for any SUBREG of a pseudo |
486d8509 RK |
980 | where both M1 and M2 are a word or smaller, M1 is wider than M2, and |
981 | M2 is an integral mode that gets extended when loaded. | |
86c31b2d | 982 | Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
eab89b90 RK |
983 | either M1 is not valid for R or M2 is wider than a word but we only |
984 | need one word to store an M2-sized quantity in R. | |
86c31b2d RS |
985 | (However, if OUT is nonzero, we need to reload the reg *and* |
986 | the subreg, so do nothing here, and let following statement handle it.) | |
987 | ||
eab89b90 RK |
988 | Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere; |
989 | we can't handle it here because CONST_INT does not indicate a mode. | |
990 | ||
991 | Similarly, we must reload the inside expression if we have a | |
fa10beec | 992 | STRICT_LOW_PART (presumably, in == out in this case). |
df62f951 RK |
993 | |
994 | Also reload the inner expression if it does not require a secondary | |
486d8509 RK |
995 | reload but the SUBREG does. |
996 | ||
997 | Finally, reload the inner expression if it is a register that is in | |
998 | the class whose registers cannot be referenced in a different size | |
b4905cba | 999 | and M1 is not the same size as M2. If subreg_lowpart_p is false, we |
d030f4b2 | 1000 | cannot reload just the inside since we might end up with the wrong |
ab87f8c8 JL |
1001 | register class. But if it is inside a STRICT_LOW_PART, we have |
1002 | no choice, so we hope we do get the right register class there. */ | |
eab89b90 | 1003 | |
ab87f8c8 | 1004 | if (in != 0 && GET_CODE (in) == SUBREG |
b4905cba | 1005 | && (subreg_lowpart_p (in) || strict_low) |
cff9f8d5 | 1006 | #ifdef CANNOT_CHANGE_MODE_CLASS |
55d796da | 1007 | && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (in)), inmode, rclass) |
94bafba7 | 1008 | #endif |
a61c98cf | 1009 | && (CONSTANT_P (SUBREG_REG (in)) |
ca769828 | 1010 | || GET_CODE (SUBREG_REG (in)) == PLUS |
eab89b90 | 1011 | || strict_low |
f8cfc6aa | 1012 | || (((REG_P (SUBREG_REG (in)) |
a61c98cf | 1013 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER) |
3c0cb5de | 1014 | || MEM_P (SUBREG_REG (in))) |
03b72c86 RK |
1015 | && ((GET_MODE_SIZE (inmode) |
1016 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
09bf0250 | 1017 | #ifdef LOAD_EXTEND_OP |
03b72c86 RK |
1018 | || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD |
1019 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1020 | <= UNITS_PER_WORD) | |
1021 | && (GET_MODE_SIZE (inmode) | |
486d8509 RK |
1022 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) |
1023 | && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in))) | |
f822d252 | 1024 | && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != UNKNOWN) |
d2c92f5a R |
1025 | #endif |
1026 | #ifdef WORD_REGISTER_OPERATIONS | |
1027 | || ((GET_MODE_SIZE (inmode) | |
1028 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
1029 | && ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD == | |
1030 | ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) - 1) | |
1031 | / UNITS_PER_WORD))) | |
f72ccbe6 | 1032 | #endif |
03b72c86 | 1033 | )) |
f8cfc6aa | 1034 | || (REG_P (SUBREG_REG (in)) |
a61c98cf | 1035 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER |
86c31b2d RS |
1036 | /* The case where out is nonzero |
1037 | is handled differently in the following statement. */ | |
b4905cba | 1038 | && (out == 0 || subreg_lowpart_p (in)) |
f72ccbe6 RK |
1039 | && ((GET_MODE_SIZE (inmode) <= UNITS_PER_WORD |
1040 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1041 | > UNITS_PER_WORD) | |
1042 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1043 | / UNITS_PER_WORD) | |
66fd46b6 JH |
1044 | != (int) hard_regno_nregs[REGNO (SUBREG_REG (in))] |
1045 | [GET_MODE (SUBREG_REG (in))])) | |
ddef6bc7 | 1046 | || ! HARD_REGNO_MODE_OK (subreg_regno (in), inmode))) |
55d796da KG |
1047 | || (secondary_reload_class (1, rclass, inmode, in) != NO_REGS |
1048 | && (secondary_reload_class (1, rclass, GET_MODE (SUBREG_REG (in)), | |
8a99f6f9 | 1049 | SUBREG_REG (in)) |
df62f951 | 1050 | == NO_REGS)) |
cff9f8d5 | 1051 | #ifdef CANNOT_CHANGE_MODE_CLASS |
f8cfc6aa | 1052 | || (REG_P (SUBREG_REG (in)) |
486d8509 | 1053 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER |
cff9f8d5 AH |
1054 | && REG_CANNOT_CHANGE_MODE_P |
1055 | (REGNO (SUBREG_REG (in)), GET_MODE (SUBREG_REG (in)), inmode)) | |
df62f951 RK |
1056 | #endif |
1057 | )) | |
eab89b90 RK |
1058 | { |
1059 | in_subreg_loc = inloc; | |
1060 | inloc = &SUBREG_REG (in); | |
1061 | in = *inloc; | |
d2c92f5a | 1062 | #if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS) |
3c0cb5de | 1063 | if (MEM_P (in)) |
eab89b90 RK |
1064 | /* This is supposed to happen only for paradoxical subregs made by |
1065 | combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */ | |
41374e13 | 1066 | gcc_assert (GET_MODE_SIZE (GET_MODE (in)) <= GET_MODE_SIZE (inmode)); |
e05a9da8 | 1067 | #endif |
eab89b90 RK |
1068 | inmode = GET_MODE (in); |
1069 | } | |
1070 | ||
86c31b2d RS |
1071 | /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
1072 | either M1 is not valid for R or M2 is wider than a word but we only | |
1073 | need one word to store an M2-sized quantity in R. | |
1074 | ||
1075 | However, we must reload the inner reg *as well as* the subreg in | |
1076 | that case. */ | |
1077 | ||
6fd5ac08 | 1078 | /* Similar issue for (SUBREG constant ...) if it was not handled by the |
ddef6bc7 | 1079 | code above. This can happen if SUBREG_BYTE != 0. */ |
6fd5ac08 | 1080 | |
4bf1d92e | 1081 | if (in != 0 && reload_inner_reg_of_subreg (in, inmode, 0)) |
86c31b2d | 1082 | { |
55d796da | 1083 | enum reg_class in_class = rclass; |
35fb60c4 | 1084 | |
f8cfc6aa | 1085 | if (REG_P (SUBREG_REG (in))) |
35fb60c4 | 1086 | in_class |
e11ab33b | 1087 | = find_valid_class (inmode, GET_MODE (SUBREG_REG (in)), |
35fb60c4 RK |
1088 | subreg_regno_offset (REGNO (SUBREG_REG (in)), |
1089 | GET_MODE (SUBREG_REG (in)), | |
1090 | SUBREG_BYTE (in), | |
a65dc37d JH |
1091 | GET_MODE (in)), |
1092 | REGNO (SUBREG_REG (in))); | |
35fb60c4 | 1093 | |
c96d01ab RK |
1094 | /* This relies on the fact that emit_reload_insns outputs the |
1095 | instructions for input reloads of type RELOAD_OTHER in the same | |
1096 | order as the reloads. Thus if the outer reload is also of type | |
1097 | RELOAD_OTHER, we are guaranteed that this inner reload will be | |
1098 | output before the outer reload. */ | |
f4f4d0f8 | 1099 | push_reload (SUBREG_REG (in), NULL_RTX, &SUBREG_REG (in), (rtx *) 0, |
35fb60c4 | 1100 | in_class, VOIDmode, VOIDmode, 0, 0, opnum, type); |
74347d76 | 1101 | dont_remove_subreg = 1; |
86c31b2d RS |
1102 | } |
1103 | ||
eab89b90 RK |
1104 | /* Similarly for paradoxical and problematical SUBREGs on the output. |
1105 | Note that there is no reason we need worry about the previous value | |
1106 | of SUBREG_REG (out); even if wider than out, | |
1107 | storing in a subreg is entitled to clobber it all | |
1108 | (except in the case of STRICT_LOW_PART, | |
1109 | and in that case the constraint should label it input-output.) */ | |
ab87f8c8 | 1110 | if (out != 0 && GET_CODE (out) == SUBREG |
b4905cba | 1111 | && (subreg_lowpart_p (out) || strict_low) |
cff9f8d5 | 1112 | #ifdef CANNOT_CHANGE_MODE_CLASS |
55d796da | 1113 | && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (out)), outmode, rclass) |
94bafba7 | 1114 | #endif |
a61c98cf | 1115 | && (CONSTANT_P (SUBREG_REG (out)) |
eab89b90 | 1116 | || strict_low |
f8cfc6aa | 1117 | || (((REG_P (SUBREG_REG (out)) |
a61c98cf | 1118 | && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER) |
3c0cb5de | 1119 | || MEM_P (SUBREG_REG (out))) |
03b72c86 | 1120 | && ((GET_MODE_SIZE (outmode) |
1914f5da RH |
1121 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) |
1122 | #ifdef WORD_REGISTER_OPERATIONS | |
6d49a073 JW |
1123 | || ((GET_MODE_SIZE (outmode) |
1124 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
1125 | && ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD == | |
1126 | ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) - 1) | |
1127 | / UNITS_PER_WORD))) | |
1914f5da | 1128 | #endif |
05d10675 | 1129 | )) |
f8cfc6aa | 1130 | || (REG_P (SUBREG_REG (out)) |
eab89b90 | 1131 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER |
f72ccbe6 RK |
1132 | && ((GET_MODE_SIZE (outmode) <= UNITS_PER_WORD |
1133 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1134 | > UNITS_PER_WORD) | |
1135 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1136 | / UNITS_PER_WORD) | |
66fd46b6 JH |
1137 | != (int) hard_regno_nregs[REGNO (SUBREG_REG (out))] |
1138 | [GET_MODE (SUBREG_REG (out))])) | |
ddef6bc7 | 1139 | || ! HARD_REGNO_MODE_OK (subreg_regno (out), outmode))) |
55d796da KG |
1140 | || (secondary_reload_class (0, rclass, outmode, out) != NO_REGS |
1141 | && (secondary_reload_class (0, rclass, GET_MODE (SUBREG_REG (out)), | |
8a99f6f9 | 1142 | SUBREG_REG (out)) |
df62f951 | 1143 | == NO_REGS)) |
cff9f8d5 | 1144 | #ifdef CANNOT_CHANGE_MODE_CLASS |
f8cfc6aa | 1145 | || (REG_P (SUBREG_REG (out)) |
486d8509 | 1146 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER |
cff9f8d5 | 1147 | && REG_CANNOT_CHANGE_MODE_P (REGNO (SUBREG_REG (out)), |
0c20a65f | 1148 | GET_MODE (SUBREG_REG (out)), |
cff9f8d5 | 1149 | outmode)) |
df62f951 RK |
1150 | #endif |
1151 | )) | |
eab89b90 RK |
1152 | { |
1153 | out_subreg_loc = outloc; | |
1154 | outloc = &SUBREG_REG (out); | |
05d10675 | 1155 | out = *outloc; |
d2c92f5a | 1156 | #if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS) |
41374e13 NS |
1157 | gcc_assert (!MEM_P (out) |
1158 | || GET_MODE_SIZE (GET_MODE (out)) | |
1159 | <= GET_MODE_SIZE (outmode)); | |
e05a9da8 | 1160 | #endif |
eab89b90 RK |
1161 | outmode = GET_MODE (out); |
1162 | } | |
1163 | ||
74347d76 RK |
1164 | /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
1165 | either M1 is not valid for R or M2 is wider than a word but we only | |
1166 | need one word to store an M2-sized quantity in R. | |
1167 | ||
1168 | However, we must reload the inner reg *as well as* the subreg in | |
1169 | that case. In this case, the inner reg is an in-out reload. */ | |
1170 | ||
4bf1d92e | 1171 | if (out != 0 && reload_inner_reg_of_subreg (out, outmode, 1)) |
74347d76 | 1172 | { |
c96d01ab RK |
1173 | /* This relies on the fact that emit_reload_insns outputs the |
1174 | instructions for output reloads of type RELOAD_OTHER in reverse | |
1175 | order of the reloads. Thus if the outer reload is also of type | |
1176 | RELOAD_OTHER, we are guaranteed that this inner reload will be | |
1177 | output after the outer reload. */ | |
74347d76 RK |
1178 | dont_remove_subreg = 1; |
1179 | push_reload (SUBREG_REG (out), SUBREG_REG (out), &SUBREG_REG (out), | |
c6716840 | 1180 | &SUBREG_REG (out), |
e11ab33b | 1181 | find_valid_class (outmode, GET_MODE (SUBREG_REG (out)), |
ddef6bc7 JJ |
1182 | subreg_regno_offset (REGNO (SUBREG_REG (out)), |
1183 | GET_MODE (SUBREG_REG (out)), | |
1184 | SUBREG_BYTE (out), | |
a65dc37d JH |
1185 | GET_MODE (out)), |
1186 | REGNO (SUBREG_REG (out))), | |
c6716840 | 1187 | VOIDmode, VOIDmode, 0, 0, |
74347d76 RK |
1188 | opnum, RELOAD_OTHER); |
1189 | } | |
1190 | ||
eab89b90 | 1191 | /* If IN appears in OUT, we can't share any input-only reload for IN. */ |
3c0cb5de | 1192 | if (in != 0 && out != 0 && MEM_P (out) |
10050f74 | 1193 | && (REG_P (in) || MEM_P (in) || GET_CODE (in) == PLUS) |
bfa30b22 | 1194 | && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0))) |
eab89b90 RK |
1195 | dont_share = 1; |
1196 | ||
0dadecf6 RK |
1197 | /* If IN is a SUBREG of a hard register, make a new REG. This |
1198 | simplifies some of the cases below. */ | |
1199 | ||
f8cfc6aa | 1200 | if (in != 0 && GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in)) |
74347d76 RK |
1201 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER |
1202 | && ! dont_remove_subreg) | |
ddef6bc7 | 1203 | in = gen_rtx_REG (GET_MODE (in), subreg_regno (in)); |
0dadecf6 RK |
1204 | |
1205 | /* Similarly for OUT. */ | |
1206 | if (out != 0 && GET_CODE (out) == SUBREG | |
f8cfc6aa | 1207 | && REG_P (SUBREG_REG (out)) |
74347d76 RK |
1208 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER |
1209 | && ! dont_remove_subreg) | |
ddef6bc7 | 1210 | out = gen_rtx_REG (GET_MODE (out), subreg_regno (out)); |
0dadecf6 | 1211 | |
eab89b90 RK |
1212 | /* Narrow down the class of register wanted if that is |
1213 | desirable on this machine for efficiency. */ | |
b5c82fa1 | 1214 | { |
55d796da | 1215 | enum reg_class preferred_class = rclass; |
b5c82fa1 PB |
1216 | |
1217 | if (in != 0) | |
55d796da | 1218 | preferred_class = PREFERRED_RELOAD_CLASS (in, rclass); |
eab89b90 | 1219 | |
ac2a9454 | 1220 | /* Output reloads may need analogous treatment, different in detail. */ |
18a53b78 | 1221 | #ifdef PREFERRED_OUTPUT_RELOAD_CLASS |
b5c82fa1 PB |
1222 | if (out != 0) |
1223 | preferred_class = PREFERRED_OUTPUT_RELOAD_CLASS (out, preferred_class); | |
18a53b78 RS |
1224 | #endif |
1225 | ||
b5c82fa1 PB |
1226 | /* Discard what the target said if we cannot do it. */ |
1227 | if (preferred_class != NO_REGS | |
1228 | || (optional && type == RELOAD_FOR_OUTPUT)) | |
55d796da | 1229 | rclass = preferred_class; |
b5c82fa1 PB |
1230 | } |
1231 | ||
eab89b90 RK |
1232 | /* Make sure we use a class that can handle the actual pseudo |
1233 | inside any subreg. For example, on the 386, QImode regs | |
1234 | can appear within SImode subregs. Although GENERAL_REGS | |
1235 | can handle SImode, QImode needs a smaller class. */ | |
1236 | #ifdef LIMIT_RELOAD_CLASS | |
1237 | if (in_subreg_loc) | |
55d796da | 1238 | rclass = LIMIT_RELOAD_CLASS (inmode, rclass); |
eab89b90 | 1239 | else if (in != 0 && GET_CODE (in) == SUBREG) |
55d796da | 1240 | rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), rclass); |
eab89b90 RK |
1241 | |
1242 | if (out_subreg_loc) | |
55d796da | 1243 | rclass = LIMIT_RELOAD_CLASS (outmode, rclass); |
eab89b90 | 1244 | if (out != 0 && GET_CODE (out) == SUBREG) |
55d796da | 1245 | rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), rclass); |
eab89b90 RK |
1246 | #endif |
1247 | ||
eab89b90 RK |
1248 | /* Verify that this class is at least possible for the mode that |
1249 | is specified. */ | |
1250 | if (this_insn_is_asm) | |
1251 | { | |
1252 | enum machine_mode mode; | |
1253 | if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) | |
1254 | mode = inmode; | |
1255 | else | |
1256 | mode = outmode; | |
5488078f RS |
1257 | if (mode == VOIDmode) |
1258 | { | |
971801ff JM |
1259 | error_for_asm (this_insn, "cannot reload integer constant " |
1260 | "operand in %<asm%>"); | |
5488078f RS |
1261 | mode = word_mode; |
1262 | if (in != 0) | |
1263 | inmode = word_mode; | |
1264 | if (out != 0) | |
1265 | outmode = word_mode; | |
1266 | } | |
eab89b90 RK |
1267 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1268 | if (HARD_REGNO_MODE_OK (i, mode) | |
55d796da | 1269 | && in_hard_reg_set_p (reg_class_contents[(int) rclass], mode, i)) |
09e18274 | 1270 | break; |
eab89b90 RK |
1271 | if (i == FIRST_PSEUDO_REGISTER) |
1272 | { | |
971801ff JM |
1273 | error_for_asm (this_insn, "impossible register constraint " |
1274 | "in %<asm%>"); | |
71156bcc JH |
1275 | /* Avoid further trouble with this insn. */ |
1276 | PATTERN (this_insn) = gen_rtx_USE (VOIDmode, const0_rtx); | |
1277 | /* We used to continue here setting class to ALL_REGS, but it triggers | |
1278 | sanity check on i386 for: | |
1279 | void foo(long double d) | |
1280 | { | |
1281 | asm("" :: "a" (d)); | |
1282 | } | |
1283 | Returning zero here ought to be safe as we take care in | |
1284 | find_reloads to not process the reloads when instruction was | |
1285 | replaced by USE. */ | |
1286 | ||
1287 | return 0; | |
eab89b90 RK |
1288 | } |
1289 | } | |
1290 | ||
cb2afeb3 R |
1291 | /* Optional output reloads are always OK even if we have no register class, |
1292 | since the function of these reloads is only to have spill_reg_store etc. | |
1293 | set, so that the storing insn can be deleted later. */ | |
55d796da | 1294 | gcc_assert (rclass != NO_REGS |
41374e13 | 1295 | || (optional != 0 && type == RELOAD_FOR_OUTPUT)); |
5488078f | 1296 | |
55d796da | 1297 | i = find_reusable_reload (&in, out, rclass, type, opnum, dont_share); |
eab89b90 RK |
1298 | |
1299 | if (i == n_reloads) | |
1300 | { | |
9ec7078b RK |
1301 | /* See if we need a secondary reload register to move between CLASS |
1302 | and IN or CLASS and OUT. Get the icode and push any required reloads | |
1303 | needed for each of them if so. */ | |
eab89b90 | 1304 | |
eab89b90 | 1305 | if (in != 0) |
9ec7078b | 1306 | secondary_in_reload |
55d796da | 1307 | = push_secondary_reload (1, in, opnum, optional, rclass, inmode, type, |
8a99f6f9 | 1308 | &secondary_in_icode, NULL); |
eab89b90 | 1309 | if (out != 0 && GET_CODE (out) != SCRATCH) |
9ec7078b | 1310 | secondary_out_reload |
55d796da | 1311 | = push_secondary_reload (0, out, opnum, optional, rclass, outmode, |
8a99f6f9 | 1312 | type, &secondary_out_icode, NULL); |
eab89b90 RK |
1313 | |
1314 | /* We found no existing reload suitable for re-use. | |
1315 | So add an additional reload. */ | |
1316 | ||
e9a25f70 JL |
1317 | #ifdef SECONDARY_MEMORY_NEEDED |
1318 | /* If a memory location is needed for the copy, make one. */ | |
71a9b19a RG |
1319 | if (in != 0 |
1320 | && (REG_P (in) | |
1321 | || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in)))) | |
344b78b8 JH |
1322 | && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER |
1323 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)), | |
55d796da | 1324 | rclass, inmode)) |
e9a25f70 JL |
1325 | get_secondary_mem (in, inmode, opnum, type); |
1326 | #endif | |
1327 | ||
9ec7078b | 1328 | i = n_reloads; |
eceef4c9 BS |
1329 | rld[i].in = in; |
1330 | rld[i].out = out; | |
48c54229 | 1331 | rld[i].rclass = rclass; |
eceef4c9 BS |
1332 | rld[i].inmode = inmode; |
1333 | rld[i].outmode = outmode; | |
1334 | rld[i].reg_rtx = 0; | |
1335 | rld[i].optional = optional; | |
eceef4c9 BS |
1336 | rld[i].inc = 0; |
1337 | rld[i].nocombine = 0; | |
1338 | rld[i].in_reg = inloc ? *inloc : 0; | |
1339 | rld[i].out_reg = outloc ? *outloc : 0; | |
1340 | rld[i].opnum = opnum; | |
1341 | rld[i].when_needed = type; | |
1342 | rld[i].secondary_in_reload = secondary_in_reload; | |
1343 | rld[i].secondary_out_reload = secondary_out_reload; | |
1344 | rld[i].secondary_in_icode = secondary_in_icode; | |
1345 | rld[i].secondary_out_icode = secondary_out_icode; | |
1346 | rld[i].secondary_p = 0; | |
eab89b90 RK |
1347 | |
1348 | n_reloads++; | |
0dadecf6 RK |
1349 | |
1350 | #ifdef SECONDARY_MEMORY_NEEDED | |
71a9b19a RG |
1351 | if (out != 0 |
1352 | && (REG_P (out) | |
1353 | || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out)))) | |
344b78b8 | 1354 | && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER |
55d796da | 1355 | && SECONDARY_MEMORY_NEEDED (rclass, |
344b78b8 | 1356 | REGNO_REG_CLASS (reg_or_subregno (out)), |
0dadecf6 | 1357 | outmode)) |
a8c9daeb | 1358 | get_secondary_mem (out, outmode, opnum, type); |
0dadecf6 | 1359 | #endif |
eab89b90 RK |
1360 | } |
1361 | else | |
1362 | { | |
1363 | /* We are reusing an existing reload, | |
1364 | but we may have additional information for it. | |
1365 | For example, we may now have both IN and OUT | |
1366 | while the old one may have just one of them. */ | |
1367 | ||
6fd5ac08 JW |
1368 | /* The modes can be different. If they are, we want to reload in |
1369 | the larger mode, so that the value is valid for both modes. */ | |
1370 | if (inmode != VOIDmode | |
eceef4c9 BS |
1371 | && GET_MODE_SIZE (inmode) > GET_MODE_SIZE (rld[i].inmode)) |
1372 | rld[i].inmode = inmode; | |
6fd5ac08 | 1373 | if (outmode != VOIDmode |
eceef4c9 BS |
1374 | && GET_MODE_SIZE (outmode) > GET_MODE_SIZE (rld[i].outmode)) |
1375 | rld[i].outmode = outmode; | |
eab89b90 | 1376 | if (in != 0) |
cb2afeb3 | 1377 | { |
506b3b3a | 1378 | rtx in_reg = inloc ? *inloc : 0; |
cb2afeb3 R |
1379 | /* If we merge reloads for two distinct rtl expressions that |
1380 | are identical in content, there might be duplicate address | |
1381 | reloads. Remove the extra set now, so that if we later find | |
1382 | that we can inherit this reload, we can get rid of the | |
b838974e JL |
1383 | address reloads altogether. |
1384 | ||
1385 | Do not do this if both reloads are optional since the result | |
1386 | would be an optional reload which could potentially leave | |
1387 | unresolved address replacements. | |
1388 | ||
1389 | It is not sufficient to call transfer_replacements since | |
1390 | choose_reload_regs will remove the replacements for address | |
1391 | reloads of inherited reloads which results in the same | |
1392 | problem. */ | |
eceef4c9 BS |
1393 | if (rld[i].in != in && rtx_equal_p (in, rld[i].in) |
1394 | && ! (rld[i].optional && optional)) | |
cb2afeb3 R |
1395 | { |
1396 | /* We must keep the address reload with the lower operand | |
1397 | number alive. */ | |
eceef4c9 | 1398 | if (opnum > rld[i].opnum) |
cb2afeb3 R |
1399 | { |
1400 | remove_address_replacements (in); | |
eceef4c9 BS |
1401 | in = rld[i].in; |
1402 | in_reg = rld[i].in_reg; | |
cb2afeb3 R |
1403 | } |
1404 | else | |
eceef4c9 | 1405 | remove_address_replacements (rld[i].in); |
cb2afeb3 | 1406 | } |
46662f25 MM |
1407 | /* When emitting reloads we don't necessarily look at the in- |
1408 | and outmode, but also directly at the operands (in and out). | |
1409 | So we can't simply overwrite them with whatever we have found | |
1410 | for this (to-be-merged) reload, we have to "merge" that too. | |
1411 | Reusing another reload already verified that we deal with the | |
1412 | same operands, just possibly in different modes. So we | |
1413 | overwrite the operands only when the new mode is larger. | |
1414 | See also PR33613. */ | |
1415 | if (!rld[i].in | |
1416 | || GET_MODE_SIZE (GET_MODE (in)) | |
1417 | > GET_MODE_SIZE (GET_MODE (rld[i].in))) | |
1418 | rld[i].in = in; | |
1419 | if (!rld[i].in_reg | |
1420 | || (in_reg | |
1421 | && GET_MODE_SIZE (GET_MODE (in_reg)) | |
1422 | > GET_MODE_SIZE (GET_MODE (rld[i].in_reg)))) | |
1423 | rld[i].in_reg = in_reg; | |
cb2afeb3 | 1424 | } |
eab89b90 | 1425 | if (out != 0) |
cb2afeb3 | 1426 | { |
46662f25 MM |
1427 | if (!rld[i].out |
1428 | || (out | |
1429 | && GET_MODE_SIZE (GET_MODE (out)) | |
1430 | > GET_MODE_SIZE (GET_MODE (rld[i].out)))) | |
1431 | rld[i].out = out; | |
1432 | if (outloc | |
1433 | && (!rld[i].out_reg | |
1434 | || GET_MODE_SIZE (GET_MODE (*outloc)) | |
1435 | > GET_MODE_SIZE (GET_MODE (rld[i].out_reg)))) | |
1436 | rld[i].out_reg = *outloc; | |
cb2afeb3 | 1437 | } |
48c54229 KG |
1438 | if (reg_class_subset_p (rclass, rld[i].rclass)) |
1439 | rld[i].rclass = rclass; | |
eceef4c9 BS |
1440 | rld[i].optional &= optional; |
1441 | if (MERGE_TO_OTHER (type, rld[i].when_needed, | |
1442 | opnum, rld[i].opnum)) | |
1443 | rld[i].when_needed = RELOAD_OTHER; | |
1444 | rld[i].opnum = MIN (rld[i].opnum, opnum); | |
eab89b90 RK |
1445 | } |
1446 | ||
e0120d6e | 1447 | /* If the ostensible rtx being reloaded differs from the rtx found |
eab89b90 RK |
1448 | in the location to substitute, this reload is not safe to combine |
1449 | because we cannot reliably tell whether it appears in the insn. */ | |
1450 | ||
1451 | if (in != 0 && in != *inloc) | |
eceef4c9 | 1452 | rld[i].nocombine = 1; |
eab89b90 RK |
1453 | |
1454 | #if 0 | |
1455 | /* This was replaced by changes in find_reloads_address_1 and the new | |
1456 | function inc_for_reload, which go with a new meaning of reload_inc. */ | |
1457 | ||
1458 | /* If this is an IN/OUT reload in an insn that sets the CC, | |
1459 | it must be for an autoincrement. It doesn't work to store | |
1460 | the incremented value after the insn because that would clobber the CC. | |
1461 | So we must do the increment of the value reloaded from, | |
1462 | increment it, store it back, then decrement again. */ | |
1463 | if (out != 0 && sets_cc0_p (PATTERN (this_insn))) | |
1464 | { | |
1465 | out = 0; | |
eceef4c9 BS |
1466 | rld[i].out = 0; |
1467 | rld[i].inc = find_inc_amount (PATTERN (this_insn), in); | |
eab89b90 RK |
1468 | /* If we did not find a nonzero amount-to-increment-by, |
1469 | that contradicts the belief that IN is being incremented | |
1470 | in an address in this insn. */ | |
41374e13 | 1471 | gcc_assert (rld[i].inc != 0); |
eab89b90 RK |
1472 | } |
1473 | #endif | |
1474 | ||
1475 | /* If we will replace IN and OUT with the reload-reg, | |
1476 | record where they are located so that substitution need | |
1477 | not do a tree walk. */ | |
1478 | ||
1479 | if (replace_reloads) | |
1480 | { | |
1481 | if (inloc != 0) | |
1482 | { | |
b3694847 | 1483 | struct replacement *r = &replacements[n_replacements++]; |
eab89b90 RK |
1484 | r->what = i; |
1485 | r->subreg_loc = in_subreg_loc; | |
1486 | r->where = inloc; | |
1487 | r->mode = inmode; | |
1488 | } | |
1489 | if (outloc != 0 && outloc != inloc) | |
1490 | { | |
b3694847 | 1491 | struct replacement *r = &replacements[n_replacements++]; |
eab89b90 RK |
1492 | r->what = i; |
1493 | r->where = outloc; | |
1494 | r->subreg_loc = out_subreg_loc; | |
1495 | r->mode = outmode; | |
1496 | } | |
1497 | } | |
1498 | ||
1499 | /* If this reload is just being introduced and it has both | |
1500 | an incoming quantity and an outgoing quantity that are | |
1501 | supposed to be made to match, see if either one of the two | |
1502 | can serve as the place to reload into. | |
1503 | ||
eceef4c9 | 1504 | If one of them is acceptable, set rld[i].reg_rtx |
eab89b90 RK |
1505 | to that one. */ |
1506 | ||
eceef4c9 | 1507 | if (in != 0 && out != 0 && in != out && rld[i].reg_rtx == 0) |
eab89b90 | 1508 | { |
eceef4c9 BS |
1509 | rld[i].reg_rtx = find_dummy_reload (in, out, inloc, outloc, |
1510 | inmode, outmode, | |
48c54229 | 1511 | rld[i].rclass, i, |
eceef4c9 | 1512 | earlyclobber_operand_p (out)); |
eab89b90 RK |
1513 | |
1514 | /* If the outgoing register already contains the same value | |
1515 | as the incoming one, we can dispense with loading it. | |
1516 | The easiest way to tell the caller that is to give a phony | |
1517 | value for the incoming operand (same as outgoing one). */ | |
eceef4c9 | 1518 | if (rld[i].reg_rtx == out |
f8cfc6aa | 1519 | && (REG_P (in) || CONSTANT_P (in)) |
bbbbb16a | 1520 | && 0 != find_equiv_reg (in, this_insn, NO_REGS, REGNO (out), |
eab89b90 | 1521 | static_reload_reg_p, i, inmode)) |
eceef4c9 | 1522 | rld[i].in = out; |
eab89b90 RK |
1523 | } |
1524 | ||
1525 | /* If this is an input reload and the operand contains a register that | |
1526 | dies in this insn and is used nowhere else, see if it is the right class | |
1527 | to be used for this reload. Use it if so. (This occurs most commonly | |
1528 | in the case of paradoxical SUBREGs and in-out reloads). We cannot do | |
1529 | this if it is also an output reload that mentions the register unless | |
1530 | the output is a SUBREG that clobbers an entire register. | |
1531 | ||
1532 | Note that the operand might be one of the spill regs, if it is a | |
1533 | pseudo reg and we are in a block where spilling has not taken place. | |
1534 | But if there is no spilling in this block, that is OK. | |
1535 | An explicitly used hard reg cannot be a spill reg. */ | |
1536 | ||
687b527d | 1537 | if (rld[i].reg_rtx == 0 && in != 0 && hard_regs_live_known) |
eab89b90 RK |
1538 | { |
1539 | rtx note; | |
1540 | int regno; | |
d0b6af71 R |
1541 | enum machine_mode rel_mode = inmode; |
1542 | ||
1543 | if (out && GET_MODE_SIZE (outmode) > GET_MODE_SIZE (inmode)) | |
1544 | rel_mode = outmode; | |
eab89b90 RK |
1545 | |
1546 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1547 | if (REG_NOTE_KIND (note) == REG_DEAD | |
f8cfc6aa | 1548 | && REG_P (XEXP (note, 0)) |
eab89b90 RK |
1549 | && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER |
1550 | && reg_mentioned_p (XEXP (note, 0), in) | |
96cdfb52 | 1551 | /* Check that a former pseudo is valid; see find_dummy_reload. */ |
687b527d | 1552 | && (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER |
174b3107 | 1553 | || (! bitmap_bit_p (DF_LR_OUT (ENTRY_BLOCK_PTR), |
058e97ec | 1554 | ORIGINAL_REGNO (XEXP (note, 0))) |
96cdfb52 | 1555 | && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] == 1)) |
eab89b90 | 1556 | && ! refers_to_regno_for_reload_p (regno, |
09e18274 RS |
1557 | end_hard_regno (rel_mode, |
1558 | regno), | |
eab89b90 | 1559 | PATTERN (this_insn), inloc) |
05b4ec4f RS |
1560 | /* If this is also an output reload, IN cannot be used as |
1561 | the reload register if it is set in this insn unless IN | |
1562 | is also OUT. */ | |
1563 | && (out == 0 || in == out | |
1564 | || ! hard_reg_set_here_p (regno, | |
09e18274 | 1565 | end_hard_regno (rel_mode, regno), |
05b4ec4f RS |
1566 | PATTERN (this_insn))) |
1567 | /* ??? Why is this code so different from the previous? | |
1568 | Is there any simple coherent way to describe the two together? | |
1569 | What's going on here. */ | |
eab89b90 RK |
1570 | && (in != out |
1571 | || (GET_CODE (in) == SUBREG | |
1572 | && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1)) | |
1573 | / UNITS_PER_WORD) | |
1574 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1575 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
1576 | /* Make sure the operand fits in the reg that dies. */ | |
d0b6af71 R |
1577 | && (GET_MODE_SIZE (rel_mode) |
1578 | <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))) | |
eab89b90 | 1579 | && HARD_REGNO_MODE_OK (regno, inmode) |
96b42f4c | 1580 | && HARD_REGNO_MODE_OK (regno, outmode)) |
eab89b90 | 1581 | { |
db30db99 | 1582 | unsigned int offs; |
66fd46b6 JH |
1583 | unsigned int nregs = MAX (hard_regno_nregs[regno][inmode], |
1584 | hard_regno_nregs[regno][outmode]); | |
db30db99 | 1585 | |
96b42f4c BS |
1586 | for (offs = 0; offs < nregs; offs++) |
1587 | if (fixed_regs[regno + offs] | |
55d796da | 1588 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], |
96b42f4c BS |
1589 | regno + offs)) |
1590 | break; | |
1591 | ||
35d6034b R |
1592 | if (offs == nregs |
1593 | && (! (refers_to_regno_for_reload_p | |
09e18274 | 1594 | (regno, end_hard_regno (inmode, regno), in, (rtx *) 0)) |
35d6034b | 1595 | || can_reload_into (in, regno, inmode))) |
96b42f4c | 1596 | { |
d0b6af71 | 1597 | rld[i].reg_rtx = gen_rtx_REG (rel_mode, regno); |
96b42f4c BS |
1598 | break; |
1599 | } | |
eab89b90 RK |
1600 | } |
1601 | } | |
1602 | ||
1603 | if (out) | |
1604 | output_reloadnum = i; | |
1605 | ||
1606 | return i; | |
1607 | } | |
1608 | ||
1609 | /* Record an additional place we must replace a value | |
1610 | for which we have already recorded a reload. | |
1611 | RELOADNUM is the value returned by push_reload | |
1612 | when the reload was recorded. | |
1613 | This is used in insn patterns that use match_dup. */ | |
1614 | ||
1615 | static void | |
0c20a65f | 1616 | push_replacement (rtx *loc, int reloadnum, enum machine_mode mode) |
eab89b90 RK |
1617 | { |
1618 | if (replace_reloads) | |
1619 | { | |
b3694847 | 1620 | struct replacement *r = &replacements[n_replacements++]; |
eab89b90 RK |
1621 | r->what = reloadnum; |
1622 | r->where = loc; | |
1623 | r->subreg_loc = 0; | |
1624 | r->mode = mode; | |
1625 | } | |
1626 | } | |
6cabe79e UW |
1627 | |
1628 | /* Duplicate any replacement we have recorded to apply at | |
1629 | location ORIG_LOC to also be performed at DUP_LOC. | |
1630 | This is used in insn patterns that use match_dup. */ | |
1631 | ||
1632 | static void | |
0c20a65f | 1633 | dup_replacements (rtx *dup_loc, rtx *orig_loc) |
6cabe79e UW |
1634 | { |
1635 | int i, n = n_replacements; | |
1636 | ||
1637 | for (i = 0; i < n; i++) | |
1638 | { | |
1639 | struct replacement *r = &replacements[i]; | |
1640 | if (r->where == orig_loc) | |
1641 | push_replacement (dup_loc, r->what, r->mode); | |
1642 | } | |
1643 | } | |
eab89b90 | 1644 | \f |
a8c9daeb RK |
1645 | /* Transfer all replacements that used to be in reload FROM to be in |
1646 | reload TO. */ | |
1647 | ||
1648 | void | |
0c20a65f | 1649 | transfer_replacements (int to, int from) |
a8c9daeb RK |
1650 | { |
1651 | int i; | |
1652 | ||
1653 | for (i = 0; i < n_replacements; i++) | |
1654 | if (replacements[i].what == from) | |
1655 | replacements[i].what = to; | |
1656 | } | |
1657 | \f | |
cb2afeb3 R |
1658 | /* IN_RTX is the value loaded by a reload that we now decided to inherit, |
1659 | or a subpart of it. If we have any replacements registered for IN_RTX, | |
1660 | cancel the reloads that were supposed to load them. | |
40f03658 | 1661 | Return nonzero if we canceled any reloads. */ |
cb2afeb3 | 1662 | int |
0c20a65f | 1663 | remove_address_replacements (rtx in_rtx) |
029b38ff R |
1664 | { |
1665 | int i, j; | |
cb2afeb3 R |
1666 | char reload_flags[MAX_RELOADS]; |
1667 | int something_changed = 0; | |
029b38ff | 1668 | |
961192e1 | 1669 | memset (reload_flags, 0, sizeof reload_flags); |
029b38ff R |
1670 | for (i = 0, j = 0; i < n_replacements; i++) |
1671 | { | |
cb2afeb3 R |
1672 | if (loc_mentioned_in_p (replacements[i].where, in_rtx)) |
1673 | reload_flags[replacements[i].what] |= 1; | |
1674 | else | |
1675 | { | |
1676 | replacements[j++] = replacements[i]; | |
1677 | reload_flags[replacements[i].what] |= 2; | |
1678 | } | |
1679 | } | |
1680 | /* Note that the following store must be done before the recursive calls. */ | |
1681 | n_replacements = j; | |
1682 | ||
1683 | for (i = n_reloads - 1; i >= 0; i--) | |
1684 | { | |
1685 | if (reload_flags[i] == 1) | |
1686 | { | |
1687 | deallocate_reload_reg (i); | |
eceef4c9 BS |
1688 | remove_address_replacements (rld[i].in); |
1689 | rld[i].in = 0; | |
cb2afeb3 R |
1690 | something_changed = 1; |
1691 | } | |
1692 | } | |
1693 | return something_changed; | |
1694 | } | |
029b38ff | 1695 | \f |
eab89b90 RK |
1696 | /* If there is only one output reload, and it is not for an earlyclobber |
1697 | operand, try to combine it with a (logically unrelated) input reload | |
1698 | to reduce the number of reload registers needed. | |
1699 | ||
1700 | This is safe if the input reload does not appear in | |
1701 | the value being output-reloaded, because this implies | |
1702 | it is not needed any more once the original insn completes. | |
1703 | ||
1704 | If that doesn't work, see we can use any of the registers that | |
1705 | die in this insn as a reload register. We can if it is of the right | |
1706 | class and does not appear in the value being output-reloaded. */ | |
1707 | ||
1708 | static void | |
0c20a65f | 1709 | combine_reloads (void) |
eab89b90 | 1710 | { |
96cdfb52 | 1711 | int i, regno; |
eab89b90 | 1712 | int output_reload = -1; |
8922eb5b | 1713 | int secondary_out = -1; |
eab89b90 RK |
1714 | rtx note; |
1715 | ||
1716 | /* Find the output reload; return unless there is exactly one | |
1717 | and that one is mandatory. */ | |
1718 | ||
1719 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 1720 | if (rld[i].out != 0) |
eab89b90 RK |
1721 | { |
1722 | if (output_reload >= 0) | |
1723 | return; | |
1724 | output_reload = i; | |
1725 | } | |
1726 | ||
eceef4c9 | 1727 | if (output_reload < 0 || rld[output_reload].optional) |
eab89b90 RK |
1728 | return; |
1729 | ||
1730 | /* An input-output reload isn't combinable. */ | |
1731 | ||
eceef4c9 | 1732 | if (rld[output_reload].in != 0) |
eab89b90 RK |
1733 | return; |
1734 | ||
6dc42e49 | 1735 | /* If this reload is for an earlyclobber operand, we can't do anything. */ |
eceef4c9 | 1736 | if (earlyclobber_operand_p (rld[output_reload].out)) |
4644aad4 | 1737 | return; |
eab89b90 | 1738 | |
6b3736a1 | 1739 | /* If there is a reload for part of the address of this operand, we would |
9f5ed61a | 1740 | need to change it to RELOAD_FOR_OTHER_ADDRESS. But that would extend |
6b3736a1 RK |
1741 | its life to the point where doing this combine would not lower the |
1742 | number of spill registers needed. */ | |
1743 | for (i = 0; i < n_reloads; i++) | |
1744 | if ((rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
1745 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
1746 | && rld[i].opnum == rld[output_reload].opnum) | |
1747 | return; | |
1748 | ||
eab89b90 RK |
1749 | /* Check each input reload; can we combine it? */ |
1750 | ||
1751 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 1752 | if (rld[i].in && ! rld[i].optional && ! rld[i].nocombine |
eab89b90 | 1753 | /* Life span of this reload must not extend past main insn. */ |
eceef4c9 BS |
1754 | && rld[i].when_needed != RELOAD_FOR_OUTPUT_ADDRESS |
1755 | && rld[i].when_needed != RELOAD_FOR_OUTADDR_ADDRESS | |
1756 | && rld[i].when_needed != RELOAD_OTHER | |
48c54229 KG |
1757 | && (CLASS_MAX_NREGS (rld[i].rclass, rld[i].inmode) |
1758 | == CLASS_MAX_NREGS (rld[output_reload].rclass, | |
eceef4c9 BS |
1759 | rld[output_reload].outmode)) |
1760 | && rld[i].inc == 0 | |
1761 | && rld[i].reg_rtx == 0 | |
a8c9daeb | 1762 | #ifdef SECONDARY_MEMORY_NEEDED |
9ec7078b RK |
1763 | /* Don't combine two reloads with different secondary |
1764 | memory locations. */ | |
eceef4c9 BS |
1765 | && (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum] == 0 |
1766 | || secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum] == 0 | |
1767 | || rtx_equal_p (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum], | |
1768 | secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum])) | |
a8c9daeb | 1769 | #endif |
e9a25f70 | 1770 | && (SMALL_REGISTER_CLASSES |
48c54229 KG |
1771 | ? (rld[i].rclass == rld[output_reload].rclass) |
1772 | : (reg_class_subset_p (rld[i].rclass, | |
1773 | rld[output_reload].rclass) | |
1774 | || reg_class_subset_p (rld[output_reload].rclass, | |
1775 | rld[i].rclass))) | |
eceef4c9 | 1776 | && (MATCHES (rld[i].in, rld[output_reload].out) |
eab89b90 RK |
1777 | /* Args reversed because the first arg seems to be |
1778 | the one that we imagine being modified | |
1779 | while the second is the one that might be affected. */ | |
eceef4c9 BS |
1780 | || (! reg_overlap_mentioned_for_reload_p (rld[output_reload].out, |
1781 | rld[i].in) | |
eab89b90 RK |
1782 | /* However, if the input is a register that appears inside |
1783 | the output, then we also can't share. | |
1784 | Imagine (set (mem (reg 69)) (plus (reg 69) ...)). | |
1785 | If the same reload reg is used for both reg 69 and the | |
1786 | result to be stored in memory, then that result | |
1787 | will clobber the address of the memory ref. */ | |
f8cfc6aa | 1788 | && ! (REG_P (rld[i].in) |
eceef4c9 BS |
1789 | && reg_overlap_mentioned_for_reload_p (rld[i].in, |
1790 | rld[output_reload].out)))) | |
4bf1d92e JH |
1791 | && ! reload_inner_reg_of_subreg (rld[i].in, rld[i].inmode, |
1792 | rld[i].when_needed != RELOAD_FOR_INPUT) | |
48c54229 | 1793 | && (reg_class_size[(int) rld[i].rclass] |
e9a25f70 | 1794 | || SMALL_REGISTER_CLASSES) |
a8c9daeb RK |
1795 | /* We will allow making things slightly worse by combining an |
1796 | input and an output, but no worse than that. */ | |
eceef4c9 BS |
1797 | && (rld[i].when_needed == RELOAD_FOR_INPUT |
1798 | || rld[i].when_needed == RELOAD_FOR_OUTPUT)) | |
eab89b90 RK |
1799 | { |
1800 | int j; | |
1801 | ||
1802 | /* We have found a reload to combine with! */ | |
eceef4c9 BS |
1803 | rld[i].out = rld[output_reload].out; |
1804 | rld[i].out_reg = rld[output_reload].out_reg; | |
1805 | rld[i].outmode = rld[output_reload].outmode; | |
eab89b90 | 1806 | /* Mark the old output reload as inoperative. */ |
eceef4c9 | 1807 | rld[output_reload].out = 0; |
eab89b90 | 1808 | /* The combined reload is needed for the entire insn. */ |
eceef4c9 | 1809 | rld[i].when_needed = RELOAD_OTHER; |
0f41302f | 1810 | /* If the output reload had a secondary reload, copy it. */ |
eceef4c9 | 1811 | if (rld[output_reload].secondary_out_reload != -1) |
9ec7078b | 1812 | { |
eceef4c9 BS |
1813 | rld[i].secondary_out_reload |
1814 | = rld[output_reload].secondary_out_reload; | |
1815 | rld[i].secondary_out_icode | |
1816 | = rld[output_reload].secondary_out_icode; | |
9ec7078b RK |
1817 | } |
1818 | ||
a8c9daeb RK |
1819 | #ifdef SECONDARY_MEMORY_NEEDED |
1820 | /* Copy any secondary MEM. */ | |
eceef4c9 BS |
1821 | if (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum] != 0) |
1822 | secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum] | |
1823 | = secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum]; | |
a8c9daeb | 1824 | #endif |
0f41302f | 1825 | /* If required, minimize the register class. */ |
48c54229 KG |
1826 | if (reg_class_subset_p (rld[output_reload].rclass, |
1827 | rld[i].rclass)) | |
1828 | rld[i].rclass = rld[output_reload].rclass; | |
eab89b90 RK |
1829 | |
1830 | /* Transfer all replacements from the old reload to the combined. */ | |
1831 | for (j = 0; j < n_replacements; j++) | |
1832 | if (replacements[j].what == output_reload) | |
1833 | replacements[j].what = i; | |
1834 | ||
1835 | return; | |
1836 | } | |
1837 | ||
1838 | /* If this insn has only one operand that is modified or written (assumed | |
1839 | to be the first), it must be the one corresponding to this reload. It | |
1840 | is safe to use anything that dies in this insn for that output provided | |
1841 | that it does not occur in the output (we already know it isn't an | |
1842 | earlyclobber. If this is an asm insn, give up. */ | |
1843 | ||
1f9a0ec2 | 1844 | if (INSN_CODE (this_insn) == -1) |
eab89b90 RK |
1845 | return; |
1846 | ||
a995e389 RH |
1847 | for (i = 1; i < insn_data[INSN_CODE (this_insn)].n_operands; i++) |
1848 | if (insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '=' | |
1849 | || insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '+') | |
eab89b90 RK |
1850 | return; |
1851 | ||
1852 | /* See if some hard register that dies in this insn and is not used in | |
1853 | the output is the right class. Only works if the register we pick | |
1854 | up can fully hold our output reload. */ | |
1855 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1856 | if (REG_NOTE_KIND (note) == REG_DEAD | |
f8cfc6aa | 1857 | && REG_P (XEXP (note, 0)) |
96cdfb52 EB |
1858 | && !reg_overlap_mentioned_for_reload_p (XEXP (note, 0), |
1859 | rld[output_reload].out) | |
1860 | && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER | |
1861 | && HARD_REGNO_MODE_OK (regno, rld[output_reload].outmode) | |
48c54229 | 1862 | && TEST_HARD_REG_BIT (reg_class_contents[(int) rld[output_reload].rclass], |
96cdfb52 EB |
1863 | regno) |
1864 | && (hard_regno_nregs[regno][rld[output_reload].outmode] | |
1865 | <= hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))]) | |
8922eb5b RK |
1866 | /* Ensure that a secondary or tertiary reload for this output |
1867 | won't want this register. */ | |
eceef4c9 | 1868 | && ((secondary_out = rld[output_reload].secondary_out_reload) == -1 |
96cdfb52 | 1869 | || (!(TEST_HARD_REG_BIT |
48c54229 | 1870 | (reg_class_contents[(int) rld[secondary_out].rclass], regno)) |
eceef4c9 | 1871 | && ((secondary_out = rld[secondary_out].secondary_out_reload) == -1 |
96cdfb52 | 1872 | || !(TEST_HARD_REG_BIT |
48c54229 | 1873 | (reg_class_contents[(int) rld[secondary_out].rclass], |
96cdfb52 EB |
1874 | regno))))) |
1875 | && !fixed_regs[regno] | |
1876 | /* Check that a former pseudo is valid; see find_dummy_reload. */ | |
c1673e1b | 1877 | && (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER |
96cdfb52 EB |
1878 | || (!bitmap_bit_p (DF_LR_OUT (ENTRY_BLOCK_PTR), |
1879 | ORIGINAL_REGNO (XEXP (note, 0))) | |
1880 | && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] == 1))) | |
eab89b90 | 1881 | { |
eceef4c9 | 1882 | rld[output_reload].reg_rtx |
96cdfb52 | 1883 | = gen_rtx_REG (rld[output_reload].outmode, regno); |
eab89b90 RK |
1884 | return; |
1885 | } | |
1886 | } | |
1887 | \f | |
1888 | /* Try to find a reload register for an in-out reload (expressions IN and OUT). | |
1889 | See if one of IN and OUT is a register that may be used; | |
1890 | this is desirable since a spill-register won't be needed. | |
1891 | If so, return the register rtx that proves acceptable. | |
1892 | ||
1893 | INLOC and OUTLOC are locations where IN and OUT appear in the insn. | |
55d796da | 1894 | RCLASS is the register class required for the reload. |
eab89b90 RK |
1895 | |
1896 | If FOR_REAL is >= 0, it is the number of the reload, | |
1897 | and in some cases when it can be discovered that OUT doesn't need | |
eceef4c9 | 1898 | to be computed, clear out rld[FOR_REAL].out. |
eab89b90 RK |
1899 | |
1900 | If FOR_REAL is -1, this should not be done, because this call | |
189086f9 RK |
1901 | is just to see if a register can be found, not to find and install it. |
1902 | ||
40f03658 | 1903 | EARLYCLOBBER is nonzero if OUT is an earlyclobber operand. This |
189086f9 RK |
1904 | puts an additional constraint on being able to use IN for OUT since |
1905 | IN must not appear elsewhere in the insn (it is assumed that IN itself | |
1906 | is safe from the earlyclobber). */ | |
eab89b90 RK |
1907 | |
1908 | static rtx | |
0c20a65f AJ |
1909 | find_dummy_reload (rtx real_in, rtx real_out, rtx *inloc, rtx *outloc, |
1910 | enum machine_mode inmode, enum machine_mode outmode, | |
55d796da | 1911 | enum reg_class rclass, int for_real, int earlyclobber) |
eab89b90 RK |
1912 | { |
1913 | rtx in = real_in; | |
1914 | rtx out = real_out; | |
1915 | int in_offset = 0; | |
1916 | int out_offset = 0; | |
1917 | rtx value = 0; | |
1918 | ||
1919 | /* If operands exceed a word, we can't use either of them | |
1920 | unless they have the same size. */ | |
36b50568 RS |
1921 | if (GET_MODE_SIZE (outmode) != GET_MODE_SIZE (inmode) |
1922 | && (GET_MODE_SIZE (outmode) > UNITS_PER_WORD | |
1923 | || GET_MODE_SIZE (inmode) > UNITS_PER_WORD)) | |
eab89b90 RK |
1924 | return 0; |
1925 | ||
ddef6bc7 JJ |
1926 | /* Note that {in,out}_offset are needed only when 'in' or 'out' |
1927 | respectively refers to a hard register. */ | |
1928 | ||
eab89b90 RK |
1929 | /* Find the inside of any subregs. */ |
1930 | while (GET_CODE (out) == SUBREG) | |
1931 | { | |
f8cfc6aa | 1932 | if (REG_P (SUBREG_REG (out)) |
ddef6bc7 JJ |
1933 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER) |
1934 | out_offset += subreg_regno_offset (REGNO (SUBREG_REG (out)), | |
1935 | GET_MODE (SUBREG_REG (out)), | |
1936 | SUBREG_BYTE (out), | |
1937 | GET_MODE (out)); | |
eab89b90 RK |
1938 | out = SUBREG_REG (out); |
1939 | } | |
1940 | while (GET_CODE (in) == SUBREG) | |
1941 | { | |
f8cfc6aa | 1942 | if (REG_P (SUBREG_REG (in)) |
ddef6bc7 JJ |
1943 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER) |
1944 | in_offset += subreg_regno_offset (REGNO (SUBREG_REG (in)), | |
1945 | GET_MODE (SUBREG_REG (in)), | |
1946 | SUBREG_BYTE (in), | |
1947 | GET_MODE (in)); | |
eab89b90 RK |
1948 | in = SUBREG_REG (in); |
1949 | } | |
1950 | ||
1951 | /* Narrow down the reg class, the same way push_reload will; | |
1952 | otherwise we might find a dummy now, but push_reload won't. */ | |
b5c82fa1 | 1953 | { |
55d796da | 1954 | enum reg_class preferred_class = PREFERRED_RELOAD_CLASS (in, rclass); |
e17e34d8 | 1955 | if (preferred_class != NO_REGS) |
55d796da | 1956 | rclass = preferred_class; |
b5c82fa1 | 1957 | } |
eab89b90 RK |
1958 | |
1959 | /* See if OUT will do. */ | |
f8cfc6aa | 1960 | if (REG_P (out) |
eab89b90 RK |
1961 | && REGNO (out) < FIRST_PSEUDO_REGISTER) |
1962 | { | |
770ae6cc | 1963 | unsigned int regno = REGNO (out) + out_offset; |
66fd46b6 | 1964 | unsigned int nwords = hard_regno_nregs[regno][outmode]; |
d3b9996a | 1965 | rtx saved_rtx; |
eab89b90 RK |
1966 | |
1967 | /* When we consider whether the insn uses OUT, | |
1968 | ignore references within IN. They don't prevent us | |
1969 | from copying IN into OUT, because those refs would | |
1970 | move into the insn that reloads IN. | |
1971 | ||
1972 | However, we only ignore IN in its role as this reload. | |
1973 | If the insn uses IN elsewhere and it contains OUT, | |
1974 | that counts. We can't be sure it's the "same" operand | |
1975 | so it might not go through this reload. */ | |
d3b9996a | 1976 | saved_rtx = *inloc; |
eab89b90 RK |
1977 | *inloc = const0_rtx; |
1978 | ||
1979 | if (regno < FIRST_PSEUDO_REGISTER | |
05fa709d | 1980 | && HARD_REGNO_MODE_OK (regno, outmode) |
eab89b90 RK |
1981 | && ! refers_to_regno_for_reload_p (regno, regno + nwords, |
1982 | PATTERN (this_insn), outloc)) | |
1983 | { | |
770ae6cc RK |
1984 | unsigned int i; |
1985 | ||
eab89b90 | 1986 | for (i = 0; i < nwords; i++) |
55d796da | 1987 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], |
eab89b90 RK |
1988 | regno + i)) |
1989 | break; | |
1990 | ||
1991 | if (i == nwords) | |
1992 | { | |
f8cfc6aa | 1993 | if (REG_P (real_out)) |
eab89b90 RK |
1994 | value = real_out; |
1995 | else | |
38a448ca | 1996 | value = gen_rtx_REG (outmode, regno); |
eab89b90 RK |
1997 | } |
1998 | } | |
1999 | ||
d3b9996a | 2000 | *inloc = saved_rtx; |
eab89b90 RK |
2001 | } |
2002 | ||
2003 | /* Consider using IN if OUT was not acceptable | |
2004 | or if OUT dies in this insn (like the quotient in a divmod insn). | |
2005 | We can't use IN unless it is dies in this insn, | |
2006 | which means we must know accurately which hard regs are live. | |
189086f9 RK |
2007 | Also, the result can't go in IN if IN is used within OUT, |
2008 | or if OUT is an earlyclobber and IN appears elsewhere in the insn. */ | |
eab89b90 | 2009 | if (hard_regs_live_known |
f8cfc6aa | 2010 | && REG_P (in) |
eab89b90 RK |
2011 | && REGNO (in) < FIRST_PSEUDO_REGISTER |
2012 | && (value == 0 | |
2013 | || find_reg_note (this_insn, REG_UNUSED, real_out)) | |
2014 | && find_reg_note (this_insn, REG_DEAD, real_in) | |
2015 | && !fixed_regs[REGNO (in)] | |
36b50568 RS |
2016 | && HARD_REGNO_MODE_OK (REGNO (in), |
2017 | /* The only case where out and real_out might | |
2018 | have different modes is where real_out | |
2019 | is a subreg, and in that case, out | |
2020 | has a real mode. */ | |
2021 | (GET_MODE (out) != VOIDmode | |
687b527d | 2022 | ? GET_MODE (out) : outmode)) |
687b527d | 2023 | && (ORIGINAL_REGNO (in) < FIRST_PSEUDO_REGISTER |
96cdfb52 EB |
2024 | /* However only do this if we can be sure that this input |
2025 | operand doesn't correspond with an uninitialized pseudo. | |
2026 | global can assign some hardreg to it that is the same as | |
2027 | the one assigned to a different, also live pseudo (as it | |
2028 | can ignore the conflict). We must never introduce writes | |
2029 | to such hardregs, as they would clobber the other live | |
2030 | pseudo. See PR 20973. */ | |
174b3107 | 2031 | || (!bitmap_bit_p (DF_LR_OUT (ENTRY_BLOCK_PTR), |
96cdfb52 EB |
2032 | ORIGINAL_REGNO (in)) |
2033 | /* Similarly, only do this if we can be sure that the death | |
2034 | note is still valid. global can assign some hardreg to | |
2035 | the pseudo referenced in the note and simultaneously a | |
2036 | subword of this hardreg to a different, also live pseudo, | |
2037 | because only another subword of the hardreg is actually | |
2038 | used in the insn. This cannot happen if the pseudo has | |
2039 | been assigned exactly one hardreg. See PR 33732. */ | |
2040 | && hard_regno_nregs[REGNO (in)][GET_MODE (in)] == 1))) | |
eab89b90 | 2041 | { |
770ae6cc | 2042 | unsigned int regno = REGNO (in) + in_offset; |
66fd46b6 | 2043 | unsigned int nwords = hard_regno_nregs[regno][inmode]; |
eab89b90 | 2044 | |
f4f4d0f8 | 2045 | if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, (rtx*) 0) |
eab89b90 | 2046 | && ! hard_reg_set_here_p (regno, regno + nwords, |
189086f9 RK |
2047 | PATTERN (this_insn)) |
2048 | && (! earlyclobber | |
2049 | || ! refers_to_regno_for_reload_p (regno, regno + nwords, | |
2050 | PATTERN (this_insn), inloc))) | |
eab89b90 | 2051 | { |
770ae6cc RK |
2052 | unsigned int i; |
2053 | ||
eab89b90 | 2054 | for (i = 0; i < nwords; i++) |
55d796da | 2055 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], |
eab89b90 RK |
2056 | regno + i)) |
2057 | break; | |
2058 | ||
2059 | if (i == nwords) | |
2060 | { | |
2061 | /* If we were going to use OUT as the reload reg | |
2062 | and changed our mind, it means OUT is a dummy that | |
2063 | dies here. So don't bother copying value to it. */ | |
2064 | if (for_real >= 0 && value == real_out) | |
eceef4c9 | 2065 | rld[for_real].out = 0; |
f8cfc6aa | 2066 | if (REG_P (real_in)) |
eab89b90 RK |
2067 | value = real_in; |
2068 | else | |
38a448ca | 2069 | value = gen_rtx_REG (inmode, regno); |
eab89b90 RK |
2070 | } |
2071 | } | |
2072 | } | |
2073 | ||
2074 | return value; | |
2075 | } | |
2076 | \f | |
2077 | /* This page contains subroutines used mainly for determining | |
2078 | whether the IN or an OUT of a reload can serve as the | |
2079 | reload register. */ | |
2080 | ||
4644aad4 RK |
2081 | /* Return 1 if X is an operand of an insn that is being earlyclobbered. */ |
2082 | ||
09a308fe | 2083 | int |
0c20a65f | 2084 | earlyclobber_operand_p (rtx x) |
4644aad4 RK |
2085 | { |
2086 | int i; | |
2087 | ||
2088 | for (i = 0; i < n_earlyclobbers; i++) | |
2089 | if (reload_earlyclobbers[i] == x) | |
2090 | return 1; | |
2091 | ||
2092 | return 0; | |
2093 | } | |
2094 | ||
eab89b90 RK |
2095 | /* Return 1 if expression X alters a hard reg in the range |
2096 | from BEG_REGNO (inclusive) to END_REGNO (exclusive), | |
2097 | either explicitly or in the guise of a pseudo-reg allocated to REGNO. | |
2098 | X should be the body of an instruction. */ | |
2099 | ||
2100 | static int | |
0c20a65f | 2101 | hard_reg_set_here_p (unsigned int beg_regno, unsigned int end_regno, rtx x) |
eab89b90 RK |
2102 | { |
2103 | if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
2104 | { | |
b3694847 | 2105 | rtx op0 = SET_DEST (x); |
770ae6cc | 2106 | |
eab89b90 RK |
2107 | while (GET_CODE (op0) == SUBREG) |
2108 | op0 = SUBREG_REG (op0); | |
f8cfc6aa | 2109 | if (REG_P (op0)) |
eab89b90 | 2110 | { |
770ae6cc RK |
2111 | unsigned int r = REGNO (op0); |
2112 | ||
eab89b90 RK |
2113 | /* See if this reg overlaps range under consideration. */ |
2114 | if (r < end_regno | |
09e18274 | 2115 | && end_hard_regno (GET_MODE (op0), r) > beg_regno) |
eab89b90 RK |
2116 | return 1; |
2117 | } | |
2118 | } | |
2119 | else if (GET_CODE (x) == PARALLEL) | |
2120 | { | |
b3694847 | 2121 | int i = XVECLEN (x, 0) - 1; |
770ae6cc | 2122 | |
eab89b90 RK |
2123 | for (; i >= 0; i--) |
2124 | if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i))) | |
2125 | return 1; | |
2126 | } | |
2127 | ||
2128 | return 0; | |
2129 | } | |
2130 | ||
2131 | /* Return 1 if ADDR is a valid memory address for mode MODE, | |
2132 | and check that each pseudo reg has the proper kind of | |
2133 | hard reg. */ | |
2134 | ||
2135 | int | |
0c20a65f | 2136 | strict_memory_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx addr) |
eab89b90 | 2137 | { |
c6c3dba9 | 2138 | #ifdef GO_IF_LEGITIMATE_ADDRESS |
eab89b90 RK |
2139 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); |
2140 | return 0; | |
2141 | ||
2142 | win: | |
2143 | return 1; | |
c6c3dba9 PB |
2144 | #else |
2145 | return targetm.legitimate_address_p (mode, addr, 1); | |
2146 | #endif | |
eab89b90 | 2147 | } |
eab89b90 RK |
2148 | \f |
2149 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
2150 | if they are the same hard reg, and has special hacks for | |
2151 | autoincrement and autodecrement. | |
2152 | This is specifically intended for find_reloads to use | |
2153 | in determining whether two operands match. | |
2154 | X is the operand whose number is the lower of the two. | |
2155 | ||
2156 | The value is 2 if Y contains a pre-increment that matches | |
2157 | a non-incrementing address in X. */ | |
2158 | ||
2159 | /* ??? To be completely correct, we should arrange to pass | |
2160 | for X the output operand and for Y the input operand. | |
2161 | For now, we assume that the output operand has the lower number | |
2162 | because that is natural in (SET output (... input ...)). */ | |
2163 | ||
2164 | int | |
0c20a65f | 2165 | operands_match_p (rtx x, rtx y) |
eab89b90 | 2166 | { |
b3694847 SS |
2167 | int i; |
2168 | RTX_CODE code = GET_CODE (x); | |
2169 | const char *fmt; | |
eab89b90 | 2170 | int success_2; |
05d10675 | 2171 | |
eab89b90 RK |
2172 | if (x == y) |
2173 | return 1; | |
f8cfc6aa JQ |
2174 | if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) |
2175 | && (REG_P (y) || (GET_CODE (y) == SUBREG | |
2176 | && REG_P (SUBREG_REG (y))))) | |
eab89b90 | 2177 | { |
b3694847 | 2178 | int j; |
eab89b90 RK |
2179 | |
2180 | if (code == SUBREG) | |
2181 | { | |
2182 | i = REGNO (SUBREG_REG (x)); | |
2183 | if (i >= FIRST_PSEUDO_REGISTER) | |
2184 | goto slow; | |
ddef6bc7 JJ |
2185 | i += subreg_regno_offset (REGNO (SUBREG_REG (x)), |
2186 | GET_MODE (SUBREG_REG (x)), | |
2187 | SUBREG_BYTE (x), | |
2188 | GET_MODE (x)); | |
eab89b90 RK |
2189 | } |
2190 | else | |
2191 | i = REGNO (x); | |
2192 | ||
2193 | if (GET_CODE (y) == SUBREG) | |
2194 | { | |
2195 | j = REGNO (SUBREG_REG (y)); | |
2196 | if (j >= FIRST_PSEUDO_REGISTER) | |
2197 | goto slow; | |
ddef6bc7 JJ |
2198 | j += subreg_regno_offset (REGNO (SUBREG_REG (y)), |
2199 | GET_MODE (SUBREG_REG (y)), | |
2200 | SUBREG_BYTE (y), | |
2201 | GET_MODE (y)); | |
eab89b90 RK |
2202 | } |
2203 | else | |
2204 | j = REGNO (y); | |
2205 | ||
dca52d80 | 2206 | /* On a WORDS_BIG_ENDIAN machine, point to the last register of a |
b436d712 DE |
2207 | multiple hard register group of scalar integer registers, so that |
2208 | for example (reg:DI 0) and (reg:SI 1) will be considered the same | |
2209 | register. */ | |
dca52d80 | 2210 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD |
b436d712 | 2211 | && SCALAR_INT_MODE_P (GET_MODE (x)) |
dca52d80 | 2212 | && i < FIRST_PSEUDO_REGISTER) |
66fd46b6 | 2213 | i += hard_regno_nregs[i][GET_MODE (x)] - 1; |
dca52d80 | 2214 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (y)) > UNITS_PER_WORD |
b436d712 | 2215 | && SCALAR_INT_MODE_P (GET_MODE (y)) |
dca52d80 | 2216 | && j < FIRST_PSEUDO_REGISTER) |
66fd46b6 | 2217 | j += hard_regno_nregs[j][GET_MODE (y)] - 1; |
dca52d80 | 2218 | |
eab89b90 RK |
2219 | return i == j; |
2220 | } | |
2221 | /* If two operands must match, because they are really a single | |
2222 | operand of an assembler insn, then two postincrements are invalid | |
2223 | because the assembler insn would increment only once. | |
09da1532 | 2224 | On the other hand, a postincrement matches ordinary indexing |
eab89b90 | 2225 | if the postincrement is the output operand. */ |
4b983fdc | 2226 | if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) |
eab89b90 RK |
2227 | return operands_match_p (XEXP (x, 0), y); |
2228 | /* Two preincrements are invalid | |
2229 | because the assembler insn would increment only once. | |
09da1532 | 2230 | On the other hand, a preincrement matches ordinary indexing |
eab89b90 RK |
2231 | if the preincrement is the input operand. |
2232 | In this case, return 2, since some callers need to do special | |
2233 | things when this happens. */ | |
4b983fdc RH |
2234 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC |
2235 | || GET_CODE (y) == PRE_MODIFY) | |
eab89b90 RK |
2236 | return operands_match_p (x, XEXP (y, 0)) ? 2 : 0; |
2237 | ||
2238 | slow: | |
2239 | ||
37cf6116 RH |
2240 | /* Now we have disposed of all the cases in which different rtx codes |
2241 | can match. */ | |
eab89b90 RK |
2242 | if (code != GET_CODE (y)) |
2243 | return 0; | |
eab89b90 RK |
2244 | |
2245 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
eab89b90 RK |
2246 | if (GET_MODE (x) != GET_MODE (y)) |
2247 | return 0; | |
2248 | ||
37cf6116 RH |
2249 | switch (code) |
2250 | { | |
2251 | case CONST_INT: | |
2252 | case CONST_DOUBLE: | |
091a3ac7 | 2253 | case CONST_FIXED: |
37cf6116 RH |
2254 | return 0; |
2255 | ||
2256 | case LABEL_REF: | |
2257 | return XEXP (x, 0) == XEXP (y, 0); | |
2258 | case SYMBOL_REF: | |
2259 | return XSTR (x, 0) == XSTR (y, 0); | |
2260 | ||
2261 | default: | |
2262 | break; | |
2263 | } | |
2264 | ||
eab89b90 RK |
2265 | /* Compare the elements. If any pair of corresponding elements |
2266 | fail to match, return 0 for the whole things. */ | |
2267 | ||
2268 | success_2 = 0; | |
2269 | fmt = GET_RTX_FORMAT (code); | |
2270 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2271 | { | |
91bb873f | 2272 | int val, j; |
eab89b90 RK |
2273 | switch (fmt[i]) |
2274 | { | |
fb3821f7 CH |
2275 | case 'w': |
2276 | if (XWINT (x, i) != XWINT (y, i)) | |
2277 | return 0; | |
2278 | break; | |
2279 | ||
eab89b90 RK |
2280 | case 'i': |
2281 | if (XINT (x, i) != XINT (y, i)) | |
2282 | return 0; | |
2283 | break; | |
2284 | ||
2285 | case 'e': | |
2286 | val = operands_match_p (XEXP (x, i), XEXP (y, i)); | |
2287 | if (val == 0) | |
2288 | return 0; | |
2289 | /* If any subexpression returns 2, | |
2290 | we should return 2 if we are successful. */ | |
2291 | if (val == 2) | |
2292 | success_2 = 1; | |
2293 | break; | |
2294 | ||
2295 | case '0': | |
2296 | break; | |
2297 | ||
91bb873f RH |
2298 | case 'E': |
2299 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
2300 | return 0; | |
2301 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
2302 | { | |
2303 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j)); | |
2304 | if (val == 0) | |
2305 | return 0; | |
2306 | if (val == 2) | |
2307 | success_2 = 1; | |
2308 | } | |
2309 | break; | |
2310 | ||
eab89b90 RK |
2311 | /* It is believed that rtx's at this level will never |
2312 | contain anything but integers and other rtx's, | |
2313 | except for within LABEL_REFs and SYMBOL_REFs. */ | |
2314 | default: | |
41374e13 | 2315 | gcc_unreachable (); |
eab89b90 RK |
2316 | } |
2317 | } | |
2318 | return 1 + success_2; | |
2319 | } | |
2320 | \f | |
eab89b90 | 2321 | /* Describe the range of registers or memory referenced by X. |
05d10675 | 2322 | If X is a register, set REG_FLAG and put the first register |
eab89b90 | 2323 | number into START and the last plus one into END. |
05d10675 | 2324 | If X is a memory reference, put a base address into BASE |
eab89b90 | 2325 | and a range of integer offsets into START and END. |
05d10675 | 2326 | If X is pushing on the stack, we can assume it causes no trouble, |
eab89b90 RK |
2327 | so we set the SAFE field. */ |
2328 | ||
2329 | static struct decomposition | |
0c20a65f | 2330 | decompose (rtx x) |
eab89b90 RK |
2331 | { |
2332 | struct decomposition val; | |
2333 | int all_const = 0; | |
2334 | ||
6de9cd9a DN |
2335 | memset (&val, 0, sizeof (val)); |
2336 | ||
41374e13 | 2337 | switch (GET_CODE (x)) |
eab89b90 | 2338 | { |
41374e13 NS |
2339 | case MEM: |
2340 | { | |
2341 | rtx base = NULL_RTX, offset = 0; | |
2342 | rtx addr = XEXP (x, 0); | |
2343 | ||
2344 | if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC | |
2345 | || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC) | |
2346 | { | |
2347 | val.base = XEXP (addr, 0); | |
2348 | val.start = -GET_MODE_SIZE (GET_MODE (x)); | |
2349 | val.end = GET_MODE_SIZE (GET_MODE (x)); | |
2350 | val.safe = REGNO (val.base) == STACK_POINTER_REGNUM; | |
2351 | return val; | |
2352 | } | |
2353 | ||
2354 | if (GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY) | |
2355 | { | |
2356 | if (GET_CODE (XEXP (addr, 1)) == PLUS | |
2357 | && XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0) | |
2358 | && CONSTANT_P (XEXP (XEXP (addr, 1), 1))) | |
2359 | { | |
2360 | val.base = XEXP (addr, 0); | |
2361 | val.start = -INTVAL (XEXP (XEXP (addr, 1), 1)); | |
2362 | val.end = INTVAL (XEXP (XEXP (addr, 1), 1)); | |
2363 | val.safe = REGNO (val.base) == STACK_POINTER_REGNUM; | |
2364 | return val; | |
2365 | } | |
2366 | } | |
2367 | ||
2368 | if (GET_CODE (addr) == CONST) | |
2369 | { | |
2370 | addr = XEXP (addr, 0); | |
2371 | all_const = 1; | |
2372 | } | |
2373 | if (GET_CODE (addr) == PLUS) | |
2374 | { | |
2375 | if (CONSTANT_P (XEXP (addr, 0))) | |
2376 | { | |
2377 | base = XEXP (addr, 1); | |
2378 | offset = XEXP (addr, 0); | |
2379 | } | |
2380 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2381 | { | |
2382 | base = XEXP (addr, 0); | |
2383 | offset = XEXP (addr, 1); | |
2384 | } | |
2385 | } | |
2386 | ||
2387 | if (offset == 0) | |
2388 | { | |
2389 | base = addr; | |
2390 | offset = const0_rtx; | |
2391 | } | |
2392 | if (GET_CODE (offset) == CONST) | |
2393 | offset = XEXP (offset, 0); | |
2394 | if (GET_CODE (offset) == PLUS) | |
2395 | { | |
481683e1 | 2396 | if (CONST_INT_P (XEXP (offset, 0))) |
41374e13 NS |
2397 | { |
2398 | base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 1)); | |
2399 | offset = XEXP (offset, 0); | |
2400 | } | |
481683e1 | 2401 | else if (CONST_INT_P (XEXP (offset, 1))) |
41374e13 NS |
2402 | { |
2403 | base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 0)); | |
2404 | offset = XEXP (offset, 1); | |
2405 | } | |
2406 | else | |
2407 | { | |
2408 | base = gen_rtx_PLUS (GET_MODE (base), base, offset); | |
2409 | offset = const0_rtx; | |
2410 | } | |
2411 | } | |
481683e1 | 2412 | else if (!CONST_INT_P (offset)) |
41374e13 NS |
2413 | { |
2414 | base = gen_rtx_PLUS (GET_MODE (base), base, offset); | |
2415 | offset = const0_rtx; | |
2416 | } | |
2417 | ||
2418 | if (all_const && GET_CODE (base) == PLUS) | |
2419 | base = gen_rtx_CONST (GET_MODE (base), base); | |
2420 | ||
481683e1 | 2421 | gcc_assert (CONST_INT_P (offset)); |
41374e13 NS |
2422 | |
2423 | val.start = INTVAL (offset); | |
2424 | val.end = val.start + GET_MODE_SIZE (GET_MODE (x)); | |
2425 | val.base = base; | |
2426 | } | |
2427 | break; | |
2428 | ||
2429 | case REG: | |
eab89b90 | 2430 | val.reg_flag = 1; |
05d10675 | 2431 | val.start = true_regnum (x); |
67468e8e | 2432 | if (val.start < 0 || val.start >= FIRST_PSEUDO_REGISTER) |
eab89b90 RK |
2433 | { |
2434 | /* A pseudo with no hard reg. */ | |
2435 | val.start = REGNO (x); | |
2436 | val.end = val.start + 1; | |
2437 | } | |
2438 | else | |
2439 | /* A hard reg. */ | |
09e18274 | 2440 | val.end = end_hard_regno (GET_MODE (x), val.start); |
41374e13 NS |
2441 | break; |
2442 | ||
2443 | case SUBREG: | |
f8cfc6aa | 2444 | if (!REG_P (SUBREG_REG (x))) |
eab89b90 RK |
2445 | /* This could be more precise, but it's good enough. */ |
2446 | return decompose (SUBREG_REG (x)); | |
2447 | val.reg_flag = 1; | |
05d10675 | 2448 | val.start = true_regnum (x); |
67468e8e | 2449 | if (val.start < 0 || val.start >= FIRST_PSEUDO_REGISTER) |
eab89b90 RK |
2450 | return decompose (SUBREG_REG (x)); |
2451 | else | |
2452 | /* A hard reg. */ | |
f1f4e530 | 2453 | val.end = val.start + subreg_nregs (x); |
41374e13 NS |
2454 | break; |
2455 | ||
2456 | case SCRATCH: | |
2457 | /* This hasn't been assigned yet, so it can't conflict yet. */ | |
2458 | val.safe = 1; | |
2459 | break; | |
2460 | ||
2461 | default: | |
2462 | gcc_assert (CONSTANT_P (x)); | |
2463 | val.safe = 1; | |
2464 | break; | |
eab89b90 | 2465 | } |
eab89b90 RK |
2466 | return val; |
2467 | } | |
2468 | ||
2469 | /* Return 1 if altering Y will not modify the value of X. | |
2470 | Y is also described by YDATA, which should be decompose (Y). */ | |
2471 | ||
2472 | static int | |
0c20a65f | 2473 | immune_p (rtx x, rtx y, struct decomposition ydata) |
eab89b90 RK |
2474 | { |
2475 | struct decomposition xdata; | |
2476 | ||
2477 | if (ydata.reg_flag) | |
f4f4d0f8 | 2478 | return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, (rtx*) 0); |
eab89b90 RK |
2479 | if (ydata.safe) |
2480 | return 1; | |
2481 | ||
41374e13 | 2482 | gcc_assert (MEM_P (y)); |
eab89b90 | 2483 | /* If Y is memory and X is not, Y can't affect X. */ |
3c0cb5de | 2484 | if (!MEM_P (x)) |
eab89b90 RK |
2485 | return 1; |
2486 | ||
4381f7c2 | 2487 | xdata = decompose (x); |
eab89b90 RK |
2488 | |
2489 | if (! rtx_equal_p (xdata.base, ydata.base)) | |
2490 | { | |
2491 | /* If bases are distinct symbolic constants, there is no overlap. */ | |
2492 | if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base)) | |
2493 | return 1; | |
2494 | /* Constants and stack slots never overlap. */ | |
2495 | if (CONSTANT_P (xdata.base) | |
2496 | && (ydata.base == frame_pointer_rtx | |
a36d4c62 | 2497 | || ydata.base == hard_frame_pointer_rtx |
eab89b90 RK |
2498 | || ydata.base == stack_pointer_rtx)) |
2499 | return 1; | |
2500 | if (CONSTANT_P (ydata.base) | |
2501 | && (xdata.base == frame_pointer_rtx | |
a36d4c62 | 2502 | || xdata.base == hard_frame_pointer_rtx |
eab89b90 RK |
2503 | || xdata.base == stack_pointer_rtx)) |
2504 | return 1; | |
2505 | /* If either base is variable, we don't know anything. */ | |
2506 | return 0; | |
2507 | } | |
2508 | ||
eab89b90 RK |
2509 | return (xdata.start >= ydata.end || ydata.start >= xdata.end); |
2510 | } | |
44ace968 | 2511 | |
f72aed24 | 2512 | /* Similar, but calls decompose. */ |
44ace968 JW |
2513 | |
2514 | int | |
0c20a65f | 2515 | safe_from_earlyclobber (rtx op, rtx clobber) |
44ace968 JW |
2516 | { |
2517 | struct decomposition early_data; | |
2518 | ||
2519 | early_data = decompose (clobber); | |
2520 | return immune_p (op, clobber, early_data); | |
2521 | } | |
eab89b90 RK |
2522 | \f |
2523 | /* Main entry point of this file: search the body of INSN | |
2524 | for values that need reloading and record them with push_reload. | |
2525 | REPLACE nonzero means record also where the values occur | |
2526 | so that subst_reloads can be used. | |
2527 | ||
2528 | IND_LEVELS says how many levels of indirection are supported by this | |
2529 | machine; a value of zero means that a memory reference is not a valid | |
2530 | memory address. | |
2531 | ||
2532 | LIVE_KNOWN says we have valid information about which hard | |
2533 | regs are live at each point in the program; this is true when | |
2534 | we are called from global_alloc but false when stupid register | |
2535 | allocation has been done. | |
2536 | ||
2537 | RELOAD_REG_P if nonzero is a vector indexed by hard reg number | |
2538 | which is nonnegative if the reg has been commandeered for reloading into. | |
2539 | It is copied into STATIC_RELOAD_REG_P and referenced from there | |
cb2afeb3 | 2540 | by various subroutines. |
eab89b90 | 2541 | |
cb2afeb3 R |
2542 | Return TRUE if some operands need to be changed, because of swapping |
2543 | commutative operands, reg_equiv_address substitution, or whatever. */ | |
2544 | ||
2545 | int | |
0c20a65f AJ |
2546 | find_reloads (rtx insn, int replace, int ind_levels, int live_known, |
2547 | short *reload_reg_p) | |
eab89b90 | 2548 | { |
b3694847 SS |
2549 | int insn_code_number; |
2550 | int i, j; | |
eab89b90 | 2551 | int noperands; |
eab89b90 RK |
2552 | /* These start out as the constraints for the insn |
2553 | and they are chewed up as we consider alternatives. */ | |
7ac28727 | 2554 | const char *constraints[MAX_RECOG_OPERANDS]; |
eab89b90 RK |
2555 | /* These are the preferred classes for an operand, or NO_REGS if it isn't |
2556 | a register. */ | |
2557 | enum reg_class preferred_class[MAX_RECOG_OPERANDS]; | |
2558 | char pref_or_nothing[MAX_RECOG_OPERANDS]; | |
0b540f12 UW |
2559 | /* Nonzero for a MEM operand whose entire address needs a reload. |
2560 | May be -1 to indicate the entire address may or may not need a reload. */ | |
eab89b90 | 2561 | int address_reloaded[MAX_RECOG_OPERANDS]; |
0b540f12 UW |
2562 | /* Nonzero for an address operand that needs to be completely reloaded. |
2563 | May be -1 to indicate the entire operand may or may not need a reload. */ | |
9537511b | 2564 | int address_operand_reloaded[MAX_RECOG_OPERANDS]; |
a8c9daeb RK |
2565 | /* Value of enum reload_type to use for operand. */ |
2566 | enum reload_type operand_type[MAX_RECOG_OPERANDS]; | |
2567 | /* Value of enum reload_type to use within address of operand. */ | |
2568 | enum reload_type address_type[MAX_RECOG_OPERANDS]; | |
2569 | /* Save the usage of each operand. */ | |
2570 | enum reload_usage { RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE } modified[MAX_RECOG_OPERANDS]; | |
eab89b90 RK |
2571 | int no_input_reloads = 0, no_output_reloads = 0; |
2572 | int n_alternatives; | |
bbbbb16a | 2573 | enum reg_class this_alternative[MAX_RECOG_OPERANDS]; |
69add2a8 | 2574 | char this_alternative_match_win[MAX_RECOG_OPERANDS]; |
eab89b90 RK |
2575 | char this_alternative_win[MAX_RECOG_OPERANDS]; |
2576 | char this_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2577 | char this_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2578 | int this_alternative_matches[MAX_RECOG_OPERANDS]; | |
2579 | int swapped; | |
2580 | int goal_alternative[MAX_RECOG_OPERANDS]; | |
2581 | int this_alternative_number; | |
a544cfd2 | 2582 | int goal_alternative_number = 0; |
eab89b90 RK |
2583 | int operand_reloadnum[MAX_RECOG_OPERANDS]; |
2584 | int goal_alternative_matches[MAX_RECOG_OPERANDS]; | |
2585 | int goal_alternative_matched[MAX_RECOG_OPERANDS]; | |
69add2a8 | 2586 | char goal_alternative_match_win[MAX_RECOG_OPERANDS]; |
eab89b90 RK |
2587 | char goal_alternative_win[MAX_RECOG_OPERANDS]; |
2588 | char goal_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2589 | char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2590 | int goal_alternative_swapped; | |
eab89b90 RK |
2591 | int best; |
2592 | int commutative; | |
2593 | char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
2594 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
2595 | rtx body = PATTERN (insn); | |
2596 | rtx set = single_set (insn); | |
a544cfd2 | 2597 | int goal_earlyclobber = 0, this_earlyclobber; |
eab89b90 | 2598 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
cb2afeb3 | 2599 | int retval = 0; |
eab89b90 RK |
2600 | |
2601 | this_insn = insn; | |
eab89b90 RK |
2602 | n_reloads = 0; |
2603 | n_replacements = 0; | |
eab89b90 RK |
2604 | n_earlyclobbers = 0; |
2605 | replace_reloads = replace; | |
2606 | hard_regs_live_known = live_known; | |
2607 | static_reload_reg_p = reload_reg_p; | |
2608 | ||
2609 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads; | |
2610 | neither are insns that SET cc0. Insns that use CC0 are not allowed | |
2611 | to have any input reloads. */ | |
4b4bf941 | 2612 | if (JUMP_P (insn) || CALL_P (insn)) |
eab89b90 RK |
2613 | no_output_reloads = 1; |
2614 | ||
2615 | #ifdef HAVE_cc0 | |
2616 | if (reg_referenced_p (cc0_rtx, PATTERN (insn))) | |
2617 | no_input_reloads = 1; | |
2618 | if (reg_set_p (cc0_rtx, PATTERN (insn))) | |
2619 | no_output_reloads = 1; | |
2620 | #endif | |
05d10675 | 2621 | |
0dadecf6 RK |
2622 | #ifdef SECONDARY_MEMORY_NEEDED |
2623 | /* The eliminated forms of any secondary memory locations are per-insn, so | |
2624 | clear them out here. */ | |
2625 | ||
048b0d2e JH |
2626 | if (secondary_memlocs_elim_used) |
2627 | { | |
2628 | memset (secondary_memlocs_elim, 0, | |
2629 | sizeof (secondary_memlocs_elim[0]) * secondary_memlocs_elim_used); | |
2630 | secondary_memlocs_elim_used = 0; | |
2631 | } | |
0dadecf6 RK |
2632 | #endif |
2633 | ||
0a578fee BS |
2634 | /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it |
2635 | is cheap to move between them. If it is not, there may not be an insn | |
2636 | to do the copy, so we may need a reload. */ | |
2637 | if (GET_CODE (body) == SET | |
f8cfc6aa | 2638 | && REG_P (SET_DEST (body)) |
0a578fee | 2639 | && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER |
f8cfc6aa | 2640 | && REG_P (SET_SRC (body)) |
0a578fee | 2641 | && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER |
e56b4594 AO |
2642 | && REGISTER_MOVE_COST (GET_MODE (SET_SRC (body)), |
2643 | REGNO_REG_CLASS (REGNO (SET_SRC (body))), | |
0a578fee BS |
2644 | REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2) |
2645 | return 0; | |
eab89b90 | 2646 | |
0a578fee | 2647 | extract_insn (insn); |
eab89b90 | 2648 | |
1ccbefce RH |
2649 | noperands = reload_n_operands = recog_data.n_operands; |
2650 | n_alternatives = recog_data.n_alternatives; | |
eab89b90 | 2651 | |
0a578fee BS |
2652 | /* Just return "no reloads" if insn has no operands with constraints. */ |
2653 | if (noperands == 0 || n_alternatives == 0) | |
2654 | return 0; | |
eab89b90 | 2655 | |
0a578fee BS |
2656 | insn_code_number = INSN_CODE (insn); |
2657 | this_insn_is_asm = insn_code_number < 0; | |
eab89b90 | 2658 | |
f428f252 KG |
2659 | memcpy (operand_mode, recog_data.operand_mode, |
2660 | noperands * sizeof (enum machine_mode)); | |
7ac28727 AK |
2661 | memcpy (constraints, recog_data.constraints, |
2662 | noperands * sizeof (const char *)); | |
eab89b90 RK |
2663 | |
2664 | commutative = -1; | |
2665 | ||
2666 | /* If we will need to know, later, whether some pair of operands | |
2667 | are the same, we must compare them now and save the result. | |
2668 | Reloading the base and index registers will clobber them | |
2669 | and afterward they will fail to match. */ | |
2670 | ||
2671 | for (i = 0; i < noperands; i++) | |
2672 | { | |
7ac28727 | 2673 | const char *p; |
b3694847 | 2674 | int c; |
7ac28727 | 2675 | char *end; |
eab89b90 | 2676 | |
1ccbefce | 2677 | substed_operand[i] = recog_data.operand[i]; |
eab89b90 RK |
2678 | p = constraints[i]; |
2679 | ||
a8c9daeb RK |
2680 | modified[i] = RELOAD_READ; |
2681 | ||
05d10675 | 2682 | /* Scan this operand's constraint to see if it is an output operand, |
a8c9daeb | 2683 | an in-out operand, is commutative, or should match another. */ |
eab89b90 | 2684 | |
97488870 | 2685 | while ((c = *p)) |
a8c9daeb | 2686 | { |
97488870 | 2687 | p += CONSTRAINT_LEN (c, p); |
f345f21a | 2688 | switch (c) |
a8c9daeb | 2689 | { |
f345f21a JH |
2690 | case '=': |
2691 | modified[i] = RELOAD_WRITE; | |
2692 | break; | |
2693 | case '+': | |
2694 | modified[i] = RELOAD_READ_WRITE; | |
2695 | break; | |
2696 | case '%': | |
2697 | { | |
2698 | /* The last operand should not be marked commutative. */ | |
41374e13 | 2699 | gcc_assert (i != noperands - 1); |
f345f21a JH |
2700 | |
2701 | /* We currently only support one commutative pair of | |
2702 | operands. Some existing asm code currently uses more | |
2703 | than one pair. Previously, that would usually work, | |
2704 | but sometimes it would crash the compiler. We | |
2705 | continue supporting that case as well as we can by | |
2706 | silently ignoring all but the first pair. In the | |
2707 | future we may handle it correctly. */ | |
2708 | if (commutative < 0) | |
2709 | commutative = i; | |
41374e13 NS |
2710 | else |
2711 | gcc_assert (this_insn_is_asm); | |
f345f21a JH |
2712 | } |
2713 | break; | |
2714 | /* Use of ISDIGIT is tempting here, but it may get expensive because | |
2715 | of locale support we don't want. */ | |
2716 | case '0': case '1': case '2': case '3': case '4': | |
2717 | case '5': case '6': case '7': case '8': case '9': | |
2718 | { | |
7ac28727 AK |
2719 | c = strtoul (p - 1, &end, 10); |
2720 | p = end; | |
f345f21a JH |
2721 | |
2722 | operands_match[c][i] | |
2723 | = operands_match_p (recog_data.operand[c], | |
2724 | recog_data.operand[i]); | |
2725 | ||
2726 | /* An operand may not match itself. */ | |
41374e13 | 2727 | gcc_assert (c != i); |
f345f21a JH |
2728 | |
2729 | /* If C can be commuted with C+1, and C might need to match I, | |
2730 | then C+1 might also need to match I. */ | |
2731 | if (commutative >= 0) | |
2732 | { | |
2733 | if (c == commutative || c == commutative + 1) | |
2734 | { | |
2735 | int other = c + (c == commutative ? 1 : -1); | |
2736 | operands_match[other][i] | |
2737 | = operands_match_p (recog_data.operand[other], | |
2738 | recog_data.operand[i]); | |
2739 | } | |
2740 | if (i == commutative || i == commutative + 1) | |
2741 | { | |
2742 | int other = i + (i == commutative ? 1 : -1); | |
2743 | operands_match[c][other] | |
2744 | = operands_match_p (recog_data.operand[c], | |
2745 | recog_data.operand[other]); | |
2746 | } | |
2747 | /* Note that C is supposed to be less than I. | |
2748 | No need to consider altering both C and I because in | |
2749 | that case we would alter one into the other. */ | |
2750 | } | |
2751 | } | |
a8c9daeb RK |
2752 | } |
2753 | } | |
eab89b90 RK |
2754 | } |
2755 | ||
2756 | /* Examine each operand that is a memory reference or memory address | |
2757 | and reload parts of the addresses into index registers. | |
eab89b90 RK |
2758 | Also here any references to pseudo regs that didn't get hard regs |
2759 | but are equivalent to constants get replaced in the insn itself | |
05d10675 | 2760 | with those constants. Nobody will ever see them again. |
eab89b90 RK |
2761 | |
2762 | Finally, set up the preferred classes of each operand. */ | |
2763 | ||
2764 | for (i = 0; i < noperands; i++) | |
2765 | { | |
b3694847 | 2766 | RTX_CODE code = GET_CODE (recog_data.operand[i]); |
a8c9daeb | 2767 | |
eab89b90 | 2768 | address_reloaded[i] = 0; |
9537511b | 2769 | address_operand_reloaded[i] = 0; |
a8c9daeb RK |
2770 | operand_type[i] = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT |
2771 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT | |
2772 | : RELOAD_OTHER); | |
2773 | address_type[i] | |
2774 | = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT_ADDRESS | |
2775 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT_ADDRESS | |
2776 | : RELOAD_OTHER); | |
eab89b90 | 2777 | |
0d38001f RS |
2778 | if (*constraints[i] == 0) |
2779 | /* Ignore things like match_operator operands. */ | |
2780 | ; | |
ccfc6cc8 | 2781 | else if (constraints[i][0] == 'p' |
97488870 | 2782 | || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i])) |
eab89b90 | 2783 | { |
9537511b UW |
2784 | address_operand_reloaded[i] |
2785 | = find_reloads_address (recog_data.operand_mode[i], (rtx*) 0, | |
2786 | recog_data.operand[i], | |
2787 | recog_data.operand_loc[i], | |
2788 | i, operand_type[i], ind_levels, insn); | |
b685dbae | 2789 | |
05d10675 | 2790 | /* If we now have a simple operand where we used to have a |
b685dbae | 2791 | PLUS or MULT, re-recognize and try again. */ |
ec8e098d | 2792 | if ((OBJECT_P (*recog_data.operand_loc[i]) |
1ccbefce RH |
2793 | || GET_CODE (*recog_data.operand_loc[i]) == SUBREG) |
2794 | && (GET_CODE (recog_data.operand[i]) == MULT | |
2795 | || GET_CODE (recog_data.operand[i]) == PLUS)) | |
b685dbae RK |
2796 | { |
2797 | INSN_CODE (insn) = -1; | |
cb2afeb3 R |
2798 | retval = find_reloads (insn, replace, ind_levels, live_known, |
2799 | reload_reg_p); | |
2800 | return retval; | |
b685dbae RK |
2801 | } |
2802 | ||
1ccbefce RH |
2803 | recog_data.operand[i] = *recog_data.operand_loc[i]; |
2804 | substed_operand[i] = recog_data.operand[i]; | |
9537511b UW |
2805 | |
2806 | /* Address operands are reloaded in their existing mode, | |
2807 | no matter what is specified in the machine description. */ | |
2808 | operand_mode[i] = GET_MODE (recog_data.operand[i]); | |
eab89b90 RK |
2809 | } |
2810 | else if (code == MEM) | |
2811 | { | |
ab87f8c8 | 2812 | address_reloaded[i] |
1ccbefce RH |
2813 | = find_reloads_address (GET_MODE (recog_data.operand[i]), |
2814 | recog_data.operand_loc[i], | |
2815 | XEXP (recog_data.operand[i], 0), | |
2816 | &XEXP (recog_data.operand[i], 0), | |
ab87f8c8 | 2817 | i, address_type[i], ind_levels, insn); |
1ccbefce RH |
2818 | recog_data.operand[i] = *recog_data.operand_loc[i]; |
2819 | substed_operand[i] = recog_data.operand[i]; | |
eab89b90 RK |
2820 | } |
2821 | else if (code == SUBREG) | |
b60a8416 | 2822 | { |
1ccbefce | 2823 | rtx reg = SUBREG_REG (recog_data.operand[i]); |
b60a8416 | 2824 | rtx op |
1ccbefce | 2825 | = find_reloads_toplev (recog_data.operand[i], i, address_type[i], |
b60a8416 R |
2826 | ind_levels, |
2827 | set != 0 | |
1ccbefce | 2828 | && &SET_DEST (set) == recog_data.operand_loc[i], |
9246aadb AH |
2829 | insn, |
2830 | &address_reloaded[i]); | |
b60a8416 R |
2831 | |
2832 | /* If we made a MEM to load (a part of) the stackslot of a pseudo | |
2833 | that didn't get a hard register, emit a USE with a REG_EQUAL | |
2834 | note in front so that we might inherit a previous, possibly | |
2835 | wider reload. */ | |
05d10675 | 2836 | |
cb2afeb3 | 2837 | if (replace |
3c0cb5de | 2838 | && MEM_P (op) |
f8cfc6aa | 2839 | && REG_P (reg) |
b60a8416 | 2840 | && (GET_MODE_SIZE (GET_MODE (reg)) |
c07fdd94 RS |
2841 | >= GET_MODE_SIZE (GET_MODE (op))) |
2842 | && reg_equiv_constant[REGNO (reg)] == 0) | |
3d238248 JJ |
2843 | set_unique_reg_note (emit_insn_before (gen_rtx_USE (VOIDmode, reg), |
2844 | insn), | |
2845 | REG_EQUAL, reg_equiv_memory_loc[REGNO (reg)]); | |
b60a8416 | 2846 | |
1ccbefce | 2847 | substed_operand[i] = recog_data.operand[i] = op; |
b60a8416 | 2848 | } |
ec8e098d | 2849 | else if (code == PLUS || GET_RTX_CLASS (code) == RTX_UNARY) |
ff428c90 ILT |
2850 | /* We can get a PLUS as an "operand" as a result of register |
2851 | elimination. See eliminate_regs and gen_reload. We handle | |
2852 | a unary operator by reloading the operand. */ | |
1ccbefce RH |
2853 | substed_operand[i] = recog_data.operand[i] |
2854 | = find_reloads_toplev (recog_data.operand[i], i, address_type[i], | |
9246aadb AH |
2855 | ind_levels, 0, insn, |
2856 | &address_reloaded[i]); | |
eab89b90 RK |
2857 | else if (code == REG) |
2858 | { | |
2859 | /* This is equivalent to calling find_reloads_toplev. | |
2860 | The code is duplicated for speed. | |
2861 | When we find a pseudo always equivalent to a constant, | |
2862 | we replace it by the constant. We must be sure, however, | |
2863 | that we don't try to replace it in the insn in which it | |
6d2f8887 | 2864 | is being set. */ |
b3694847 | 2865 | int regno = REGNO (recog_data.operand[i]); |
eab89b90 | 2866 | if (reg_equiv_constant[regno] != 0 |
1ccbefce | 2867 | && (set == 0 || &SET_DEST (set) != recog_data.operand_loc[i])) |
726e2d54 JW |
2868 | { |
2869 | /* Record the existing mode so that the check if constants are | |
eceef4c9 | 2870 | allowed will work when operand_mode isn't specified. */ |
726e2d54 JW |
2871 | |
2872 | if (operand_mode[i] == VOIDmode) | |
1ccbefce | 2873 | operand_mode[i] = GET_MODE (recog_data.operand[i]); |
726e2d54 | 2874 | |
1ccbefce | 2875 | substed_operand[i] = recog_data.operand[i] |
05d10675 | 2876 | = reg_equiv_constant[regno]; |
726e2d54 | 2877 | } |
cb2afeb3 R |
2878 | if (reg_equiv_memory_loc[regno] != 0 |
2879 | && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)) | |
2880 | /* We need not give a valid is_set_dest argument since the case | |
2881 | of a constant equivalence was checked above. */ | |
1ccbefce RH |
2882 | substed_operand[i] = recog_data.operand[i] |
2883 | = find_reloads_toplev (recog_data.operand[i], i, address_type[i], | |
9246aadb AH |
2884 | ind_levels, 0, insn, |
2885 | &address_reloaded[i]); | |
eab89b90 | 2886 | } |
aaf9712e RS |
2887 | /* If the operand is still a register (we didn't replace it with an |
2888 | equivalent), get the preferred class to reload it into. */ | |
1ccbefce | 2889 | code = GET_CODE (recog_data.operand[i]); |
aaf9712e | 2890 | preferred_class[i] |
1ccbefce RH |
2891 | = ((code == REG && REGNO (recog_data.operand[i]) |
2892 | >= FIRST_PSEUDO_REGISTER) | |
2893 | ? reg_preferred_class (REGNO (recog_data.operand[i])) | |
2894 | : NO_REGS); | |
aaf9712e | 2895 | pref_or_nothing[i] |
1ccbefce RH |
2896 | = (code == REG |
2897 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER | |
2898 | && reg_alternate_class (REGNO (recog_data.operand[i])) == NO_REGS); | |
eab89b90 RK |
2899 | } |
2900 | ||
2901 | /* If this is simply a copy from operand 1 to operand 0, merge the | |
2902 | preferred classes for the operands. */ | |
1ccbefce RH |
2903 | if (set != 0 && noperands >= 2 && recog_data.operand[0] == SET_DEST (set) |
2904 | && recog_data.operand[1] == SET_SRC (set)) | |
eab89b90 RK |
2905 | { |
2906 | preferred_class[0] = preferred_class[1] | |
2907 | = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]]; | |
2908 | pref_or_nothing[0] |= pref_or_nothing[1]; | |
2909 | pref_or_nothing[1] |= pref_or_nothing[0]; | |
2910 | } | |
2911 | ||
2912 | /* Now see what we need for pseudo-regs that didn't get hard regs | |
2913 | or got the wrong kind of hard reg. For this, we must consider | |
2914 | all the operands together against the register constraints. */ | |
2915 | ||
812f2051 | 2916 | best = MAX_RECOG_OPERANDS * 2 + 600; |
eab89b90 RK |
2917 | |
2918 | swapped = 0; | |
2919 | goal_alternative_swapped = 0; | |
2920 | try_swapped: | |
2921 | ||
2922 | /* The constraints are made of several alternatives. | |
2923 | Each operand's constraint looks like foo,bar,... with commas | |
2924 | separating the alternatives. The first alternatives for all | |
2925 | operands go together, the second alternatives go together, etc. | |
2926 | ||
2927 | First loop over alternatives. */ | |
2928 | ||
2929 | for (this_alternative_number = 0; | |
2930 | this_alternative_number < n_alternatives; | |
2931 | this_alternative_number++) | |
2932 | { | |
2933 | /* Loop over operands for one constraint alternative. */ | |
2934 | /* LOSERS counts those that don't fit this alternative | |
2935 | and would require loading. */ | |
2936 | int losers = 0; | |
2937 | /* BAD is set to 1 if it some operand can't fit this alternative | |
2938 | even after reloading. */ | |
2939 | int bad = 0; | |
2940 | /* REJECT is a count of how undesirable this alternative says it is | |
2941 | if any reloading is required. If the alternative matches exactly | |
2942 | then REJECT is ignored, but otherwise it gets this much | |
05d10675 | 2943 | counted against it in addition to the reloading needed. Each |
eab89b90 RK |
2944 | ? counts three times here since we want the disparaging caused by |
2945 | a bad register class to only count 1/3 as much. */ | |
2946 | int reject = 0; | |
2947 | ||
7ac28727 AK |
2948 | if (!recog_data.alternative_enabled_p[this_alternative_number]) |
2949 | { | |
2950 | int i; | |
2951 | ||
2952 | for (i = 0; i < recog_data.n_operands; i++) | |
2953 | constraints[i] = skip_alternative (constraints[i]); | |
2954 | ||
2955 | continue; | |
2956 | } | |
2957 | ||
eab89b90 RK |
2958 | this_earlyclobber = 0; |
2959 | ||
2960 | for (i = 0; i < noperands; i++) | |
2961 | { | |
7ac28727 | 2962 | const char *p = constraints[i]; |
97488870 R |
2963 | char *end; |
2964 | int len; | |
b3694847 | 2965 | int win = 0; |
69add2a8 | 2966 | int did_match = 0; |
82efa2e5 | 2967 | /* 0 => this operand can be reloaded somehow for this alternative. */ |
eab89b90 RK |
2968 | int badop = 1; |
2969 | /* 0 => this operand can be reloaded if the alternative allows regs. */ | |
2970 | int winreg = 0; | |
2971 | int c; | |
97488870 | 2972 | int m; |
b3694847 | 2973 | rtx operand = recog_data.operand[i]; |
eab89b90 RK |
2974 | int offset = 0; |
2975 | /* Nonzero means this is a MEM that must be reloaded into a reg | |
2976 | regardless of what the constraint says. */ | |
2977 | int force_reload = 0; | |
2978 | int offmemok = 0; | |
9d926da5 RK |
2979 | /* Nonzero if a constant forced into memory would be OK for this |
2980 | operand. */ | |
2981 | int constmemok = 0; | |
eab89b90 RK |
2982 | int earlyclobber = 0; |
2983 | ||
ff428c90 | 2984 | /* If the predicate accepts a unary operator, it means that |
05d10675 | 2985 | we need to reload the operand, but do not do this for |
ad729076 | 2986 | match_operator and friends. */ |
ec8e098d | 2987 | if (UNARY_P (operand) && *p != 0) |
ff428c90 ILT |
2988 | operand = XEXP (operand, 0); |
2989 | ||
eab89b90 RK |
2990 | /* If the operand is a SUBREG, extract |
2991 | the REG or MEM (or maybe even a constant) within. | |
2992 | (Constants can occur as a result of reg_equiv_constant.) */ | |
2993 | ||
2994 | while (GET_CODE (operand) == SUBREG) | |
2995 | { | |
ddef6bc7 JJ |
2996 | /* Offset only matters when operand is a REG and |
2997 | it is a hard reg. This is because it is passed | |
2998 | to reg_fits_class_p if it is a REG and all pseudos | |
2999 | return 0 from that function. */ | |
f8cfc6aa | 3000 | if (REG_P (SUBREG_REG (operand)) |
ddef6bc7 JJ |
3001 | && REGNO (SUBREG_REG (operand)) < FIRST_PSEUDO_REGISTER) |
3002 | { | |
eef302d2 RS |
3003 | if (simplify_subreg_regno (REGNO (SUBREG_REG (operand)), |
3004 | GET_MODE (SUBREG_REG (operand)), | |
3005 | SUBREG_BYTE (operand), | |
3006 | GET_MODE (operand)) < 0) | |
3007 | force_reload = 1; | |
ddef6bc7 JJ |
3008 | offset += subreg_regno_offset (REGNO (SUBREG_REG (operand)), |
3009 | GET_MODE (SUBREG_REG (operand)), | |
3010 | SUBREG_BYTE (operand), | |
3011 | GET_MODE (operand)); | |
3012 | } | |
eab89b90 | 3013 | operand = SUBREG_REG (operand); |
38e01259 | 3014 | /* Force reload if this is a constant or PLUS or if there may |
a61c98cf RK |
3015 | be a problem accessing OPERAND in the outer mode. */ |
3016 | if (CONSTANT_P (operand) | |
ca769828 | 3017 | || GET_CODE (operand) == PLUS |
03b72c86 RK |
3018 | /* We must force a reload of paradoxical SUBREGs |
3019 | of a MEM because the alignment of the inner value | |
beb5a9b8 RK |
3020 | may not be enough to do the outer reference. On |
3021 | big-endian machines, it may also reference outside | |
3022 | the object. | |
03b72c86 RK |
3023 | |
3024 | On machines that extend byte operations and we have a | |
486d8509 RK |
3025 | SUBREG where both the inner and outer modes are no wider |
3026 | than a word and the inner mode is narrower, is integral, | |
3027 | and gets extended when loaded from memory, combine.c has | |
3028 | made assumptions about the behavior of the machine in such | |
03b72c86 RK |
3029 | register access. If the data is, in fact, in memory we |
3030 | must always load using the size assumed to be in the | |
05d10675 | 3031 | register and let the insn do the different-sized |
5ec105cd RH |
3032 | accesses. |
3033 | ||
05d10675 | 3034 | This is doubly true if WORD_REGISTER_OPERATIONS. In |
5ec105cd | 3035 | this case eliminate_regs has left non-paradoxical |
bd235d86 | 3036 | subregs for push_reload to see. Make sure it does |
5ec105cd RH |
3037 | by forcing the reload. |
3038 | ||
3039 | ??? When is it right at this stage to have a subreg | |
14b493d6 | 3040 | of a mem that is _not_ to be handled specially? IMO |
5ec105cd | 3041 | those should have been reduced to just a mem. */ |
3c0cb5de | 3042 | || ((MEM_P (operand) |
f8cfc6aa | 3043 | || (REG_P (operand) |
a61c98cf | 3044 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) |
5ec105cd | 3045 | #ifndef WORD_REGISTER_OPERATIONS |
03b72c86 RK |
3046 | && (((GET_MODE_BITSIZE (GET_MODE (operand)) |
3047 | < BIGGEST_ALIGNMENT) | |
3048 | && (GET_MODE_SIZE (operand_mode[i]) | |
3049 | > GET_MODE_SIZE (GET_MODE (operand)))) | |
b605eb59 | 3050 | || BYTES_BIG_ENDIAN |
03b72c86 RK |
3051 | #ifdef LOAD_EXTEND_OP |
3052 | || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD | |
3053 | && (GET_MODE_SIZE (GET_MODE (operand)) | |
3054 | <= UNITS_PER_WORD) | |
3055 | && (GET_MODE_SIZE (operand_mode[i]) | |
486d8509 RK |
3056 | > GET_MODE_SIZE (GET_MODE (operand))) |
3057 | && INTEGRAL_MODE_P (GET_MODE (operand)) | |
f822d252 | 3058 | && LOAD_EXTEND_OP (GET_MODE (operand)) != UNKNOWN) |
46da6b3a | 3059 | #endif |
5ec105cd RH |
3060 | ) |
3061 | #endif | |
3062 | ) | |
ddef6bc7 | 3063 | ) |
eab89b90 RK |
3064 | force_reload = 1; |
3065 | } | |
3066 | ||
bbbbb16a | 3067 | this_alternative[i] = NO_REGS; |
eab89b90 | 3068 | this_alternative_win[i] = 0; |
69add2a8 | 3069 | this_alternative_match_win[i] = 0; |
eab89b90 RK |
3070 | this_alternative_offmemok[i] = 0; |
3071 | this_alternative_earlyclobber[i] = 0; | |
3072 | this_alternative_matches[i] = -1; | |
3073 | ||
3074 | /* An empty constraint or empty alternative | |
3075 | allows anything which matched the pattern. */ | |
3076 | if (*p == 0 || *p == ',') | |
3077 | win = 1, badop = 0; | |
3078 | ||
3079 | /* Scan this alternative's specs for this operand; | |
3080 | set WIN if the operand fits any letter in this alternative. | |
3081 | Otherwise, clear BADOP if this operand could | |
3082 | fit some letter after reloads, | |
3083 | or set WINREG if this operand could fit after reloads | |
3084 | provided the constraint allows some registers. */ | |
3085 | ||
97488870 R |
3086 | do |
3087 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
eab89b90 | 3088 | { |
97488870 R |
3089 | case '\0': |
3090 | len = 0; | |
3091 | break; | |
3092 | case ',': | |
3093 | c = '\0'; | |
3094 | break; | |
3095 | ||
c5c76735 | 3096 | case '=': case '+': case '*': |
eab89b90 RK |
3097 | break; |
3098 | ||
3099 | case '%': | |
7e3aa041 ILT |
3100 | /* We only support one commutative marker, the first |
3101 | one. We already set commutative above. */ | |
eab89b90 RK |
3102 | break; |
3103 | ||
3104 | case '?': | |
812f2051 | 3105 | reject += 6; |
eab89b90 RK |
3106 | break; |
3107 | ||
3108 | case '!': | |
812f2051 | 3109 | reject = 600; |
eab89b90 RK |
3110 | break; |
3111 | ||
3112 | case '#': | |
3113 | /* Ignore rest of this alternative as far as | |
3114 | reloading is concerned. */ | |
97488870 | 3115 | do |
4381f7c2 | 3116 | p++; |
97488870 R |
3117 | while (*p && *p != ','); |
3118 | len = 0; | |
eab89b90 RK |
3119 | break; |
3120 | ||
c5c76735 JL |
3121 | case '0': case '1': case '2': case '3': case '4': |
3122 | case '5': case '6': case '7': case '8': case '9': | |
97488870 R |
3123 | m = strtoul (p, &end, 10); |
3124 | p = end; | |
3125 | len = 0; | |
c5c76735 | 3126 | |
97488870 | 3127 | this_alternative_matches[i] = m; |
eab89b90 RK |
3128 | /* We are supposed to match a previous operand. |
3129 | If we do, we win if that one did. | |
3130 | If we do not, count both of the operands as losers. | |
3131 | (This is too conservative, since most of the time | |
3132 | only a single reload insn will be needed to make | |
3133 | the two operands win. As a result, this alternative | |
3134 | may be rejected when it is actually desirable.) */ | |
97488870 | 3135 | if ((swapped && (m != commutative || i != commutative + 1)) |
eab89b90 RK |
3136 | /* If we are matching as if two operands were swapped, |
3137 | also pretend that operands_match had been computed | |
3138 | with swapped. | |
3139 | But if I is the second of those and C is the first, | |
3140 | don't exchange them, because operands_match is valid | |
3141 | only on one side of its diagonal. */ | |
3142 | ? (operands_match | |
97488870 R |
3143 | [(m == commutative || m == commutative + 1) |
3144 | ? 2 * commutative + 1 - m : m] | |
05d10675 | 3145 | [(i == commutative || i == commutative + 1) |
4381f7c2 | 3146 | ? 2 * commutative + 1 - i : i]) |
97488870 | 3147 | : operands_match[m][i]) |
fc79eafe JW |
3148 | { |
3149 | /* If we are matching a non-offsettable address where an | |
3150 | offsettable address was expected, then we must reject | |
3151 | this combination, because we can't reload it. */ | |
97488870 | 3152 | if (this_alternative_offmemok[m] |
3c0cb5de | 3153 | && MEM_P (recog_data.operand[m]) |
bbbbb16a | 3154 | && this_alternative[m] == NO_REGS |
97488870 | 3155 | && ! this_alternative_win[m]) |
fc79eafe JW |
3156 | bad = 1; |
3157 | ||
97488870 | 3158 | did_match = this_alternative_win[m]; |
fc79eafe | 3159 | } |
eab89b90 RK |
3160 | else |
3161 | { | |
3162 | /* Operands don't match. */ | |
3163 | rtx value; | |
87cda9d6 | 3164 | int loc1, loc2; |
eab89b90 RK |
3165 | /* Retroactively mark the operand we had to match |
3166 | as a loser, if it wasn't already. */ | |
97488870 | 3167 | if (this_alternative_win[m]) |
eab89b90 | 3168 | losers++; |
97488870 | 3169 | this_alternative_win[m] = 0; |
bbbbb16a | 3170 | if (this_alternative[m] == NO_REGS) |
eab89b90 RK |
3171 | bad = 1; |
3172 | /* But count the pair only once in the total badness of | |
87cda9d6 DJ |
3173 | this alternative, if the pair can be a dummy reload. |
3174 | The pointers in operand_loc are not swapped; swap | |
3175 | them by hand if necessary. */ | |
3176 | if (swapped && i == commutative) | |
3177 | loc1 = commutative + 1; | |
3178 | else if (swapped && i == commutative + 1) | |
3179 | loc1 = commutative; | |
3180 | else | |
3181 | loc1 = i; | |
3182 | if (swapped && m == commutative) | |
3183 | loc2 = commutative + 1; | |
3184 | else if (swapped && m == commutative + 1) | |
3185 | loc2 = commutative; | |
3186 | else | |
3187 | loc2 = m; | |
eab89b90 | 3188 | value |
1ccbefce | 3189 | = find_dummy_reload (recog_data.operand[i], |
97488870 | 3190 | recog_data.operand[m], |
87cda9d6 DJ |
3191 | recog_data.operand_loc[loc1], |
3192 | recog_data.operand_loc[loc2], | |
97488870 R |
3193 | operand_mode[i], operand_mode[m], |
3194 | this_alternative[m], -1, | |
3195 | this_alternative_earlyclobber[m]); | |
eab89b90 RK |
3196 | |
3197 | if (value != 0) | |
3198 | losers--; | |
3199 | } | |
3200 | /* This can be fixed with reloads if the operand | |
3201 | we are supposed to match can be fixed with reloads. */ | |
3202 | badop = 0; | |
97488870 | 3203 | this_alternative[i] = this_alternative[m]; |
e64c4f9e RK |
3204 | |
3205 | /* If we have to reload this operand and some previous | |
3206 | operand also had to match the same thing as this | |
3207 | operand, we don't know how to do that. So reject this | |
3208 | alternative. */ | |
69add2a8 | 3209 | if (! did_match || force_reload) |
e64c4f9e RK |
3210 | for (j = 0; j < i; j++) |
3211 | if (this_alternative_matches[j] | |
3212 | == this_alternative_matches[i]) | |
3213 | badop = 1; | |
eab89b90 RK |
3214 | break; |
3215 | ||
3216 | case 'p': | |
3217 | /* All necessary reloads for an address_operand | |
3218 | were handled in find_reloads_address. */ | |
bbbbb16a ILT |
3219 | this_alternative[i] = base_reg_class (VOIDmode, ADDRESS, |
3220 | SCRATCH); | |
eab89b90 | 3221 | win = 1; |
8d53318f | 3222 | badop = 0; |
eab89b90 RK |
3223 | break; |
3224 | ||
a4edaf83 | 3225 | case TARGET_MEM_CONSTRAINT: |
eab89b90 RK |
3226 | if (force_reload) |
3227 | break; | |
3c0cb5de | 3228 | if (MEM_P (operand) |
f8cfc6aa | 3229 | || (REG_P (operand) |
eab89b90 RK |
3230 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER |
3231 | && reg_renumber[REGNO (operand)] < 0)) | |
3232 | win = 1; | |
34208acf | 3233 | if (CONST_POOL_OK_P (operand)) |
eab89b90 | 3234 | badop = 0; |
9d926da5 | 3235 | constmemok = 1; |
eab89b90 RK |
3236 | break; |
3237 | ||
3238 | case '<': | |
3c0cb5de | 3239 | if (MEM_P (operand) |
eab89b90 RK |
3240 | && ! address_reloaded[i] |
3241 | && (GET_CODE (XEXP (operand, 0)) == PRE_DEC | |
3242 | || GET_CODE (XEXP (operand, 0)) == POST_DEC)) | |
3243 | win = 1; | |
3244 | break; | |
3245 | ||
3246 | case '>': | |
3c0cb5de | 3247 | if (MEM_P (operand) |
eab89b90 RK |
3248 | && ! address_reloaded[i] |
3249 | && (GET_CODE (XEXP (operand, 0)) == PRE_INC | |
3250 | || GET_CODE (XEXP (operand, 0)) == POST_INC)) | |
3251 | win = 1; | |
3252 | break; | |
3253 | ||
3254 | /* Memory operand whose address is not offsettable. */ | |
3255 | case 'V': | |
3256 | if (force_reload) | |
3257 | break; | |
3c0cb5de | 3258 | if (MEM_P (operand) |
eab89b90 RK |
3259 | && ! (ind_levels ? offsettable_memref_p (operand) |
3260 | : offsettable_nonstrict_memref_p (operand)) | |
3261 | /* Certain mem addresses will become offsettable | |
3262 | after they themselves are reloaded. This is important; | |
3263 | we don't want our own handling of unoffsettables | |
3264 | to override the handling of reg_equiv_address. */ | |
f8cfc6aa | 3265 | && !(REG_P (XEXP (operand, 0)) |
eab89b90 RK |
3266 | && (ind_levels == 0 |
3267 | || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0))) | |
3268 | win = 1; | |
3269 | break; | |
3270 | ||
3271 | /* Memory operand whose address is offsettable. */ | |
3272 | case 'o': | |
3273 | if (force_reload) | |
3274 | break; | |
3c0cb5de | 3275 | if ((MEM_P (operand) |
eab89b90 RK |
3276 | /* If IND_LEVELS, find_reloads_address won't reload a |
3277 | pseudo that didn't get a hard reg, so we have to | |
3278 | reject that case. */ | |
ab87f8c8 JL |
3279 | && ((ind_levels ? offsettable_memref_p (operand) |
3280 | : offsettable_nonstrict_memref_p (operand)) | |
3281 | /* A reloaded address is offsettable because it is now | |
3282 | just a simple register indirect. */ | |
0b540f12 | 3283 | || address_reloaded[i] == 1)) |
f8cfc6aa | 3284 | || (REG_P (operand) |
eab89b90 | 3285 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER |
3a322c50 RK |
3286 | && reg_renumber[REGNO (operand)] < 0 |
3287 | /* If reg_equiv_address is nonzero, we will be | |
3288 | loading it into a register; hence it will be | |
3289 | offsettable, but we cannot say that reg_equiv_mem | |
3290 | is offsettable without checking. */ | |
3291 | && ((reg_equiv_mem[REGNO (operand)] != 0 | |
3292 | && offsettable_memref_p (reg_equiv_mem[REGNO (operand)])) | |
3293 | || (reg_equiv_address[REGNO (operand)] != 0)))) | |
eab89b90 | 3294 | win = 1; |
34208acf | 3295 | if (CONST_POOL_OK_P (operand) |
3c0cb5de | 3296 | || MEM_P (operand)) |
eab89b90 | 3297 | badop = 0; |
9d926da5 | 3298 | constmemok = 1; |
eab89b90 RK |
3299 | offmemok = 1; |
3300 | break; | |
3301 | ||
3302 | case '&': | |
3303 | /* Output operand that is stored before the need for the | |
3304 | input operands (and their index registers) is over. */ | |
3305 | earlyclobber = 1, this_earlyclobber = 1; | |
3306 | break; | |
3307 | ||
3308 | case 'E': | |
eab89b90 | 3309 | case 'F': |
bf7cd754 R |
3310 | if (GET_CODE (operand) == CONST_DOUBLE |
3311 | || (GET_CODE (operand) == CONST_VECTOR | |
3312 | && (GET_MODE_CLASS (GET_MODE (operand)) | |
3313 | == MODE_VECTOR_FLOAT))) | |
eab89b90 RK |
3314 | win = 1; |
3315 | break; | |
3316 | ||
3317 | case 'G': | |
3318 | case 'H': | |
3319 | if (GET_CODE (operand) == CONST_DOUBLE | |
97488870 | 3320 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (operand, c, p)) |
eab89b90 RK |
3321 | win = 1; |
3322 | break; | |
3323 | ||
3324 | case 's': | |
481683e1 | 3325 | if (CONST_INT_P (operand) |
eab89b90 RK |
3326 | || (GET_CODE (operand) == CONST_DOUBLE |
3327 | && GET_MODE (operand) == VOIDmode)) | |
3328 | break; | |
3329 | case 'i': | |
3330 | if (CONSTANT_P (operand) | |
2e4e72b1 | 3331 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand))) |
eab89b90 RK |
3332 | win = 1; |
3333 | break; | |
3334 | ||
3335 | case 'n': | |
481683e1 | 3336 | if (CONST_INT_P (operand) |
eab89b90 RK |
3337 | || (GET_CODE (operand) == CONST_DOUBLE |
3338 | && GET_MODE (operand) == VOIDmode)) | |
3339 | win = 1; | |
3340 | break; | |
3341 | ||
3342 | case 'I': | |
3343 | case 'J': | |
3344 | case 'K': | |
3345 | case 'L': | |
3346 | case 'M': | |
3347 | case 'N': | |
3348 | case 'O': | |
3349 | case 'P': | |
481683e1 | 3350 | if (CONST_INT_P (operand) |
97488870 | 3351 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operand), c, p)) |
eab89b90 RK |
3352 | win = 1; |
3353 | break; | |
3354 | ||
3355 | case 'X': | |
6c65d757 | 3356 | force_reload = 0; |
eab89b90 RK |
3357 | win = 1; |
3358 | break; | |
3359 | ||
3360 | case 'g': | |
3361 | if (! force_reload | |
3362 | /* A PLUS is never a valid operand, but reload can make | |
3363 | it from a register when eliminating registers. */ | |
3364 | && GET_CODE (operand) != PLUS | |
3365 | /* A SCRATCH is not a valid operand. */ | |
3366 | && GET_CODE (operand) != SCRATCH | |
05d10675 BS |
3367 | && (! CONSTANT_P (operand) |
3368 | || ! flag_pic | |
eab89b90 | 3369 | || LEGITIMATE_PIC_OPERAND_P (operand)) |
eab89b90 | 3370 | && (GENERAL_REGS == ALL_REGS |
f8cfc6aa | 3371 | || !REG_P (operand) |
eab89b90 RK |
3372 | || (REGNO (operand) >= FIRST_PSEUDO_REGISTER |
3373 | && reg_renumber[REGNO (operand)] < 0))) | |
3374 | win = 1; | |
82efa2e5 | 3375 | /* Drop through into 'r' case. */ |
eab89b90 RK |
3376 | |
3377 | case 'r': | |
3378 | this_alternative[i] | |
bbbbb16a | 3379 | = reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS]; |
eab89b90 RK |
3380 | goto reg; |
3381 | ||
c2cba7a9 | 3382 | default: |
97488870 | 3383 | if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS) |
c2cba7a9 | 3384 | { |
97488870 R |
3385 | #ifdef EXTRA_CONSTRAINT_STR |
3386 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
ccfc6cc8 UW |
3387 | { |
3388 | if (force_reload) | |
3389 | break; | |
97488870 | 3390 | if (EXTRA_CONSTRAINT_STR (operand, c, p)) |
ccfc6cc8 UW |
3391 | win = 1; |
3392 | /* If the address was already reloaded, | |
3393 | we win as well. */ | |
3c0cb5de | 3394 | else if (MEM_P (operand) |
0b540f12 | 3395 | && address_reloaded[i] == 1) |
ccfc6cc8 UW |
3396 | win = 1; |
3397 | /* Likewise if the address will be reloaded because | |
3398 | reg_equiv_address is nonzero. For reg_equiv_mem | |
3399 | we have to check. */ | |
f8cfc6aa | 3400 | else if (REG_P (operand) |
3b6c3bb0 JW |
3401 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER |
3402 | && reg_renumber[REGNO (operand)] < 0 | |
3403 | && ((reg_equiv_mem[REGNO (operand)] != 0 | |
3404 | && EXTRA_CONSTRAINT_STR (reg_equiv_mem[REGNO (operand)], c, p)) | |
3405 | || (reg_equiv_address[REGNO (operand)] != 0))) | |
ccfc6cc8 UW |
3406 | win = 1; |
3407 | ||
3408 | /* If we didn't already win, we can reload | |
3409 | constants via force_const_mem, and other | |
3410 | MEMs by reloading the address like for 'o'. */ | |
34208acf | 3411 | if (CONST_POOL_OK_P (operand) |
3c0cb5de | 3412 | || MEM_P (operand)) |
ccfc6cc8 UW |
3413 | badop = 0; |
3414 | constmemok = 1; | |
3415 | offmemok = 1; | |
3416 | break; | |
3417 | } | |
97488870 | 3418 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) |
ccfc6cc8 | 3419 | { |
97488870 | 3420 | if (EXTRA_CONSTRAINT_STR (operand, c, p)) |
ccfc6cc8 UW |
3421 | win = 1; |
3422 | ||
3423 | /* If we didn't already win, we can reload | |
3424 | the address into a base register. */ | |
bbbbb16a ILT |
3425 | this_alternative[i] = base_reg_class (VOIDmode, |
3426 | ADDRESS, | |
3427 | SCRATCH); | |
ccfc6cc8 UW |
3428 | badop = 0; |
3429 | break; | |
3430 | } | |
3431 | ||
97488870 | 3432 | if (EXTRA_CONSTRAINT_STR (operand, c, p)) |
c2cba7a9 | 3433 | win = 1; |
eab89b90 | 3434 | #endif |
c2cba7a9 RH |
3435 | break; |
3436 | } | |
05d10675 | 3437 | |
eab89b90 | 3438 | this_alternative[i] |
bbbbb16a ILT |
3439 | = (reg_class_subunion |
3440 | [this_alternative[i]] | |
3441 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]); | |
eab89b90 RK |
3442 | reg: |
3443 | if (GET_MODE (operand) == BLKmode) | |
3444 | break; | |
3445 | winreg = 1; | |
f8cfc6aa | 3446 | if (REG_P (operand) |
eab89b90 | 3447 | && reg_fits_class_p (operand, this_alternative[i], |
1ccbefce | 3448 | offset, GET_MODE (recog_data.operand[i]))) |
eab89b90 RK |
3449 | win = 1; |
3450 | break; | |
3451 | } | |
97488870 | 3452 | while ((p += len), c); |
eab89b90 RK |
3453 | |
3454 | constraints[i] = p; | |
3455 | ||
3456 | /* If this operand could be handled with a reg, | |
3457 | and some reg is allowed, then this operand can be handled. */ | |
bbbbb16a | 3458 | if (winreg && this_alternative[i] != NO_REGS) |
eab89b90 RK |
3459 | badop = 0; |
3460 | ||
3461 | /* Record which operands fit this alternative. */ | |
3462 | this_alternative_earlyclobber[i] = earlyclobber; | |
3463 | if (win && ! force_reload) | |
3464 | this_alternative_win[i] = 1; | |
69add2a8 BS |
3465 | else if (did_match && ! force_reload) |
3466 | this_alternative_match_win[i] = 1; | |
eab89b90 RK |
3467 | else |
3468 | { | |
9d926da5 RK |
3469 | int const_to_mem = 0; |
3470 | ||
eab89b90 RK |
3471 | this_alternative_offmemok[i] = offmemok; |
3472 | losers++; | |
3473 | if (badop) | |
3474 | bad = 1; | |
3475 | /* Alternative loses if it has no regs for a reg operand. */ | |
f8cfc6aa | 3476 | if (REG_P (operand) |
bbbbb16a | 3477 | && this_alternative[i] == NO_REGS |
eab89b90 RK |
3478 | && this_alternative_matches[i] < 0) |
3479 | bad = 1; | |
3480 | ||
3a322c50 RK |
3481 | /* If this is a constant that is reloaded into the desired |
3482 | class by copying it to memory first, count that as another | |
3483 | reload. This is consistent with other code and is | |
293166be | 3484 | required to avoid choosing another alternative when |
3a322c50 | 3485 | the constant is moved into memory by this function on |
05d10675 | 3486 | an early reload pass. Note that the test here is |
3a322c50 RK |
3487 | precisely the same as in the code below that calls |
3488 | force_const_mem. */ | |
34208acf | 3489 | if (CONST_POOL_OK_P (operand) |
bbbbb16a | 3490 | && ((PREFERRED_RELOAD_CLASS (operand, this_alternative[i]) |
e5e809f4 JL |
3491 | == NO_REGS) |
3492 | || no_input_reloads) | |
3a322c50 | 3493 | && operand_mode[i] != VOIDmode) |
9d926da5 RK |
3494 | { |
3495 | const_to_mem = 1; | |
bbbbb16a | 3496 | if (this_alternative[i] != NO_REGS) |
9d926da5 RK |
3497 | losers++; |
3498 | } | |
3a322c50 | 3499 | |
e5e809f4 JL |
3500 | /* Alternative loses if it requires a type of reload not |
3501 | permitted for this insn. We can always reload SCRATCH | |
3502 | and objects with a REG_UNUSED note. */ | |
b5c82fa1 | 3503 | if (GET_CODE (operand) != SCRATCH |
05d10675 BS |
3504 | && modified[i] != RELOAD_READ && no_output_reloads |
3505 | && ! find_reg_note (insn, REG_UNUSED, operand)) | |
e5e809f4 JL |
3506 | bad = 1; |
3507 | else if (modified[i] != RELOAD_WRITE && no_input_reloads | |
3508 | && ! const_to_mem) | |
3509 | bad = 1; | |
3510 | ||
b5c82fa1 PB |
3511 | /* If we can't reload this value at all, reject this |
3512 | alternative. Note that we could also lose due to | |
3513 | LIMIT_RELOAD_CLASS, but we don't check that | |
3514 | here. */ | |
3515 | ||
bbbbb16a | 3516 | if (! CONSTANT_P (operand) && this_alternative[i] != NO_REGS) |
b5c82fa1 | 3517 | { |
bbbbb16a | 3518 | if (PREFERRED_RELOAD_CLASS (operand, this_alternative[i]) |
b5c82fa1 PB |
3519 | == NO_REGS) |
3520 | reject = 600; | |
3521 | ||
3522 | #ifdef PREFERRED_OUTPUT_RELOAD_CLASS | |
3523 | if (operand_type[i] == RELOAD_FOR_OUTPUT | |
bbbbb16a ILT |
3524 | && (PREFERRED_OUTPUT_RELOAD_CLASS (operand, |
3525 | this_alternative[i]) | |
3526 | == NO_REGS)) | |
b5c82fa1 PB |
3527 | reject = 600; |
3528 | #endif | |
3529 | } | |
3530 | ||
eab89b90 RK |
3531 | /* We prefer to reload pseudos over reloading other things, |
3532 | since such reloads may be able to be eliminated later. | |
3533 | If we are reloading a SCRATCH, we won't be generating any | |
05d10675 | 3534 | insns, just using a register, so it is also preferred. |
9d926da5 RK |
3535 | So bump REJECT in other cases. Don't do this in the |
3536 | case where we are forcing a constant into memory and | |
3537 | it will then win since we don't want to have a different | |
3538 | alternative match then. */ | |
f8cfc6aa | 3539 | if (! (REG_P (operand) |
915bb763 | 3540 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER) |
9d926da5 RK |
3541 | && GET_CODE (operand) != SCRATCH |
3542 | && ! (const_to_mem && constmemok)) | |
812f2051 R |
3543 | reject += 2; |
3544 | ||
3545 | /* Input reloads can be inherited more often than output | |
3546 | reloads can be removed, so penalize output reloads. */ | |
7924156a JW |
3547 | if (operand_type[i] != RELOAD_FOR_INPUT |
3548 | && GET_CODE (operand) != SCRATCH) | |
eab89b90 RK |
3549 | reject++; |
3550 | } | |
3551 | ||
05d10675 | 3552 | /* If this operand is a pseudo register that didn't get a hard |
eab89b90 RK |
3553 | reg and this alternative accepts some register, see if the |
3554 | class that we want is a subset of the preferred class for this | |
3555 | register. If not, but it intersects that class, use the | |
3556 | preferred class instead. If it does not intersect the preferred | |
3557 | class, show that usage of this alternative should be discouraged; | |
3558 | it will be discouraged more still if the register is `preferred | |
3559 | or nothing'. We do this because it increases the chance of | |
3560 | reusing our spill register in a later insn and avoiding a pair | |
3561 | of memory stores and loads. | |
3562 | ||
3563 | Don't bother with this if this alternative will accept this | |
3564 | operand. | |
3565 | ||
a2d353e5 RK |
3566 | Don't do this for a multiword operand, since it is only a |
3567 | small win and has the risk of requiring more spill registers, | |
3568 | which could cause a large loss. | |
5aa14fee | 3569 | |
eab89b90 RK |
3570 | Don't do this if the preferred class has only one register |
3571 | because we might otherwise exhaust the class. */ | |
3572 | ||
69add2a8 | 3573 | if (! win && ! did_match |
bbbbb16a | 3574 | && this_alternative[i] != NO_REGS |
5aa14fee | 3575 | && GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD |
e9840398 AO |
3576 | && reg_class_size [(int) preferred_class[i]] > 0 |
3577 | && ! SMALL_REGISTER_CLASS_P (preferred_class[i])) | |
eab89b90 RK |
3578 | { |
3579 | if (! reg_class_subset_p (this_alternative[i], | |
3580 | preferred_class[i])) | |
3581 | { | |
3582 | /* Since we don't have a way of forming the intersection, | |
3583 | we just do something special if the preferred class | |
05d10675 | 3584 | is a subset of the class we have; that's the most |
eab89b90 RK |
3585 | common case anyway. */ |
3586 | if (reg_class_subset_p (preferred_class[i], | |
3587 | this_alternative[i])) | |
bbbbb16a | 3588 | this_alternative[i] = preferred_class[i]; |
eab89b90 | 3589 | else |
812f2051 | 3590 | reject += (2 + 2 * pref_or_nothing[i]); |
eab89b90 RK |
3591 | } |
3592 | } | |
3593 | } | |
3594 | ||
3595 | /* Now see if any output operands that are marked "earlyclobber" | |
3596 | in this alternative conflict with any input operands | |
3597 | or any memory addresses. */ | |
3598 | ||
3599 | for (i = 0; i < noperands; i++) | |
3600 | if (this_alternative_earlyclobber[i] | |
69add2a8 | 3601 | && (this_alternative_win[i] || this_alternative_match_win[i])) |
eab89b90 | 3602 | { |
05d10675 | 3603 | struct decomposition early_data; |
eab89b90 | 3604 | |
1ccbefce | 3605 | early_data = decompose (recog_data.operand[i]); |
eab89b90 | 3606 | |
41374e13 | 3607 | gcc_assert (modified[i] != RELOAD_READ); |
05d10675 | 3608 | |
eab89b90 RK |
3609 | if (this_alternative[i] == NO_REGS) |
3610 | { | |
3611 | this_alternative_earlyclobber[i] = 0; | |
41374e13 NS |
3612 | gcc_assert (this_insn_is_asm); |
3613 | error_for_asm (this_insn, | |
971801ff | 3614 | "%<&%> constraint used with no register class"); |
eab89b90 RK |
3615 | } |
3616 | ||
3617 | for (j = 0; j < noperands; j++) | |
3618 | /* Is this an input operand or a memory ref? */ | |
3c0cb5de | 3619 | if ((MEM_P (recog_data.operand[j]) |
eab89b90 RK |
3620 | || modified[j] != RELOAD_WRITE) |
3621 | && j != i | |
3622 | /* Ignore things like match_operator operands. */ | |
1ccbefce | 3623 | && *recog_data.constraints[j] != 0 |
eab89b90 RK |
3624 | /* Don't count an input operand that is constrained to match |
3625 | the early clobber operand. */ | |
3626 | && ! (this_alternative_matches[j] == i | |
1ccbefce RH |
3627 | && rtx_equal_p (recog_data.operand[i], |
3628 | recog_data.operand[j])) | |
eab89b90 | 3629 | /* Is it altered by storing the earlyclobber operand? */ |
1ccbefce RH |
3630 | && !immune_p (recog_data.operand[j], recog_data.operand[i], |
3631 | early_data)) | |
eab89b90 | 3632 | { |
e9840398 | 3633 | /* If the output is in a non-empty few-regs class, |
eab89b90 | 3634 | it's costly to reload it, so reload the input instead. */ |
e9840398 | 3635 | if (SMALL_REGISTER_CLASS_P (this_alternative[i]) |
f8cfc6aa | 3636 | && (REG_P (recog_data.operand[j]) |
1ccbefce | 3637 | || GET_CODE (recog_data.operand[j]) == SUBREG)) |
eab89b90 RK |
3638 | { |
3639 | losers++; | |
3640 | this_alternative_win[j] = 0; | |
69add2a8 | 3641 | this_alternative_match_win[j] = 0; |
eab89b90 RK |
3642 | } |
3643 | else | |
3644 | break; | |
3645 | } | |
3646 | /* If an earlyclobber operand conflicts with something, | |
3647 | it must be reloaded, so request this and count the cost. */ | |
3648 | if (j != noperands) | |
3649 | { | |
3650 | losers++; | |
3651 | this_alternative_win[i] = 0; | |
69add2a8 | 3652 | this_alternative_match_win[j] = 0; |
eab89b90 RK |
3653 | for (j = 0; j < noperands; j++) |
3654 | if (this_alternative_matches[j] == i | |
69add2a8 | 3655 | && this_alternative_match_win[j]) |
eab89b90 RK |
3656 | { |
3657 | this_alternative_win[j] = 0; | |
69add2a8 | 3658 | this_alternative_match_win[j] = 0; |
eab89b90 RK |
3659 | losers++; |
3660 | } | |
3661 | } | |
3662 | } | |
3663 | ||
3664 | /* If one alternative accepts all the operands, no reload required, | |
3665 | choose that alternative; don't consider the remaining ones. */ | |
3666 | if (losers == 0) | |
3667 | { | |
3668 | /* Unswap these so that they are never swapped at `finish'. */ | |
3669 | if (commutative >= 0) | |
3670 | { | |
1ccbefce RH |
3671 | recog_data.operand[commutative] = substed_operand[commutative]; |
3672 | recog_data.operand[commutative + 1] | |
eab89b90 RK |
3673 | = substed_operand[commutative + 1]; |
3674 | } | |
3675 | for (i = 0; i < noperands; i++) | |
3676 | { | |
69add2a8 BS |
3677 | goal_alternative_win[i] = this_alternative_win[i]; |
3678 | goal_alternative_match_win[i] = this_alternative_match_win[i]; | |
eab89b90 RK |
3679 | goal_alternative[i] = this_alternative[i]; |
3680 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; | |
3681 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3682 | goal_alternative_earlyclobber[i] | |
3683 | = this_alternative_earlyclobber[i]; | |
3684 | } | |
3685 | goal_alternative_number = this_alternative_number; | |
3686 | goal_alternative_swapped = swapped; | |
3687 | goal_earlyclobber = this_earlyclobber; | |
3688 | goto finish; | |
3689 | } | |
3690 | ||
3691 | /* REJECT, set by the ! and ? constraint characters and when a register | |
3692 | would be reloaded into a non-preferred class, discourages the use of | |
812f2051 R |
3693 | this alternative for a reload goal. REJECT is incremented by six |
3694 | for each ? and two for each non-preferred class. */ | |
3695 | losers = losers * 6 + reject; | |
eab89b90 RK |
3696 | |
3697 | /* If this alternative can be made to work by reloading, | |
3698 | and it needs less reloading than the others checked so far, | |
3699 | record it as the chosen goal for reloading. */ | |
3700 | if (! bad && best > losers) | |
3701 | { | |
3702 | for (i = 0; i < noperands; i++) | |
3703 | { | |
3704 | goal_alternative[i] = this_alternative[i]; | |
3705 | goal_alternative_win[i] = this_alternative_win[i]; | |
69add2a8 | 3706 | goal_alternative_match_win[i] = this_alternative_match_win[i]; |
eab89b90 RK |
3707 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; |
3708 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3709 | goal_alternative_earlyclobber[i] | |
3710 | = this_alternative_earlyclobber[i]; | |
3711 | } | |
3712 | goal_alternative_swapped = swapped; | |
3713 | best = losers; | |
3714 | goal_alternative_number = this_alternative_number; | |
3715 | goal_earlyclobber = this_earlyclobber; | |
3716 | } | |
3717 | } | |
3718 | ||
3719 | /* If insn is commutative (it's safe to exchange a certain pair of operands) | |
3720 | then we need to try each alternative twice, | |
3721 | the second time matching those two operands | |
3722 | as if we had exchanged them. | |
3723 | To do this, really exchange them in operands. | |
3724 | ||
3725 | If we have just tried the alternatives the second time, | |
3726 | return operands to normal and drop through. */ | |
3727 | ||
3728 | if (commutative >= 0) | |
3729 | { | |
3730 | swapped = !swapped; | |
3731 | if (swapped) | |
3732 | { | |
b3694847 SS |
3733 | enum reg_class tclass; |
3734 | int t; | |
eab89b90 | 3735 | |
1ccbefce RH |
3736 | recog_data.operand[commutative] = substed_operand[commutative + 1]; |
3737 | recog_data.operand[commutative + 1] = substed_operand[commutative]; | |
9cd56be1 JH |
3738 | /* Swap the duplicates too. */ |
3739 | for (i = 0; i < recog_data.n_dups; i++) | |
3740 | if (recog_data.dup_num[i] == commutative | |
3741 | || recog_data.dup_num[i] == commutative + 1) | |
3742 | *recog_data.dup_loc[i] | |
3743 | = recog_data.operand[(int) recog_data.dup_num[i]]; | |
eab89b90 RK |
3744 | |
3745 | tclass = preferred_class[commutative]; | |
3746 | preferred_class[commutative] = preferred_class[commutative + 1]; | |
3747 | preferred_class[commutative + 1] = tclass; | |
3748 | ||
3749 | t = pref_or_nothing[commutative]; | |
3750 | pref_or_nothing[commutative] = pref_or_nothing[commutative + 1]; | |
3751 | pref_or_nothing[commutative + 1] = t; | |
3752 | ||
e88d55cd UW |
3753 | t = address_reloaded[commutative]; |
3754 | address_reloaded[commutative] = address_reloaded[commutative + 1]; | |
3755 | address_reloaded[commutative + 1] = t; | |
3756 | ||
f428f252 | 3757 | memcpy (constraints, recog_data.constraints, |
7ac28727 | 3758 | noperands * sizeof (const char *)); |
eab89b90 RK |
3759 | goto try_swapped; |
3760 | } | |
3761 | else | |
3762 | { | |
1ccbefce RH |
3763 | recog_data.operand[commutative] = substed_operand[commutative]; |
3764 | recog_data.operand[commutative + 1] | |
3765 | = substed_operand[commutative + 1]; | |
9cd56be1 JH |
3766 | /* Unswap the duplicates too. */ |
3767 | for (i = 0; i < recog_data.n_dups; i++) | |
3768 | if (recog_data.dup_num[i] == commutative | |
3769 | || recog_data.dup_num[i] == commutative + 1) | |
3770 | *recog_data.dup_loc[i] | |
3771 | = recog_data.operand[(int) recog_data.dup_num[i]]; | |
eab89b90 RK |
3772 | } |
3773 | } | |
3774 | ||
3775 | /* The operands don't meet the constraints. | |
3776 | goal_alternative describes the alternative | |
3777 | that we could reach by reloading the fewest operands. | |
3778 | Reload so as to fit it. */ | |
3779 | ||
c22eaf8a | 3780 | if (best == MAX_RECOG_OPERANDS * 2 + 600) |
eab89b90 RK |
3781 | { |
3782 | /* No alternative works with reloads?? */ | |
3783 | if (insn_code_number >= 0) | |
1f978f5f | 3784 | fatal_insn ("unable to generate reloads for:", insn); |
971801ff | 3785 | error_for_asm (insn, "inconsistent operand constraints in an %<asm%>"); |
eab89b90 | 3786 | /* Avoid further trouble with this insn. */ |
38a448ca | 3787 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
eab89b90 | 3788 | n_reloads = 0; |
cb2afeb3 | 3789 | return 0; |
eab89b90 RK |
3790 | } |
3791 | ||
3792 | /* Jump to `finish' from above if all operands are valid already. | |
3793 | In that case, goal_alternative_win is all 1. */ | |
3794 | finish: | |
3795 | ||
3796 | /* Right now, for any pair of operands I and J that are required to match, | |
3797 | with I < J, | |
3798 | goal_alternative_matches[J] is I. | |
3799 | Set up goal_alternative_matched as the inverse function: | |
3800 | goal_alternative_matched[I] = J. */ | |
3801 | ||
3802 | for (i = 0; i < noperands; i++) | |
3803 | goal_alternative_matched[i] = -1; | |
a6a2274a | 3804 | |
eab89b90 RK |
3805 | for (i = 0; i < noperands; i++) |
3806 | if (! goal_alternative_win[i] | |
3807 | && goal_alternative_matches[i] >= 0) | |
3808 | goal_alternative_matched[goal_alternative_matches[i]] = i; | |
3809 | ||
69add2a8 BS |
3810 | for (i = 0; i < noperands; i++) |
3811 | goal_alternative_win[i] |= goal_alternative_match_win[i]; | |
3812 | ||
eab89b90 | 3813 | /* If the best alternative is with operands 1 and 2 swapped, |
a8c9daeb RK |
3814 | consider them swapped before reporting the reloads. Update the |
3815 | operand numbers of any reloads already pushed. */ | |
eab89b90 RK |
3816 | |
3817 | if (goal_alternative_swapped) | |
3818 | { | |
b3694847 | 3819 | rtx tem; |
eab89b90 RK |
3820 | |
3821 | tem = substed_operand[commutative]; | |
3822 | substed_operand[commutative] = substed_operand[commutative + 1]; | |
3823 | substed_operand[commutative + 1] = tem; | |
1ccbefce RH |
3824 | tem = recog_data.operand[commutative]; |
3825 | recog_data.operand[commutative] = recog_data.operand[commutative + 1]; | |
3826 | recog_data.operand[commutative + 1] = tem; | |
3827 | tem = *recog_data.operand_loc[commutative]; | |
3828 | *recog_data.operand_loc[commutative] | |
3829 | = *recog_data.operand_loc[commutative + 1]; | |
4381f7c2 | 3830 | *recog_data.operand_loc[commutative + 1] = tem; |
a8c9daeb RK |
3831 | |
3832 | for (i = 0; i < n_reloads; i++) | |
3833 | { | |
eceef4c9 BS |
3834 | if (rld[i].opnum == commutative) |
3835 | rld[i].opnum = commutative + 1; | |
3836 | else if (rld[i].opnum == commutative + 1) | |
3837 | rld[i].opnum = commutative; | |
a8c9daeb | 3838 | } |
eab89b90 RK |
3839 | } |
3840 | ||
eab89b90 RK |
3841 | for (i = 0; i < noperands; i++) |
3842 | { | |
eab89b90 | 3843 | operand_reloadnum[i] = -1; |
a8c9daeb RK |
3844 | |
3845 | /* If this is an earlyclobber operand, we need to widen the scope. | |
3846 | The reload must remain valid from the start of the insn being | |
3847 | reloaded until after the operand is stored into its destination. | |
3848 | We approximate this with RELOAD_OTHER even though we know that we | |
3849 | do not conflict with RELOAD_FOR_INPUT_ADDRESS reloads. | |
3850 | ||
3851 | One special case that is worth checking is when we have an | |
3852 | output that is earlyclobber but isn't used past the insn (typically | |
05d10675 | 3853 | a SCRATCH). In this case, we only need have the reload live |
a8c9daeb | 3854 | through the insn itself, but not for any of our input or output |
05d10675 | 3855 | reloads. |
f9df0a1d R |
3856 | But we must not accidentally narrow the scope of an existing |
3857 | RELOAD_OTHER reload - leave these alone. | |
a8c9daeb RK |
3858 | |
3859 | In any case, anything needed to address this operand can remain | |
3860 | however they were previously categorized. */ | |
3861 | ||
f9df0a1d | 3862 | if (goal_alternative_earlyclobber[i] && operand_type[i] != RELOAD_OTHER) |
a8c9daeb | 3863 | operand_type[i] |
1ccbefce | 3864 | = (find_reg_note (insn, REG_UNUSED, recog_data.operand[i]) |
a8c9daeb | 3865 | ? RELOAD_FOR_INSN : RELOAD_OTHER); |
eab89b90 RK |
3866 | } |
3867 | ||
3868 | /* Any constants that aren't allowed and can't be reloaded | |
3869 | into registers are here changed into memory references. */ | |
3870 | for (i = 0; i < noperands; i++) | |
e0a17959 | 3871 | if (! goal_alternative_win[i]) |
eab89b90 | 3872 | { |
e0a17959 AK |
3873 | rtx op = recog_data.operand[i]; |
3874 | rtx subreg = NULL_RTX; | |
3875 | rtx plus = NULL_RTX; | |
3876 | enum machine_mode mode = operand_mode[i]; | |
3877 | ||
3878 | /* Reloads of SUBREGs of CONSTANT RTXs are handled later in | |
3879 | push_reload so we have to let them pass here. */ | |
3880 | if (GET_CODE (op) == SUBREG) | |
3881 | { | |
3882 | subreg = op; | |
3883 | op = SUBREG_REG (op); | |
3884 | mode = GET_MODE (op); | |
3885 | } | |
1f7f6676 | 3886 | |
e0a17959 AK |
3887 | if (GET_CODE (op) == PLUS) |
3888 | { | |
3889 | plus = op; | |
3890 | op = XEXP (op, 1); | |
3891 | } | |
eab89b90 | 3892 | |
e0a17959 AK |
3893 | if (CONST_POOL_OK_P (op) |
3894 | && ((PREFERRED_RELOAD_CLASS (op, | |
3895 | (enum reg_class) goal_alternative[i]) | |
3896 | == NO_REGS) | |
3897 | || no_input_reloads) | |
3898 | && mode != VOIDmode) | |
3899 | { | |
3900 | int this_address_reloaded; | |
3901 | rtx tem = force_const_mem (mode, op); | |
d58005c7 | 3902 | |
e0a17959 AK |
3903 | /* If we stripped a SUBREG or a PLUS above add it back. */ |
3904 | if (plus != NULL_RTX) | |
3905 | tem = gen_rtx_PLUS (mode, XEXP (plus, 0), tem); | |
3906 | ||
3907 | if (subreg != NULL_RTX) | |
3908 | tem = gen_rtx_SUBREG (operand_mode[i], tem, SUBREG_BYTE (subreg)); | |
3909 | ||
3910 | this_address_reloaded = 0; | |
3911 | substed_operand[i] = recog_data.operand[i] | |
3912 | = find_reloads_toplev (tem, i, address_type[i], ind_levels, | |
3913 | 0, insn, &this_address_reloaded); | |
3914 | ||
3915 | /* If the alternative accepts constant pool refs directly | |
3916 | there will be no reload needed at all. */ | |
3917 | if (plus == NULL_RTX | |
3918 | && subreg == NULL_RTX | |
3919 | && alternative_allows_const_pool_ref (this_address_reloaded == 0 | |
3920 | ? substed_operand[i] | |
3921 | : NULL, | |
3922 | recog_data.constraints[i], | |
3923 | goal_alternative_number)) | |
3924 | goal_alternative_win[i] = 1; | |
3925 | } | |
d58005c7 UW |
3926 | } |
3927 | ||
4644aad4 RK |
3928 | /* Record the values of the earlyclobber operands for the caller. */ |
3929 | if (goal_earlyclobber) | |
3930 | for (i = 0; i < noperands; i++) | |
3931 | if (goal_alternative_earlyclobber[i]) | |
1ccbefce | 3932 | reload_earlyclobbers[n_earlyclobbers++] = recog_data.operand[i]; |
4644aad4 | 3933 | |
eab89b90 RK |
3934 | /* Now record reloads for all the operands that need them. */ |
3935 | for (i = 0; i < noperands; i++) | |
3936 | if (! goal_alternative_win[i]) | |
3937 | { | |
3938 | /* Operands that match previous ones have already been handled. */ | |
3939 | if (goal_alternative_matches[i] >= 0) | |
3940 | ; | |
3941 | /* Handle an operand with a nonoffsettable address | |
3942 | appearing where an offsettable address will do | |
3a322c50 RK |
3943 | by reloading the address into a base register. |
3944 | ||
3945 | ??? We can also do this when the operand is a register and | |
3946 | reg_equiv_mem is not offsettable, but this is a bit tricky, | |
3947 | so we don't bother with it. It may not be worth doing. */ | |
eab89b90 RK |
3948 | else if (goal_alternative_matched[i] == -1 |
3949 | && goal_alternative_offmemok[i] | |
3c0cb5de | 3950 | && MEM_P (recog_data.operand[i])) |
eab89b90 | 3951 | { |
7c7ce73a UW |
3952 | /* If the address to be reloaded is a VOIDmode constant, |
3953 | use Pmode as mode of the reload register, as would have | |
3954 | been done by find_reloads_address. */ | |
3955 | enum machine_mode address_mode; | |
3956 | address_mode = GET_MODE (XEXP (recog_data.operand[i], 0)); | |
3957 | if (address_mode == VOIDmode) | |
3958 | address_mode = Pmode; | |
3959 | ||
eab89b90 | 3960 | operand_reloadnum[i] |
1ccbefce | 3961 | = push_reload (XEXP (recog_data.operand[i], 0), NULL_RTX, |
f4f4d0f8 | 3962 | &XEXP (recog_data.operand[i], 0), (rtx*) 0, |
c4963a0a | 3963 | base_reg_class (VOIDmode, MEM, SCRATCH), |
7c7ce73a | 3964 | address_mode, |
a8c9daeb | 3965 | VOIDmode, 0, 0, i, RELOAD_FOR_INPUT); |
eceef4c9 | 3966 | rld[operand_reloadnum[i]].inc |
1ccbefce | 3967 | = GET_MODE_SIZE (GET_MODE (recog_data.operand[i])); |
a8c9daeb RK |
3968 | |
3969 | /* If this operand is an output, we will have made any | |
3970 | reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but | |
3971 | now we are treating part of the operand as an input, so | |
3972 | we must change these to RELOAD_FOR_INPUT_ADDRESS. */ | |
3973 | ||
2d55b7e8 | 3974 | if (modified[i] == RELOAD_WRITE) |
47c8cf91 ILT |
3975 | { |
3976 | for (j = 0; j < n_reloads; j++) | |
3977 | { | |
eceef4c9 | 3978 | if (rld[j].opnum == i) |
47c8cf91 | 3979 | { |
eceef4c9 BS |
3980 | if (rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS) |
3981 | rld[j].when_needed = RELOAD_FOR_INPUT_ADDRESS; | |
3982 | else if (rld[j].when_needed | |
47c8cf91 | 3983 | == RELOAD_FOR_OUTADDR_ADDRESS) |
eceef4c9 | 3984 | rld[j].when_needed = RELOAD_FOR_INPADDR_ADDRESS; |
47c8cf91 ILT |
3985 | } |
3986 | } | |
3987 | } | |
eab89b90 RK |
3988 | } |
3989 | else if (goal_alternative_matched[i] == -1) | |
9ec36da5 JL |
3990 | { |
3991 | operand_reloadnum[i] | |
3992 | = push_reload ((modified[i] != RELOAD_WRITE | |
1ccbefce RH |
3993 | ? recog_data.operand[i] : 0), |
3994 | (modified[i] != RELOAD_READ | |
3995 | ? recog_data.operand[i] : 0), | |
9ec36da5 | 3996 | (modified[i] != RELOAD_WRITE |
1ccbefce | 3997 | ? recog_data.operand_loc[i] : 0), |
9ec36da5 | 3998 | (modified[i] != RELOAD_READ |
1ccbefce | 3999 | ? recog_data.operand_loc[i] : 0), |
9ec36da5 JL |
4000 | (enum reg_class) goal_alternative[i], |
4001 | (modified[i] == RELOAD_WRITE | |
4002 | ? VOIDmode : operand_mode[i]), | |
4003 | (modified[i] == RELOAD_READ | |
4004 | ? VOIDmode : operand_mode[i]), | |
4005 | (insn_code_number < 0 ? 0 | |
a995e389 | 4006 | : insn_data[insn_code_number].operand[i].strict_low), |
9ec36da5 | 4007 | 0, i, operand_type[i]); |
9ec36da5 | 4008 | } |
eab89b90 RK |
4009 | /* In a matching pair of operands, one must be input only |
4010 | and the other must be output only. | |
4011 | Pass the input operand as IN and the other as OUT. */ | |
4012 | else if (modified[i] == RELOAD_READ | |
4013 | && modified[goal_alternative_matched[i]] == RELOAD_WRITE) | |
4014 | { | |
4015 | operand_reloadnum[i] | |
1ccbefce RH |
4016 | = push_reload (recog_data.operand[i], |
4017 | recog_data.operand[goal_alternative_matched[i]], | |
4018 | recog_data.operand_loc[i], | |
4019 | recog_data.operand_loc[goal_alternative_matched[i]], | |
eab89b90 RK |
4020 | (enum reg_class) goal_alternative[i], |
4021 | operand_mode[i], | |
4022 | operand_mode[goal_alternative_matched[i]], | |
a8c9daeb | 4023 | 0, 0, i, RELOAD_OTHER); |
eab89b90 RK |
4024 | operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum; |
4025 | } | |
4026 | else if (modified[i] == RELOAD_WRITE | |
4027 | && modified[goal_alternative_matched[i]] == RELOAD_READ) | |
4028 | { | |
4029 | operand_reloadnum[goal_alternative_matched[i]] | |
1ccbefce RH |
4030 | = push_reload (recog_data.operand[goal_alternative_matched[i]], |
4031 | recog_data.operand[i], | |
4032 | recog_data.operand_loc[goal_alternative_matched[i]], | |
4033 | recog_data.operand_loc[i], | |
eab89b90 RK |
4034 | (enum reg_class) goal_alternative[i], |
4035 | operand_mode[goal_alternative_matched[i]], | |
4036 | operand_mode[i], | |
a8c9daeb | 4037 | 0, 0, i, RELOAD_OTHER); |
eab89b90 RK |
4038 | operand_reloadnum[i] = output_reloadnum; |
4039 | } | |
eab89b90 RK |
4040 | else |
4041 | { | |
41374e13 | 4042 | gcc_assert (insn_code_number < 0); |
971801ff JM |
4043 | error_for_asm (insn, "inconsistent operand constraints " |
4044 | "in an %<asm%>"); | |
eab89b90 | 4045 | /* Avoid further trouble with this insn. */ |
38a448ca | 4046 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
eab89b90 | 4047 | n_reloads = 0; |
cb2afeb3 | 4048 | return 0; |
eab89b90 RK |
4049 | } |
4050 | } | |
4051 | else if (goal_alternative_matched[i] < 0 | |
112f7223 | 4052 | && goal_alternative_matches[i] < 0 |
0b540f12 | 4053 | && address_operand_reloaded[i] != 1 |
112f7223 | 4054 | && optimize) |
eab89b90 | 4055 | { |
05d10675 | 4056 | /* For each non-matching operand that's a MEM or a pseudo-register |
eab89b90 RK |
4057 | that didn't get a hard register, make an optional reload. |
4058 | This may get done even if the insn needs no reloads otherwise. */ | |
a8c9daeb | 4059 | |
1ccbefce | 4060 | rtx operand = recog_data.operand[i]; |
a8c9daeb | 4061 | |
eab89b90 | 4062 | while (GET_CODE (operand) == SUBREG) |
ddef6bc7 | 4063 | operand = SUBREG_REG (operand); |
3c0cb5de | 4064 | if ((MEM_P (operand) |
f8cfc6aa | 4065 | || (REG_P (operand) |
a8c9daeb | 4066 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) |
cb2afeb3 R |
4067 | /* If this is only for an output, the optional reload would not |
4068 | actually cause us to use a register now, just note that | |
4069 | something is stored here. */ | |
4070 | && ((enum reg_class) goal_alternative[i] != NO_REGS | |
4071 | || modified[i] == RELOAD_WRITE) | |
a8c9daeb | 4072 | && ! no_input_reloads |
cb2afeb3 R |
4073 | /* An optional output reload might allow to delete INSN later. |
4074 | We mustn't make in-out reloads on insns that are not permitted | |
4075 | output reloads. | |
4076 | If this is an asm, we can't delete it; we must not even call | |
4077 | push_reload for an optional output reload in this case, | |
4078 | because we can't be sure that the constraint allows a register, | |
4079 | and push_reload verifies the constraints for asms. */ | |
eab89b90 | 4080 | && (modified[i] == RELOAD_READ |
cb2afeb3 | 4081 | || (! no_output_reloads && ! this_insn_is_asm))) |
eab89b90 | 4082 | operand_reloadnum[i] |
1ccbefce RH |
4083 | = push_reload ((modified[i] != RELOAD_WRITE |
4084 | ? recog_data.operand[i] : 0), | |
4085 | (modified[i] != RELOAD_READ | |
4086 | ? recog_data.operand[i] : 0), | |
a8c9daeb | 4087 | (modified[i] != RELOAD_WRITE |
1ccbefce | 4088 | ? recog_data.operand_loc[i] : 0), |
a8c9daeb | 4089 | (modified[i] != RELOAD_READ |
1ccbefce | 4090 | ? recog_data.operand_loc[i] : 0), |
eab89b90 | 4091 | (enum reg_class) goal_alternative[i], |
a8c9daeb RK |
4092 | (modified[i] == RELOAD_WRITE |
4093 | ? VOIDmode : operand_mode[i]), | |
4094 | (modified[i] == RELOAD_READ | |
4095 | ? VOIDmode : operand_mode[i]), | |
eab89b90 | 4096 | (insn_code_number < 0 ? 0 |
a995e389 | 4097 | : insn_data[insn_code_number].operand[i].strict_low), |
a8c9daeb | 4098 | 1, i, operand_type[i]); |
87afbee6 JL |
4099 | /* If a memory reference remains (either as a MEM or a pseudo that |
4100 | did not get a hard register), yet we can't make an optional | |
cb2afeb3 R |
4101 | reload, check if this is actually a pseudo register reference; |
4102 | we then need to emit a USE and/or a CLOBBER so that reload | |
4103 | inheritance will do the right thing. */ | |
112f7223 | 4104 | else if (replace |
3c0cb5de | 4105 | && (MEM_P (operand) |
f8cfc6aa | 4106 | || (REG_P (operand) |
112f7223 UW |
4107 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER |
4108 | && reg_renumber [REGNO (operand)] < 0))) | |
cb2afeb3 | 4109 | { |
1ccbefce | 4110 | operand = *recog_data.operand_loc[i]; |
cb2afeb3 R |
4111 | |
4112 | while (GET_CODE (operand) == SUBREG) | |
ddef6bc7 | 4113 | operand = SUBREG_REG (operand); |
f8cfc6aa | 4114 | if (REG_P (operand)) |
cb2afeb3 R |
4115 | { |
4116 | if (modified[i] != RELOAD_WRITE) | |
3d17d93d AO |
4117 | /* We mark the USE with QImode so that we recognize |
4118 | it as one that can be safely deleted at the end | |
4119 | of reload. */ | |
4120 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, operand), | |
4121 | insn), QImode); | |
cb2afeb3 | 4122 | if (modified[i] != RELOAD_READ) |
c41c1387 | 4123 | emit_insn_after (gen_clobber (operand), insn); |
cb2afeb3 R |
4124 | } |
4125 | } | |
eab89b90 | 4126 | } |
a8c9daeb RK |
4127 | else if (goal_alternative_matches[i] >= 0 |
4128 | && goal_alternative_win[goal_alternative_matches[i]] | |
4129 | && modified[i] == RELOAD_READ | |
4130 | && modified[goal_alternative_matches[i]] == RELOAD_WRITE | |
112f7223 UW |
4131 | && ! no_input_reloads && ! no_output_reloads |
4132 | && optimize) | |
a8c9daeb RK |
4133 | { |
4134 | /* Similarly, make an optional reload for a pair of matching | |
4135 | objects that are in MEM or a pseudo that didn't get a hard reg. */ | |
eab89b90 | 4136 | |
1ccbefce | 4137 | rtx operand = recog_data.operand[i]; |
a8c9daeb RK |
4138 | |
4139 | while (GET_CODE (operand) == SUBREG) | |
ddef6bc7 | 4140 | operand = SUBREG_REG (operand); |
3c0cb5de | 4141 | if ((MEM_P (operand) |
f8cfc6aa | 4142 | || (REG_P (operand) |
a8c9daeb RK |
4143 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) |
4144 | && ((enum reg_class) goal_alternative[goal_alternative_matches[i]] | |
4145 | != NO_REGS)) | |
4146 | operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]] | |
1ccbefce RH |
4147 | = push_reload (recog_data.operand[goal_alternative_matches[i]], |
4148 | recog_data.operand[i], | |
4149 | recog_data.operand_loc[goal_alternative_matches[i]], | |
4150 | recog_data.operand_loc[i], | |
a8c9daeb RK |
4151 | (enum reg_class) goal_alternative[goal_alternative_matches[i]], |
4152 | operand_mode[goal_alternative_matches[i]], | |
4153 | operand_mode[i], | |
4154 | 0, 1, goal_alternative_matches[i], RELOAD_OTHER); | |
4155 | } | |
05d10675 | 4156 | |
cb2afeb3 R |
4157 | /* Perform whatever substitutions on the operands we are supposed |
4158 | to make due to commutativity or replacement of registers | |
4159 | with equivalent constants or memory slots. */ | |
4160 | ||
4161 | for (i = 0; i < noperands; i++) | |
4162 | { | |
4163 | /* We only do this on the last pass through reload, because it is | |
05d10675 | 4164 | possible for some data (like reg_equiv_address) to be changed during |
425de739 | 4165 | later passes. Moreover, we lose the opportunity to get a useful |
05d10675 | 4166 | reload_{in,out}_reg when we do these replacements. */ |
cb2afeb3 R |
4167 | |
4168 | if (replace) | |
e54db24f MM |
4169 | { |
4170 | rtx substitution = substed_operand[i]; | |
4171 | ||
1ccbefce | 4172 | *recog_data.operand_loc[i] = substitution; |
e54db24f | 4173 | |
cf7c4aa6 HPN |
4174 | /* If we're replacing an operand with a LABEL_REF, we need to |
4175 | make sure that there's a REG_LABEL_OPERAND note attached to | |
e54db24f | 4176 | this instruction. */ |
cf7c4aa6 HPN |
4177 | if (GET_CODE (substitution) == LABEL_REF |
4178 | && !find_reg_note (insn, REG_LABEL_OPERAND, | |
4179 | XEXP (substitution, 0)) | |
4180 | /* For a JUMP_P, if it was a branch target it must have | |
4181 | already been recorded as such. */ | |
4182 | && (!JUMP_P (insn) | |
4183 | || !label_is_jump_target_p (XEXP (substitution, 0), | |
4184 | insn))) | |
65c5f2a6 | 4185 | add_reg_note (insn, REG_LABEL_OPERAND, XEXP (substitution, 0)); |
e54db24f | 4186 | } |
cb2afeb3 | 4187 | else |
1ccbefce | 4188 | retval |= (substed_operand[i] != *recog_data.operand_loc[i]); |
cb2afeb3 R |
4189 | } |
4190 | ||
eab89b90 RK |
4191 | /* If this insn pattern contains any MATCH_DUP's, make sure that |
4192 | they will be substituted if the operands they match are substituted. | |
4193 | Also do now any substitutions we already did on the operands. | |
4194 | ||
4195 | Don't do this if we aren't making replacements because we might be | |
4196 | propagating things allocated by frame pointer elimination into places | |
4197 | it doesn't expect. */ | |
4198 | ||
4199 | if (insn_code_number >= 0 && replace) | |
a995e389 | 4200 | for (i = insn_data[insn_code_number].n_dups - 1; i >= 0; i--) |
eab89b90 | 4201 | { |
1ccbefce RH |
4202 | int opno = recog_data.dup_num[i]; |
4203 | *recog_data.dup_loc[i] = *recog_data.operand_loc[opno]; | |
6cabe79e | 4204 | dup_replacements (recog_data.dup_loc[i], recog_data.operand_loc[opno]); |
eab89b90 RK |
4205 | } |
4206 | ||
4207 | #if 0 | |
4208 | /* This loses because reloading of prior insns can invalidate the equivalence | |
4209 | (or at least find_equiv_reg isn't smart enough to find it any more), | |
4210 | causing this insn to need more reload regs than it needed before. | |
4211 | It may be too late to make the reload regs available. | |
4212 | Now this optimization is done safely in choose_reload_regs. */ | |
4213 | ||
4214 | /* For each reload of a reg into some other class of reg, | |
4215 | search for an existing equivalent reg (same value now) in the right class. | |
4216 | We can use it as long as we don't need to change its contents. */ | |
4217 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 BS |
4218 | if (rld[i].reg_rtx == 0 |
4219 | && rld[i].in != 0 | |
f8cfc6aa | 4220 | && REG_P (rld[i].in) |
eceef4c9 | 4221 | && rld[i].out == 0) |
eab89b90 | 4222 | { |
eceef4c9 | 4223 | rld[i].reg_rtx |
48c54229 | 4224 | = find_equiv_reg (rld[i].in, insn, rld[i].rclass, -1, |
eceef4c9 | 4225 | static_reload_reg_p, 0, rld[i].inmode); |
eab89b90 RK |
4226 | /* Prevent generation of insn to load the value |
4227 | because the one we found already has the value. */ | |
eceef4c9 BS |
4228 | if (rld[i].reg_rtx) |
4229 | rld[i].in = rld[i].reg_rtx; | |
eab89b90 RK |
4230 | } |
4231 | #endif | |
4232 | ||
71156bcc JH |
4233 | /* If we detected error and replaced asm instruction by USE, forget about the |
4234 | reloads. */ | |
4235 | if (GET_CODE (PATTERN (insn)) == USE | |
481683e1 | 4236 | && CONST_INT_P (XEXP (PATTERN (insn), 0))) |
71156bcc JH |
4237 | n_reloads = 0; |
4238 | ||
a8c9daeb RK |
4239 | /* Perhaps an output reload can be combined with another |
4240 | to reduce needs by one. */ | |
4241 | if (!goal_earlyclobber) | |
4242 | combine_reloads (); | |
4243 | ||
4244 | /* If we have a pair of reloads for parts of an address, they are reloading | |
4245 | the same object, the operands themselves were not reloaded, and they | |
4246 | are for two operands that are supposed to match, merge the reloads and | |
0f41302f | 4247 | change the type of the surviving reload to RELOAD_FOR_OPERAND_ADDRESS. */ |
a8c9daeb RK |
4248 | |
4249 | for (i = 0; i < n_reloads; i++) | |
4250 | { | |
4251 | int k; | |
4252 | ||
4253 | for (j = i + 1; j < n_reloads; j++) | |
eceef4c9 BS |
4254 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS |
4255 | || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
4256 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS | |
4257 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4258 | && (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
4259 | || rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
4260 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS | |
4261 | || rld[j].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4262 | && rtx_equal_p (rld[i].in, rld[j].in) | |
4263 | && (operand_reloadnum[rld[i].opnum] < 0 | |
4264 | || rld[operand_reloadnum[rld[i].opnum]].optional) | |
4265 | && (operand_reloadnum[rld[j].opnum] < 0 | |
4266 | || rld[operand_reloadnum[rld[j].opnum]].optional) | |
4267 | && (goal_alternative_matches[rld[i].opnum] == rld[j].opnum | |
4268 | || (goal_alternative_matches[rld[j].opnum] | |
4269 | == rld[i].opnum))) | |
a8c9daeb RK |
4270 | { |
4271 | for (k = 0; k < n_replacements; k++) | |
4272 | if (replacements[k].what == j) | |
4273 | replacements[k].what = i; | |
4274 | ||
eceef4c9 BS |
4275 | if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS |
4276 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4277 | rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR; | |
47c8cf91 | 4278 | else |
eceef4c9 BS |
4279 | rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS; |
4280 | rld[j].in = 0; | |
a8c9daeb RK |
4281 | } |
4282 | } | |
4283 | ||
05d10675 | 4284 | /* Scan all the reloads and update their type. |
a8c9daeb RK |
4285 | If a reload is for the address of an operand and we didn't reload |
4286 | that operand, change the type. Similarly, change the operand number | |
4287 | of a reload when two operands match. If a reload is optional, treat it | |
4288 | as though the operand isn't reloaded. | |
4289 | ||
4290 | ??? This latter case is somewhat odd because if we do the optional | |
4291 | reload, it means the object is hanging around. Thus we need only | |
4292 | do the address reload if the optional reload was NOT done. | |
4293 | ||
4294 | Change secondary reloads to be the address type of their operand, not | |
4295 | the normal type. | |
4296 | ||
4297 | If an operand's reload is now RELOAD_OTHER, change any | |
4298 | RELOAD_FOR_INPUT_ADDRESS reloads of that operand to | |
4299 | RELOAD_FOR_OTHER_ADDRESS. */ | |
4300 | ||
4301 | for (i = 0; i < n_reloads; i++) | |
4302 | { | |
eceef4c9 | 4303 | if (rld[i].secondary_p |
38323cc3 RH |
4304 | && rld[i].when_needed == operand_type[rld[i].opnum]) |
4305 | rld[i].when_needed = address_type[rld[i].opnum]; | |
eceef4c9 BS |
4306 | |
4307 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
4308 | || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
4309 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS | |
4310 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4311 | && (operand_reloadnum[rld[i].opnum] < 0 | |
4312 | || rld[operand_reloadnum[rld[i].opnum]].optional)) | |
f98bb7d3 RK |
4313 | { |
4314 | /* If we have a secondary reload to go along with this reload, | |
0f41302f | 4315 | change its type to RELOAD_FOR_OPADDR_ADDR. */ |
f98bb7d3 | 4316 | |
eceef4c9 BS |
4317 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS |
4318 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
4319 | && rld[i].secondary_in_reload != -1) | |
f98bb7d3 | 4320 | { |
eceef4c9 | 4321 | int secondary_in_reload = rld[i].secondary_in_reload; |
f98bb7d3 | 4322 | |
4381f7c2 | 4323 | rld[secondary_in_reload].when_needed = RELOAD_FOR_OPADDR_ADDR; |
f98bb7d3 | 4324 | |
0f41302f | 4325 | /* If there's a tertiary reload we have to change it also. */ |
f98bb7d3 | 4326 | if (secondary_in_reload > 0 |
eceef4c9 BS |
4327 | && rld[secondary_in_reload].secondary_in_reload != -1) |
4328 | rld[rld[secondary_in_reload].secondary_in_reload].when_needed | |
38323cc3 | 4329 | = RELOAD_FOR_OPADDR_ADDR; |
f98bb7d3 RK |
4330 | } |
4331 | ||
eceef4c9 BS |
4332 | if ((rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS |
4333 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4334 | && rld[i].secondary_out_reload != -1) | |
f98bb7d3 | 4335 | { |
eceef4c9 | 4336 | int secondary_out_reload = rld[i].secondary_out_reload; |
f98bb7d3 | 4337 | |
4381f7c2 | 4338 | rld[secondary_out_reload].when_needed = RELOAD_FOR_OPADDR_ADDR; |
f98bb7d3 | 4339 | |
0f41302f | 4340 | /* If there's a tertiary reload we have to change it also. */ |
f98bb7d3 | 4341 | if (secondary_out_reload |
eceef4c9 BS |
4342 | && rld[secondary_out_reload].secondary_out_reload != -1) |
4343 | rld[rld[secondary_out_reload].secondary_out_reload].when_needed | |
38323cc3 | 4344 | = RELOAD_FOR_OPADDR_ADDR; |
f98bb7d3 | 4345 | } |
e5e809f4 | 4346 | |
eceef4c9 BS |
4347 | if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS |
4348 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4349 | rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR; | |
cb2afeb3 | 4350 | else |
eceef4c9 | 4351 | rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS; |
f98bb7d3 | 4352 | } |
a8c9daeb | 4353 | |
eceef4c9 BS |
4354 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS |
4355 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
4356 | && operand_reloadnum[rld[i].opnum] >= 0 | |
4357 | && (rld[operand_reloadnum[rld[i].opnum]].when_needed | |
a8c9daeb | 4358 | == RELOAD_OTHER)) |
eceef4c9 | 4359 | rld[i].when_needed = RELOAD_FOR_OTHER_ADDRESS; |
a8c9daeb | 4360 | |
eceef4c9 BS |
4361 | if (goal_alternative_matches[rld[i].opnum] >= 0) |
4362 | rld[i].opnum = goal_alternative_matches[rld[i].opnum]; | |
a8c9daeb RK |
4363 | } |
4364 | ||
a94ce333 JW |
4365 | /* Scan all the reloads, and check for RELOAD_FOR_OPERAND_ADDRESS reloads. |
4366 | If we have more than one, then convert all RELOAD_FOR_OPADDR_ADDR | |
4367 | reloads to RELOAD_FOR_OPERAND_ADDRESS reloads. | |
4368 | ||
4369 | choose_reload_regs assumes that RELOAD_FOR_OPADDR_ADDR reloads never | |
4370 | conflict with RELOAD_FOR_OPERAND_ADDRESS reloads. This is true for a | |
4371 | single pair of RELOAD_FOR_OPADDR_ADDR/RELOAD_FOR_OPERAND_ADDRESS reloads. | |
4372 | However, if there is more than one RELOAD_FOR_OPERAND_ADDRESS reload, | |
4373 | then a RELOAD_FOR_OPADDR_ADDR reload conflicts with all | |
4374 | RELOAD_FOR_OPERAND_ADDRESS reloads other than the one that uses it. | |
4375 | This is complicated by the fact that a single operand can have more | |
4376 | than one RELOAD_FOR_OPERAND_ADDRESS reload. It is very difficult to fix | |
4377 | choose_reload_regs without affecting code quality, and cases that | |
4378 | actually fail are extremely rare, so it turns out to be better to fix | |
4379 | the problem here by not generating cases that choose_reload_regs will | |
4380 | fail for. */ | |
d3adbeea | 4381 | /* There is a similar problem with RELOAD_FOR_INPUT_ADDRESS / |
826e3854 R |
4382 | RELOAD_FOR_OUTPUT_ADDRESS when there is more than one of a kind for |
4383 | a single operand. | |
4384 | We can reduce the register pressure by exploiting that a | |
4385 | RELOAD_FOR_X_ADDR_ADDR that precedes all RELOAD_FOR_X_ADDRESS reloads | |
c10638c9 R |
4386 | does not conflict with any of them, if it is only used for the first of |
4387 | the RELOAD_FOR_X_ADDRESS reloads. */ | |
a94ce333 | 4388 | { |
826e3854 R |
4389 | int first_op_addr_num = -2; |
4390 | int first_inpaddr_num[MAX_RECOG_OPERANDS]; | |
4391 | int first_outpaddr_num[MAX_RECOG_OPERANDS]; | |
4381f7c2 | 4392 | int need_change = 0; |
826e3854 R |
4393 | /* We use last_op_addr_reload and the contents of the above arrays |
4394 | first as flags - -2 means no instance encountered, -1 means exactly | |
4395 | one instance encountered. | |
4396 | If more than one instance has been encountered, we store the reload | |
4397 | number of the first reload of the kind in question; reload numbers | |
4398 | are known to be non-negative. */ | |
4399 | for (i = 0; i < noperands; i++) | |
4400 | first_inpaddr_num[i] = first_outpaddr_num[i] = -2; | |
4401 | for (i = n_reloads - 1; i >= 0; i--) | |
4402 | { | |
eceef4c9 | 4403 | switch (rld[i].when_needed) |
826e3854 R |
4404 | { |
4405 | case RELOAD_FOR_OPERAND_ADDRESS: | |
c10638c9 | 4406 | if (++first_op_addr_num >= 0) |
826e3854 | 4407 | { |
c10638c9 | 4408 | first_op_addr_num = i; |
826e3854 R |
4409 | need_change = 1; |
4410 | } | |
4411 | break; | |
4412 | case RELOAD_FOR_INPUT_ADDRESS: | |
eceef4c9 | 4413 | if (++first_inpaddr_num[rld[i].opnum] >= 0) |
826e3854 | 4414 | { |
eceef4c9 | 4415 | first_inpaddr_num[rld[i].opnum] = i; |
826e3854 R |
4416 | need_change = 1; |
4417 | } | |
4418 | break; | |
4419 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
eceef4c9 | 4420 | if (++first_outpaddr_num[rld[i].opnum] >= 0) |
826e3854 | 4421 | { |
eceef4c9 | 4422 | first_outpaddr_num[rld[i].opnum] = i; |
826e3854 R |
4423 | need_change = 1; |
4424 | } | |
4425 | break; | |
4426 | default: | |
4427 | break; | |
4428 | } | |
4429 | } | |
a94ce333 | 4430 | |
826e3854 R |
4431 | if (need_change) |
4432 | { | |
4433 | for (i = 0; i < n_reloads; i++) | |
4434 | { | |
c8d8ed65 RK |
4435 | int first_num; |
4436 | enum reload_type type; | |
826e3854 | 4437 | |
eceef4c9 | 4438 | switch (rld[i].when_needed) |
826e3854 R |
4439 | { |
4440 | case RELOAD_FOR_OPADDR_ADDR: | |
4441 | first_num = first_op_addr_num; | |
4442 | type = RELOAD_FOR_OPERAND_ADDRESS; | |
4443 | break; | |
4444 | case RELOAD_FOR_INPADDR_ADDRESS: | |
eceef4c9 | 4445 | first_num = first_inpaddr_num[rld[i].opnum]; |
826e3854 R |
4446 | type = RELOAD_FOR_INPUT_ADDRESS; |
4447 | break; | |
4448 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
eceef4c9 | 4449 | first_num = first_outpaddr_num[rld[i].opnum]; |
826e3854 R |
4450 | type = RELOAD_FOR_OUTPUT_ADDRESS; |
4451 | break; | |
4452 | default: | |
4453 | continue; | |
4454 | } | |
c10638c9 R |
4455 | if (first_num < 0) |
4456 | continue; | |
4457 | else if (i > first_num) | |
eceef4c9 | 4458 | rld[i].when_needed = type; |
c10638c9 R |
4459 | else |
4460 | { | |
4461 | /* Check if the only TYPE reload that uses reload I is | |
4462 | reload FIRST_NUM. */ | |
4463 | for (j = n_reloads - 1; j > first_num; j--) | |
4464 | { | |
eceef4c9 BS |
4465 | if (rld[j].when_needed == type |
4466 | && (rld[i].secondary_p | |
4467 | ? rld[j].secondary_in_reload == i | |
4468 | : reg_mentioned_p (rld[i].in, rld[j].in))) | |
c10638c9 | 4469 | { |
eceef4c9 | 4470 | rld[i].when_needed = type; |
c10638c9 R |
4471 | break; |
4472 | } | |
4473 | } | |
4474 | } | |
826e3854 R |
4475 | } |
4476 | } | |
a94ce333 JW |
4477 | } |
4478 | ||
a8c9daeb RK |
4479 | /* See if we have any reloads that are now allowed to be merged |
4480 | because we've changed when the reload is needed to | |
4481 | RELOAD_FOR_OPERAND_ADDRESS or RELOAD_FOR_OTHER_ADDRESS. Only | |
4482 | check for the most common cases. */ | |
4483 | ||
4484 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 BS |
4485 | if (rld[i].in != 0 && rld[i].out == 0 |
4486 | && (rld[i].when_needed == RELOAD_FOR_OPERAND_ADDRESS | |
4487 | || rld[i].when_needed == RELOAD_FOR_OPADDR_ADDR | |
4488 | || rld[i].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
a8c9daeb | 4489 | for (j = 0; j < n_reloads; j++) |
eceef4c9 BS |
4490 | if (i != j && rld[j].in != 0 && rld[j].out == 0 |
4491 | && rld[j].when_needed == rld[i].when_needed | |
4492 | && MATCHES (rld[i].in, rld[j].in) | |
48c54229 | 4493 | && rld[i].rclass == rld[j].rclass |
eceef4c9 BS |
4494 | && !rld[i].nocombine && !rld[j].nocombine |
4495 | && rld[i].reg_rtx == rld[j].reg_rtx) | |
a8c9daeb | 4496 | { |
eceef4c9 | 4497 | rld[i].opnum = MIN (rld[i].opnum, rld[j].opnum); |
a8c9daeb | 4498 | transfer_replacements (i, j); |
eceef4c9 | 4499 | rld[j].in = 0; |
a8c9daeb RK |
4500 | } |
4501 | ||
14a774a9 RK |
4502 | #ifdef HAVE_cc0 |
4503 | /* If we made any reloads for addresses, see if they violate a | |
4504 | "no input reloads" requirement for this insn. But loads that we | |
4505 | do after the insn (such as for output addresses) are fine. */ | |
4506 | if (no_input_reloads) | |
4507 | for (i = 0; i < n_reloads; i++) | |
41374e13 NS |
4508 | gcc_assert (rld[i].in == 0 |
4509 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS | |
4510 | || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS); | |
14a774a9 RK |
4511 | #endif |
4512 | ||
67e61fe7 BS |
4513 | /* Compute reload_mode and reload_nregs. */ |
4514 | for (i = 0; i < n_reloads; i++) | |
4515 | { | |
4516 | rld[i].mode | |
4517 | = (rld[i].inmode == VOIDmode | |
4518 | || (GET_MODE_SIZE (rld[i].outmode) | |
4519 | > GET_MODE_SIZE (rld[i].inmode))) | |
4520 | ? rld[i].outmode : rld[i].inmode; | |
4521 | ||
48c54229 | 4522 | rld[i].nregs = CLASS_MAX_NREGS (rld[i].rclass, rld[i].mode); |
67e61fe7 BS |
4523 | } |
4524 | ||
02a10130 RH |
4525 | /* Special case a simple move with an input reload and a |
4526 | destination of a hard reg, if the hard reg is ok, use it. */ | |
4527 | for (i = 0; i < n_reloads; i++) | |
4528 | if (rld[i].when_needed == RELOAD_FOR_INPUT | |
4529 | && GET_CODE (PATTERN (insn)) == SET | |
f8cfc6aa | 4530 | && REG_P (SET_DEST (PATTERN (insn))) |
b3519e7c L |
4531 | && (SET_SRC (PATTERN (insn)) == rld[i].in |
4532 | || SET_SRC (PATTERN (insn)) == rld[i].in_reg) | |
8c74fb06 | 4533 | && !elimination_target_reg_p (SET_DEST (PATTERN (insn)))) |
02a10130 | 4534 | { |
0c20a65f | 4535 | rtx dest = SET_DEST (PATTERN (insn)); |
02a10130 RH |
4536 | unsigned int regno = REGNO (dest); |
4537 | ||
0c20a65f | 4538 | if (regno < FIRST_PSEUDO_REGISTER |
48c54229 | 4539 | && TEST_HARD_REG_BIT (reg_class_contents[rld[i].rclass], regno) |
0c20a65f | 4540 | && HARD_REGNO_MODE_OK (regno, rld[i].mode)) |
57458e8a | 4541 | { |
66fd46b6 | 4542 | int nr = hard_regno_nregs[regno][rld[i].mode]; |
57458e8a DD |
4543 | int ok = 1, nri; |
4544 | ||
4545 | for (nri = 1; nri < nr; nri ++) | |
48c54229 | 4546 | if (! TEST_HARD_REG_BIT (reg_class_contents[rld[i].rclass], regno + nri)) |
57458e8a DD |
4547 | ok = 0; |
4548 | ||
4549 | if (ok) | |
4550 | rld[i].reg_rtx = dest; | |
4551 | } | |
02a10130 RH |
4552 | } |
4553 | ||
cb2afeb3 | 4554 | return retval; |
eab89b90 RK |
4555 | } |
4556 | ||
1f7f6676 RS |
4557 | /* Return true if alternative number ALTNUM in constraint-string |
4558 | CONSTRAINT is guaranteed to accept a reloaded constant-pool reference. | |
4559 | MEM gives the reference if it didn't need any reloads, otherwise it | |
4560 | is null. */ | |
eab89b90 | 4561 | |
1f7f6676 RS |
4562 | static bool |
4563 | alternative_allows_const_pool_ref (rtx mem, const char *constraint, int altnum) | |
eab89b90 | 4564 | { |
b3694847 | 4565 | int c; |
1f7f6676 | 4566 | |
eab89b90 RK |
4567 | /* Skip alternatives before the one requested. */ |
4568 | while (altnum > 0) | |
4569 | { | |
4570 | while (*constraint++ != ','); | |
4571 | altnum--; | |
4572 | } | |
a4edaf83 | 4573 | /* Scan the requested alternative for TARGET_MEM_CONSTRAINT or 'o'. |
1f7f6676 RS |
4574 | If one of them is present, this alternative accepts the result of |
4575 | passing a constant-pool reference through find_reloads_toplev. | |
4576 | ||
4577 | The same is true of extra memory constraints if the address | |
4578 | was reloaded into a register. However, the target may elect | |
4579 | to disallow the original constant address, forcing it to be | |
4580 | reloaded into a register instead. */ | |
97488870 R |
4581 | for (; (c = *constraint) && c != ',' && c != '#'; |
4582 | constraint += CONSTRAINT_LEN (c, constraint)) | |
1f7f6676 | 4583 | { |
a4edaf83 | 4584 | if (c == TARGET_MEM_CONSTRAINT || c == 'o') |
1f7f6676 RS |
4585 | return true; |
4586 | #ifdef EXTRA_CONSTRAINT_STR | |
4587 | if (EXTRA_MEMORY_CONSTRAINT (c, constraint) | |
4588 | && (mem == NULL || EXTRA_CONSTRAINT_STR (mem, c, constraint))) | |
4589 | return true; | |
4590 | #endif | |
4591 | } | |
4592 | return false; | |
eab89b90 RK |
4593 | } |
4594 | \f | |
4595 | /* Scan X for memory references and scan the addresses for reloading. | |
4596 | Also checks for references to "constant" regs that we want to eliminate | |
4597 | and replaces them with the values they stand for. | |
6dc42e49 | 4598 | We may alter X destructively if it contains a reference to such. |
eab89b90 RK |
4599 | If X is just a constant reg, we return the equivalent value |
4600 | instead of X. | |
4601 | ||
4602 | IND_LEVELS says how many levels of indirect addressing this machine | |
4603 | supports. | |
4604 | ||
a8c9daeb RK |
4605 | OPNUM and TYPE identify the purpose of the reload. |
4606 | ||
eab89b90 | 4607 | IS_SET_DEST is true if X is the destination of a SET, which is not |
cb2afeb3 R |
4608 | appropriate to be replaced by a constant. |
4609 | ||
4610 | INSN, if nonzero, is the insn in which we do the reload. It is used | |
4611 | to determine if we may generate output reloads, and where to put USEs | |
9246aadb AH |
4612 | for pseudos that we have to replace with stack slots. |
4613 | ||
4614 | ADDRESS_RELOADED. If nonzero, is a pointer to where we put the | |
4615 | result of find_reloads_address. */ | |
eab89b90 RK |
4616 | |
4617 | static rtx | |
0c20a65f AJ |
4618 | find_reloads_toplev (rtx x, int opnum, enum reload_type type, |
4619 | int ind_levels, int is_set_dest, rtx insn, | |
4620 | int *address_reloaded) | |
eab89b90 | 4621 | { |
b3694847 | 4622 | RTX_CODE code = GET_CODE (x); |
eab89b90 | 4623 | |
b3694847 SS |
4624 | const char *fmt = GET_RTX_FORMAT (code); |
4625 | int i; | |
9f4749b1 | 4626 | int copied; |
eab89b90 RK |
4627 | |
4628 | if (code == REG) | |
4629 | { | |
4630 | /* This code is duplicated for speed in find_reloads. */ | |
b3694847 | 4631 | int regno = REGNO (x); |
eab89b90 RK |
4632 | if (reg_equiv_constant[regno] != 0 && !is_set_dest) |
4633 | x = reg_equiv_constant[regno]; | |
4634 | #if 0 | |
05d10675 BS |
4635 | /* This creates (subreg (mem...)) which would cause an unnecessary |
4636 | reload of the mem. */ | |
eab89b90 RK |
4637 | else if (reg_equiv_mem[regno] != 0) |
4638 | x = reg_equiv_mem[regno]; | |
4639 | #endif | |
cb2afeb3 R |
4640 | else if (reg_equiv_memory_loc[regno] |
4641 | && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)) | |
eab89b90 | 4642 | { |
cb2afeb3 R |
4643 | rtx mem = make_memloc (x, regno); |
4644 | if (reg_equiv_address[regno] | |
4645 | || ! rtx_equal_p (mem, reg_equiv_mem[regno])) | |
4646 | { | |
4647 | /* If this is not a toplevel operand, find_reloads doesn't see | |
4648 | this substitution. We have to emit a USE of the pseudo so | |
4649 | that delete_output_reload can see it. */ | |
1ccbefce | 4650 | if (replace_reloads && recog_data.operand[opnum] != x) |
3d17d93d AO |
4651 | /* We mark the USE with QImode so that we recognize it |
4652 | as one that can be safely deleted at the end of | |
4653 | reload. */ | |
4654 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, x), insn), | |
4655 | QImode); | |
cb2afeb3 | 4656 | x = mem; |
9246aadb AH |
4657 | i = find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), &XEXP (x, 0), |
4658 | opnum, type, ind_levels, insn); | |
0f4b25a3 | 4659 | if (!rtx_equal_p (x, mem)) |
3f1e3e70 | 4660 | push_reg_equiv_alt_mem (regno, x); |
9246aadb AH |
4661 | if (address_reloaded) |
4662 | *address_reloaded = i; | |
cb2afeb3 | 4663 | } |
eab89b90 RK |
4664 | } |
4665 | return x; | |
4666 | } | |
4667 | if (code == MEM) | |
4668 | { | |
4669 | rtx tem = x; | |
9246aadb AH |
4670 | |
4671 | i = find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0), | |
4672 | opnum, type, ind_levels, insn); | |
4673 | if (address_reloaded) | |
4674 | *address_reloaded = i; | |
4675 | ||
eab89b90 RK |
4676 | return tem; |
4677 | } | |
4678 | ||
f8cfc6aa | 4679 | if (code == SUBREG && REG_P (SUBREG_REG (x))) |
eab89b90 | 4680 | { |
0e61db61 NS |
4681 | /* Check for SUBREG containing a REG that's equivalent to a |
4682 | constant. If the constant has a known value, truncate it | |
4683 | right now. Similarly if we are extracting a single-word of a | |
4684 | multi-word constant. If the constant is symbolic, allow it | |
4685 | to be substituted normally. push_reload will strip the | |
4686 | subreg later. The constant must not be VOIDmode, because we | |
4687 | will lose the mode of the register (this should never happen | |
4688 | because one of the cases above should handle it). */ | |
eab89b90 | 4689 | |
b3694847 | 4690 | int regno = REGNO (SUBREG_REG (x)); |
eab89b90 RK |
4691 | rtx tem; |
4692 | ||
857e5753 RS |
4693 | if (regno >= FIRST_PSEUDO_REGISTER |
4694 | && reg_renumber[regno] < 0 | |
451f86fd | 4695 | && reg_equiv_constant[regno] != 0) |
0365438d | 4696 | { |
451f86fd R |
4697 | tem = |
4698 | simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno], | |
4699 | GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); | |
41374e13 | 4700 | gcc_assert (tem); |
c07fdd94 RS |
4701 | if (CONSTANT_P (tem) && !LEGITIMATE_CONSTANT_P (tem)) |
4702 | { | |
4703 | tem = force_const_mem (GET_MODE (x), tem); | |
4704 | i = find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), | |
4705 | &XEXP (tem, 0), opnum, type, | |
4706 | ind_levels, insn); | |
4707 | if (address_reloaded) | |
4708 | *address_reloaded = i; | |
4709 | } | |
4119019b | 4710 | return tem; |
0365438d | 4711 | } |
eab89b90 | 4712 | |
eab89b90 RK |
4713 | /* If the subreg contains a reg that will be converted to a mem, |
4714 | convert the subreg to a narrower memref now. | |
4715 | Otherwise, we would get (subreg (mem ...) ...), | |
4716 | which would force reload of the mem. | |
4717 | ||
4718 | We also need to do this if there is an equivalent MEM that is | |
4719 | not offsettable. In that case, alter_subreg would produce an | |
4720 | invalid address on big-endian machines. | |
4721 | ||
46da6b3a | 4722 | For machines that extend byte loads, we must not reload using |
eab89b90 RK |
4723 | a wider mode if we have a paradoxical SUBREG. find_reloads will |
4724 | force a reload in that case. So we should not do anything here. */ | |
4725 | ||
857e5753 | 4726 | if (regno >= FIRST_PSEUDO_REGISTER |
fd72420f | 4727 | #ifdef LOAD_EXTEND_OP |
eab89b90 RK |
4728 | && (GET_MODE_SIZE (GET_MODE (x)) |
4729 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
4730 | #endif | |
4731 | && (reg_equiv_address[regno] != 0 | |
4732 | || (reg_equiv_mem[regno] != 0 | |
05d10675 | 4733 | && (! strict_memory_address_p (GET_MODE (x), |
f2fbfe92 | 4734 | XEXP (reg_equiv_mem[regno], 0)) |
cb2afeb3 R |
4735 | || ! offsettable_memref_p (reg_equiv_mem[regno]) |
4736 | || num_not_at_initial_offset)))) | |
22505ad8 R |
4737 | x = find_reloads_subreg_address (x, 1, opnum, type, ind_levels, |
4738 | insn); | |
eab89b90 RK |
4739 | } |
4740 | ||
9f4749b1 | 4741 | for (copied = 0, i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
eab89b90 RK |
4742 | { |
4743 | if (fmt[i] == 'e') | |
9f4749b1 R |
4744 | { |
4745 | rtx new_part = find_reloads_toplev (XEXP (x, i), opnum, type, | |
9246aadb AH |
4746 | ind_levels, is_set_dest, insn, |
4747 | address_reloaded); | |
9f4749b1 R |
4748 | /* If we have replaced a reg with it's equivalent memory loc - |
4749 | that can still be handled here e.g. if it's in a paradoxical | |
4750 | subreg - we must make the change in a copy, rather than using | |
4751 | a destructive change. This way, find_reloads can still elect | |
4752 | not to do the change. */ | |
4753 | if (new_part != XEXP (x, i) && ! CONSTANT_P (new_part) && ! copied) | |
4754 | { | |
ce9d4c6d | 4755 | x = shallow_copy_rtx (x); |
9f4749b1 R |
4756 | copied = 1; |
4757 | } | |
4758 | XEXP (x, i) = new_part; | |
4759 | } | |
eab89b90 RK |
4760 | } |
4761 | return x; | |
4762 | } | |
4763 | ||
dbf85761 RS |
4764 | /* Return a mem ref for the memory equivalent of reg REGNO. |
4765 | This mem ref is not shared with anything. */ | |
4766 | ||
eab89b90 | 4767 | static rtx |
0c20a65f | 4768 | make_memloc (rtx ad, int regno) |
eab89b90 | 4769 | { |
4ffeab02 JW |
4770 | /* We must rerun eliminate_regs, in case the elimination |
4771 | offsets have changed. */ | |
cb2afeb3 | 4772 | rtx tem |
bbbbb16a ILT |
4773 | = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], VOIDmode, NULL_RTX), |
4774 | 0); | |
eab89b90 RK |
4775 | |
4776 | /* If TEM might contain a pseudo, we must copy it to avoid | |
4777 | modifying it when we do the substitution for the reload. */ | |
e38fe8e0 | 4778 | if (rtx_varies_p (tem, 0)) |
eab89b90 RK |
4779 | tem = copy_rtx (tem); |
4780 | ||
f1ec5147 | 4781 | tem = replace_equiv_address_nv (reg_equiv_memory_loc[regno], tem); |
cf728d61 HPN |
4782 | tem = adjust_address_nv (tem, GET_MODE (ad), 0); |
4783 | ||
4784 | /* Copy the result if it's still the same as the equivalence, to avoid | |
4785 | modifying it when we do the substitution for the reload. */ | |
4786 | if (tem == reg_equiv_memory_loc[regno]) | |
4787 | tem = copy_rtx (tem); | |
4788 | return tem; | |
eab89b90 RK |
4789 | } |
4790 | ||
acf9fa5f | 4791 | /* Returns true if AD could be turned into a valid memory reference |
0c20a65f | 4792 | to mode MODE by reloading the part pointed to by PART into a |
acf9fa5f UW |
4793 | register. */ |
4794 | ||
4795 | static int | |
0c20a65f | 4796 | maybe_memory_address_p (enum machine_mode mode, rtx ad, rtx *part) |
acf9fa5f UW |
4797 | { |
4798 | int retv; | |
4799 | rtx tem = *part; | |
4800 | rtx reg = gen_rtx_REG (GET_MODE (tem), max_reg_num ()); | |
4801 | ||
4802 | *part = reg; | |
4803 | retv = memory_address_p (mode, ad); | |
4804 | *part = tem; | |
4805 | ||
4806 | return retv; | |
4807 | } | |
4808 | ||
eab89b90 RK |
4809 | /* Record all reloads needed for handling memory address AD |
4810 | which appears in *LOC in a memory reference to mode MODE | |
4811 | which itself is found in location *MEMREFLOC. | |
4812 | Note that we take shortcuts assuming that no multi-reg machine mode | |
4813 | occurs as part of an address. | |
4814 | ||
a8c9daeb | 4815 | OPNUM and TYPE specify the purpose of this reload. |
eab89b90 RK |
4816 | |
4817 | IND_LEVELS says how many levels of indirect addressing this machine | |
4818 | supports. | |
4819 | ||
55c22565 | 4820 | INSN, if nonzero, is the insn in which we do the reload. It is used |
cb2afeb3 R |
4821 | to determine if we may generate output reloads, and where to put USEs |
4822 | for pseudos that we have to replace with stack slots. | |
55c22565 | 4823 | |
0b540f12 UW |
4824 | Value is one if this address is reloaded or replaced as a whole; it is |
4825 | zero if the top level of this address was not reloaded or replaced, and | |
4826 | it is -1 if it may or may not have been reloaded or replaced. | |
eab89b90 RK |
4827 | |
4828 | Note that there is no verification that the address will be valid after | |
4829 | this routine does its work. Instead, we rely on the fact that the address | |
4830 | was valid when reload started. So we need only undo things that reload | |
4831 | could have broken. These are wrong register types, pseudos not allocated | |
4832 | to a hard register, and frame pointer elimination. */ | |
4833 | ||
4834 | static int | |
0c20a65f AJ |
4835 | find_reloads_address (enum machine_mode mode, rtx *memrefloc, rtx ad, |
4836 | rtx *loc, int opnum, enum reload_type type, | |
4837 | int ind_levels, rtx insn) | |
eab89b90 | 4838 | { |
b3694847 | 4839 | int regno; |
ab87f8c8 | 4840 | int removed_and = 0; |
14d3dc34 | 4841 | int op_index; |
eab89b90 RK |
4842 | rtx tem; |
4843 | ||
4844 | /* If the address is a register, see if it is a legitimate address and | |
4845 | reload if not. We first handle the cases where we need not reload | |
4846 | or where we must reload in a non-standard way. */ | |
4847 | ||
f8cfc6aa | 4848 | if (REG_P (ad)) |
eab89b90 RK |
4849 | { |
4850 | regno = REGNO (ad); | |
4851 | ||
90d12f1f | 4852 | if (reg_equiv_constant[regno] != 0) |
eab89b90 | 4853 | { |
90d12f1f AK |
4854 | find_reloads_address_part (reg_equiv_constant[regno], loc, |
4855 | base_reg_class (mode, MEM, SCRATCH), | |
4856 | GET_MODE (ad), opnum, type, ind_levels); | |
4857 | return 1; | |
eab89b90 RK |
4858 | } |
4859 | ||
cb2afeb3 R |
4860 | tem = reg_equiv_memory_loc[regno]; |
4861 | if (tem != 0) | |
eab89b90 | 4862 | { |
cb2afeb3 R |
4863 | if (reg_equiv_address[regno] != 0 || num_not_at_initial_offset) |
4864 | { | |
4865 | tem = make_memloc (ad, regno); | |
4866 | if (! strict_memory_address_p (GET_MODE (tem), XEXP (tem, 0))) | |
4867 | { | |
3f1e3e70 AO |
4868 | rtx orig = tem; |
4869 | ||
57292ec3 AL |
4870 | find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), |
4871 | &XEXP (tem, 0), opnum, | |
4872 | ADDR_TYPE (type), ind_levels, insn); | |
0f4b25a3 | 4873 | if (!rtx_equal_p (tem, orig)) |
3f1e3e70 | 4874 | push_reg_equiv_alt_mem (regno, tem); |
cb2afeb3 R |
4875 | } |
4876 | /* We can avoid a reload if the register's equivalent memory | |
4877 | expression is valid as an indirect memory address. | |
4878 | But not all addresses are valid in a mem used as an indirect | |
4879 | address: only reg or reg+constant. */ | |
4880 | ||
4881 | if (ind_levels > 0 | |
4882 | && strict_memory_address_p (mode, tem) | |
f8cfc6aa | 4883 | && (REG_P (XEXP (tem, 0)) |
cb2afeb3 | 4884 | || (GET_CODE (XEXP (tem, 0)) == PLUS |
f8cfc6aa | 4885 | && REG_P (XEXP (XEXP (tem, 0), 0)) |
cb2afeb3 R |
4886 | && CONSTANT_P (XEXP (XEXP (tem, 0), 1))))) |
4887 | { | |
4888 | /* TEM is not the same as what we'll be replacing the | |
4889 | pseudo with after reload, put a USE in front of INSN | |
4890 | in the final reload pass. */ | |
4891 | if (replace_reloads | |
4892 | && num_not_at_initial_offset | |
4893 | && ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
4894 | { | |
4895 | *loc = tem; | |
3d17d93d AO |
4896 | /* We mark the USE with QImode so that we |
4897 | recognize it as one that can be safely | |
4898 | deleted at the end of reload. */ | |
4899 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, ad), | |
4900 | insn), QImode); | |
4901 | ||
cb2afeb3 R |
4902 | /* This doesn't really count as replacing the address |
4903 | as a whole, since it is still a memory access. */ | |
4904 | } | |
4905 | return 0; | |
4906 | } | |
4907 | ad = tem; | |
4908 | } | |
eab89b90 RK |
4909 | } |
4910 | ||
eab89b90 RK |
4911 | /* The only remaining case where we can avoid a reload is if this is a |
4912 | hard register that is valid as a base register and which is not the | |
4913 | subject of a CLOBBER in this insn. */ | |
4914 | ||
858c3c8c | 4915 | else if (regno < FIRST_PSEUDO_REGISTER |
c4963a0a | 4916 | && regno_ok_for_base_p (regno, mode, MEM, SCRATCH) |
9532e31f | 4917 | && ! regno_clobbered_p (regno, this_insn, mode, 0)) |
eab89b90 RK |
4918 | return 0; |
4919 | ||
4920 | /* If we do not have one of the cases above, we must do the reload. */ | |
c4963a0a | 4921 | push_reload (ad, NULL_RTX, loc, (rtx*) 0, base_reg_class (mode, MEM, SCRATCH), |
a8c9daeb | 4922 | GET_MODE (ad), VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
4923 | return 1; |
4924 | } | |
4925 | ||
4926 | if (strict_memory_address_p (mode, ad)) | |
4927 | { | |
4928 | /* The address appears valid, so reloads are not needed. | |
4929 | But the address may contain an eliminable register. | |
4930 | This can happen because a machine with indirect addressing | |
4931 | may consider a pseudo register by itself a valid address even when | |
4932 | it has failed to get a hard reg. | |
4933 | So do a tree-walk to find and eliminate all such regs. */ | |
4934 | ||
4935 | /* But first quickly dispose of a common case. */ | |
4936 | if (GET_CODE (ad) == PLUS | |
481683e1 | 4937 | && CONST_INT_P (XEXP (ad, 1)) |
f8cfc6aa | 4938 | && REG_P (XEXP (ad, 0)) |
eab89b90 RK |
4939 | && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0) |
4940 | return 0; | |
4941 | ||
4942 | subst_reg_equivs_changed = 0; | |
cb2afeb3 | 4943 | *loc = subst_reg_equivs (ad, insn); |
eab89b90 RK |
4944 | |
4945 | if (! subst_reg_equivs_changed) | |
4946 | return 0; | |
4947 | ||
4948 | /* Check result for validity after substitution. */ | |
4949 | if (strict_memory_address_p (mode, ad)) | |
4950 | return 0; | |
4951 | } | |
4952 | ||
a9a2595b JR |
4953 | #ifdef LEGITIMIZE_RELOAD_ADDRESS |
4954 | do | |
4955 | { | |
4956 | if (memrefloc) | |
4957 | { | |
4958 | LEGITIMIZE_RELOAD_ADDRESS (ad, GET_MODE (*memrefloc), opnum, type, | |
4959 | ind_levels, win); | |
4960 | } | |
4961 | break; | |
4962 | win: | |
4963 | *memrefloc = copy_rtx (*memrefloc); | |
4964 | XEXP (*memrefloc, 0) = ad; | |
4965 | move_replacements (&ad, &XEXP (*memrefloc, 0)); | |
0b540f12 | 4966 | return -1; |
a9a2595b JR |
4967 | } |
4968 | while (0); | |
4969 | #endif | |
4970 | ||
ab87f8c8 JL |
4971 | /* The address is not valid. We have to figure out why. First see if |
4972 | we have an outer AND and remove it if so. Then analyze what's inside. */ | |
4973 | ||
4974 | if (GET_CODE (ad) == AND) | |
4975 | { | |
4976 | removed_and = 1; | |
4977 | loc = &XEXP (ad, 0); | |
4978 | ad = *loc; | |
4979 | } | |
4980 | ||
4981 | /* One possibility for why the address is invalid is that it is itself | |
4982 | a MEM. This can happen when the frame pointer is being eliminated, a | |
4983 | pseudo is not allocated to a hard register, and the offset between the | |
4984 | frame and stack pointers is not its initial value. In that case the | |
4985 | pseudo will have been replaced by a MEM referring to the | |
4986 | stack pointer. */ | |
3c0cb5de | 4987 | if (MEM_P (ad)) |
eab89b90 RK |
4988 | { |
4989 | /* First ensure that the address in this MEM is valid. Then, unless | |
4990 | indirect addresses are valid, reload the MEM into a register. */ | |
4991 | tem = ad; | |
4992 | find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0), | |
47c8cf91 | 4993 | opnum, ADDR_TYPE (type), |
55c22565 | 4994 | ind_levels == 0 ? 0 : ind_levels - 1, insn); |
d2555454 RS |
4995 | |
4996 | /* If tem was changed, then we must create a new memory reference to | |
4997 | hold it and store it back into memrefloc. */ | |
4998 | if (tem != ad && memrefloc) | |
ca3e4a2f | 4999 | { |
ca3e4a2f | 5000 | *memrefloc = copy_rtx (*memrefloc); |
3c80f7ed | 5001 | copy_replacements (tem, XEXP (*memrefloc, 0)); |
ca3e4a2f | 5002 | loc = &XEXP (*memrefloc, 0); |
ab87f8c8 JL |
5003 | if (removed_and) |
5004 | loc = &XEXP (*loc, 0); | |
ca3e4a2f | 5005 | } |
d2555454 | 5006 | |
eab89b90 RK |
5007 | /* Check similar cases as for indirect addresses as above except |
5008 | that we can allow pseudos and a MEM since they should have been | |
5009 | taken care of above. */ | |
5010 | ||
5011 | if (ind_levels == 0 | |
5012 | || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok) | |
3c0cb5de | 5013 | || MEM_P (XEXP (tem, 0)) |
f8cfc6aa | 5014 | || ! (REG_P (XEXP (tem, 0)) |
eab89b90 | 5015 | || (GET_CODE (XEXP (tem, 0)) == PLUS |
f8cfc6aa | 5016 | && REG_P (XEXP (XEXP (tem, 0), 0)) |
481683e1 | 5017 | && CONST_INT_P (XEXP (XEXP (tem, 0), 1))))) |
eab89b90 RK |
5018 | { |
5019 | /* Must use TEM here, not AD, since it is the one that will | |
5020 | have any subexpressions reloaded, if needed. */ | |
f4f4d0f8 | 5021 | push_reload (tem, NULL_RTX, loc, (rtx*) 0, |
c4963a0a | 5022 | base_reg_class (mode, MEM, SCRATCH), GET_MODE (tem), |
1ba61f4e | 5023 | VOIDmode, 0, |
a8c9daeb | 5024 | 0, opnum, type); |
ab87f8c8 | 5025 | return ! removed_and; |
eab89b90 RK |
5026 | } |
5027 | else | |
5028 | return 0; | |
5029 | } | |
5030 | ||
1b4d2764 RK |
5031 | /* If we have address of a stack slot but it's not valid because the |
5032 | displacement is too large, compute the sum in a register. | |
5033 | Handle all base registers here, not just fp/ap/sp, because on some | |
5034 | targets (namely SH) we can also get too large displacements from | |
5035 | big-endian corrections. */ | |
eab89b90 | 5036 | else if (GET_CODE (ad) == PLUS |
f8cfc6aa | 5037 | && REG_P (XEXP (ad, 0)) |
1b4d2764 | 5038 | && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER |
481683e1 | 5039 | && CONST_INT_P (XEXP (ad, 1)) |
c4963a0a BS |
5040 | && regno_ok_for_base_p (REGNO (XEXP (ad, 0)), mode, PLUS, |
5041 | CONST_INT)) | |
5042 | ||
eab89b90 RK |
5043 | { |
5044 | /* Unshare the MEM rtx so we can safely alter it. */ | |
5045 | if (memrefloc) | |
5046 | { | |
eab89b90 RK |
5047 | *memrefloc = copy_rtx (*memrefloc); |
5048 | loc = &XEXP (*memrefloc, 0); | |
ab87f8c8 JL |
5049 | if (removed_and) |
5050 | loc = &XEXP (*loc, 0); | |
eab89b90 | 5051 | } |
ab87f8c8 | 5052 | |
eab89b90 RK |
5053 | if (double_reg_address_ok) |
5054 | { | |
5055 | /* Unshare the sum as well. */ | |
5056 | *loc = ad = copy_rtx (ad); | |
ab87f8c8 | 5057 | |
eab89b90 RK |
5058 | /* Reload the displacement into an index reg. |
5059 | We assume the frame pointer or arg pointer is a base reg. */ | |
5060 | find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), | |
03acd8f8 BS |
5061 | INDEX_REG_CLASS, GET_MODE (ad), opnum, |
5062 | type, ind_levels); | |
ab87f8c8 | 5063 | return 0; |
eab89b90 RK |
5064 | } |
5065 | else | |
5066 | { | |
5067 | /* If the sum of two regs is not necessarily valid, | |
5068 | reload the sum into a base reg. | |
5069 | That will at least work. */ | |
c4963a0a BS |
5070 | find_reloads_address_part (ad, loc, |
5071 | base_reg_class (mode, MEM, SCRATCH), | |
1ba61f4e | 5072 | Pmode, opnum, type, ind_levels); |
eab89b90 | 5073 | } |
ab87f8c8 | 5074 | return ! removed_and; |
eab89b90 RK |
5075 | } |
5076 | ||
5077 | /* If we have an indexed stack slot, there are three possible reasons why | |
5078 | it might be invalid: The index might need to be reloaded, the address | |
5079 | might have been made by frame pointer elimination and hence have a | |
05d10675 | 5080 | constant out of range, or both reasons might apply. |
eab89b90 RK |
5081 | |
5082 | We can easily check for an index needing reload, but even if that is the | |
5083 | case, we might also have an invalid constant. To avoid making the | |
5084 | conservative assumption and requiring two reloads, we see if this address | |
5085 | is valid when not interpreted strictly. If it is, the only problem is | |
5086 | that the index needs a reload and find_reloads_address_1 will take care | |
5087 | of it. | |
5088 | ||
27e484bc | 5089 | Handle all base registers here, not just fp/ap/sp, because on some |
6356f892 | 5090 | targets (namely SPARC) we can also get invalid addresses from preventive |
14d3dc34 MM |
5091 | subreg big-endian corrections made by find_reloads_toplev. We |
5092 | can also get expressions involving LO_SUM (rather than PLUS) from | |
5093 | find_reloads_subreg_address. | |
27e484bc EB |
5094 | |
5095 | If we decide to do something, it must be that `double_reg_address_ok' | |
5096 | is true. We generate a reload of the base register + constant and | |
eab89b90 RK |
5097 | rework the sum so that the reload register will be added to the index. |
5098 | This is safe because we know the address isn't shared. | |
5099 | ||
27e484bc | 5100 | We check for the base register as both the first and second operand of |
14d3dc34 MM |
5101 | the innermost PLUS and/or LO_SUM. */ |
5102 | ||
5103 | for (op_index = 0; op_index < 2; ++op_index) | |
eab89b90 | 5104 | { |
c4963a0a BS |
5105 | rtx operand, addend; |
5106 | enum rtx_code inner_code; | |
5107 | ||
5108 | if (GET_CODE (ad) != PLUS) | |
5109 | continue; | |
eab89b90 | 5110 | |
c4963a0a | 5111 | inner_code = GET_CODE (XEXP (ad, 0)); |
14d3dc34 | 5112 | if (!(GET_CODE (ad) == PLUS |
481683e1 | 5113 | && CONST_INT_P (XEXP (ad, 1)) |
c4963a0a | 5114 | && (inner_code == PLUS || inner_code == LO_SUM))) |
14d3dc34 | 5115 | continue; |
05d10675 | 5116 | |
14d3dc34 | 5117 | operand = XEXP (XEXP (ad, 0), op_index); |
0e544c37 | 5118 | if (!REG_P (operand) || REGNO (operand) >= FIRST_PSEUDO_REGISTER) |
14d3dc34 MM |
5119 | continue; |
5120 | ||
c4963a0a BS |
5121 | addend = XEXP (XEXP (ad, 0), 1 - op_index); |
5122 | ||
5123 | if ((regno_ok_for_base_p (REGNO (operand), mode, inner_code, | |
5124 | GET_CODE (addend)) | |
14d3dc34 | 5125 | || operand == frame_pointer_rtx |
0422e940 | 5126 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM |
14d3dc34 | 5127 | || operand == hard_frame_pointer_rtx |
0422e940 UW |
5128 | #endif |
5129 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
14d3dc34 | 5130 | || operand == arg_pointer_rtx |
0422e940 | 5131 | #endif |
14d3dc34 MM |
5132 | || operand == stack_pointer_rtx) |
5133 | && ! maybe_memory_address_p (mode, ad, | |
7bb09d15 | 5134 | &XEXP (XEXP (ad, 0), 1 - op_index))) |
14d3dc34 MM |
5135 | { |
5136 | rtx offset_reg; | |
c4963a0a | 5137 | enum reg_class cls; |
14d3dc34 MM |
5138 | |
5139 | offset_reg = plus_constant (operand, INTVAL (XEXP (ad, 1))); | |
c4963a0a | 5140 | |
14d3dc34 MM |
5141 | /* Form the adjusted address. */ |
5142 | if (GET_CODE (XEXP (ad, 0)) == PLUS) | |
5143 | ad = gen_rtx_PLUS (GET_MODE (ad), | |
5144 | op_index == 0 ? offset_reg : addend, | |
5145 | op_index == 0 ? addend : offset_reg); | |
5146 | else | |
5147 | ad = gen_rtx_LO_SUM (GET_MODE (ad), | |
5148 | op_index == 0 ? offset_reg : addend, | |
5149 | op_index == 0 ? addend : offset_reg); | |
5150 | *loc = ad; | |
5151 | ||
c4963a0a | 5152 | cls = base_reg_class (mode, MEM, GET_CODE (addend)); |
14d3dc34 | 5153 | find_reloads_address_part (XEXP (ad, op_index), |
c4963a0a | 5154 | &XEXP (ad, op_index), cls, |
14d3dc34 | 5155 | GET_MODE (ad), opnum, type, ind_levels); |
c4963a0a BS |
5156 | find_reloads_address_1 (mode, |
5157 | XEXP (ad, 1 - op_index), 1, GET_CODE (ad), | |
5158 | GET_CODE (XEXP (ad, op_index)), | |
14d3dc34 MM |
5159 | &XEXP (ad, 1 - op_index), opnum, |
5160 | type, 0, insn); | |
eab89b90 | 5161 | |
14d3dc34 MM |
5162 | return 0; |
5163 | } | |
eab89b90 | 5164 | } |
05d10675 | 5165 | |
eab89b90 RK |
5166 | /* See if address becomes valid when an eliminable register |
5167 | in a sum is replaced. */ | |
5168 | ||
5169 | tem = ad; | |
5170 | if (GET_CODE (ad) == PLUS) | |
5171 | tem = subst_indexed_address (ad); | |
5172 | if (tem != ad && strict_memory_address_p (mode, tem)) | |
5173 | { | |
5174 | /* Ok, we win that way. Replace any additional eliminable | |
5175 | registers. */ | |
5176 | ||
5177 | subst_reg_equivs_changed = 0; | |
cb2afeb3 | 5178 | tem = subst_reg_equivs (tem, insn); |
eab89b90 RK |
5179 | |
5180 | /* Make sure that didn't make the address invalid again. */ | |
5181 | ||
5182 | if (! subst_reg_equivs_changed || strict_memory_address_p (mode, tem)) | |
5183 | { | |
5184 | *loc = tem; | |
5185 | return 0; | |
5186 | } | |
5187 | } | |
5188 | ||
5189 | /* If constants aren't valid addresses, reload the constant address | |
5190 | into a register. */ | |
191b18e9 | 5191 | if (CONSTANT_P (ad) && ! strict_memory_address_p (mode, ad)) |
eab89b90 | 5192 | { |
e0120d6e | 5193 | /* If AD is an address in the constant pool, the MEM rtx may be shared. |
eab89b90 RK |
5194 | Unshare it so we can safely alter it. */ |
5195 | if (memrefloc && GET_CODE (ad) == SYMBOL_REF | |
5196 | && CONSTANT_POOL_ADDRESS_P (ad)) | |
5197 | { | |
eab89b90 RK |
5198 | *memrefloc = copy_rtx (*memrefloc); |
5199 | loc = &XEXP (*memrefloc, 0); | |
ab87f8c8 JL |
5200 | if (removed_and) |
5201 | loc = &XEXP (*loc, 0); | |
eab89b90 RK |
5202 | } |
5203 | ||
c4963a0a | 5204 | find_reloads_address_part (ad, loc, base_reg_class (mode, MEM, SCRATCH), |
3dcc68a4 | 5205 | Pmode, opnum, type, ind_levels); |
ab87f8c8 | 5206 | return ! removed_and; |
eab89b90 RK |
5207 | } |
5208 | ||
c4963a0a BS |
5209 | return find_reloads_address_1 (mode, ad, 0, MEM, SCRATCH, loc, opnum, type, |
5210 | ind_levels, insn); | |
eab89b90 RK |
5211 | } |
5212 | \f | |
5213 | /* Find all pseudo regs appearing in AD | |
5214 | that are eliminable in favor of equivalent values | |
cb2afeb3 R |
5215 | and do not have hard regs; replace them by their equivalents. |
5216 | INSN, if nonzero, is the insn in which we do the reload. We put USEs in | |
5217 | front of it for pseudos that we have to replace with stack slots. */ | |
eab89b90 RK |
5218 | |
5219 | static rtx | |
0c20a65f | 5220 | subst_reg_equivs (rtx ad, rtx insn) |
eab89b90 | 5221 | { |
b3694847 SS |
5222 | RTX_CODE code = GET_CODE (ad); |
5223 | int i; | |
5224 | const char *fmt; | |
eab89b90 RK |
5225 | |
5226 | switch (code) | |
5227 | { | |
5228 | case HIGH: | |
5229 | case CONST_INT: | |
5230 | case CONST: | |
5231 | case CONST_DOUBLE: | |
091a3ac7 | 5232 | case CONST_FIXED: |
69ef87e2 | 5233 | case CONST_VECTOR: |
eab89b90 RK |
5234 | case SYMBOL_REF: |
5235 | case LABEL_REF: | |
5236 | case PC: | |
5237 | case CC0: | |
5238 | return ad; | |
5239 | ||
5240 | case REG: | |
5241 | { | |
b3694847 | 5242 | int regno = REGNO (ad); |
eab89b90 RK |
5243 | |
5244 | if (reg_equiv_constant[regno] != 0) | |
5245 | { | |
5246 | subst_reg_equivs_changed = 1; | |
5247 | return reg_equiv_constant[regno]; | |
5248 | } | |
cb2afeb3 R |
5249 | if (reg_equiv_memory_loc[regno] && num_not_at_initial_offset) |
5250 | { | |
5251 | rtx mem = make_memloc (ad, regno); | |
5252 | if (! rtx_equal_p (mem, reg_equiv_mem[regno])) | |
5253 | { | |
5254 | subst_reg_equivs_changed = 1; | |
3d17d93d AO |
5255 | /* We mark the USE with QImode so that we recognize it |
5256 | as one that can be safely deleted at the end of | |
5257 | reload. */ | |
5258 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, ad), insn), | |
5259 | QImode); | |
cb2afeb3 R |
5260 | return mem; |
5261 | } | |
5262 | } | |
eab89b90 RK |
5263 | } |
5264 | return ad; | |
5265 | ||
5266 | case PLUS: | |
5267 | /* Quickly dispose of a common case. */ | |
5268 | if (XEXP (ad, 0) == frame_pointer_rtx | |
481683e1 | 5269 | && CONST_INT_P (XEXP (ad, 1))) |
eab89b90 | 5270 | return ad; |
e9a25f70 | 5271 | break; |
05d10675 | 5272 | |
e9a25f70 JL |
5273 | default: |
5274 | break; | |
eab89b90 RK |
5275 | } |
5276 | ||
5277 | fmt = GET_RTX_FORMAT (code); | |
5278 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5279 | if (fmt[i] == 'e') | |
cb2afeb3 | 5280 | XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i), insn); |
eab89b90 RK |
5281 | return ad; |
5282 | } | |
5283 | \f | |
5284 | /* Compute the sum of X and Y, making canonicalizations assumed in an | |
5285 | address, namely: sum constant integers, surround the sum of two | |
5286 | constants with a CONST, put the constant as the second operand, and | |
5287 | group the constant on the outermost sum. | |
5288 | ||
5289 | This routine assumes both inputs are already in canonical form. */ | |
5290 | ||
5291 | rtx | |
0c20a65f | 5292 | form_sum (rtx x, rtx y) |
eab89b90 RK |
5293 | { |
5294 | rtx tem; | |
2c0623e8 RK |
5295 | enum machine_mode mode = GET_MODE (x); |
5296 | ||
5297 | if (mode == VOIDmode) | |
5298 | mode = GET_MODE (y); | |
5299 | ||
5300 | if (mode == VOIDmode) | |
5301 | mode = Pmode; | |
eab89b90 | 5302 | |
481683e1 | 5303 | if (CONST_INT_P (x)) |
eab89b90 | 5304 | return plus_constant (y, INTVAL (x)); |
481683e1 | 5305 | else if (CONST_INT_P (y)) |
eab89b90 RK |
5306 | return plus_constant (x, INTVAL (y)); |
5307 | else if (CONSTANT_P (x)) | |
5308 | tem = x, x = y, y = tem; | |
5309 | ||
5310 | if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1))) | |
5311 | return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y)); | |
5312 | ||
5313 | /* Note that if the operands of Y are specified in the opposite | |
5314 | order in the recursive calls below, infinite recursion will occur. */ | |
d9771f62 | 5315 | if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1))) |
eab89b90 RK |
5316 | return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1)); |
5317 | ||
5318 | /* If both constant, encapsulate sum. Otherwise, just form sum. A | |
5319 | constant will have been placed second. */ | |
5320 | if (CONSTANT_P (x) && CONSTANT_P (y)) | |
5321 | { | |
5322 | if (GET_CODE (x) == CONST) | |
5323 | x = XEXP (x, 0); | |
5324 | if (GET_CODE (y) == CONST) | |
5325 | y = XEXP (y, 0); | |
5326 | ||
38a448ca | 5327 | return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y)); |
eab89b90 RK |
5328 | } |
5329 | ||
38a448ca | 5330 | return gen_rtx_PLUS (mode, x, y); |
eab89b90 RK |
5331 | } |
5332 | \f | |
5333 | /* If ADDR is a sum containing a pseudo register that should be | |
5334 | replaced with a constant (from reg_equiv_constant), | |
5335 | return the result of doing so, and also apply the associative | |
5336 | law so that the result is more likely to be a valid address. | |
5337 | (But it is not guaranteed to be one.) | |
5338 | ||
5339 | Note that at most one register is replaced, even if more are | |
5340 | replaceable. Also, we try to put the result into a canonical form | |
5341 | so it is more likely to be a valid address. | |
5342 | ||
5343 | In all other cases, return ADDR. */ | |
5344 | ||
5345 | static rtx | |
0c20a65f | 5346 | subst_indexed_address (rtx addr) |
eab89b90 RK |
5347 | { |
5348 | rtx op0 = 0, op1 = 0, op2 = 0; | |
5349 | rtx tem; | |
5350 | int regno; | |
5351 | ||
5352 | if (GET_CODE (addr) == PLUS) | |
5353 | { | |
5354 | /* Try to find a register to replace. */ | |
5355 | op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0; | |
f8cfc6aa | 5356 | if (REG_P (op0) |
eab89b90 RK |
5357 | && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER |
5358 | && reg_renumber[regno] < 0 | |
5359 | && reg_equiv_constant[regno] != 0) | |
5360 | op0 = reg_equiv_constant[regno]; | |
f8cfc6aa | 5361 | else if (REG_P (op1) |
05d10675 BS |
5362 | && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER |
5363 | && reg_renumber[regno] < 0 | |
5364 | && reg_equiv_constant[regno] != 0) | |
eab89b90 RK |
5365 | op1 = reg_equiv_constant[regno]; |
5366 | else if (GET_CODE (op0) == PLUS | |
5367 | && (tem = subst_indexed_address (op0)) != op0) | |
5368 | op0 = tem; | |
5369 | else if (GET_CODE (op1) == PLUS | |
5370 | && (tem = subst_indexed_address (op1)) != op1) | |
5371 | op1 = tem; | |
5372 | else | |
5373 | return addr; | |
5374 | ||
5375 | /* Pick out up to three things to add. */ | |
5376 | if (GET_CODE (op1) == PLUS) | |
5377 | op2 = XEXP (op1, 1), op1 = XEXP (op1, 0); | |
5378 | else if (GET_CODE (op0) == PLUS) | |
5379 | op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
5380 | ||
5381 | /* Compute the sum. */ | |
5382 | if (op2 != 0) | |
5383 | op1 = form_sum (op1, op2); | |
5384 | if (op1 != 0) | |
5385 | op0 = form_sum (op0, op1); | |
5386 | ||
5387 | return op0; | |
5388 | } | |
5389 | return addr; | |
5390 | } | |
5391 | \f | |
98c17df2 GS |
5392 | /* Update the REG_INC notes for an insn. It updates all REG_INC |
5393 | notes for the instruction which refer to REGNO the to refer | |
5394 | to the reload number. | |
5395 | ||
5396 | INSN is the insn for which any REG_INC notes need updating. | |
5397 | ||
5398 | REGNO is the register number which has been reloaded. | |
5399 | ||
5400 | RELOADNUM is the reload number. */ | |
5401 | ||
5402 | static void | |
0c20a65f AJ |
5403 | update_auto_inc_notes (rtx insn ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED, |
5404 | int reloadnum ATTRIBUTE_UNUSED) | |
98c17df2 GS |
5405 | { |
5406 | #ifdef AUTO_INC_DEC | |
5407 | rtx link; | |
5408 | ||
5409 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
5410 | if (REG_NOTE_KIND (link) == REG_INC | |
fc555370 | 5411 | && (int) REGNO (XEXP (link, 0)) == regno) |
98c17df2 GS |
5412 | push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); |
5413 | #endif | |
5414 | } | |
5415 | \f | |
858c3c8c ILT |
5416 | /* Record the pseudo registers we must reload into hard registers in a |
5417 | subexpression of a would-be memory address, X referring to a value | |
5418 | in mode MODE. (This function is not called if the address we find | |
5419 | is strictly valid.) | |
5420 | ||
eab89b90 | 5421 | CONTEXT = 1 means we are considering regs as index regs, |
c4963a0a BS |
5422 | = 0 means we are considering them as base regs. |
5423 | OUTER_CODE is the code of the enclosing RTX, typically a MEM, a PLUS, | |
5424 | or an autoinc code. | |
5425 | If CONTEXT == 0 and OUTER_CODE is a PLUS or LO_SUM, then INDEX_CODE | |
5426 | is the code of the index part of the address. Otherwise, pass SCRATCH | |
5427 | for this argument. | |
a8c9daeb | 5428 | OPNUM and TYPE specify the purpose of any reloads made. |
eab89b90 RK |
5429 | |
5430 | IND_LEVELS says how many levels of indirect addressing are | |
5431 | supported at this point in the address. | |
5432 | ||
55c22565 RK |
5433 | INSN, if nonzero, is the insn in which we do the reload. It is used |
5434 | to determine if we may generate output reloads. | |
5435 | ||
eab89b90 RK |
5436 | We return nonzero if X, as a whole, is reloaded or replaced. */ |
5437 | ||
5438 | /* Note that we take shortcuts assuming that no multi-reg machine mode | |
5439 | occurs as part of an address. | |
5440 | Also, this is not fully machine-customizable; it works for machines | |
8aeea6e6 | 5441 | such as VAXen and 68000's and 32000's, but other possible machines |
ff0d9879 HPN |
5442 | could have addressing modes that this does not handle right. |
5443 | If you add push_reload calls here, you need to make sure gen_reload | |
5444 | handles those cases gracefully. */ | |
eab89b90 RK |
5445 | |
5446 | static int | |
0c20a65f | 5447 | find_reloads_address_1 (enum machine_mode mode, rtx x, int context, |
c4963a0a | 5448 | enum rtx_code outer_code, enum rtx_code index_code, |
0c20a65f AJ |
5449 | rtx *loc, int opnum, enum reload_type type, |
5450 | int ind_levels, rtx insn) | |
eab89b90 | 5451 | { |
c4963a0a BS |
5452 | #define REG_OK_FOR_CONTEXT(CONTEXT, REGNO, MODE, OUTER, INDEX) \ |
5453 | ((CONTEXT) == 0 \ | |
5454 | ? regno_ok_for_base_p (REGNO, MODE, OUTER, INDEX) \ | |
5455 | : REGNO_OK_FOR_INDEX_P (REGNO)) | |
888d2cd6 DJ |
5456 | |
5457 | enum reg_class context_reg_class; | |
b3694847 | 5458 | RTX_CODE code = GET_CODE (x); |
eab89b90 | 5459 | |
c4963a0a | 5460 | if (context == 1) |
888d2cd6 DJ |
5461 | context_reg_class = INDEX_REG_CLASS; |
5462 | else | |
c4963a0a | 5463 | context_reg_class = base_reg_class (mode, outer_code, index_code); |
888d2cd6 | 5464 | |
a2d353e5 | 5465 | switch (code) |
eab89b90 | 5466 | { |
a2d353e5 RK |
5467 | case PLUS: |
5468 | { | |
b3694847 SS |
5469 | rtx orig_op0 = XEXP (x, 0); |
5470 | rtx orig_op1 = XEXP (x, 1); | |
5471 | RTX_CODE code0 = GET_CODE (orig_op0); | |
5472 | RTX_CODE code1 = GET_CODE (orig_op1); | |
5473 | rtx op0 = orig_op0; | |
5474 | rtx op1 = orig_op1; | |
a2d353e5 RK |
5475 | |
5476 | if (GET_CODE (op0) == SUBREG) | |
5477 | { | |
5478 | op0 = SUBREG_REG (op0); | |
5479 | code0 = GET_CODE (op0); | |
922db4bb | 5480 | if (code0 == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER) |
38a448ca | 5481 | op0 = gen_rtx_REG (word_mode, |
ddef6bc7 JJ |
5482 | (REGNO (op0) + |
5483 | subreg_regno_offset (REGNO (SUBREG_REG (orig_op0)), | |
5484 | GET_MODE (SUBREG_REG (orig_op0)), | |
5485 | SUBREG_BYTE (orig_op0), | |
5486 | GET_MODE (orig_op0)))); | |
a2d353e5 | 5487 | } |
87935f60 | 5488 | |
a2d353e5 RK |
5489 | if (GET_CODE (op1) == SUBREG) |
5490 | { | |
5491 | op1 = SUBREG_REG (op1); | |
5492 | code1 = GET_CODE (op1); | |
922db4bb | 5493 | if (code1 == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER) |
ddef6bc7 JJ |
5494 | /* ??? Why is this given op1's mode and above for |
5495 | ??? op0 SUBREGs we use word_mode? */ | |
38a448ca | 5496 | op1 = gen_rtx_REG (GET_MODE (op1), |
ddef6bc7 JJ |
5497 | (REGNO (op1) + |
5498 | subreg_regno_offset (REGNO (SUBREG_REG (orig_op1)), | |
5499 | GET_MODE (SUBREG_REG (orig_op1)), | |
5500 | SUBREG_BYTE (orig_op1), | |
5501 | GET_MODE (orig_op1)))); | |
a2d353e5 | 5502 | } |
04c5580f | 5503 | /* Plus in the index register may be created only as a result of |
6fc0bb99 | 5504 | register rematerialization for expression like &localvar*4. Reload it. |
04c5580f JH |
5505 | It may be possible to combine the displacement on the outer level, |
5506 | but it is probably not worthwhile to do so. */ | |
888d2cd6 | 5507 | if (context == 1) |
04c5580f JH |
5508 | { |
5509 | find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0), | |
5510 | opnum, ADDR_TYPE (type), ind_levels, insn); | |
5511 | push_reload (*loc, NULL_RTX, loc, (rtx*) 0, | |
888d2cd6 | 5512 | context_reg_class, |
04c5580f JH |
5513 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5514 | return 1; | |
5515 | } | |
a2d353e5 | 5516 | |
05d10675 | 5517 | if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE |
5f8997b9 | 5518 | || code0 == ZERO_EXTEND || code1 == MEM) |
a2d353e5 | 5519 | { |
c4963a0a BS |
5520 | find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH, |
5521 | &XEXP (x, 0), opnum, type, ind_levels, | |
5522 | insn); | |
5523 | find_reloads_address_1 (mode, orig_op1, 0, PLUS, code0, | |
5524 | &XEXP (x, 1), opnum, type, ind_levels, | |
5525 | insn); | |
a2d353e5 RK |
5526 | } |
5527 | ||
5f8997b9 SC |
5528 | else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE |
5529 | || code1 == ZERO_EXTEND || code0 == MEM) | |
a2d353e5 | 5530 | { |
c4963a0a BS |
5531 | find_reloads_address_1 (mode, orig_op0, 0, PLUS, code1, |
5532 | &XEXP (x, 0), opnum, type, ind_levels, | |
5533 | insn); | |
5534 | find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH, | |
5535 | &XEXP (x, 1), opnum, type, ind_levels, | |
5536 | insn); | |
a2d353e5 RK |
5537 | } |
5538 | ||
5539 | else if (code0 == CONST_INT || code0 == CONST | |
5540 | || code0 == SYMBOL_REF || code0 == LABEL_REF) | |
c4963a0a BS |
5541 | find_reloads_address_1 (mode, orig_op1, 0, PLUS, code0, |
5542 | &XEXP (x, 1), opnum, type, ind_levels, | |
5543 | insn); | |
a2d353e5 RK |
5544 | |
5545 | else if (code1 == CONST_INT || code1 == CONST | |
5546 | || code1 == SYMBOL_REF || code1 == LABEL_REF) | |
c4963a0a BS |
5547 | find_reloads_address_1 (mode, orig_op0, 0, PLUS, code1, |
5548 | &XEXP (x, 0), opnum, type, ind_levels, | |
5549 | insn); | |
a2d353e5 RK |
5550 | |
5551 | else if (code0 == REG && code1 == REG) | |
5552 | { | |
bd379f73 PH |
5553 | if (REGNO_OK_FOR_INDEX_P (REGNO (op1)) |
5554 | && regno_ok_for_base_p (REGNO (op0), mode, PLUS, REG)) | |
a2d353e5 | 5555 | return 0; |
bd379f73 PH |
5556 | else if (REGNO_OK_FOR_INDEX_P (REGNO (op0)) |
5557 | && regno_ok_for_base_p (REGNO (op1), mode, PLUS, REG)) | |
a2d353e5 | 5558 | return 0; |
c4963a0a BS |
5559 | else if (regno_ok_for_base_p (REGNO (op0), mode, PLUS, REG)) |
5560 | find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH, | |
5561 | &XEXP (x, 1), opnum, type, ind_levels, | |
5562 | insn); | |
5563 | else if (REGNO_OK_FOR_INDEX_P (REGNO (op1))) | |
5564 | find_reloads_address_1 (mode, orig_op0, 0, PLUS, REG, | |
5565 | &XEXP (x, 0), opnum, type, ind_levels, | |
5566 | insn); | |
bd379f73 PH |
5567 | else if (regno_ok_for_base_p (REGNO (op1), mode, PLUS, REG)) |
5568 | find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH, | |
5569 | &XEXP (x, 0), opnum, type, ind_levels, | |
5570 | insn); | |
c4963a0a BS |
5571 | else if (REGNO_OK_FOR_INDEX_P (REGNO (op0))) |
5572 | find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG, | |
5573 | &XEXP (x, 1), opnum, type, ind_levels, | |
5574 | insn); | |
a2d353e5 RK |
5575 | else |
5576 | { | |
bd379f73 | 5577 | find_reloads_address_1 (mode, orig_op0, 0, PLUS, REG, |
c4963a0a BS |
5578 | &XEXP (x, 0), opnum, type, ind_levels, |
5579 | insn); | |
bd379f73 | 5580 | find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH, |
c4963a0a BS |
5581 | &XEXP (x, 1), opnum, type, ind_levels, |
5582 | insn); | |
a2d353e5 RK |
5583 | } |
5584 | } | |
5585 | ||
5586 | else if (code0 == REG) | |
5587 | { | |
c4963a0a BS |
5588 | find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH, |
5589 | &XEXP (x, 0), opnum, type, ind_levels, | |
5590 | insn); | |
5591 | find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG, | |
5592 | &XEXP (x, 1), opnum, type, ind_levels, | |
5593 | insn); | |
a2d353e5 RK |
5594 | } |
5595 | ||
5596 | else if (code1 == REG) | |
5597 | { | |
c4963a0a BS |
5598 | find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH, |
5599 | &XEXP (x, 1), opnum, type, ind_levels, | |
5600 | insn); | |
5601 | find_reloads_address_1 (mode, orig_op0, 0, PLUS, REG, | |
5602 | &XEXP (x, 0), opnum, type, ind_levels, | |
5603 | insn); | |
a2d353e5 RK |
5604 | } |
5605 | } | |
5606 | ||
5607 | return 0; | |
5608 | ||
4b983fdc RH |
5609 | case POST_MODIFY: |
5610 | case PRE_MODIFY: | |
5611 | { | |
5612 | rtx op0 = XEXP (x, 0); | |
5613 | rtx op1 = XEXP (x, 1); | |
c4963a0a | 5614 | enum rtx_code index_code; |
41374e13 NS |
5615 | int regno; |
5616 | int reloadnum; | |
4b983fdc RH |
5617 | |
5618 | if (GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS) | |
5619 | return 0; | |
5620 | ||
5621 | /* Currently, we only support {PRE,POST}_MODIFY constructs | |
5622 | where a base register is {inc,dec}remented by the contents | |
5623 | of another register or by a constant value. Thus, these | |
5624 | operands must match. */ | |
41374e13 | 5625 | gcc_assert (op0 == XEXP (op1, 0)); |
4b983fdc RH |
5626 | |
5627 | /* Require index register (or constant). Let's just handle the | |
5628 | register case in the meantime... If the target allows | |
5629 | auto-modify by a constant then we could try replacing a pseudo | |
4b7b277a RS |
5630 | register with its equivalent constant where applicable. |
5631 | ||
b098aaf2 UW |
5632 | We also handle the case where the register was eliminated |
5633 | resulting in a PLUS subexpression. | |
5634 | ||
4b7b277a RS |
5635 | If we later decide to reload the whole PRE_MODIFY or |
5636 | POST_MODIFY, inc_for_reload might clobber the reload register | |
5637 | before reading the index. The index register might therefore | |
5638 | need to live longer than a TYPE reload normally would, so be | |
5639 | conservative and class it as RELOAD_OTHER. */ | |
b098aaf2 UW |
5640 | if ((REG_P (XEXP (op1, 1)) |
5641 | && !REGNO_OK_FOR_INDEX_P (REGNO (XEXP (op1, 1)))) | |
5642 | || GET_CODE (XEXP (op1, 1)) == PLUS) | |
5643 | find_reloads_address_1 (mode, XEXP (op1, 1), 1, code, SCRATCH, | |
5644 | &XEXP (op1, 1), opnum, RELOAD_OTHER, | |
5645 | ind_levels, insn); | |
4b983fdc | 5646 | |
41374e13 | 5647 | gcc_assert (REG_P (XEXP (op1, 0))); |
4b983fdc | 5648 | |
41374e13 | 5649 | regno = REGNO (XEXP (op1, 0)); |
c4963a0a | 5650 | index_code = GET_CODE (XEXP (op1, 1)); |
41374e13 NS |
5651 | |
5652 | /* A register that is incremented cannot be constant! */ | |
5653 | gcc_assert (regno < FIRST_PSEUDO_REGISTER | |
5654 | || reg_equiv_constant[regno] == 0); | |
4b983fdc | 5655 | |
41374e13 NS |
5656 | /* Handle a register that is equivalent to a memory location |
5657 | which cannot be addressed directly. */ | |
5658 | if (reg_equiv_memory_loc[regno] != 0 | |
5659 | && (reg_equiv_address[regno] != 0 | |
5660 | || num_not_at_initial_offset)) | |
5661 | { | |
5662 | rtx tem = make_memloc (XEXP (x, 0), regno); | |
4b983fdc | 5663 | |
41374e13 NS |
5664 | if (reg_equiv_address[regno] |
5665 | || ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
4b983fdc | 5666 | { |
3f1e3e70 AO |
5667 | rtx orig = tem; |
5668 | ||
41374e13 NS |
5669 | /* First reload the memory location's address. |
5670 | We can't use ADDR_TYPE (type) here, because we need to | |
5671 | write back the value after reading it, hence we actually | |
5672 | need two registers. */ | |
5673 | find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), | |
5674 | &XEXP (tem, 0), opnum, | |
5675 | RELOAD_OTHER, | |
5676 | ind_levels, insn); | |
5677 | ||
0f4b25a3 | 5678 | if (!rtx_equal_p (tem, orig)) |
3f1e3e70 AO |
5679 | push_reg_equiv_alt_mem (regno, tem); |
5680 | ||
41374e13 | 5681 | /* Then reload the memory location into a base |
c4963a0a | 5682 | register. */ |
41374e13 | 5683 | reloadnum = push_reload (tem, tem, &XEXP (x, 0), |
c4963a0a BS |
5684 | &XEXP (op1, 0), |
5685 | base_reg_class (mode, code, | |
5686 | index_code), | |
5687 | GET_MODE (x), GET_MODE (x), 0, | |
5688 | 0, opnum, RELOAD_OTHER); | |
9532e31f | 5689 | |
98c17df2 GS |
5690 | update_auto_inc_notes (this_insn, regno, reloadnum); |
5691 | return 0; | |
5692 | } | |
4b983fdc | 5693 | } |
41374e13 NS |
5694 | |
5695 | if (reg_renumber[regno] >= 0) | |
5696 | regno = reg_renumber[regno]; | |
5697 | ||
5698 | /* We require a base register here... */ | |
c4963a0a | 5699 | if (!regno_ok_for_base_p (regno, GET_MODE (x), code, index_code)) |
41374e13 NS |
5700 | { |
5701 | reloadnum = push_reload (XEXP (op1, 0), XEXP (x, 0), | |
c4963a0a BS |
5702 | &XEXP (op1, 0), &XEXP (x, 0), |
5703 | base_reg_class (mode, code, index_code), | |
5704 | GET_MODE (x), GET_MODE (x), 0, 0, | |
5705 | opnum, RELOAD_OTHER); | |
41374e13 NS |
5706 | |
5707 | update_auto_inc_notes (this_insn, regno, reloadnum); | |
5708 | return 0; | |
5709 | } | |
4b983fdc RH |
5710 | } |
5711 | return 0; | |
5712 | ||
a2d353e5 RK |
5713 | case POST_INC: |
5714 | case POST_DEC: | |
5715 | case PRE_INC: | |
5716 | case PRE_DEC: | |
f8cfc6aa | 5717 | if (REG_P (XEXP (x, 0))) |
eab89b90 | 5718 | { |
b3694847 | 5719 | int regno = REGNO (XEXP (x, 0)); |
eab89b90 RK |
5720 | int value = 0; |
5721 | rtx x_orig = x; | |
5722 | ||
5723 | /* A register that is incremented cannot be constant! */ | |
41374e13 NS |
5724 | gcc_assert (regno < FIRST_PSEUDO_REGISTER |
5725 | || reg_equiv_constant[regno] == 0); | |
eab89b90 RK |
5726 | |
5727 | /* Handle a register that is equivalent to a memory location | |
5728 | which cannot be addressed directly. */ | |
cb2afeb3 R |
5729 | if (reg_equiv_memory_loc[regno] != 0 |
5730 | && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)) | |
eab89b90 RK |
5731 | { |
5732 | rtx tem = make_memloc (XEXP (x, 0), regno); | |
cb2afeb3 R |
5733 | if (reg_equiv_address[regno] |
5734 | || ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
5735 | { | |
3f1e3e70 AO |
5736 | rtx orig = tem; |
5737 | ||
cb2afeb3 R |
5738 | /* First reload the memory location's address. |
5739 | We can't use ADDR_TYPE (type) here, because we need to | |
5740 | write back the value after reading it, hence we actually | |
5741 | need two registers. */ | |
5742 | find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), | |
5743 | &XEXP (tem, 0), opnum, type, | |
5744 | ind_levels, insn); | |
0f4b25a3 | 5745 | if (!rtx_equal_p (tem, orig)) |
3f1e3e70 | 5746 | push_reg_equiv_alt_mem (regno, tem); |
cb2afeb3 R |
5747 | /* Put this inside a new increment-expression. */ |
5748 | x = gen_rtx_fmt_e (GET_CODE (x), GET_MODE (x), tem); | |
5749 | /* Proceed to reload that, as if it contained a register. */ | |
5750 | } | |
eab89b90 RK |
5751 | } |
5752 | ||
f89935ed HPN |
5753 | /* If we have a hard register that is ok in this incdec context, |
5754 | don't make a reload. If the register isn't nice enough for | |
5755 | autoincdec, we can reload it. But, if an autoincrement of a | |
5756 | register that we here verified as playing nice, still outside | |
eab89b90 RK |
5757 | isn't "valid", it must be that no autoincrement is "valid". |
5758 | If that is true and something made an autoincrement anyway, | |
5759 | this must be a special context where one is allowed. | |
5760 | (For example, a "push" instruction.) | |
5761 | We can't improve this address, so leave it alone. */ | |
5762 | ||
5763 | /* Otherwise, reload the autoincrement into a suitable hard reg | |
5764 | and record how much to increment by. */ | |
5765 | ||
5766 | if (reg_renumber[regno] >= 0) | |
5767 | regno = reg_renumber[regno]; | |
888d2cd6 | 5768 | if (regno >= FIRST_PSEUDO_REGISTER |
f89935ed | 5769 | || !REG_OK_FOR_CONTEXT (context, regno, mode, code, |
c4963a0a | 5770 | index_code)) |
eab89b90 | 5771 | { |
55c22565 RK |
5772 | int reloadnum; |
5773 | ||
5774 | /* If we can output the register afterwards, do so, this | |
5775 | saves the extra update. | |
5776 | We can do so if we have an INSN - i.e. no JUMP_INSN nor | |
5777 | CALL_INSN - and it does not set CC0. | |
5778 | But don't do this if we cannot directly address the | |
5779 | memory location, since this will make it harder to | |
956d6950 | 5780 | reuse address reloads, and increases register pressure. |
55c22565 | 5781 | Also don't do this if we can probably update x directly. */ |
3c0cb5de | 5782 | rtx equiv = (MEM_P (XEXP (x, 0)) |
cb2afeb3 R |
5783 | ? XEXP (x, 0) |
5784 | : reg_equiv_mem[regno]); | |
166cdb08 | 5785 | int icode = (int) optab_handler (add_optab, Pmode)->insn_code; |
4b4bf941 | 5786 | if (insn && NONJUMP_INSN_P (insn) && equiv |
cb2afeb3 | 5787 | && memory_operand (equiv, GET_MODE (equiv)) |
55c22565 RK |
5788 | #ifdef HAVE_cc0 |
5789 | && ! sets_cc0_p (PATTERN (insn)) | |
5790 | #endif | |
5791 | && ! (icode != CODE_FOR_nothing | |
a995e389 RH |
5792 | && ((*insn_data[icode].operand[0].predicate) |
5793 | (equiv, Pmode)) | |
5794 | && ((*insn_data[icode].operand[1].predicate) | |
5795 | (equiv, Pmode)))) | |
55c22565 | 5796 | { |
9e8f528c AO |
5797 | /* We use the original pseudo for loc, so that |
5798 | emit_reload_insns() knows which pseudo this | |
5799 | reload refers to and updates the pseudo rtx, not | |
5800 | its equivalent memory location, as well as the | |
5801 | corresponding entry in reg_last_reload_reg. */ | |
5802 | loc = &XEXP (x_orig, 0); | |
55c22565 RK |
5803 | x = XEXP (x, 0); |
5804 | reloadnum | |
5805 | = push_reload (x, x, loc, loc, | |
888d2cd6 | 5806 | context_reg_class, |
05d10675 BS |
5807 | GET_MODE (x), GET_MODE (x), 0, 0, |
5808 | opnum, RELOAD_OTHER); | |
55c22565 RK |
5809 | } |
5810 | else | |
5811 | { | |
5812 | reloadnum | |
7fb446a3 | 5813 | = push_reload (x, x, loc, (rtx*) 0, |
888d2cd6 | 5814 | context_reg_class, |
e9a25f70 | 5815 | GET_MODE (x), GET_MODE (x), 0, 0, |
55c22565 | 5816 | opnum, type); |
eceef4c9 | 5817 | rld[reloadnum].inc |
55c22565 | 5818 | = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0)); |
05d10675 | 5819 | |
55c22565 RK |
5820 | value = 1; |
5821 | } | |
eab89b90 | 5822 | |
98c17df2 GS |
5823 | update_auto_inc_notes (this_insn, REGNO (XEXP (x_orig, 0)), |
5824 | reloadnum); | |
eab89b90 RK |
5825 | } |
5826 | return value; | |
5827 | } | |
a2d353e5 RK |
5828 | return 0; |
5829 | ||
19fe122f HPN |
5830 | case TRUNCATE: |
5831 | case SIGN_EXTEND: | |
5832 | case ZERO_EXTEND: | |
5833 | /* Look for parts to reload in the inner expression and reload them | |
5834 | too, in addition to this operation. Reloading all inner parts in | |
5835 | addition to this one shouldn't be necessary, but at this point, | |
5836 | we don't know if we can possibly omit any part that *can* be | |
5837 | reloaded. Targets that are better off reloading just either part | |
5838 | (or perhaps even a different part of an outer expression), should | |
5839 | define LEGITIMIZE_RELOAD_ADDRESS. */ | |
5840 | find_reloads_address_1 (GET_MODE (XEXP (x, 0)), XEXP (x, 0), | |
c4963a0a | 5841 | context, code, SCRATCH, &XEXP (x, 0), opnum, |
19fe122f HPN |
5842 | type, ind_levels, insn); |
5843 | push_reload (x, NULL_RTX, loc, (rtx*) 0, | |
5844 | context_reg_class, | |
5845 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); | |
5846 | return 1; | |
5847 | ||
a2d353e5 RK |
5848 | case MEM: |
5849 | /* This is probably the result of a substitution, by eliminate_regs, of | |
5850 | an equivalent address for a pseudo that was not allocated to a hard | |
5851 | register. Verify that the specified address is valid and reload it | |
5852 | into a register. | |
eab89b90 | 5853 | |
a2d353e5 RK |
5854 | Since we know we are going to reload this item, don't decrement for |
5855 | the indirection level. | |
eab89b90 RK |
5856 | |
5857 | Note that this is actually conservative: it would be slightly more | |
5858 | efficient to use the value of SPILL_INDIRECT_LEVELS from | |
5859 | reload1.c here. */ | |
5860 | ||
5861 | find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0), | |
55c22565 | 5862 | opnum, ADDR_TYPE (type), ind_levels, insn); |
f4f4d0f8 | 5863 | push_reload (*loc, NULL_RTX, loc, (rtx*) 0, |
888d2cd6 | 5864 | context_reg_class, |
a8c9daeb | 5865 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
eab89b90 | 5866 | return 1; |
eab89b90 | 5867 | |
a2d353e5 RK |
5868 | case REG: |
5869 | { | |
b3694847 | 5870 | int regno = REGNO (x); |
a2d353e5 RK |
5871 | |
5872 | if (reg_equiv_constant[regno] != 0) | |
5873 | { | |
03acd8f8 | 5874 | find_reloads_address_part (reg_equiv_constant[regno], loc, |
888d2cd6 | 5875 | context_reg_class, |
a2d353e5 RK |
5876 | GET_MODE (x), opnum, type, ind_levels); |
5877 | return 1; | |
5878 | } | |
eab89b90 RK |
5879 | |
5880 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
5881 | that feeds this insn. */ | |
a2d353e5 RK |
5882 | if (reg_equiv_mem[regno] != 0) |
5883 | { | |
f4f4d0f8 | 5884 | push_reload (reg_equiv_mem[regno], NULL_RTX, loc, (rtx*) 0, |
888d2cd6 | 5885 | context_reg_class, |
a2d353e5 RK |
5886 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5887 | return 1; | |
5888 | } | |
eab89b90 | 5889 | #endif |
eab89b90 | 5890 | |
cb2afeb3 R |
5891 | if (reg_equiv_memory_loc[regno] |
5892 | && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)) | |
a2d353e5 | 5893 | { |
cb2afeb3 R |
5894 | rtx tem = make_memloc (x, regno); |
5895 | if (reg_equiv_address[regno] != 0 | |
5896 | || ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
5897 | { | |
5898 | x = tem; | |
5899 | find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), | |
5900 | &XEXP (x, 0), opnum, ADDR_TYPE (type), | |
5901 | ind_levels, insn); | |
0f4b25a3 | 5902 | if (!rtx_equal_p (x, tem)) |
3f1e3e70 | 5903 | push_reg_equiv_alt_mem (regno, x); |
cb2afeb3 | 5904 | } |
a2d353e5 | 5905 | } |
eab89b90 | 5906 | |
a2d353e5 RK |
5907 | if (reg_renumber[regno] >= 0) |
5908 | regno = reg_renumber[regno]; | |
5909 | ||
888d2cd6 | 5910 | if (regno >= FIRST_PSEUDO_REGISTER |
c4963a0a BS |
5911 | || !REG_OK_FOR_CONTEXT (context, regno, mode, outer_code, |
5912 | index_code)) | |
a2d353e5 | 5913 | { |
f4f4d0f8 | 5914 | push_reload (x, NULL_RTX, loc, (rtx*) 0, |
888d2cd6 | 5915 | context_reg_class, |
a2d353e5 RK |
5916 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5917 | return 1; | |
5918 | } | |
5919 | ||
5920 | /* If a register appearing in an address is the subject of a CLOBBER | |
5921 | in this insn, reload it into some other register to be safe. | |
5922 | The CLOBBER is supposed to make the register unavailable | |
5923 | from before this insn to after it. */ | |
9532e31f | 5924 | if (regno_clobbered_p (regno, this_insn, GET_MODE (x), 0)) |
a2d353e5 | 5925 | { |
f4f4d0f8 | 5926 | push_reload (x, NULL_RTX, loc, (rtx*) 0, |
888d2cd6 | 5927 | context_reg_class, |
a2d353e5 RK |
5928 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5929 | return 1; | |
5930 | } | |
5931 | } | |
5932 | return 0; | |
5933 | ||
5934 | case SUBREG: | |
f8cfc6aa | 5935 | if (REG_P (SUBREG_REG (x))) |
eab89b90 | 5936 | { |
922db4bb RK |
5937 | /* If this is a SUBREG of a hard register and the resulting register |
5938 | is of the wrong class, reload the whole SUBREG. This avoids | |
5939 | needless copies if SUBREG_REG is multi-word. */ | |
5940 | if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) | |
5941 | { | |
4977bab6 | 5942 | int regno ATTRIBUTE_UNUSED = subreg_regno (x); |
a2d353e5 | 5943 | |
c4963a0a BS |
5944 | if (!REG_OK_FOR_CONTEXT (context, regno, mode, outer_code, |
5945 | index_code)) | |
922db4bb | 5946 | { |
f4f4d0f8 | 5947 | push_reload (x, NULL_RTX, loc, (rtx*) 0, |
888d2cd6 | 5948 | context_reg_class, |
922db4bb RK |
5949 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5950 | return 1; | |
5951 | } | |
5952 | } | |
abc95ed3 | 5953 | /* If this is a SUBREG of a pseudo-register, and the pseudo-register |
922db4bb RK |
5954 | is larger than the class size, then reload the whole SUBREG. */ |
5955 | else | |
a2d353e5 | 5956 | { |
55d796da KG |
5957 | enum reg_class rclass = context_reg_class; |
5958 | if ((unsigned) CLASS_MAX_NREGS (rclass, GET_MODE (SUBREG_REG (x))) | |
5959 | > reg_class_size[rclass]) | |
922db4bb | 5960 | { |
50aa8e71 R |
5961 | x = find_reloads_subreg_address (x, 0, opnum, |
5962 | ADDR_TYPE (type), | |
22505ad8 | 5963 | ind_levels, insn); |
55d796da | 5964 | push_reload (x, NULL_RTX, loc, (rtx*) 0, rclass, |
922db4bb RK |
5965 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5966 | return 1; | |
5967 | } | |
a2d353e5 | 5968 | } |
eab89b90 | 5969 | } |
a2d353e5 | 5970 | break; |
05d10675 | 5971 | |
e9a25f70 JL |
5972 | default: |
5973 | break; | |
eab89b90 RK |
5974 | } |
5975 | ||
a2d353e5 | 5976 | { |
b3694847 SS |
5977 | const char *fmt = GET_RTX_FORMAT (code); |
5978 | int i; | |
a2d353e5 RK |
5979 | |
5980 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5981 | { | |
5982 | if (fmt[i] == 'e') | |
c4963a0a BS |
5983 | /* Pass SCRATCH for INDEX_CODE, since CODE can never be a PLUS once |
5984 | we get here. */ | |
5985 | find_reloads_address_1 (mode, XEXP (x, i), context, code, SCRATCH, | |
5986 | &XEXP (x, i), opnum, type, ind_levels, insn); | |
a2d353e5 RK |
5987 | } |
5988 | } | |
5989 | ||
888d2cd6 | 5990 | #undef REG_OK_FOR_CONTEXT |
eab89b90 RK |
5991 | return 0; |
5992 | } | |
5993 | \f | |
5994 | /* X, which is found at *LOC, is a part of an address that needs to be | |
55d796da | 5995 | reloaded into a register of class RCLASS. If X is a constant, or if |
eab89b90 RK |
5996 | X is a PLUS that contains a constant, check that the constant is a |
5997 | legitimate operand and that we are supposed to be able to load | |
5998 | it into the register. | |
5999 | ||
6000 | If not, force the constant into memory and reload the MEM instead. | |
6001 | ||
6002 | MODE is the mode to use, in case X is an integer constant. | |
6003 | ||
a8c9daeb | 6004 | OPNUM and TYPE describe the purpose of any reloads made. |
eab89b90 RK |
6005 | |
6006 | IND_LEVELS says how many levels of indirect addressing this machine | |
6007 | supports. */ | |
6008 | ||
6009 | static void | |
55d796da | 6010 | find_reloads_address_part (rtx x, rtx *loc, enum reg_class rclass, |
0c20a65f AJ |
6011 | enum machine_mode mode, int opnum, |
6012 | enum reload_type type, int ind_levels) | |
eab89b90 RK |
6013 | { |
6014 | if (CONSTANT_P (x) | |
6015 | && (! LEGITIMATE_CONSTANT_P (x) | |
55d796da | 6016 | || PREFERRED_RELOAD_CLASS (x, rclass) == NO_REGS)) |
eab89b90 | 6017 | { |
e4fd64d6 SL |
6018 | x = force_const_mem (mode, x); |
6019 | find_reloads_address (mode, &x, XEXP (x, 0), &XEXP (x, 0), | |
55c22565 | 6020 | opnum, type, ind_levels, 0); |
eab89b90 RK |
6021 | } |
6022 | ||
6023 | else if (GET_CODE (x) == PLUS | |
6024 | && CONSTANT_P (XEXP (x, 1)) | |
6025 | && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1)) | |
55d796da | 6026 | || PREFERRED_RELOAD_CLASS (XEXP (x, 1), rclass) == NO_REGS)) |
eab89b90 | 6027 | { |
ef18065c JW |
6028 | rtx tem; |
6029 | ||
081b49f1 | 6030 | tem = force_const_mem (GET_MODE (x), XEXP (x, 1)); |
38a448ca | 6031 | x = gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), tem); |
e4fd64d6 | 6032 | find_reloads_address (mode, &XEXP (x, 1), XEXP (tem, 0), &XEXP (tem, 0), |
55c22565 | 6033 | opnum, type, ind_levels, 0); |
eab89b90 RK |
6034 | } |
6035 | ||
55d796da | 6036 | push_reload (x, NULL_RTX, loc, (rtx*) 0, rclass, |
a8c9daeb | 6037 | mode, VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
6038 | } |
6039 | \f | |
22505ad8 R |
6040 | /* X, a subreg of a pseudo, is a part of an address that needs to be |
6041 | reloaded. | |
6042 | ||
6043 | If the pseudo is equivalent to a memory location that cannot be directly | |
6044 | addressed, make the necessary address reloads. | |
6045 | ||
6046 | If address reloads have been necessary, or if the address is changed | |
6047 | by register elimination, return the rtx of the memory location; | |
6048 | otherwise, return X. | |
6049 | ||
6050 | If FORCE_REPLACE is nonzero, unconditionally replace the subreg with the | |
6051 | memory location. | |
6052 | ||
6053 | OPNUM and TYPE identify the purpose of the reload. | |
6054 | ||
6055 | IND_LEVELS says how many levels of indirect addressing are | |
6056 | supported at this point in the address. | |
6057 | ||
6058 | INSN, if nonzero, is the insn in which we do the reload. It is used | |
6059 | to determine where to put USEs for pseudos that we have to replace with | |
6060 | stack slots. */ | |
6061 | ||
6062 | static rtx | |
0c20a65f AJ |
6063 | find_reloads_subreg_address (rtx x, int force_replace, int opnum, |
6064 | enum reload_type type, int ind_levels, rtx insn) | |
22505ad8 R |
6065 | { |
6066 | int regno = REGNO (SUBREG_REG (x)); | |
6067 | ||
6068 | if (reg_equiv_memory_loc[regno]) | |
6069 | { | |
6070 | /* If the address is not directly addressable, or if the address is not | |
6071 | offsettable, then it must be replaced. */ | |
6072 | if (! force_replace | |
6073 | && (reg_equiv_address[regno] | |
6074 | || ! offsettable_memref_p (reg_equiv_mem[regno]))) | |
6075 | force_replace = 1; | |
6076 | ||
6077 | if (force_replace || num_not_at_initial_offset) | |
6078 | { | |
6079 | rtx tem = make_memloc (SUBREG_REG (x), regno); | |
6080 | ||
6081 | /* If the address changes because of register elimination, then | |
dd074554 | 6082 | it must be replaced. */ |
22505ad8 R |
6083 | if (force_replace |
6084 | || ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
6085 | { | |
0a28aef9 RH |
6086 | unsigned outer_size = GET_MODE_SIZE (GET_MODE (x)); |
6087 | unsigned inner_size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))); | |
6357135a | 6088 | int offset; |
3f1e3e70 | 6089 | rtx orig = tem; |
f5c3dc96 | 6090 | int reloaded; |
6357135a UW |
6091 | |
6092 | /* For big-endian paradoxical subregs, SUBREG_BYTE does not | |
6093 | hold the correct (negative) byte offset. */ | |
6094 | if (BYTES_BIG_ENDIAN && outer_size > inner_size) | |
6095 | offset = inner_size - outer_size; | |
6096 | else | |
6097 | offset = SUBREG_BYTE (x); | |
22505ad8 | 6098 | |
22505ad8 R |
6099 | XEXP (tem, 0) = plus_constant (XEXP (tem, 0), offset); |
6100 | PUT_MODE (tem, GET_MODE (x)); | |
38ae7651 RS |
6101 | if (MEM_OFFSET (tem)) |
6102 | set_mem_offset (tem, plus_constant (MEM_OFFSET (tem), offset)); | |
0a28aef9 RH |
6103 | |
6104 | /* If this was a paradoxical subreg that we replaced, the | |
6105 | resulting memory must be sufficiently aligned to allow | |
6106 | us to widen the mode of the memory. */ | |
5a575f77 | 6107 | if (outer_size > inner_size) |
0a28aef9 RH |
6108 | { |
6109 | rtx base; | |
6110 | ||
6111 | base = XEXP (tem, 0); | |
6112 | if (GET_CODE (base) == PLUS) | |
6113 | { | |
481683e1 | 6114 | if (CONST_INT_P (XEXP (base, 1)) |
0a28aef9 RH |
6115 | && INTVAL (XEXP (base, 1)) % outer_size != 0) |
6116 | return x; | |
6117 | base = XEXP (base, 0); | |
6118 | } | |
f8cfc6aa | 6119 | if (!REG_P (base) |
0a28aef9 RH |
6120 | || (REGNO_POINTER_ALIGN (REGNO (base)) |
6121 | < outer_size * BITS_PER_UNIT)) | |
6122 | return x; | |
6123 | } | |
6124 | ||
f5c3dc96 ILT |
6125 | reloaded = find_reloads_address (GET_MODE (tem), &tem, |
6126 | XEXP (tem, 0), &XEXP (tem, 0), | |
6127 | opnum, type, ind_levels, insn); | |
3f1e3e70 | 6128 | /* ??? Do we need to handle nonzero offsets somehow? */ |
0f4b25a3 | 6129 | if (!offset && !rtx_equal_p (tem, orig)) |
3f1e3e70 | 6130 | push_reg_equiv_alt_mem (regno, tem); |
0a28aef9 | 6131 | |
f5c3dc96 ILT |
6132 | /* For some processors an address may be valid in the |
6133 | original mode but not in a smaller mode. For | |
6134 | example, ARM accepts a scaled index register in | |
10932211 JM |
6135 | SImode but not in HImode. Similarly, the address may |
6136 | have been valid before the subreg offset was added, | |
6137 | but not afterwards. find_reloads_address | |
f5c3dc96 ILT |
6138 | assumes that we pass it a valid address, and doesn't |
6139 | force a reload. This will probably be fine if | |
6140 | find_reloads_address finds some reloads. But if it | |
6141 | doesn't find any, then we may have just converted a | |
6142 | valid address into an invalid one. Check for that | |
6143 | here. */ | |
ea471af0 | 6144 | if (reloaded == 0 |
f5c3dc96 ILT |
6145 | && !strict_memory_address_p (GET_MODE (tem), |
6146 | XEXP (tem, 0))) | |
6147 | push_reload (XEXP (tem, 0), NULL_RTX, &XEXP (tem, 0), (rtx*) 0, | |
6148 | base_reg_class (GET_MODE (tem), MEM, SCRATCH), | |
6149 | GET_MODE (XEXP (tem, 0)), VOIDmode, 0, 0, | |
6150 | opnum, type); | |
6151 | ||
22505ad8 R |
6152 | /* If this is not a toplevel operand, find_reloads doesn't see |
6153 | this substitution. We have to emit a USE of the pseudo so | |
6154 | that delete_output_reload can see it. */ | |
1ccbefce | 6155 | if (replace_reloads && recog_data.operand[opnum] != x) |
3d17d93d AO |
6156 | /* We mark the USE with QImode so that we recognize it |
6157 | as one that can be safely deleted at the end of | |
6158 | reload. */ | |
6159 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, | |
6160 | SUBREG_REG (x)), | |
6161 | insn), QImode); | |
0ba9b9e6 | 6162 | x = tem; |
22505ad8 R |
6163 | } |
6164 | } | |
6165 | } | |
6166 | return x; | |
6167 | } | |
6168 | \f | |
a8c9daeb | 6169 | /* Substitute into the current INSN the registers into which we have reloaded |
eab89b90 | 6170 | the things that need reloading. The array `replacements' |
ecbe6c61 | 6171 | contains the locations of all pointers that must be changed |
eab89b90 RK |
6172 | and says what to replace them with. |
6173 | ||
6174 | Return the rtx that X translates into; usually X, but modified. */ | |
6175 | ||
6176 | void | |
0c20a65f | 6177 | subst_reloads (rtx insn) |
eab89b90 | 6178 | { |
b3694847 | 6179 | int i; |
eab89b90 RK |
6180 | |
6181 | for (i = 0; i < n_replacements; i++) | |
6182 | { | |
b3694847 SS |
6183 | struct replacement *r = &replacements[i]; |
6184 | rtx reloadreg = rld[r->what].reg_rtx; | |
eab89b90 RK |
6185 | if (reloadreg) |
6186 | { | |
0fa4cb7d SE |
6187 | #ifdef DEBUG_RELOAD |
6188 | /* This checking takes a very long time on some platforms | |
6189 | causing the gcc.c-torture/compile/limits-fnargs.c test | |
6190 | to time out during testing. See PR 31850. | |
6191 | ||
6192 | Internal consistency test. Check that we don't modify | |
cf728d61 HPN |
6193 | anything in the equivalence arrays. Whenever something from |
6194 | those arrays needs to be reloaded, it must be unshared before | |
6195 | being substituted into; the equivalence must not be modified. | |
6196 | Otherwise, if the equivalence is used after that, it will | |
6197 | have been modified, and the thing substituted (probably a | |
6198 | register) is likely overwritten and not a usable equivalence. */ | |
6199 | int check_regno; | |
6200 | ||
6201 | for (check_regno = 0; check_regno < max_regno; check_regno++) | |
6202 | { | |
6203 | #define CHECK_MODF(ARRAY) \ | |
41374e13 NS |
6204 | gcc_assert (!ARRAY[check_regno] \ |
6205 | || !loc_mentioned_in_p (r->where, \ | |
6206 | ARRAY[check_regno])) | |
cf728d61 HPN |
6207 | |
6208 | CHECK_MODF (reg_equiv_constant); | |
6209 | CHECK_MODF (reg_equiv_memory_loc); | |
6210 | CHECK_MODF (reg_equiv_address); | |
6211 | CHECK_MODF (reg_equiv_mem); | |
6212 | #undef CHECK_MODF | |
6213 | } | |
0fa4cb7d | 6214 | #endif /* DEBUG_RELOAD */ |
cf728d61 | 6215 | |
cf7c4aa6 HPN |
6216 | /* If we're replacing a LABEL_REF with a register, there must |
6217 | already be an indication (to e.g. flow) which label this | |
f759eb8b | 6218 | register refers to. */ |
cf7c4aa6 HPN |
6219 | gcc_assert (GET_CODE (*r->where) != LABEL_REF |
6220 | || !JUMP_P (insn) | |
6221 | || find_reg_note (insn, | |
6222 | REG_LABEL_OPERAND, | |
6223 | XEXP (*r->where, 0)) | |
6224 | || label_is_jump_target_p (XEXP (*r->where, 0), insn)); | |
f759eb8b | 6225 | |
eab89b90 | 6226 | /* Encapsulate RELOADREG so its machine mode matches what |
26f1a00e RK |
6227 | used to be there. Note that gen_lowpart_common will |
6228 | do the wrong thing if RELOADREG is multi-word. RELOADREG | |
6229 | will always be a REG here. */ | |
eab89b90 | 6230 | if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode) |
f12448c8 | 6231 | reloadreg = reload_adjust_reg_for_mode (reloadreg, r->mode); |
eab89b90 RK |
6232 | |
6233 | /* If we are putting this into a SUBREG and RELOADREG is a | |
6234 | SUBREG, we would be making nested SUBREGs, so we have to fix | |
6235 | this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */ | |
6236 | ||
6237 | if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG) | |
6238 | { | |
6239 | if (GET_MODE (*r->subreg_loc) | |
6240 | == GET_MODE (SUBREG_REG (reloadreg))) | |
6241 | *r->subreg_loc = SUBREG_REG (reloadreg); | |
6242 | else | |
6243 | { | |
ddef6bc7 JJ |
6244 | int final_offset = |
6245 | SUBREG_BYTE (*r->subreg_loc) + SUBREG_BYTE (reloadreg); | |
6246 | ||
6247 | /* When working with SUBREGs the rule is that the byte | |
6248 | offset must be a multiple of the SUBREG's mode. */ | |
6249 | final_offset = (final_offset / | |
6250 | GET_MODE_SIZE (GET_MODE (*r->subreg_loc))); | |
6251 | final_offset = (final_offset * | |
6252 | GET_MODE_SIZE (GET_MODE (*r->subreg_loc))); | |
6253 | ||
eab89b90 | 6254 | *r->where = SUBREG_REG (reloadreg); |
ddef6bc7 | 6255 | SUBREG_BYTE (*r->subreg_loc) = final_offset; |
eab89b90 RK |
6256 | } |
6257 | } | |
6258 | else | |
6259 | *r->where = reloadreg; | |
6260 | } | |
6261 | /* If reload got no reg and isn't optional, something's wrong. */ | |
41374e13 NS |
6262 | else |
6263 | gcc_assert (rld[r->what].optional); | |
eab89b90 RK |
6264 | } |
6265 | } | |
6266 | \f | |
561c9153 RH |
6267 | /* Make a copy of any replacements being done into X and move those |
6268 | copies to locations in Y, a copy of X. */ | |
eab89b90 RK |
6269 | |
6270 | void | |
0c20a65f | 6271 | copy_replacements (rtx x, rtx y) |
eab89b90 | 6272 | { |
eab89b90 RK |
6273 | /* We can't support X being a SUBREG because we might then need to know its |
6274 | location if something inside it was replaced. */ | |
41374e13 | 6275 | gcc_assert (GET_CODE (x) != SUBREG); |
eab89b90 | 6276 | |
561c9153 RH |
6277 | copy_replacements_1 (&x, &y, n_replacements); |
6278 | } | |
6279 | ||
6280 | static void | |
0c20a65f | 6281 | copy_replacements_1 (rtx *px, rtx *py, int orig_replacements) |
561c9153 RH |
6282 | { |
6283 | int i, j; | |
6284 | rtx x, y; | |
6285 | struct replacement *r; | |
6286 | enum rtx_code code; | |
6287 | const char *fmt; | |
6288 | ||
6289 | for (j = 0; j < orig_replacements; j++) | |
6290 | { | |
6291 | if (replacements[j].subreg_loc == px) | |
eab89b90 | 6292 | { |
561c9153 RH |
6293 | r = &replacements[n_replacements++]; |
6294 | r->where = replacements[j].where; | |
6295 | r->subreg_loc = py; | |
6296 | r->what = replacements[j].what; | |
6297 | r->mode = replacements[j].mode; | |
6298 | } | |
6299 | else if (replacements[j].where == px) | |
6300 | { | |
6301 | r = &replacements[n_replacements++]; | |
6302 | r->where = py; | |
6303 | r->subreg_loc = 0; | |
6304 | r->what = replacements[j].what; | |
6305 | r->mode = replacements[j].mode; | |
eab89b90 | 6306 | } |
561c9153 RH |
6307 | } |
6308 | ||
6309 | x = *px; | |
6310 | y = *py; | |
6311 | code = GET_CODE (x); | |
6312 | fmt = GET_RTX_FORMAT (code); | |
6313 | ||
6314 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6315 | { | |
6316 | if (fmt[i] == 'e') | |
6317 | copy_replacements_1 (&XEXP (x, i), &XEXP (y, i), orig_replacements); | |
6318 | else if (fmt[i] == 'E') | |
6319 | for (j = XVECLEN (x, i); --j >= 0; ) | |
6320 | copy_replacements_1 (&XVECEXP (x, i, j), &XVECEXP (y, i, j), | |
6321 | orig_replacements); | |
6322 | } | |
eab89b90 | 6323 | } |
a9a2595b | 6324 | |
3eae4643 | 6325 | /* Change any replacements being done to *X to be done to *Y. */ |
a9a2595b JR |
6326 | |
6327 | void | |
0c20a65f | 6328 | move_replacements (rtx *x, rtx *y) |
a9a2595b JR |
6329 | { |
6330 | int i; | |
6331 | ||
6332 | for (i = 0; i < n_replacements; i++) | |
6333 | if (replacements[i].subreg_loc == x) | |
6334 | replacements[i].subreg_loc = y; | |
6335 | else if (replacements[i].where == x) | |
6336 | { | |
6337 | replacements[i].where = y; | |
6338 | replacements[i].subreg_loc = 0; | |
6339 | } | |
6340 | } | |
eab89b90 | 6341 | \f |
af929c62 RK |
6342 | /* If LOC was scheduled to be replaced by something, return the replacement. |
6343 | Otherwise, return *LOC. */ | |
6344 | ||
6345 | rtx | |
0c20a65f | 6346 | find_replacement (rtx *loc) |
af929c62 RK |
6347 | { |
6348 | struct replacement *r; | |
6349 | ||
6350 | for (r = &replacements[0]; r < &replacements[n_replacements]; r++) | |
6351 | { | |
eceef4c9 | 6352 | rtx reloadreg = rld[r->what].reg_rtx; |
af929c62 RK |
6353 | |
6354 | if (reloadreg && r->where == loc) | |
6355 | { | |
6356 | if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode) | |
38a448ca | 6357 | reloadreg = gen_rtx_REG (r->mode, REGNO (reloadreg)); |
af929c62 RK |
6358 | |
6359 | return reloadreg; | |
6360 | } | |
6361 | else if (reloadreg && r->subreg_loc == loc) | |
6362 | { | |
6363 | /* RELOADREG must be either a REG or a SUBREG. | |
6364 | ||
6365 | ??? Is it actually still ever a SUBREG? If so, why? */ | |
6366 | ||
f8cfc6aa | 6367 | if (REG_P (reloadreg)) |
38a448ca | 6368 | return gen_rtx_REG (GET_MODE (*loc), |
ddef6bc7 JJ |
6369 | (REGNO (reloadreg) + |
6370 | subreg_regno_offset (REGNO (SUBREG_REG (*loc)), | |
6371 | GET_MODE (SUBREG_REG (*loc)), | |
6372 | SUBREG_BYTE (*loc), | |
6373 | GET_MODE (*loc)))); | |
af929c62 RK |
6374 | else if (GET_MODE (reloadreg) == GET_MODE (*loc)) |
6375 | return reloadreg; | |
6376 | else | |
ddef6bc7 JJ |
6377 | { |
6378 | int final_offset = SUBREG_BYTE (reloadreg) + SUBREG_BYTE (*loc); | |
6379 | ||
6380 | /* When working with SUBREGs the rule is that the byte | |
6381 | offset must be a multiple of the SUBREG's mode. */ | |
6382 | final_offset = (final_offset / GET_MODE_SIZE (GET_MODE (*loc))); | |
6383 | final_offset = (final_offset * GET_MODE_SIZE (GET_MODE (*loc))); | |
6384 | return gen_rtx_SUBREG (GET_MODE (*loc), SUBREG_REG (reloadreg), | |
6385 | final_offset); | |
6386 | } | |
af929c62 RK |
6387 | } |
6388 | } | |
6389 | ||
956d6950 JL |
6390 | /* If *LOC is a PLUS, MINUS, or MULT, see if a replacement is scheduled for |
6391 | what's inside and make a new rtl if so. */ | |
6392 | if (GET_CODE (*loc) == PLUS || GET_CODE (*loc) == MINUS | |
6393 | || GET_CODE (*loc) == MULT) | |
6394 | { | |
6395 | rtx x = find_replacement (&XEXP (*loc, 0)); | |
6396 | rtx y = find_replacement (&XEXP (*loc, 1)); | |
6397 | ||
6398 | if (x != XEXP (*loc, 0) || y != XEXP (*loc, 1)) | |
38a448ca | 6399 | return gen_rtx_fmt_ee (GET_CODE (*loc), GET_MODE (*loc), x, y); |
956d6950 JL |
6400 | } |
6401 | ||
af929c62 RK |
6402 | return *loc; |
6403 | } | |
6404 | \f | |
eab89b90 RK |
6405 | /* Return nonzero if register in range [REGNO, ENDREGNO) |
6406 | appears either explicitly or implicitly in X | |
4644aad4 | 6407 | other than being stored into (except for earlyclobber operands). |
eab89b90 RK |
6408 | |
6409 | References contained within the substructure at LOC do not count. | |
6410 | LOC may be zero, meaning don't ignore anything. | |
6411 | ||
6412 | This is similar to refers_to_regno_p in rtlanal.c except that we | |
6413 | look at equivalences for pseudos that didn't get hard registers. */ | |
6414 | ||
10015a27 | 6415 | static int |
0c20a65f AJ |
6416 | refers_to_regno_for_reload_p (unsigned int regno, unsigned int endregno, |
6417 | rtx x, rtx *loc) | |
eab89b90 | 6418 | { |
770ae6cc RK |
6419 | int i; |
6420 | unsigned int r; | |
6421 | RTX_CODE code; | |
6422 | const char *fmt; | |
eab89b90 RK |
6423 | |
6424 | if (x == 0) | |
6425 | return 0; | |
6426 | ||
6427 | repeat: | |
6428 | code = GET_CODE (x); | |
6429 | ||
6430 | switch (code) | |
6431 | { | |
6432 | case REG: | |
770ae6cc | 6433 | r = REGNO (x); |
eab89b90 | 6434 | |
4803a34a RK |
6435 | /* If this is a pseudo, a hard register must not have been allocated. |
6436 | X must therefore either be a constant or be in memory. */ | |
770ae6cc | 6437 | if (r >= FIRST_PSEUDO_REGISTER) |
4803a34a | 6438 | { |
770ae6cc | 6439 | if (reg_equiv_memory_loc[r]) |
4803a34a | 6440 | return refers_to_regno_for_reload_p (regno, endregno, |
770ae6cc | 6441 | reg_equiv_memory_loc[r], |
f4f4d0f8 | 6442 | (rtx*) 0); |
4803a34a | 6443 | |
444aea52 | 6444 | gcc_assert (reg_equiv_constant[r] || reg_equiv_invariant[r]); |
41374e13 | 6445 | return 0; |
4803a34a | 6446 | } |
eab89b90 | 6447 | |
770ae6cc RK |
6448 | return (endregno > r |
6449 | && regno < r + (r < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 6450 | ? hard_regno_nregs[r][GET_MODE (x)] |
eab89b90 RK |
6451 | : 1)); |
6452 | ||
6453 | case SUBREG: | |
6454 | /* If this is a SUBREG of a hard reg, we can see exactly which | |
6455 | registers are being modified. Otherwise, handle normally. */ | |
f8cfc6aa | 6456 | if (REG_P (SUBREG_REG (x)) |
eab89b90 RK |
6457 | && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) |
6458 | { | |
ddef6bc7 | 6459 | unsigned int inner_regno = subreg_regno (x); |
770ae6cc | 6460 | unsigned int inner_endregno |
403c659c | 6461 | = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER |
f1f4e530 | 6462 | ? subreg_nregs (x) : 1); |
eab89b90 RK |
6463 | |
6464 | return endregno > inner_regno && regno < inner_endregno; | |
6465 | } | |
6466 | break; | |
6467 | ||
6468 | case CLOBBER: | |
6469 | case SET: | |
6470 | if (&SET_DEST (x) != loc | |
6471 | /* Note setting a SUBREG counts as referring to the REG it is in for | |
6472 | a pseudo but not for hard registers since we can | |
6473 | treat each word individually. */ | |
6474 | && ((GET_CODE (SET_DEST (x)) == SUBREG | |
6475 | && loc != &SUBREG_REG (SET_DEST (x)) | |
f8cfc6aa | 6476 | && REG_P (SUBREG_REG (SET_DEST (x))) |
eab89b90 RK |
6477 | && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER |
6478 | && refers_to_regno_for_reload_p (regno, endregno, | |
6479 | SUBREG_REG (SET_DEST (x)), | |
6480 | loc)) | |
abc95ed3 | 6481 | /* If the output is an earlyclobber operand, this is |
4644aad4 | 6482 | a conflict. */ |
f8cfc6aa | 6483 | || ((!REG_P (SET_DEST (x)) |
4644aad4 | 6484 | || earlyclobber_operand_p (SET_DEST (x))) |
eab89b90 RK |
6485 | && refers_to_regno_for_reload_p (regno, endregno, |
6486 | SET_DEST (x), loc)))) | |
6487 | return 1; | |
6488 | ||
6489 | if (code == CLOBBER || loc == &SET_SRC (x)) | |
6490 | return 0; | |
6491 | x = SET_SRC (x); | |
6492 | goto repeat; | |
05d10675 | 6493 | |
e9a25f70 JL |
6494 | default: |
6495 | break; | |
eab89b90 RK |
6496 | } |
6497 | ||
6498 | /* X does not match, so try its subexpressions. */ | |
6499 | ||
6500 | fmt = GET_RTX_FORMAT (code); | |
6501 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6502 | { | |
6503 | if (fmt[i] == 'e' && loc != &XEXP (x, i)) | |
6504 | { | |
6505 | if (i == 0) | |
6506 | { | |
6507 | x = XEXP (x, 0); | |
6508 | goto repeat; | |
6509 | } | |
6510 | else | |
6511 | if (refers_to_regno_for_reload_p (regno, endregno, | |
6512 | XEXP (x, i), loc)) | |
6513 | return 1; | |
6514 | } | |
6515 | else if (fmt[i] == 'E') | |
6516 | { | |
b3694847 | 6517 | int j; |
4381f7c2 | 6518 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
eab89b90 RK |
6519 | if (loc != &XVECEXP (x, i, j) |
6520 | && refers_to_regno_for_reload_p (regno, endregno, | |
6521 | XVECEXP (x, i, j), loc)) | |
6522 | return 1; | |
6523 | } | |
6524 | } | |
6525 | return 0; | |
6526 | } | |
bfa30b22 RK |
6527 | |
6528 | /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG, | |
6529 | we check if any register number in X conflicts with the relevant register | |
6530 | numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN | |
6531 | contains a MEM (we don't bother checking for memory addresses that can't | |
05d10675 | 6532 | conflict because we expect this to be a rare case. |
bfa30b22 | 6533 | |
e0120d6e | 6534 | This function is similar to reg_overlap_mentioned_p in rtlanal.c except |
bfa30b22 RK |
6535 | that we look at equivalences for pseudos that didn't get hard registers. */ |
6536 | ||
6537 | int | |
0c20a65f | 6538 | reg_overlap_mentioned_for_reload_p (rtx x, rtx in) |
bfa30b22 RK |
6539 | { |
6540 | int regno, endregno; | |
6541 | ||
b98b49ac | 6542 | /* Overly conservative. */ |
38979c65 | 6543 | if (GET_CODE (x) == STRICT_LOW_PART |
ec8e098d | 6544 | || GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC) |
b98b49ac JL |
6545 | x = XEXP (x, 0); |
6546 | ||
6547 | /* If either argument is a constant, then modifying X can not affect IN. */ | |
6548 | if (CONSTANT_P (x) || CONSTANT_P (in)) | |
6549 | return 0; | |
481683e1 | 6550 | else if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x))) |
838f78d6 | 6551 | return refers_to_mem_for_reload_p (in); |
b98b49ac | 6552 | else if (GET_CODE (x) == SUBREG) |
bfa30b22 RK |
6553 | { |
6554 | regno = REGNO (SUBREG_REG (x)); | |
6555 | if (regno < FIRST_PSEUDO_REGISTER) | |
ddef6bc7 JJ |
6556 | regno += subreg_regno_offset (REGNO (SUBREG_REG (x)), |
6557 | GET_MODE (SUBREG_REG (x)), | |
6558 | SUBREG_BYTE (x), | |
6559 | GET_MODE (x)); | |
f1f4e530 JM |
6560 | endregno = regno + (regno < FIRST_PSEUDO_REGISTER |
6561 | ? subreg_nregs (x) : 1); | |
6562 | ||
6563 | return refers_to_regno_for_reload_p (regno, endregno, in, (rtx*) 0); | |
bfa30b22 | 6564 | } |
f8cfc6aa | 6565 | else if (REG_P (x)) |
bfa30b22 RK |
6566 | { |
6567 | regno = REGNO (x); | |
4803a34a RK |
6568 | |
6569 | /* If this is a pseudo, it must not have been assigned a hard register. | |
6570 | Therefore, it must either be in memory or be a constant. */ | |
6571 | ||
6572 | if (regno >= FIRST_PSEUDO_REGISTER) | |
6573 | { | |
6574 | if (reg_equiv_memory_loc[regno]) | |
6575 | return refers_to_mem_for_reload_p (in); | |
41374e13 NS |
6576 | gcc_assert (reg_equiv_constant[regno]); |
6577 | return 0; | |
4803a34a | 6578 | } |
f1f4e530 | 6579 | |
09e18274 | 6580 | endregno = END_HARD_REGNO (x); |
f1f4e530 JM |
6581 | |
6582 | return refers_to_regno_for_reload_p (regno, endregno, in, (rtx*) 0); | |
bfa30b22 | 6583 | } |
3c0cb5de | 6584 | else if (MEM_P (x)) |
4803a34a | 6585 | return refers_to_mem_for_reload_p (in); |
bfa30b22 RK |
6586 | else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC |
6587 | || GET_CODE (x) == CC0) | |
6588 | return reg_mentioned_p (x, in); | |
41374e13 | 6589 | else |
69f38ab9 | 6590 | { |
41374e13 NS |
6591 | gcc_assert (GET_CODE (x) == PLUS); |
6592 | ||
69f38ab9 R |
6593 | /* We actually want to know if X is mentioned somewhere inside IN. |
6594 | We must not say that (plus (sp) (const_int 124)) is in | |
6595 | (plus (sp) (const_int 64)), since that can lead to incorrect reload | |
6596 | allocation when spuriously changing a RELOAD_FOR_OUTPUT_ADDRESS | |
6597 | into a RELOAD_OTHER on behalf of another RELOAD_OTHER. */ | |
3c0cb5de | 6598 | while (MEM_P (in)) |
69f38ab9 | 6599 | in = XEXP (in, 0); |
f8cfc6aa | 6600 | if (REG_P (in)) |
69f38ab9 R |
6601 | return 0; |
6602 | else if (GET_CODE (in) == PLUS) | |
10050f74 KK |
6603 | return (rtx_equal_p (x, in) |
6604 | || reg_overlap_mentioned_for_reload_p (x, XEXP (in, 0)) | |
69f38ab9 R |
6605 | || reg_overlap_mentioned_for_reload_p (x, XEXP (in, 1))); |
6606 | else return (reg_overlap_mentioned_for_reload_p (XEXP (x, 0), in) | |
6607 | || reg_overlap_mentioned_for_reload_p (XEXP (x, 1), in)); | |
6608 | } | |
bfa30b22 | 6609 | |
f1f4e530 | 6610 | gcc_unreachable (); |
bfa30b22 | 6611 | } |
4803a34a RK |
6612 | |
6613 | /* Return nonzero if anything in X contains a MEM. Look also for pseudo | |
6614 | registers. */ | |
6615 | ||
10015a27 | 6616 | static int |
0c20a65f | 6617 | refers_to_mem_for_reload_p (rtx x) |
4803a34a | 6618 | { |
6f7d635c | 6619 | const char *fmt; |
4803a34a RK |
6620 | int i; |
6621 | ||
3c0cb5de | 6622 | if (MEM_P (x)) |
4803a34a RK |
6623 | return 1; |
6624 | ||
f8cfc6aa | 6625 | if (REG_P (x)) |
4803a34a RK |
6626 | return (REGNO (x) >= FIRST_PSEUDO_REGISTER |
6627 | && reg_equiv_memory_loc[REGNO (x)]); | |
05d10675 | 6628 | |
4803a34a RK |
6629 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
6630 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
6631 | if (fmt[i] == 'e' | |
3c0cb5de | 6632 | && (MEM_P (XEXP (x, i)) |
4803a34a RK |
6633 | || refers_to_mem_for_reload_p (XEXP (x, i)))) |
6634 | return 1; | |
05d10675 | 6635 | |
4803a34a RK |
6636 | return 0; |
6637 | } | |
eab89b90 | 6638 | \f |
eab89b90 RK |
6639 | /* Check the insns before INSN to see if there is a suitable register |
6640 | containing the same value as GOAL. | |
55d796da | 6641 | If OTHER is -1, look for a register in class RCLASS. |
eab89b90 RK |
6642 | Otherwise, just see if register number OTHER shares GOAL's value. |
6643 | ||
6644 | Return an rtx for the register found, or zero if none is found. | |
6645 | ||
6646 | If RELOAD_REG_P is (short *)1, | |
6647 | we reject any hard reg that appears in reload_reg_rtx | |
6648 | because such a hard reg is also needed coming into this insn. | |
6649 | ||
6650 | If RELOAD_REG_P is any other nonzero value, | |
6651 | it is a vector indexed by hard reg number | |
6652 | and we reject any hard reg whose element in the vector is nonnegative | |
6653 | as well as any that appears in reload_reg_rtx. | |
6654 | ||
6655 | If GOAL is zero, then GOALREG is a register number; we look | |
6656 | for an equivalent for that register. | |
6657 | ||
6658 | MODE is the machine mode of the value we want an equivalence for. | |
6659 | If GOAL is nonzero and not VOIDmode, then it must have mode MODE. | |
6660 | ||
6661 | This function is used by jump.c as well as in the reload pass. | |
6662 | ||
6663 | If GOAL is the sum of the stack pointer and a constant, we treat it | |
6664 | as if it were a constant except that sp is required to be unchanging. */ | |
6665 | ||
6666 | rtx | |
55d796da | 6667 | find_equiv_reg (rtx goal, rtx insn, enum reg_class rclass, int other, |
0c20a65f | 6668 | short *reload_reg_p, int goalreg, enum machine_mode mode) |
eab89b90 | 6669 | { |
b3694847 | 6670 | rtx p = insn; |
f55b1d97 | 6671 | rtx goaltry, valtry, value, where; |
b3694847 SS |
6672 | rtx pat; |
6673 | int regno = -1; | |
eab89b90 RK |
6674 | int valueno; |
6675 | int goal_mem = 0; | |
6676 | int goal_const = 0; | |
6677 | int goal_mem_addr_varies = 0; | |
6678 | int need_stable_sp = 0; | |
6679 | int nregs; | |
6680 | int valuenregs; | |
0bcf8261 | 6681 | int num = 0; |
eab89b90 RK |
6682 | |
6683 | if (goal == 0) | |
6684 | regno = goalreg; | |
f8cfc6aa | 6685 | else if (REG_P (goal)) |
eab89b90 | 6686 | regno = REGNO (goal); |
3c0cb5de | 6687 | else if (MEM_P (goal)) |
eab89b90 RK |
6688 | { |
6689 | enum rtx_code code = GET_CODE (XEXP (goal, 0)); | |
6690 | if (MEM_VOLATILE_P (goal)) | |
6691 | return 0; | |
3d8bf70f | 6692 | if (flag_float_store && SCALAR_FLOAT_MODE_P (GET_MODE (goal))) |
eab89b90 RK |
6693 | return 0; |
6694 | /* An address with side effects must be reexecuted. */ | |
6695 | switch (code) | |
6696 | { | |
6697 | case POST_INC: | |
6698 | case PRE_INC: | |
6699 | case POST_DEC: | |
6700 | case PRE_DEC: | |
4b983fdc RH |
6701 | case POST_MODIFY: |
6702 | case PRE_MODIFY: | |
eab89b90 | 6703 | return 0; |
e9a25f70 JL |
6704 | default: |
6705 | break; | |
eab89b90 RK |
6706 | } |
6707 | goal_mem = 1; | |
6708 | } | |
6709 | else if (CONSTANT_P (goal)) | |
6710 | goal_const = 1; | |
6711 | else if (GET_CODE (goal) == PLUS | |
6712 | && XEXP (goal, 0) == stack_pointer_rtx | |
6713 | && CONSTANT_P (XEXP (goal, 1))) | |
6714 | goal_const = need_stable_sp = 1; | |
812f2051 R |
6715 | else if (GET_CODE (goal) == PLUS |
6716 | && XEXP (goal, 0) == frame_pointer_rtx | |
6717 | && CONSTANT_P (XEXP (goal, 1))) | |
6718 | goal_const = 1; | |
eab89b90 RK |
6719 | else |
6720 | return 0; | |
6721 | ||
0bcf8261 | 6722 | num = 0; |
eab89b90 RK |
6723 | /* Scan insns back from INSN, looking for one that copies |
6724 | a value into or out of GOAL. | |
6725 | Stop and give up if we reach a label. */ | |
6726 | ||
6727 | while (1) | |
6728 | { | |
6729 | p = PREV_INSN (p); | |
0bcf8261 | 6730 | num++; |
4b4bf941 | 6731 | if (p == 0 || LABEL_P (p) |
0bcf8261 | 6732 | || num > PARAM_VALUE (PARAM_MAX_RELOAD_SEARCH_INSNS)) |
eab89b90 | 6733 | return 0; |
770ae6cc | 6734 | |
4b4bf941 | 6735 | if (NONJUMP_INSN_P (p) |
0f41302f | 6736 | /* If we don't want spill regs ... */ |
a8c9daeb RK |
6737 | && (! (reload_reg_p != 0 |
6738 | && reload_reg_p != (short *) (HOST_WIDE_INT) 1) | |
770ae6cc RK |
6739 | /* ... then ignore insns introduced by reload; they aren't |
6740 | useful and can cause results in reload_as_needed to be | |
6741 | different from what they were when calculating the need for | |
6742 | spills. If we notice an input-reload insn here, we will | |
6743 | reject it below, but it might hide a usable equivalent. | |
0e61db61 | 6744 | That makes bad code. It may even fail: perhaps no reg was |
770ae6cc RK |
6745 | spilled for this insn because it was assumed we would find |
6746 | that equivalent. */ | |
eab89b90 RK |
6747 | || INSN_UID (p) < reload_first_uid)) |
6748 | { | |
e8094962 | 6749 | rtx tem; |
eab89b90 | 6750 | pat = single_set (p); |
770ae6cc | 6751 | |
eab89b90 RK |
6752 | /* First check for something that sets some reg equal to GOAL. */ |
6753 | if (pat != 0 | |
6754 | && ((regno >= 0 | |
6755 | && true_regnum (SET_SRC (pat)) == regno | |
6756 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
6757 | || | |
6758 | (regno >= 0 | |
6759 | && true_regnum (SET_DEST (pat)) == regno | |
6760 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0) | |
6761 | || | |
6762 | (goal_const && rtx_equal_p (SET_SRC (pat), goal) | |
a5546290 R |
6763 | /* When looking for stack pointer + const, |
6764 | make sure we don't use a stack adjust. */ | |
6765 | && !reg_overlap_mentioned_for_reload_p (SET_DEST (pat), goal) | |
eab89b90 RK |
6766 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) |
6767 | || (goal_mem | |
6768 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0 | |
6769 | && rtx_renumbered_equal_p (goal, SET_SRC (pat))) | |
6770 | || (goal_mem | |
6771 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0 | |
e8094962 RK |
6772 | && rtx_renumbered_equal_p (goal, SET_DEST (pat))) |
6773 | /* If we are looking for a constant, | |
6774 | and something equivalent to that constant was copied | |
6775 | into a reg, we can use that reg. */ | |
efc9bd41 RK |
6776 | || (goal_const && REG_NOTES (p) != 0 |
6777 | && (tem = find_reg_note (p, REG_EQUIV, NULL_RTX)) | |
6778 | && ((rtx_equal_p (XEXP (tem, 0), goal) | |
6779 | && (valueno | |
6780 | = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
f8cfc6aa | 6781 | || (REG_P (SET_DEST (pat)) |
efc9bd41 | 6782 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE |
3d8bf70f | 6783 | && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0))) |
481683e1 | 6784 | && CONST_INT_P (goal) |
efc9bd41 RK |
6785 | && 0 != (goaltry |
6786 | = operand_subword (XEXP (tem, 0), 0, 0, | |
f55b1d97 | 6787 | VOIDmode)) |
efc9bd41 RK |
6788 | && rtx_equal_p (goal, goaltry) |
6789 | && (valtry | |
6790 | = operand_subword (SET_DEST (pat), 0, 0, | |
6791 | VOIDmode)) | |
6792 | && (valueno = true_regnum (valtry)) >= 0))) | |
fb3821f7 CH |
6793 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
6794 | NULL_RTX)) | |
f8cfc6aa | 6795 | && REG_P (SET_DEST (pat)) |
e8094962 | 6796 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE |
3d8bf70f | 6797 | && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0))) |
481683e1 | 6798 | && CONST_INT_P (goal) |
f55b1d97 RK |
6799 | && 0 != (goaltry = operand_subword (XEXP (tem, 0), 1, 0, |
6800 | VOIDmode)) | |
6801 | && rtx_equal_p (goal, goaltry) | |
e8094962 RK |
6802 | && (valtry |
6803 | = operand_subword (SET_DEST (pat), 1, 0, VOIDmode)) | |
95d3562b | 6804 | && (valueno = true_regnum (valtry)) >= 0))) |
0192d704 R |
6805 | { |
6806 | if (other >= 0) | |
6807 | { | |
6808 | if (valueno != other) | |
6809 | continue; | |
6810 | } | |
6811 | else if ((unsigned) valueno >= FIRST_PSEUDO_REGISTER) | |
6812 | continue; | |
55d796da | 6813 | else if (!in_hard_reg_set_p (reg_class_contents[(int) rclass], |
09e18274 RS |
6814 | mode, valueno)) |
6815 | continue; | |
0192d704 R |
6816 | value = valtry; |
6817 | where = p; | |
6818 | break; | |
6819 | } | |
eab89b90 RK |
6820 | } |
6821 | } | |
6822 | ||
6823 | /* We found a previous insn copying GOAL into a suitable other reg VALUE | |
6824 | (or copying VALUE into GOAL, if GOAL is also a register). | |
6825 | Now verify that VALUE is really valid. */ | |
6826 | ||
6827 | /* VALUENO is the register number of VALUE; a hard register. */ | |
6828 | ||
6829 | /* Don't try to re-use something that is killed in this insn. We want | |
6830 | to be able to trust REG_UNUSED notes. */ | |
efc9bd41 | 6831 | if (REG_NOTES (where) != 0 && find_reg_note (where, REG_UNUSED, value)) |
eab89b90 RK |
6832 | return 0; |
6833 | ||
6834 | /* If we propose to get the value from the stack pointer or if GOAL is | |
6835 | a MEM based on the stack pointer, we need a stable SP. */ | |
d5a1d1c7 | 6836 | if (valueno == STACK_POINTER_REGNUM || regno == STACK_POINTER_REGNUM |
bfa30b22 RK |
6837 | || (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx, |
6838 | goal))) | |
eab89b90 RK |
6839 | need_stable_sp = 1; |
6840 | ||
6841 | /* Reject VALUE if the copy-insn moved the wrong sort of datum. */ | |
6842 | if (GET_MODE (value) != mode) | |
6843 | return 0; | |
6844 | ||
6845 | /* Reject VALUE if it was loaded from GOAL | |
6846 | and is also a register that appears in the address of GOAL. */ | |
6847 | ||
bd5f6d44 | 6848 | if (goal_mem && value == SET_DEST (single_set (where)) |
09e18274 | 6849 | && refers_to_regno_for_reload_p (valueno, end_hard_regno (mode, valueno), |
f4f4d0f8 | 6850 | goal, (rtx*) 0)) |
eab89b90 RK |
6851 | return 0; |
6852 | ||
6853 | /* Reject registers that overlap GOAL. */ | |
6854 | ||
66fd46b6 JH |
6855 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER) |
6856 | nregs = hard_regno_nregs[regno][mode]; | |
6857 | else | |
6858 | nregs = 1; | |
6859 | valuenregs = hard_regno_nregs[valueno][mode]; | |
16ab191f | 6860 | |
3c241c19 GK |
6861 | if (!goal_mem && !goal_const |
6862 | && regno + nregs > valueno && regno < valueno + valuenregs) | |
6863 | return 0; | |
6864 | ||
eab89b90 RK |
6865 | /* Reject VALUE if it is one of the regs reserved for reloads. |
6866 | Reload1 knows how to reuse them anyway, and it would get | |
6867 | confused if we allocated one without its knowledge. | |
6868 | (Now that insns introduced by reload are ignored above, | |
6869 | this case shouldn't happen, but I'm not positive.) */ | |
6870 | ||
16ab191f DC |
6871 | if (reload_reg_p != 0 && reload_reg_p != (short *) (HOST_WIDE_INT) 1) |
6872 | { | |
6873 | int i; | |
6874 | for (i = 0; i < valuenregs; ++i) | |
6875 | if (reload_reg_p[valueno + i] >= 0) | |
6876 | return 0; | |
6877 | } | |
eab89b90 RK |
6878 | |
6879 | /* Reject VALUE if it is a register being used for an input reload | |
6880 | even if it is not one of those reserved. */ | |
6881 | ||
6882 | if (reload_reg_p != 0) | |
6883 | { | |
6884 | int i; | |
6885 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 6886 | if (rld[i].reg_rtx != 0 && rld[i].in) |
eab89b90 | 6887 | { |
eceef4c9 | 6888 | int regno1 = REGNO (rld[i].reg_rtx); |
66fd46b6 JH |
6889 | int nregs1 = hard_regno_nregs[regno1] |
6890 | [GET_MODE (rld[i].reg_rtx)]; | |
eab89b90 RK |
6891 | if (regno1 < valueno + valuenregs |
6892 | && regno1 + nregs1 > valueno) | |
6893 | return 0; | |
6894 | } | |
6895 | } | |
6896 | ||
6897 | if (goal_mem) | |
54b5ffe9 RS |
6898 | /* We must treat frame pointer as varying here, |
6899 | since it can vary--in a nonlocal goto as generated by expand_goto. */ | |
6900 | goal_mem_addr_varies = !CONSTANT_ADDRESS_P (XEXP (goal, 0)); | |
eab89b90 RK |
6901 | |
6902 | /* Now verify that the values of GOAL and VALUE remain unaltered | |
6903 | until INSN is reached. */ | |
6904 | ||
6905 | p = insn; | |
6906 | while (1) | |
6907 | { | |
6908 | p = PREV_INSN (p); | |
6909 | if (p == where) | |
6910 | return value; | |
6911 | ||
6912 | /* Don't trust the conversion past a function call | |
6913 | if either of the two is in a call-clobbered register, or memory. */ | |
4b4bf941 | 6914 | if (CALL_P (p)) |
aad2919f DC |
6915 | { |
6916 | int i; | |
4381f7c2 | 6917 | |
aad2919f DC |
6918 | if (goal_mem || need_stable_sp) |
6919 | return 0; | |
4381f7c2 | 6920 | |
aad2919f DC |
6921 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER) |
6922 | for (i = 0; i < nregs; ++i) | |
7e42db17 DJ |
6923 | if (call_used_regs[regno + i] |
6924 | || HARD_REGNO_CALL_PART_CLOBBERED (regno + i, mode)) | |
aad2919f DC |
6925 | return 0; |
6926 | ||
6927 | if (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER) | |
6928 | for (i = 0; i < valuenregs; ++i) | |
7e42db17 DJ |
6929 | if (call_used_regs[valueno + i] |
6930 | || HARD_REGNO_CALL_PART_CLOBBERED (valueno + i, mode)) | |
aad2919f | 6931 | return 0; |
570a98eb | 6932 | } |
41fe17ab | 6933 | |
2c3c49de | 6934 | if (INSN_P (p)) |
eab89b90 | 6935 | { |
8ec82f87 RH |
6936 | pat = PATTERN (p); |
6937 | ||
05d10675 BS |
6938 | /* Watch out for unspec_volatile, and volatile asms. */ |
6939 | if (volatile_insn_p (pat)) | |
8ec82f87 RH |
6940 | return 0; |
6941 | ||
eab89b90 RK |
6942 | /* If this insn P stores in either GOAL or VALUE, return 0. |
6943 | If GOAL is a memory ref and this insn writes memory, return 0. | |
6944 | If GOAL is a memory ref and its address is not constant, | |
6945 | and this insn P changes a register used in GOAL, return 0. */ | |
6946 | ||
0c99ec5c RH |
6947 | if (GET_CODE (pat) == COND_EXEC) |
6948 | pat = COND_EXEC_CODE (pat); | |
eab89b90 RK |
6949 | if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER) |
6950 | { | |
b3694847 | 6951 | rtx dest = SET_DEST (pat); |
eab89b90 RK |
6952 | while (GET_CODE (dest) == SUBREG |
6953 | || GET_CODE (dest) == ZERO_EXTRACT | |
eab89b90 RK |
6954 | || GET_CODE (dest) == STRICT_LOW_PART) |
6955 | dest = XEXP (dest, 0); | |
f8cfc6aa | 6956 | if (REG_P (dest)) |
eab89b90 | 6957 | { |
b3694847 | 6958 | int xregno = REGNO (dest); |
eab89b90 RK |
6959 | int xnregs; |
6960 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
66fd46b6 | 6961 | xnregs = hard_regno_nregs[xregno][GET_MODE (dest)]; |
eab89b90 RK |
6962 | else |
6963 | xnregs = 1; | |
6964 | if (xregno < regno + nregs && xregno + xnregs > regno) | |
6965 | return 0; | |
6966 | if (xregno < valueno + valuenregs | |
6967 | && xregno + xnregs > valueno) | |
6968 | return 0; | |
6969 | if (goal_mem_addr_varies | |
bfa30b22 | 6970 | && reg_overlap_mentioned_for_reload_p (dest, goal)) |
eab89b90 | 6971 | return 0; |
1b4d8b2b R |
6972 | if (xregno == STACK_POINTER_REGNUM && need_stable_sp) |
6973 | return 0; | |
eab89b90 | 6974 | } |
3c0cb5de | 6975 | else if (goal_mem && MEM_P (dest) |
eab89b90 RK |
6976 | && ! push_operand (dest, GET_MODE (dest))) |
6977 | return 0; | |
3c0cb5de | 6978 | else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER |
9fac9680 RK |
6979 | && reg_equiv_memory_loc[regno] != 0) |
6980 | return 0; | |
eab89b90 RK |
6981 | else if (need_stable_sp && push_operand (dest, GET_MODE (dest))) |
6982 | return 0; | |
6983 | } | |
6984 | else if (GET_CODE (pat) == PARALLEL) | |
6985 | { | |
b3694847 | 6986 | int i; |
eab89b90 RK |
6987 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) |
6988 | { | |
b3694847 | 6989 | rtx v1 = XVECEXP (pat, 0, i); |
0c99ec5c RH |
6990 | if (GET_CODE (v1) == COND_EXEC) |
6991 | v1 = COND_EXEC_CODE (v1); | |
eab89b90 RK |
6992 | if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER) |
6993 | { | |
b3694847 | 6994 | rtx dest = SET_DEST (v1); |
eab89b90 RK |
6995 | while (GET_CODE (dest) == SUBREG |
6996 | || GET_CODE (dest) == ZERO_EXTRACT | |
eab89b90 RK |
6997 | || GET_CODE (dest) == STRICT_LOW_PART) |
6998 | dest = XEXP (dest, 0); | |
f8cfc6aa | 6999 | if (REG_P (dest)) |
eab89b90 | 7000 | { |
b3694847 | 7001 | int xregno = REGNO (dest); |
eab89b90 RK |
7002 | int xnregs; |
7003 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
66fd46b6 | 7004 | xnregs = hard_regno_nregs[xregno][GET_MODE (dest)]; |
eab89b90 RK |
7005 | else |
7006 | xnregs = 1; | |
7007 | if (xregno < regno + nregs | |
7008 | && xregno + xnregs > regno) | |
7009 | return 0; | |
7010 | if (xregno < valueno + valuenregs | |
7011 | && xregno + xnregs > valueno) | |
7012 | return 0; | |
7013 | if (goal_mem_addr_varies | |
bfa30b22 RK |
7014 | && reg_overlap_mentioned_for_reload_p (dest, |
7015 | goal)) | |
eab89b90 | 7016 | return 0; |
930176e7 R |
7017 | if (xregno == STACK_POINTER_REGNUM && need_stable_sp) |
7018 | return 0; | |
eab89b90 | 7019 | } |
3c0cb5de | 7020 | else if (goal_mem && MEM_P (dest) |
eab89b90 RK |
7021 | && ! push_operand (dest, GET_MODE (dest))) |
7022 | return 0; | |
3c0cb5de | 7023 | else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER |
e9a25f70 JL |
7024 | && reg_equiv_memory_loc[regno] != 0) |
7025 | return 0; | |
369c7ab6 JW |
7026 | else if (need_stable_sp |
7027 | && push_operand (dest, GET_MODE (dest))) | |
7028 | return 0; | |
7029 | } | |
7030 | } | |
7031 | } | |
7032 | ||
4b4bf941 | 7033 | if (CALL_P (p) && CALL_INSN_FUNCTION_USAGE (p)) |
369c7ab6 JW |
7034 | { |
7035 | rtx link; | |
7036 | ||
7037 | for (link = CALL_INSN_FUNCTION_USAGE (p); XEXP (link, 1) != 0; | |
7038 | link = XEXP (link, 1)) | |
7039 | { | |
7040 | pat = XEXP (link, 0); | |
7041 | if (GET_CODE (pat) == CLOBBER) | |
7042 | { | |
b3694847 | 7043 | rtx dest = SET_DEST (pat); |
f8cd4126 | 7044 | |
f8cfc6aa | 7045 | if (REG_P (dest)) |
369c7ab6 | 7046 | { |
b3694847 | 7047 | int xregno = REGNO (dest); |
f8cd4126 | 7048 | int xnregs |
66fd46b6 | 7049 | = hard_regno_nregs[xregno][GET_MODE (dest)]; |
f8cd4126 | 7050 | |
369c7ab6 JW |
7051 | if (xregno < regno + nregs |
7052 | && xregno + xnregs > regno) | |
7053 | return 0; | |
f8cd4126 | 7054 | else if (xregno < valueno + valuenregs |
4381f7c2 | 7055 | && xregno + xnregs > valueno) |
369c7ab6 | 7056 | return 0; |
f8cd4126 RK |
7057 | else if (goal_mem_addr_varies |
7058 | && reg_overlap_mentioned_for_reload_p (dest, | |
369c7ab6 JW |
7059 | goal)) |
7060 | return 0; | |
7061 | } | |
f8cd4126 | 7062 | |
3c0cb5de | 7063 | else if (goal_mem && MEM_P (dest) |
369c7ab6 JW |
7064 | && ! push_operand (dest, GET_MODE (dest))) |
7065 | return 0; | |
eab89b90 RK |
7066 | else if (need_stable_sp |
7067 | && push_operand (dest, GET_MODE (dest))) | |
7068 | return 0; | |
7069 | } | |
7070 | } | |
7071 | } | |
7072 | ||
7073 | #ifdef AUTO_INC_DEC | |
7074 | /* If this insn auto-increments or auto-decrements | |
7075 | either regno or valueno, return 0 now. | |
7076 | If GOAL is a memory ref and its address is not constant, | |
7077 | and this insn P increments a register used in GOAL, return 0. */ | |
7078 | { | |
b3694847 | 7079 | rtx link; |
eab89b90 RK |
7080 | |
7081 | for (link = REG_NOTES (p); link; link = XEXP (link, 1)) | |
7082 | if (REG_NOTE_KIND (link) == REG_INC | |
f8cfc6aa | 7083 | && REG_P (XEXP (link, 0))) |
eab89b90 | 7084 | { |
b3694847 | 7085 | int incno = REGNO (XEXP (link, 0)); |
eab89b90 RK |
7086 | if (incno < regno + nregs && incno >= regno) |
7087 | return 0; | |
7088 | if (incno < valueno + valuenregs && incno >= valueno) | |
7089 | return 0; | |
7090 | if (goal_mem_addr_varies | |
bfa30b22 RK |
7091 | && reg_overlap_mentioned_for_reload_p (XEXP (link, 0), |
7092 | goal)) | |
eab89b90 RK |
7093 | return 0; |
7094 | } | |
7095 | } | |
7096 | #endif | |
7097 | } | |
7098 | } | |
7099 | } | |
7100 | \f | |
7101 | /* Find a place where INCED appears in an increment or decrement operator | |
7102 | within X, and return the amount INCED is incremented or decremented by. | |
7103 | The value is always positive. */ | |
7104 | ||
7105 | static int | |
0c20a65f | 7106 | find_inc_amount (rtx x, rtx inced) |
eab89b90 | 7107 | { |
b3694847 SS |
7108 | enum rtx_code code = GET_CODE (x); |
7109 | const char *fmt; | |
7110 | int i; | |
eab89b90 RK |
7111 | |
7112 | if (code == MEM) | |
7113 | { | |
b3694847 | 7114 | rtx addr = XEXP (x, 0); |
eab89b90 RK |
7115 | if ((GET_CODE (addr) == PRE_DEC |
7116 | || GET_CODE (addr) == POST_DEC | |
7117 | || GET_CODE (addr) == PRE_INC | |
7118 | || GET_CODE (addr) == POST_INC) | |
7119 | && XEXP (addr, 0) == inced) | |
7120 | return GET_MODE_SIZE (GET_MODE (x)); | |
4b983fdc RH |
7121 | else if ((GET_CODE (addr) == PRE_MODIFY |
7122 | || GET_CODE (addr) == POST_MODIFY) | |
7123 | && GET_CODE (XEXP (addr, 1)) == PLUS | |
7124 | && XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0) | |
7125 | && XEXP (addr, 0) == inced | |
481683e1 | 7126 | && CONST_INT_P (XEXP (XEXP (addr, 1), 1))) |
4381f7c2 KH |
7127 | { |
7128 | i = INTVAL (XEXP (XEXP (addr, 1), 1)); | |
7129 | return i < 0 ? -i : i; | |
7130 | } | |
7131 | } | |
eab89b90 RK |
7132 | |
7133 | fmt = GET_RTX_FORMAT (code); | |
7134 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7135 | { | |
7136 | if (fmt[i] == 'e') | |
7137 | { | |
b3694847 | 7138 | int tem = find_inc_amount (XEXP (x, i), inced); |
eab89b90 RK |
7139 | if (tem != 0) |
7140 | return tem; | |
7141 | } | |
7142 | if (fmt[i] == 'E') | |
7143 | { | |
b3694847 | 7144 | int j; |
eab89b90 RK |
7145 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
7146 | { | |
b3694847 | 7147 | int tem = find_inc_amount (XVECEXP (x, i, j), inced); |
eab89b90 RK |
7148 | if (tem != 0) |
7149 | return tem; | |
7150 | } | |
7151 | } | |
7152 | } | |
7153 | ||
7154 | return 0; | |
7155 | } | |
7156 | \f | |
d0236c3b DN |
7157 | /* Return 1 if registers from REGNO to ENDREGNO are the subjects of a |
7158 | REG_INC note in insn INSN. REGNO must refer to a hard register. */ | |
7159 | ||
7160 | #ifdef AUTO_INC_DEC | |
7161 | static int | |
7162 | reg_inc_found_and_valid_p (unsigned int regno, unsigned int endregno, | |
7163 | rtx insn) | |
7164 | { | |
7165 | rtx link; | |
7166 | ||
7167 | gcc_assert (insn); | |
7168 | ||
7169 | if (! INSN_P (insn)) | |
7170 | return 0; | |
7171 | ||
7172 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
7173 | if (REG_NOTE_KIND (link) == REG_INC) | |
7174 | { | |
7175 | unsigned int test = (int) REGNO (XEXP (link, 0)); | |
7176 | if (test >= regno && test < endregno) | |
7177 | return 1; | |
7178 | } | |
7179 | return 0; | |
7180 | } | |
7181 | #else | |
7182 | ||
7183 | #define reg_inc_found_and_valid_p(regno,endregno,insn) 0 | |
7184 | ||
7185 | #endif | |
7186 | ||
9532e31f | 7187 | /* Return 1 if register REGNO is the subject of a clobber in insn INSN. |
d0236c3b DN |
7188 | If SETS is 1, also consider SETs. If SETS is 2, enable checking |
7189 | REG_INC. REGNO must refer to a hard register. */ | |
eab89b90 RK |
7190 | |
7191 | int | |
0c20a65f AJ |
7192 | regno_clobbered_p (unsigned int regno, rtx insn, enum machine_mode mode, |
7193 | int sets) | |
eab89b90 | 7194 | { |
5b804e8a RS |
7195 | unsigned int nregs, endregno; |
7196 | ||
7197 | /* regno must be a hard register. */ | |
7198 | gcc_assert (regno < FIRST_PSEUDO_REGISTER); | |
7199 | ||
7200 | nregs = hard_regno_nregs[regno][mode]; | |
7201 | endregno = regno + nregs; | |
8441bc30 | 7202 | |
9532e31f | 7203 | if ((GET_CODE (PATTERN (insn)) == CLOBBER |
d0236c3b | 7204 | || (sets == 1 && GET_CODE (PATTERN (insn)) == SET)) |
f8cfc6aa | 7205 | && REG_P (XEXP (PATTERN (insn), 0))) |
8441bc30 | 7206 | { |
ae0ed63a | 7207 | unsigned int test = REGNO (XEXP (PATTERN (insn), 0)); |
8441bc30 | 7208 | |
e695931e | 7209 | return test >= regno && test < endregno; |
8441bc30 | 7210 | } |
eab89b90 | 7211 | |
d0236c3b DN |
7212 | if (sets == 2 && reg_inc_found_and_valid_p (regno, endregno, insn)) |
7213 | return 1; | |
7214 | ||
eab89b90 RK |
7215 | if (GET_CODE (PATTERN (insn)) == PARALLEL) |
7216 | { | |
7217 | int i = XVECLEN (PATTERN (insn), 0) - 1; | |
7218 | ||
7219 | for (; i >= 0; i--) | |
7220 | { | |
7221 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
9532e31f | 7222 | if ((GET_CODE (elt) == CLOBBER |
d0236c3b | 7223 | || (sets == 1 && GET_CODE (PATTERN (insn)) == SET)) |
f8cfc6aa | 7224 | && REG_P (XEXP (elt, 0))) |
8441bc30 | 7225 | { |
ae0ed63a | 7226 | unsigned int test = REGNO (XEXP (elt, 0)); |
a6a2274a | 7227 | |
e695931e | 7228 | if (test >= regno && test < endregno) |
8441bc30 BS |
7229 | return 1; |
7230 | } | |
d0236c3b DN |
7231 | if (sets == 2 |
7232 | && reg_inc_found_and_valid_p (regno, endregno, elt)) | |
7233 | return 1; | |
eab89b90 RK |
7234 | } |
7235 | } | |
7236 | ||
7237 | return 0; | |
7238 | } | |
10bcde0d | 7239 | |
f12448c8 AO |
7240 | /* Find the low part, with mode MODE, of a hard regno RELOADREG. */ |
7241 | rtx | |
0c20a65f | 7242 | reload_adjust_reg_for_mode (rtx reloadreg, enum machine_mode mode) |
f12448c8 AO |
7243 | { |
7244 | int regno; | |
7245 | ||
7246 | if (GET_MODE (reloadreg) == mode) | |
7247 | return reloadreg; | |
7248 | ||
7249 | regno = REGNO (reloadreg); | |
7250 | ||
7251 | if (WORDS_BIG_ENDIAN) | |
66fd46b6 JH |
7252 | regno += (int) hard_regno_nregs[regno][GET_MODE (reloadreg)] |
7253 | - (int) hard_regno_nregs[regno][mode]; | |
f12448c8 AO |
7254 | |
7255 | return gen_rtx_REG (mode, regno); | |
7256 | } | |
7257 | ||
27c38fbe | 7258 | static const char *const reload_when_needed_name[] = |
10bcde0d | 7259 | { |
05d10675 BS |
7260 | "RELOAD_FOR_INPUT", |
7261 | "RELOAD_FOR_OUTPUT", | |
10bcde0d | 7262 | "RELOAD_FOR_INSN", |
47c8cf91 ILT |
7263 | "RELOAD_FOR_INPUT_ADDRESS", |
7264 | "RELOAD_FOR_INPADDR_ADDRESS", | |
10bcde0d | 7265 | "RELOAD_FOR_OUTPUT_ADDRESS", |
47c8cf91 | 7266 | "RELOAD_FOR_OUTADDR_ADDRESS", |
05d10675 | 7267 | "RELOAD_FOR_OPERAND_ADDRESS", |
10bcde0d | 7268 | "RELOAD_FOR_OPADDR_ADDR", |
05d10675 | 7269 | "RELOAD_OTHER", |
10bcde0d RK |
7270 | "RELOAD_FOR_OTHER_ADDRESS" |
7271 | }; | |
7272 | ||
b8fb2d72 | 7273 | /* These functions are used to print the variables set by 'find_reloads' */ |
10bcde0d RK |
7274 | |
7275 | void | |
0c20a65f | 7276 | debug_reload_to_stream (FILE *f) |
10bcde0d RK |
7277 | { |
7278 | int r; | |
6f7d635c | 7279 | const char *prefix; |
10bcde0d | 7280 | |
b8fb2d72 CI |
7281 | if (! f) |
7282 | f = stderr; | |
10bcde0d RK |
7283 | for (r = 0; r < n_reloads; r++) |
7284 | { | |
b8fb2d72 | 7285 | fprintf (f, "Reload %d: ", r); |
10bcde0d | 7286 | |
eceef4c9 | 7287 | if (rld[r].in != 0) |
10bcde0d | 7288 | { |
b8fb2d72 | 7289 | fprintf (f, "reload_in (%s) = ", |
eceef4c9 BS |
7290 | GET_MODE_NAME (rld[r].inmode)); |
7291 | print_inline_rtx (f, rld[r].in, 24); | |
b8fb2d72 | 7292 | fprintf (f, "\n\t"); |
10bcde0d RK |
7293 | } |
7294 | ||
eceef4c9 | 7295 | if (rld[r].out != 0) |
10bcde0d | 7296 | { |
b8fb2d72 | 7297 | fprintf (f, "reload_out (%s) = ", |
eceef4c9 BS |
7298 | GET_MODE_NAME (rld[r].outmode)); |
7299 | print_inline_rtx (f, rld[r].out, 24); | |
b8fb2d72 | 7300 | fprintf (f, "\n\t"); |
10bcde0d RK |
7301 | } |
7302 | ||
48c54229 | 7303 | fprintf (f, "%s, ", reg_class_names[(int) rld[r].rclass]); |
10bcde0d | 7304 | |
b8fb2d72 | 7305 | fprintf (f, "%s (opnum = %d)", |
eceef4c9 BS |
7306 | reload_when_needed_name[(int) rld[r].when_needed], |
7307 | rld[r].opnum); | |
10bcde0d | 7308 | |
eceef4c9 | 7309 | if (rld[r].optional) |
b8fb2d72 | 7310 | fprintf (f, ", optional"); |
10bcde0d | 7311 | |
eceef4c9 | 7312 | if (rld[r].nongroup) |
b2ee8ec2 | 7313 | fprintf (f, ", nongroup"); |
f5963e61 | 7314 | |
eceef4c9 BS |
7315 | if (rld[r].inc != 0) |
7316 | fprintf (f, ", inc by %d", rld[r].inc); | |
10bcde0d | 7317 | |
eceef4c9 | 7318 | if (rld[r].nocombine) |
b8fb2d72 | 7319 | fprintf (f, ", can't combine"); |
10bcde0d | 7320 | |
eceef4c9 | 7321 | if (rld[r].secondary_p) |
b8fb2d72 | 7322 | fprintf (f, ", secondary_reload_p"); |
10bcde0d | 7323 | |
eceef4c9 | 7324 | if (rld[r].in_reg != 0) |
10bcde0d | 7325 | { |
b8fb2d72 | 7326 | fprintf (f, "\n\treload_in_reg: "); |
eceef4c9 | 7327 | print_inline_rtx (f, rld[r].in_reg, 24); |
10bcde0d RK |
7328 | } |
7329 | ||
eceef4c9 | 7330 | if (rld[r].out_reg != 0) |
cb2afeb3 R |
7331 | { |
7332 | fprintf (f, "\n\treload_out_reg: "); | |
eceef4c9 | 7333 | print_inline_rtx (f, rld[r].out_reg, 24); |
cb2afeb3 R |
7334 | } |
7335 | ||
eceef4c9 | 7336 | if (rld[r].reg_rtx != 0) |
10bcde0d | 7337 | { |
b8fb2d72 | 7338 | fprintf (f, "\n\treload_reg_rtx: "); |
eceef4c9 | 7339 | print_inline_rtx (f, rld[r].reg_rtx, 24); |
10bcde0d RK |
7340 | } |
7341 | ||
505923a0 | 7342 | prefix = "\n\t"; |
eceef4c9 | 7343 | if (rld[r].secondary_in_reload != -1) |
10bcde0d | 7344 | { |
b8fb2d72 | 7345 | fprintf (f, "%ssecondary_in_reload = %d", |
eceef4c9 | 7346 | prefix, rld[r].secondary_in_reload); |
505923a0 | 7347 | prefix = ", "; |
10bcde0d RK |
7348 | } |
7349 | ||
eceef4c9 | 7350 | if (rld[r].secondary_out_reload != -1) |
b8fb2d72 | 7351 | fprintf (f, "%ssecondary_out_reload = %d\n", |
eceef4c9 | 7352 | prefix, rld[r].secondary_out_reload); |
10bcde0d | 7353 | |
505923a0 | 7354 | prefix = "\n\t"; |
eceef4c9 | 7355 | if (rld[r].secondary_in_icode != CODE_FOR_nothing) |
10bcde0d | 7356 | { |
b2ee8ec2 | 7357 | fprintf (f, "%ssecondary_in_icode = %s", prefix, |
eceef4c9 | 7358 | insn_data[rld[r].secondary_in_icode].name); |
505923a0 | 7359 | prefix = ", "; |
10bcde0d RK |
7360 | } |
7361 | ||
eceef4c9 | 7362 | if (rld[r].secondary_out_icode != CODE_FOR_nothing) |
b2ee8ec2 | 7363 | fprintf (f, "%ssecondary_out_icode = %s", prefix, |
eceef4c9 | 7364 | insn_data[rld[r].secondary_out_icode].name); |
10bcde0d | 7365 | |
b8fb2d72 | 7366 | fprintf (f, "\n"); |
10bcde0d | 7367 | } |
10bcde0d | 7368 | } |
b8fb2d72 CI |
7369 | |
7370 | void | |
0c20a65f | 7371 | debug_reload (void) |
b8fb2d72 CI |
7372 | { |
7373 | debug_reload_to_stream (stderr); | |
7374 | } |