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Commit | Line | Data |
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eab89b90 | 1 | /* Search an insn for pseudo regs that must be in hard regs and are not. |
af841dbd | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
6fb5fa3c DB |
3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
4 | Free Software Foundation, Inc. | |
eab89b90 | 5 | |
1322177d | 6 | This file is part of GCC. |
eab89b90 | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
eab89b90 | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
eab89b90 RK |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
eab89b90 | 21 | |
eab89b90 RK |
22 | /* This file contains subroutines used only from the file reload1.c. |
23 | It knows how to scan one insn for operands and values | |
24 | that need to be copied into registers to make valid code. | |
25 | It also finds other operands and values which are valid | |
26 | but for which equivalent values in registers exist and | |
27 | ought to be used instead. | |
28 | ||
29 | Before processing the first insn of the function, call `init_reload'. | |
965ccc5a | 30 | init_reload actually has to be called earlier anyway. |
eab89b90 RK |
31 | |
32 | To scan an insn, call `find_reloads'. This does two things: | |
33 | 1. sets up tables describing which values must be reloaded | |
34 | for this insn, and what kind of hard regs they must be reloaded into; | |
35 | 2. optionally record the locations where those values appear in | |
36 | the data, so they can be replaced properly later. | |
37 | This is done only if the second arg to `find_reloads' is nonzero. | |
38 | ||
39 | The third arg to `find_reloads' specifies the number of levels | |
40 | of indirect addressing supported by the machine. If it is zero, | |
41 | indirect addressing is not valid. If it is one, (MEM (REG n)) | |
42 | is valid even if (REG n) did not get a hard register; if it is two, | |
43 | (MEM (MEM (REG n))) is also valid even if (REG n) did not get a | |
44 | hard register, and similarly for higher values. | |
45 | ||
46 | Then you must choose the hard regs to reload those pseudo regs into, | |
47 | and generate appropriate load insns before this insn and perhaps | |
48 | also store insns after this insn. Set up the array `reload_reg_rtx' | |
49 | to contain the REG rtx's for the registers you used. In some | |
50 | cases `find_reloads' will return a nonzero value in `reload_reg_rtx' | |
51 | for certain reloads. Then that tells you which register to use, | |
52 | so you do not need to allocate one. But you still do need to add extra | |
53 | instructions to copy the value into and out of that register. | |
54 | ||
55 | Finally you must call `subst_reloads' to substitute the reload reg rtx's | |
56 | into the locations already recorded. | |
57 | ||
58 | NOTE SIDE EFFECTS: | |
59 | ||
60 | find_reloads can alter the operands of the instruction it is called on. | |
61 | ||
62 | 1. Two operands of any sort may be interchanged, if they are in a | |
63 | commutative instruction. | |
64 | This happens only if find_reloads thinks the instruction will compile | |
65 | better that way. | |
66 | ||
67 | 2. Pseudo-registers that are equivalent to constants are replaced | |
68 | with those constants if they are not in hard registers. | |
69 | ||
70 | 1 happens every time find_reloads is called. | |
71 | 2 happens only when REPLACE is 1, which is only when | |
72 | actually doing the reloads, not when just counting them. | |
73 | ||
eab89b90 RK |
74 | Using a reload register for several reloads in one insn: |
75 | ||
76 | When an insn has reloads, it is considered as having three parts: | |
77 | the input reloads, the insn itself after reloading, and the output reloads. | |
78 | Reloads of values used in memory addresses are often needed for only one part. | |
79 | ||
80 | When this is so, reload_when_needed records which part needs the reload. | |
81 | Two reloads for different parts of the insn can share the same reload | |
82 | register. | |
83 | ||
84 | When a reload is used for addresses in multiple parts, or when it is | |
85 | an ordinary operand, it is classified as RELOAD_OTHER, and cannot share | |
86 | a register with any other reload. */ | |
87 | ||
88 | #define REG_OK_STRICT | |
89 | ||
0fa4cb7d SE |
90 | /* We do not enable this with ENABLE_CHECKING, since it is awfully slow. */ |
91 | #undef DEBUG_RELOAD | |
92 | ||
eab89b90 | 93 | #include "config.h" |
670ee920 | 94 | #include "system.h" |
4977bab6 ZW |
95 | #include "coretypes.h" |
96 | #include "tm.h" | |
eab89b90 | 97 | #include "rtl.h" |
6baf1cc8 | 98 | #include "tm_p.h" |
eab89b90 | 99 | #include "insn-config.h" |
e78d8e51 ZW |
100 | #include "expr.h" |
101 | #include "optabs.h" | |
eab89b90 RK |
102 | #include "recog.h" |
103 | #include "reload.h" | |
104 | #include "regs.h" | |
c4963a0a | 105 | #include "addresses.h" |
eab89b90 RK |
106 | #include "hard-reg-set.h" |
107 | #include "flags.h" | |
108 | #include "real.h" | |
8a840ac9 | 109 | #include "output.h" |
49ad7cfa | 110 | #include "function.h" |
10f0ad3d | 111 | #include "toplev.h" |
0bcf8261 | 112 | #include "params.h" |
34208acf | 113 | #include "target.h" |
6fb5fa3c | 114 | #include "df.h" |
eab89b90 | 115 | |
34208acf AO |
116 | /* True if X is a constant that can be forced into the constant pool. */ |
117 | #define CONST_POOL_OK_P(X) \ | |
118 | (CONSTANT_P (X) \ | |
119 | && GET_CODE (X) != HIGH \ | |
120 | && !targetm.cannot_force_const_mem (X)) | |
e9840398 AO |
121 | |
122 | /* True if C is a non-empty register class that has too few registers | |
123 | to be safely used as a reload target class. */ | |
124 | #define SMALL_REGISTER_CLASS_P(C) \ | |
125 | (reg_class_size [(C)] == 1 \ | |
126 | || (reg_class_size [(C)] >= 1 && CLASS_LIKELY_SPILLED_P (C))) | |
127 | ||
eab89b90 | 128 | \f |
eceef4c9 BS |
129 | /* All reloads of the current insn are recorded here. See reload.h for |
130 | comments. */ | |
eab89b90 | 131 | int n_reloads; |
eceef4c9 | 132 | struct reload rld[MAX_RELOADS]; |
eab89b90 RK |
133 | |
134 | /* All the "earlyclobber" operands of the current insn | |
135 | are recorded here. */ | |
136 | int n_earlyclobbers; | |
137 | rtx reload_earlyclobbers[MAX_RECOG_OPERANDS]; | |
138 | ||
a8c9daeb RK |
139 | int reload_n_operands; |
140 | ||
eab89b90 RK |
141 | /* Replacing reloads. |
142 | ||
143 | If `replace_reloads' is nonzero, then as each reload is recorded | |
144 | an entry is made for it in the table `replacements'. | |
145 | Then later `subst_reloads' can look through that table and | |
146 | perform all the replacements needed. */ | |
147 | ||
148 | /* Nonzero means record the places to replace. */ | |
149 | static int replace_reloads; | |
150 | ||
151 | /* Each replacement is recorded with a structure like this. */ | |
152 | struct replacement | |
153 | { | |
154 | rtx *where; /* Location to store in */ | |
155 | rtx *subreg_loc; /* Location of SUBREG if WHERE is inside | |
156 | a SUBREG; 0 otherwise. */ | |
157 | int what; /* which reload this is for */ | |
158 | enum machine_mode mode; /* mode it must have */ | |
159 | }; | |
160 | ||
161 | static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; | |
162 | ||
163 | /* Number of replacements currently recorded. */ | |
164 | static int n_replacements; | |
165 | ||
a8c9daeb RK |
166 | /* Used to track what is modified by an operand. */ |
167 | struct decomposition | |
168 | { | |
0f41302f MS |
169 | int reg_flag; /* Nonzero if referencing a register. */ |
170 | int safe; /* Nonzero if this can't conflict with anything. */ | |
171 | rtx base; /* Base address for MEM. */ | |
172 | HOST_WIDE_INT start; /* Starting offset or register number. */ | |
2a6d5ce0 | 173 | HOST_WIDE_INT end; /* Ending offset or register number. */ |
a8c9daeb RK |
174 | }; |
175 | ||
0dadecf6 RK |
176 | #ifdef SECONDARY_MEMORY_NEEDED |
177 | ||
178 | /* Save MEMs needed to copy from one class of registers to another. One MEM | |
05d10675 | 179 | is used per mode, but normally only one or two modes are ever used. |
0dadecf6 | 180 | |
05d10675 | 181 | We keep two versions, before and after register elimination. The one |
a8c9daeb RK |
182 | after register elimination is record separately for each operand. This |
183 | is done in case the address is not valid to be sure that we separately | |
184 | reload each. */ | |
0dadecf6 RK |
185 | |
186 | static rtx secondary_memlocs[NUM_MACHINE_MODES]; | |
77545d45 | 187 | static rtx secondary_memlocs_elim[NUM_MACHINE_MODES][MAX_RECOG_OPERANDS]; |
048b0d2e | 188 | static int secondary_memlocs_elim_used = 0; |
0dadecf6 RK |
189 | #endif |
190 | ||
eab89b90 RK |
191 | /* The instruction we are doing reloads for; |
192 | so we can test whether a register dies in it. */ | |
193 | static rtx this_insn; | |
194 | ||
195 | /* Nonzero if this instruction is a user-specified asm with operands. */ | |
196 | static int this_insn_is_asm; | |
197 | ||
198 | /* If hard_regs_live_known is nonzero, | |
199 | we can tell which hard regs are currently live, | |
200 | at least enough to succeed in choosing dummy reloads. */ | |
201 | static int hard_regs_live_known; | |
202 | ||
203 | /* Indexed by hard reg number, | |
956d6950 | 204 | element is nonnegative if hard reg has been spilled. |
eab89b90 RK |
205 | This vector is passed to `find_reloads' as an argument |
206 | and is not changed here. */ | |
207 | static short *static_reload_reg_p; | |
208 | ||
209 | /* Set to 1 in subst_reg_equivs if it changes anything. */ | |
210 | static int subst_reg_equivs_changed; | |
211 | ||
212 | /* On return from push_reload, holds the reload-number for the OUT | |
213 | operand, which can be different for that from the input operand. */ | |
214 | static int output_reloadnum; | |
215 | ||
9ec7078b RK |
216 | /* Compare two RTX's. */ |
217 | #define MATCHES(x, y) \ | |
f8cfc6aa JQ |
218 | (x == y || (x != 0 && (REG_P (x) \ |
219 | ? REG_P (y) && REGNO (x) == REGNO (y) \ | |
9ec7078b RK |
220 | : rtx_equal_p (x, y) && ! side_effects_p (x)))) |
221 | ||
222 | /* Indicates if two reloads purposes are for similar enough things that we | |
223 | can merge their reloads. */ | |
224 | #define MERGABLE_RELOADS(when1, when2, op1, op2) \ | |
225 | ((when1) == RELOAD_OTHER || (when2) == RELOAD_OTHER \ | |
226 | || ((when1) == (when2) && (op1) == (op2)) \ | |
227 | || ((when1) == RELOAD_FOR_INPUT && (when2) == RELOAD_FOR_INPUT) \ | |
228 | || ((when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
229 | && (when2) == RELOAD_FOR_OPERAND_ADDRESS) \ | |
230 | || ((when1) == RELOAD_FOR_OTHER_ADDRESS \ | |
231 | && (when2) == RELOAD_FOR_OTHER_ADDRESS)) | |
232 | ||
233 | /* Nonzero if these two reload purposes produce RELOAD_OTHER when merged. */ | |
234 | #define MERGE_TO_OTHER(when1, when2, op1, op2) \ | |
235 | ((when1) != (when2) \ | |
236 | || ! ((op1) == (op2) \ | |
237 | || (when1) == RELOAD_FOR_INPUT \ | |
238 | || (when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
239 | || (when1) == RELOAD_FOR_OTHER_ADDRESS)) | |
240 | ||
47c8cf91 ILT |
241 | /* If we are going to reload an address, compute the reload type to |
242 | use. */ | |
243 | #define ADDR_TYPE(type) \ | |
244 | ((type) == RELOAD_FOR_INPUT_ADDRESS \ | |
245 | ? RELOAD_FOR_INPADDR_ADDRESS \ | |
246 | : ((type) == RELOAD_FOR_OUTPUT_ADDRESS \ | |
247 | ? RELOAD_FOR_OUTADDR_ADDRESS \ | |
248 | : (type))) | |
249 | ||
0c20a65f AJ |
250 | static int push_secondary_reload (int, rtx, int, int, enum reg_class, |
251 | enum machine_mode, enum reload_type, | |
8a99f6f9 | 252 | enum insn_code *, secondary_reload_info *); |
e11ab33b DD |
253 | static enum reg_class find_valid_class (enum machine_mode, enum machine_mode, |
254 | int, unsigned int); | |
0c20a65f AJ |
255 | static int reload_inner_reg_of_subreg (rtx, enum machine_mode, int); |
256 | static void push_replacement (rtx *, int, enum machine_mode); | |
257 | static void dup_replacements (rtx *, rtx *); | |
258 | static void combine_reloads (void); | |
259 | static int find_reusable_reload (rtx *, rtx, enum reg_class, | |
260 | enum reload_type, int, int); | |
261 | static rtx find_dummy_reload (rtx, rtx, rtx *, rtx *, enum machine_mode, | |
262 | enum machine_mode, enum reg_class, int, int); | |
263 | static int hard_reg_set_here_p (unsigned int, unsigned int, rtx); | |
264 | static struct decomposition decompose (rtx); | |
265 | static int immune_p (rtx, rtx, struct decomposition); | |
266 | static int alternative_allows_memconst (const char *, int); | |
267 | static rtx find_reloads_toplev (rtx, int, enum reload_type, int, int, rtx, | |
268 | int *); | |
269 | static rtx make_memloc (rtx, int); | |
270 | static int maybe_memory_address_p (enum machine_mode, rtx, rtx *); | |
271 | static int find_reloads_address (enum machine_mode, rtx *, rtx, rtx *, | |
272 | int, enum reload_type, int, rtx); | |
273 | static rtx subst_reg_equivs (rtx, rtx); | |
274 | static rtx subst_indexed_address (rtx); | |
275 | static void update_auto_inc_notes (rtx, int, int); | |
c4963a0a BS |
276 | static int find_reloads_address_1 (enum machine_mode, rtx, int, |
277 | enum rtx_code, enum rtx_code, rtx *, | |
0c20a65f AJ |
278 | int, enum reload_type,int, rtx); |
279 | static void find_reloads_address_part (rtx, rtx *, enum reg_class, | |
280 | enum machine_mode, int, | |
281 | enum reload_type, int); | |
282 | static rtx find_reloads_subreg_address (rtx, int, int, enum reload_type, | |
283 | int, rtx); | |
284 | static void copy_replacements_1 (rtx *, rtx *, int); | |
285 | static int find_inc_amount (rtx, rtx); | |
10015a27 KH |
286 | static int refers_to_mem_for_reload_p (rtx); |
287 | static int refers_to_regno_for_reload_p (unsigned int, unsigned int, | |
288 | rtx, rtx *); | |
3f1e3e70 AO |
289 | |
290 | /* Add NEW to reg_equiv_alt_mem_list[REGNO] if it's not present in the | |
291 | list yet. */ | |
292 | ||
293 | static void | |
294 | push_reg_equiv_alt_mem (int regno, rtx mem) | |
295 | { | |
296 | rtx it; | |
297 | ||
298 | for (it = reg_equiv_alt_mem_list [regno]; it; it = XEXP (it, 1)) | |
299 | if (rtx_equal_p (XEXP (it, 0), mem)) | |
300 | return; | |
301 | ||
302 | reg_equiv_alt_mem_list [regno] | |
303 | = alloc_EXPR_LIST (REG_EQUIV, mem, | |
304 | reg_equiv_alt_mem_list [regno]); | |
305 | } | |
eab89b90 | 306 | \f |
eab89b90 | 307 | /* Determine if any secondary reloads are needed for loading (if IN_P is |
40f03658 | 308 | nonzero) or storing (if IN_P is zero) X to or from a reload register of |
9ec7078b RK |
309 | register class RELOAD_CLASS in mode RELOAD_MODE. If secondary reloads |
310 | are needed, push them. | |
311 | ||
312 | Return the reload number of the secondary reload we made, or -1 if | |
313 | we didn't need one. *PICODE is set to the insn_code to use if we do | |
314 | need a secondary reload. */ | |
315 | ||
316 | static int | |
0c20a65f AJ |
317 | push_secondary_reload (int in_p, rtx x, int opnum, int optional, |
318 | enum reg_class reload_class, | |
319 | enum machine_mode reload_mode, enum reload_type type, | |
8a99f6f9 | 320 | enum insn_code *picode, secondary_reload_info *prev_sri) |
eab89b90 RK |
321 | { |
322 | enum reg_class class = NO_REGS; | |
8a99f6f9 | 323 | enum reg_class scratch_class; |
eab89b90 RK |
324 | enum machine_mode mode = reload_mode; |
325 | enum insn_code icode = CODE_FOR_nothing; | |
65b4c337 | 326 | enum insn_code t_icode = CODE_FOR_nothing; |
d94d2abc | 327 | enum reload_type secondary_type; |
9ec7078b | 328 | int s_reload, t_reload = -1; |
8a99f6f9 R |
329 | const char *scratch_constraint; |
330 | char letter; | |
331 | secondary_reload_info sri; | |
9ec7078b | 332 | |
47c8cf91 ILT |
333 | if (type == RELOAD_FOR_INPUT_ADDRESS |
334 | || type == RELOAD_FOR_OUTPUT_ADDRESS | |
335 | || type == RELOAD_FOR_INPADDR_ADDRESS | |
336 | || type == RELOAD_FOR_OUTADDR_ADDRESS) | |
d94d2abc RK |
337 | secondary_type = type; |
338 | else | |
339 | secondary_type = in_p ? RELOAD_FOR_INPUT_ADDRESS : RELOAD_FOR_OUTPUT_ADDRESS; | |
340 | ||
9ec7078b | 341 | *picode = CODE_FOR_nothing; |
eab89b90 | 342 | |
67340b03 RK |
343 | /* If X is a paradoxical SUBREG, use the inner value to determine both the |
344 | mode and object being reloaded. */ | |
345 | if (GET_CODE (x) == SUBREG | |
346 | && (GET_MODE_SIZE (GET_MODE (x)) | |
347 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
348 | { | |
349 | x = SUBREG_REG (x); | |
350 | reload_mode = GET_MODE (x); | |
351 | } | |
352 | ||
d45cf215 RS |
353 | /* If X is a pseudo-register that has an equivalent MEM (actually, if it |
354 | is still a pseudo-register by now, it *must* have an equivalent MEM | |
355 | but we don't want to assume that), use that equivalent when seeing if | |
356 | a secondary reload is needed since whether or not a reload is needed | |
357 | might be sensitive to the form of the MEM. */ | |
358 | ||
f8cfc6aa | 359 | if (REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER |
d45cf215 RS |
360 | && reg_equiv_mem[REGNO (x)] != 0) |
361 | x = reg_equiv_mem[REGNO (x)]; | |
362 | ||
8a99f6f9 R |
363 | sri.icode = CODE_FOR_nothing; |
364 | sri.prev_sri = prev_sri; | |
365 | class = targetm.secondary_reload (in_p, x, reload_class, reload_mode, &sri); | |
366 | icode = sri.icode; | |
eab89b90 | 367 | |
9ec7078b | 368 | /* If we don't need any secondary registers, done. */ |
8a99f6f9 | 369 | if (class == NO_REGS && icode == CODE_FOR_nothing) |
9ec7078b | 370 | return -1; |
eab89b90 | 371 | |
8a99f6f9 R |
372 | if (class != NO_REGS) |
373 | t_reload = push_secondary_reload (in_p, x, opnum, optional, class, | |
374 | reload_mode, type, &t_icode, &sri); | |
eab89b90 | 375 | |
8a99f6f9 R |
376 | /* If we will be using an insn, the secondary reload is for a |
377 | scratch register. */ | |
eab89b90 RK |
378 | |
379 | if (icode != CODE_FOR_nothing) | |
380 | { | |
40f03658 | 381 | /* If IN_P is nonzero, the reload register will be the output in |
eab89b90 RK |
382 | operand 0. If IN_P is zero, the reload register will be the input |
383 | in operand 1. Outputs should have an initial "=", which we must | |
384 | skip. */ | |
385 | ||
8a99f6f9 R |
386 | /* ??? It would be useful to be able to handle only two, or more than |
387 | three, operands, but for now we can only handle the case of having | |
388 | exactly three: output, input and one temp/scratch. */ | |
389 | gcc_assert (insn_data[(int) icode].n_operands == 3); | |
390 | ||
391 | /* ??? We currently have no way to represent a reload that needs | |
6416ae7f | 392 | an icode to reload from an intermediate tertiary reload register. |
8a99f6f9 R |
393 | We should probably have a new field in struct reload to tag a |
394 | chain of scratch operand reloads onto. */ | |
395 | gcc_assert (class == NO_REGS); | |
396 | ||
397 | scratch_constraint = insn_data[(int) icode].operand[2].constraint; | |
398 | gcc_assert (*scratch_constraint == '='); | |
399 | scratch_constraint++; | |
400 | if (*scratch_constraint == '&') | |
401 | scratch_constraint++; | |
402 | letter = *scratch_constraint; | |
403 | scratch_class = (letter == 'r' ? GENERAL_REGS | |
404 | : REG_CLASS_FROM_CONSTRAINT ((unsigned char) letter, | |
58477b5d | 405 | scratch_constraint)); |
8a99f6f9 R |
406 | |
407 | class = scratch_class; | |
408 | mode = insn_data[(int) icode].operand[2].mode; | |
eab89b90 RK |
409 | } |
410 | ||
9ec7078b RK |
411 | /* This case isn't valid, so fail. Reload is allowed to use the same |
412 | register for RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT reloads, but | |
413 | in the case of a secondary register, we actually need two different | |
414 | registers for correct code. We fail here to prevent the possibility of | |
415 | silently generating incorrect code later. | |
416 | ||
417 | The convention is that secondary input reloads are valid only if the | |
31989264 RH |
418 | secondary_class is different from class. If you have such a case, you |
419 | can not use secondary reloads, you must work around the problem some | |
420 | other way. | |
9ec7078b | 421 | |
94aaab7a RH |
422 | Allow this when a reload_in/out pattern is being used. I.e. assume |
423 | that the generated code handles this case. */ | |
9ec7078b | 424 | |
41374e13 NS |
425 | gcc_assert (!in_p || class != reload_class || icode != CODE_FOR_nothing |
426 | || t_icode != CODE_FOR_nothing); | |
9ec7078b | 427 | |
9ec7078b RK |
428 | /* See if we can reuse an existing secondary reload. */ |
429 | for (s_reload = 0; s_reload < n_reloads; s_reload++) | |
eceef4c9 BS |
430 | if (rld[s_reload].secondary_p |
431 | && (reg_class_subset_p (class, rld[s_reload].class) | |
432 | || reg_class_subset_p (rld[s_reload].class, class)) | |
433 | && ((in_p && rld[s_reload].inmode == mode) | |
434 | || (! in_p && rld[s_reload].outmode == mode)) | |
435 | && ((in_p && rld[s_reload].secondary_in_reload == t_reload) | |
436 | || (! in_p && rld[s_reload].secondary_out_reload == t_reload)) | |
437 | && ((in_p && rld[s_reload].secondary_in_icode == t_icode) | |
438 | || (! in_p && rld[s_reload].secondary_out_icode == t_icode)) | |
e9840398 | 439 | && (SMALL_REGISTER_CLASS_P (class) || SMALL_REGISTER_CLASSES) |
eceef4c9 BS |
440 | && MERGABLE_RELOADS (secondary_type, rld[s_reload].when_needed, |
441 | opnum, rld[s_reload].opnum)) | |
9ec7078b RK |
442 | { |
443 | if (in_p) | |
eceef4c9 | 444 | rld[s_reload].inmode = mode; |
9ec7078b | 445 | if (! in_p) |
eceef4c9 | 446 | rld[s_reload].outmode = mode; |
9ec7078b | 447 | |
eceef4c9 BS |
448 | if (reg_class_subset_p (class, rld[s_reload].class)) |
449 | rld[s_reload].class = class; | |
9ec7078b | 450 | |
eceef4c9 BS |
451 | rld[s_reload].opnum = MIN (rld[s_reload].opnum, opnum); |
452 | rld[s_reload].optional &= optional; | |
453 | rld[s_reload].secondary_p = 1; | |
454 | if (MERGE_TO_OTHER (secondary_type, rld[s_reload].when_needed, | |
455 | opnum, rld[s_reload].opnum)) | |
456 | rld[s_reload].when_needed = RELOAD_OTHER; | |
9ec7078b | 457 | } |
eab89b90 | 458 | |
9ec7078b RK |
459 | if (s_reload == n_reloads) |
460 | { | |
e9a25f70 JL |
461 | #ifdef SECONDARY_MEMORY_NEEDED |
462 | /* If we need a memory location to copy between the two reload regs, | |
463 | set it up now. Note that we do the input case before making | |
05d10675 | 464 | the reload and the output case after. This is due to the |
e9a25f70 JL |
465 | way reloads are output. */ |
466 | ||
467 | if (in_p && icode == CODE_FOR_nothing | |
468 | && SECONDARY_MEMORY_NEEDED (class, reload_class, mode)) | |
6fe8aebc RH |
469 | { |
470 | get_secondary_mem (x, reload_mode, opnum, type); | |
471 | ||
472 | /* We may have just added new reloads. Make sure we add | |
473 | the new reload at the end. */ | |
474 | s_reload = n_reloads; | |
475 | } | |
e9a25f70 JL |
476 | #endif |
477 | ||
9ec7078b | 478 | /* We need to make a new secondary reload for this register class. */ |
eceef4c9 BS |
479 | rld[s_reload].in = rld[s_reload].out = 0; |
480 | rld[s_reload].class = class; | |
481 | ||
482 | rld[s_reload].inmode = in_p ? mode : VOIDmode; | |
483 | rld[s_reload].outmode = ! in_p ? mode : VOIDmode; | |
484 | rld[s_reload].reg_rtx = 0; | |
485 | rld[s_reload].optional = optional; | |
eceef4c9 | 486 | rld[s_reload].inc = 0; |
9ec7078b | 487 | /* Maybe we could combine these, but it seems too tricky. */ |
eceef4c9 BS |
488 | rld[s_reload].nocombine = 1; |
489 | rld[s_reload].in_reg = 0; | |
490 | rld[s_reload].out_reg = 0; | |
491 | rld[s_reload].opnum = opnum; | |
492 | rld[s_reload].when_needed = secondary_type; | |
493 | rld[s_reload].secondary_in_reload = in_p ? t_reload : -1; | |
494 | rld[s_reload].secondary_out_reload = ! in_p ? t_reload : -1; | |
495 | rld[s_reload].secondary_in_icode = in_p ? t_icode : CODE_FOR_nothing; | |
496 | rld[s_reload].secondary_out_icode | |
9ec7078b | 497 | = ! in_p ? t_icode : CODE_FOR_nothing; |
eceef4c9 | 498 | rld[s_reload].secondary_p = 1; |
9ec7078b RK |
499 | |
500 | n_reloads++; | |
501 | ||
502 | #ifdef SECONDARY_MEMORY_NEEDED | |
9ec7078b | 503 | if (! in_p && icode == CODE_FOR_nothing |
f49e4127 JW |
504 | && SECONDARY_MEMORY_NEEDED (reload_class, class, mode)) |
505 | get_secondary_mem (x, mode, opnum, type); | |
9ec7078b RK |
506 | #endif |
507 | } | |
508 | ||
509 | *picode = icode; | |
510 | return s_reload; | |
eab89b90 | 511 | } |
8a99f6f9 R |
512 | |
513 | /* If a secondary reload is needed, return its class. If both an intermediate | |
514 | register and a scratch register is needed, we return the class of the | |
515 | intermediate register. */ | |
516 | enum reg_class | |
517 | secondary_reload_class (bool in_p, enum reg_class class, | |
518 | enum machine_mode mode, rtx x) | |
519 | { | |
520 | enum insn_code icode; | |
521 | secondary_reload_info sri; | |
522 | ||
523 | sri.icode = CODE_FOR_nothing; | |
524 | sri.prev_sri = NULL; | |
525 | class = targetm.secondary_reload (in_p, x, class, mode, &sri); | |
526 | icode = sri.icode; | |
527 | ||
528 | /* If there are no secondary reloads at all, we return NO_REGS. | |
529 | If an intermediate register is needed, we return its class. */ | |
530 | if (icode == CODE_FOR_nothing || class != NO_REGS) | |
531 | return class; | |
532 | ||
533 | /* No intermediate register is needed, but we have a special reload | |
534 | pattern, which we assume for now needs a scratch register. */ | |
535 | return scratch_reload_class (icode); | |
536 | } | |
537 | ||
538 | /* ICODE is the insn_code of a reload pattern. Check that it has exactly | |
539 | three operands, verify that operand 2 is an output operand, and return | |
540 | its register class. | |
541 | ??? We'd like to be able to handle any pattern with at least 2 operands, | |
542 | for zero or more scratch registers, but that needs more infrastructure. */ | |
543 | enum reg_class | |
544 | scratch_reload_class (enum insn_code icode) | |
545 | { | |
546 | const char *scratch_constraint; | |
547 | char scratch_letter; | |
548 | enum reg_class class; | |
549 | ||
550 | gcc_assert (insn_data[(int) icode].n_operands == 3); | |
551 | scratch_constraint = insn_data[(int) icode].operand[2].constraint; | |
552 | gcc_assert (*scratch_constraint == '='); | |
553 | scratch_constraint++; | |
554 | if (*scratch_constraint == '&') | |
555 | scratch_constraint++; | |
556 | scratch_letter = *scratch_constraint; | |
557 | if (scratch_letter == 'r') | |
558 | return GENERAL_REGS; | |
559 | class = REG_CLASS_FROM_CONSTRAINT ((unsigned char) scratch_letter, | |
560 | scratch_constraint); | |
561 | gcc_assert (class != NO_REGS); | |
562 | return class; | |
563 | } | |
eab89b90 | 564 | \f |
0dadecf6 RK |
565 | #ifdef SECONDARY_MEMORY_NEEDED |
566 | ||
05d10675 | 567 | /* Return a memory location that will be used to copy X in mode MODE. |
0dadecf6 RK |
568 | If we haven't already made a location for this mode in this insn, |
569 | call find_reloads_address on the location being returned. */ | |
570 | ||
571 | rtx | |
0c20a65f AJ |
572 | get_secondary_mem (rtx x ATTRIBUTE_UNUSED, enum machine_mode mode, |
573 | int opnum, enum reload_type type) | |
0dadecf6 RK |
574 | { |
575 | rtx loc; | |
576 | int mem_valid; | |
577 | ||
64609742 RK |
578 | /* By default, if MODE is narrower than a word, widen it to a word. |
579 | This is required because most machines that require these memory | |
580 | locations do not support short load and stores from all registers | |
581 | (e.g., FP registers). */ | |
582 | ||
583 | #ifdef SECONDARY_MEMORY_NEEDED_MODE | |
584 | mode = SECONDARY_MEMORY_NEEDED_MODE (mode); | |
585 | #else | |
4f9e0766 | 586 | if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD && INTEGRAL_MODE_P (mode)) |
0dadecf6 | 587 | mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0); |
64609742 | 588 | #endif |
0dadecf6 | 589 | |
77545d45 RK |
590 | /* If we already have made a MEM for this operand in MODE, return it. */ |
591 | if (secondary_memlocs_elim[(int) mode][opnum] != 0) | |
592 | return secondary_memlocs_elim[(int) mode][opnum]; | |
0dadecf6 | 593 | |
05d10675 | 594 | /* If this is the first time we've tried to get a MEM for this mode, |
0dadecf6 RK |
595 | allocate a new one. `something_changed' in reload will get set |
596 | by noticing that the frame size has changed. */ | |
597 | ||
598 | if (secondary_memlocs[(int) mode] == 0) | |
b24a53d5 JW |
599 | { |
600 | #ifdef SECONDARY_MEMORY_NEEDED_RTX | |
601 | secondary_memlocs[(int) mode] = SECONDARY_MEMORY_NEEDED_RTX (mode); | |
602 | #else | |
603 | secondary_memlocs[(int) mode] | |
604 | = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); | |
605 | #endif | |
606 | } | |
0dadecf6 RK |
607 | |
608 | /* Get a version of the address doing any eliminations needed. If that | |
609 | didn't give us a new MEM, make a new one if it isn't valid. */ | |
610 | ||
1914f5da | 611 | loc = eliminate_regs (secondary_memlocs[(int) mode], VOIDmode, NULL_RTX); |
0dadecf6 RK |
612 | mem_valid = strict_memory_address_p (mode, XEXP (loc, 0)); |
613 | ||
614 | if (! mem_valid && loc == secondary_memlocs[(int) mode]) | |
615 | loc = copy_rtx (loc); | |
616 | ||
617 | /* The only time the call below will do anything is if the stack | |
618 | offset is too large. In that case IND_LEVELS doesn't matter, so we | |
a8c9daeb RK |
619 | can just pass a zero. Adjust the type to be the address of the |
620 | corresponding object. If the address was valid, save the eliminated | |
621 | address. If it wasn't valid, we need to make a reload each time, so | |
622 | don't save it. */ | |
0dadecf6 | 623 | |
a8c9daeb RK |
624 | if (! mem_valid) |
625 | { | |
626 | type = (type == RELOAD_FOR_INPUT ? RELOAD_FOR_INPUT_ADDRESS | |
627 | : type == RELOAD_FOR_OUTPUT ? RELOAD_FOR_OUTPUT_ADDRESS | |
628 | : RELOAD_OTHER); | |
8d618585 | 629 | |
57292ec3 | 630 | find_reloads_address (mode, &loc, XEXP (loc, 0), &XEXP (loc, 0), |
55c22565 | 631 | opnum, type, 0, 0); |
a8c9daeb | 632 | } |
0dadecf6 | 633 | |
77545d45 | 634 | secondary_memlocs_elim[(int) mode][opnum] = loc; |
98e5e087 JH |
635 | if (secondary_memlocs_elim_used <= (int)mode) |
636 | secondary_memlocs_elim_used = (int)mode + 1; | |
0dadecf6 RK |
637 | return loc; |
638 | } | |
639 | ||
640 | /* Clear any secondary memory locations we've made. */ | |
641 | ||
642 | void | |
0c20a65f | 643 | clear_secondary_mem (void) |
0dadecf6 | 644 | { |
703ad42b | 645 | memset (secondary_memlocs, 0, sizeof secondary_memlocs); |
0dadecf6 RK |
646 | } |
647 | #endif /* SECONDARY_MEMORY_NEEDED */ | |
648 | \f | |
e11ab33b DD |
649 | |
650 | /* Find the largest class which has at least one register valid in | |
651 | mode INNER, and which for every such register, that register number | |
652 | plus N is also valid in OUTER (if in range) and is cheap to move | |
0e61db61 | 653 | into REGNO. Such a class must exist. */ |
c6716840 RK |
654 | |
655 | static enum reg_class | |
e11ab33b DD |
656 | find_valid_class (enum machine_mode outer ATTRIBUTE_UNUSED, |
657 | enum machine_mode inner ATTRIBUTE_UNUSED, int n, | |
0c20a65f | 658 | unsigned int dest_regno ATTRIBUTE_UNUSED) |
c6716840 | 659 | { |
a65dc37d | 660 | int best_cost = -1; |
c6716840 RK |
661 | int class; |
662 | int regno; | |
f428f252 | 663 | enum reg_class best_class = NO_REGS; |
4977bab6 | 664 | enum reg_class dest_class ATTRIBUTE_UNUSED = REGNO_REG_CLASS (dest_regno); |
770ae6cc | 665 | unsigned int best_size = 0; |
b80cb6e2 | 666 | int cost; |
c6716840 RK |
667 | |
668 | for (class = 1; class < N_REG_CLASSES; class++) | |
669 | { | |
670 | int bad = 0; | |
e11ab33b DD |
671 | int good = 0; |
672 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER - n && ! bad; regno++) | |
673 | if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)) | |
674 | { | |
675 | if (HARD_REGNO_MODE_OK (regno, inner)) | |
676 | { | |
677 | good = 1; | |
678 | if (! TEST_HARD_REG_BIT (reg_class_contents[class], regno + n) | |
679 | || ! HARD_REGNO_MODE_OK (regno + n, outer)) | |
680 | bad = 1; | |
681 | } | |
682 | } | |
c6716840 | 683 | |
e11ab33b | 684 | if (bad || !good) |
b80cb6e2 | 685 | continue; |
e11ab33b | 686 | cost = REGISTER_MOVE_COST (outer, class, dest_class); |
b80cb6e2 JH |
687 | |
688 | if ((reg_class_size[class] > best_size | |
689 | && (best_cost < 0 || best_cost >= cost)) | |
690 | || best_cost > cost) | |
a65dc37d JH |
691 | { |
692 | best_class = class; | |
693 | best_size = reg_class_size[class]; | |
e11ab33b | 694 | best_cost = REGISTER_MOVE_COST (outer, class, dest_class); |
a65dc37d | 695 | } |
c6716840 RK |
696 | } |
697 | ||
41374e13 | 698 | gcc_assert (best_size != 0); |
c6716840 RK |
699 | |
700 | return best_class; | |
701 | } | |
702 | \f | |
121315ea BS |
703 | /* Return the number of a previously made reload that can be combined with |
704 | a new one, or n_reloads if none of the existing reloads can be used. | |
705 | OUT, CLASS, TYPE and OPNUM are the same arguments as passed to | |
706 | push_reload, they determine the kind of the new reload that we try to | |
707 | combine. P_IN points to the corresponding value of IN, which can be | |
708 | modified by this function. | |
709 | DONT_SHARE is nonzero if we can't share any input-only reload for IN. */ | |
35fb60c4 | 710 | |
121315ea | 711 | static int |
0c20a65f AJ |
712 | find_reusable_reload (rtx *p_in, rtx out, enum reg_class class, |
713 | enum reload_type type, int opnum, int dont_share) | |
121315ea BS |
714 | { |
715 | rtx in = *p_in; | |
716 | int i; | |
717 | /* We can't merge two reloads if the output of either one is | |
718 | earlyclobbered. */ | |
719 | ||
720 | if (earlyclobber_operand_p (out)) | |
721 | return n_reloads; | |
722 | ||
723 | /* We can use an existing reload if the class is right | |
724 | and at least one of IN and OUT is a match | |
725 | and the other is at worst neutral. | |
05d10675 | 726 | (A zero compared against anything is neutral.) |
121315ea BS |
727 | |
728 | If SMALL_REGISTER_CLASSES, don't use existing reloads unless they are | |
729 | for the same thing since that can cause us to need more reload registers | |
730 | than we otherwise would. */ | |
05d10675 | 731 | |
121315ea | 732 | for (i = 0; i < n_reloads; i++) |
eceef4c9 BS |
733 | if ((reg_class_subset_p (class, rld[i].class) |
734 | || reg_class_subset_p (rld[i].class, class)) | |
121315ea | 735 | /* If the existing reload has a register, it must fit our class. */ |
eceef4c9 | 736 | && (rld[i].reg_rtx == 0 |
121315ea | 737 | || TEST_HARD_REG_BIT (reg_class_contents[(int) class], |
eceef4c9 BS |
738 | true_regnum (rld[i].reg_rtx))) |
739 | && ((in != 0 && MATCHES (rld[i].in, in) && ! dont_share | |
740 | && (out == 0 || rld[i].out == 0 || MATCHES (rld[i].out, out))) | |
741 | || (out != 0 && MATCHES (rld[i].out, out) | |
742 | && (in == 0 || rld[i].in == 0 || MATCHES (rld[i].in, in)))) | |
743 | && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out)) | |
e9840398 | 744 | && (SMALL_REGISTER_CLASS_P (class) || SMALL_REGISTER_CLASSES) |
eceef4c9 | 745 | && MERGABLE_RELOADS (type, rld[i].when_needed, opnum, rld[i].opnum)) |
121315ea BS |
746 | return i; |
747 | ||
748 | /* Reloading a plain reg for input can match a reload to postincrement | |
749 | that reg, since the postincrement's value is the right value. | |
750 | Likewise, it can match a preincrement reload, since we regard | |
751 | the preincrementation as happening before any ref in this insn | |
752 | to that register. */ | |
753 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 BS |
754 | if ((reg_class_subset_p (class, rld[i].class) |
755 | || reg_class_subset_p (rld[i].class, class)) | |
121315ea BS |
756 | /* If the existing reload has a register, it must fit our |
757 | class. */ | |
eceef4c9 | 758 | && (rld[i].reg_rtx == 0 |
121315ea | 759 | || TEST_HARD_REG_BIT (reg_class_contents[(int) class], |
eceef4c9 BS |
760 | true_regnum (rld[i].reg_rtx))) |
761 | && out == 0 && rld[i].out == 0 && rld[i].in != 0 | |
f8cfc6aa | 762 | && ((REG_P (in) |
ec8e098d | 763 | && GET_RTX_CLASS (GET_CODE (rld[i].in)) == RTX_AUTOINC |
eceef4c9 | 764 | && MATCHES (XEXP (rld[i].in, 0), in)) |
f8cfc6aa | 765 | || (REG_P (rld[i].in) |
ec8e098d | 766 | && GET_RTX_CLASS (GET_CODE (in)) == RTX_AUTOINC |
4b983fdc | 767 | && MATCHES (XEXP (in, 0), rld[i].in))) |
eceef4c9 | 768 | && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out)) |
e9840398 | 769 | && (SMALL_REGISTER_CLASS_P (class) || SMALL_REGISTER_CLASSES) |
eceef4c9 BS |
770 | && MERGABLE_RELOADS (type, rld[i].when_needed, |
771 | opnum, rld[i].opnum)) | |
121315ea BS |
772 | { |
773 | /* Make sure reload_in ultimately has the increment, | |
774 | not the plain register. */ | |
f8cfc6aa | 775 | if (REG_P (in)) |
eceef4c9 | 776 | *p_in = rld[i].in; |
121315ea BS |
777 | return i; |
778 | } | |
779 | return n_reloads; | |
780 | } | |
781 | ||
e6ea3b5f JL |
782 | /* Return nonzero if X is a SUBREG which will require reloading of its |
783 | SUBREG_REG expression. */ | |
784 | ||
785 | static int | |
0c20a65f | 786 | reload_inner_reg_of_subreg (rtx x, enum machine_mode mode, int output) |
e6ea3b5f JL |
787 | { |
788 | rtx inner; | |
789 | ||
790 | /* Only SUBREGs are problematical. */ | |
791 | if (GET_CODE (x) != SUBREG) | |
792 | return 0; | |
793 | ||
794 | inner = SUBREG_REG (x); | |
795 | ||
35fb60c4 RK |
796 | /* If INNER is a constant or PLUS, then INNER must be reloaded. */ |
797 | if (CONSTANT_P (inner) || GET_CODE (inner) == PLUS) | |
e6ea3b5f JL |
798 | return 1; |
799 | ||
800 | /* If INNER is not a hard register, then INNER will not need to | |
801 | be reloaded. */ | |
f8cfc6aa | 802 | if (!REG_P (inner) |
e6ea3b5f JL |
803 | || REGNO (inner) >= FIRST_PSEUDO_REGISTER) |
804 | return 0; | |
805 | ||
806 | /* If INNER is not ok for MODE, then INNER will need reloading. */ | |
ddef6bc7 | 807 | if (! HARD_REGNO_MODE_OK (subreg_regno (x), mode)) |
e6ea3b5f JL |
808 | return 1; |
809 | ||
810 | /* If the outer part is a word or smaller, INNER larger than a | |
811 | word and the number of regs for INNER is not the same as the | |
812 | number of words in INNER, then INNER will need reloading. */ | |
813 | return (GET_MODE_SIZE (mode) <= UNITS_PER_WORD | |
4bf1d92e | 814 | && output |
e6ea3b5f JL |
815 | && GET_MODE_SIZE (GET_MODE (inner)) > UNITS_PER_WORD |
816 | && ((GET_MODE_SIZE (GET_MODE (inner)) / UNITS_PER_WORD) | |
66fd46b6 | 817 | != (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)])); |
e6ea3b5f JL |
818 | } |
819 | ||
35d6034b R |
820 | /* Return nonzero if IN can be reloaded into REGNO with mode MODE without |
821 | requiring an extra reload register. The caller has already found that | |
822 | IN contains some reference to REGNO, so check that we can produce the | |
823 | new value in a single step. E.g. if we have | |
824 | (set (reg r13) (plus (reg r13) (const int 1))), and there is an | |
825 | instruction that adds one to a register, this should succeed. | |
826 | However, if we have something like | |
827 | (set (reg r13) (plus (reg r13) (const int 999))), and the constant 999 | |
828 | needs to be loaded into a register first, we need a separate reload | |
829 | register. | |
830 | Such PLUS reloads are generated by find_reload_address_part. | |
831 | The out-of-range PLUS expressions are usually introduced in the instruction | |
832 | patterns by register elimination and substituting pseudos without a home | |
833 | by their function-invariant equivalences. */ | |
834 | static int | |
835 | can_reload_into (rtx in, int regno, enum machine_mode mode) | |
836 | { | |
837 | rtx dst, test_insn; | |
838 | int r = 0; | |
839 | struct recog_data save_recog_data; | |
840 | ||
841 | /* For matching constraints, we often get notional input reloads where | |
842 | we want to use the original register as the reload register. I.e. | |
843 | technically this is a non-optional input-output reload, but IN is | |
844 | already a valid register, and has been chosen as the reload register. | |
845 | Speed this up, since it trivially works. */ | |
f8cfc6aa | 846 | if (REG_P (in)) |
35d6034b R |
847 | return 1; |
848 | ||
849 | /* To test MEMs properly, we'd have to take into account all the reloads | |
850 | that are already scheduled, which can become quite complicated. | |
851 | And since we've already handled address reloads for this MEM, it | |
852 | should always succeed anyway. */ | |
3c0cb5de | 853 | if (MEM_P (in)) |
35d6034b R |
854 | return 1; |
855 | ||
856 | /* If we can make a simple SET insn that does the job, everything should | |
857 | be fine. */ | |
858 | dst = gen_rtx_REG (mode, regno); | |
859 | test_insn = make_insn_raw (gen_rtx_SET (VOIDmode, dst, in)); | |
860 | save_recog_data = recog_data; | |
861 | if (recog_memoized (test_insn) >= 0) | |
862 | { | |
863 | extract_insn (test_insn); | |
864 | r = constrain_operands (1); | |
865 | } | |
866 | recog_data = save_recog_data; | |
867 | return r; | |
868 | } | |
869 | ||
a8c9daeb | 870 | /* Record one reload that needs to be performed. |
eab89b90 RK |
871 | IN is an rtx saying where the data are to be found before this instruction. |
872 | OUT says where they must be stored after the instruction. | |
873 | (IN is zero for data not read, and OUT is zero for data not written.) | |
874 | INLOC and OUTLOC point to the places in the instructions where | |
875 | IN and OUT were found. | |
40f03658 | 876 | If IN and OUT are both nonzero, it means the same register must be used |
a8c9daeb RK |
877 | to reload both IN and OUT. |
878 | ||
eab89b90 RK |
879 | CLASS is a register class required for the reloaded data. |
880 | INMODE is the machine mode that the instruction requires | |
881 | for the reg that replaces IN and OUTMODE is likewise for OUT. | |
882 | ||
883 | If IN is zero, then OUT's location and mode should be passed as | |
884 | INLOC and INMODE. | |
885 | ||
886 | STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx. | |
887 | ||
888 | OPTIONAL nonzero means this reload does not need to be performed: | |
889 | it can be discarded if that is more convenient. | |
890 | ||
a8c9daeb RK |
891 | OPNUM and TYPE say what the purpose of this reload is. |
892 | ||
eab89b90 RK |
893 | The return value is the reload-number for this reload. |
894 | ||
895 | If both IN and OUT are nonzero, in some rare cases we might | |
896 | want to make two separate reloads. (Actually we never do this now.) | |
897 | Therefore, the reload-number for OUT is stored in | |
898 | output_reloadnum when we return; the return value applies to IN. | |
899 | Usually (presently always), when IN and OUT are nonzero, | |
900 | the two reload-numbers are equal, but the caller should be careful to | |
901 | distinguish them. */ | |
902 | ||
aead1ca3 | 903 | int |
0c20a65f AJ |
904 | push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc, |
905 | enum reg_class class, enum machine_mode inmode, | |
906 | enum machine_mode outmode, int strict_low, int optional, | |
907 | int opnum, enum reload_type type) | |
eab89b90 | 908 | { |
b3694847 | 909 | int i; |
eab89b90 | 910 | int dont_share = 0; |
74347d76 | 911 | int dont_remove_subreg = 0; |
eab89b90 | 912 | rtx *in_subreg_loc = 0, *out_subreg_loc = 0; |
9ec7078b | 913 | int secondary_in_reload = -1, secondary_out_reload = -1; |
a229128d RK |
914 | enum insn_code secondary_in_icode = CODE_FOR_nothing; |
915 | enum insn_code secondary_out_icode = CODE_FOR_nothing; | |
a8c9daeb | 916 | |
eab89b90 RK |
917 | /* INMODE and/or OUTMODE could be VOIDmode if no mode |
918 | has been specified for the operand. In that case, | |
919 | use the operand's mode as the mode to reload. */ | |
920 | if (inmode == VOIDmode && in != 0) | |
921 | inmode = GET_MODE (in); | |
922 | if (outmode == VOIDmode && out != 0) | |
923 | outmode = GET_MODE (out); | |
924 | ||
05d10675 | 925 | /* If IN is a pseudo register everywhere-equivalent to a constant, and |
eab89b90 RK |
926 | it is not in a hard register, reload straight from the constant, |
927 | since we want to get rid of such pseudo registers. | |
928 | Often this is done earlier, but not always in find_reloads_address. */ | |
f8cfc6aa | 929 | if (in != 0 && REG_P (in)) |
eab89b90 | 930 | { |
b3694847 | 931 | int regno = REGNO (in); |
eab89b90 RK |
932 | |
933 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
934 | && reg_equiv_constant[regno] != 0) | |
935 | in = reg_equiv_constant[regno]; | |
936 | } | |
937 | ||
938 | /* Likewise for OUT. Of course, OUT will never be equivalent to | |
939 | an actual constant, but it might be equivalent to a memory location | |
940 | (in the case of a parameter). */ | |
f8cfc6aa | 941 | if (out != 0 && REG_P (out)) |
eab89b90 | 942 | { |
b3694847 | 943 | int regno = REGNO (out); |
eab89b90 RK |
944 | |
945 | if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 | |
946 | && reg_equiv_constant[regno] != 0) | |
947 | out = reg_equiv_constant[regno]; | |
948 | } | |
949 | ||
950 | /* If we have a read-write operand with an address side-effect, | |
951 | change either IN or OUT so the side-effect happens only once. */ | |
3c0cb5de | 952 | if (in != 0 && out != 0 && MEM_P (in) && rtx_equal_p (in, out)) |
f1ec5147 RK |
953 | switch (GET_CODE (XEXP (in, 0))) |
954 | { | |
955 | case POST_INC: case POST_DEC: case POST_MODIFY: | |
956 | in = replace_equiv_address_nv (in, XEXP (XEXP (in, 0), 0)); | |
957 | break; | |
3bdf5ad1 | 958 | |
f1ec5147 RK |
959 | case PRE_INC: case PRE_DEC: case PRE_MODIFY: |
960 | out = replace_equiv_address_nv (out, XEXP (XEXP (out, 0), 0)); | |
961 | break; | |
3bdf5ad1 | 962 | |
f1ec5147 RK |
963 | default: |
964 | break; | |
f4f4d0f8 | 965 | } |
eab89b90 | 966 | |
a61c98cf | 967 | /* If we are reloading a (SUBREG constant ...), really reload just the |
ca769828 | 968 | inside expression in its own mode. Similarly for (SUBREG (PLUS ...)). |
a61c98cf RK |
969 | If we have (SUBREG:M1 (MEM:M2 ...) ...) (or an inner REG that is still |
970 | a pseudo and hence will become a MEM) with M1 wider than M2 and the | |
971 | register is a pseudo, also reload the inside expression. | |
f72ccbe6 | 972 | For machines that extend byte loads, do this for any SUBREG of a pseudo |
486d8509 RK |
973 | where both M1 and M2 are a word or smaller, M1 is wider than M2, and |
974 | M2 is an integral mode that gets extended when loaded. | |
86c31b2d | 975 | Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
eab89b90 RK |
976 | either M1 is not valid for R or M2 is wider than a word but we only |
977 | need one word to store an M2-sized quantity in R. | |
86c31b2d RS |
978 | (However, if OUT is nonzero, we need to reload the reg *and* |
979 | the subreg, so do nothing here, and let following statement handle it.) | |
980 | ||
eab89b90 RK |
981 | Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere; |
982 | we can't handle it here because CONST_INT does not indicate a mode. | |
983 | ||
984 | Similarly, we must reload the inside expression if we have a | |
df62f951 RK |
985 | STRICT_LOW_PART (presumably, in == out in the cas). |
986 | ||
987 | Also reload the inner expression if it does not require a secondary | |
486d8509 RK |
988 | reload but the SUBREG does. |
989 | ||
990 | Finally, reload the inner expression if it is a register that is in | |
991 | the class whose registers cannot be referenced in a different size | |
b4905cba | 992 | and M1 is not the same size as M2. If subreg_lowpart_p is false, we |
d030f4b2 | 993 | cannot reload just the inside since we might end up with the wrong |
ab87f8c8 JL |
994 | register class. But if it is inside a STRICT_LOW_PART, we have |
995 | no choice, so we hope we do get the right register class there. */ | |
eab89b90 | 996 | |
ab87f8c8 | 997 | if (in != 0 && GET_CODE (in) == SUBREG |
b4905cba | 998 | && (subreg_lowpart_p (in) || strict_low) |
cff9f8d5 | 999 | #ifdef CANNOT_CHANGE_MODE_CLASS |
b0c42aed | 1000 | && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (in)), inmode, class) |
94bafba7 | 1001 | #endif |
a61c98cf | 1002 | && (CONSTANT_P (SUBREG_REG (in)) |
ca769828 | 1003 | || GET_CODE (SUBREG_REG (in)) == PLUS |
eab89b90 | 1004 | || strict_low |
f8cfc6aa | 1005 | || (((REG_P (SUBREG_REG (in)) |
a61c98cf | 1006 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER) |
3c0cb5de | 1007 | || MEM_P (SUBREG_REG (in))) |
03b72c86 RK |
1008 | && ((GET_MODE_SIZE (inmode) |
1009 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
09bf0250 | 1010 | #ifdef LOAD_EXTEND_OP |
03b72c86 RK |
1011 | || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD |
1012 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1013 | <= UNITS_PER_WORD) | |
1014 | && (GET_MODE_SIZE (inmode) | |
486d8509 RK |
1015 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) |
1016 | && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in))) | |
f822d252 | 1017 | && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != UNKNOWN) |
d2c92f5a R |
1018 | #endif |
1019 | #ifdef WORD_REGISTER_OPERATIONS | |
1020 | || ((GET_MODE_SIZE (inmode) | |
1021 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
1022 | && ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD == | |
1023 | ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) - 1) | |
1024 | / UNITS_PER_WORD))) | |
f72ccbe6 | 1025 | #endif |
03b72c86 | 1026 | )) |
f8cfc6aa | 1027 | || (REG_P (SUBREG_REG (in)) |
a61c98cf | 1028 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER |
86c31b2d RS |
1029 | /* The case where out is nonzero |
1030 | is handled differently in the following statement. */ | |
b4905cba | 1031 | && (out == 0 || subreg_lowpart_p (in)) |
f72ccbe6 RK |
1032 | && ((GET_MODE_SIZE (inmode) <= UNITS_PER_WORD |
1033 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1034 | > UNITS_PER_WORD) | |
1035 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1036 | / UNITS_PER_WORD) | |
66fd46b6 JH |
1037 | != (int) hard_regno_nregs[REGNO (SUBREG_REG (in))] |
1038 | [GET_MODE (SUBREG_REG (in))])) | |
ddef6bc7 | 1039 | || ! HARD_REGNO_MODE_OK (subreg_regno (in), inmode))) |
8a99f6f9 R |
1040 | || (secondary_reload_class (1, class, inmode, in) != NO_REGS |
1041 | && (secondary_reload_class (1, class, GET_MODE (SUBREG_REG (in)), | |
1042 | SUBREG_REG (in)) | |
df62f951 | 1043 | == NO_REGS)) |
cff9f8d5 | 1044 | #ifdef CANNOT_CHANGE_MODE_CLASS |
f8cfc6aa | 1045 | || (REG_P (SUBREG_REG (in)) |
486d8509 | 1046 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER |
cff9f8d5 AH |
1047 | && REG_CANNOT_CHANGE_MODE_P |
1048 | (REGNO (SUBREG_REG (in)), GET_MODE (SUBREG_REG (in)), inmode)) | |
df62f951 RK |
1049 | #endif |
1050 | )) | |
eab89b90 RK |
1051 | { |
1052 | in_subreg_loc = inloc; | |
1053 | inloc = &SUBREG_REG (in); | |
1054 | in = *inloc; | |
d2c92f5a | 1055 | #if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS) |
3c0cb5de | 1056 | if (MEM_P (in)) |
eab89b90 RK |
1057 | /* This is supposed to happen only for paradoxical subregs made by |
1058 | combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */ | |
41374e13 | 1059 | gcc_assert (GET_MODE_SIZE (GET_MODE (in)) <= GET_MODE_SIZE (inmode)); |
e05a9da8 | 1060 | #endif |
eab89b90 RK |
1061 | inmode = GET_MODE (in); |
1062 | } | |
1063 | ||
86c31b2d RS |
1064 | /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
1065 | either M1 is not valid for R or M2 is wider than a word but we only | |
1066 | need one word to store an M2-sized quantity in R. | |
1067 | ||
1068 | However, we must reload the inner reg *as well as* the subreg in | |
1069 | that case. */ | |
1070 | ||
6fd5ac08 | 1071 | /* Similar issue for (SUBREG constant ...) if it was not handled by the |
ddef6bc7 | 1072 | code above. This can happen if SUBREG_BYTE != 0. */ |
6fd5ac08 | 1073 | |
4bf1d92e | 1074 | if (in != 0 && reload_inner_reg_of_subreg (in, inmode, 0)) |
86c31b2d | 1075 | { |
35fb60c4 RK |
1076 | enum reg_class in_class = class; |
1077 | ||
f8cfc6aa | 1078 | if (REG_P (SUBREG_REG (in))) |
35fb60c4 | 1079 | in_class |
e11ab33b | 1080 | = find_valid_class (inmode, GET_MODE (SUBREG_REG (in)), |
35fb60c4 RK |
1081 | subreg_regno_offset (REGNO (SUBREG_REG (in)), |
1082 | GET_MODE (SUBREG_REG (in)), | |
1083 | SUBREG_BYTE (in), | |
a65dc37d JH |
1084 | GET_MODE (in)), |
1085 | REGNO (SUBREG_REG (in))); | |
35fb60c4 | 1086 | |
c96d01ab RK |
1087 | /* This relies on the fact that emit_reload_insns outputs the |
1088 | instructions for input reloads of type RELOAD_OTHER in the same | |
1089 | order as the reloads. Thus if the outer reload is also of type | |
1090 | RELOAD_OTHER, we are guaranteed that this inner reload will be | |
1091 | output before the outer reload. */ | |
f4f4d0f8 | 1092 | push_reload (SUBREG_REG (in), NULL_RTX, &SUBREG_REG (in), (rtx *) 0, |
35fb60c4 | 1093 | in_class, VOIDmode, VOIDmode, 0, 0, opnum, type); |
74347d76 | 1094 | dont_remove_subreg = 1; |
86c31b2d RS |
1095 | } |
1096 | ||
eab89b90 RK |
1097 | /* Similarly for paradoxical and problematical SUBREGs on the output. |
1098 | Note that there is no reason we need worry about the previous value | |
1099 | of SUBREG_REG (out); even if wider than out, | |
1100 | storing in a subreg is entitled to clobber it all | |
1101 | (except in the case of STRICT_LOW_PART, | |
1102 | and in that case the constraint should label it input-output.) */ | |
ab87f8c8 | 1103 | if (out != 0 && GET_CODE (out) == SUBREG |
b4905cba | 1104 | && (subreg_lowpart_p (out) || strict_low) |
cff9f8d5 | 1105 | #ifdef CANNOT_CHANGE_MODE_CLASS |
b0c42aed | 1106 | && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (out)), outmode, class) |
94bafba7 | 1107 | #endif |
a61c98cf | 1108 | && (CONSTANT_P (SUBREG_REG (out)) |
eab89b90 | 1109 | || strict_low |
f8cfc6aa | 1110 | || (((REG_P (SUBREG_REG (out)) |
a61c98cf | 1111 | && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER) |
3c0cb5de | 1112 | || MEM_P (SUBREG_REG (out))) |
03b72c86 | 1113 | && ((GET_MODE_SIZE (outmode) |
1914f5da RH |
1114 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) |
1115 | #ifdef WORD_REGISTER_OPERATIONS | |
6d49a073 JW |
1116 | || ((GET_MODE_SIZE (outmode) |
1117 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
1118 | && ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD == | |
1119 | ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) - 1) | |
1120 | / UNITS_PER_WORD))) | |
1914f5da | 1121 | #endif |
05d10675 | 1122 | )) |
f8cfc6aa | 1123 | || (REG_P (SUBREG_REG (out)) |
eab89b90 | 1124 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER |
f72ccbe6 RK |
1125 | && ((GET_MODE_SIZE (outmode) <= UNITS_PER_WORD |
1126 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1127 | > UNITS_PER_WORD) | |
1128 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1129 | / UNITS_PER_WORD) | |
66fd46b6 JH |
1130 | != (int) hard_regno_nregs[REGNO (SUBREG_REG (out))] |
1131 | [GET_MODE (SUBREG_REG (out))])) | |
ddef6bc7 | 1132 | || ! HARD_REGNO_MODE_OK (subreg_regno (out), outmode))) |
8a99f6f9 R |
1133 | || (secondary_reload_class (0, class, outmode, out) != NO_REGS |
1134 | && (secondary_reload_class (0, class, GET_MODE (SUBREG_REG (out)), | |
1135 | SUBREG_REG (out)) | |
df62f951 | 1136 | == NO_REGS)) |
cff9f8d5 | 1137 | #ifdef CANNOT_CHANGE_MODE_CLASS |
f8cfc6aa | 1138 | || (REG_P (SUBREG_REG (out)) |
486d8509 | 1139 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER |
cff9f8d5 | 1140 | && REG_CANNOT_CHANGE_MODE_P (REGNO (SUBREG_REG (out)), |
0c20a65f | 1141 | GET_MODE (SUBREG_REG (out)), |
cff9f8d5 | 1142 | outmode)) |
df62f951 RK |
1143 | #endif |
1144 | )) | |
eab89b90 RK |
1145 | { |
1146 | out_subreg_loc = outloc; | |
1147 | outloc = &SUBREG_REG (out); | |
05d10675 | 1148 | out = *outloc; |
d2c92f5a | 1149 | #if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS) |
41374e13 NS |
1150 | gcc_assert (!MEM_P (out) |
1151 | || GET_MODE_SIZE (GET_MODE (out)) | |
1152 | <= GET_MODE_SIZE (outmode)); | |
e05a9da8 | 1153 | #endif |
eab89b90 RK |
1154 | outmode = GET_MODE (out); |
1155 | } | |
1156 | ||
74347d76 RK |
1157 | /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where |
1158 | either M1 is not valid for R or M2 is wider than a word but we only | |
1159 | need one word to store an M2-sized quantity in R. | |
1160 | ||
1161 | However, we must reload the inner reg *as well as* the subreg in | |
1162 | that case. In this case, the inner reg is an in-out reload. */ | |
1163 | ||
4bf1d92e | 1164 | if (out != 0 && reload_inner_reg_of_subreg (out, outmode, 1)) |
74347d76 | 1165 | { |
c96d01ab RK |
1166 | /* This relies on the fact that emit_reload_insns outputs the |
1167 | instructions for output reloads of type RELOAD_OTHER in reverse | |
1168 | order of the reloads. Thus if the outer reload is also of type | |
1169 | RELOAD_OTHER, we are guaranteed that this inner reload will be | |
1170 | output after the outer reload. */ | |
74347d76 RK |
1171 | dont_remove_subreg = 1; |
1172 | push_reload (SUBREG_REG (out), SUBREG_REG (out), &SUBREG_REG (out), | |
c6716840 | 1173 | &SUBREG_REG (out), |
e11ab33b | 1174 | find_valid_class (outmode, GET_MODE (SUBREG_REG (out)), |
ddef6bc7 JJ |
1175 | subreg_regno_offset (REGNO (SUBREG_REG (out)), |
1176 | GET_MODE (SUBREG_REG (out)), | |
1177 | SUBREG_BYTE (out), | |
a65dc37d JH |
1178 | GET_MODE (out)), |
1179 | REGNO (SUBREG_REG (out))), | |
c6716840 | 1180 | VOIDmode, VOIDmode, 0, 0, |
74347d76 RK |
1181 | opnum, RELOAD_OTHER); |
1182 | } | |
1183 | ||
eab89b90 | 1184 | /* If IN appears in OUT, we can't share any input-only reload for IN. */ |
3c0cb5de | 1185 | if (in != 0 && out != 0 && MEM_P (out) |
10050f74 | 1186 | && (REG_P (in) || MEM_P (in) || GET_CODE (in) == PLUS) |
bfa30b22 | 1187 | && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0))) |
eab89b90 RK |
1188 | dont_share = 1; |
1189 | ||
0dadecf6 RK |
1190 | /* If IN is a SUBREG of a hard register, make a new REG. This |
1191 | simplifies some of the cases below. */ | |
1192 | ||
f8cfc6aa | 1193 | if (in != 0 && GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in)) |
74347d76 RK |
1194 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER |
1195 | && ! dont_remove_subreg) | |
ddef6bc7 | 1196 | in = gen_rtx_REG (GET_MODE (in), subreg_regno (in)); |
0dadecf6 RK |
1197 | |
1198 | /* Similarly for OUT. */ | |
1199 | if (out != 0 && GET_CODE (out) == SUBREG | |
f8cfc6aa | 1200 | && REG_P (SUBREG_REG (out)) |
74347d76 RK |
1201 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER |
1202 | && ! dont_remove_subreg) | |
ddef6bc7 | 1203 | out = gen_rtx_REG (GET_MODE (out), subreg_regno (out)); |
0dadecf6 | 1204 | |
eab89b90 RK |
1205 | /* Narrow down the class of register wanted if that is |
1206 | desirable on this machine for efficiency. */ | |
b5c82fa1 PB |
1207 | { |
1208 | enum reg_class preferred_class = class; | |
1209 | ||
1210 | if (in != 0) | |
1211 | preferred_class = PREFERRED_RELOAD_CLASS (in, class); | |
eab89b90 | 1212 | |
ac2a9454 | 1213 | /* Output reloads may need analogous treatment, different in detail. */ |
18a53b78 | 1214 | #ifdef PREFERRED_OUTPUT_RELOAD_CLASS |
b5c82fa1 PB |
1215 | if (out != 0) |
1216 | preferred_class = PREFERRED_OUTPUT_RELOAD_CLASS (out, preferred_class); | |
18a53b78 RS |
1217 | #endif |
1218 | ||
b5c82fa1 PB |
1219 | /* Discard what the target said if we cannot do it. */ |
1220 | if (preferred_class != NO_REGS | |
1221 | || (optional && type == RELOAD_FOR_OUTPUT)) | |
1222 | class = preferred_class; | |
1223 | } | |
1224 | ||
eab89b90 RK |
1225 | /* Make sure we use a class that can handle the actual pseudo |
1226 | inside any subreg. For example, on the 386, QImode regs | |
1227 | can appear within SImode subregs. Although GENERAL_REGS | |
1228 | can handle SImode, QImode needs a smaller class. */ | |
1229 | #ifdef LIMIT_RELOAD_CLASS | |
1230 | if (in_subreg_loc) | |
1231 | class = LIMIT_RELOAD_CLASS (inmode, class); | |
1232 | else if (in != 0 && GET_CODE (in) == SUBREG) | |
1233 | class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), class); | |
1234 | ||
1235 | if (out_subreg_loc) | |
1236 | class = LIMIT_RELOAD_CLASS (outmode, class); | |
1237 | if (out != 0 && GET_CODE (out) == SUBREG) | |
1238 | class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), class); | |
1239 | #endif | |
1240 | ||
eab89b90 RK |
1241 | /* Verify that this class is at least possible for the mode that |
1242 | is specified. */ | |
1243 | if (this_insn_is_asm) | |
1244 | { | |
1245 | enum machine_mode mode; | |
1246 | if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) | |
1247 | mode = inmode; | |
1248 | else | |
1249 | mode = outmode; | |
5488078f RS |
1250 | if (mode == VOIDmode) |
1251 | { | |
971801ff JM |
1252 | error_for_asm (this_insn, "cannot reload integer constant " |
1253 | "operand in %<asm%>"); | |
5488078f RS |
1254 | mode = word_mode; |
1255 | if (in != 0) | |
1256 | inmode = word_mode; | |
1257 | if (out != 0) | |
1258 | outmode = word_mode; | |
1259 | } | |
eab89b90 RK |
1260 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1261 | if (HARD_REGNO_MODE_OK (i, mode) | |
09e18274 RS |
1262 | && in_hard_reg_set_p (reg_class_contents[(int) class], mode, i)) |
1263 | break; | |
eab89b90 RK |
1264 | if (i == FIRST_PSEUDO_REGISTER) |
1265 | { | |
971801ff JM |
1266 | error_for_asm (this_insn, "impossible register constraint " |
1267 | "in %<asm%>"); | |
71156bcc JH |
1268 | /* Avoid further trouble with this insn. */ |
1269 | PATTERN (this_insn) = gen_rtx_USE (VOIDmode, const0_rtx); | |
1270 | /* We used to continue here setting class to ALL_REGS, but it triggers | |
1271 | sanity check on i386 for: | |
1272 | void foo(long double d) | |
1273 | { | |
1274 | asm("" :: "a" (d)); | |
1275 | } | |
1276 | Returning zero here ought to be safe as we take care in | |
1277 | find_reloads to not process the reloads when instruction was | |
1278 | replaced by USE. */ | |
1279 | ||
1280 | return 0; | |
eab89b90 RK |
1281 | } |
1282 | } | |
1283 | ||
cb2afeb3 R |
1284 | /* Optional output reloads are always OK even if we have no register class, |
1285 | since the function of these reloads is only to have spill_reg_store etc. | |
1286 | set, so that the storing insn can be deleted later. */ | |
41374e13 NS |
1287 | gcc_assert (class != NO_REGS |
1288 | || (optional != 0 && type == RELOAD_FOR_OUTPUT)); | |
5488078f | 1289 | |
121315ea | 1290 | i = find_reusable_reload (&in, out, class, type, opnum, dont_share); |
eab89b90 RK |
1291 | |
1292 | if (i == n_reloads) | |
1293 | { | |
9ec7078b RK |
1294 | /* See if we need a secondary reload register to move between CLASS |
1295 | and IN or CLASS and OUT. Get the icode and push any required reloads | |
1296 | needed for each of them if so. */ | |
eab89b90 | 1297 | |
eab89b90 | 1298 | if (in != 0) |
9ec7078b RK |
1299 | secondary_in_reload |
1300 | = push_secondary_reload (1, in, opnum, optional, class, inmode, type, | |
8a99f6f9 | 1301 | &secondary_in_icode, NULL); |
eab89b90 | 1302 | if (out != 0 && GET_CODE (out) != SCRATCH) |
9ec7078b RK |
1303 | secondary_out_reload |
1304 | = push_secondary_reload (0, out, opnum, optional, class, outmode, | |
8a99f6f9 | 1305 | type, &secondary_out_icode, NULL); |
eab89b90 RK |
1306 | |
1307 | /* We found no existing reload suitable for re-use. | |
1308 | So add an additional reload. */ | |
1309 | ||
e9a25f70 JL |
1310 | #ifdef SECONDARY_MEMORY_NEEDED |
1311 | /* If a memory location is needed for the copy, make one. */ | |
71a9b19a RG |
1312 | if (in != 0 |
1313 | && (REG_P (in) | |
1314 | || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in)))) | |
344b78b8 JH |
1315 | && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER |
1316 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)), | |
05d10675 | 1317 | class, inmode)) |
e9a25f70 JL |
1318 | get_secondary_mem (in, inmode, opnum, type); |
1319 | #endif | |
1320 | ||
9ec7078b | 1321 | i = n_reloads; |
eceef4c9 BS |
1322 | rld[i].in = in; |
1323 | rld[i].out = out; | |
1324 | rld[i].class = class; | |
1325 | rld[i].inmode = inmode; | |
1326 | rld[i].outmode = outmode; | |
1327 | rld[i].reg_rtx = 0; | |
1328 | rld[i].optional = optional; | |
eceef4c9 BS |
1329 | rld[i].inc = 0; |
1330 | rld[i].nocombine = 0; | |
1331 | rld[i].in_reg = inloc ? *inloc : 0; | |
1332 | rld[i].out_reg = outloc ? *outloc : 0; | |
1333 | rld[i].opnum = opnum; | |
1334 | rld[i].when_needed = type; | |
1335 | rld[i].secondary_in_reload = secondary_in_reload; | |
1336 | rld[i].secondary_out_reload = secondary_out_reload; | |
1337 | rld[i].secondary_in_icode = secondary_in_icode; | |
1338 | rld[i].secondary_out_icode = secondary_out_icode; | |
1339 | rld[i].secondary_p = 0; | |
eab89b90 RK |
1340 | |
1341 | n_reloads++; | |
0dadecf6 RK |
1342 | |
1343 | #ifdef SECONDARY_MEMORY_NEEDED | |
71a9b19a RG |
1344 | if (out != 0 |
1345 | && (REG_P (out) | |
1346 | || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out)))) | |
344b78b8 JH |
1347 | && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER |
1348 | && SECONDARY_MEMORY_NEEDED (class, | |
1349 | REGNO_REG_CLASS (reg_or_subregno (out)), | |
0dadecf6 | 1350 | outmode)) |
a8c9daeb | 1351 | get_secondary_mem (out, outmode, opnum, type); |
0dadecf6 | 1352 | #endif |
eab89b90 RK |
1353 | } |
1354 | else | |
1355 | { | |
1356 | /* We are reusing an existing reload, | |
1357 | but we may have additional information for it. | |
1358 | For example, we may now have both IN and OUT | |
1359 | while the old one may have just one of them. */ | |
1360 | ||
6fd5ac08 JW |
1361 | /* The modes can be different. If they are, we want to reload in |
1362 | the larger mode, so that the value is valid for both modes. */ | |
1363 | if (inmode != VOIDmode | |
eceef4c9 BS |
1364 | && GET_MODE_SIZE (inmode) > GET_MODE_SIZE (rld[i].inmode)) |
1365 | rld[i].inmode = inmode; | |
6fd5ac08 | 1366 | if (outmode != VOIDmode |
eceef4c9 BS |
1367 | && GET_MODE_SIZE (outmode) > GET_MODE_SIZE (rld[i].outmode)) |
1368 | rld[i].outmode = outmode; | |
eab89b90 | 1369 | if (in != 0) |
cb2afeb3 | 1370 | { |
506b3b3a | 1371 | rtx in_reg = inloc ? *inloc : 0; |
cb2afeb3 R |
1372 | /* If we merge reloads for two distinct rtl expressions that |
1373 | are identical in content, there might be duplicate address | |
1374 | reloads. Remove the extra set now, so that if we later find | |
1375 | that we can inherit this reload, we can get rid of the | |
b838974e JL |
1376 | address reloads altogether. |
1377 | ||
1378 | Do not do this if both reloads are optional since the result | |
1379 | would be an optional reload which could potentially leave | |
1380 | unresolved address replacements. | |
1381 | ||
1382 | It is not sufficient to call transfer_replacements since | |
1383 | choose_reload_regs will remove the replacements for address | |
1384 | reloads of inherited reloads which results in the same | |
1385 | problem. */ | |
eceef4c9 BS |
1386 | if (rld[i].in != in && rtx_equal_p (in, rld[i].in) |
1387 | && ! (rld[i].optional && optional)) | |
cb2afeb3 R |
1388 | { |
1389 | /* We must keep the address reload with the lower operand | |
1390 | number alive. */ | |
eceef4c9 | 1391 | if (opnum > rld[i].opnum) |
cb2afeb3 R |
1392 | { |
1393 | remove_address_replacements (in); | |
eceef4c9 BS |
1394 | in = rld[i].in; |
1395 | in_reg = rld[i].in_reg; | |
cb2afeb3 R |
1396 | } |
1397 | else | |
eceef4c9 | 1398 | remove_address_replacements (rld[i].in); |
cb2afeb3 | 1399 | } |
eceef4c9 BS |
1400 | rld[i].in = in; |
1401 | rld[i].in_reg = in_reg; | |
cb2afeb3 | 1402 | } |
eab89b90 | 1403 | if (out != 0) |
cb2afeb3 | 1404 | { |
eceef4c9 BS |
1405 | rld[i].out = out; |
1406 | rld[i].out_reg = outloc ? *outloc : 0; | |
cb2afeb3 | 1407 | } |
eceef4c9 BS |
1408 | if (reg_class_subset_p (class, rld[i].class)) |
1409 | rld[i].class = class; | |
1410 | rld[i].optional &= optional; | |
1411 | if (MERGE_TO_OTHER (type, rld[i].when_needed, | |
1412 | opnum, rld[i].opnum)) | |
1413 | rld[i].when_needed = RELOAD_OTHER; | |
1414 | rld[i].opnum = MIN (rld[i].opnum, opnum); | |
eab89b90 RK |
1415 | } |
1416 | ||
e0120d6e | 1417 | /* If the ostensible rtx being reloaded differs from the rtx found |
eab89b90 RK |
1418 | in the location to substitute, this reload is not safe to combine |
1419 | because we cannot reliably tell whether it appears in the insn. */ | |
1420 | ||
1421 | if (in != 0 && in != *inloc) | |
eceef4c9 | 1422 | rld[i].nocombine = 1; |
eab89b90 RK |
1423 | |
1424 | #if 0 | |
1425 | /* This was replaced by changes in find_reloads_address_1 and the new | |
1426 | function inc_for_reload, which go with a new meaning of reload_inc. */ | |
1427 | ||
1428 | /* If this is an IN/OUT reload in an insn that sets the CC, | |
1429 | it must be for an autoincrement. It doesn't work to store | |
1430 | the incremented value after the insn because that would clobber the CC. | |
1431 | So we must do the increment of the value reloaded from, | |
1432 | increment it, store it back, then decrement again. */ | |
1433 | if (out != 0 && sets_cc0_p (PATTERN (this_insn))) | |
1434 | { | |
1435 | out = 0; | |
eceef4c9 BS |
1436 | rld[i].out = 0; |
1437 | rld[i].inc = find_inc_amount (PATTERN (this_insn), in); | |
eab89b90 RK |
1438 | /* If we did not find a nonzero amount-to-increment-by, |
1439 | that contradicts the belief that IN is being incremented | |
1440 | in an address in this insn. */ | |
41374e13 | 1441 | gcc_assert (rld[i].inc != 0); |
eab89b90 RK |
1442 | } |
1443 | #endif | |
1444 | ||
1445 | /* If we will replace IN and OUT with the reload-reg, | |
1446 | record where they are located so that substitution need | |
1447 | not do a tree walk. */ | |
1448 | ||
1449 | if (replace_reloads) | |
1450 | { | |
1451 | if (inloc != 0) | |
1452 | { | |
b3694847 | 1453 | struct replacement *r = &replacements[n_replacements++]; |
eab89b90 RK |
1454 | r->what = i; |
1455 | r->subreg_loc = in_subreg_loc; | |
1456 | r->where = inloc; | |
1457 | r->mode = inmode; | |
1458 | } | |
1459 | if (outloc != 0 && outloc != inloc) | |
1460 | { | |
b3694847 | 1461 | struct replacement *r = &replacements[n_replacements++]; |
eab89b90 RK |
1462 | r->what = i; |
1463 | r->where = outloc; | |
1464 | r->subreg_loc = out_subreg_loc; | |
1465 | r->mode = outmode; | |
1466 | } | |
1467 | } | |
1468 | ||
1469 | /* If this reload is just being introduced and it has both | |
1470 | an incoming quantity and an outgoing quantity that are | |
1471 | supposed to be made to match, see if either one of the two | |
1472 | can serve as the place to reload into. | |
1473 | ||
eceef4c9 | 1474 | If one of them is acceptable, set rld[i].reg_rtx |
eab89b90 RK |
1475 | to that one. */ |
1476 | ||
eceef4c9 | 1477 | if (in != 0 && out != 0 && in != out && rld[i].reg_rtx == 0) |
eab89b90 | 1478 | { |
eceef4c9 BS |
1479 | rld[i].reg_rtx = find_dummy_reload (in, out, inloc, outloc, |
1480 | inmode, outmode, | |
1481 | rld[i].class, i, | |
1482 | earlyclobber_operand_p (out)); | |
eab89b90 RK |
1483 | |
1484 | /* If the outgoing register already contains the same value | |
1485 | as the incoming one, we can dispense with loading it. | |
1486 | The easiest way to tell the caller that is to give a phony | |
1487 | value for the incoming operand (same as outgoing one). */ | |
eceef4c9 | 1488 | if (rld[i].reg_rtx == out |
f8cfc6aa | 1489 | && (REG_P (in) || CONSTANT_P (in)) |
eab89b90 RK |
1490 | && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out), |
1491 | static_reload_reg_p, i, inmode)) | |
eceef4c9 | 1492 | rld[i].in = out; |
eab89b90 RK |
1493 | } |
1494 | ||
1495 | /* If this is an input reload and the operand contains a register that | |
1496 | dies in this insn and is used nowhere else, see if it is the right class | |
1497 | to be used for this reload. Use it if so. (This occurs most commonly | |
1498 | in the case of paradoxical SUBREGs and in-out reloads). We cannot do | |
1499 | this if it is also an output reload that mentions the register unless | |
1500 | the output is a SUBREG that clobbers an entire register. | |
1501 | ||
1502 | Note that the operand might be one of the spill regs, if it is a | |
1503 | pseudo reg and we are in a block where spilling has not taken place. | |
1504 | But if there is no spilling in this block, that is OK. | |
1505 | An explicitly used hard reg cannot be a spill reg. */ | |
1506 | ||
687b527d | 1507 | if (rld[i].reg_rtx == 0 && in != 0 && hard_regs_live_known) |
eab89b90 RK |
1508 | { |
1509 | rtx note; | |
1510 | int regno; | |
d0b6af71 R |
1511 | enum machine_mode rel_mode = inmode; |
1512 | ||
1513 | if (out && GET_MODE_SIZE (outmode) > GET_MODE_SIZE (inmode)) | |
1514 | rel_mode = outmode; | |
eab89b90 RK |
1515 | |
1516 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1517 | if (REG_NOTE_KIND (note) == REG_DEAD | |
f8cfc6aa | 1518 | && REG_P (XEXP (note, 0)) |
eab89b90 RK |
1519 | && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER |
1520 | && reg_mentioned_p (XEXP (note, 0), in) | |
687b527d MM |
1521 | /* Check that we don't use a hardreg for an uninitialized |
1522 | pseudo. See also find_dummy_reload(). */ | |
1523 | && (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER | |
6fb5fa3c | 1524 | || ! bitmap_bit_p (DF_RA_LIVE_OUT (ENTRY_BLOCK_PTR), |
687b527d | 1525 | ORIGINAL_REGNO (XEXP (note, 0)))) |
eab89b90 | 1526 | && ! refers_to_regno_for_reload_p (regno, |
09e18274 RS |
1527 | end_hard_regno (rel_mode, |
1528 | regno), | |
eab89b90 | 1529 | PATTERN (this_insn), inloc) |
05b4ec4f RS |
1530 | /* If this is also an output reload, IN cannot be used as |
1531 | the reload register if it is set in this insn unless IN | |
1532 | is also OUT. */ | |
1533 | && (out == 0 || in == out | |
1534 | || ! hard_reg_set_here_p (regno, | |
09e18274 | 1535 | end_hard_regno (rel_mode, regno), |
05b4ec4f RS |
1536 | PATTERN (this_insn))) |
1537 | /* ??? Why is this code so different from the previous? | |
1538 | Is there any simple coherent way to describe the two together? | |
1539 | What's going on here. */ | |
eab89b90 RK |
1540 | && (in != out |
1541 | || (GET_CODE (in) == SUBREG | |
1542 | && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1)) | |
1543 | / UNITS_PER_WORD) | |
1544 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1545 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
1546 | /* Make sure the operand fits in the reg that dies. */ | |
d0b6af71 R |
1547 | && (GET_MODE_SIZE (rel_mode) |
1548 | <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))) | |
eab89b90 | 1549 | && HARD_REGNO_MODE_OK (regno, inmode) |
96b42f4c | 1550 | && HARD_REGNO_MODE_OK (regno, outmode)) |
eab89b90 | 1551 | { |
db30db99 | 1552 | unsigned int offs; |
66fd46b6 JH |
1553 | unsigned int nregs = MAX (hard_regno_nregs[regno][inmode], |
1554 | hard_regno_nregs[regno][outmode]); | |
db30db99 | 1555 | |
96b42f4c BS |
1556 | for (offs = 0; offs < nregs; offs++) |
1557 | if (fixed_regs[regno + offs] | |
1558 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1559 | regno + offs)) | |
1560 | break; | |
1561 | ||
35d6034b R |
1562 | if (offs == nregs |
1563 | && (! (refers_to_regno_for_reload_p | |
09e18274 | 1564 | (regno, end_hard_regno (inmode, regno), in, (rtx *) 0)) |
35d6034b | 1565 | || can_reload_into (in, regno, inmode))) |
96b42f4c | 1566 | { |
d0b6af71 | 1567 | rld[i].reg_rtx = gen_rtx_REG (rel_mode, regno); |
96b42f4c BS |
1568 | break; |
1569 | } | |
eab89b90 RK |
1570 | } |
1571 | } | |
1572 | ||
1573 | if (out) | |
1574 | output_reloadnum = i; | |
1575 | ||
1576 | return i; | |
1577 | } | |
1578 | ||
1579 | /* Record an additional place we must replace a value | |
1580 | for which we have already recorded a reload. | |
1581 | RELOADNUM is the value returned by push_reload | |
1582 | when the reload was recorded. | |
1583 | This is used in insn patterns that use match_dup. */ | |
1584 | ||
1585 | static void | |
0c20a65f | 1586 | push_replacement (rtx *loc, int reloadnum, enum machine_mode mode) |
eab89b90 RK |
1587 | { |
1588 | if (replace_reloads) | |
1589 | { | |
b3694847 | 1590 | struct replacement *r = &replacements[n_replacements++]; |
eab89b90 RK |
1591 | r->what = reloadnum; |
1592 | r->where = loc; | |
1593 | r->subreg_loc = 0; | |
1594 | r->mode = mode; | |
1595 | } | |
1596 | } | |
6cabe79e UW |
1597 | |
1598 | /* Duplicate any replacement we have recorded to apply at | |
1599 | location ORIG_LOC to also be performed at DUP_LOC. | |
1600 | This is used in insn patterns that use match_dup. */ | |
1601 | ||
1602 | static void | |
0c20a65f | 1603 | dup_replacements (rtx *dup_loc, rtx *orig_loc) |
6cabe79e UW |
1604 | { |
1605 | int i, n = n_replacements; | |
1606 | ||
1607 | for (i = 0; i < n; i++) | |
1608 | { | |
1609 | struct replacement *r = &replacements[i]; | |
1610 | if (r->where == orig_loc) | |
1611 | push_replacement (dup_loc, r->what, r->mode); | |
1612 | } | |
1613 | } | |
eab89b90 | 1614 | \f |
a8c9daeb RK |
1615 | /* Transfer all replacements that used to be in reload FROM to be in |
1616 | reload TO. */ | |
1617 | ||
1618 | void | |
0c20a65f | 1619 | transfer_replacements (int to, int from) |
a8c9daeb RK |
1620 | { |
1621 | int i; | |
1622 | ||
1623 | for (i = 0; i < n_replacements; i++) | |
1624 | if (replacements[i].what == from) | |
1625 | replacements[i].what = to; | |
1626 | } | |
1627 | \f | |
cb2afeb3 R |
1628 | /* IN_RTX is the value loaded by a reload that we now decided to inherit, |
1629 | or a subpart of it. If we have any replacements registered for IN_RTX, | |
1630 | cancel the reloads that were supposed to load them. | |
40f03658 | 1631 | Return nonzero if we canceled any reloads. */ |
cb2afeb3 | 1632 | int |
0c20a65f | 1633 | remove_address_replacements (rtx in_rtx) |
029b38ff R |
1634 | { |
1635 | int i, j; | |
cb2afeb3 R |
1636 | char reload_flags[MAX_RELOADS]; |
1637 | int something_changed = 0; | |
029b38ff | 1638 | |
961192e1 | 1639 | memset (reload_flags, 0, sizeof reload_flags); |
029b38ff R |
1640 | for (i = 0, j = 0; i < n_replacements; i++) |
1641 | { | |
cb2afeb3 R |
1642 | if (loc_mentioned_in_p (replacements[i].where, in_rtx)) |
1643 | reload_flags[replacements[i].what] |= 1; | |
1644 | else | |
1645 | { | |
1646 | replacements[j++] = replacements[i]; | |
1647 | reload_flags[replacements[i].what] |= 2; | |
1648 | } | |
1649 | } | |
1650 | /* Note that the following store must be done before the recursive calls. */ | |
1651 | n_replacements = j; | |
1652 | ||
1653 | for (i = n_reloads - 1; i >= 0; i--) | |
1654 | { | |
1655 | if (reload_flags[i] == 1) | |
1656 | { | |
1657 | deallocate_reload_reg (i); | |
eceef4c9 BS |
1658 | remove_address_replacements (rld[i].in); |
1659 | rld[i].in = 0; | |
cb2afeb3 R |
1660 | something_changed = 1; |
1661 | } | |
1662 | } | |
1663 | return something_changed; | |
1664 | } | |
029b38ff | 1665 | \f |
eab89b90 RK |
1666 | /* If there is only one output reload, and it is not for an earlyclobber |
1667 | operand, try to combine it with a (logically unrelated) input reload | |
1668 | to reduce the number of reload registers needed. | |
1669 | ||
1670 | This is safe if the input reload does not appear in | |
1671 | the value being output-reloaded, because this implies | |
1672 | it is not needed any more once the original insn completes. | |
1673 | ||
1674 | If that doesn't work, see we can use any of the registers that | |
1675 | die in this insn as a reload register. We can if it is of the right | |
1676 | class and does not appear in the value being output-reloaded. */ | |
1677 | ||
1678 | static void | |
0c20a65f | 1679 | combine_reloads (void) |
eab89b90 RK |
1680 | { |
1681 | int i; | |
1682 | int output_reload = -1; | |
8922eb5b | 1683 | int secondary_out = -1; |
eab89b90 RK |
1684 | rtx note; |
1685 | ||
1686 | /* Find the output reload; return unless there is exactly one | |
1687 | and that one is mandatory. */ | |
1688 | ||
1689 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 1690 | if (rld[i].out != 0) |
eab89b90 RK |
1691 | { |
1692 | if (output_reload >= 0) | |
1693 | return; | |
1694 | output_reload = i; | |
1695 | } | |
1696 | ||
eceef4c9 | 1697 | if (output_reload < 0 || rld[output_reload].optional) |
eab89b90 RK |
1698 | return; |
1699 | ||
1700 | /* An input-output reload isn't combinable. */ | |
1701 | ||
eceef4c9 | 1702 | if (rld[output_reload].in != 0) |
eab89b90 RK |
1703 | return; |
1704 | ||
6dc42e49 | 1705 | /* If this reload is for an earlyclobber operand, we can't do anything. */ |
eceef4c9 | 1706 | if (earlyclobber_operand_p (rld[output_reload].out)) |
4644aad4 | 1707 | return; |
eab89b90 | 1708 | |
6b3736a1 | 1709 | /* If there is a reload for part of the address of this operand, we would |
9f5ed61a | 1710 | need to change it to RELOAD_FOR_OTHER_ADDRESS. But that would extend |
6b3736a1 RK |
1711 | its life to the point where doing this combine would not lower the |
1712 | number of spill registers needed. */ | |
1713 | for (i = 0; i < n_reloads; i++) | |
1714 | if ((rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
1715 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
1716 | && rld[i].opnum == rld[output_reload].opnum) | |
1717 | return; | |
1718 | ||
eab89b90 RK |
1719 | /* Check each input reload; can we combine it? */ |
1720 | ||
1721 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 1722 | if (rld[i].in && ! rld[i].optional && ! rld[i].nocombine |
eab89b90 | 1723 | /* Life span of this reload must not extend past main insn. */ |
eceef4c9 BS |
1724 | && rld[i].when_needed != RELOAD_FOR_OUTPUT_ADDRESS |
1725 | && rld[i].when_needed != RELOAD_FOR_OUTADDR_ADDRESS | |
1726 | && rld[i].when_needed != RELOAD_OTHER | |
1727 | && (CLASS_MAX_NREGS (rld[i].class, rld[i].inmode) | |
1728 | == CLASS_MAX_NREGS (rld[output_reload].class, | |
1729 | rld[output_reload].outmode)) | |
1730 | && rld[i].inc == 0 | |
1731 | && rld[i].reg_rtx == 0 | |
a8c9daeb | 1732 | #ifdef SECONDARY_MEMORY_NEEDED |
9ec7078b RK |
1733 | /* Don't combine two reloads with different secondary |
1734 | memory locations. */ | |
eceef4c9 BS |
1735 | && (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum] == 0 |
1736 | || secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum] == 0 | |
1737 | || rtx_equal_p (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum], | |
1738 | secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum])) | |
a8c9daeb | 1739 | #endif |
e9a25f70 | 1740 | && (SMALL_REGISTER_CLASSES |
eceef4c9 BS |
1741 | ? (rld[i].class == rld[output_reload].class) |
1742 | : (reg_class_subset_p (rld[i].class, | |
1743 | rld[output_reload].class) | |
1744 | || reg_class_subset_p (rld[output_reload].class, | |
1745 | rld[i].class))) | |
1746 | && (MATCHES (rld[i].in, rld[output_reload].out) | |
eab89b90 RK |
1747 | /* Args reversed because the first arg seems to be |
1748 | the one that we imagine being modified | |
1749 | while the second is the one that might be affected. */ | |
eceef4c9 BS |
1750 | || (! reg_overlap_mentioned_for_reload_p (rld[output_reload].out, |
1751 | rld[i].in) | |
eab89b90 RK |
1752 | /* However, if the input is a register that appears inside |
1753 | the output, then we also can't share. | |
1754 | Imagine (set (mem (reg 69)) (plus (reg 69) ...)). | |
1755 | If the same reload reg is used for both reg 69 and the | |
1756 | result to be stored in memory, then that result | |
1757 | will clobber the address of the memory ref. */ | |
f8cfc6aa | 1758 | && ! (REG_P (rld[i].in) |
eceef4c9 BS |
1759 | && reg_overlap_mentioned_for_reload_p (rld[i].in, |
1760 | rld[output_reload].out)))) | |
4bf1d92e JH |
1761 | && ! reload_inner_reg_of_subreg (rld[i].in, rld[i].inmode, |
1762 | rld[i].when_needed != RELOAD_FOR_INPUT) | |
eceef4c9 | 1763 | && (reg_class_size[(int) rld[i].class] |
e9a25f70 | 1764 | || SMALL_REGISTER_CLASSES) |
a8c9daeb RK |
1765 | /* We will allow making things slightly worse by combining an |
1766 | input and an output, but no worse than that. */ | |
eceef4c9 BS |
1767 | && (rld[i].when_needed == RELOAD_FOR_INPUT |
1768 | || rld[i].when_needed == RELOAD_FOR_OUTPUT)) | |
eab89b90 RK |
1769 | { |
1770 | int j; | |
1771 | ||
1772 | /* We have found a reload to combine with! */ | |
eceef4c9 BS |
1773 | rld[i].out = rld[output_reload].out; |
1774 | rld[i].out_reg = rld[output_reload].out_reg; | |
1775 | rld[i].outmode = rld[output_reload].outmode; | |
eab89b90 | 1776 | /* Mark the old output reload as inoperative. */ |
eceef4c9 | 1777 | rld[output_reload].out = 0; |
eab89b90 | 1778 | /* The combined reload is needed for the entire insn. */ |
eceef4c9 | 1779 | rld[i].when_needed = RELOAD_OTHER; |
0f41302f | 1780 | /* If the output reload had a secondary reload, copy it. */ |
eceef4c9 | 1781 | if (rld[output_reload].secondary_out_reload != -1) |
9ec7078b | 1782 | { |
eceef4c9 BS |
1783 | rld[i].secondary_out_reload |
1784 | = rld[output_reload].secondary_out_reload; | |
1785 | rld[i].secondary_out_icode | |
1786 | = rld[output_reload].secondary_out_icode; | |
9ec7078b RK |
1787 | } |
1788 | ||
a8c9daeb RK |
1789 | #ifdef SECONDARY_MEMORY_NEEDED |
1790 | /* Copy any secondary MEM. */ | |
eceef4c9 BS |
1791 | if (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum] != 0) |
1792 | secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum] | |
1793 | = secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum]; | |
a8c9daeb | 1794 | #endif |
0f41302f | 1795 | /* If required, minimize the register class. */ |
eceef4c9 BS |
1796 | if (reg_class_subset_p (rld[output_reload].class, |
1797 | rld[i].class)) | |
1798 | rld[i].class = rld[output_reload].class; | |
eab89b90 RK |
1799 | |
1800 | /* Transfer all replacements from the old reload to the combined. */ | |
1801 | for (j = 0; j < n_replacements; j++) | |
1802 | if (replacements[j].what == output_reload) | |
1803 | replacements[j].what = i; | |
1804 | ||
1805 | return; | |
1806 | } | |
1807 | ||
1808 | /* If this insn has only one operand that is modified or written (assumed | |
1809 | to be the first), it must be the one corresponding to this reload. It | |
1810 | is safe to use anything that dies in this insn for that output provided | |
1811 | that it does not occur in the output (we already know it isn't an | |
1812 | earlyclobber. If this is an asm insn, give up. */ | |
1813 | ||
1f9a0ec2 | 1814 | if (INSN_CODE (this_insn) == -1) |
eab89b90 RK |
1815 | return; |
1816 | ||
a995e389 RH |
1817 | for (i = 1; i < insn_data[INSN_CODE (this_insn)].n_operands; i++) |
1818 | if (insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '=' | |
1819 | || insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '+') | |
eab89b90 RK |
1820 | return; |
1821 | ||
1822 | /* See if some hard register that dies in this insn and is not used in | |
1823 | the output is the right class. Only works if the register we pick | |
1824 | up can fully hold our output reload. */ | |
1825 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1826 | if (REG_NOTE_KIND (note) == REG_DEAD | |
f8cfc6aa | 1827 | && REG_P (XEXP (note, 0)) |
bfa30b22 | 1828 | && ! reg_overlap_mentioned_for_reload_p (XEXP (note, 0), |
eceef4c9 | 1829 | rld[output_reload].out) |
eab89b90 | 1830 | && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER |
eceef4c9 BS |
1831 | && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), rld[output_reload].outmode) |
1832 | && TEST_HARD_REG_BIT (reg_class_contents[(int) rld[output_reload].class], | |
eab89b90 | 1833 | REGNO (XEXP (note, 0))) |
66fd46b6 JH |
1834 | && (hard_regno_nregs[REGNO (XEXP (note, 0))][rld[output_reload].outmode] |
1835 | <= hard_regno_nregs[REGNO (XEXP (note, 0))][GET_MODE (XEXP (note, 0))]) | |
8922eb5b RK |
1836 | /* Ensure that a secondary or tertiary reload for this output |
1837 | won't want this register. */ | |
eceef4c9 | 1838 | && ((secondary_out = rld[output_reload].secondary_out_reload) == -1 |
05d10675 | 1839 | || (! (TEST_HARD_REG_BIT |
eceef4c9 | 1840 | (reg_class_contents[(int) rld[secondary_out].class], |
05d10675 | 1841 | REGNO (XEXP (note, 0)))) |
eceef4c9 | 1842 | && ((secondary_out = rld[secondary_out].secondary_out_reload) == -1 |
8922eb5b | 1843 | || ! (TEST_HARD_REG_BIT |
eceef4c9 | 1844 | (reg_class_contents[(int) rld[secondary_out].class], |
8922eb5b | 1845 | REGNO (XEXP (note, 0))))))) |
c1673e1b BS |
1846 | && ! fixed_regs[REGNO (XEXP (note, 0))] |
1847 | /* Check that we don't use a hardreg for an uninitialized | |
1848 | pseudo. See also find_dummy_reload(). */ | |
1849 | && (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER | |
6fb5fa3c | 1850 | || ! bitmap_bit_p (DF_LR_OUT (ENTRY_BLOCK_PTR), |
c1673e1b | 1851 | ORIGINAL_REGNO (XEXP (note, 0))))) |
eab89b90 | 1852 | { |
eceef4c9 BS |
1853 | rld[output_reload].reg_rtx |
1854 | = gen_rtx_REG (rld[output_reload].outmode, | |
38a448ca | 1855 | REGNO (XEXP (note, 0))); |
eab89b90 RK |
1856 | return; |
1857 | } | |
1858 | } | |
1859 | \f | |
1860 | /* Try to find a reload register for an in-out reload (expressions IN and OUT). | |
1861 | See if one of IN and OUT is a register that may be used; | |
1862 | this is desirable since a spill-register won't be needed. | |
1863 | If so, return the register rtx that proves acceptable. | |
1864 | ||
1865 | INLOC and OUTLOC are locations where IN and OUT appear in the insn. | |
1866 | CLASS is the register class required for the reload. | |
1867 | ||
1868 | If FOR_REAL is >= 0, it is the number of the reload, | |
1869 | and in some cases when it can be discovered that OUT doesn't need | |
eceef4c9 | 1870 | to be computed, clear out rld[FOR_REAL].out. |
eab89b90 RK |
1871 | |
1872 | If FOR_REAL is -1, this should not be done, because this call | |
189086f9 RK |
1873 | is just to see if a register can be found, not to find and install it. |
1874 | ||
40f03658 | 1875 | EARLYCLOBBER is nonzero if OUT is an earlyclobber operand. This |
189086f9 RK |
1876 | puts an additional constraint on being able to use IN for OUT since |
1877 | IN must not appear elsewhere in the insn (it is assumed that IN itself | |
1878 | is safe from the earlyclobber). */ | |
eab89b90 RK |
1879 | |
1880 | static rtx | |
0c20a65f AJ |
1881 | find_dummy_reload (rtx real_in, rtx real_out, rtx *inloc, rtx *outloc, |
1882 | enum machine_mode inmode, enum machine_mode outmode, | |
1883 | enum reg_class class, int for_real, int earlyclobber) | |
eab89b90 RK |
1884 | { |
1885 | rtx in = real_in; | |
1886 | rtx out = real_out; | |
1887 | int in_offset = 0; | |
1888 | int out_offset = 0; | |
1889 | rtx value = 0; | |
1890 | ||
1891 | /* If operands exceed a word, we can't use either of them | |
1892 | unless they have the same size. */ | |
36b50568 RS |
1893 | if (GET_MODE_SIZE (outmode) != GET_MODE_SIZE (inmode) |
1894 | && (GET_MODE_SIZE (outmode) > UNITS_PER_WORD | |
1895 | || GET_MODE_SIZE (inmode) > UNITS_PER_WORD)) | |
eab89b90 RK |
1896 | return 0; |
1897 | ||
ddef6bc7 JJ |
1898 | /* Note that {in,out}_offset are needed only when 'in' or 'out' |
1899 | respectively refers to a hard register. */ | |
1900 | ||
eab89b90 RK |
1901 | /* Find the inside of any subregs. */ |
1902 | while (GET_CODE (out) == SUBREG) | |
1903 | { | |
f8cfc6aa | 1904 | if (REG_P (SUBREG_REG (out)) |
ddef6bc7 JJ |
1905 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER) |
1906 | out_offset += subreg_regno_offset (REGNO (SUBREG_REG (out)), | |
1907 | GET_MODE (SUBREG_REG (out)), | |
1908 | SUBREG_BYTE (out), | |
1909 | GET_MODE (out)); | |
eab89b90 RK |
1910 | out = SUBREG_REG (out); |
1911 | } | |
1912 | while (GET_CODE (in) == SUBREG) | |
1913 | { | |
f8cfc6aa | 1914 | if (REG_P (SUBREG_REG (in)) |
ddef6bc7 JJ |
1915 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER) |
1916 | in_offset += subreg_regno_offset (REGNO (SUBREG_REG (in)), | |
1917 | GET_MODE (SUBREG_REG (in)), | |
1918 | SUBREG_BYTE (in), | |
1919 | GET_MODE (in)); | |
eab89b90 RK |
1920 | in = SUBREG_REG (in); |
1921 | } | |
1922 | ||
1923 | /* Narrow down the reg class, the same way push_reload will; | |
1924 | otherwise we might find a dummy now, but push_reload won't. */ | |
b5c82fa1 PB |
1925 | { |
1926 | enum reg_class preferred_class = PREFERRED_RELOAD_CLASS (in, class); | |
e17e34d8 | 1927 | if (preferred_class != NO_REGS) |
b5c82fa1 PB |
1928 | class = preferred_class; |
1929 | } | |
eab89b90 RK |
1930 | |
1931 | /* See if OUT will do. */ | |
f8cfc6aa | 1932 | if (REG_P (out) |
eab89b90 RK |
1933 | && REGNO (out) < FIRST_PSEUDO_REGISTER) |
1934 | { | |
770ae6cc | 1935 | unsigned int regno = REGNO (out) + out_offset; |
66fd46b6 | 1936 | unsigned int nwords = hard_regno_nregs[regno][outmode]; |
d3b9996a | 1937 | rtx saved_rtx; |
eab89b90 RK |
1938 | |
1939 | /* When we consider whether the insn uses OUT, | |
1940 | ignore references within IN. They don't prevent us | |
1941 | from copying IN into OUT, because those refs would | |
1942 | move into the insn that reloads IN. | |
1943 | ||
1944 | However, we only ignore IN in its role as this reload. | |
1945 | If the insn uses IN elsewhere and it contains OUT, | |
1946 | that counts. We can't be sure it's the "same" operand | |
1947 | so it might not go through this reload. */ | |
d3b9996a | 1948 | saved_rtx = *inloc; |
eab89b90 RK |
1949 | *inloc = const0_rtx; |
1950 | ||
1951 | if (regno < FIRST_PSEUDO_REGISTER | |
05fa709d | 1952 | && HARD_REGNO_MODE_OK (regno, outmode) |
eab89b90 RK |
1953 | && ! refers_to_regno_for_reload_p (regno, regno + nwords, |
1954 | PATTERN (this_insn), outloc)) | |
1955 | { | |
770ae6cc RK |
1956 | unsigned int i; |
1957 | ||
eab89b90 RK |
1958 | for (i = 0; i < nwords; i++) |
1959 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
1960 | regno + i)) | |
1961 | break; | |
1962 | ||
1963 | if (i == nwords) | |
1964 | { | |
f8cfc6aa | 1965 | if (REG_P (real_out)) |
eab89b90 RK |
1966 | value = real_out; |
1967 | else | |
38a448ca | 1968 | value = gen_rtx_REG (outmode, regno); |
eab89b90 RK |
1969 | } |
1970 | } | |
1971 | ||
d3b9996a | 1972 | *inloc = saved_rtx; |
eab89b90 RK |
1973 | } |
1974 | ||
1975 | /* Consider using IN if OUT was not acceptable | |
1976 | or if OUT dies in this insn (like the quotient in a divmod insn). | |
1977 | We can't use IN unless it is dies in this insn, | |
1978 | which means we must know accurately which hard regs are live. | |
189086f9 RK |
1979 | Also, the result can't go in IN if IN is used within OUT, |
1980 | or if OUT is an earlyclobber and IN appears elsewhere in the insn. */ | |
eab89b90 | 1981 | if (hard_regs_live_known |
f8cfc6aa | 1982 | && REG_P (in) |
eab89b90 RK |
1983 | && REGNO (in) < FIRST_PSEUDO_REGISTER |
1984 | && (value == 0 | |
1985 | || find_reg_note (this_insn, REG_UNUSED, real_out)) | |
1986 | && find_reg_note (this_insn, REG_DEAD, real_in) | |
1987 | && !fixed_regs[REGNO (in)] | |
36b50568 RS |
1988 | && HARD_REGNO_MODE_OK (REGNO (in), |
1989 | /* The only case where out and real_out might | |
1990 | have different modes is where real_out | |
1991 | is a subreg, and in that case, out | |
1992 | has a real mode. */ | |
1993 | (GET_MODE (out) != VOIDmode | |
687b527d MM |
1994 | ? GET_MODE (out) : outmode)) |
1995 | /* But only do all this if we can be sure, that this input | |
1996 | operand doesn't correspond with an uninitialized pseudoreg. | |
1997 | global can assign some hardreg to it, which is the same as | |
1998 | a different pseudo also currently live (as it can ignore the | |
1999 | conflict). So we never must introduce writes to such hardregs, | |
2000 | as they would clobber the other live pseudo using the same. | |
2001 | See also PR20973. */ | |
2002 | && (ORIGINAL_REGNO (in) < FIRST_PSEUDO_REGISTER | |
6fb5fa3c | 2003 | || ! bitmap_bit_p (DF_RA_LIVE_OUT (ENTRY_BLOCK_PTR), |
687b527d | 2004 | ORIGINAL_REGNO (in)))) |
eab89b90 | 2005 | { |
770ae6cc | 2006 | unsigned int regno = REGNO (in) + in_offset; |
66fd46b6 | 2007 | unsigned int nwords = hard_regno_nregs[regno][inmode]; |
eab89b90 | 2008 | |
f4f4d0f8 | 2009 | if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, (rtx*) 0) |
eab89b90 | 2010 | && ! hard_reg_set_here_p (regno, regno + nwords, |
189086f9 RK |
2011 | PATTERN (this_insn)) |
2012 | && (! earlyclobber | |
2013 | || ! refers_to_regno_for_reload_p (regno, regno + nwords, | |
2014 | PATTERN (this_insn), inloc))) | |
eab89b90 | 2015 | { |
770ae6cc RK |
2016 | unsigned int i; |
2017 | ||
eab89b90 RK |
2018 | for (i = 0; i < nwords; i++) |
2019 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], | |
2020 | regno + i)) | |
2021 | break; | |
2022 | ||
2023 | if (i == nwords) | |
2024 | { | |
2025 | /* If we were going to use OUT as the reload reg | |
2026 | and changed our mind, it means OUT is a dummy that | |
2027 | dies here. So don't bother copying value to it. */ | |
2028 | if (for_real >= 0 && value == real_out) | |
eceef4c9 | 2029 | rld[for_real].out = 0; |
f8cfc6aa | 2030 | if (REG_P (real_in)) |
eab89b90 RK |
2031 | value = real_in; |
2032 | else | |
38a448ca | 2033 | value = gen_rtx_REG (inmode, regno); |
eab89b90 RK |
2034 | } |
2035 | } | |
2036 | } | |
2037 | ||
2038 | return value; | |
2039 | } | |
2040 | \f | |
2041 | /* This page contains subroutines used mainly for determining | |
2042 | whether the IN or an OUT of a reload can serve as the | |
2043 | reload register. */ | |
2044 | ||
4644aad4 RK |
2045 | /* Return 1 if X is an operand of an insn that is being earlyclobbered. */ |
2046 | ||
09a308fe | 2047 | int |
0c20a65f | 2048 | earlyclobber_operand_p (rtx x) |
4644aad4 RK |
2049 | { |
2050 | int i; | |
2051 | ||
2052 | for (i = 0; i < n_earlyclobbers; i++) | |
2053 | if (reload_earlyclobbers[i] == x) | |
2054 | return 1; | |
2055 | ||
2056 | return 0; | |
2057 | } | |
2058 | ||
eab89b90 RK |
2059 | /* Return 1 if expression X alters a hard reg in the range |
2060 | from BEG_REGNO (inclusive) to END_REGNO (exclusive), | |
2061 | either explicitly or in the guise of a pseudo-reg allocated to REGNO. | |
2062 | X should be the body of an instruction. */ | |
2063 | ||
2064 | static int | |
0c20a65f | 2065 | hard_reg_set_here_p (unsigned int beg_regno, unsigned int end_regno, rtx x) |
eab89b90 RK |
2066 | { |
2067 | if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
2068 | { | |
b3694847 | 2069 | rtx op0 = SET_DEST (x); |
770ae6cc | 2070 | |
eab89b90 RK |
2071 | while (GET_CODE (op0) == SUBREG) |
2072 | op0 = SUBREG_REG (op0); | |
f8cfc6aa | 2073 | if (REG_P (op0)) |
eab89b90 | 2074 | { |
770ae6cc RK |
2075 | unsigned int r = REGNO (op0); |
2076 | ||
eab89b90 RK |
2077 | /* See if this reg overlaps range under consideration. */ |
2078 | if (r < end_regno | |
09e18274 | 2079 | && end_hard_regno (GET_MODE (op0), r) > beg_regno) |
eab89b90 RK |
2080 | return 1; |
2081 | } | |
2082 | } | |
2083 | else if (GET_CODE (x) == PARALLEL) | |
2084 | { | |
b3694847 | 2085 | int i = XVECLEN (x, 0) - 1; |
770ae6cc | 2086 | |
eab89b90 RK |
2087 | for (; i >= 0; i--) |
2088 | if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i))) | |
2089 | return 1; | |
2090 | } | |
2091 | ||
2092 | return 0; | |
2093 | } | |
2094 | ||
2095 | /* Return 1 if ADDR is a valid memory address for mode MODE, | |
2096 | and check that each pseudo reg has the proper kind of | |
2097 | hard reg. */ | |
2098 | ||
2099 | int | |
0c20a65f | 2100 | strict_memory_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx addr) |
eab89b90 RK |
2101 | { |
2102 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); | |
2103 | return 0; | |
2104 | ||
2105 | win: | |
2106 | return 1; | |
2107 | } | |
eab89b90 RK |
2108 | \f |
2109 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
2110 | if they are the same hard reg, and has special hacks for | |
2111 | autoincrement and autodecrement. | |
2112 | This is specifically intended for find_reloads to use | |
2113 | in determining whether two operands match. | |
2114 | X is the operand whose number is the lower of the two. | |
2115 | ||
2116 | The value is 2 if Y contains a pre-increment that matches | |
2117 | a non-incrementing address in X. */ | |
2118 | ||
2119 | /* ??? To be completely correct, we should arrange to pass | |
2120 | for X the output operand and for Y the input operand. | |
2121 | For now, we assume that the output operand has the lower number | |
2122 | because that is natural in (SET output (... input ...)). */ | |
2123 | ||
2124 | int | |
0c20a65f | 2125 | operands_match_p (rtx x, rtx y) |
eab89b90 | 2126 | { |
b3694847 SS |
2127 | int i; |
2128 | RTX_CODE code = GET_CODE (x); | |
2129 | const char *fmt; | |
eab89b90 | 2130 | int success_2; |
05d10675 | 2131 | |
eab89b90 RK |
2132 | if (x == y) |
2133 | return 1; | |
f8cfc6aa JQ |
2134 | if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) |
2135 | && (REG_P (y) || (GET_CODE (y) == SUBREG | |
2136 | && REG_P (SUBREG_REG (y))))) | |
eab89b90 | 2137 | { |
b3694847 | 2138 | int j; |
eab89b90 RK |
2139 | |
2140 | if (code == SUBREG) | |
2141 | { | |
2142 | i = REGNO (SUBREG_REG (x)); | |
2143 | if (i >= FIRST_PSEUDO_REGISTER) | |
2144 | goto slow; | |
ddef6bc7 JJ |
2145 | i += subreg_regno_offset (REGNO (SUBREG_REG (x)), |
2146 | GET_MODE (SUBREG_REG (x)), | |
2147 | SUBREG_BYTE (x), | |
2148 | GET_MODE (x)); | |
eab89b90 RK |
2149 | } |
2150 | else | |
2151 | i = REGNO (x); | |
2152 | ||
2153 | if (GET_CODE (y) == SUBREG) | |
2154 | { | |
2155 | j = REGNO (SUBREG_REG (y)); | |
2156 | if (j >= FIRST_PSEUDO_REGISTER) | |
2157 | goto slow; | |
ddef6bc7 JJ |
2158 | j += subreg_regno_offset (REGNO (SUBREG_REG (y)), |
2159 | GET_MODE (SUBREG_REG (y)), | |
2160 | SUBREG_BYTE (y), | |
2161 | GET_MODE (y)); | |
eab89b90 RK |
2162 | } |
2163 | else | |
2164 | j = REGNO (y); | |
2165 | ||
dca52d80 | 2166 | /* On a WORDS_BIG_ENDIAN machine, point to the last register of a |
b436d712 DE |
2167 | multiple hard register group of scalar integer registers, so that |
2168 | for example (reg:DI 0) and (reg:SI 1) will be considered the same | |
2169 | register. */ | |
dca52d80 | 2170 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD |
b436d712 | 2171 | && SCALAR_INT_MODE_P (GET_MODE (x)) |
dca52d80 | 2172 | && i < FIRST_PSEUDO_REGISTER) |
66fd46b6 | 2173 | i += hard_regno_nregs[i][GET_MODE (x)] - 1; |
dca52d80 | 2174 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (y)) > UNITS_PER_WORD |
b436d712 | 2175 | && SCALAR_INT_MODE_P (GET_MODE (y)) |
dca52d80 | 2176 | && j < FIRST_PSEUDO_REGISTER) |
66fd46b6 | 2177 | j += hard_regno_nregs[j][GET_MODE (y)] - 1; |
dca52d80 | 2178 | |
eab89b90 RK |
2179 | return i == j; |
2180 | } | |
2181 | /* If two operands must match, because they are really a single | |
2182 | operand of an assembler insn, then two postincrements are invalid | |
2183 | because the assembler insn would increment only once. | |
09da1532 | 2184 | On the other hand, a postincrement matches ordinary indexing |
eab89b90 | 2185 | if the postincrement is the output operand. */ |
4b983fdc | 2186 | if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) |
eab89b90 RK |
2187 | return operands_match_p (XEXP (x, 0), y); |
2188 | /* Two preincrements are invalid | |
2189 | because the assembler insn would increment only once. | |
09da1532 | 2190 | On the other hand, a preincrement matches ordinary indexing |
eab89b90 RK |
2191 | if the preincrement is the input operand. |
2192 | In this case, return 2, since some callers need to do special | |
2193 | things when this happens. */ | |
4b983fdc RH |
2194 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC |
2195 | || GET_CODE (y) == PRE_MODIFY) | |
eab89b90 RK |
2196 | return operands_match_p (x, XEXP (y, 0)) ? 2 : 0; |
2197 | ||
2198 | slow: | |
2199 | ||
37cf6116 RH |
2200 | /* Now we have disposed of all the cases in which different rtx codes |
2201 | can match. */ | |
eab89b90 RK |
2202 | if (code != GET_CODE (y)) |
2203 | return 0; | |
eab89b90 RK |
2204 | |
2205 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
eab89b90 RK |
2206 | if (GET_MODE (x) != GET_MODE (y)) |
2207 | return 0; | |
2208 | ||
37cf6116 RH |
2209 | switch (code) |
2210 | { | |
2211 | case CONST_INT: | |
2212 | case CONST_DOUBLE: | |
2213 | return 0; | |
2214 | ||
2215 | case LABEL_REF: | |
2216 | return XEXP (x, 0) == XEXP (y, 0); | |
2217 | case SYMBOL_REF: | |
2218 | return XSTR (x, 0) == XSTR (y, 0); | |
2219 | ||
2220 | default: | |
2221 | break; | |
2222 | } | |
2223 | ||
eab89b90 RK |
2224 | /* Compare the elements. If any pair of corresponding elements |
2225 | fail to match, return 0 for the whole things. */ | |
2226 | ||
2227 | success_2 = 0; | |
2228 | fmt = GET_RTX_FORMAT (code); | |
2229 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2230 | { | |
91bb873f | 2231 | int val, j; |
eab89b90 RK |
2232 | switch (fmt[i]) |
2233 | { | |
fb3821f7 CH |
2234 | case 'w': |
2235 | if (XWINT (x, i) != XWINT (y, i)) | |
2236 | return 0; | |
2237 | break; | |
2238 | ||
eab89b90 RK |
2239 | case 'i': |
2240 | if (XINT (x, i) != XINT (y, i)) | |
2241 | return 0; | |
2242 | break; | |
2243 | ||
2244 | case 'e': | |
2245 | val = operands_match_p (XEXP (x, i), XEXP (y, i)); | |
2246 | if (val == 0) | |
2247 | return 0; | |
2248 | /* If any subexpression returns 2, | |
2249 | we should return 2 if we are successful. */ | |
2250 | if (val == 2) | |
2251 | success_2 = 1; | |
2252 | break; | |
2253 | ||
2254 | case '0': | |
2255 | break; | |
2256 | ||
91bb873f RH |
2257 | case 'E': |
2258 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
2259 | return 0; | |
2260 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
2261 | { | |
2262 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j)); | |
2263 | if (val == 0) | |
2264 | return 0; | |
2265 | if (val == 2) | |
2266 | success_2 = 1; | |
2267 | } | |
2268 | break; | |
2269 | ||
eab89b90 RK |
2270 | /* It is believed that rtx's at this level will never |
2271 | contain anything but integers and other rtx's, | |
2272 | except for within LABEL_REFs and SYMBOL_REFs. */ | |
2273 | default: | |
41374e13 | 2274 | gcc_unreachable (); |
eab89b90 RK |
2275 | } |
2276 | } | |
2277 | return 1 + success_2; | |
2278 | } | |
2279 | \f | |
eab89b90 | 2280 | /* Describe the range of registers or memory referenced by X. |
05d10675 | 2281 | If X is a register, set REG_FLAG and put the first register |
eab89b90 | 2282 | number into START and the last plus one into END. |
05d10675 | 2283 | If X is a memory reference, put a base address into BASE |
eab89b90 | 2284 | and a range of integer offsets into START and END. |
05d10675 | 2285 | If X is pushing on the stack, we can assume it causes no trouble, |
eab89b90 RK |
2286 | so we set the SAFE field. */ |
2287 | ||
2288 | static struct decomposition | |
0c20a65f | 2289 | decompose (rtx x) |
eab89b90 RK |
2290 | { |
2291 | struct decomposition val; | |
2292 | int all_const = 0; | |
2293 | ||
6de9cd9a DN |
2294 | memset (&val, 0, sizeof (val)); |
2295 | ||
41374e13 | 2296 | switch (GET_CODE (x)) |
eab89b90 | 2297 | { |
41374e13 NS |
2298 | case MEM: |
2299 | { | |
2300 | rtx base = NULL_RTX, offset = 0; | |
2301 | rtx addr = XEXP (x, 0); | |
2302 | ||
2303 | if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC | |
2304 | || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC) | |
2305 | { | |
2306 | val.base = XEXP (addr, 0); | |
2307 | val.start = -GET_MODE_SIZE (GET_MODE (x)); | |
2308 | val.end = GET_MODE_SIZE (GET_MODE (x)); | |
2309 | val.safe = REGNO (val.base) == STACK_POINTER_REGNUM; | |
2310 | return val; | |
2311 | } | |
2312 | ||
2313 | if (GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY) | |
2314 | { | |
2315 | if (GET_CODE (XEXP (addr, 1)) == PLUS | |
2316 | && XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0) | |
2317 | && CONSTANT_P (XEXP (XEXP (addr, 1), 1))) | |
2318 | { | |
2319 | val.base = XEXP (addr, 0); | |
2320 | val.start = -INTVAL (XEXP (XEXP (addr, 1), 1)); | |
2321 | val.end = INTVAL (XEXP (XEXP (addr, 1), 1)); | |
2322 | val.safe = REGNO (val.base) == STACK_POINTER_REGNUM; | |
2323 | return val; | |
2324 | } | |
2325 | } | |
2326 | ||
2327 | if (GET_CODE (addr) == CONST) | |
2328 | { | |
2329 | addr = XEXP (addr, 0); | |
2330 | all_const = 1; | |
2331 | } | |
2332 | if (GET_CODE (addr) == PLUS) | |
2333 | { | |
2334 | if (CONSTANT_P (XEXP (addr, 0))) | |
2335 | { | |
2336 | base = XEXP (addr, 1); | |
2337 | offset = XEXP (addr, 0); | |
2338 | } | |
2339 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2340 | { | |
2341 | base = XEXP (addr, 0); | |
2342 | offset = XEXP (addr, 1); | |
2343 | } | |
2344 | } | |
2345 | ||
2346 | if (offset == 0) | |
2347 | { | |
2348 | base = addr; | |
2349 | offset = const0_rtx; | |
2350 | } | |
2351 | if (GET_CODE (offset) == CONST) | |
2352 | offset = XEXP (offset, 0); | |
2353 | if (GET_CODE (offset) == PLUS) | |
2354 | { | |
2355 | if (GET_CODE (XEXP (offset, 0)) == CONST_INT) | |
2356 | { | |
2357 | base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 1)); | |
2358 | offset = XEXP (offset, 0); | |
2359 | } | |
2360 | else if (GET_CODE (XEXP (offset, 1)) == CONST_INT) | |
2361 | { | |
2362 | base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 0)); | |
2363 | offset = XEXP (offset, 1); | |
2364 | } | |
2365 | else | |
2366 | { | |
2367 | base = gen_rtx_PLUS (GET_MODE (base), base, offset); | |
2368 | offset = const0_rtx; | |
2369 | } | |
2370 | } | |
2371 | else if (GET_CODE (offset) != CONST_INT) | |
2372 | { | |
2373 | base = gen_rtx_PLUS (GET_MODE (base), base, offset); | |
2374 | offset = const0_rtx; | |
2375 | } | |
2376 | ||
2377 | if (all_const && GET_CODE (base) == PLUS) | |
2378 | base = gen_rtx_CONST (GET_MODE (base), base); | |
2379 | ||
2380 | gcc_assert (GET_CODE (offset) == CONST_INT); | |
2381 | ||
2382 | val.start = INTVAL (offset); | |
2383 | val.end = val.start + GET_MODE_SIZE (GET_MODE (x)); | |
2384 | val.base = base; | |
2385 | } | |
2386 | break; | |
2387 | ||
2388 | case REG: | |
eab89b90 | 2389 | val.reg_flag = 1; |
05d10675 | 2390 | val.start = true_regnum (x); |
67468e8e | 2391 | if (val.start < 0 || val.start >= FIRST_PSEUDO_REGISTER) |
eab89b90 RK |
2392 | { |
2393 | /* A pseudo with no hard reg. */ | |
2394 | val.start = REGNO (x); | |
2395 | val.end = val.start + 1; | |
2396 | } | |
2397 | else | |
2398 | /* A hard reg. */ | |
09e18274 | 2399 | val.end = end_hard_regno (GET_MODE (x), val.start); |
41374e13 NS |
2400 | break; |
2401 | ||
2402 | case SUBREG: | |
f8cfc6aa | 2403 | if (!REG_P (SUBREG_REG (x))) |
eab89b90 RK |
2404 | /* This could be more precise, but it's good enough. */ |
2405 | return decompose (SUBREG_REG (x)); | |
2406 | val.reg_flag = 1; | |
05d10675 | 2407 | val.start = true_regnum (x); |
67468e8e | 2408 | if (val.start < 0 || val.start >= FIRST_PSEUDO_REGISTER) |
eab89b90 RK |
2409 | return decompose (SUBREG_REG (x)); |
2410 | else | |
2411 | /* A hard reg. */ | |
f1f4e530 | 2412 | val.end = val.start + subreg_nregs (x); |
41374e13 NS |
2413 | break; |
2414 | ||
2415 | case SCRATCH: | |
2416 | /* This hasn't been assigned yet, so it can't conflict yet. */ | |
2417 | val.safe = 1; | |
2418 | break; | |
2419 | ||
2420 | default: | |
2421 | gcc_assert (CONSTANT_P (x)); | |
2422 | val.safe = 1; | |
2423 | break; | |
eab89b90 | 2424 | } |
eab89b90 RK |
2425 | return val; |
2426 | } | |
2427 | ||
2428 | /* Return 1 if altering Y will not modify the value of X. | |
2429 | Y is also described by YDATA, which should be decompose (Y). */ | |
2430 | ||
2431 | static int | |
0c20a65f | 2432 | immune_p (rtx x, rtx y, struct decomposition ydata) |
eab89b90 RK |
2433 | { |
2434 | struct decomposition xdata; | |
2435 | ||
2436 | if (ydata.reg_flag) | |
f4f4d0f8 | 2437 | return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, (rtx*) 0); |
eab89b90 RK |
2438 | if (ydata.safe) |
2439 | return 1; | |
2440 | ||
41374e13 | 2441 | gcc_assert (MEM_P (y)); |
eab89b90 | 2442 | /* If Y is memory and X is not, Y can't affect X. */ |
3c0cb5de | 2443 | if (!MEM_P (x)) |
eab89b90 RK |
2444 | return 1; |
2445 | ||
4381f7c2 | 2446 | xdata = decompose (x); |
eab89b90 RK |
2447 | |
2448 | if (! rtx_equal_p (xdata.base, ydata.base)) | |
2449 | { | |
2450 | /* If bases are distinct symbolic constants, there is no overlap. */ | |
2451 | if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base)) | |
2452 | return 1; | |
2453 | /* Constants and stack slots never overlap. */ | |
2454 | if (CONSTANT_P (xdata.base) | |
2455 | && (ydata.base == frame_pointer_rtx | |
a36d4c62 | 2456 | || ydata.base == hard_frame_pointer_rtx |
eab89b90 RK |
2457 | || ydata.base == stack_pointer_rtx)) |
2458 | return 1; | |
2459 | if (CONSTANT_P (ydata.base) | |
2460 | && (xdata.base == frame_pointer_rtx | |
a36d4c62 | 2461 | || xdata.base == hard_frame_pointer_rtx |
eab89b90 RK |
2462 | || xdata.base == stack_pointer_rtx)) |
2463 | return 1; | |
2464 | /* If either base is variable, we don't know anything. */ | |
2465 | return 0; | |
2466 | } | |
2467 | ||
eab89b90 RK |
2468 | return (xdata.start >= ydata.end || ydata.start >= xdata.end); |
2469 | } | |
44ace968 | 2470 | |
f72aed24 | 2471 | /* Similar, but calls decompose. */ |
44ace968 JW |
2472 | |
2473 | int | |
0c20a65f | 2474 | safe_from_earlyclobber (rtx op, rtx clobber) |
44ace968 JW |
2475 | { |
2476 | struct decomposition early_data; | |
2477 | ||
2478 | early_data = decompose (clobber); | |
2479 | return immune_p (op, clobber, early_data); | |
2480 | } | |
eab89b90 RK |
2481 | \f |
2482 | /* Main entry point of this file: search the body of INSN | |
2483 | for values that need reloading and record them with push_reload. | |
2484 | REPLACE nonzero means record also where the values occur | |
2485 | so that subst_reloads can be used. | |
2486 | ||
2487 | IND_LEVELS says how many levels of indirection are supported by this | |
2488 | machine; a value of zero means that a memory reference is not a valid | |
2489 | memory address. | |
2490 | ||
2491 | LIVE_KNOWN says we have valid information about which hard | |
2492 | regs are live at each point in the program; this is true when | |
2493 | we are called from global_alloc but false when stupid register | |
2494 | allocation has been done. | |
2495 | ||
2496 | RELOAD_REG_P if nonzero is a vector indexed by hard reg number | |
2497 | which is nonnegative if the reg has been commandeered for reloading into. | |
2498 | It is copied into STATIC_RELOAD_REG_P and referenced from there | |
cb2afeb3 | 2499 | by various subroutines. |
eab89b90 | 2500 | |
cb2afeb3 R |
2501 | Return TRUE if some operands need to be changed, because of swapping |
2502 | commutative operands, reg_equiv_address substitution, or whatever. */ | |
2503 | ||
2504 | int | |
0c20a65f AJ |
2505 | find_reloads (rtx insn, int replace, int ind_levels, int live_known, |
2506 | short *reload_reg_p) | |
eab89b90 | 2507 | { |
b3694847 SS |
2508 | int insn_code_number; |
2509 | int i, j; | |
eab89b90 | 2510 | int noperands; |
eab89b90 RK |
2511 | /* These start out as the constraints for the insn |
2512 | and they are chewed up as we consider alternatives. */ | |
2513 | char *constraints[MAX_RECOG_OPERANDS]; | |
2514 | /* These are the preferred classes for an operand, or NO_REGS if it isn't | |
2515 | a register. */ | |
2516 | enum reg_class preferred_class[MAX_RECOG_OPERANDS]; | |
2517 | char pref_or_nothing[MAX_RECOG_OPERANDS]; | |
0b540f12 UW |
2518 | /* Nonzero for a MEM operand whose entire address needs a reload. |
2519 | May be -1 to indicate the entire address may or may not need a reload. */ | |
eab89b90 | 2520 | int address_reloaded[MAX_RECOG_OPERANDS]; |
0b540f12 UW |
2521 | /* Nonzero for an address operand that needs to be completely reloaded. |
2522 | May be -1 to indicate the entire operand may or may not need a reload. */ | |
9537511b | 2523 | int address_operand_reloaded[MAX_RECOG_OPERANDS]; |
a8c9daeb RK |
2524 | /* Value of enum reload_type to use for operand. */ |
2525 | enum reload_type operand_type[MAX_RECOG_OPERANDS]; | |
2526 | /* Value of enum reload_type to use within address of operand. */ | |
2527 | enum reload_type address_type[MAX_RECOG_OPERANDS]; | |
2528 | /* Save the usage of each operand. */ | |
2529 | enum reload_usage { RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE } modified[MAX_RECOG_OPERANDS]; | |
eab89b90 RK |
2530 | int no_input_reloads = 0, no_output_reloads = 0; |
2531 | int n_alternatives; | |
2532 | int this_alternative[MAX_RECOG_OPERANDS]; | |
69add2a8 | 2533 | char this_alternative_match_win[MAX_RECOG_OPERANDS]; |
eab89b90 RK |
2534 | char this_alternative_win[MAX_RECOG_OPERANDS]; |
2535 | char this_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2536 | char this_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2537 | int this_alternative_matches[MAX_RECOG_OPERANDS]; | |
2538 | int swapped; | |
2539 | int goal_alternative[MAX_RECOG_OPERANDS]; | |
2540 | int this_alternative_number; | |
a544cfd2 | 2541 | int goal_alternative_number = 0; |
eab89b90 RK |
2542 | int operand_reloadnum[MAX_RECOG_OPERANDS]; |
2543 | int goal_alternative_matches[MAX_RECOG_OPERANDS]; | |
2544 | int goal_alternative_matched[MAX_RECOG_OPERANDS]; | |
69add2a8 | 2545 | char goal_alternative_match_win[MAX_RECOG_OPERANDS]; |
eab89b90 RK |
2546 | char goal_alternative_win[MAX_RECOG_OPERANDS]; |
2547 | char goal_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2548 | char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2549 | int goal_alternative_swapped; | |
eab89b90 RK |
2550 | int best; |
2551 | int commutative; | |
2552 | char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
2553 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
2554 | rtx body = PATTERN (insn); | |
2555 | rtx set = single_set (insn); | |
a544cfd2 | 2556 | int goal_earlyclobber = 0, this_earlyclobber; |
eab89b90 | 2557 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
cb2afeb3 | 2558 | int retval = 0; |
eab89b90 RK |
2559 | |
2560 | this_insn = insn; | |
eab89b90 RK |
2561 | n_reloads = 0; |
2562 | n_replacements = 0; | |
eab89b90 RK |
2563 | n_earlyclobbers = 0; |
2564 | replace_reloads = replace; | |
2565 | hard_regs_live_known = live_known; | |
2566 | static_reload_reg_p = reload_reg_p; | |
2567 | ||
2568 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads; | |
2569 | neither are insns that SET cc0. Insns that use CC0 are not allowed | |
2570 | to have any input reloads. */ | |
4b4bf941 | 2571 | if (JUMP_P (insn) || CALL_P (insn)) |
eab89b90 RK |
2572 | no_output_reloads = 1; |
2573 | ||
2574 | #ifdef HAVE_cc0 | |
2575 | if (reg_referenced_p (cc0_rtx, PATTERN (insn))) | |
2576 | no_input_reloads = 1; | |
2577 | if (reg_set_p (cc0_rtx, PATTERN (insn))) | |
2578 | no_output_reloads = 1; | |
2579 | #endif | |
05d10675 | 2580 | |
0dadecf6 RK |
2581 | #ifdef SECONDARY_MEMORY_NEEDED |
2582 | /* The eliminated forms of any secondary memory locations are per-insn, so | |
2583 | clear them out here. */ | |
2584 | ||
048b0d2e JH |
2585 | if (secondary_memlocs_elim_used) |
2586 | { | |
2587 | memset (secondary_memlocs_elim, 0, | |
2588 | sizeof (secondary_memlocs_elim[0]) * secondary_memlocs_elim_used); | |
2589 | secondary_memlocs_elim_used = 0; | |
2590 | } | |
0dadecf6 RK |
2591 | #endif |
2592 | ||
0a578fee BS |
2593 | /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it |
2594 | is cheap to move between them. If it is not, there may not be an insn | |
2595 | to do the copy, so we may need a reload. */ | |
2596 | if (GET_CODE (body) == SET | |
f8cfc6aa | 2597 | && REG_P (SET_DEST (body)) |
0a578fee | 2598 | && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER |
f8cfc6aa | 2599 | && REG_P (SET_SRC (body)) |
0a578fee | 2600 | && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER |
e56b4594 AO |
2601 | && REGISTER_MOVE_COST (GET_MODE (SET_SRC (body)), |
2602 | REGNO_REG_CLASS (REGNO (SET_SRC (body))), | |
0a578fee BS |
2603 | REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2) |
2604 | return 0; | |
eab89b90 | 2605 | |
0a578fee | 2606 | extract_insn (insn); |
eab89b90 | 2607 | |
1ccbefce RH |
2608 | noperands = reload_n_operands = recog_data.n_operands; |
2609 | n_alternatives = recog_data.n_alternatives; | |
eab89b90 | 2610 | |
0a578fee BS |
2611 | /* Just return "no reloads" if insn has no operands with constraints. */ |
2612 | if (noperands == 0 || n_alternatives == 0) | |
2613 | return 0; | |
eab89b90 | 2614 | |
0a578fee BS |
2615 | insn_code_number = INSN_CODE (insn); |
2616 | this_insn_is_asm = insn_code_number < 0; | |
eab89b90 | 2617 | |
f428f252 KG |
2618 | memcpy (operand_mode, recog_data.operand_mode, |
2619 | noperands * sizeof (enum machine_mode)); | |
2620 | memcpy (constraints, recog_data.constraints, noperands * sizeof (char *)); | |
eab89b90 RK |
2621 | |
2622 | commutative = -1; | |
2623 | ||
2624 | /* If we will need to know, later, whether some pair of operands | |
2625 | are the same, we must compare them now and save the result. | |
2626 | Reloading the base and index registers will clobber them | |
2627 | and afterward they will fail to match. */ | |
2628 | ||
2629 | for (i = 0; i < noperands; i++) | |
2630 | { | |
b3694847 SS |
2631 | char *p; |
2632 | int c; | |
eab89b90 | 2633 | |
1ccbefce | 2634 | substed_operand[i] = recog_data.operand[i]; |
eab89b90 RK |
2635 | p = constraints[i]; |
2636 | ||
a8c9daeb RK |
2637 | modified[i] = RELOAD_READ; |
2638 | ||
05d10675 | 2639 | /* Scan this operand's constraint to see if it is an output operand, |
a8c9daeb | 2640 | an in-out operand, is commutative, or should match another. */ |
eab89b90 | 2641 | |
97488870 | 2642 | while ((c = *p)) |
a8c9daeb | 2643 | { |
97488870 | 2644 | p += CONSTRAINT_LEN (c, p); |
f345f21a | 2645 | switch (c) |
a8c9daeb | 2646 | { |
f345f21a JH |
2647 | case '=': |
2648 | modified[i] = RELOAD_WRITE; | |
2649 | break; | |
2650 | case '+': | |
2651 | modified[i] = RELOAD_READ_WRITE; | |
2652 | break; | |
2653 | case '%': | |
2654 | { | |
2655 | /* The last operand should not be marked commutative. */ | |
41374e13 | 2656 | gcc_assert (i != noperands - 1); |
f345f21a JH |
2657 | |
2658 | /* We currently only support one commutative pair of | |
2659 | operands. Some existing asm code currently uses more | |
2660 | than one pair. Previously, that would usually work, | |
2661 | but sometimes it would crash the compiler. We | |
2662 | continue supporting that case as well as we can by | |
2663 | silently ignoring all but the first pair. In the | |
2664 | future we may handle it correctly. */ | |
2665 | if (commutative < 0) | |
2666 | commutative = i; | |
41374e13 NS |
2667 | else |
2668 | gcc_assert (this_insn_is_asm); | |
f345f21a JH |
2669 | } |
2670 | break; | |
2671 | /* Use of ISDIGIT is tempting here, but it may get expensive because | |
2672 | of locale support we don't want. */ | |
2673 | case '0': case '1': case '2': case '3': case '4': | |
2674 | case '5': case '6': case '7': case '8': case '9': | |
2675 | { | |
2676 | c = strtoul (p - 1, &p, 10); | |
2677 | ||
2678 | operands_match[c][i] | |
2679 | = operands_match_p (recog_data.operand[c], | |
2680 | recog_data.operand[i]); | |
2681 | ||
2682 | /* An operand may not match itself. */ | |
41374e13 | 2683 | gcc_assert (c != i); |
f345f21a JH |
2684 | |
2685 | /* If C can be commuted with C+1, and C might need to match I, | |
2686 | then C+1 might also need to match I. */ | |
2687 | if (commutative >= 0) | |
2688 | { | |
2689 | if (c == commutative || c == commutative + 1) | |
2690 | { | |
2691 | int other = c + (c == commutative ? 1 : -1); | |
2692 | operands_match[other][i] | |
2693 | = operands_match_p (recog_data.operand[other], | |
2694 | recog_data.operand[i]); | |
2695 | } | |
2696 | if (i == commutative || i == commutative + 1) | |
2697 | { | |
2698 | int other = i + (i == commutative ? 1 : -1); | |
2699 | operands_match[c][other] | |
2700 | = operands_match_p (recog_data.operand[c], | |
2701 | recog_data.operand[other]); | |
2702 | } | |
2703 | /* Note that C is supposed to be less than I. | |
2704 | No need to consider altering both C and I because in | |
2705 | that case we would alter one into the other. */ | |
2706 | } | |
2707 | } | |
a8c9daeb RK |
2708 | } |
2709 | } | |
eab89b90 RK |
2710 | } |
2711 | ||
2712 | /* Examine each operand that is a memory reference or memory address | |
2713 | and reload parts of the addresses into index registers. | |
eab89b90 RK |
2714 | Also here any references to pseudo regs that didn't get hard regs |
2715 | but are equivalent to constants get replaced in the insn itself | |
05d10675 | 2716 | with those constants. Nobody will ever see them again. |
eab89b90 RK |
2717 | |
2718 | Finally, set up the preferred classes of each operand. */ | |
2719 | ||
2720 | for (i = 0; i < noperands; i++) | |
2721 | { | |
b3694847 | 2722 | RTX_CODE code = GET_CODE (recog_data.operand[i]); |
a8c9daeb | 2723 | |
eab89b90 | 2724 | address_reloaded[i] = 0; |
9537511b | 2725 | address_operand_reloaded[i] = 0; |
a8c9daeb RK |
2726 | operand_type[i] = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT |
2727 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT | |
2728 | : RELOAD_OTHER); | |
2729 | address_type[i] | |
2730 | = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT_ADDRESS | |
2731 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT_ADDRESS | |
2732 | : RELOAD_OTHER); | |
eab89b90 | 2733 | |
0d38001f RS |
2734 | if (*constraints[i] == 0) |
2735 | /* Ignore things like match_operator operands. */ | |
2736 | ; | |
ccfc6cc8 | 2737 | else if (constraints[i][0] == 'p' |
97488870 | 2738 | || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i])) |
eab89b90 | 2739 | { |
9537511b UW |
2740 | address_operand_reloaded[i] |
2741 | = find_reloads_address (recog_data.operand_mode[i], (rtx*) 0, | |
2742 | recog_data.operand[i], | |
2743 | recog_data.operand_loc[i], | |
2744 | i, operand_type[i], ind_levels, insn); | |
b685dbae | 2745 | |
05d10675 | 2746 | /* If we now have a simple operand where we used to have a |
b685dbae | 2747 | PLUS or MULT, re-recognize and try again. */ |
ec8e098d | 2748 | if ((OBJECT_P (*recog_data.operand_loc[i]) |
1ccbefce RH |
2749 | || GET_CODE (*recog_data.operand_loc[i]) == SUBREG) |
2750 | && (GET_CODE (recog_data.operand[i]) == MULT | |
2751 | || GET_CODE (recog_data.operand[i]) == PLUS)) | |
b685dbae RK |
2752 | { |
2753 | INSN_CODE (insn) = -1; | |
cb2afeb3 R |
2754 | retval = find_reloads (insn, replace, ind_levels, live_known, |
2755 | reload_reg_p); | |
2756 | return retval; | |
b685dbae RK |
2757 | } |
2758 | ||
1ccbefce RH |
2759 | recog_data.operand[i] = *recog_data.operand_loc[i]; |
2760 | substed_operand[i] = recog_data.operand[i]; | |
9537511b UW |
2761 | |
2762 | /* Address operands are reloaded in their existing mode, | |
2763 | no matter what is specified in the machine description. */ | |
2764 | operand_mode[i] = GET_MODE (recog_data.operand[i]); | |
eab89b90 RK |
2765 | } |
2766 | else if (code == MEM) | |
2767 | { | |
ab87f8c8 | 2768 | address_reloaded[i] |
1ccbefce RH |
2769 | = find_reloads_address (GET_MODE (recog_data.operand[i]), |
2770 | recog_data.operand_loc[i], | |
2771 | XEXP (recog_data.operand[i], 0), | |
2772 | &XEXP (recog_data.operand[i], 0), | |
ab87f8c8 | 2773 | i, address_type[i], ind_levels, insn); |
1ccbefce RH |
2774 | recog_data.operand[i] = *recog_data.operand_loc[i]; |
2775 | substed_operand[i] = recog_data.operand[i]; | |
eab89b90 RK |
2776 | } |
2777 | else if (code == SUBREG) | |
b60a8416 | 2778 | { |
1ccbefce | 2779 | rtx reg = SUBREG_REG (recog_data.operand[i]); |
b60a8416 | 2780 | rtx op |
1ccbefce | 2781 | = find_reloads_toplev (recog_data.operand[i], i, address_type[i], |
b60a8416 R |
2782 | ind_levels, |
2783 | set != 0 | |
1ccbefce | 2784 | && &SET_DEST (set) == recog_data.operand_loc[i], |
9246aadb AH |
2785 | insn, |
2786 | &address_reloaded[i]); | |
b60a8416 R |
2787 | |
2788 | /* If we made a MEM to load (a part of) the stackslot of a pseudo | |
2789 | that didn't get a hard register, emit a USE with a REG_EQUAL | |
2790 | note in front so that we might inherit a previous, possibly | |
2791 | wider reload. */ | |
05d10675 | 2792 | |
cb2afeb3 | 2793 | if (replace |
3c0cb5de | 2794 | && MEM_P (op) |
f8cfc6aa | 2795 | && REG_P (reg) |
b60a8416 R |
2796 | && (GET_MODE_SIZE (GET_MODE (reg)) |
2797 | >= GET_MODE_SIZE (GET_MODE (op)))) | |
3d238248 JJ |
2798 | set_unique_reg_note (emit_insn_before (gen_rtx_USE (VOIDmode, reg), |
2799 | insn), | |
2800 | REG_EQUAL, reg_equiv_memory_loc[REGNO (reg)]); | |
b60a8416 | 2801 | |
1ccbefce | 2802 | substed_operand[i] = recog_data.operand[i] = op; |
b60a8416 | 2803 | } |
ec8e098d | 2804 | else if (code == PLUS || GET_RTX_CLASS (code) == RTX_UNARY) |
ff428c90 ILT |
2805 | /* We can get a PLUS as an "operand" as a result of register |
2806 | elimination. See eliminate_regs and gen_reload. We handle | |
2807 | a unary operator by reloading the operand. */ | |
1ccbefce RH |
2808 | substed_operand[i] = recog_data.operand[i] |
2809 | = find_reloads_toplev (recog_data.operand[i], i, address_type[i], | |
9246aadb AH |
2810 | ind_levels, 0, insn, |
2811 | &address_reloaded[i]); | |
eab89b90 RK |
2812 | else if (code == REG) |
2813 | { | |
2814 | /* This is equivalent to calling find_reloads_toplev. | |
2815 | The code is duplicated for speed. | |
2816 | When we find a pseudo always equivalent to a constant, | |
2817 | we replace it by the constant. We must be sure, however, | |
2818 | that we don't try to replace it in the insn in which it | |
6d2f8887 | 2819 | is being set. */ |
b3694847 | 2820 | int regno = REGNO (recog_data.operand[i]); |
eab89b90 | 2821 | if (reg_equiv_constant[regno] != 0 |
1ccbefce | 2822 | && (set == 0 || &SET_DEST (set) != recog_data.operand_loc[i])) |
726e2d54 JW |
2823 | { |
2824 | /* Record the existing mode so that the check if constants are | |
eceef4c9 | 2825 | allowed will work when operand_mode isn't specified. */ |
726e2d54 JW |
2826 | |
2827 | if (operand_mode[i] == VOIDmode) | |
1ccbefce | 2828 | operand_mode[i] = GET_MODE (recog_data.operand[i]); |
726e2d54 | 2829 | |
1ccbefce | 2830 | substed_operand[i] = recog_data.operand[i] |
05d10675 | 2831 | = reg_equiv_constant[regno]; |
726e2d54 | 2832 | } |
cb2afeb3 R |
2833 | if (reg_equiv_memory_loc[regno] != 0 |
2834 | && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)) | |
2835 | /* We need not give a valid is_set_dest argument since the case | |
2836 | of a constant equivalence was checked above. */ | |
1ccbefce RH |
2837 | substed_operand[i] = recog_data.operand[i] |
2838 | = find_reloads_toplev (recog_data.operand[i], i, address_type[i], | |
9246aadb AH |
2839 | ind_levels, 0, insn, |
2840 | &address_reloaded[i]); | |
eab89b90 | 2841 | } |
aaf9712e RS |
2842 | /* If the operand is still a register (we didn't replace it with an |
2843 | equivalent), get the preferred class to reload it into. */ | |
1ccbefce | 2844 | code = GET_CODE (recog_data.operand[i]); |
aaf9712e | 2845 | preferred_class[i] |
1ccbefce RH |
2846 | = ((code == REG && REGNO (recog_data.operand[i]) |
2847 | >= FIRST_PSEUDO_REGISTER) | |
2848 | ? reg_preferred_class (REGNO (recog_data.operand[i])) | |
2849 | : NO_REGS); | |
aaf9712e | 2850 | pref_or_nothing[i] |
1ccbefce RH |
2851 | = (code == REG |
2852 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER | |
2853 | && reg_alternate_class (REGNO (recog_data.operand[i])) == NO_REGS); | |
eab89b90 RK |
2854 | } |
2855 | ||
2856 | /* If this is simply a copy from operand 1 to operand 0, merge the | |
2857 | preferred classes for the operands. */ | |
1ccbefce RH |
2858 | if (set != 0 && noperands >= 2 && recog_data.operand[0] == SET_DEST (set) |
2859 | && recog_data.operand[1] == SET_SRC (set)) | |
eab89b90 RK |
2860 | { |
2861 | preferred_class[0] = preferred_class[1] | |
2862 | = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]]; | |
2863 | pref_or_nothing[0] |= pref_or_nothing[1]; | |
2864 | pref_or_nothing[1] |= pref_or_nothing[0]; | |
2865 | } | |
2866 | ||
2867 | /* Now see what we need for pseudo-regs that didn't get hard regs | |
2868 | or got the wrong kind of hard reg. For this, we must consider | |
2869 | all the operands together against the register constraints. */ | |
2870 | ||
812f2051 | 2871 | best = MAX_RECOG_OPERANDS * 2 + 600; |
eab89b90 RK |
2872 | |
2873 | swapped = 0; | |
2874 | goal_alternative_swapped = 0; | |
2875 | try_swapped: | |
2876 | ||
2877 | /* The constraints are made of several alternatives. | |
2878 | Each operand's constraint looks like foo,bar,... with commas | |
2879 | separating the alternatives. The first alternatives for all | |
2880 | operands go together, the second alternatives go together, etc. | |
2881 | ||
2882 | First loop over alternatives. */ | |
2883 | ||
2884 | for (this_alternative_number = 0; | |
2885 | this_alternative_number < n_alternatives; | |
2886 | this_alternative_number++) | |
2887 | { | |
2888 | /* Loop over operands for one constraint alternative. */ | |
2889 | /* LOSERS counts those that don't fit this alternative | |
2890 | and would require loading. */ | |
2891 | int losers = 0; | |
2892 | /* BAD is set to 1 if it some operand can't fit this alternative | |
2893 | even after reloading. */ | |
2894 | int bad = 0; | |
2895 | /* REJECT is a count of how undesirable this alternative says it is | |
2896 | if any reloading is required. If the alternative matches exactly | |
2897 | then REJECT is ignored, but otherwise it gets this much | |
05d10675 | 2898 | counted against it in addition to the reloading needed. Each |
eab89b90 RK |
2899 | ? counts three times here since we want the disparaging caused by |
2900 | a bad register class to only count 1/3 as much. */ | |
2901 | int reject = 0; | |
2902 | ||
2903 | this_earlyclobber = 0; | |
2904 | ||
2905 | for (i = 0; i < noperands; i++) | |
2906 | { | |
b3694847 | 2907 | char *p = constraints[i]; |
97488870 R |
2908 | char *end; |
2909 | int len; | |
b3694847 | 2910 | int win = 0; |
69add2a8 | 2911 | int did_match = 0; |
82efa2e5 | 2912 | /* 0 => this operand can be reloaded somehow for this alternative. */ |
eab89b90 RK |
2913 | int badop = 1; |
2914 | /* 0 => this operand can be reloaded if the alternative allows regs. */ | |
2915 | int winreg = 0; | |
2916 | int c; | |
97488870 | 2917 | int m; |
b3694847 | 2918 | rtx operand = recog_data.operand[i]; |
eab89b90 RK |
2919 | int offset = 0; |
2920 | /* Nonzero means this is a MEM that must be reloaded into a reg | |
2921 | regardless of what the constraint says. */ | |
2922 | int force_reload = 0; | |
2923 | int offmemok = 0; | |
9d926da5 RK |
2924 | /* Nonzero if a constant forced into memory would be OK for this |
2925 | operand. */ | |
2926 | int constmemok = 0; | |
eab89b90 RK |
2927 | int earlyclobber = 0; |
2928 | ||
ff428c90 | 2929 | /* If the predicate accepts a unary operator, it means that |
05d10675 | 2930 | we need to reload the operand, but do not do this for |
ad729076 | 2931 | match_operator and friends. */ |
ec8e098d | 2932 | if (UNARY_P (operand) && *p != 0) |
ff428c90 ILT |
2933 | operand = XEXP (operand, 0); |
2934 | ||
eab89b90 RK |
2935 | /* If the operand is a SUBREG, extract |
2936 | the REG or MEM (or maybe even a constant) within. | |
2937 | (Constants can occur as a result of reg_equiv_constant.) */ | |
2938 | ||
2939 | while (GET_CODE (operand) == SUBREG) | |
2940 | { | |
ddef6bc7 JJ |
2941 | /* Offset only matters when operand is a REG and |
2942 | it is a hard reg. This is because it is passed | |
2943 | to reg_fits_class_p if it is a REG and all pseudos | |
2944 | return 0 from that function. */ | |
f8cfc6aa | 2945 | if (REG_P (SUBREG_REG (operand)) |
ddef6bc7 JJ |
2946 | && REGNO (SUBREG_REG (operand)) < FIRST_PSEUDO_REGISTER) |
2947 | { | |
04c5580f JH |
2948 | if (!subreg_offset_representable_p |
2949 | (REGNO (SUBREG_REG (operand)), | |
2950 | GET_MODE (SUBREG_REG (operand)), | |
2951 | SUBREG_BYTE (operand), | |
2952 | GET_MODE (operand))) | |
2953 | force_reload = 1; | |
ddef6bc7 JJ |
2954 | offset += subreg_regno_offset (REGNO (SUBREG_REG (operand)), |
2955 | GET_MODE (SUBREG_REG (operand)), | |
2956 | SUBREG_BYTE (operand), | |
2957 | GET_MODE (operand)); | |
2958 | } | |
eab89b90 | 2959 | operand = SUBREG_REG (operand); |
38e01259 | 2960 | /* Force reload if this is a constant or PLUS or if there may |
a61c98cf RK |
2961 | be a problem accessing OPERAND in the outer mode. */ |
2962 | if (CONSTANT_P (operand) | |
ca769828 | 2963 | || GET_CODE (operand) == PLUS |
03b72c86 RK |
2964 | /* We must force a reload of paradoxical SUBREGs |
2965 | of a MEM because the alignment of the inner value | |
beb5a9b8 RK |
2966 | may not be enough to do the outer reference. On |
2967 | big-endian machines, it may also reference outside | |
2968 | the object. | |
03b72c86 RK |
2969 | |
2970 | On machines that extend byte operations and we have a | |
486d8509 RK |
2971 | SUBREG where both the inner and outer modes are no wider |
2972 | than a word and the inner mode is narrower, is integral, | |
2973 | and gets extended when loaded from memory, combine.c has | |
2974 | made assumptions about the behavior of the machine in such | |
03b72c86 RK |
2975 | register access. If the data is, in fact, in memory we |
2976 | must always load using the size assumed to be in the | |
05d10675 | 2977 | register and let the insn do the different-sized |
5ec105cd RH |
2978 | accesses. |
2979 | ||
05d10675 | 2980 | This is doubly true if WORD_REGISTER_OPERATIONS. In |
5ec105cd | 2981 | this case eliminate_regs has left non-paradoxical |
bd235d86 | 2982 | subregs for push_reload to see. Make sure it does |
5ec105cd RH |
2983 | by forcing the reload. |
2984 | ||
2985 | ??? When is it right at this stage to have a subreg | |
14b493d6 | 2986 | of a mem that is _not_ to be handled specially? IMO |
5ec105cd | 2987 | those should have been reduced to just a mem. */ |
3c0cb5de | 2988 | || ((MEM_P (operand) |
f8cfc6aa | 2989 | || (REG_P (operand) |
a61c98cf | 2990 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) |
5ec105cd | 2991 | #ifndef WORD_REGISTER_OPERATIONS |
03b72c86 RK |
2992 | && (((GET_MODE_BITSIZE (GET_MODE (operand)) |
2993 | < BIGGEST_ALIGNMENT) | |
2994 | && (GET_MODE_SIZE (operand_mode[i]) | |
2995 | > GET_MODE_SIZE (GET_MODE (operand)))) | |
b605eb59 | 2996 | || BYTES_BIG_ENDIAN |
03b72c86 RK |
2997 | #ifdef LOAD_EXTEND_OP |
2998 | || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD | |
2999 | && (GET_MODE_SIZE (GET_MODE (operand)) | |
3000 | <= UNITS_PER_WORD) | |
3001 | && (GET_MODE_SIZE (operand_mode[i]) | |
486d8509 RK |
3002 | > GET_MODE_SIZE (GET_MODE (operand))) |
3003 | && INTEGRAL_MODE_P (GET_MODE (operand)) | |
f822d252 | 3004 | && LOAD_EXTEND_OP (GET_MODE (operand)) != UNKNOWN) |
46da6b3a | 3005 | #endif |
5ec105cd RH |
3006 | ) |
3007 | #endif | |
3008 | ) | |
ddef6bc7 | 3009 | ) |
eab89b90 RK |
3010 | force_reload = 1; |
3011 | } | |
3012 | ||
3013 | this_alternative[i] = (int) NO_REGS; | |
3014 | this_alternative_win[i] = 0; | |
69add2a8 | 3015 | this_alternative_match_win[i] = 0; |
eab89b90 RK |
3016 | this_alternative_offmemok[i] = 0; |
3017 | this_alternative_earlyclobber[i] = 0; | |
3018 | this_alternative_matches[i] = -1; | |
3019 | ||
3020 | /* An empty constraint or empty alternative | |
3021 | allows anything which matched the pattern. */ | |
3022 | if (*p == 0 || *p == ',') | |
3023 | win = 1, badop = 0; | |
3024 | ||
3025 | /* Scan this alternative's specs for this operand; | |
3026 | set WIN if the operand fits any letter in this alternative. | |
3027 | Otherwise, clear BADOP if this operand could | |
3028 | fit some letter after reloads, | |
3029 | or set WINREG if this operand could fit after reloads | |
3030 | provided the constraint allows some registers. */ | |
3031 | ||
97488870 R |
3032 | do |
3033 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
eab89b90 | 3034 | { |
97488870 R |
3035 | case '\0': |
3036 | len = 0; | |
3037 | break; | |
3038 | case ',': | |
3039 | c = '\0'; | |
3040 | break; | |
3041 | ||
c5c76735 | 3042 | case '=': case '+': case '*': |
eab89b90 RK |
3043 | break; |
3044 | ||
3045 | case '%': | |
7e3aa041 ILT |
3046 | /* We only support one commutative marker, the first |
3047 | one. We already set commutative above. */ | |
eab89b90 RK |
3048 | break; |
3049 | ||
3050 | case '?': | |
812f2051 | 3051 | reject += 6; |
eab89b90 RK |
3052 | break; |
3053 | ||
3054 | case '!': | |
812f2051 | 3055 | reject = 600; |
eab89b90 RK |
3056 | break; |
3057 | ||
3058 | case '#': | |
3059 | /* Ignore rest of this alternative as far as | |
3060 | reloading is concerned. */ | |
97488870 | 3061 | do |
4381f7c2 | 3062 | p++; |
97488870 R |
3063 | while (*p && *p != ','); |
3064 | len = 0; | |
eab89b90 RK |
3065 | break; |
3066 | ||
c5c76735 JL |
3067 | case '0': case '1': case '2': case '3': case '4': |
3068 | case '5': case '6': case '7': case '8': case '9': | |
97488870 R |
3069 | m = strtoul (p, &end, 10); |
3070 | p = end; | |
3071 | len = 0; | |
c5c76735 | 3072 | |
97488870 | 3073 | this_alternative_matches[i] = m; |
eab89b90 RK |
3074 | /* We are supposed to match a previous operand. |
3075 | If we do, we win if that one did. | |
3076 | If we do not, count both of the operands as losers. | |
3077 | (This is too conservative, since most of the time | |
3078 | only a single reload insn will be needed to make | |
3079 | the two operands win. As a result, this alternative | |
3080 | may be rejected when it is actually desirable.) */ | |
97488870 | 3081 | if ((swapped && (m != commutative || i != commutative + 1)) |
eab89b90 RK |
3082 | /* If we are matching as if two operands were swapped, |
3083 | also pretend that operands_match had been computed | |
3084 | with swapped. | |
3085 | But if I is the second of those and C is the first, | |
3086 | don't exchange them, because operands_match is valid | |
3087 | only on one side of its diagonal. */ | |
3088 | ? (operands_match | |
97488870 R |
3089 | [(m == commutative || m == commutative + 1) |
3090 | ? 2 * commutative + 1 - m : m] | |
05d10675 | 3091 | [(i == commutative || i == commutative + 1) |
4381f7c2 | 3092 | ? 2 * commutative + 1 - i : i]) |
97488870 | 3093 | : operands_match[m][i]) |
fc79eafe JW |
3094 | { |
3095 | /* If we are matching a non-offsettable address where an | |
3096 | offsettable address was expected, then we must reject | |
3097 | this combination, because we can't reload it. */ | |
97488870 | 3098 | if (this_alternative_offmemok[m] |
3c0cb5de | 3099 | && MEM_P (recog_data.operand[m]) |
97488870 R |
3100 | && this_alternative[m] == (int) NO_REGS |
3101 | && ! this_alternative_win[m]) | |
fc79eafe JW |
3102 | bad = 1; |
3103 | ||
97488870 | 3104 | did_match = this_alternative_win[m]; |
fc79eafe | 3105 | } |
eab89b90 RK |
3106 | else |
3107 | { | |
3108 | /* Operands don't match. */ | |
3109 | rtx value; | |
87cda9d6 | 3110 | int loc1, loc2; |
eab89b90 RK |
3111 | /* Retroactively mark the operand we had to match |
3112 | as a loser, if it wasn't already. */ | |
97488870 | 3113 | if (this_alternative_win[m]) |
eab89b90 | 3114 | losers++; |
97488870 R |
3115 | this_alternative_win[m] = 0; |
3116 | if (this_alternative[m] == (int) NO_REGS) | |
eab89b90 RK |
3117 | bad = 1; |
3118 | /* But count the pair only once in the total badness of | |
87cda9d6 DJ |
3119 | this alternative, if the pair can be a dummy reload. |
3120 | The pointers in operand_loc are not swapped; swap | |
3121 | them by hand if necessary. */ | |
3122 | if (swapped && i == commutative) | |
3123 | loc1 = commutative + 1; | |
3124 | else if (swapped && i == commutative + 1) | |
3125 | loc1 = commutative; | |
3126 | else | |
3127 | loc1 = i; | |
3128 | if (swapped && m == commutative) | |
3129 | loc2 = commutative + 1; | |
3130 | else if (swapped && m == commutative + 1) | |
3131 | loc2 = commutative; | |
3132 | else | |
3133 | loc2 = m; | |
eab89b90 | 3134 | value |
1ccbefce | 3135 | = find_dummy_reload (recog_data.operand[i], |
97488870 | 3136 | recog_data.operand[m], |
87cda9d6 DJ |
3137 | recog_data.operand_loc[loc1], |
3138 | recog_data.operand_loc[loc2], | |
97488870 R |
3139 | operand_mode[i], operand_mode[m], |
3140 | this_alternative[m], -1, | |
3141 | this_alternative_earlyclobber[m]); | |
eab89b90 RK |
3142 | |
3143 | if (value != 0) | |
3144 | losers--; | |
3145 | } | |
3146 | /* This can be fixed with reloads if the operand | |
3147 | we are supposed to match can be fixed with reloads. */ | |
3148 | badop = 0; | |
97488870 | 3149 | this_alternative[i] = this_alternative[m]; |
e64c4f9e RK |
3150 | |
3151 | /* If we have to reload this operand and some previous | |
3152 | operand also had to match the same thing as this | |
3153 | operand, we don't know how to do that. So reject this | |
3154 | alternative. */ | |
69add2a8 | 3155 | if (! did_match || force_reload) |
e64c4f9e RK |
3156 | for (j = 0; j < i; j++) |
3157 | if (this_alternative_matches[j] | |
3158 | == this_alternative_matches[i]) | |
3159 | badop = 1; | |
eab89b90 RK |
3160 | break; |
3161 | ||
3162 | case 'p': | |
3163 | /* All necessary reloads for an address_operand | |
3164 | were handled in find_reloads_address. */ | |
c4963a0a BS |
3165 | this_alternative[i] |
3166 | = (int) base_reg_class (VOIDmode, ADDRESS, SCRATCH); | |
eab89b90 | 3167 | win = 1; |
8d53318f | 3168 | badop = 0; |
eab89b90 RK |
3169 | break; |
3170 | ||
3171 | case 'm': | |
3172 | if (force_reload) | |
3173 | break; | |
3c0cb5de | 3174 | if (MEM_P (operand) |
f8cfc6aa | 3175 | || (REG_P (operand) |
eab89b90 RK |
3176 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER |
3177 | && reg_renumber[REGNO (operand)] < 0)) | |
3178 | win = 1; | |
34208acf | 3179 | if (CONST_POOL_OK_P (operand)) |
eab89b90 | 3180 | badop = 0; |
9d926da5 | 3181 | constmemok = 1; |
eab89b90 RK |
3182 | break; |
3183 | ||
3184 | case '<': | |
3c0cb5de | 3185 | if (MEM_P (operand) |
eab89b90 RK |
3186 | && ! address_reloaded[i] |
3187 | && (GET_CODE (XEXP (operand, 0)) == PRE_DEC | |
3188 | || GET_CODE (XEXP (operand, 0)) == POST_DEC)) | |
3189 | win = 1; | |
3190 | break; | |
3191 | ||
3192 | case '>': | |
3c0cb5de | 3193 | if (MEM_P (operand) |
eab89b90 RK |
3194 | && ! address_reloaded[i] |
3195 | && (GET_CODE (XEXP (operand, 0)) == PRE_INC | |
3196 | || GET_CODE (XEXP (operand, 0)) == POST_INC)) | |
3197 | win = 1; | |
3198 | break; | |
3199 | ||
3200 | /* Memory operand whose address is not offsettable. */ | |
3201 | case 'V': | |
3202 | if (force_reload) | |
3203 | break; | |
3c0cb5de | 3204 | if (MEM_P (operand) |
eab89b90 RK |
3205 | && ! (ind_levels ? offsettable_memref_p (operand) |
3206 | : offsettable_nonstrict_memref_p (operand)) | |
3207 | /* Certain mem addresses will become offsettable | |
3208 | after they themselves are reloaded. This is important; | |
3209 | we don't want our own handling of unoffsettables | |
3210 | to override the handling of reg_equiv_address. */ | |
f8cfc6aa | 3211 | && !(REG_P (XEXP (operand, 0)) |
eab89b90 RK |
3212 | && (ind_levels == 0 |
3213 | || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0))) | |
3214 | win = 1; | |
3215 | break; | |
3216 | ||
3217 | /* Memory operand whose address is offsettable. */ | |
3218 | case 'o': | |
3219 | if (force_reload) | |
3220 | break; | |
3c0cb5de | 3221 | if ((MEM_P (operand) |
eab89b90 RK |
3222 | /* If IND_LEVELS, find_reloads_address won't reload a |
3223 | pseudo that didn't get a hard reg, so we have to | |
3224 | reject that case. */ | |
ab87f8c8 JL |
3225 | && ((ind_levels ? offsettable_memref_p (operand) |
3226 | : offsettable_nonstrict_memref_p (operand)) | |
3227 | /* A reloaded address is offsettable because it is now | |
3228 | just a simple register indirect. */ | |
0b540f12 | 3229 | || address_reloaded[i] == 1)) |
f8cfc6aa | 3230 | || (REG_P (operand) |
eab89b90 | 3231 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER |
3a322c50 RK |
3232 | && reg_renumber[REGNO (operand)] < 0 |
3233 | /* If reg_equiv_address is nonzero, we will be | |
3234 | loading it into a register; hence it will be | |
3235 | offsettable, but we cannot say that reg_equiv_mem | |
3236 | is offsettable without checking. */ | |
3237 | && ((reg_equiv_mem[REGNO (operand)] != 0 | |
3238 | && offsettable_memref_p (reg_equiv_mem[REGNO (operand)])) | |
3239 | || (reg_equiv_address[REGNO (operand)] != 0)))) | |
eab89b90 | 3240 | win = 1; |
34208acf | 3241 | if (CONST_POOL_OK_P (operand) |
3c0cb5de | 3242 | || MEM_P (operand)) |
eab89b90 | 3243 | badop = 0; |
9d926da5 | 3244 | constmemok = 1; |
eab89b90 RK |
3245 | offmemok = 1; |
3246 | break; | |
3247 | ||
3248 | case '&': | |
3249 | /* Output operand that is stored before the need for the | |
3250 | input operands (and their index registers) is over. */ | |
3251 | earlyclobber = 1, this_earlyclobber = 1; | |
3252 | break; | |
3253 | ||
3254 | case 'E': | |
eab89b90 | 3255 | case 'F': |
bf7cd754 R |
3256 | if (GET_CODE (operand) == CONST_DOUBLE |
3257 | || (GET_CODE (operand) == CONST_VECTOR | |
3258 | && (GET_MODE_CLASS (GET_MODE (operand)) | |
3259 | == MODE_VECTOR_FLOAT))) | |
eab89b90 RK |
3260 | win = 1; |
3261 | break; | |
3262 | ||
3263 | case 'G': | |
3264 | case 'H': | |
3265 | if (GET_CODE (operand) == CONST_DOUBLE | |
97488870 | 3266 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (operand, c, p)) |
eab89b90 RK |
3267 | win = 1; |
3268 | break; | |
3269 | ||
3270 | case 's': | |
3271 | if (GET_CODE (operand) == CONST_INT | |
3272 | || (GET_CODE (operand) == CONST_DOUBLE | |
3273 | && GET_MODE (operand) == VOIDmode)) | |
3274 | break; | |
3275 | case 'i': | |
3276 | if (CONSTANT_P (operand) | |
2e4e72b1 | 3277 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand))) |
eab89b90 RK |
3278 | win = 1; |
3279 | break; | |
3280 | ||
3281 | case 'n': | |
3282 | if (GET_CODE (operand) == CONST_INT | |
3283 | || (GET_CODE (operand) == CONST_DOUBLE | |
3284 | && GET_MODE (operand) == VOIDmode)) | |
3285 | win = 1; | |
3286 | break; | |
3287 | ||
3288 | case 'I': | |
3289 | case 'J': | |
3290 | case 'K': | |
3291 | case 'L': | |
3292 | case 'M': | |
3293 | case 'N': | |
3294 | case 'O': | |
3295 | case 'P': | |
3296 | if (GET_CODE (operand) == CONST_INT | |
97488870 | 3297 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operand), c, p)) |
eab89b90 RK |
3298 | win = 1; |
3299 | break; | |
3300 | ||
3301 | case 'X': | |
6c65d757 | 3302 | force_reload = 0; |
eab89b90 RK |
3303 | win = 1; |
3304 | break; | |
3305 | ||
3306 | case 'g': | |
3307 | if (! force_reload | |
3308 | /* A PLUS is never a valid operand, but reload can make | |
3309 | it from a register when eliminating registers. */ | |
3310 | && GET_CODE (operand) != PLUS | |
3311 | /* A SCRATCH is not a valid operand. */ | |
3312 | && GET_CODE (operand) != SCRATCH | |
05d10675 BS |
3313 | && (! CONSTANT_P (operand) |
3314 | || ! flag_pic | |
eab89b90 | 3315 | || LEGITIMATE_PIC_OPERAND_P (operand)) |
eab89b90 | 3316 | && (GENERAL_REGS == ALL_REGS |
f8cfc6aa | 3317 | || !REG_P (operand) |
eab89b90 RK |
3318 | || (REGNO (operand) >= FIRST_PSEUDO_REGISTER |
3319 | && reg_renumber[REGNO (operand)] < 0))) | |
3320 | win = 1; | |
82efa2e5 | 3321 | /* Drop through into 'r' case. */ |
eab89b90 RK |
3322 | |
3323 | case 'r': | |
3324 | this_alternative[i] | |
3325 | = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS]; | |
3326 | goto reg; | |
3327 | ||
c2cba7a9 | 3328 | default: |
97488870 | 3329 | if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS) |
c2cba7a9 | 3330 | { |
97488870 R |
3331 | #ifdef EXTRA_CONSTRAINT_STR |
3332 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
ccfc6cc8 UW |
3333 | { |
3334 | if (force_reload) | |
3335 | break; | |
97488870 | 3336 | if (EXTRA_CONSTRAINT_STR (operand, c, p)) |
ccfc6cc8 UW |
3337 | win = 1; |
3338 | /* If the address was already reloaded, | |
3339 | we win as well. */ | |
3c0cb5de | 3340 | else if (MEM_P (operand) |
0b540f12 | 3341 | && address_reloaded[i] == 1) |
ccfc6cc8 UW |
3342 | win = 1; |
3343 | /* Likewise if the address will be reloaded because | |
3344 | reg_equiv_address is nonzero. For reg_equiv_mem | |
3345 | we have to check. */ | |
f8cfc6aa | 3346 | else if (REG_P (operand) |
3b6c3bb0 JW |
3347 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER |
3348 | && reg_renumber[REGNO (operand)] < 0 | |
3349 | && ((reg_equiv_mem[REGNO (operand)] != 0 | |
3350 | && EXTRA_CONSTRAINT_STR (reg_equiv_mem[REGNO (operand)], c, p)) | |
3351 | || (reg_equiv_address[REGNO (operand)] != 0))) | |
ccfc6cc8 UW |
3352 | win = 1; |
3353 | ||
3354 | /* If we didn't already win, we can reload | |
3355 | constants via force_const_mem, and other | |
3356 | MEMs by reloading the address like for 'o'. */ | |
34208acf | 3357 | if (CONST_POOL_OK_P (operand) |
3c0cb5de | 3358 | || MEM_P (operand)) |
ccfc6cc8 UW |
3359 | badop = 0; |
3360 | constmemok = 1; | |
3361 | offmemok = 1; | |
3362 | break; | |
3363 | } | |
97488870 | 3364 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) |
ccfc6cc8 | 3365 | { |
97488870 | 3366 | if (EXTRA_CONSTRAINT_STR (operand, c, p)) |
ccfc6cc8 UW |
3367 | win = 1; |
3368 | ||
3369 | /* If we didn't already win, we can reload | |
3370 | the address into a base register. */ | |
c4963a0a BS |
3371 | this_alternative[i] |
3372 | = (int) base_reg_class (VOIDmode, ADDRESS, SCRATCH); | |
ccfc6cc8 UW |
3373 | badop = 0; |
3374 | break; | |
3375 | } | |
3376 | ||
97488870 | 3377 | if (EXTRA_CONSTRAINT_STR (operand, c, p)) |
c2cba7a9 | 3378 | win = 1; |
eab89b90 | 3379 | #endif |
c2cba7a9 RH |
3380 | break; |
3381 | } | |
05d10675 | 3382 | |
eab89b90 | 3383 | this_alternative[i] |
97488870 R |
3384 | = (int) (reg_class_subunion |
3385 | [this_alternative[i]] | |
3386 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]); | |
eab89b90 RK |
3387 | reg: |
3388 | if (GET_MODE (operand) == BLKmode) | |
3389 | break; | |
3390 | winreg = 1; | |
f8cfc6aa | 3391 | if (REG_P (operand) |
eab89b90 | 3392 | && reg_fits_class_p (operand, this_alternative[i], |
1ccbefce | 3393 | offset, GET_MODE (recog_data.operand[i]))) |
eab89b90 RK |
3394 | win = 1; |
3395 | break; | |
3396 | } | |
97488870 | 3397 | while ((p += len), c); |
eab89b90 RK |
3398 | |
3399 | constraints[i] = p; | |
3400 | ||
3401 | /* If this operand could be handled with a reg, | |
3402 | and some reg is allowed, then this operand can be handled. */ | |
3403 | if (winreg && this_alternative[i] != (int) NO_REGS) | |
3404 | badop = 0; | |
3405 | ||
3406 | /* Record which operands fit this alternative. */ | |
3407 | this_alternative_earlyclobber[i] = earlyclobber; | |
3408 | if (win && ! force_reload) | |
3409 | this_alternative_win[i] = 1; | |
69add2a8 BS |
3410 | else if (did_match && ! force_reload) |
3411 | this_alternative_match_win[i] = 1; | |
eab89b90 RK |
3412 | else |
3413 | { | |
9d926da5 RK |
3414 | int const_to_mem = 0; |
3415 | ||
eab89b90 RK |
3416 | this_alternative_offmemok[i] = offmemok; |
3417 | losers++; | |
3418 | if (badop) | |
3419 | bad = 1; | |
3420 | /* Alternative loses if it has no regs for a reg operand. */ | |
f8cfc6aa | 3421 | if (REG_P (operand) |
eab89b90 RK |
3422 | && this_alternative[i] == (int) NO_REGS |
3423 | && this_alternative_matches[i] < 0) | |
3424 | bad = 1; | |
3425 | ||
3a322c50 RK |
3426 | /* If this is a constant that is reloaded into the desired |
3427 | class by copying it to memory first, count that as another | |
3428 | reload. This is consistent with other code and is | |
293166be | 3429 | required to avoid choosing another alternative when |
3a322c50 | 3430 | the constant is moved into memory by this function on |
05d10675 | 3431 | an early reload pass. Note that the test here is |
3a322c50 RK |
3432 | precisely the same as in the code below that calls |
3433 | force_const_mem. */ | |
34208acf | 3434 | if (CONST_POOL_OK_P (operand) |
e5e809f4 | 3435 | && ((PREFERRED_RELOAD_CLASS (operand, |
05d10675 | 3436 | (enum reg_class) this_alternative[i]) |
e5e809f4 JL |
3437 | == NO_REGS) |
3438 | || no_input_reloads) | |
3a322c50 | 3439 | && operand_mode[i] != VOIDmode) |
9d926da5 RK |
3440 | { |
3441 | const_to_mem = 1; | |
3442 | if (this_alternative[i] != (int) NO_REGS) | |
3443 | losers++; | |
3444 | } | |
3a322c50 | 3445 | |
e5e809f4 JL |
3446 | /* Alternative loses if it requires a type of reload not |
3447 | permitted for this insn. We can always reload SCRATCH | |
3448 | and objects with a REG_UNUSED note. */ | |
b5c82fa1 | 3449 | if (GET_CODE (operand) != SCRATCH |
05d10675 BS |
3450 | && modified[i] != RELOAD_READ && no_output_reloads |
3451 | && ! find_reg_note (insn, REG_UNUSED, operand)) | |
e5e809f4 JL |
3452 | bad = 1; |
3453 | else if (modified[i] != RELOAD_WRITE && no_input_reloads | |
3454 | && ! const_to_mem) | |
3455 | bad = 1; | |
3456 | ||
b5c82fa1 PB |
3457 | /* If we can't reload this value at all, reject this |
3458 | alternative. Note that we could also lose due to | |
3459 | LIMIT_RELOAD_CLASS, but we don't check that | |
3460 | here. */ | |
3461 | ||
3462 | if (! CONSTANT_P (operand) | |
3463 | && (enum reg_class) this_alternative[i] != NO_REGS) | |
3464 | { | |
3465 | if (PREFERRED_RELOAD_CLASS | |
3466 | (operand, (enum reg_class) this_alternative[i]) | |
3467 | == NO_REGS) | |
3468 | reject = 600; | |
3469 | ||
3470 | #ifdef PREFERRED_OUTPUT_RELOAD_CLASS | |
3471 | if (operand_type[i] == RELOAD_FOR_OUTPUT | |
3472 | && PREFERRED_OUTPUT_RELOAD_CLASS | |
3473 | (operand, (enum reg_class) this_alternative[i]) | |
3474 | == NO_REGS) | |
3475 | reject = 600; | |
3476 | #endif | |
3477 | } | |
3478 | ||
eab89b90 RK |
3479 | /* We prefer to reload pseudos over reloading other things, |
3480 | since such reloads may be able to be eliminated later. | |
3481 | If we are reloading a SCRATCH, we won't be generating any | |
05d10675 | 3482 | insns, just using a register, so it is also preferred. |
9d926da5 RK |
3483 | So bump REJECT in other cases. Don't do this in the |
3484 | case where we are forcing a constant into memory and | |
3485 | it will then win since we don't want to have a different | |
3486 | alternative match then. */ | |
f8cfc6aa | 3487 | if (! (REG_P (operand) |
915bb763 | 3488 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER) |
9d926da5 RK |
3489 | && GET_CODE (operand) != SCRATCH |
3490 | && ! (const_to_mem && constmemok)) | |
812f2051 R |
3491 | reject += 2; |
3492 | ||
3493 | /* Input reloads can be inherited more often than output | |
3494 | reloads can be removed, so penalize output reloads. */ | |
7924156a JW |
3495 | if (operand_type[i] != RELOAD_FOR_INPUT |
3496 | && GET_CODE (operand) != SCRATCH) | |
eab89b90 RK |
3497 | reject++; |
3498 | } | |
3499 | ||
05d10675 | 3500 | /* If this operand is a pseudo register that didn't get a hard |
eab89b90 RK |
3501 | reg and this alternative accepts some register, see if the |
3502 | class that we want is a subset of the preferred class for this | |
3503 | register. If not, but it intersects that class, use the | |
3504 | preferred class instead. If it does not intersect the preferred | |
3505 | class, show that usage of this alternative should be discouraged; | |
3506 | it will be discouraged more still if the register is `preferred | |
3507 | or nothing'. We do this because it increases the chance of | |
3508 | reusing our spill register in a later insn and avoiding a pair | |
3509 | of memory stores and loads. | |
3510 | ||
3511 | Don't bother with this if this alternative will accept this | |
3512 | operand. | |
3513 | ||
a2d353e5 RK |
3514 | Don't do this for a multiword operand, since it is only a |
3515 | small win and has the risk of requiring more spill registers, | |
3516 | which could cause a large loss. | |
5aa14fee | 3517 | |
eab89b90 RK |
3518 | Don't do this if the preferred class has only one register |
3519 | because we might otherwise exhaust the class. */ | |
3520 | ||
69add2a8 BS |
3521 | if (! win && ! did_match |
3522 | && this_alternative[i] != (int) NO_REGS | |
5aa14fee | 3523 | && GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD |
e9840398 AO |
3524 | && reg_class_size [(int) preferred_class[i]] > 0 |
3525 | && ! SMALL_REGISTER_CLASS_P (preferred_class[i])) | |
eab89b90 RK |
3526 | { |
3527 | if (! reg_class_subset_p (this_alternative[i], | |
3528 | preferred_class[i])) | |
3529 | { | |
3530 | /* Since we don't have a way of forming the intersection, | |
3531 | we just do something special if the preferred class | |
05d10675 | 3532 | is a subset of the class we have; that's the most |
eab89b90 RK |
3533 | common case anyway. */ |
3534 | if (reg_class_subset_p (preferred_class[i], | |
3535 | this_alternative[i])) | |
3536 | this_alternative[i] = (int) preferred_class[i]; | |
3537 | else | |
812f2051 | 3538 | reject += (2 + 2 * pref_or_nothing[i]); |
eab89b90 RK |
3539 | } |
3540 | } | |
3541 | } | |
3542 | ||
3543 | /* Now see if any output operands that are marked "earlyclobber" | |
3544 | in this alternative conflict with any input operands | |
3545 | or any memory addresses. */ | |
3546 | ||
3547 | for (i = 0; i < noperands; i++) | |
3548 | if (this_alternative_earlyclobber[i] | |
69add2a8 | 3549 | && (this_alternative_win[i] || this_alternative_match_win[i])) |
eab89b90 | 3550 | { |
05d10675 | 3551 | struct decomposition early_data; |
eab89b90 | 3552 | |
1ccbefce | 3553 | early_data = decompose (recog_data.operand[i]); |
eab89b90 | 3554 | |
41374e13 | 3555 | gcc_assert (modified[i] != RELOAD_READ); |
05d10675 | 3556 | |
eab89b90 RK |
3557 | if (this_alternative[i] == NO_REGS) |
3558 | { | |
3559 | this_alternative_earlyclobber[i] = 0; | |
41374e13 NS |
3560 | gcc_assert (this_insn_is_asm); |
3561 | error_for_asm (this_insn, | |
971801ff | 3562 | "%<&%> constraint used with no register class"); |
eab89b90 RK |
3563 | } |
3564 | ||
3565 | for (j = 0; j < noperands; j++) | |
3566 | /* Is this an input operand or a memory ref? */ | |
3c0cb5de | 3567 | if ((MEM_P (recog_data.operand[j]) |
eab89b90 RK |
3568 | || modified[j] != RELOAD_WRITE) |
3569 | && j != i | |
3570 | /* Ignore things like match_operator operands. */ | |
1ccbefce | 3571 | && *recog_data.constraints[j] != 0 |
eab89b90 RK |
3572 | /* Don't count an input operand that is constrained to match |
3573 | the early clobber operand. */ | |
3574 | && ! (this_alternative_matches[j] == i | |
1ccbefce RH |
3575 | && rtx_equal_p (recog_data.operand[i], |
3576 | recog_data.operand[j])) | |
eab89b90 | 3577 | /* Is it altered by storing the earlyclobber operand? */ |
1ccbefce RH |
3578 | && !immune_p (recog_data.operand[j], recog_data.operand[i], |
3579 | early_data)) | |
eab89b90 | 3580 | { |
e9840398 | 3581 | /* If the output is in a non-empty few-regs class, |
eab89b90 | 3582 | it's costly to reload it, so reload the input instead. */ |
e9840398 | 3583 | if (SMALL_REGISTER_CLASS_P (this_alternative[i]) |
f8cfc6aa | 3584 | && (REG_P (recog_data.operand[j]) |
1ccbefce | 3585 | || GET_CODE (recog_data.operand[j]) == SUBREG)) |
eab89b90 RK |
3586 | { |
3587 | losers++; | |
3588 | this_alternative_win[j] = 0; | |
69add2a8 | 3589 | this_alternative_match_win[j] = 0; |
eab89b90 RK |
3590 | } |
3591 | else | |
3592 | break; | |
3593 | } | |
3594 | /* If an earlyclobber operand conflicts with something, | |
3595 | it must be reloaded, so request this and count the cost. */ | |
3596 | if (j != noperands) | |
3597 | { | |
3598 | losers++; | |
3599 | this_alternative_win[i] = 0; | |
69add2a8 | 3600 | this_alternative_match_win[j] = 0; |
eab89b90 RK |
3601 | for (j = 0; j < noperands; j++) |
3602 | if (this_alternative_matches[j] == i | |
69add2a8 | 3603 | && this_alternative_match_win[j]) |
eab89b90 RK |
3604 | { |
3605 | this_alternative_win[j] = 0; | |
69add2a8 | 3606 | this_alternative_match_win[j] = 0; |
eab89b90 RK |
3607 | losers++; |
3608 | } | |
3609 | } | |
3610 | } | |
3611 | ||
3612 | /* If one alternative accepts all the operands, no reload required, | |
3613 | choose that alternative; don't consider the remaining ones. */ | |
3614 | if (losers == 0) | |
3615 | { | |
3616 | /* Unswap these so that they are never swapped at `finish'. */ | |
3617 | if (commutative >= 0) | |
3618 | { | |
1ccbefce RH |
3619 | recog_data.operand[commutative] = substed_operand[commutative]; |
3620 | recog_data.operand[commutative + 1] | |
eab89b90 RK |
3621 | = substed_operand[commutative + 1]; |
3622 | } | |
3623 | for (i = 0; i < noperands; i++) | |
3624 | { | |
69add2a8 BS |
3625 | goal_alternative_win[i] = this_alternative_win[i]; |
3626 | goal_alternative_match_win[i] = this_alternative_match_win[i]; | |
eab89b90 RK |
3627 | goal_alternative[i] = this_alternative[i]; |
3628 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; | |
3629 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3630 | goal_alternative_earlyclobber[i] | |
3631 | = this_alternative_earlyclobber[i]; | |
3632 | } | |
3633 | goal_alternative_number = this_alternative_number; | |
3634 | goal_alternative_swapped = swapped; | |
3635 | goal_earlyclobber = this_earlyclobber; | |
3636 | goto finish; | |
3637 | } | |
3638 | ||
3639 | /* REJECT, set by the ! and ? constraint characters and when a register | |
3640 | would be reloaded into a non-preferred class, discourages the use of | |
812f2051 R |
3641 | this alternative for a reload goal. REJECT is incremented by six |
3642 | for each ? and two for each non-preferred class. */ | |
3643 | losers = losers * 6 + reject; | |
eab89b90 RK |
3644 | |
3645 | /* If this alternative can be made to work by reloading, | |
3646 | and it needs less reloading than the others checked so far, | |
3647 | record it as the chosen goal for reloading. */ | |
3648 | if (! bad && best > losers) | |
3649 | { | |
3650 | for (i = 0; i < noperands; i++) | |
3651 | { | |
3652 | goal_alternative[i] = this_alternative[i]; | |
3653 | goal_alternative_win[i] = this_alternative_win[i]; | |
69add2a8 | 3654 | goal_alternative_match_win[i] = this_alternative_match_win[i]; |
eab89b90 RK |
3655 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; |
3656 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3657 | goal_alternative_earlyclobber[i] | |
3658 | = this_alternative_earlyclobber[i]; | |
3659 | } | |
3660 | goal_alternative_swapped = swapped; | |
3661 | best = losers; | |
3662 | goal_alternative_number = this_alternative_number; | |
3663 | goal_earlyclobber = this_earlyclobber; | |
3664 | } | |
3665 | } | |
3666 | ||
3667 | /* If insn is commutative (it's safe to exchange a certain pair of operands) | |
3668 | then we need to try each alternative twice, | |
3669 | the second time matching those two operands | |
3670 | as if we had exchanged them. | |
3671 | To do this, really exchange them in operands. | |
3672 | ||
3673 | If we have just tried the alternatives the second time, | |
3674 | return operands to normal and drop through. */ | |
3675 | ||
3676 | if (commutative >= 0) | |
3677 | { | |
3678 | swapped = !swapped; | |
3679 | if (swapped) | |
3680 | { | |
b3694847 SS |
3681 | enum reg_class tclass; |
3682 | int t; | |
eab89b90 | 3683 | |
1ccbefce RH |
3684 | recog_data.operand[commutative] = substed_operand[commutative + 1]; |
3685 | recog_data.operand[commutative + 1] = substed_operand[commutative]; | |
9cd56be1 JH |
3686 | /* Swap the duplicates too. */ |
3687 | for (i = 0; i < recog_data.n_dups; i++) | |
3688 | if (recog_data.dup_num[i] == commutative | |
3689 | || recog_data.dup_num[i] == commutative + 1) | |
3690 | *recog_data.dup_loc[i] | |
3691 | = recog_data.operand[(int) recog_data.dup_num[i]]; | |
eab89b90 RK |
3692 | |
3693 | tclass = preferred_class[commutative]; | |
3694 | preferred_class[commutative] = preferred_class[commutative + 1]; | |
3695 | preferred_class[commutative + 1] = tclass; | |
3696 | ||
3697 | t = pref_or_nothing[commutative]; | |
3698 | pref_or_nothing[commutative] = pref_or_nothing[commutative + 1]; | |
3699 | pref_or_nothing[commutative + 1] = t; | |
3700 | ||
e88d55cd UW |
3701 | t = address_reloaded[commutative]; |
3702 | address_reloaded[commutative] = address_reloaded[commutative + 1]; | |
3703 | address_reloaded[commutative + 1] = t; | |
3704 | ||
f428f252 KG |
3705 | memcpy (constraints, recog_data.constraints, |
3706 | noperands * sizeof (char *)); | |
eab89b90 RK |
3707 | goto try_swapped; |
3708 | } | |
3709 | else | |
3710 | { | |
1ccbefce RH |
3711 | recog_data.operand[commutative] = substed_operand[commutative]; |
3712 | recog_data.operand[commutative + 1] | |
3713 | = substed_operand[commutative + 1]; | |
9cd56be1 JH |
3714 | /* Unswap the duplicates too. */ |
3715 | for (i = 0; i < recog_data.n_dups; i++) | |
3716 | if (recog_data.dup_num[i] == commutative | |
3717 | || recog_data.dup_num[i] == commutative + 1) | |
3718 | *recog_data.dup_loc[i] | |
3719 | = recog_data.operand[(int) recog_data.dup_num[i]]; | |
eab89b90 RK |
3720 | } |
3721 | } | |
3722 | ||
3723 | /* The operands don't meet the constraints. | |
3724 | goal_alternative describes the alternative | |
3725 | that we could reach by reloading the fewest operands. | |
3726 | Reload so as to fit it. */ | |
3727 | ||
c22eaf8a | 3728 | if (best == MAX_RECOG_OPERANDS * 2 + 600) |
eab89b90 RK |
3729 | { |
3730 | /* No alternative works with reloads?? */ | |
3731 | if (insn_code_number >= 0) | |
1f978f5f | 3732 | fatal_insn ("unable to generate reloads for:", insn); |
971801ff | 3733 | error_for_asm (insn, "inconsistent operand constraints in an %<asm%>"); |
eab89b90 | 3734 | /* Avoid further trouble with this insn. */ |
38a448ca | 3735 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
eab89b90 | 3736 | n_reloads = 0; |
cb2afeb3 | 3737 | return 0; |
eab89b90 RK |
3738 | } |
3739 | ||
3740 | /* Jump to `finish' from above if all operands are valid already. | |
3741 | In that case, goal_alternative_win is all 1. */ | |
3742 | finish: | |
3743 | ||
3744 | /* Right now, for any pair of operands I and J that are required to match, | |
3745 | with I < J, | |
3746 | goal_alternative_matches[J] is I. | |
3747 | Set up goal_alternative_matched as the inverse function: | |
3748 | goal_alternative_matched[I] = J. */ | |
3749 | ||
3750 | for (i = 0; i < noperands; i++) | |
3751 | goal_alternative_matched[i] = -1; | |
a6a2274a | 3752 | |
eab89b90 RK |
3753 | for (i = 0; i < noperands; i++) |
3754 | if (! goal_alternative_win[i] | |
3755 | && goal_alternative_matches[i] >= 0) | |
3756 | goal_alternative_matched[goal_alternative_matches[i]] = i; | |
3757 | ||
69add2a8 BS |
3758 | for (i = 0; i < noperands; i++) |
3759 | goal_alternative_win[i] |= goal_alternative_match_win[i]; | |
3760 | ||
eab89b90 | 3761 | /* If the best alternative is with operands 1 and 2 swapped, |
a8c9daeb RK |
3762 | consider them swapped before reporting the reloads. Update the |
3763 | operand numbers of any reloads already pushed. */ | |
eab89b90 RK |
3764 | |
3765 | if (goal_alternative_swapped) | |
3766 | { | |
b3694847 | 3767 | rtx tem; |
eab89b90 RK |
3768 | |
3769 | tem = substed_operand[commutative]; | |
3770 | substed_operand[commutative] = substed_operand[commutative + 1]; | |
3771 | substed_operand[commutative + 1] = tem; | |
1ccbefce RH |
3772 | tem = recog_data.operand[commutative]; |
3773 | recog_data.operand[commutative] = recog_data.operand[commutative + 1]; | |
3774 | recog_data.operand[commutative + 1] = tem; | |
3775 | tem = *recog_data.operand_loc[commutative]; | |
3776 | *recog_data.operand_loc[commutative] | |
3777 | = *recog_data.operand_loc[commutative + 1]; | |
4381f7c2 | 3778 | *recog_data.operand_loc[commutative + 1] = tem; |
a8c9daeb RK |
3779 | |
3780 | for (i = 0; i < n_reloads; i++) | |
3781 | { | |
eceef4c9 BS |
3782 | if (rld[i].opnum == commutative) |
3783 | rld[i].opnum = commutative + 1; | |
3784 | else if (rld[i].opnum == commutative + 1) | |
3785 | rld[i].opnum = commutative; | |
a8c9daeb | 3786 | } |
eab89b90 RK |
3787 | } |
3788 | ||
eab89b90 RK |
3789 | for (i = 0; i < noperands; i++) |
3790 | { | |
eab89b90 | 3791 | operand_reloadnum[i] = -1; |
a8c9daeb RK |
3792 | |
3793 | /* If this is an earlyclobber operand, we need to widen the scope. | |
3794 | The reload must remain valid from the start of the insn being | |
3795 | reloaded until after the operand is stored into its destination. | |
3796 | We approximate this with RELOAD_OTHER even though we know that we | |
3797 | do not conflict with RELOAD_FOR_INPUT_ADDRESS reloads. | |
3798 | ||
3799 | One special case that is worth checking is when we have an | |
3800 | output that is earlyclobber but isn't used past the insn (typically | |
05d10675 | 3801 | a SCRATCH). In this case, we only need have the reload live |
a8c9daeb | 3802 | through the insn itself, but not for any of our input or output |
05d10675 | 3803 | reloads. |
f9df0a1d R |
3804 | But we must not accidentally narrow the scope of an existing |
3805 | RELOAD_OTHER reload - leave these alone. | |
a8c9daeb RK |
3806 | |
3807 | In any case, anything needed to address this operand can remain | |
3808 | however they were previously categorized. */ | |
3809 | ||
f9df0a1d | 3810 | if (goal_alternative_earlyclobber[i] && operand_type[i] != RELOAD_OTHER) |
a8c9daeb | 3811 | operand_type[i] |
1ccbefce | 3812 | = (find_reg_note (insn, REG_UNUSED, recog_data.operand[i]) |
a8c9daeb | 3813 | ? RELOAD_FOR_INSN : RELOAD_OTHER); |
eab89b90 RK |
3814 | } |
3815 | ||
3816 | /* Any constants that aren't allowed and can't be reloaded | |
3817 | into registers are here changed into memory references. */ | |
3818 | for (i = 0; i < noperands; i++) | |
3819 | if (! goal_alternative_win[i] | |
34208acf | 3820 | && CONST_POOL_OK_P (recog_data.operand[i]) |
1ccbefce | 3821 | && ((PREFERRED_RELOAD_CLASS (recog_data.operand[i], |
05d10675 | 3822 | (enum reg_class) goal_alternative[i]) |
e5e809f4 JL |
3823 | == NO_REGS) |
3824 | || no_input_reloads) | |
eab89b90 RK |
3825 | && operand_mode[i] != VOIDmode) |
3826 | { | |
1ccbefce | 3827 | substed_operand[i] = recog_data.operand[i] |
eab89b90 | 3828 | = find_reloads_toplev (force_const_mem (operand_mode[i], |
1ccbefce | 3829 | recog_data.operand[i]), |
9246aadb AH |
3830 | i, address_type[i], ind_levels, 0, insn, |
3831 | NULL); | |
1ccbefce | 3832 | if (alternative_allows_memconst (recog_data.constraints[i], |
eab89b90 RK |
3833 | goal_alternative_number)) |
3834 | goal_alternative_win[i] = 1; | |
3835 | } | |
3836 | ||
d58005c7 UW |
3837 | /* Likewise any invalid constants appearing as operand of a PLUS |
3838 | that is to be reloaded. */ | |
3839 | for (i = 0; i < noperands; i++) | |
3840 | if (! goal_alternative_win[i] | |
3841 | && GET_CODE (recog_data.operand[i]) == PLUS | |
3842 | && CONST_POOL_OK_P (XEXP (recog_data.operand[i], 1)) | |
3843 | && (PREFERRED_RELOAD_CLASS (XEXP (recog_data.operand[i], 1), | |
3844 | (enum reg_class) goal_alternative[i]) | |
3845 | == NO_REGS) | |
3846 | && operand_mode[i] != VOIDmode) | |
3847 | { | |
3848 | rtx tem = force_const_mem (operand_mode[i], | |
3849 | XEXP (recog_data.operand[i], 1)); | |
3850 | tem = gen_rtx_PLUS (operand_mode[i], | |
3851 | XEXP (recog_data.operand[i], 0), tem); | |
3852 | ||
3853 | substed_operand[i] = recog_data.operand[i] | |
3854 | = find_reloads_toplev (tem, i, address_type[i], | |
3855 | ind_levels, 0, insn, NULL); | |
3856 | } | |
3857 | ||
4644aad4 RK |
3858 | /* Record the values of the earlyclobber operands for the caller. */ |
3859 | if (goal_earlyclobber) | |
3860 | for (i = 0; i < noperands; i++) | |
3861 | if (goal_alternative_earlyclobber[i]) | |
1ccbefce | 3862 | reload_earlyclobbers[n_earlyclobbers++] = recog_data.operand[i]; |
4644aad4 | 3863 | |
eab89b90 RK |
3864 | /* Now record reloads for all the operands that need them. */ |
3865 | for (i = 0; i < noperands; i++) | |
3866 | if (! goal_alternative_win[i]) | |
3867 | { | |
3868 | /* Operands that match previous ones have already been handled. */ | |
3869 | if (goal_alternative_matches[i] >= 0) | |
3870 | ; | |
3871 | /* Handle an operand with a nonoffsettable address | |
3872 | appearing where an offsettable address will do | |
3a322c50 RK |
3873 | by reloading the address into a base register. |
3874 | ||
3875 | ??? We can also do this when the operand is a register and | |
3876 | reg_equiv_mem is not offsettable, but this is a bit tricky, | |
3877 | so we don't bother with it. It may not be worth doing. */ | |
eab89b90 RK |
3878 | else if (goal_alternative_matched[i] == -1 |
3879 | && goal_alternative_offmemok[i] | |
3c0cb5de | 3880 | && MEM_P (recog_data.operand[i])) |
eab89b90 | 3881 | { |
7c7ce73a UW |
3882 | /* If the address to be reloaded is a VOIDmode constant, |
3883 | use Pmode as mode of the reload register, as would have | |
3884 | been done by find_reloads_address. */ | |
3885 | enum machine_mode address_mode; | |
3886 | address_mode = GET_MODE (XEXP (recog_data.operand[i], 0)); | |
3887 | if (address_mode == VOIDmode) | |
3888 | address_mode = Pmode; | |
3889 | ||
eab89b90 | 3890 | operand_reloadnum[i] |
1ccbefce | 3891 | = push_reload (XEXP (recog_data.operand[i], 0), NULL_RTX, |
f4f4d0f8 | 3892 | &XEXP (recog_data.operand[i], 0), (rtx*) 0, |
c4963a0a | 3893 | base_reg_class (VOIDmode, MEM, SCRATCH), |
7c7ce73a | 3894 | address_mode, |
a8c9daeb | 3895 | VOIDmode, 0, 0, i, RELOAD_FOR_INPUT); |
eceef4c9 | 3896 | rld[operand_reloadnum[i]].inc |
1ccbefce | 3897 | = GET_MODE_SIZE (GET_MODE (recog_data.operand[i])); |
a8c9daeb RK |
3898 | |
3899 | /* If this operand is an output, we will have made any | |
3900 | reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but | |
3901 | now we are treating part of the operand as an input, so | |
3902 | we must change these to RELOAD_FOR_INPUT_ADDRESS. */ | |
3903 | ||
2d55b7e8 | 3904 | if (modified[i] == RELOAD_WRITE) |
47c8cf91 ILT |
3905 | { |
3906 | for (j = 0; j < n_reloads; j++) | |
3907 | { | |
eceef4c9 | 3908 | if (rld[j].opnum == i) |
47c8cf91 | 3909 | { |
eceef4c9 BS |
3910 | if (rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS) |
3911 | rld[j].when_needed = RELOAD_FOR_INPUT_ADDRESS; | |
3912 | else if (rld[j].when_needed | |
47c8cf91 | 3913 | == RELOAD_FOR_OUTADDR_ADDRESS) |
eceef4c9 | 3914 | rld[j].when_needed = RELOAD_FOR_INPADDR_ADDRESS; |
47c8cf91 ILT |
3915 | } |
3916 | } | |
3917 | } | |
eab89b90 RK |
3918 | } |
3919 | else if (goal_alternative_matched[i] == -1) | |
9ec36da5 JL |
3920 | { |
3921 | operand_reloadnum[i] | |
3922 | = push_reload ((modified[i] != RELOAD_WRITE | |
1ccbefce RH |
3923 | ? recog_data.operand[i] : 0), |
3924 | (modified[i] != RELOAD_READ | |
3925 | ? recog_data.operand[i] : 0), | |
9ec36da5 | 3926 | (modified[i] != RELOAD_WRITE |
1ccbefce | 3927 | ? recog_data.operand_loc[i] : 0), |
9ec36da5 | 3928 | (modified[i] != RELOAD_READ |
1ccbefce | 3929 | ? recog_data.operand_loc[i] : 0), |
9ec36da5 JL |
3930 | (enum reg_class) goal_alternative[i], |
3931 | (modified[i] == RELOAD_WRITE | |
3932 | ? VOIDmode : operand_mode[i]), | |
3933 | (modified[i] == RELOAD_READ | |
3934 | ? VOIDmode : operand_mode[i]), | |
3935 | (insn_code_number < 0 ? 0 | |
a995e389 | 3936 | : insn_data[insn_code_number].operand[i].strict_low), |
9ec36da5 | 3937 | 0, i, operand_type[i]); |
9ec36da5 | 3938 | } |
eab89b90 RK |
3939 | /* In a matching pair of operands, one must be input only |
3940 | and the other must be output only. | |
3941 | Pass the input operand as IN and the other as OUT. */ | |
3942 | else if (modified[i] == RELOAD_READ | |
3943 | && modified[goal_alternative_matched[i]] == RELOAD_WRITE) | |
3944 | { | |
3945 | operand_reloadnum[i] | |
1ccbefce RH |
3946 | = push_reload (recog_data.operand[i], |
3947 | recog_data.operand[goal_alternative_matched[i]], | |
3948 | recog_data.operand_loc[i], | |
3949 | recog_data.operand_loc[goal_alternative_matched[i]], | |
eab89b90 RK |
3950 | (enum reg_class) goal_alternative[i], |
3951 | operand_mode[i], | |
3952 | operand_mode[goal_alternative_matched[i]], | |
a8c9daeb | 3953 | 0, 0, i, RELOAD_OTHER); |
eab89b90 RK |
3954 | operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum; |
3955 | } | |
3956 | else if (modified[i] == RELOAD_WRITE | |
3957 | && modified[goal_alternative_matched[i]] == RELOAD_READ) | |
3958 | { | |
3959 | operand_reloadnum[goal_alternative_matched[i]] | |
1ccbefce RH |
3960 | = push_reload (recog_data.operand[goal_alternative_matched[i]], |
3961 | recog_data.operand[i], | |
3962 | recog_data.operand_loc[goal_alternative_matched[i]], | |
3963 | recog_data.operand_loc[i], | |
eab89b90 RK |
3964 | (enum reg_class) goal_alternative[i], |
3965 | operand_mode[goal_alternative_matched[i]], | |
3966 | operand_mode[i], | |
a8c9daeb | 3967 | 0, 0, i, RELOAD_OTHER); |
eab89b90 RK |
3968 | operand_reloadnum[i] = output_reloadnum; |
3969 | } | |
eab89b90 RK |
3970 | else |
3971 | { | |
41374e13 | 3972 | gcc_assert (insn_code_number < 0); |
971801ff JM |
3973 | error_for_asm (insn, "inconsistent operand constraints " |
3974 | "in an %<asm%>"); | |
eab89b90 | 3975 | /* Avoid further trouble with this insn. */ |
38a448ca | 3976 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
eab89b90 | 3977 | n_reloads = 0; |
cb2afeb3 | 3978 | return 0; |
eab89b90 RK |
3979 | } |
3980 | } | |
3981 | else if (goal_alternative_matched[i] < 0 | |
112f7223 | 3982 | && goal_alternative_matches[i] < 0 |
0b540f12 | 3983 | && address_operand_reloaded[i] != 1 |
112f7223 | 3984 | && optimize) |
eab89b90 | 3985 | { |
05d10675 | 3986 | /* For each non-matching operand that's a MEM or a pseudo-register |
eab89b90 RK |
3987 | that didn't get a hard register, make an optional reload. |
3988 | This may get done even if the insn needs no reloads otherwise. */ | |
a8c9daeb | 3989 | |
1ccbefce | 3990 | rtx operand = recog_data.operand[i]; |
a8c9daeb | 3991 | |
eab89b90 | 3992 | while (GET_CODE (operand) == SUBREG) |
ddef6bc7 | 3993 | operand = SUBREG_REG (operand); |
3c0cb5de | 3994 | if ((MEM_P (operand) |
f8cfc6aa | 3995 | || (REG_P (operand) |
a8c9daeb | 3996 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) |
cb2afeb3 R |
3997 | /* If this is only for an output, the optional reload would not |
3998 | actually cause us to use a register now, just note that | |
3999 | something is stored here. */ | |
4000 | && ((enum reg_class) goal_alternative[i] != NO_REGS | |
4001 | || modified[i] == RELOAD_WRITE) | |
a8c9daeb | 4002 | && ! no_input_reloads |
cb2afeb3 R |
4003 | /* An optional output reload might allow to delete INSN later. |
4004 | We mustn't make in-out reloads on insns that are not permitted | |
4005 | output reloads. | |
4006 | If this is an asm, we can't delete it; we must not even call | |
4007 | push_reload for an optional output reload in this case, | |
4008 | because we can't be sure that the constraint allows a register, | |
4009 | and push_reload verifies the constraints for asms. */ | |
eab89b90 | 4010 | && (modified[i] == RELOAD_READ |
cb2afeb3 | 4011 | || (! no_output_reloads && ! this_insn_is_asm))) |
eab89b90 | 4012 | operand_reloadnum[i] |
1ccbefce RH |
4013 | = push_reload ((modified[i] != RELOAD_WRITE |
4014 | ? recog_data.operand[i] : 0), | |
4015 | (modified[i] != RELOAD_READ | |
4016 | ? recog_data.operand[i] : 0), | |
a8c9daeb | 4017 | (modified[i] != RELOAD_WRITE |
1ccbefce | 4018 | ? recog_data.operand_loc[i] : 0), |
a8c9daeb | 4019 | (modified[i] != RELOAD_READ |
1ccbefce | 4020 | ? recog_data.operand_loc[i] : 0), |
eab89b90 | 4021 | (enum reg_class) goal_alternative[i], |
a8c9daeb RK |
4022 | (modified[i] == RELOAD_WRITE |
4023 | ? VOIDmode : operand_mode[i]), | |
4024 | (modified[i] == RELOAD_READ | |
4025 | ? VOIDmode : operand_mode[i]), | |
eab89b90 | 4026 | (insn_code_number < 0 ? 0 |
a995e389 | 4027 | : insn_data[insn_code_number].operand[i].strict_low), |
a8c9daeb | 4028 | 1, i, operand_type[i]); |
87afbee6 JL |
4029 | /* If a memory reference remains (either as a MEM or a pseudo that |
4030 | did not get a hard register), yet we can't make an optional | |
cb2afeb3 R |
4031 | reload, check if this is actually a pseudo register reference; |
4032 | we then need to emit a USE and/or a CLOBBER so that reload | |
4033 | inheritance will do the right thing. */ | |
112f7223 | 4034 | else if (replace |
3c0cb5de | 4035 | && (MEM_P (operand) |
f8cfc6aa | 4036 | || (REG_P (operand) |
112f7223 UW |
4037 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER |
4038 | && reg_renumber [REGNO (operand)] < 0))) | |
cb2afeb3 | 4039 | { |
1ccbefce | 4040 | operand = *recog_data.operand_loc[i]; |
cb2afeb3 R |
4041 | |
4042 | while (GET_CODE (operand) == SUBREG) | |
ddef6bc7 | 4043 | operand = SUBREG_REG (operand); |
f8cfc6aa | 4044 | if (REG_P (operand)) |
cb2afeb3 R |
4045 | { |
4046 | if (modified[i] != RELOAD_WRITE) | |
3d17d93d AO |
4047 | /* We mark the USE with QImode so that we recognize |
4048 | it as one that can be safely deleted at the end | |
4049 | of reload. */ | |
4050 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, operand), | |
4051 | insn), QImode); | |
cb2afeb3 R |
4052 | if (modified[i] != RELOAD_READ) |
4053 | emit_insn_after (gen_rtx_CLOBBER (VOIDmode, operand), insn); | |
4054 | } | |
4055 | } | |
eab89b90 | 4056 | } |
a8c9daeb RK |
4057 | else if (goal_alternative_matches[i] >= 0 |
4058 | && goal_alternative_win[goal_alternative_matches[i]] | |
4059 | && modified[i] == RELOAD_READ | |
4060 | && modified[goal_alternative_matches[i]] == RELOAD_WRITE | |
112f7223 UW |
4061 | && ! no_input_reloads && ! no_output_reloads |
4062 | && optimize) | |
a8c9daeb RK |
4063 | { |
4064 | /* Similarly, make an optional reload for a pair of matching | |
4065 | objects that are in MEM or a pseudo that didn't get a hard reg. */ | |
eab89b90 | 4066 | |
1ccbefce | 4067 | rtx operand = recog_data.operand[i]; |
a8c9daeb RK |
4068 | |
4069 | while (GET_CODE (operand) == SUBREG) | |
ddef6bc7 | 4070 | operand = SUBREG_REG (operand); |
3c0cb5de | 4071 | if ((MEM_P (operand) |
f8cfc6aa | 4072 | || (REG_P (operand) |
a8c9daeb RK |
4073 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) |
4074 | && ((enum reg_class) goal_alternative[goal_alternative_matches[i]] | |
4075 | != NO_REGS)) | |
4076 | operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]] | |
1ccbefce RH |
4077 | = push_reload (recog_data.operand[goal_alternative_matches[i]], |
4078 | recog_data.operand[i], | |
4079 | recog_data.operand_loc[goal_alternative_matches[i]], | |
4080 | recog_data.operand_loc[i], | |
a8c9daeb RK |
4081 | (enum reg_class) goal_alternative[goal_alternative_matches[i]], |
4082 | operand_mode[goal_alternative_matches[i]], | |
4083 | operand_mode[i], | |
4084 | 0, 1, goal_alternative_matches[i], RELOAD_OTHER); | |
4085 | } | |
05d10675 | 4086 | |
cb2afeb3 R |
4087 | /* Perform whatever substitutions on the operands we are supposed |
4088 | to make due to commutativity or replacement of registers | |
4089 | with equivalent constants or memory slots. */ | |
4090 | ||
4091 | for (i = 0; i < noperands; i++) | |
4092 | { | |
4093 | /* We only do this on the last pass through reload, because it is | |
05d10675 | 4094 | possible for some data (like reg_equiv_address) to be changed during |
425de739 | 4095 | later passes. Moreover, we lose the opportunity to get a useful |
05d10675 | 4096 | reload_{in,out}_reg when we do these replacements. */ |
cb2afeb3 R |
4097 | |
4098 | if (replace) | |
e54db24f MM |
4099 | { |
4100 | rtx substitution = substed_operand[i]; | |
4101 | ||
1ccbefce | 4102 | *recog_data.operand_loc[i] = substitution; |
e54db24f MM |
4103 | |
4104 | /* If we're replacing an operand with a LABEL_REF, we need | |
4105 | to make sure that there's a REG_LABEL note attached to | |
4106 | this instruction. */ | |
4b4bf941 | 4107 | if (!JUMP_P (insn) |
e54db24f MM |
4108 | && GET_CODE (substitution) == LABEL_REF |
4109 | && !find_reg_note (insn, REG_LABEL, XEXP (substitution, 0))) | |
6b8c9327 | 4110 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, |
e54db24f MM |
4111 | XEXP (substitution, 0), |
4112 | REG_NOTES (insn)); | |
4113 | } | |
cb2afeb3 | 4114 | else |
1ccbefce | 4115 | retval |= (substed_operand[i] != *recog_data.operand_loc[i]); |
cb2afeb3 R |
4116 | } |
4117 | ||
eab89b90 RK |
4118 | /* If this insn pattern contains any MATCH_DUP's, make sure that |
4119 | they will be substituted if the operands they match are substituted. | |
4120 | Also do now any substitutions we already did on the operands. | |
4121 | ||
4122 | Don't do this if we aren't making replacements because we might be | |
4123 | propagating things allocated by frame pointer elimination into places | |
4124 | it doesn't expect. */ | |
4125 | ||
4126 | if (insn_code_number >= 0 && replace) | |
a995e389 | 4127 | for (i = insn_data[insn_code_number].n_dups - 1; i >= 0; i--) |
eab89b90 | 4128 | { |
1ccbefce RH |
4129 | int opno = recog_data.dup_num[i]; |
4130 | *recog_data.dup_loc[i] = *recog_data.operand_loc[opno]; | |
6cabe79e | 4131 | dup_replacements (recog_data.dup_loc[i], recog_data.operand_loc[opno]); |
eab89b90 RK |
4132 | } |
4133 | ||
4134 | #if 0 | |
4135 | /* This loses because reloading of prior insns can invalidate the equivalence | |
4136 | (or at least find_equiv_reg isn't smart enough to find it any more), | |
4137 | causing this insn to need more reload regs than it needed before. | |
4138 | It may be too late to make the reload regs available. | |
4139 | Now this optimization is done safely in choose_reload_regs. */ | |
4140 | ||
4141 | /* For each reload of a reg into some other class of reg, | |
4142 | search for an existing equivalent reg (same value now) in the right class. | |
4143 | We can use it as long as we don't need to change its contents. */ | |
4144 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 BS |
4145 | if (rld[i].reg_rtx == 0 |
4146 | && rld[i].in != 0 | |
f8cfc6aa | 4147 | && REG_P (rld[i].in) |
eceef4c9 | 4148 | && rld[i].out == 0) |
eab89b90 | 4149 | { |
eceef4c9 BS |
4150 | rld[i].reg_rtx |
4151 | = find_equiv_reg (rld[i].in, insn, rld[i].class, -1, | |
4152 | static_reload_reg_p, 0, rld[i].inmode); | |
eab89b90 RK |
4153 | /* Prevent generation of insn to load the value |
4154 | because the one we found already has the value. */ | |
eceef4c9 BS |
4155 | if (rld[i].reg_rtx) |
4156 | rld[i].in = rld[i].reg_rtx; | |
eab89b90 RK |
4157 | } |
4158 | #endif | |
4159 | ||
71156bcc JH |
4160 | /* If we detected error and replaced asm instruction by USE, forget about the |
4161 | reloads. */ | |
4162 | if (GET_CODE (PATTERN (insn)) == USE | |
4163 | && GET_CODE (XEXP (PATTERN (insn), 0)) == CONST_INT) | |
4164 | n_reloads = 0; | |
4165 | ||
a8c9daeb RK |
4166 | /* Perhaps an output reload can be combined with another |
4167 | to reduce needs by one. */ | |
4168 | if (!goal_earlyclobber) | |
4169 | combine_reloads (); | |
4170 | ||
4171 | /* If we have a pair of reloads for parts of an address, they are reloading | |
4172 | the same object, the operands themselves were not reloaded, and they | |
4173 | are for two operands that are supposed to match, merge the reloads and | |
0f41302f | 4174 | change the type of the surviving reload to RELOAD_FOR_OPERAND_ADDRESS. */ |
a8c9daeb RK |
4175 | |
4176 | for (i = 0; i < n_reloads; i++) | |
4177 | { | |
4178 | int k; | |
4179 | ||
4180 | for (j = i + 1; j < n_reloads; j++) | |
eceef4c9 BS |
4181 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS |
4182 | || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
4183 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS | |
4184 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4185 | && (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
4186 | || rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
4187 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS | |
4188 | || rld[j].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4189 | && rtx_equal_p (rld[i].in, rld[j].in) | |
4190 | && (operand_reloadnum[rld[i].opnum] < 0 | |
4191 | || rld[operand_reloadnum[rld[i].opnum]].optional) | |
4192 | && (operand_reloadnum[rld[j].opnum] < 0 | |
4193 | || rld[operand_reloadnum[rld[j].opnum]].optional) | |
4194 | && (goal_alternative_matches[rld[i].opnum] == rld[j].opnum | |
4195 | || (goal_alternative_matches[rld[j].opnum] | |
4196 | == rld[i].opnum))) | |
a8c9daeb RK |
4197 | { |
4198 | for (k = 0; k < n_replacements; k++) | |
4199 | if (replacements[k].what == j) | |
4200 | replacements[k].what = i; | |
4201 | ||
eceef4c9 BS |
4202 | if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS |
4203 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4204 | rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR; | |
47c8cf91 | 4205 | else |
eceef4c9 BS |
4206 | rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS; |
4207 | rld[j].in = 0; | |
a8c9daeb RK |
4208 | } |
4209 | } | |
4210 | ||
05d10675 | 4211 | /* Scan all the reloads and update their type. |
a8c9daeb RK |
4212 | If a reload is for the address of an operand and we didn't reload |
4213 | that operand, change the type. Similarly, change the operand number | |
4214 | of a reload when two operands match. If a reload is optional, treat it | |
4215 | as though the operand isn't reloaded. | |
4216 | ||
4217 | ??? This latter case is somewhat odd because if we do the optional | |
4218 | reload, it means the object is hanging around. Thus we need only | |
4219 | do the address reload if the optional reload was NOT done. | |
4220 | ||
4221 | Change secondary reloads to be the address type of their operand, not | |
4222 | the normal type. | |
4223 | ||
4224 | If an operand's reload is now RELOAD_OTHER, change any | |
4225 | RELOAD_FOR_INPUT_ADDRESS reloads of that operand to | |
4226 | RELOAD_FOR_OTHER_ADDRESS. */ | |
4227 | ||
4228 | for (i = 0; i < n_reloads; i++) | |
4229 | { | |
eceef4c9 | 4230 | if (rld[i].secondary_p |
38323cc3 RH |
4231 | && rld[i].when_needed == operand_type[rld[i].opnum]) |
4232 | rld[i].when_needed = address_type[rld[i].opnum]; | |
eceef4c9 BS |
4233 | |
4234 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
4235 | || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
4236 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS | |
4237 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4238 | && (operand_reloadnum[rld[i].opnum] < 0 | |
4239 | || rld[operand_reloadnum[rld[i].opnum]].optional)) | |
f98bb7d3 RK |
4240 | { |
4241 | /* If we have a secondary reload to go along with this reload, | |
0f41302f | 4242 | change its type to RELOAD_FOR_OPADDR_ADDR. */ |
f98bb7d3 | 4243 | |
eceef4c9 BS |
4244 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS |
4245 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
4246 | && rld[i].secondary_in_reload != -1) | |
f98bb7d3 | 4247 | { |
eceef4c9 | 4248 | int secondary_in_reload = rld[i].secondary_in_reload; |
f98bb7d3 | 4249 | |
4381f7c2 | 4250 | rld[secondary_in_reload].when_needed = RELOAD_FOR_OPADDR_ADDR; |
f98bb7d3 | 4251 | |
0f41302f | 4252 | /* If there's a tertiary reload we have to change it also. */ |
f98bb7d3 | 4253 | if (secondary_in_reload > 0 |
eceef4c9 BS |
4254 | && rld[secondary_in_reload].secondary_in_reload != -1) |
4255 | rld[rld[secondary_in_reload].secondary_in_reload].when_needed | |
38323cc3 | 4256 | = RELOAD_FOR_OPADDR_ADDR; |
f98bb7d3 RK |
4257 | } |
4258 | ||
eceef4c9 BS |
4259 | if ((rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS |
4260 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4261 | && rld[i].secondary_out_reload != -1) | |
f98bb7d3 | 4262 | { |
eceef4c9 | 4263 | int secondary_out_reload = rld[i].secondary_out_reload; |
f98bb7d3 | 4264 | |
4381f7c2 | 4265 | rld[secondary_out_reload].when_needed = RELOAD_FOR_OPADDR_ADDR; |
f98bb7d3 | 4266 | |
0f41302f | 4267 | /* If there's a tertiary reload we have to change it also. */ |
f98bb7d3 | 4268 | if (secondary_out_reload |
eceef4c9 BS |
4269 | && rld[secondary_out_reload].secondary_out_reload != -1) |
4270 | rld[rld[secondary_out_reload].secondary_out_reload].when_needed | |
38323cc3 | 4271 | = RELOAD_FOR_OPADDR_ADDR; |
f98bb7d3 | 4272 | } |
e5e809f4 | 4273 | |
eceef4c9 BS |
4274 | if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS |
4275 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4276 | rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR; | |
cb2afeb3 | 4277 | else |
eceef4c9 | 4278 | rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS; |
f98bb7d3 | 4279 | } |
a8c9daeb | 4280 | |
eceef4c9 BS |
4281 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS |
4282 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
4283 | && operand_reloadnum[rld[i].opnum] >= 0 | |
4284 | && (rld[operand_reloadnum[rld[i].opnum]].when_needed | |
a8c9daeb | 4285 | == RELOAD_OTHER)) |
eceef4c9 | 4286 | rld[i].when_needed = RELOAD_FOR_OTHER_ADDRESS; |
a8c9daeb | 4287 | |
eceef4c9 BS |
4288 | if (goal_alternative_matches[rld[i].opnum] >= 0) |
4289 | rld[i].opnum = goal_alternative_matches[rld[i].opnum]; | |
a8c9daeb RK |
4290 | } |
4291 | ||
a94ce333 JW |
4292 | /* Scan all the reloads, and check for RELOAD_FOR_OPERAND_ADDRESS reloads. |
4293 | If we have more than one, then convert all RELOAD_FOR_OPADDR_ADDR | |
4294 | reloads to RELOAD_FOR_OPERAND_ADDRESS reloads. | |
4295 | ||
4296 | choose_reload_regs assumes that RELOAD_FOR_OPADDR_ADDR reloads never | |
4297 | conflict with RELOAD_FOR_OPERAND_ADDRESS reloads. This is true for a | |
4298 | single pair of RELOAD_FOR_OPADDR_ADDR/RELOAD_FOR_OPERAND_ADDRESS reloads. | |
4299 | However, if there is more than one RELOAD_FOR_OPERAND_ADDRESS reload, | |
4300 | then a RELOAD_FOR_OPADDR_ADDR reload conflicts with all | |
4301 | RELOAD_FOR_OPERAND_ADDRESS reloads other than the one that uses it. | |
4302 | This is complicated by the fact that a single operand can have more | |
4303 | than one RELOAD_FOR_OPERAND_ADDRESS reload. It is very difficult to fix | |
4304 | choose_reload_regs without affecting code quality, and cases that | |
4305 | actually fail are extremely rare, so it turns out to be better to fix | |
4306 | the problem here by not generating cases that choose_reload_regs will | |
4307 | fail for. */ | |
d3adbeea | 4308 | /* There is a similar problem with RELOAD_FOR_INPUT_ADDRESS / |
826e3854 R |
4309 | RELOAD_FOR_OUTPUT_ADDRESS when there is more than one of a kind for |
4310 | a single operand. | |
4311 | We can reduce the register pressure by exploiting that a | |
4312 | RELOAD_FOR_X_ADDR_ADDR that precedes all RELOAD_FOR_X_ADDRESS reloads | |
c10638c9 R |
4313 | does not conflict with any of them, if it is only used for the first of |
4314 | the RELOAD_FOR_X_ADDRESS reloads. */ | |
a94ce333 | 4315 | { |
826e3854 R |
4316 | int first_op_addr_num = -2; |
4317 | int first_inpaddr_num[MAX_RECOG_OPERANDS]; | |
4318 | int first_outpaddr_num[MAX_RECOG_OPERANDS]; | |
4381f7c2 | 4319 | int need_change = 0; |
826e3854 R |
4320 | /* We use last_op_addr_reload and the contents of the above arrays |
4321 | first as flags - -2 means no instance encountered, -1 means exactly | |
4322 | one instance encountered. | |
4323 | If more than one instance has been encountered, we store the reload | |
4324 | number of the first reload of the kind in question; reload numbers | |
4325 | are known to be non-negative. */ | |
4326 | for (i = 0; i < noperands; i++) | |
4327 | first_inpaddr_num[i] = first_outpaddr_num[i] = -2; | |
4328 | for (i = n_reloads - 1; i >= 0; i--) | |
4329 | { | |
eceef4c9 | 4330 | switch (rld[i].when_needed) |
826e3854 R |
4331 | { |
4332 | case RELOAD_FOR_OPERAND_ADDRESS: | |
c10638c9 | 4333 | if (++first_op_addr_num >= 0) |
826e3854 | 4334 | { |
c10638c9 | 4335 | first_op_addr_num = i; |
826e3854 R |
4336 | need_change = 1; |
4337 | } | |
4338 | break; | |
4339 | case RELOAD_FOR_INPUT_ADDRESS: | |
eceef4c9 | 4340 | if (++first_inpaddr_num[rld[i].opnum] >= 0) |
826e3854 | 4341 | { |
eceef4c9 | 4342 | first_inpaddr_num[rld[i].opnum] = i; |
826e3854 R |
4343 | need_change = 1; |
4344 | } | |
4345 | break; | |
4346 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
eceef4c9 | 4347 | if (++first_outpaddr_num[rld[i].opnum] >= 0) |
826e3854 | 4348 | { |
eceef4c9 | 4349 | first_outpaddr_num[rld[i].opnum] = i; |
826e3854 R |
4350 | need_change = 1; |
4351 | } | |
4352 | break; | |
4353 | default: | |
4354 | break; | |
4355 | } | |
4356 | } | |
a94ce333 | 4357 | |
826e3854 R |
4358 | if (need_change) |
4359 | { | |
4360 | for (i = 0; i < n_reloads; i++) | |
4361 | { | |
c8d8ed65 RK |
4362 | int first_num; |
4363 | enum reload_type type; | |
826e3854 | 4364 | |
eceef4c9 | 4365 | switch (rld[i].when_needed) |
826e3854 R |
4366 | { |
4367 | case RELOAD_FOR_OPADDR_ADDR: | |
4368 | first_num = first_op_addr_num; | |
4369 | type = RELOAD_FOR_OPERAND_ADDRESS; | |
4370 | break; | |
4371 | case RELOAD_FOR_INPADDR_ADDRESS: | |
eceef4c9 | 4372 | first_num = first_inpaddr_num[rld[i].opnum]; |
826e3854 R |
4373 | type = RELOAD_FOR_INPUT_ADDRESS; |
4374 | break; | |
4375 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
eceef4c9 | 4376 | first_num = first_outpaddr_num[rld[i].opnum]; |
826e3854 R |
4377 | type = RELOAD_FOR_OUTPUT_ADDRESS; |
4378 | break; | |
4379 | default: | |
4380 | continue; | |
4381 | } | |
c10638c9 R |
4382 | if (first_num < 0) |
4383 | continue; | |
4384 | else if (i > first_num) | |
eceef4c9 | 4385 | rld[i].when_needed = type; |
c10638c9 R |
4386 | else |
4387 | { | |
4388 | /* Check if the only TYPE reload that uses reload I is | |
4389 | reload FIRST_NUM. */ | |
4390 | for (j = n_reloads - 1; j > first_num; j--) | |
4391 | { | |
eceef4c9 BS |
4392 | if (rld[j].when_needed == type |
4393 | && (rld[i].secondary_p | |
4394 | ? rld[j].secondary_in_reload == i | |
4395 | : reg_mentioned_p (rld[i].in, rld[j].in))) | |
c10638c9 | 4396 | { |
eceef4c9 | 4397 | rld[i].when_needed = type; |
c10638c9 R |
4398 | break; |
4399 | } | |
4400 | } | |
4401 | } | |
826e3854 R |
4402 | } |
4403 | } | |
a94ce333 JW |
4404 | } |
4405 | ||
a8c9daeb RK |
4406 | /* See if we have any reloads that are now allowed to be merged |
4407 | because we've changed when the reload is needed to | |
4408 | RELOAD_FOR_OPERAND_ADDRESS or RELOAD_FOR_OTHER_ADDRESS. Only | |
4409 | check for the most common cases. */ | |
4410 | ||
4411 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 BS |
4412 | if (rld[i].in != 0 && rld[i].out == 0 |
4413 | && (rld[i].when_needed == RELOAD_FOR_OPERAND_ADDRESS | |
4414 | || rld[i].when_needed == RELOAD_FOR_OPADDR_ADDR | |
4415 | || rld[i].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
a8c9daeb | 4416 | for (j = 0; j < n_reloads; j++) |
eceef4c9 BS |
4417 | if (i != j && rld[j].in != 0 && rld[j].out == 0 |
4418 | && rld[j].when_needed == rld[i].when_needed | |
4419 | && MATCHES (rld[i].in, rld[j].in) | |
4420 | && rld[i].class == rld[j].class | |
4421 | && !rld[i].nocombine && !rld[j].nocombine | |
4422 | && rld[i].reg_rtx == rld[j].reg_rtx) | |
a8c9daeb | 4423 | { |
eceef4c9 | 4424 | rld[i].opnum = MIN (rld[i].opnum, rld[j].opnum); |
a8c9daeb | 4425 | transfer_replacements (i, j); |
eceef4c9 | 4426 | rld[j].in = 0; |
a8c9daeb RK |
4427 | } |
4428 | ||
14a774a9 RK |
4429 | #ifdef HAVE_cc0 |
4430 | /* If we made any reloads for addresses, see if they violate a | |
4431 | "no input reloads" requirement for this insn. But loads that we | |
4432 | do after the insn (such as for output addresses) are fine. */ | |
4433 | if (no_input_reloads) | |
4434 | for (i = 0; i < n_reloads; i++) | |
41374e13 NS |
4435 | gcc_assert (rld[i].in == 0 |
4436 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS | |
4437 | || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS); | |
14a774a9 RK |
4438 | #endif |
4439 | ||
67e61fe7 BS |
4440 | /* Compute reload_mode and reload_nregs. */ |
4441 | for (i = 0; i < n_reloads; i++) | |
4442 | { | |
4443 | rld[i].mode | |
4444 | = (rld[i].inmode == VOIDmode | |
4445 | || (GET_MODE_SIZE (rld[i].outmode) | |
4446 | > GET_MODE_SIZE (rld[i].inmode))) | |
4447 | ? rld[i].outmode : rld[i].inmode; | |
4448 | ||
4449 | rld[i].nregs = CLASS_MAX_NREGS (rld[i].class, rld[i].mode); | |
4450 | } | |
4451 | ||
02a10130 RH |
4452 | /* Special case a simple move with an input reload and a |
4453 | destination of a hard reg, if the hard reg is ok, use it. */ | |
4454 | for (i = 0; i < n_reloads; i++) | |
4455 | if (rld[i].when_needed == RELOAD_FOR_INPUT | |
4456 | && GET_CODE (PATTERN (insn)) == SET | |
f8cfc6aa | 4457 | && REG_P (SET_DEST (PATTERN (insn))) |
8c74fb06 RS |
4458 | && SET_SRC (PATTERN (insn)) == rld[i].in |
4459 | && !elimination_target_reg_p (SET_DEST (PATTERN (insn)))) | |
02a10130 | 4460 | { |
0c20a65f | 4461 | rtx dest = SET_DEST (PATTERN (insn)); |
02a10130 RH |
4462 | unsigned int regno = REGNO (dest); |
4463 | ||
0c20a65f AJ |
4464 | if (regno < FIRST_PSEUDO_REGISTER |
4465 | && TEST_HARD_REG_BIT (reg_class_contents[rld[i].class], regno) | |
4466 | && HARD_REGNO_MODE_OK (regno, rld[i].mode)) | |
57458e8a | 4467 | { |
66fd46b6 | 4468 | int nr = hard_regno_nregs[regno][rld[i].mode]; |
57458e8a DD |
4469 | int ok = 1, nri; |
4470 | ||
4471 | for (nri = 1; nri < nr; nri ++) | |
4472 | if (! TEST_HARD_REG_BIT (reg_class_contents[rld[i].class], regno + nri)) | |
4473 | ok = 0; | |
4474 | ||
4475 | if (ok) | |
4476 | rld[i].reg_rtx = dest; | |
4477 | } | |
02a10130 RH |
4478 | } |
4479 | ||
cb2afeb3 | 4480 | return retval; |
eab89b90 RK |
4481 | } |
4482 | ||
4483 | /* Return 1 if alternative number ALTNUM in constraint-string CONSTRAINT | |
4484 | accepts a memory operand with constant address. */ | |
4485 | ||
4486 | static int | |
0c20a65f | 4487 | alternative_allows_memconst (const char *constraint, int altnum) |
eab89b90 | 4488 | { |
b3694847 | 4489 | int c; |
eab89b90 RK |
4490 | /* Skip alternatives before the one requested. */ |
4491 | while (altnum > 0) | |
4492 | { | |
4493 | while (*constraint++ != ','); | |
4494 | altnum--; | |
4495 | } | |
4496 | /* Scan the requested alternative for 'm' or 'o'. | |
4497 | If one of them is present, this alternative accepts memory constants. */ | |
97488870 R |
4498 | for (; (c = *constraint) && c != ',' && c != '#'; |
4499 | constraint += CONSTRAINT_LEN (c, constraint)) | |
4500 | if (c == 'm' || c == 'o' || EXTRA_MEMORY_CONSTRAINT (c, constraint)) | |
eab89b90 RK |
4501 | return 1; |
4502 | return 0; | |
4503 | } | |
4504 | \f | |
4505 | /* Scan X for memory references and scan the addresses for reloading. | |
4506 | Also checks for references to "constant" regs that we want to eliminate | |
4507 | and replaces them with the values they stand for. | |
6dc42e49 | 4508 | We may alter X destructively if it contains a reference to such. |
eab89b90 RK |
4509 | If X is just a constant reg, we return the equivalent value |
4510 | instead of X. | |
4511 | ||
4512 | IND_LEVELS says how many levels of indirect addressing this machine | |
4513 | supports. | |
4514 | ||
a8c9daeb RK |
4515 | OPNUM and TYPE identify the purpose of the reload. |
4516 | ||
eab89b90 | 4517 | IS_SET_DEST is true if X is the destination of a SET, which is not |
cb2afeb3 R |
4518 | appropriate to be replaced by a constant. |
4519 | ||
4520 | INSN, if nonzero, is the insn in which we do the reload. It is used | |
4521 | to determine if we may generate output reloads, and where to put USEs | |
9246aadb AH |
4522 | for pseudos that we have to replace with stack slots. |
4523 | ||
4524 | ADDRESS_RELOADED. If nonzero, is a pointer to where we put the | |
4525 | result of find_reloads_address. */ | |
eab89b90 RK |
4526 | |
4527 | static rtx | |
0c20a65f AJ |
4528 | find_reloads_toplev (rtx x, int opnum, enum reload_type type, |
4529 | int ind_levels, int is_set_dest, rtx insn, | |
4530 | int *address_reloaded) | |
eab89b90 | 4531 | { |
b3694847 | 4532 | RTX_CODE code = GET_CODE (x); |
eab89b90 | 4533 | |
b3694847 SS |
4534 | const char *fmt = GET_RTX_FORMAT (code); |
4535 | int i; | |
9f4749b1 | 4536 | int copied; |
eab89b90 RK |
4537 | |
4538 | if (code == REG) | |
4539 | { | |
4540 | /* This code is duplicated for speed in find_reloads. */ | |
b3694847 | 4541 | int regno = REGNO (x); |
eab89b90 RK |
4542 | if (reg_equiv_constant[regno] != 0 && !is_set_dest) |
4543 | x = reg_equiv_constant[regno]; | |
4544 | #if 0 | |
05d10675 BS |
4545 | /* This creates (subreg (mem...)) which would cause an unnecessary |
4546 | reload of the mem. */ | |
eab89b90 RK |
4547 | else if (reg_equiv_mem[regno] != 0) |
4548 | x = reg_equiv_mem[regno]; | |
4549 | #endif | |
cb2afeb3 R |
4550 | else if (reg_equiv_memory_loc[regno] |
4551 | && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)) | |
eab89b90 | 4552 | { |
cb2afeb3 R |
4553 | rtx mem = make_memloc (x, regno); |
4554 | if (reg_equiv_address[regno] | |
4555 | || ! rtx_equal_p (mem, reg_equiv_mem[regno])) | |
4556 | { | |
4557 | /* If this is not a toplevel operand, find_reloads doesn't see | |
4558 | this substitution. We have to emit a USE of the pseudo so | |
4559 | that delete_output_reload can see it. */ | |
1ccbefce | 4560 | if (replace_reloads && recog_data.operand[opnum] != x) |
3d17d93d AO |
4561 | /* We mark the USE with QImode so that we recognize it |
4562 | as one that can be safely deleted at the end of | |
4563 | reload. */ | |
4564 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, x), insn), | |
4565 | QImode); | |
cb2afeb3 | 4566 | x = mem; |
9246aadb AH |
4567 | i = find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), &XEXP (x, 0), |
4568 | opnum, type, ind_levels, insn); | |
0f4b25a3 | 4569 | if (!rtx_equal_p (x, mem)) |
3f1e3e70 | 4570 | push_reg_equiv_alt_mem (regno, x); |
9246aadb AH |
4571 | if (address_reloaded) |
4572 | *address_reloaded = i; | |
cb2afeb3 | 4573 | } |
eab89b90 RK |
4574 | } |
4575 | return x; | |
4576 | } | |
4577 | if (code == MEM) | |
4578 | { | |
4579 | rtx tem = x; | |
9246aadb AH |
4580 | |
4581 | i = find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0), | |
4582 | opnum, type, ind_levels, insn); | |
4583 | if (address_reloaded) | |
4584 | *address_reloaded = i; | |
4585 | ||
eab89b90 RK |
4586 | return tem; |
4587 | } | |
4588 | ||
f8cfc6aa | 4589 | if (code == SUBREG && REG_P (SUBREG_REG (x))) |
eab89b90 | 4590 | { |
0e61db61 NS |
4591 | /* Check for SUBREG containing a REG that's equivalent to a |
4592 | constant. If the constant has a known value, truncate it | |
4593 | right now. Similarly if we are extracting a single-word of a | |
4594 | multi-word constant. If the constant is symbolic, allow it | |
4595 | to be substituted normally. push_reload will strip the | |
4596 | subreg later. The constant must not be VOIDmode, because we | |
4597 | will lose the mode of the register (this should never happen | |
4598 | because one of the cases above should handle it). */ | |
eab89b90 | 4599 | |
b3694847 | 4600 | int regno = REGNO (SUBREG_REG (x)); |
eab89b90 RK |
4601 | rtx tem; |
4602 | ||
4603 | if (subreg_lowpart_p (x) | |
857e5753 RS |
4604 | && regno >= FIRST_PSEUDO_REGISTER |
4605 | && reg_renumber[regno] < 0 | |
eab89b90 RK |
4606 | && reg_equiv_constant[regno] != 0 |
4607 | && (tem = gen_lowpart_common (GET_MODE (x), | |
4119019b | 4608 | reg_equiv_constant[regno])) != 0) |
eab89b90 RK |
4609 | return tem; |
4610 | ||
857e5753 RS |
4611 | if (regno >= FIRST_PSEUDO_REGISTER |
4612 | && reg_renumber[regno] < 0 | |
451f86fd | 4613 | && reg_equiv_constant[regno] != 0) |
0365438d | 4614 | { |
451f86fd R |
4615 | tem = |
4616 | simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno], | |
4617 | GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); | |
41374e13 | 4618 | gcc_assert (tem); |
4119019b | 4619 | return tem; |
0365438d | 4620 | } |
eab89b90 | 4621 | |
eab89b90 RK |
4622 | /* If the subreg contains a reg that will be converted to a mem, |
4623 | convert the subreg to a narrower memref now. | |
4624 | Otherwise, we would get (subreg (mem ...) ...), | |
4625 | which would force reload of the mem. | |
4626 | ||
4627 | We also need to do this if there is an equivalent MEM that is | |
4628 | not offsettable. In that case, alter_subreg would produce an | |
4629 | invalid address on big-endian machines. | |
4630 | ||
46da6b3a | 4631 | For machines that extend byte loads, we must not reload using |
eab89b90 RK |
4632 | a wider mode if we have a paradoxical SUBREG. find_reloads will |
4633 | force a reload in that case. So we should not do anything here. */ | |
4634 | ||
857e5753 | 4635 | if (regno >= FIRST_PSEUDO_REGISTER |
fd72420f | 4636 | #ifdef LOAD_EXTEND_OP |
eab89b90 RK |
4637 | && (GET_MODE_SIZE (GET_MODE (x)) |
4638 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
4639 | #endif | |
4640 | && (reg_equiv_address[regno] != 0 | |
4641 | || (reg_equiv_mem[regno] != 0 | |
05d10675 | 4642 | && (! strict_memory_address_p (GET_MODE (x), |
f2fbfe92 | 4643 | XEXP (reg_equiv_mem[regno], 0)) |
cb2afeb3 R |
4644 | || ! offsettable_memref_p (reg_equiv_mem[regno]) |
4645 | || num_not_at_initial_offset)))) | |
22505ad8 R |
4646 | x = find_reloads_subreg_address (x, 1, opnum, type, ind_levels, |
4647 | insn); | |
eab89b90 RK |
4648 | } |
4649 | ||
9f4749b1 | 4650 | for (copied = 0, i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
eab89b90 RK |
4651 | { |
4652 | if (fmt[i] == 'e') | |
9f4749b1 R |
4653 | { |
4654 | rtx new_part = find_reloads_toplev (XEXP (x, i), opnum, type, | |
9246aadb AH |
4655 | ind_levels, is_set_dest, insn, |
4656 | address_reloaded); | |
9f4749b1 R |
4657 | /* If we have replaced a reg with it's equivalent memory loc - |
4658 | that can still be handled here e.g. if it's in a paradoxical | |
4659 | subreg - we must make the change in a copy, rather than using | |
4660 | a destructive change. This way, find_reloads can still elect | |
4661 | not to do the change. */ | |
4662 | if (new_part != XEXP (x, i) && ! CONSTANT_P (new_part) && ! copied) | |
4663 | { | |
ce9d4c6d | 4664 | x = shallow_copy_rtx (x); |
9f4749b1 R |
4665 | copied = 1; |
4666 | } | |
4667 | XEXP (x, i) = new_part; | |
4668 | } | |
eab89b90 RK |
4669 | } |
4670 | return x; | |
4671 | } | |
4672 | ||
dbf85761 RS |
4673 | /* Return a mem ref for the memory equivalent of reg REGNO. |
4674 | This mem ref is not shared with anything. */ | |
4675 | ||
eab89b90 | 4676 | static rtx |
0c20a65f | 4677 | make_memloc (rtx ad, int regno) |
eab89b90 | 4678 | { |
4ffeab02 JW |
4679 | /* We must rerun eliminate_regs, in case the elimination |
4680 | offsets have changed. */ | |
cb2afeb3 R |
4681 | rtx tem |
4682 | = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], 0, NULL_RTX), 0); | |
eab89b90 RK |
4683 | |
4684 | /* If TEM might contain a pseudo, we must copy it to avoid | |
4685 | modifying it when we do the substitution for the reload. */ | |
e38fe8e0 | 4686 | if (rtx_varies_p (tem, 0)) |
eab89b90 RK |
4687 | tem = copy_rtx (tem); |
4688 | ||
f1ec5147 | 4689 | tem = replace_equiv_address_nv (reg_equiv_memory_loc[regno], tem); |
cf728d61 HPN |
4690 | tem = adjust_address_nv (tem, GET_MODE (ad), 0); |
4691 | ||
4692 | /* Copy the result if it's still the same as the equivalence, to avoid | |
4693 | modifying it when we do the substitution for the reload. */ | |
4694 | if (tem == reg_equiv_memory_loc[regno]) | |
4695 | tem = copy_rtx (tem); | |
4696 | return tem; | |
eab89b90 RK |
4697 | } |
4698 | ||
acf9fa5f | 4699 | /* Returns true if AD could be turned into a valid memory reference |
0c20a65f | 4700 | to mode MODE by reloading the part pointed to by PART into a |
acf9fa5f UW |
4701 | register. */ |
4702 | ||
4703 | static int | |
0c20a65f | 4704 | maybe_memory_address_p (enum machine_mode mode, rtx ad, rtx *part) |
acf9fa5f UW |
4705 | { |
4706 | int retv; | |
4707 | rtx tem = *part; | |
4708 | rtx reg = gen_rtx_REG (GET_MODE (tem), max_reg_num ()); | |
4709 | ||
4710 | *part = reg; | |
4711 | retv = memory_address_p (mode, ad); | |
4712 | *part = tem; | |
4713 | ||
4714 | return retv; | |
4715 | } | |
4716 | ||
eab89b90 RK |
4717 | /* Record all reloads needed for handling memory address AD |
4718 | which appears in *LOC in a memory reference to mode MODE | |
4719 | which itself is found in location *MEMREFLOC. | |
4720 | Note that we take shortcuts assuming that no multi-reg machine mode | |
4721 | occurs as part of an address. | |
4722 | ||
a8c9daeb | 4723 | OPNUM and TYPE specify the purpose of this reload. |
eab89b90 RK |
4724 | |
4725 | IND_LEVELS says how many levels of indirect addressing this machine | |
4726 | supports. | |
4727 | ||
55c22565 | 4728 | INSN, if nonzero, is the insn in which we do the reload. It is used |
cb2afeb3 R |
4729 | to determine if we may generate output reloads, and where to put USEs |
4730 | for pseudos that we have to replace with stack slots. | |
55c22565 | 4731 | |
0b540f12 UW |
4732 | Value is one if this address is reloaded or replaced as a whole; it is |
4733 | zero if the top level of this address was not reloaded or replaced, and | |
4734 | it is -1 if it may or may not have been reloaded or replaced. | |
eab89b90 RK |
4735 | |
4736 | Note that there is no verification that the address will be valid after | |
4737 | this routine does its work. Instead, we rely on the fact that the address | |
4738 | was valid when reload started. So we need only undo things that reload | |
4739 | could have broken. These are wrong register types, pseudos not allocated | |
4740 | to a hard register, and frame pointer elimination. */ | |
4741 | ||
4742 | static int | |
0c20a65f AJ |
4743 | find_reloads_address (enum machine_mode mode, rtx *memrefloc, rtx ad, |
4744 | rtx *loc, int opnum, enum reload_type type, | |
4745 | int ind_levels, rtx insn) | |
eab89b90 | 4746 | { |
b3694847 | 4747 | int regno; |
ab87f8c8 | 4748 | int removed_and = 0; |
14d3dc34 | 4749 | int op_index; |
eab89b90 RK |
4750 | rtx tem; |
4751 | ||
4752 | /* If the address is a register, see if it is a legitimate address and | |
4753 | reload if not. We first handle the cases where we need not reload | |
4754 | or where we must reload in a non-standard way. */ | |
4755 | ||
f8cfc6aa | 4756 | if (REG_P (ad)) |
eab89b90 RK |
4757 | { |
4758 | regno = REGNO (ad); | |
4759 | ||
4971426b | 4760 | /* If the register is equivalent to an invariant expression, substitute |
82efa2e5 | 4761 | the invariant, and eliminate any eliminable register references. */ |
4971426b AL |
4762 | tem = reg_equiv_constant[regno]; |
4763 | if (tem != 0 | |
4764 | && (tem = eliminate_regs (tem, mode, insn)) | |
4765 | && strict_memory_address_p (mode, tem)) | |
eab89b90 | 4766 | { |
4971426b | 4767 | *loc = ad = tem; |
ab87f8c8 | 4768 | return 0; |
eab89b90 RK |
4769 | } |
4770 | ||
cb2afeb3 R |
4771 | tem = reg_equiv_memory_loc[regno]; |
4772 | if (tem != 0) | |
eab89b90 | 4773 | { |
cb2afeb3 R |
4774 | if (reg_equiv_address[regno] != 0 || num_not_at_initial_offset) |
4775 | { | |
4776 | tem = make_memloc (ad, regno); | |
4777 | if (! strict_memory_address_p (GET_MODE (tem), XEXP (tem, 0))) | |
4778 | { | |
3f1e3e70 AO |
4779 | rtx orig = tem; |
4780 | ||
57292ec3 AL |
4781 | find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), |
4782 | &XEXP (tem, 0), opnum, | |
4783 | ADDR_TYPE (type), ind_levels, insn); | |
0f4b25a3 | 4784 | if (!rtx_equal_p (tem, orig)) |
3f1e3e70 | 4785 | push_reg_equiv_alt_mem (regno, tem); |
cb2afeb3 R |
4786 | } |
4787 | /* We can avoid a reload if the register's equivalent memory | |
4788 | expression is valid as an indirect memory address. | |
4789 | But not all addresses are valid in a mem used as an indirect | |
4790 | address: only reg or reg+constant. */ | |
4791 | ||
4792 | if (ind_levels > 0 | |
4793 | && strict_memory_address_p (mode, tem) | |
f8cfc6aa | 4794 | && (REG_P (XEXP (tem, 0)) |
cb2afeb3 | 4795 | || (GET_CODE (XEXP (tem, 0)) == PLUS |
f8cfc6aa | 4796 | && REG_P (XEXP (XEXP (tem, 0), 0)) |
cb2afeb3 R |
4797 | && CONSTANT_P (XEXP (XEXP (tem, 0), 1))))) |
4798 | { | |
4799 | /* TEM is not the same as what we'll be replacing the | |
4800 | pseudo with after reload, put a USE in front of INSN | |
4801 | in the final reload pass. */ | |
4802 | if (replace_reloads | |
4803 | && num_not_at_initial_offset | |
4804 | && ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
4805 | { | |
4806 | *loc = tem; | |
3d17d93d AO |
4807 | /* We mark the USE with QImode so that we |
4808 | recognize it as one that can be safely | |
4809 | deleted at the end of reload. */ | |
4810 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, ad), | |
4811 | insn), QImode); | |
4812 | ||
cb2afeb3 R |
4813 | /* This doesn't really count as replacing the address |
4814 | as a whole, since it is still a memory access. */ | |
4815 | } | |
4816 | return 0; | |
4817 | } | |
4818 | ad = tem; | |
4819 | } | |
eab89b90 RK |
4820 | } |
4821 | ||
eab89b90 RK |
4822 | /* The only remaining case where we can avoid a reload is if this is a |
4823 | hard register that is valid as a base register and which is not the | |
4824 | subject of a CLOBBER in this insn. */ | |
4825 | ||
858c3c8c | 4826 | else if (regno < FIRST_PSEUDO_REGISTER |
c4963a0a | 4827 | && regno_ok_for_base_p (regno, mode, MEM, SCRATCH) |
9532e31f | 4828 | && ! regno_clobbered_p (regno, this_insn, mode, 0)) |
eab89b90 RK |
4829 | return 0; |
4830 | ||
4831 | /* If we do not have one of the cases above, we must do the reload. */ | |
c4963a0a | 4832 | push_reload (ad, NULL_RTX, loc, (rtx*) 0, base_reg_class (mode, MEM, SCRATCH), |
a8c9daeb | 4833 | GET_MODE (ad), VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
4834 | return 1; |
4835 | } | |
4836 | ||
4837 | if (strict_memory_address_p (mode, ad)) | |
4838 | { | |
4839 | /* The address appears valid, so reloads are not needed. | |
4840 | But the address may contain an eliminable register. | |
4841 | This can happen because a machine with indirect addressing | |
4842 | may consider a pseudo register by itself a valid address even when | |
4843 | it has failed to get a hard reg. | |
4844 | So do a tree-walk to find and eliminate all such regs. */ | |
4845 | ||
4846 | /* But first quickly dispose of a common case. */ | |
4847 | if (GET_CODE (ad) == PLUS | |
4848 | && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
f8cfc6aa | 4849 | && REG_P (XEXP (ad, 0)) |
eab89b90 RK |
4850 | && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0) |
4851 | return 0; | |
4852 | ||
4853 | subst_reg_equivs_changed = 0; | |
cb2afeb3 | 4854 | *loc = subst_reg_equivs (ad, insn); |
eab89b90 RK |
4855 | |
4856 | if (! subst_reg_equivs_changed) | |
4857 | return 0; | |
4858 | ||
4859 | /* Check result for validity after substitution. */ | |
4860 | if (strict_memory_address_p (mode, ad)) | |
4861 | return 0; | |
4862 | } | |
4863 | ||
a9a2595b JR |
4864 | #ifdef LEGITIMIZE_RELOAD_ADDRESS |
4865 | do | |
4866 | { | |
4867 | if (memrefloc) | |
4868 | { | |
4869 | LEGITIMIZE_RELOAD_ADDRESS (ad, GET_MODE (*memrefloc), opnum, type, | |
4870 | ind_levels, win); | |
4871 | } | |
4872 | break; | |
4873 | win: | |
4874 | *memrefloc = copy_rtx (*memrefloc); | |
4875 | XEXP (*memrefloc, 0) = ad; | |
4876 | move_replacements (&ad, &XEXP (*memrefloc, 0)); | |
0b540f12 | 4877 | return -1; |
a9a2595b JR |
4878 | } |
4879 | while (0); | |
4880 | #endif | |
4881 | ||
ab87f8c8 JL |
4882 | /* The address is not valid. We have to figure out why. First see if |
4883 | we have an outer AND and remove it if so. Then analyze what's inside. */ | |
4884 | ||
4885 | if (GET_CODE (ad) == AND) | |
4886 | { | |
4887 | removed_and = 1; | |
4888 | loc = &XEXP (ad, 0); | |
4889 | ad = *loc; | |
4890 | } | |
4891 | ||
4892 | /* One possibility for why the address is invalid is that it is itself | |
4893 | a MEM. This can happen when the frame pointer is being eliminated, a | |
4894 | pseudo is not allocated to a hard register, and the offset between the | |
4895 | frame and stack pointers is not its initial value. In that case the | |
4896 | pseudo will have been replaced by a MEM referring to the | |
4897 | stack pointer. */ | |
3c0cb5de | 4898 | if (MEM_P (ad)) |
eab89b90 RK |
4899 | { |
4900 | /* First ensure that the address in this MEM is valid. Then, unless | |
4901 | indirect addresses are valid, reload the MEM into a register. */ | |
4902 | tem = ad; | |
4903 | find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0), | |
47c8cf91 | 4904 | opnum, ADDR_TYPE (type), |
55c22565 | 4905 | ind_levels == 0 ? 0 : ind_levels - 1, insn); |
d2555454 RS |
4906 | |
4907 | /* If tem was changed, then we must create a new memory reference to | |
4908 | hold it and store it back into memrefloc. */ | |
4909 | if (tem != ad && memrefloc) | |
ca3e4a2f | 4910 | { |
ca3e4a2f | 4911 | *memrefloc = copy_rtx (*memrefloc); |
3c80f7ed | 4912 | copy_replacements (tem, XEXP (*memrefloc, 0)); |
ca3e4a2f | 4913 | loc = &XEXP (*memrefloc, 0); |
ab87f8c8 JL |
4914 | if (removed_and) |
4915 | loc = &XEXP (*loc, 0); | |
ca3e4a2f | 4916 | } |
d2555454 | 4917 | |
eab89b90 RK |
4918 | /* Check similar cases as for indirect addresses as above except |
4919 | that we can allow pseudos and a MEM since they should have been | |
4920 | taken care of above. */ | |
4921 | ||
4922 | if (ind_levels == 0 | |
4923 | || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok) | |
3c0cb5de | 4924 | || MEM_P (XEXP (tem, 0)) |
f8cfc6aa | 4925 | || ! (REG_P (XEXP (tem, 0)) |
eab89b90 | 4926 | || (GET_CODE (XEXP (tem, 0)) == PLUS |
f8cfc6aa | 4927 | && REG_P (XEXP (XEXP (tem, 0), 0)) |
eab89b90 RK |
4928 | && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT))) |
4929 | { | |
4930 | /* Must use TEM here, not AD, since it is the one that will | |
4931 | have any subexpressions reloaded, if needed. */ | |
f4f4d0f8 | 4932 | push_reload (tem, NULL_RTX, loc, (rtx*) 0, |
c4963a0a | 4933 | base_reg_class (mode, MEM, SCRATCH), GET_MODE (tem), |
1ba61f4e | 4934 | VOIDmode, 0, |
a8c9daeb | 4935 | 0, opnum, type); |
ab87f8c8 | 4936 | return ! removed_and; |
eab89b90 RK |
4937 | } |
4938 | else | |
4939 | return 0; | |
4940 | } | |
4941 | ||
1b4d2764 RK |
4942 | /* If we have address of a stack slot but it's not valid because the |
4943 | displacement is too large, compute the sum in a register. | |
4944 | Handle all base registers here, not just fp/ap/sp, because on some | |
4945 | targets (namely SH) we can also get too large displacements from | |
4946 | big-endian corrections. */ | |
eab89b90 | 4947 | else if (GET_CODE (ad) == PLUS |
f8cfc6aa | 4948 | && REG_P (XEXP (ad, 0)) |
1b4d2764 | 4949 | && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER |
c4963a0a BS |
4950 | && GET_CODE (XEXP (ad, 1)) == CONST_INT |
4951 | && regno_ok_for_base_p (REGNO (XEXP (ad, 0)), mode, PLUS, | |
4952 | CONST_INT)) | |
4953 | ||
eab89b90 RK |
4954 | { |
4955 | /* Unshare the MEM rtx so we can safely alter it. */ | |
4956 | if (memrefloc) | |
4957 | { | |
eab89b90 RK |
4958 | *memrefloc = copy_rtx (*memrefloc); |
4959 | loc = &XEXP (*memrefloc, 0); | |
ab87f8c8 JL |
4960 | if (removed_and) |
4961 | loc = &XEXP (*loc, 0); | |
eab89b90 | 4962 | } |
ab87f8c8 | 4963 | |
eab89b90 RK |
4964 | if (double_reg_address_ok) |
4965 | { | |
4966 | /* Unshare the sum as well. */ | |
4967 | *loc = ad = copy_rtx (ad); | |
ab87f8c8 | 4968 | |
eab89b90 RK |
4969 | /* Reload the displacement into an index reg. |
4970 | We assume the frame pointer or arg pointer is a base reg. */ | |
4971 | find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), | |
03acd8f8 BS |
4972 | INDEX_REG_CLASS, GET_MODE (ad), opnum, |
4973 | type, ind_levels); | |
ab87f8c8 | 4974 | return 0; |
eab89b90 RK |
4975 | } |
4976 | else | |
4977 | { | |
4978 | /* If the sum of two regs is not necessarily valid, | |
4979 | reload the sum into a base reg. | |
4980 | That will at least work. */ | |
c4963a0a BS |
4981 | find_reloads_address_part (ad, loc, |
4982 | base_reg_class (mode, MEM, SCRATCH), | |
1ba61f4e | 4983 | Pmode, opnum, type, ind_levels); |
eab89b90 | 4984 | } |
ab87f8c8 | 4985 | return ! removed_and; |
eab89b90 RK |
4986 | } |
4987 | ||
4988 | /* If we have an indexed stack slot, there are three possible reasons why | |
4989 | it might be invalid: The index might need to be reloaded, the address | |
4990 | might have been made by frame pointer elimination and hence have a | |
05d10675 | 4991 | constant out of range, or both reasons might apply. |
eab89b90 RK |
4992 | |
4993 | We can easily check for an index needing reload, but even if that is the | |
4994 | case, we might also have an invalid constant. To avoid making the | |
4995 | conservative assumption and requiring two reloads, we see if this address | |
4996 | is valid when not interpreted strictly. If it is, the only problem is | |
4997 | that the index needs a reload and find_reloads_address_1 will take care | |
4998 | of it. | |
4999 | ||
27e484bc | 5000 | Handle all base registers here, not just fp/ap/sp, because on some |
6356f892 | 5001 | targets (namely SPARC) we can also get invalid addresses from preventive |
14d3dc34 MM |
5002 | subreg big-endian corrections made by find_reloads_toplev. We |
5003 | can also get expressions involving LO_SUM (rather than PLUS) from | |
5004 | find_reloads_subreg_address. | |
27e484bc EB |
5005 | |
5006 | If we decide to do something, it must be that `double_reg_address_ok' | |
5007 | is true. We generate a reload of the base register + constant and | |
eab89b90 RK |
5008 | rework the sum so that the reload register will be added to the index. |
5009 | This is safe because we know the address isn't shared. | |
5010 | ||
27e484bc | 5011 | We check for the base register as both the first and second operand of |
14d3dc34 MM |
5012 | the innermost PLUS and/or LO_SUM. */ |
5013 | ||
5014 | for (op_index = 0; op_index < 2; ++op_index) | |
eab89b90 | 5015 | { |
c4963a0a BS |
5016 | rtx operand, addend; |
5017 | enum rtx_code inner_code; | |
5018 | ||
5019 | if (GET_CODE (ad) != PLUS) | |
5020 | continue; | |
eab89b90 | 5021 | |
c4963a0a | 5022 | inner_code = GET_CODE (XEXP (ad, 0)); |
14d3dc34 MM |
5023 | if (!(GET_CODE (ad) == PLUS |
5024 | && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
c4963a0a | 5025 | && (inner_code == PLUS || inner_code == LO_SUM))) |
14d3dc34 | 5026 | continue; |
05d10675 | 5027 | |
14d3dc34 | 5028 | operand = XEXP (XEXP (ad, 0), op_index); |
0e544c37 | 5029 | if (!REG_P (operand) || REGNO (operand) >= FIRST_PSEUDO_REGISTER) |
14d3dc34 MM |
5030 | continue; |
5031 | ||
c4963a0a BS |
5032 | addend = XEXP (XEXP (ad, 0), 1 - op_index); |
5033 | ||
5034 | if ((regno_ok_for_base_p (REGNO (operand), mode, inner_code, | |
5035 | GET_CODE (addend)) | |
14d3dc34 | 5036 | || operand == frame_pointer_rtx |
0422e940 | 5037 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM |
14d3dc34 | 5038 | || operand == hard_frame_pointer_rtx |
0422e940 UW |
5039 | #endif |
5040 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
14d3dc34 | 5041 | || operand == arg_pointer_rtx |
0422e940 | 5042 | #endif |
14d3dc34 MM |
5043 | || operand == stack_pointer_rtx) |
5044 | && ! maybe_memory_address_p (mode, ad, | |
7bb09d15 | 5045 | &XEXP (XEXP (ad, 0), 1 - op_index))) |
14d3dc34 MM |
5046 | { |
5047 | rtx offset_reg; | |
c4963a0a | 5048 | enum reg_class cls; |
14d3dc34 MM |
5049 | |
5050 | offset_reg = plus_constant (operand, INTVAL (XEXP (ad, 1))); | |
c4963a0a | 5051 | |
14d3dc34 MM |
5052 | /* Form the adjusted address. */ |
5053 | if (GET_CODE (XEXP (ad, 0)) == PLUS) | |
5054 | ad = gen_rtx_PLUS (GET_MODE (ad), | |
5055 | op_index == 0 ? offset_reg : addend, | |
5056 | op_index == 0 ? addend : offset_reg); | |
5057 | else | |
5058 | ad = gen_rtx_LO_SUM (GET_MODE (ad), | |
5059 | op_index == 0 ? offset_reg : addend, | |
5060 | op_index == 0 ? addend : offset_reg); | |
5061 | *loc = ad; | |
5062 | ||
c4963a0a | 5063 | cls = base_reg_class (mode, MEM, GET_CODE (addend)); |
14d3dc34 | 5064 | find_reloads_address_part (XEXP (ad, op_index), |
c4963a0a | 5065 | &XEXP (ad, op_index), cls, |
14d3dc34 | 5066 | GET_MODE (ad), opnum, type, ind_levels); |
c4963a0a BS |
5067 | find_reloads_address_1 (mode, |
5068 | XEXP (ad, 1 - op_index), 1, GET_CODE (ad), | |
5069 | GET_CODE (XEXP (ad, op_index)), | |
14d3dc34 MM |
5070 | &XEXP (ad, 1 - op_index), opnum, |
5071 | type, 0, insn); | |
eab89b90 | 5072 | |
14d3dc34 MM |
5073 | return 0; |
5074 | } | |
eab89b90 | 5075 | } |
05d10675 | 5076 | |
eab89b90 RK |
5077 | /* See if address becomes valid when an eliminable register |
5078 | in a sum is replaced. */ | |
5079 | ||
5080 | tem = ad; | |
5081 | if (GET_CODE (ad) == PLUS) | |
5082 | tem = subst_indexed_address (ad); | |
5083 | if (tem != ad && strict_memory_address_p (mode, tem)) | |
5084 | { | |
5085 | /* Ok, we win that way. Replace any additional eliminable | |
5086 | registers. */ | |
5087 | ||
5088 | subst_reg_equivs_changed = 0; | |
cb2afeb3 | 5089 | tem = subst_reg_equivs (tem, insn); |
eab89b90 RK |
5090 | |
5091 | /* Make sure that didn't make the address invalid again. */ | |
5092 | ||
5093 | if (! subst_reg_equivs_changed || strict_memory_address_p (mode, tem)) | |
5094 | { | |
5095 | *loc = tem; | |
5096 | return 0; | |
5097 | } | |
5098 | } | |
5099 | ||
5100 | /* If constants aren't valid addresses, reload the constant address | |
5101 | into a register. */ | |
191b18e9 | 5102 | if (CONSTANT_P (ad) && ! strict_memory_address_p (mode, ad)) |
eab89b90 | 5103 | { |
e0120d6e | 5104 | /* If AD is an address in the constant pool, the MEM rtx may be shared. |
eab89b90 RK |
5105 | Unshare it so we can safely alter it. */ |
5106 | if (memrefloc && GET_CODE (ad) == SYMBOL_REF | |
5107 | && CONSTANT_POOL_ADDRESS_P (ad)) | |
5108 | { | |
eab89b90 RK |
5109 | *memrefloc = copy_rtx (*memrefloc); |
5110 | loc = &XEXP (*memrefloc, 0); | |
ab87f8c8 JL |
5111 | if (removed_and) |
5112 | loc = &XEXP (*loc, 0); | |
eab89b90 RK |
5113 | } |
5114 | ||
c4963a0a | 5115 | find_reloads_address_part (ad, loc, base_reg_class (mode, MEM, SCRATCH), |
3dcc68a4 | 5116 | Pmode, opnum, type, ind_levels); |
ab87f8c8 | 5117 | return ! removed_and; |
eab89b90 RK |
5118 | } |
5119 | ||
c4963a0a BS |
5120 | return find_reloads_address_1 (mode, ad, 0, MEM, SCRATCH, loc, opnum, type, |
5121 | ind_levels, insn); | |
eab89b90 RK |
5122 | } |
5123 | \f | |
5124 | /* Find all pseudo regs appearing in AD | |
5125 | that are eliminable in favor of equivalent values | |
cb2afeb3 R |
5126 | and do not have hard regs; replace them by their equivalents. |
5127 | INSN, if nonzero, is the insn in which we do the reload. We put USEs in | |
5128 | front of it for pseudos that we have to replace with stack slots. */ | |
eab89b90 RK |
5129 | |
5130 | static rtx | |
0c20a65f | 5131 | subst_reg_equivs (rtx ad, rtx insn) |
eab89b90 | 5132 | { |
b3694847 SS |
5133 | RTX_CODE code = GET_CODE (ad); |
5134 | int i; | |
5135 | const char *fmt; | |
eab89b90 RK |
5136 | |
5137 | switch (code) | |
5138 | { | |
5139 | case HIGH: | |
5140 | case CONST_INT: | |
5141 | case CONST: | |
5142 | case CONST_DOUBLE: | |
69ef87e2 | 5143 | case CONST_VECTOR: |
eab89b90 RK |
5144 | case SYMBOL_REF: |
5145 | case LABEL_REF: | |
5146 | case PC: | |
5147 | case CC0: | |
5148 | return ad; | |
5149 | ||
5150 | case REG: | |
5151 | { | |
b3694847 | 5152 | int regno = REGNO (ad); |
eab89b90 RK |
5153 | |
5154 | if (reg_equiv_constant[regno] != 0) | |
5155 | { | |
5156 | subst_reg_equivs_changed = 1; | |
5157 | return reg_equiv_constant[regno]; | |
5158 | } | |
cb2afeb3 R |
5159 | if (reg_equiv_memory_loc[regno] && num_not_at_initial_offset) |
5160 | { | |
5161 | rtx mem = make_memloc (ad, regno); | |
5162 | if (! rtx_equal_p (mem, reg_equiv_mem[regno])) | |
5163 | { | |
5164 | subst_reg_equivs_changed = 1; | |
3d17d93d AO |
5165 | /* We mark the USE with QImode so that we recognize it |
5166 | as one that can be safely deleted at the end of | |
5167 | reload. */ | |
5168 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, ad), insn), | |
5169 | QImode); | |
cb2afeb3 R |
5170 | return mem; |
5171 | } | |
5172 | } | |
eab89b90 RK |
5173 | } |
5174 | return ad; | |
5175 | ||
5176 | case PLUS: | |
5177 | /* Quickly dispose of a common case. */ | |
5178 | if (XEXP (ad, 0) == frame_pointer_rtx | |
5179 | && GET_CODE (XEXP (ad, 1)) == CONST_INT) | |
5180 | return ad; | |
e9a25f70 | 5181 | break; |
05d10675 | 5182 | |
e9a25f70 JL |
5183 | default: |
5184 | break; | |
eab89b90 RK |
5185 | } |
5186 | ||
5187 | fmt = GET_RTX_FORMAT (code); | |
5188 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5189 | if (fmt[i] == 'e') | |
cb2afeb3 | 5190 | XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i), insn); |
eab89b90 RK |
5191 | return ad; |
5192 | } | |
5193 | \f | |
5194 | /* Compute the sum of X and Y, making canonicalizations assumed in an | |
5195 | address, namely: sum constant integers, surround the sum of two | |
5196 | constants with a CONST, put the constant as the second operand, and | |
5197 | group the constant on the outermost sum. | |
5198 | ||
5199 | This routine assumes both inputs are already in canonical form. */ | |
5200 | ||
5201 | rtx | |
0c20a65f | 5202 | form_sum (rtx x, rtx y) |
eab89b90 RK |
5203 | { |
5204 | rtx tem; | |
2c0623e8 RK |
5205 | enum machine_mode mode = GET_MODE (x); |
5206 | ||
5207 | if (mode == VOIDmode) | |
5208 | mode = GET_MODE (y); | |
5209 | ||
5210 | if (mode == VOIDmode) | |
5211 | mode = Pmode; | |
eab89b90 RK |
5212 | |
5213 | if (GET_CODE (x) == CONST_INT) | |
5214 | return plus_constant (y, INTVAL (x)); | |
5215 | else if (GET_CODE (y) == CONST_INT) | |
5216 | return plus_constant (x, INTVAL (y)); | |
5217 | else if (CONSTANT_P (x)) | |
5218 | tem = x, x = y, y = tem; | |
5219 | ||
5220 | if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1))) | |
5221 | return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y)); | |
5222 | ||
5223 | /* Note that if the operands of Y are specified in the opposite | |
5224 | order in the recursive calls below, infinite recursion will occur. */ | |
d9771f62 | 5225 | if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1))) |
eab89b90 RK |
5226 | return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1)); |
5227 | ||
5228 | /* If both constant, encapsulate sum. Otherwise, just form sum. A | |
5229 | constant will have been placed second. */ | |
5230 | if (CONSTANT_P (x) && CONSTANT_P (y)) | |
5231 | { | |
5232 | if (GET_CODE (x) == CONST) | |
5233 | x = XEXP (x, 0); | |
5234 | if (GET_CODE (y) == CONST) | |
5235 | y = XEXP (y, 0); | |
5236 | ||
38a448ca | 5237 | return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y)); |
eab89b90 RK |
5238 | } |
5239 | ||
38a448ca | 5240 | return gen_rtx_PLUS (mode, x, y); |
eab89b90 RK |
5241 | } |
5242 | \f | |
5243 | /* If ADDR is a sum containing a pseudo register that should be | |
5244 | replaced with a constant (from reg_equiv_constant), | |
5245 | return the result of doing so, and also apply the associative | |
5246 | law so that the result is more likely to be a valid address. | |
5247 | (But it is not guaranteed to be one.) | |
5248 | ||
5249 | Note that at most one register is replaced, even if more are | |
5250 | replaceable. Also, we try to put the result into a canonical form | |
5251 | so it is more likely to be a valid address. | |
5252 | ||
5253 | In all other cases, return ADDR. */ | |
5254 | ||
5255 | static rtx | |
0c20a65f | 5256 | subst_indexed_address (rtx addr) |
eab89b90 RK |
5257 | { |
5258 | rtx op0 = 0, op1 = 0, op2 = 0; | |
5259 | rtx tem; | |
5260 | int regno; | |
5261 | ||
5262 | if (GET_CODE (addr) == PLUS) | |
5263 | { | |
5264 | /* Try to find a register to replace. */ | |
5265 | op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0; | |
f8cfc6aa | 5266 | if (REG_P (op0) |
eab89b90 RK |
5267 | && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER |
5268 | && reg_renumber[regno] < 0 | |
5269 | && reg_equiv_constant[regno] != 0) | |
5270 | op0 = reg_equiv_constant[regno]; | |
f8cfc6aa | 5271 | else if (REG_P (op1) |
05d10675 BS |
5272 | && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER |
5273 | && reg_renumber[regno] < 0 | |
5274 | && reg_equiv_constant[regno] != 0) | |
eab89b90 RK |
5275 | op1 = reg_equiv_constant[regno]; |
5276 | else if (GET_CODE (op0) == PLUS | |
5277 | && (tem = subst_indexed_address (op0)) != op0) | |
5278 | op0 = tem; | |
5279 | else if (GET_CODE (op1) == PLUS | |
5280 | && (tem = subst_indexed_address (op1)) != op1) | |
5281 | op1 = tem; | |
5282 | else | |
5283 | return addr; | |
5284 | ||
5285 | /* Pick out up to three things to add. */ | |
5286 | if (GET_CODE (op1) == PLUS) | |
5287 | op2 = XEXP (op1, 1), op1 = XEXP (op1, 0); | |
5288 | else if (GET_CODE (op0) == PLUS) | |
5289 | op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
5290 | ||
5291 | /* Compute the sum. */ | |
5292 | if (op2 != 0) | |
5293 | op1 = form_sum (op1, op2); | |
5294 | if (op1 != 0) | |
5295 | op0 = form_sum (op0, op1); | |
5296 | ||
5297 | return op0; | |
5298 | } | |
5299 | return addr; | |
5300 | } | |
5301 | \f | |
98c17df2 GS |
5302 | /* Update the REG_INC notes for an insn. It updates all REG_INC |
5303 | notes for the instruction which refer to REGNO the to refer | |
5304 | to the reload number. | |
5305 | ||
5306 | INSN is the insn for which any REG_INC notes need updating. | |
5307 | ||
5308 | REGNO is the register number which has been reloaded. | |
5309 | ||
5310 | RELOADNUM is the reload number. */ | |
5311 | ||
5312 | static void | |
0c20a65f AJ |
5313 | update_auto_inc_notes (rtx insn ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED, |
5314 | int reloadnum ATTRIBUTE_UNUSED) | |
98c17df2 GS |
5315 | { |
5316 | #ifdef AUTO_INC_DEC | |
5317 | rtx link; | |
5318 | ||
5319 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
5320 | if (REG_NOTE_KIND (link) == REG_INC | |
fc555370 | 5321 | && (int) REGNO (XEXP (link, 0)) == regno) |
98c17df2 GS |
5322 | push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); |
5323 | #endif | |
5324 | } | |
5325 | \f | |
858c3c8c ILT |
5326 | /* Record the pseudo registers we must reload into hard registers in a |
5327 | subexpression of a would-be memory address, X referring to a value | |
5328 | in mode MODE. (This function is not called if the address we find | |
5329 | is strictly valid.) | |
5330 | ||
eab89b90 | 5331 | CONTEXT = 1 means we are considering regs as index regs, |
c4963a0a BS |
5332 | = 0 means we are considering them as base regs. |
5333 | OUTER_CODE is the code of the enclosing RTX, typically a MEM, a PLUS, | |
5334 | or an autoinc code. | |
5335 | If CONTEXT == 0 and OUTER_CODE is a PLUS or LO_SUM, then INDEX_CODE | |
5336 | is the code of the index part of the address. Otherwise, pass SCRATCH | |
5337 | for this argument. | |
a8c9daeb | 5338 | OPNUM and TYPE specify the purpose of any reloads made. |
eab89b90 RK |
5339 | |
5340 | IND_LEVELS says how many levels of indirect addressing are | |
5341 | supported at this point in the address. | |
5342 | ||
55c22565 RK |
5343 | INSN, if nonzero, is the insn in which we do the reload. It is used |
5344 | to determine if we may generate output reloads. | |
5345 | ||
eab89b90 RK |
5346 | We return nonzero if X, as a whole, is reloaded or replaced. */ |
5347 | ||
5348 | /* Note that we take shortcuts assuming that no multi-reg machine mode | |
5349 | occurs as part of an address. | |
5350 | Also, this is not fully machine-customizable; it works for machines | |
8aeea6e6 | 5351 | such as VAXen and 68000's and 32000's, but other possible machines |
ff0d9879 HPN |
5352 | could have addressing modes that this does not handle right. |
5353 | If you add push_reload calls here, you need to make sure gen_reload | |
5354 | handles those cases gracefully. */ | |
eab89b90 RK |
5355 | |
5356 | static int | |
0c20a65f | 5357 | find_reloads_address_1 (enum machine_mode mode, rtx x, int context, |
c4963a0a | 5358 | enum rtx_code outer_code, enum rtx_code index_code, |
0c20a65f AJ |
5359 | rtx *loc, int opnum, enum reload_type type, |
5360 | int ind_levels, rtx insn) | |
eab89b90 | 5361 | { |
c4963a0a BS |
5362 | #define REG_OK_FOR_CONTEXT(CONTEXT, REGNO, MODE, OUTER, INDEX) \ |
5363 | ((CONTEXT) == 0 \ | |
5364 | ? regno_ok_for_base_p (REGNO, MODE, OUTER, INDEX) \ | |
5365 | : REGNO_OK_FOR_INDEX_P (REGNO)) | |
888d2cd6 DJ |
5366 | |
5367 | enum reg_class context_reg_class; | |
b3694847 | 5368 | RTX_CODE code = GET_CODE (x); |
eab89b90 | 5369 | |
c4963a0a | 5370 | if (context == 1) |
888d2cd6 DJ |
5371 | context_reg_class = INDEX_REG_CLASS; |
5372 | else | |
c4963a0a | 5373 | context_reg_class = base_reg_class (mode, outer_code, index_code); |
888d2cd6 | 5374 | |
a2d353e5 | 5375 | switch (code) |
eab89b90 | 5376 | { |
a2d353e5 RK |
5377 | case PLUS: |
5378 | { | |
b3694847 SS |
5379 | rtx orig_op0 = XEXP (x, 0); |
5380 | rtx orig_op1 = XEXP (x, 1); | |
5381 | RTX_CODE code0 = GET_CODE (orig_op0); | |
5382 | RTX_CODE code1 = GET_CODE (orig_op1); | |
5383 | rtx op0 = orig_op0; | |
5384 | rtx op1 = orig_op1; | |
a2d353e5 RK |
5385 | |
5386 | if (GET_CODE (op0) == SUBREG) | |
5387 | { | |
5388 | op0 = SUBREG_REG (op0); | |
5389 | code0 = GET_CODE (op0); | |
922db4bb | 5390 | if (code0 == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER) |
38a448ca | 5391 | op0 = gen_rtx_REG (word_mode, |
ddef6bc7 JJ |
5392 | (REGNO (op0) + |
5393 | subreg_regno_offset (REGNO (SUBREG_REG (orig_op0)), | |
5394 | GET_MODE (SUBREG_REG (orig_op0)), | |
5395 | SUBREG_BYTE (orig_op0), | |
5396 | GET_MODE (orig_op0)))); | |
a2d353e5 | 5397 | } |
87935f60 | 5398 | |
a2d353e5 RK |
5399 | if (GET_CODE (op1) == SUBREG) |
5400 | { | |
5401 | op1 = SUBREG_REG (op1); | |
5402 | code1 = GET_CODE (op1); | |
922db4bb | 5403 | if (code1 == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER) |
ddef6bc7 JJ |
5404 | /* ??? Why is this given op1's mode and above for |
5405 | ??? op0 SUBREGs we use word_mode? */ | |
38a448ca | 5406 | op1 = gen_rtx_REG (GET_MODE (op1), |
ddef6bc7 JJ |
5407 | (REGNO (op1) + |
5408 | subreg_regno_offset (REGNO (SUBREG_REG (orig_op1)), | |
5409 | GET_MODE (SUBREG_REG (orig_op1)), | |
5410 | SUBREG_BYTE (orig_op1), | |
5411 | GET_MODE (orig_op1)))); | |
a2d353e5 | 5412 | } |
04c5580f | 5413 | /* Plus in the index register may be created only as a result of |
6fc0bb99 | 5414 | register rematerialization for expression like &localvar*4. Reload it. |
04c5580f JH |
5415 | It may be possible to combine the displacement on the outer level, |
5416 | but it is probably not worthwhile to do so. */ | |
888d2cd6 | 5417 | if (context == 1) |
04c5580f JH |
5418 | { |
5419 | find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0), | |
5420 | opnum, ADDR_TYPE (type), ind_levels, insn); | |
5421 | push_reload (*loc, NULL_RTX, loc, (rtx*) 0, | |
888d2cd6 | 5422 | context_reg_class, |
04c5580f JH |
5423 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5424 | return 1; | |
5425 | } | |
a2d353e5 | 5426 | |
05d10675 | 5427 | if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE |
5f8997b9 | 5428 | || code0 == ZERO_EXTEND || code1 == MEM) |
a2d353e5 | 5429 | { |
c4963a0a BS |
5430 | find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH, |
5431 | &XEXP (x, 0), opnum, type, ind_levels, | |
5432 | insn); | |
5433 | find_reloads_address_1 (mode, orig_op1, 0, PLUS, code0, | |
5434 | &XEXP (x, 1), opnum, type, ind_levels, | |
5435 | insn); | |
a2d353e5 RK |
5436 | } |
5437 | ||
5f8997b9 SC |
5438 | else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE |
5439 | || code1 == ZERO_EXTEND || code0 == MEM) | |
a2d353e5 | 5440 | { |
c4963a0a BS |
5441 | find_reloads_address_1 (mode, orig_op0, 0, PLUS, code1, |
5442 | &XEXP (x, 0), opnum, type, ind_levels, | |
5443 | insn); | |
5444 | find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH, | |
5445 | &XEXP (x, 1), opnum, type, ind_levels, | |
5446 | insn); | |
a2d353e5 RK |
5447 | } |
5448 | ||
5449 | else if (code0 == CONST_INT || code0 == CONST | |
5450 | || code0 == SYMBOL_REF || code0 == LABEL_REF) | |
c4963a0a BS |
5451 | find_reloads_address_1 (mode, orig_op1, 0, PLUS, code0, |
5452 | &XEXP (x, 1), opnum, type, ind_levels, | |
5453 | insn); | |
a2d353e5 RK |
5454 | |
5455 | else if (code1 == CONST_INT || code1 == CONST | |
5456 | || code1 == SYMBOL_REF || code1 == LABEL_REF) | |
c4963a0a BS |
5457 | find_reloads_address_1 (mode, orig_op0, 0, PLUS, code1, |
5458 | &XEXP (x, 0), opnum, type, ind_levels, | |
5459 | insn); | |
a2d353e5 RK |
5460 | |
5461 | else if (code0 == REG && code1 == REG) | |
5462 | { | |
c4963a0a BS |
5463 | if (REGNO_OK_FOR_INDEX_P (REGNO (op0)) |
5464 | && regno_ok_for_base_p (REGNO (op1), mode, PLUS, REG)) | |
a2d353e5 | 5465 | return 0; |
c4963a0a BS |
5466 | else if (REGNO_OK_FOR_INDEX_P (REGNO (op1)) |
5467 | && regno_ok_for_base_p (REGNO (op0), mode, PLUS, REG)) | |
a2d353e5 | 5468 | return 0; |
c4963a0a BS |
5469 | else if (regno_ok_for_base_p (REGNO (op1), mode, PLUS, REG)) |
5470 | find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH, | |
5471 | &XEXP (x, 0), opnum, type, ind_levels, | |
5472 | insn); | |
5473 | else if (regno_ok_for_base_p (REGNO (op0), mode, PLUS, REG)) | |
5474 | find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH, | |
5475 | &XEXP (x, 1), opnum, type, ind_levels, | |
5476 | insn); | |
5477 | else if (REGNO_OK_FOR_INDEX_P (REGNO (op1))) | |
5478 | find_reloads_address_1 (mode, orig_op0, 0, PLUS, REG, | |
5479 | &XEXP (x, 0), opnum, type, ind_levels, | |
5480 | insn); | |
5481 | else if (REGNO_OK_FOR_INDEX_P (REGNO (op0))) | |
5482 | find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG, | |
5483 | &XEXP (x, 1), opnum, type, ind_levels, | |
5484 | insn); | |
a2d353e5 RK |
5485 | else |
5486 | { | |
c4963a0a BS |
5487 | find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH, |
5488 | &XEXP (x, 0), opnum, type, ind_levels, | |
5489 | insn); | |
5490 | find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG, | |
5491 | &XEXP (x, 1), opnum, type, ind_levels, | |
5492 | insn); | |
a2d353e5 RK |
5493 | } |
5494 | } | |
5495 | ||
5496 | else if (code0 == REG) | |
5497 | { | |
c4963a0a BS |
5498 | find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH, |
5499 | &XEXP (x, 0), opnum, type, ind_levels, | |
5500 | insn); | |
5501 | find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG, | |
5502 | &XEXP (x, 1), opnum, type, ind_levels, | |
5503 | insn); | |
a2d353e5 RK |
5504 | } |
5505 | ||
5506 | else if (code1 == REG) | |
5507 | { | |
c4963a0a BS |
5508 | find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH, |
5509 | &XEXP (x, 1), opnum, type, ind_levels, | |
5510 | insn); | |
5511 | find_reloads_address_1 (mode, orig_op0, 0, PLUS, REG, | |
5512 | &XEXP (x, 0), opnum, type, ind_levels, | |
5513 | insn); | |
a2d353e5 RK |
5514 | } |
5515 | } | |
5516 | ||
5517 | return 0; | |
5518 | ||
4b983fdc RH |
5519 | case POST_MODIFY: |
5520 | case PRE_MODIFY: | |
5521 | { | |
5522 | rtx op0 = XEXP (x, 0); | |
5523 | rtx op1 = XEXP (x, 1); | |
c4963a0a | 5524 | enum rtx_code index_code; |
41374e13 NS |
5525 | int regno; |
5526 | int reloadnum; | |
4b983fdc RH |
5527 | |
5528 | if (GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS) | |
5529 | return 0; | |
5530 | ||
5531 | /* Currently, we only support {PRE,POST}_MODIFY constructs | |
5532 | where a base register is {inc,dec}remented by the contents | |
5533 | of another register or by a constant value. Thus, these | |
5534 | operands must match. */ | |
41374e13 | 5535 | gcc_assert (op0 == XEXP (op1, 0)); |
4b983fdc RH |
5536 | |
5537 | /* Require index register (or constant). Let's just handle the | |
5538 | register case in the meantime... If the target allows | |
5539 | auto-modify by a constant then we could try replacing a pseudo | |
4b7b277a RS |
5540 | register with its equivalent constant where applicable. |
5541 | ||
b098aaf2 UW |
5542 | We also handle the case where the register was eliminated |
5543 | resulting in a PLUS subexpression. | |
5544 | ||
4b7b277a RS |
5545 | If we later decide to reload the whole PRE_MODIFY or |
5546 | POST_MODIFY, inc_for_reload might clobber the reload register | |
5547 | before reading the index. The index register might therefore | |
5548 | need to live longer than a TYPE reload normally would, so be | |
5549 | conservative and class it as RELOAD_OTHER. */ | |
b098aaf2 UW |
5550 | if ((REG_P (XEXP (op1, 1)) |
5551 | && !REGNO_OK_FOR_INDEX_P (REGNO (XEXP (op1, 1)))) | |
5552 | || GET_CODE (XEXP (op1, 1)) == PLUS) | |
5553 | find_reloads_address_1 (mode, XEXP (op1, 1), 1, code, SCRATCH, | |
5554 | &XEXP (op1, 1), opnum, RELOAD_OTHER, | |
5555 | ind_levels, insn); | |
4b983fdc | 5556 | |
41374e13 | 5557 | gcc_assert (REG_P (XEXP (op1, 0))); |
4b983fdc | 5558 | |
41374e13 | 5559 | regno = REGNO (XEXP (op1, 0)); |
c4963a0a | 5560 | index_code = GET_CODE (XEXP (op1, 1)); |
41374e13 NS |
5561 | |
5562 | /* A register that is incremented cannot be constant! */ | |
5563 | gcc_assert (regno < FIRST_PSEUDO_REGISTER | |
5564 | || reg_equiv_constant[regno] == 0); | |
4b983fdc | 5565 | |
41374e13 NS |
5566 | /* Handle a register that is equivalent to a memory location |
5567 | which cannot be addressed directly. */ | |
5568 | if (reg_equiv_memory_loc[regno] != 0 | |
5569 | && (reg_equiv_address[regno] != 0 | |
5570 | || num_not_at_initial_offset)) | |
5571 | { | |
5572 | rtx tem = make_memloc (XEXP (x, 0), regno); | |
4b983fdc | 5573 | |
41374e13 NS |
5574 | if (reg_equiv_address[regno] |
5575 | || ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
4b983fdc | 5576 | { |
3f1e3e70 AO |
5577 | rtx orig = tem; |
5578 | ||
41374e13 NS |
5579 | /* First reload the memory location's address. |
5580 | We can't use ADDR_TYPE (type) here, because we need to | |
5581 | write back the value after reading it, hence we actually | |
5582 | need two registers. */ | |
5583 | find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), | |
5584 | &XEXP (tem, 0), opnum, | |
5585 | RELOAD_OTHER, | |
5586 | ind_levels, insn); | |
5587 | ||
0f4b25a3 | 5588 | if (!rtx_equal_p (tem, orig)) |
3f1e3e70 AO |
5589 | push_reg_equiv_alt_mem (regno, tem); |
5590 | ||
41374e13 | 5591 | /* Then reload the memory location into a base |
c4963a0a | 5592 | register. */ |
41374e13 | 5593 | reloadnum = push_reload (tem, tem, &XEXP (x, 0), |
c4963a0a BS |
5594 | &XEXP (op1, 0), |
5595 | base_reg_class (mode, code, | |
5596 | index_code), | |
5597 | GET_MODE (x), GET_MODE (x), 0, | |
5598 | 0, opnum, RELOAD_OTHER); | |
9532e31f | 5599 | |
98c17df2 GS |
5600 | update_auto_inc_notes (this_insn, regno, reloadnum); |
5601 | return 0; | |
5602 | } | |
4b983fdc | 5603 | } |
41374e13 NS |
5604 | |
5605 | if (reg_renumber[regno] >= 0) | |
5606 | regno = reg_renumber[regno]; | |
5607 | ||
5608 | /* We require a base register here... */ | |
c4963a0a | 5609 | if (!regno_ok_for_base_p (regno, GET_MODE (x), code, index_code)) |
41374e13 NS |
5610 | { |
5611 | reloadnum = push_reload (XEXP (op1, 0), XEXP (x, 0), | |
c4963a0a BS |
5612 | &XEXP (op1, 0), &XEXP (x, 0), |
5613 | base_reg_class (mode, code, index_code), | |
5614 | GET_MODE (x), GET_MODE (x), 0, 0, | |
5615 | opnum, RELOAD_OTHER); | |
41374e13 NS |
5616 | |
5617 | update_auto_inc_notes (this_insn, regno, reloadnum); | |
5618 | return 0; | |
5619 | } | |
4b983fdc RH |
5620 | } |
5621 | return 0; | |
5622 | ||
a2d353e5 RK |
5623 | case POST_INC: |
5624 | case POST_DEC: | |
5625 | case PRE_INC: | |
5626 | case PRE_DEC: | |
f8cfc6aa | 5627 | if (REG_P (XEXP (x, 0))) |
eab89b90 | 5628 | { |
b3694847 | 5629 | int regno = REGNO (XEXP (x, 0)); |
eab89b90 RK |
5630 | int value = 0; |
5631 | rtx x_orig = x; | |
5632 | ||
5633 | /* A register that is incremented cannot be constant! */ | |
41374e13 NS |
5634 | gcc_assert (regno < FIRST_PSEUDO_REGISTER |
5635 | || reg_equiv_constant[regno] == 0); | |
eab89b90 RK |
5636 | |
5637 | /* Handle a register that is equivalent to a memory location | |
5638 | which cannot be addressed directly. */ | |
cb2afeb3 R |
5639 | if (reg_equiv_memory_loc[regno] != 0 |
5640 | && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)) | |
eab89b90 RK |
5641 | { |
5642 | rtx tem = make_memloc (XEXP (x, 0), regno); | |
cb2afeb3 R |
5643 | if (reg_equiv_address[regno] |
5644 | || ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
5645 | { | |
3f1e3e70 AO |
5646 | rtx orig = tem; |
5647 | ||
cb2afeb3 R |
5648 | /* First reload the memory location's address. |
5649 | We can't use ADDR_TYPE (type) here, because we need to | |
5650 | write back the value after reading it, hence we actually | |
5651 | need two registers. */ | |
5652 | find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), | |
5653 | &XEXP (tem, 0), opnum, type, | |
5654 | ind_levels, insn); | |
0f4b25a3 | 5655 | if (!rtx_equal_p (tem, orig)) |
3f1e3e70 | 5656 | push_reg_equiv_alt_mem (regno, tem); |
cb2afeb3 R |
5657 | /* Put this inside a new increment-expression. */ |
5658 | x = gen_rtx_fmt_e (GET_CODE (x), GET_MODE (x), tem); | |
5659 | /* Proceed to reload that, as if it contained a register. */ | |
5660 | } | |
eab89b90 RK |
5661 | } |
5662 | ||
5663 | /* If we have a hard register that is ok as an index, | |
5664 | don't make a reload. If an autoincrement of a nice register | |
5665 | isn't "valid", it must be that no autoincrement is "valid". | |
5666 | If that is true and something made an autoincrement anyway, | |
5667 | this must be a special context where one is allowed. | |
5668 | (For example, a "push" instruction.) | |
5669 | We can't improve this address, so leave it alone. */ | |
5670 | ||
5671 | /* Otherwise, reload the autoincrement into a suitable hard reg | |
5672 | and record how much to increment by. */ | |
5673 | ||
5674 | if (reg_renumber[regno] >= 0) | |
5675 | regno = reg_renumber[regno]; | |
888d2cd6 | 5676 | if (regno >= FIRST_PSEUDO_REGISTER |
c4963a0a BS |
5677 | || !REG_OK_FOR_CONTEXT (context, regno, mode, outer_code, |
5678 | index_code)) | |
eab89b90 | 5679 | { |
55c22565 RK |
5680 | int reloadnum; |
5681 | ||
5682 | /* If we can output the register afterwards, do so, this | |
5683 | saves the extra update. | |
5684 | We can do so if we have an INSN - i.e. no JUMP_INSN nor | |
5685 | CALL_INSN - and it does not set CC0. | |
5686 | But don't do this if we cannot directly address the | |
5687 | memory location, since this will make it harder to | |
956d6950 | 5688 | reuse address reloads, and increases register pressure. |
55c22565 | 5689 | Also don't do this if we can probably update x directly. */ |
3c0cb5de | 5690 | rtx equiv = (MEM_P (XEXP (x, 0)) |
cb2afeb3 R |
5691 | ? XEXP (x, 0) |
5692 | : reg_equiv_mem[regno]); | |
55c22565 | 5693 | int icode = (int) add_optab->handlers[(int) Pmode].insn_code; |
4b4bf941 | 5694 | if (insn && NONJUMP_INSN_P (insn) && equiv |
cb2afeb3 | 5695 | && memory_operand (equiv, GET_MODE (equiv)) |
55c22565 RK |
5696 | #ifdef HAVE_cc0 |
5697 | && ! sets_cc0_p (PATTERN (insn)) | |
5698 | #endif | |
5699 | && ! (icode != CODE_FOR_nothing | |
a995e389 RH |
5700 | && ((*insn_data[icode].operand[0].predicate) |
5701 | (equiv, Pmode)) | |
5702 | && ((*insn_data[icode].operand[1].predicate) | |
5703 | (equiv, Pmode)))) | |
55c22565 | 5704 | { |
9e8f528c AO |
5705 | /* We use the original pseudo for loc, so that |
5706 | emit_reload_insns() knows which pseudo this | |
5707 | reload refers to and updates the pseudo rtx, not | |
5708 | its equivalent memory location, as well as the | |
5709 | corresponding entry in reg_last_reload_reg. */ | |
5710 | loc = &XEXP (x_orig, 0); | |
55c22565 RK |
5711 | x = XEXP (x, 0); |
5712 | reloadnum | |
5713 | = push_reload (x, x, loc, loc, | |
888d2cd6 | 5714 | context_reg_class, |
05d10675 BS |
5715 | GET_MODE (x), GET_MODE (x), 0, 0, |
5716 | opnum, RELOAD_OTHER); | |
55c22565 RK |
5717 | } |
5718 | else | |
5719 | { | |
5720 | reloadnum | |
f4f4d0f8 | 5721 | = push_reload (x, NULL_RTX, loc, (rtx*) 0, |
888d2cd6 | 5722 | context_reg_class, |
e9a25f70 | 5723 | GET_MODE (x), GET_MODE (x), 0, 0, |
55c22565 | 5724 | opnum, type); |
eceef4c9 | 5725 | rld[reloadnum].inc |
55c22565 | 5726 | = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0)); |
05d10675 | 5727 | |
55c22565 RK |
5728 | value = 1; |
5729 | } | |
eab89b90 | 5730 | |
98c17df2 GS |
5731 | update_auto_inc_notes (this_insn, REGNO (XEXP (x_orig, 0)), |
5732 | reloadnum); | |
eab89b90 RK |
5733 | } |
5734 | return value; | |
5735 | } | |
a2d353e5 RK |
5736 | return 0; |
5737 | ||
19fe122f HPN |
5738 | case TRUNCATE: |
5739 | case SIGN_EXTEND: | |
5740 | case ZERO_EXTEND: | |
5741 | /* Look for parts to reload in the inner expression and reload them | |
5742 | too, in addition to this operation. Reloading all inner parts in | |
5743 | addition to this one shouldn't be necessary, but at this point, | |
5744 | we don't know if we can possibly omit any part that *can* be | |
5745 | reloaded. Targets that are better off reloading just either part | |
5746 | (or perhaps even a different part of an outer expression), should | |
5747 | define LEGITIMIZE_RELOAD_ADDRESS. */ | |
5748 | find_reloads_address_1 (GET_MODE (XEXP (x, 0)), XEXP (x, 0), | |
c4963a0a | 5749 | context, code, SCRATCH, &XEXP (x, 0), opnum, |
19fe122f HPN |
5750 | type, ind_levels, insn); |
5751 | push_reload (x, NULL_RTX, loc, (rtx*) 0, | |
5752 | context_reg_class, | |
5753 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); | |
5754 | return 1; | |
5755 | ||
a2d353e5 RK |
5756 | case MEM: |
5757 | /* This is probably the result of a substitution, by eliminate_regs, of | |
5758 | an equivalent address for a pseudo that was not allocated to a hard | |
5759 | register. Verify that the specified address is valid and reload it | |
5760 | into a register. | |
eab89b90 | 5761 | |
a2d353e5 RK |
5762 | Since we know we are going to reload this item, don't decrement for |
5763 | the indirection level. | |
eab89b90 RK |
5764 | |
5765 | Note that this is actually conservative: it would be slightly more | |
5766 | efficient to use the value of SPILL_INDIRECT_LEVELS from | |
5767 | reload1.c here. */ | |
5768 | ||
5769 | find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0), | |
55c22565 | 5770 | opnum, ADDR_TYPE (type), ind_levels, insn); |
f4f4d0f8 | 5771 | push_reload (*loc, NULL_RTX, loc, (rtx*) 0, |
888d2cd6 | 5772 | context_reg_class, |
a8c9daeb | 5773 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
eab89b90 | 5774 | return 1; |
eab89b90 | 5775 | |
a2d353e5 RK |
5776 | case REG: |
5777 | { | |
b3694847 | 5778 | int regno = REGNO (x); |
a2d353e5 RK |
5779 | |
5780 | if (reg_equiv_constant[regno] != 0) | |
5781 | { | |
03acd8f8 | 5782 | find_reloads_address_part (reg_equiv_constant[regno], loc, |
888d2cd6 | 5783 | context_reg_class, |
a2d353e5 RK |
5784 | GET_MODE (x), opnum, type, ind_levels); |
5785 | return 1; | |
5786 | } | |
eab89b90 RK |
5787 | |
5788 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
5789 | that feeds this insn. */ | |
a2d353e5 RK |
5790 | if (reg_equiv_mem[regno] != 0) |
5791 | { | |
f4f4d0f8 | 5792 | push_reload (reg_equiv_mem[regno], NULL_RTX, loc, (rtx*) 0, |
888d2cd6 | 5793 | context_reg_class, |
a2d353e5 RK |
5794 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5795 | return 1; | |
5796 | } | |
eab89b90 | 5797 | #endif |
eab89b90 | 5798 | |
cb2afeb3 R |
5799 | if (reg_equiv_memory_loc[regno] |
5800 | && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)) | |
a2d353e5 | 5801 | { |
cb2afeb3 R |
5802 | rtx tem = make_memloc (x, regno); |
5803 | if (reg_equiv_address[regno] != 0 | |
5804 | || ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
5805 | { | |
5806 | x = tem; | |
5807 | find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), | |
5808 | &XEXP (x, 0), opnum, ADDR_TYPE (type), | |
5809 | ind_levels, insn); | |
0f4b25a3 | 5810 | if (!rtx_equal_p (x, tem)) |
3f1e3e70 | 5811 | push_reg_equiv_alt_mem (regno, x); |
cb2afeb3 | 5812 | } |
a2d353e5 | 5813 | } |
eab89b90 | 5814 | |
a2d353e5 RK |
5815 | if (reg_renumber[regno] >= 0) |
5816 | regno = reg_renumber[regno]; | |
5817 | ||
888d2cd6 | 5818 | if (regno >= FIRST_PSEUDO_REGISTER |
c4963a0a BS |
5819 | || !REG_OK_FOR_CONTEXT (context, regno, mode, outer_code, |
5820 | index_code)) | |
a2d353e5 | 5821 | { |
f4f4d0f8 | 5822 | push_reload (x, NULL_RTX, loc, (rtx*) 0, |
888d2cd6 | 5823 | context_reg_class, |
a2d353e5 RK |
5824 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5825 | return 1; | |
5826 | } | |
5827 | ||
5828 | /* If a register appearing in an address is the subject of a CLOBBER | |
5829 | in this insn, reload it into some other register to be safe. | |
5830 | The CLOBBER is supposed to make the register unavailable | |
5831 | from before this insn to after it. */ | |
9532e31f | 5832 | if (regno_clobbered_p (regno, this_insn, GET_MODE (x), 0)) |
a2d353e5 | 5833 | { |
f4f4d0f8 | 5834 | push_reload (x, NULL_RTX, loc, (rtx*) 0, |
888d2cd6 | 5835 | context_reg_class, |
a2d353e5 RK |
5836 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5837 | return 1; | |
5838 | } | |
5839 | } | |
5840 | return 0; | |
5841 | ||
5842 | case SUBREG: | |
f8cfc6aa | 5843 | if (REG_P (SUBREG_REG (x))) |
eab89b90 | 5844 | { |
922db4bb RK |
5845 | /* If this is a SUBREG of a hard register and the resulting register |
5846 | is of the wrong class, reload the whole SUBREG. This avoids | |
5847 | needless copies if SUBREG_REG is multi-word. */ | |
5848 | if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) | |
5849 | { | |
4977bab6 | 5850 | int regno ATTRIBUTE_UNUSED = subreg_regno (x); |
a2d353e5 | 5851 | |
c4963a0a BS |
5852 | if (!REG_OK_FOR_CONTEXT (context, regno, mode, outer_code, |
5853 | index_code)) | |
922db4bb | 5854 | { |
f4f4d0f8 | 5855 | push_reload (x, NULL_RTX, loc, (rtx*) 0, |
888d2cd6 | 5856 | context_reg_class, |
922db4bb RK |
5857 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5858 | return 1; | |
5859 | } | |
5860 | } | |
abc95ed3 | 5861 | /* If this is a SUBREG of a pseudo-register, and the pseudo-register |
922db4bb RK |
5862 | is larger than the class size, then reload the whole SUBREG. */ |
5863 | else | |
a2d353e5 | 5864 | { |
888d2cd6 | 5865 | enum reg_class class = context_reg_class; |
f7043461 | 5866 | if ((unsigned) CLASS_MAX_NREGS (class, GET_MODE (SUBREG_REG (x))) |
922db4bb RK |
5867 | > reg_class_size[class]) |
5868 | { | |
50aa8e71 R |
5869 | x = find_reloads_subreg_address (x, 0, opnum, |
5870 | ADDR_TYPE (type), | |
22505ad8 | 5871 | ind_levels, insn); |
f4f4d0f8 | 5872 | push_reload (x, NULL_RTX, loc, (rtx*) 0, class, |
922db4bb RK |
5873 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5874 | return 1; | |
5875 | } | |
a2d353e5 | 5876 | } |
eab89b90 | 5877 | } |
a2d353e5 | 5878 | break; |
05d10675 | 5879 | |
e9a25f70 JL |
5880 | default: |
5881 | break; | |
eab89b90 RK |
5882 | } |
5883 | ||
a2d353e5 | 5884 | { |
b3694847 SS |
5885 | const char *fmt = GET_RTX_FORMAT (code); |
5886 | int i; | |
a2d353e5 RK |
5887 | |
5888 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5889 | { | |
5890 | if (fmt[i] == 'e') | |
c4963a0a BS |
5891 | /* Pass SCRATCH for INDEX_CODE, since CODE can never be a PLUS once |
5892 | we get here. */ | |
5893 | find_reloads_address_1 (mode, XEXP (x, i), context, code, SCRATCH, | |
5894 | &XEXP (x, i), opnum, type, ind_levels, insn); | |
a2d353e5 RK |
5895 | } |
5896 | } | |
5897 | ||
888d2cd6 | 5898 | #undef REG_OK_FOR_CONTEXT |
eab89b90 RK |
5899 | return 0; |
5900 | } | |
5901 | \f | |
5902 | /* X, which is found at *LOC, is a part of an address that needs to be | |
5903 | reloaded into a register of class CLASS. If X is a constant, or if | |
5904 | X is a PLUS that contains a constant, check that the constant is a | |
5905 | legitimate operand and that we are supposed to be able to load | |
5906 | it into the register. | |
5907 | ||
5908 | If not, force the constant into memory and reload the MEM instead. | |
5909 | ||
5910 | MODE is the mode to use, in case X is an integer constant. | |
5911 | ||
a8c9daeb | 5912 | OPNUM and TYPE describe the purpose of any reloads made. |
eab89b90 RK |
5913 | |
5914 | IND_LEVELS says how many levels of indirect addressing this machine | |
5915 | supports. */ | |
5916 | ||
5917 | static void | |
0c20a65f AJ |
5918 | find_reloads_address_part (rtx x, rtx *loc, enum reg_class class, |
5919 | enum machine_mode mode, int opnum, | |
5920 | enum reload_type type, int ind_levels) | |
eab89b90 RK |
5921 | { |
5922 | if (CONSTANT_P (x) | |
5923 | && (! LEGITIMATE_CONSTANT_P (x) | |
5924 | || PREFERRED_RELOAD_CLASS (x, class) == NO_REGS)) | |
5925 | { | |
ef18065c JW |
5926 | rtx tem; |
5927 | ||
081b49f1 | 5928 | tem = x = force_const_mem (mode, x); |
eab89b90 | 5929 | find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), |
55c22565 | 5930 | opnum, type, ind_levels, 0); |
eab89b90 RK |
5931 | } |
5932 | ||
5933 | else if (GET_CODE (x) == PLUS | |
5934 | && CONSTANT_P (XEXP (x, 1)) | |
5935 | && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1)) | |
5936 | || PREFERRED_RELOAD_CLASS (XEXP (x, 1), class) == NO_REGS)) | |
5937 | { | |
ef18065c JW |
5938 | rtx tem; |
5939 | ||
081b49f1 | 5940 | tem = force_const_mem (GET_MODE (x), XEXP (x, 1)); |
38a448ca | 5941 | x = gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), tem); |
eab89b90 | 5942 | find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), |
55c22565 | 5943 | opnum, type, ind_levels, 0); |
eab89b90 RK |
5944 | } |
5945 | ||
f4f4d0f8 | 5946 | push_reload (x, NULL_RTX, loc, (rtx*) 0, class, |
a8c9daeb | 5947 | mode, VOIDmode, 0, 0, opnum, type); |
eab89b90 RK |
5948 | } |
5949 | \f | |
22505ad8 R |
5950 | /* X, a subreg of a pseudo, is a part of an address that needs to be |
5951 | reloaded. | |
5952 | ||
5953 | If the pseudo is equivalent to a memory location that cannot be directly | |
5954 | addressed, make the necessary address reloads. | |
5955 | ||
5956 | If address reloads have been necessary, or if the address is changed | |
5957 | by register elimination, return the rtx of the memory location; | |
5958 | otherwise, return X. | |
5959 | ||
5960 | If FORCE_REPLACE is nonzero, unconditionally replace the subreg with the | |
5961 | memory location. | |
5962 | ||
5963 | OPNUM and TYPE identify the purpose of the reload. | |
5964 | ||
5965 | IND_LEVELS says how many levels of indirect addressing are | |
5966 | supported at this point in the address. | |
5967 | ||
5968 | INSN, if nonzero, is the insn in which we do the reload. It is used | |
5969 | to determine where to put USEs for pseudos that we have to replace with | |
5970 | stack slots. */ | |
5971 | ||
5972 | static rtx | |
0c20a65f AJ |
5973 | find_reloads_subreg_address (rtx x, int force_replace, int opnum, |
5974 | enum reload_type type, int ind_levels, rtx insn) | |
22505ad8 R |
5975 | { |
5976 | int regno = REGNO (SUBREG_REG (x)); | |
5977 | ||
5978 | if (reg_equiv_memory_loc[regno]) | |
5979 | { | |
5980 | /* If the address is not directly addressable, or if the address is not | |
5981 | offsettable, then it must be replaced. */ | |
5982 | if (! force_replace | |
5983 | && (reg_equiv_address[regno] | |
5984 | || ! offsettable_memref_p (reg_equiv_mem[regno]))) | |
5985 | force_replace = 1; | |
5986 | ||
5987 | if (force_replace || num_not_at_initial_offset) | |
5988 | { | |
5989 | rtx tem = make_memloc (SUBREG_REG (x), regno); | |
5990 | ||
5991 | /* If the address changes because of register elimination, then | |
dd074554 | 5992 | it must be replaced. */ |
22505ad8 R |
5993 | if (force_replace |
5994 | || ! rtx_equal_p (tem, reg_equiv_mem[regno])) | |
5995 | { | |
0a28aef9 RH |
5996 | unsigned outer_size = GET_MODE_SIZE (GET_MODE (x)); |
5997 | unsigned inner_size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))); | |
6357135a | 5998 | int offset; |
3f1e3e70 | 5999 | rtx orig = tem; |
f5c3dc96 ILT |
6000 | enum machine_mode orig_mode = GET_MODE (orig); |
6001 | int reloaded; | |
6357135a UW |
6002 | |
6003 | /* For big-endian paradoxical subregs, SUBREG_BYTE does not | |
6004 | hold the correct (negative) byte offset. */ | |
6005 | if (BYTES_BIG_ENDIAN && outer_size > inner_size) | |
6006 | offset = inner_size - outer_size; | |
6007 | else | |
6008 | offset = SUBREG_BYTE (x); | |
22505ad8 | 6009 | |
22505ad8 R |
6010 | XEXP (tem, 0) = plus_constant (XEXP (tem, 0), offset); |
6011 | PUT_MODE (tem, GET_MODE (x)); | |
0a28aef9 RH |
6012 | |
6013 | /* If this was a paradoxical subreg that we replaced, the | |
6014 | resulting memory must be sufficiently aligned to allow | |
6015 | us to widen the mode of the memory. */ | |
5a575f77 | 6016 | if (outer_size > inner_size) |
0a28aef9 RH |
6017 | { |
6018 | rtx base; | |
6019 | ||
6020 | base = XEXP (tem, 0); | |
6021 | if (GET_CODE (base) == PLUS) | |
6022 | { | |
6023 | if (GET_CODE (XEXP (base, 1)) == CONST_INT | |
6024 | && INTVAL (XEXP (base, 1)) % outer_size != 0) | |
6025 | return x; | |
6026 | base = XEXP (base, 0); | |
6027 | } | |
f8cfc6aa | 6028 | if (!REG_P (base) |
0a28aef9 RH |
6029 | || (REGNO_POINTER_ALIGN (REGNO (base)) |
6030 | < outer_size * BITS_PER_UNIT)) | |
6031 | return x; | |
6032 | } | |
6033 | ||
f5c3dc96 ILT |
6034 | reloaded = find_reloads_address (GET_MODE (tem), &tem, |
6035 | XEXP (tem, 0), &XEXP (tem, 0), | |
6036 | opnum, type, ind_levels, insn); | |
3f1e3e70 | 6037 | /* ??? Do we need to handle nonzero offsets somehow? */ |
0f4b25a3 | 6038 | if (!offset && !rtx_equal_p (tem, orig)) |
3f1e3e70 | 6039 | push_reg_equiv_alt_mem (regno, tem); |
0a28aef9 | 6040 | |
f5c3dc96 ILT |
6041 | /* For some processors an address may be valid in the |
6042 | original mode but not in a smaller mode. For | |
6043 | example, ARM accepts a scaled index register in | |
6044 | SImode but not in HImode. find_reloads_address | |
6045 | assumes that we pass it a valid address, and doesn't | |
6046 | force a reload. This will probably be fine if | |
6047 | find_reloads_address finds some reloads. But if it | |
6048 | doesn't find any, then we may have just converted a | |
6049 | valid address into an invalid one. Check for that | |
6050 | here. */ | |
6051 | if (reloaded != 1 | |
6052 | && strict_memory_address_p (orig_mode, XEXP (tem, 0)) | |
6053 | && !strict_memory_address_p (GET_MODE (tem), | |
6054 | XEXP (tem, 0))) | |
6055 | push_reload (XEXP (tem, 0), NULL_RTX, &XEXP (tem, 0), (rtx*) 0, | |
6056 | base_reg_class (GET_MODE (tem), MEM, SCRATCH), | |
6057 | GET_MODE (XEXP (tem, 0)), VOIDmode, 0, 0, | |
6058 | opnum, type); | |
6059 | ||
22505ad8 R |
6060 | /* If this is not a toplevel operand, find_reloads doesn't see |
6061 | this substitution. We have to emit a USE of the pseudo so | |
6062 | that delete_output_reload can see it. */ | |
1ccbefce | 6063 | if (replace_reloads && recog_data.operand[opnum] != x) |
3d17d93d AO |
6064 | /* We mark the USE with QImode so that we recognize it |
6065 | as one that can be safely deleted at the end of | |
6066 | reload. */ | |
6067 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, | |
6068 | SUBREG_REG (x)), | |
6069 | insn), QImode); | |
0ba9b9e6 | 6070 | x = tem; |
22505ad8 R |
6071 | } |
6072 | } | |
6073 | } | |
6074 | return x; | |
6075 | } | |
6076 | \f | |
a8c9daeb | 6077 | /* Substitute into the current INSN the registers into which we have reloaded |
eab89b90 | 6078 | the things that need reloading. The array `replacements' |
ecbe6c61 | 6079 | contains the locations of all pointers that must be changed |
eab89b90 RK |
6080 | and says what to replace them with. |
6081 | ||
6082 | Return the rtx that X translates into; usually X, but modified. */ | |
6083 | ||
6084 | void | |
0c20a65f | 6085 | subst_reloads (rtx insn) |
eab89b90 | 6086 | { |
b3694847 | 6087 | int i; |
eab89b90 RK |
6088 | |
6089 | for (i = 0; i < n_replacements; i++) | |
6090 | { | |
b3694847 SS |
6091 | struct replacement *r = &replacements[i]; |
6092 | rtx reloadreg = rld[r->what].reg_rtx; | |
eab89b90 RK |
6093 | if (reloadreg) |
6094 | { | |
0fa4cb7d SE |
6095 | #ifdef DEBUG_RELOAD |
6096 | /* This checking takes a very long time on some platforms | |
6097 | causing the gcc.c-torture/compile/limits-fnargs.c test | |
6098 | to time out during testing. See PR 31850. | |
6099 | ||
6100 | Internal consistency test. Check that we don't modify | |
cf728d61 HPN |
6101 | anything in the equivalence arrays. Whenever something from |
6102 | those arrays needs to be reloaded, it must be unshared before | |
6103 | being substituted into; the equivalence must not be modified. | |
6104 | Otherwise, if the equivalence is used after that, it will | |
6105 | have been modified, and the thing substituted (probably a | |
6106 | register) is likely overwritten and not a usable equivalence. */ | |
6107 | int check_regno; | |
6108 | ||
6109 | for (check_regno = 0; check_regno < max_regno; check_regno++) | |
6110 | { | |
6111 | #define CHECK_MODF(ARRAY) \ | |
41374e13 NS |
6112 | gcc_assert (!ARRAY[check_regno] \ |
6113 | || !loc_mentioned_in_p (r->where, \ | |
6114 | ARRAY[check_regno])) | |
cf728d61 HPN |
6115 | |
6116 | CHECK_MODF (reg_equiv_constant); | |
6117 | CHECK_MODF (reg_equiv_memory_loc); | |
6118 | CHECK_MODF (reg_equiv_address); | |
6119 | CHECK_MODF (reg_equiv_mem); | |
6120 | #undef CHECK_MODF | |
6121 | } | |
0fa4cb7d | 6122 | #endif /* DEBUG_RELOAD */ |
cf728d61 | 6123 | |
f759eb8b AO |
6124 | /* If we're replacing a LABEL_REF with a register, add a |
6125 | REG_LABEL note to indicate to flow which label this | |
6126 | register refers to. */ | |
6127 | if (GET_CODE (*r->where) == LABEL_REF | |
4b4bf941 | 6128 | && JUMP_P (insn)) |
d14e25e0 AP |
6129 | { |
6130 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, | |
6131 | XEXP (*r->where, 0), | |
6132 | REG_NOTES (insn)); | |
6133 | JUMP_LABEL (insn) = XEXP (*r->where, 0); | |
6134 | } | |
f759eb8b | 6135 | |
eab89b90 | 6136 | /* Encapsulate RELOADREG so its machine mode matches what |
26f1a00e RK |
6137 | used to be there. Note that gen_lowpart_common will |
6138 | do the wrong thing if RELOADREG is multi-word. RELOADREG | |
6139 | will always be a REG here. */ | |
eab89b90 | 6140 | if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode) |
f12448c8 | 6141 | reloadreg = reload_adjust_reg_for_mode (reloadreg, r->mode); |
eab89b90 RK |
6142 | |
6143 | /* If we are putting this into a SUBREG and RELOADREG is a | |
6144 | SUBREG, we would be making nested SUBREGs, so we have to fix | |
6145 | this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */ | |
6146 | ||
6147 | if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG) | |
6148 | { | |
6149 | if (GET_MODE (*r->subreg_loc) | |
6150 | == GET_MODE (SUBREG_REG (reloadreg))) | |
6151 | *r->subreg_loc = SUBREG_REG (reloadreg); | |
6152 | else | |
6153 | { | |
ddef6bc7 JJ |
6154 | int final_offset = |
6155 | SUBREG_BYTE (*r->subreg_loc) + SUBREG_BYTE (reloadreg); | |
6156 | ||
6157 | /* When working with SUBREGs the rule is that the byte | |
6158 | offset must be a multiple of the SUBREG's mode. */ | |
6159 | final_offset = (final_offset / | |
6160 | GET_MODE_SIZE (GET_MODE (*r->subreg_loc))); | |
6161 | final_offset = (final_offset * | |
6162 | GET_MODE_SIZE (GET_MODE (*r->subreg_loc))); | |
6163 | ||
eab89b90 | 6164 | *r->where = SUBREG_REG (reloadreg); |
ddef6bc7 | 6165 | SUBREG_BYTE (*r->subreg_loc) = final_offset; |
eab89b90 RK |
6166 | } |
6167 | } | |
6168 | else | |
6169 | *r->where = reloadreg; | |
6170 | } | |
6171 | /* If reload got no reg and isn't optional, something's wrong. */ | |
41374e13 NS |
6172 | else |
6173 | gcc_assert (rld[r->what].optional); | |
eab89b90 RK |
6174 | } |
6175 | } | |
6176 | \f | |
561c9153 RH |
6177 | /* Make a copy of any replacements being done into X and move those |
6178 | copies to locations in Y, a copy of X. */ | |
eab89b90 RK |
6179 | |
6180 | void | |
0c20a65f | 6181 | copy_replacements (rtx x, rtx y) |
eab89b90 | 6182 | { |
eab89b90 RK |
6183 | /* We can't support X being a SUBREG because we might then need to know its |
6184 | location if something inside it was replaced. */ | |
41374e13 | 6185 | gcc_assert (GET_CODE (x) != SUBREG); |
eab89b90 | 6186 | |
561c9153 RH |
6187 | copy_replacements_1 (&x, &y, n_replacements); |
6188 | } | |
6189 | ||
6190 | static void | |
0c20a65f | 6191 | copy_replacements_1 (rtx *px, rtx *py, int orig_replacements) |
561c9153 RH |
6192 | { |
6193 | int i, j; | |
6194 | rtx x, y; | |
6195 | struct replacement *r; | |
6196 | enum rtx_code code; | |
6197 | const char *fmt; | |
6198 | ||
6199 | for (j = 0; j < orig_replacements; j++) | |
6200 | { | |
6201 | if (replacements[j].subreg_loc == px) | |
eab89b90 | 6202 | { |
561c9153 RH |
6203 | r = &replacements[n_replacements++]; |
6204 | r->where = replacements[j].where; | |
6205 | r->subreg_loc = py; | |
6206 | r->what = replacements[j].what; | |
6207 | r->mode = replacements[j].mode; | |
6208 | } | |
6209 | else if (replacements[j].where == px) | |
6210 | { | |
6211 | r = &replacements[n_replacements++]; | |
6212 | r->where = py; | |
6213 | r->subreg_loc = 0; | |
6214 | r->what = replacements[j].what; | |
6215 | r->mode = replacements[j].mode; | |
eab89b90 | 6216 | } |
561c9153 RH |
6217 | } |
6218 | ||
6219 | x = *px; | |
6220 | y = *py; | |
6221 | code = GET_CODE (x); | |
6222 | fmt = GET_RTX_FORMAT (code); | |
6223 | ||
6224 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6225 | { | |
6226 | if (fmt[i] == 'e') | |
6227 | copy_replacements_1 (&XEXP (x, i), &XEXP (y, i), orig_replacements); | |
6228 | else if (fmt[i] == 'E') | |
6229 | for (j = XVECLEN (x, i); --j >= 0; ) | |
6230 | copy_replacements_1 (&XVECEXP (x, i, j), &XVECEXP (y, i, j), | |
6231 | orig_replacements); | |
6232 | } | |
eab89b90 | 6233 | } |
a9a2595b | 6234 | |
3eae4643 | 6235 | /* Change any replacements being done to *X to be done to *Y. */ |
a9a2595b JR |
6236 | |
6237 | void | |
0c20a65f | 6238 | move_replacements (rtx *x, rtx *y) |
a9a2595b JR |
6239 | { |
6240 | int i; | |
6241 | ||
6242 | for (i = 0; i < n_replacements; i++) | |
6243 | if (replacements[i].subreg_loc == x) | |
6244 | replacements[i].subreg_loc = y; | |
6245 | else if (replacements[i].where == x) | |
6246 | { | |
6247 | replacements[i].where = y; | |
6248 | replacements[i].subreg_loc = 0; | |
6249 | } | |
6250 | } | |
eab89b90 | 6251 | \f |
af929c62 RK |
6252 | /* If LOC was scheduled to be replaced by something, return the replacement. |
6253 | Otherwise, return *LOC. */ | |
6254 | ||
6255 | rtx | |
0c20a65f | 6256 | find_replacement (rtx *loc) |
af929c62 RK |
6257 | { |
6258 | struct replacement *r; | |
6259 | ||
6260 | for (r = &replacements[0]; r < &replacements[n_replacements]; r++) | |
6261 | { | |
eceef4c9 | 6262 | rtx reloadreg = rld[r->what].reg_rtx; |
af929c62 RK |
6263 | |
6264 | if (reloadreg && r->where == loc) | |
6265 | { | |
6266 | if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode) | |
38a448ca | 6267 | reloadreg = gen_rtx_REG (r->mode, REGNO (reloadreg)); |
af929c62 RK |
6268 | |
6269 | return reloadreg; | |
6270 | } | |
6271 | else if (reloadreg && r->subreg_loc == loc) | |
6272 | { | |
6273 | /* RELOADREG must be either a REG or a SUBREG. | |
6274 | ||
6275 | ??? Is it actually still ever a SUBREG? If so, why? */ | |
6276 | ||
f8cfc6aa | 6277 | if (REG_P (reloadreg)) |
38a448ca | 6278 | return gen_rtx_REG (GET_MODE (*loc), |
ddef6bc7 JJ |
6279 | (REGNO (reloadreg) + |
6280 | subreg_regno_offset (REGNO (SUBREG_REG (*loc)), | |
6281 | GET_MODE (SUBREG_REG (*loc)), | |
6282 | SUBREG_BYTE (*loc), | |
6283 | GET_MODE (*loc)))); | |
af929c62 RK |
6284 | else if (GET_MODE (reloadreg) == GET_MODE (*loc)) |
6285 | return reloadreg; | |
6286 | else | |
ddef6bc7 JJ |
6287 | { |
6288 | int final_offset = SUBREG_BYTE (reloadreg) + SUBREG_BYTE (*loc); | |
6289 | ||
6290 | /* When working with SUBREGs the rule is that the byte | |
6291 | offset must be a multiple of the SUBREG's mode. */ | |
6292 | final_offset = (final_offset / GET_MODE_SIZE (GET_MODE (*loc))); | |
6293 | final_offset = (final_offset * GET_MODE_SIZE (GET_MODE (*loc))); | |
6294 | return gen_rtx_SUBREG (GET_MODE (*loc), SUBREG_REG (reloadreg), | |
6295 | final_offset); | |
6296 | } | |
af929c62 RK |
6297 | } |
6298 | } | |
6299 | ||
956d6950 JL |
6300 | /* If *LOC is a PLUS, MINUS, or MULT, see if a replacement is scheduled for |
6301 | what's inside and make a new rtl if so. */ | |
6302 | if (GET_CODE (*loc) == PLUS || GET_CODE (*loc) == MINUS | |
6303 | || GET_CODE (*loc) == MULT) | |
6304 | { | |
6305 | rtx x = find_replacement (&XEXP (*loc, 0)); | |
6306 | rtx y = find_replacement (&XEXP (*loc, 1)); | |
6307 | ||
6308 | if (x != XEXP (*loc, 0) || y != XEXP (*loc, 1)) | |
38a448ca | 6309 | return gen_rtx_fmt_ee (GET_CODE (*loc), GET_MODE (*loc), x, y); |
956d6950 JL |
6310 | } |
6311 | ||
af929c62 RK |
6312 | return *loc; |
6313 | } | |
6314 | \f | |
eab89b90 RK |
6315 | /* Return nonzero if register in range [REGNO, ENDREGNO) |
6316 | appears either explicitly or implicitly in X | |
4644aad4 | 6317 | other than being stored into (except for earlyclobber operands). |
eab89b90 RK |
6318 | |
6319 | References contained within the substructure at LOC do not count. | |
6320 | LOC may be zero, meaning don't ignore anything. | |
6321 | ||
6322 | This is similar to refers_to_regno_p in rtlanal.c except that we | |
6323 | look at equivalences for pseudos that didn't get hard registers. */ | |
6324 | ||
10015a27 | 6325 | static int |
0c20a65f AJ |
6326 | refers_to_regno_for_reload_p (unsigned int regno, unsigned int endregno, |
6327 | rtx x, rtx *loc) | |
eab89b90 | 6328 | { |
770ae6cc RK |
6329 | int i; |
6330 | unsigned int r; | |
6331 | RTX_CODE code; | |
6332 | const char *fmt; | |
eab89b90 RK |
6333 | |
6334 | if (x == 0) | |
6335 | return 0; | |
6336 | ||
6337 | repeat: | |
6338 | code = GET_CODE (x); | |
6339 | ||
6340 | switch (code) | |
6341 | { | |
6342 | case REG: | |
770ae6cc | 6343 | r = REGNO (x); |
eab89b90 | 6344 | |
4803a34a RK |
6345 | /* If this is a pseudo, a hard register must not have been allocated. |
6346 | X must therefore either be a constant or be in memory. */ | |
770ae6cc | 6347 | if (r >= FIRST_PSEUDO_REGISTER) |
4803a34a | 6348 | { |
770ae6cc | 6349 | if (reg_equiv_memory_loc[r]) |
4803a34a | 6350 | return refers_to_regno_for_reload_p (regno, endregno, |
770ae6cc | 6351 | reg_equiv_memory_loc[r], |
f4f4d0f8 | 6352 | (rtx*) 0); |
4803a34a | 6353 | |
444aea52 | 6354 | gcc_assert (reg_equiv_constant[r] || reg_equiv_invariant[r]); |
41374e13 | 6355 | return 0; |
4803a34a | 6356 | } |
eab89b90 | 6357 | |
770ae6cc RK |
6358 | return (endregno > r |
6359 | && regno < r + (r < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 6360 | ? hard_regno_nregs[r][GET_MODE (x)] |
eab89b90 RK |
6361 | : 1)); |
6362 | ||
6363 | case SUBREG: | |
6364 | /* If this is a SUBREG of a hard reg, we can see exactly which | |
6365 | registers are being modified. Otherwise, handle normally. */ | |
f8cfc6aa | 6366 | if (REG_P (SUBREG_REG (x)) |
eab89b90 RK |
6367 | && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) |
6368 | { | |
ddef6bc7 | 6369 | unsigned int inner_regno = subreg_regno (x); |
770ae6cc | 6370 | unsigned int inner_endregno |
403c659c | 6371 | = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER |
f1f4e530 | 6372 | ? subreg_nregs (x) : 1); |
eab89b90 RK |
6373 | |
6374 | return endregno > inner_regno && regno < inner_endregno; | |
6375 | } | |
6376 | break; | |
6377 | ||
6378 | case CLOBBER: | |
6379 | case SET: | |
6380 | if (&SET_DEST (x) != loc | |
6381 | /* Note setting a SUBREG counts as referring to the REG it is in for | |
6382 | a pseudo but not for hard registers since we can | |
6383 | treat each word individually. */ | |
6384 | && ((GET_CODE (SET_DEST (x)) == SUBREG | |
6385 | && loc != &SUBREG_REG (SET_DEST (x)) | |
f8cfc6aa | 6386 | && REG_P (SUBREG_REG (SET_DEST (x))) |
eab89b90 RK |
6387 | && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER |
6388 | && refers_to_regno_for_reload_p (regno, endregno, | |
6389 | SUBREG_REG (SET_DEST (x)), | |
6390 | loc)) | |
abc95ed3 | 6391 | /* If the output is an earlyclobber operand, this is |
4644aad4 | 6392 | a conflict. */ |
f8cfc6aa | 6393 | || ((!REG_P (SET_DEST (x)) |
4644aad4 | 6394 | || earlyclobber_operand_p (SET_DEST (x))) |
eab89b90 RK |
6395 | && refers_to_regno_for_reload_p (regno, endregno, |
6396 | SET_DEST (x), loc)))) | |
6397 | return 1; | |
6398 | ||
6399 | if (code == CLOBBER || loc == &SET_SRC (x)) | |
6400 | return 0; | |
6401 | x = SET_SRC (x); | |
6402 | goto repeat; | |
05d10675 | 6403 | |
e9a25f70 JL |
6404 | default: |
6405 | break; | |
eab89b90 RK |
6406 | } |
6407 | ||
6408 | /* X does not match, so try its subexpressions. */ | |
6409 | ||
6410 | fmt = GET_RTX_FORMAT (code); | |
6411 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6412 | { | |
6413 | if (fmt[i] == 'e' && loc != &XEXP (x, i)) | |
6414 | { | |
6415 | if (i == 0) | |
6416 | { | |
6417 | x = XEXP (x, 0); | |
6418 | goto repeat; | |
6419 | } | |
6420 | else | |
6421 | if (refers_to_regno_for_reload_p (regno, endregno, | |
6422 | XEXP (x, i), loc)) | |
6423 | return 1; | |
6424 | } | |
6425 | else if (fmt[i] == 'E') | |
6426 | { | |
b3694847 | 6427 | int j; |
4381f7c2 | 6428 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
eab89b90 RK |
6429 | if (loc != &XVECEXP (x, i, j) |
6430 | && refers_to_regno_for_reload_p (regno, endregno, | |
6431 | XVECEXP (x, i, j), loc)) | |
6432 | return 1; | |
6433 | } | |
6434 | } | |
6435 | return 0; | |
6436 | } | |
bfa30b22 RK |
6437 | |
6438 | /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG, | |
6439 | we check if any register number in X conflicts with the relevant register | |
6440 | numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN | |
6441 | contains a MEM (we don't bother checking for memory addresses that can't | |
05d10675 | 6442 | conflict because we expect this to be a rare case. |
bfa30b22 | 6443 | |
e0120d6e | 6444 | This function is similar to reg_overlap_mentioned_p in rtlanal.c except |
bfa30b22 RK |
6445 | that we look at equivalences for pseudos that didn't get hard registers. */ |
6446 | ||
6447 | int | |
0c20a65f | 6448 | reg_overlap_mentioned_for_reload_p (rtx x, rtx in) |
bfa30b22 RK |
6449 | { |
6450 | int regno, endregno; | |
6451 | ||
b98b49ac | 6452 | /* Overly conservative. */ |
38979c65 | 6453 | if (GET_CODE (x) == STRICT_LOW_PART |
ec8e098d | 6454 | || GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC) |
b98b49ac JL |
6455 | x = XEXP (x, 0); |
6456 | ||
6457 | /* If either argument is a constant, then modifying X can not affect IN. */ | |
6458 | if (CONSTANT_P (x) || CONSTANT_P (in)) | |
6459 | return 0; | |
838f78d6 DD |
6460 | else if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM) |
6461 | return refers_to_mem_for_reload_p (in); | |
b98b49ac | 6462 | else if (GET_CODE (x) == SUBREG) |
bfa30b22 RK |
6463 | { |
6464 | regno = REGNO (SUBREG_REG (x)); | |
6465 | if (regno < FIRST_PSEUDO_REGISTER) | |
ddef6bc7 JJ |
6466 | regno += subreg_regno_offset (REGNO (SUBREG_REG (x)), |
6467 | GET_MODE (SUBREG_REG (x)), | |
6468 | SUBREG_BYTE (x), | |
6469 | GET_MODE (x)); | |
f1f4e530 JM |
6470 | endregno = regno + (regno < FIRST_PSEUDO_REGISTER |
6471 | ? subreg_nregs (x) : 1); | |
6472 | ||
6473 | return refers_to_regno_for_reload_p (regno, endregno, in, (rtx*) 0); | |
bfa30b22 | 6474 | } |
f8cfc6aa | 6475 | else if (REG_P (x)) |
bfa30b22 RK |
6476 | { |
6477 | regno = REGNO (x); | |
4803a34a RK |
6478 | |
6479 | /* If this is a pseudo, it must not have been assigned a hard register. | |
6480 | Therefore, it must either be in memory or be a constant. */ | |
6481 | ||
6482 | if (regno >= FIRST_PSEUDO_REGISTER) | |
6483 | { | |
6484 | if (reg_equiv_memory_loc[regno]) | |
6485 | return refers_to_mem_for_reload_p (in); | |
41374e13 NS |
6486 | gcc_assert (reg_equiv_constant[regno]); |
6487 | return 0; | |
4803a34a | 6488 | } |
f1f4e530 | 6489 | |
09e18274 | 6490 | endregno = END_HARD_REGNO (x); |
f1f4e530 JM |
6491 | |
6492 | return refers_to_regno_for_reload_p (regno, endregno, in, (rtx*) 0); | |
bfa30b22 | 6493 | } |
3c0cb5de | 6494 | else if (MEM_P (x)) |
4803a34a | 6495 | return refers_to_mem_for_reload_p (in); |
bfa30b22 RK |
6496 | else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC |
6497 | || GET_CODE (x) == CC0) | |
6498 | return reg_mentioned_p (x, in); | |
41374e13 | 6499 | else |
69f38ab9 | 6500 | { |
41374e13 NS |
6501 | gcc_assert (GET_CODE (x) == PLUS); |
6502 | ||
69f38ab9 R |
6503 | /* We actually want to know if X is mentioned somewhere inside IN. |
6504 | We must not say that (plus (sp) (const_int 124)) is in | |
6505 | (plus (sp) (const_int 64)), since that can lead to incorrect reload | |
6506 | allocation when spuriously changing a RELOAD_FOR_OUTPUT_ADDRESS | |
6507 | into a RELOAD_OTHER on behalf of another RELOAD_OTHER. */ | |
3c0cb5de | 6508 | while (MEM_P (in)) |
69f38ab9 | 6509 | in = XEXP (in, 0); |
f8cfc6aa | 6510 | if (REG_P (in)) |
69f38ab9 R |
6511 | return 0; |
6512 | else if (GET_CODE (in) == PLUS) | |
10050f74 KK |
6513 | return (rtx_equal_p (x, in) |
6514 | || reg_overlap_mentioned_for_reload_p (x, XEXP (in, 0)) | |
69f38ab9 R |
6515 | || reg_overlap_mentioned_for_reload_p (x, XEXP (in, 1))); |
6516 | else return (reg_overlap_mentioned_for_reload_p (XEXP (x, 0), in) | |
6517 | || reg_overlap_mentioned_for_reload_p (XEXP (x, 1), in)); | |
6518 | } | |
bfa30b22 | 6519 | |
f1f4e530 | 6520 | gcc_unreachable (); |
bfa30b22 | 6521 | } |
4803a34a RK |
6522 | |
6523 | /* Return nonzero if anything in X contains a MEM. Look also for pseudo | |
6524 | registers. */ | |
6525 | ||
10015a27 | 6526 | static int |
0c20a65f | 6527 | refers_to_mem_for_reload_p (rtx x) |
4803a34a | 6528 | { |
6f7d635c | 6529 | const char *fmt; |
4803a34a RK |
6530 | int i; |
6531 | ||
3c0cb5de | 6532 | if (MEM_P (x)) |
4803a34a RK |
6533 | return 1; |
6534 | ||
f8cfc6aa | 6535 | if (REG_P (x)) |
4803a34a RK |
6536 | return (REGNO (x) >= FIRST_PSEUDO_REGISTER |
6537 | && reg_equiv_memory_loc[REGNO (x)]); | |
05d10675 | 6538 | |
4803a34a RK |
6539 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
6540 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
6541 | if (fmt[i] == 'e' | |
3c0cb5de | 6542 | && (MEM_P (XEXP (x, i)) |
4803a34a RK |
6543 | || refers_to_mem_for_reload_p (XEXP (x, i)))) |
6544 | return 1; | |
05d10675 | 6545 | |
4803a34a RK |
6546 | return 0; |
6547 | } | |
eab89b90 | 6548 | \f |
eab89b90 RK |
6549 | /* Check the insns before INSN to see if there is a suitable register |
6550 | containing the same value as GOAL. | |
6551 | If OTHER is -1, look for a register in class CLASS. | |
6552 | Otherwise, just see if register number OTHER shares GOAL's value. | |
6553 | ||
6554 | Return an rtx for the register found, or zero if none is found. | |
6555 | ||
6556 | If RELOAD_REG_P is (short *)1, | |
6557 | we reject any hard reg that appears in reload_reg_rtx | |
6558 | because such a hard reg is also needed coming into this insn. | |
6559 | ||
6560 | If RELOAD_REG_P is any other nonzero value, | |
6561 | it is a vector indexed by hard reg number | |
6562 | and we reject any hard reg whose element in the vector is nonnegative | |
6563 | as well as any that appears in reload_reg_rtx. | |
6564 | ||
6565 | If GOAL is zero, then GOALREG is a register number; we look | |
6566 | for an equivalent for that register. | |
6567 | ||
6568 | MODE is the machine mode of the value we want an equivalence for. | |
6569 | If GOAL is nonzero and not VOIDmode, then it must have mode MODE. | |
6570 | ||
6571 | This function is used by jump.c as well as in the reload pass. | |
6572 | ||
6573 | If GOAL is the sum of the stack pointer and a constant, we treat it | |
6574 | as if it were a constant except that sp is required to be unchanging. */ | |
6575 | ||
6576 | rtx | |
0c20a65f AJ |
6577 | find_equiv_reg (rtx goal, rtx insn, enum reg_class class, int other, |
6578 | short *reload_reg_p, int goalreg, enum machine_mode mode) | |
eab89b90 | 6579 | { |
b3694847 | 6580 | rtx p = insn; |
f55b1d97 | 6581 | rtx goaltry, valtry, value, where; |
b3694847 SS |
6582 | rtx pat; |
6583 | int regno = -1; | |
eab89b90 RK |
6584 | int valueno; |
6585 | int goal_mem = 0; | |
6586 | int goal_const = 0; | |
6587 | int goal_mem_addr_varies = 0; | |
6588 | int need_stable_sp = 0; | |
6589 | int nregs; | |
6590 | int valuenregs; | |
0bcf8261 | 6591 | int num = 0; |
eab89b90 RK |
6592 | |
6593 | if (goal == 0) | |
6594 | regno = goalreg; | |
f8cfc6aa | 6595 | else if (REG_P (goal)) |
eab89b90 | 6596 | regno = REGNO (goal); |
3c0cb5de | 6597 | else if (MEM_P (goal)) |
eab89b90 RK |
6598 | { |
6599 | enum rtx_code code = GET_CODE (XEXP (goal, 0)); | |
6600 | if (MEM_VOLATILE_P (goal)) | |
6601 | return 0; | |
3d8bf70f | 6602 | if (flag_float_store && SCALAR_FLOAT_MODE_P (GET_MODE (goal))) |
eab89b90 RK |
6603 | return 0; |
6604 | /* An address with side effects must be reexecuted. */ | |
6605 | switch (code) | |
6606 | { | |
6607 | case POST_INC: | |
6608 | case PRE_INC: | |
6609 | case POST_DEC: | |
6610 | case PRE_DEC: | |
4b983fdc RH |
6611 | case POST_MODIFY: |
6612 | case PRE_MODIFY: | |
eab89b90 | 6613 | return 0; |
e9a25f70 JL |
6614 | default: |
6615 | break; | |
eab89b90 RK |
6616 | } |
6617 | goal_mem = 1; | |
6618 | } | |
6619 | else if (CONSTANT_P (goal)) | |
6620 | goal_const = 1; | |
6621 | else if (GET_CODE (goal) == PLUS | |
6622 | && XEXP (goal, 0) == stack_pointer_rtx | |
6623 | && CONSTANT_P (XEXP (goal, 1))) | |
6624 | goal_const = need_stable_sp = 1; | |
812f2051 R |
6625 | else if (GET_CODE (goal) == PLUS |
6626 | && XEXP (goal, 0) == frame_pointer_rtx | |
6627 | && CONSTANT_P (XEXP (goal, 1))) | |
6628 | goal_const = 1; | |
eab89b90 RK |
6629 | else |
6630 | return 0; | |
6631 | ||
0bcf8261 | 6632 | num = 0; |
eab89b90 RK |
6633 | /* Scan insns back from INSN, looking for one that copies |
6634 | a value into or out of GOAL. | |
6635 | Stop and give up if we reach a label. */ | |
6636 | ||
6637 | while (1) | |
6638 | { | |
6639 | p = PREV_INSN (p); | |
0bcf8261 | 6640 | num++; |
4b4bf941 | 6641 | if (p == 0 || LABEL_P (p) |
0bcf8261 | 6642 | || num > PARAM_VALUE (PARAM_MAX_RELOAD_SEARCH_INSNS)) |
eab89b90 | 6643 | return 0; |
770ae6cc | 6644 | |
4b4bf941 | 6645 | if (NONJUMP_INSN_P (p) |
0f41302f | 6646 | /* If we don't want spill regs ... */ |
a8c9daeb RK |
6647 | && (! (reload_reg_p != 0 |
6648 | && reload_reg_p != (short *) (HOST_WIDE_INT) 1) | |
770ae6cc RK |
6649 | /* ... then ignore insns introduced by reload; they aren't |
6650 | useful and can cause results in reload_as_needed to be | |
6651 | different from what they were when calculating the need for | |
6652 | spills. If we notice an input-reload insn here, we will | |
6653 | reject it below, but it might hide a usable equivalent. | |
0e61db61 | 6654 | That makes bad code. It may even fail: perhaps no reg was |
770ae6cc RK |
6655 | spilled for this insn because it was assumed we would find |
6656 | that equivalent. */ | |
eab89b90 RK |
6657 | || INSN_UID (p) < reload_first_uid)) |
6658 | { | |
e8094962 | 6659 | rtx tem; |
eab89b90 | 6660 | pat = single_set (p); |
770ae6cc | 6661 | |
eab89b90 RK |
6662 | /* First check for something that sets some reg equal to GOAL. */ |
6663 | if (pat != 0 | |
6664 | && ((regno >= 0 | |
6665 | && true_regnum (SET_SRC (pat)) == regno | |
6666 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
6667 | || | |
6668 | (regno >= 0 | |
6669 | && true_regnum (SET_DEST (pat)) == regno | |
6670 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0) | |
6671 | || | |
6672 | (goal_const && rtx_equal_p (SET_SRC (pat), goal) | |
a5546290 R |
6673 | /* When looking for stack pointer + const, |
6674 | make sure we don't use a stack adjust. */ | |
6675 | && !reg_overlap_mentioned_for_reload_p (SET_DEST (pat), goal) | |
eab89b90 RK |
6676 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) |
6677 | || (goal_mem | |
6678 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0 | |
6679 | && rtx_renumbered_equal_p (goal, SET_SRC (pat))) | |
6680 | || (goal_mem | |
6681 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0 | |
e8094962 RK |
6682 | && rtx_renumbered_equal_p (goal, SET_DEST (pat))) |
6683 | /* If we are looking for a constant, | |
6684 | and something equivalent to that constant was copied | |
6685 | into a reg, we can use that reg. */ | |
efc9bd41 RK |
6686 | || (goal_const && REG_NOTES (p) != 0 |
6687 | && (tem = find_reg_note (p, REG_EQUIV, NULL_RTX)) | |
6688 | && ((rtx_equal_p (XEXP (tem, 0), goal) | |
6689 | && (valueno | |
6690 | = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
f8cfc6aa | 6691 | || (REG_P (SET_DEST (pat)) |
efc9bd41 | 6692 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE |
3d8bf70f | 6693 | && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0))) |
efc9bd41 RK |
6694 | && GET_CODE (goal) == CONST_INT |
6695 | && 0 != (goaltry | |
6696 | = operand_subword (XEXP (tem, 0), 0, 0, | |
f55b1d97 | 6697 | VOIDmode)) |
efc9bd41 RK |
6698 | && rtx_equal_p (goal, goaltry) |
6699 | && (valtry | |
6700 | = operand_subword (SET_DEST (pat), 0, 0, | |
6701 | VOIDmode)) | |
6702 | && (valueno = true_regnum (valtry)) >= 0))) | |
fb3821f7 CH |
6703 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
6704 | NULL_RTX)) | |
f8cfc6aa | 6705 | && REG_P (SET_DEST (pat)) |
e8094962 | 6706 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE |
3d8bf70f | 6707 | && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0))) |
e8094962 | 6708 | && GET_CODE (goal) == CONST_INT |
f55b1d97 RK |
6709 | && 0 != (goaltry = operand_subword (XEXP (tem, 0), 1, 0, |
6710 | VOIDmode)) | |
6711 | && rtx_equal_p (goal, goaltry) | |
e8094962 RK |
6712 | && (valtry |
6713 | = operand_subword (SET_DEST (pat), 1, 0, VOIDmode)) | |
95d3562b | 6714 | && (valueno = true_regnum (valtry)) >= 0))) |
0192d704 R |
6715 | { |
6716 | if (other >= 0) | |
6717 | { | |
6718 | if (valueno != other) | |
6719 | continue; | |
6720 | } | |
6721 | else if ((unsigned) valueno >= FIRST_PSEUDO_REGISTER) | |
6722 | continue; | |
09e18274 RS |
6723 | else if (!in_hard_reg_set_p (reg_class_contents[(int) class], |
6724 | mode, valueno)) | |
6725 | continue; | |
0192d704 R |
6726 | value = valtry; |
6727 | where = p; | |
6728 | break; | |
6729 | } | |
eab89b90 RK |
6730 | } |
6731 | } | |
6732 | ||
6733 | /* We found a previous insn copying GOAL into a suitable other reg VALUE | |
6734 | (or copying VALUE into GOAL, if GOAL is also a register). | |
6735 | Now verify that VALUE is really valid. */ | |
6736 | ||
6737 | /* VALUENO is the register number of VALUE; a hard register. */ | |
6738 | ||
6739 | /* Don't try to re-use something that is killed in this insn. We want | |
6740 | to be able to trust REG_UNUSED notes. */ | |
efc9bd41 | 6741 | if (REG_NOTES (where) != 0 && find_reg_note (where, REG_UNUSED, value)) |
eab89b90 RK |
6742 | return 0; |
6743 | ||
6744 | /* If we propose to get the value from the stack pointer or if GOAL is | |
6745 | a MEM based on the stack pointer, we need a stable SP. */ | |
d5a1d1c7 | 6746 | if (valueno == STACK_POINTER_REGNUM || regno == STACK_POINTER_REGNUM |
bfa30b22 RK |
6747 | || (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx, |
6748 | goal))) | |
eab89b90 RK |
6749 | need_stable_sp = 1; |
6750 | ||
6751 | /* Reject VALUE if the copy-insn moved the wrong sort of datum. */ | |
6752 | if (GET_MODE (value) != mode) | |
6753 | return 0; | |
6754 | ||
6755 | /* Reject VALUE if it was loaded from GOAL | |
6756 | and is also a register that appears in the address of GOAL. */ | |
6757 | ||
bd5f6d44 | 6758 | if (goal_mem && value == SET_DEST (single_set (where)) |
09e18274 | 6759 | && refers_to_regno_for_reload_p (valueno, end_hard_regno (mode, valueno), |
f4f4d0f8 | 6760 | goal, (rtx*) 0)) |
eab89b90 RK |
6761 | return 0; |
6762 | ||
6763 | /* Reject registers that overlap GOAL. */ | |
6764 | ||
66fd46b6 JH |
6765 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER) |
6766 | nregs = hard_regno_nregs[regno][mode]; | |
6767 | else | |
6768 | nregs = 1; | |
6769 | valuenregs = hard_regno_nregs[valueno][mode]; | |
16ab191f | 6770 | |
3c241c19 GK |
6771 | if (!goal_mem && !goal_const |
6772 | && regno + nregs > valueno && regno < valueno + valuenregs) | |
6773 | return 0; | |
6774 | ||
eab89b90 RK |
6775 | /* Reject VALUE if it is one of the regs reserved for reloads. |
6776 | Reload1 knows how to reuse them anyway, and it would get | |
6777 | confused if we allocated one without its knowledge. | |
6778 | (Now that insns introduced by reload are ignored above, | |
6779 | this case shouldn't happen, but I'm not positive.) */ | |
6780 | ||
16ab191f DC |
6781 | if (reload_reg_p != 0 && reload_reg_p != (short *) (HOST_WIDE_INT) 1) |
6782 | { | |
6783 | int i; | |
6784 | for (i = 0; i < valuenregs; ++i) | |
6785 | if (reload_reg_p[valueno + i] >= 0) | |
6786 | return 0; | |
6787 | } | |
eab89b90 RK |
6788 | |
6789 | /* Reject VALUE if it is a register being used for an input reload | |
6790 | even if it is not one of those reserved. */ | |
6791 | ||
6792 | if (reload_reg_p != 0) | |
6793 | { | |
6794 | int i; | |
6795 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 6796 | if (rld[i].reg_rtx != 0 && rld[i].in) |
eab89b90 | 6797 | { |
eceef4c9 | 6798 | int regno1 = REGNO (rld[i].reg_rtx); |
66fd46b6 JH |
6799 | int nregs1 = hard_regno_nregs[regno1] |
6800 | [GET_MODE (rld[i].reg_rtx)]; | |
eab89b90 RK |
6801 | if (regno1 < valueno + valuenregs |
6802 | && regno1 + nregs1 > valueno) | |
6803 | return 0; | |
6804 | } | |
6805 | } | |
6806 | ||
6807 | if (goal_mem) | |
54b5ffe9 RS |
6808 | /* We must treat frame pointer as varying here, |
6809 | since it can vary--in a nonlocal goto as generated by expand_goto. */ | |
6810 | goal_mem_addr_varies = !CONSTANT_ADDRESS_P (XEXP (goal, 0)); | |
eab89b90 RK |
6811 | |
6812 | /* Now verify that the values of GOAL and VALUE remain unaltered | |
6813 | until INSN is reached. */ | |
6814 | ||
6815 | p = insn; | |
6816 | while (1) | |
6817 | { | |
6818 | p = PREV_INSN (p); | |
6819 | if (p == where) | |
6820 | return value; | |
6821 | ||
6822 | /* Don't trust the conversion past a function call | |
6823 | if either of the two is in a call-clobbered register, or memory. */ | |
4b4bf941 | 6824 | if (CALL_P (p)) |
aad2919f DC |
6825 | { |
6826 | int i; | |
4381f7c2 | 6827 | |
aad2919f DC |
6828 | if (goal_mem || need_stable_sp) |
6829 | return 0; | |
4381f7c2 | 6830 | |
aad2919f DC |
6831 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER) |
6832 | for (i = 0; i < nregs; ++i) | |
7e42db17 DJ |
6833 | if (call_used_regs[regno + i] |
6834 | || HARD_REGNO_CALL_PART_CLOBBERED (regno + i, mode)) | |
aad2919f DC |
6835 | return 0; |
6836 | ||
6837 | if (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER) | |
6838 | for (i = 0; i < valuenregs; ++i) | |
7e42db17 DJ |
6839 | if (call_used_regs[valueno + i] |
6840 | || HARD_REGNO_CALL_PART_CLOBBERED (valueno + i, mode)) | |
aad2919f | 6841 | return 0; |
570a98eb | 6842 | } |
41fe17ab | 6843 | |
2c3c49de | 6844 | if (INSN_P (p)) |
eab89b90 | 6845 | { |
8ec82f87 RH |
6846 | pat = PATTERN (p); |
6847 | ||
05d10675 BS |
6848 | /* Watch out for unspec_volatile, and volatile asms. */ |
6849 | if (volatile_insn_p (pat)) | |
8ec82f87 RH |
6850 | return 0; |
6851 | ||
eab89b90 RK |
6852 | /* If this insn P stores in either GOAL or VALUE, return 0. |
6853 | If GOAL is a memory ref and this insn writes memory, return 0. | |
6854 | If GOAL is a memory ref and its address is not constant, | |
6855 | and this insn P changes a register used in GOAL, return 0. */ | |
6856 | ||
0c99ec5c RH |
6857 | if (GET_CODE (pat) == COND_EXEC) |
6858 | pat = COND_EXEC_CODE (pat); | |
eab89b90 RK |
6859 | if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER) |
6860 | { | |
b3694847 | 6861 | rtx dest = SET_DEST (pat); |
eab89b90 RK |
6862 | while (GET_CODE (dest) == SUBREG |
6863 | || GET_CODE (dest) == ZERO_EXTRACT | |
eab89b90 RK |
6864 | || GET_CODE (dest) == STRICT_LOW_PART) |
6865 | dest = XEXP (dest, 0); | |
f8cfc6aa | 6866 | if (REG_P (dest)) |
eab89b90 | 6867 | { |
b3694847 | 6868 | int xregno = REGNO (dest); |
eab89b90 RK |
6869 | int xnregs; |
6870 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
66fd46b6 | 6871 | xnregs = hard_regno_nregs[xregno][GET_MODE (dest)]; |
eab89b90 RK |
6872 | else |
6873 | xnregs = 1; | |
6874 | if (xregno < regno + nregs && xregno + xnregs > regno) | |
6875 | return 0; | |
6876 | if (xregno < valueno + valuenregs | |
6877 | && xregno + xnregs > valueno) | |
6878 | return 0; | |
6879 | if (goal_mem_addr_varies | |
bfa30b22 | 6880 | && reg_overlap_mentioned_for_reload_p (dest, goal)) |
eab89b90 | 6881 | return 0; |
1b4d8b2b R |
6882 | if (xregno == STACK_POINTER_REGNUM && need_stable_sp) |
6883 | return 0; | |
eab89b90 | 6884 | } |
3c0cb5de | 6885 | else if (goal_mem && MEM_P (dest) |
eab89b90 RK |
6886 | && ! push_operand (dest, GET_MODE (dest))) |
6887 | return 0; | |
3c0cb5de | 6888 | else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER |
9fac9680 RK |
6889 | && reg_equiv_memory_loc[regno] != 0) |
6890 | return 0; | |
eab89b90 RK |
6891 | else if (need_stable_sp && push_operand (dest, GET_MODE (dest))) |
6892 | return 0; | |
6893 | } | |
6894 | else if (GET_CODE (pat) == PARALLEL) | |
6895 | { | |
b3694847 | 6896 | int i; |
eab89b90 RK |
6897 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) |
6898 | { | |
b3694847 | 6899 | rtx v1 = XVECEXP (pat, 0, i); |
0c99ec5c RH |
6900 | if (GET_CODE (v1) == COND_EXEC) |
6901 | v1 = COND_EXEC_CODE (v1); | |
eab89b90 RK |
6902 | if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER) |
6903 | { | |
b3694847 | 6904 | rtx dest = SET_DEST (v1); |
eab89b90 RK |
6905 | while (GET_CODE (dest) == SUBREG |
6906 | || GET_CODE (dest) == ZERO_EXTRACT | |
eab89b90 RK |
6907 | || GET_CODE (dest) == STRICT_LOW_PART) |
6908 | dest = XEXP (dest, 0); | |
f8cfc6aa | 6909 | if (REG_P (dest)) |
eab89b90 | 6910 | { |
b3694847 | 6911 | int xregno = REGNO (dest); |
eab89b90 RK |
6912 | int xnregs; |
6913 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
66fd46b6 | 6914 | xnregs = hard_regno_nregs[xregno][GET_MODE (dest)]; |
eab89b90 RK |
6915 | else |
6916 | xnregs = 1; | |
6917 | if (xregno < regno + nregs | |
6918 | && xregno + xnregs > regno) | |
6919 | return 0; | |
6920 | if (xregno < valueno + valuenregs | |
6921 | && xregno + xnregs > valueno) | |
6922 | return 0; | |
6923 | if (goal_mem_addr_varies | |
bfa30b22 RK |
6924 | && reg_overlap_mentioned_for_reload_p (dest, |
6925 | goal)) | |
eab89b90 | 6926 | return 0; |
930176e7 R |
6927 | if (xregno == STACK_POINTER_REGNUM && need_stable_sp) |
6928 | return 0; | |
eab89b90 | 6929 | } |
3c0cb5de | 6930 | else if (goal_mem && MEM_P (dest) |
eab89b90 RK |
6931 | && ! push_operand (dest, GET_MODE (dest))) |
6932 | return 0; | |
3c0cb5de | 6933 | else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER |
e9a25f70 JL |
6934 | && reg_equiv_memory_loc[regno] != 0) |
6935 | return 0; | |
369c7ab6 JW |
6936 | else if (need_stable_sp |
6937 | && push_operand (dest, GET_MODE (dest))) | |
6938 | return 0; | |
6939 | } | |
6940 | } | |
6941 | } | |
6942 | ||
4b4bf941 | 6943 | if (CALL_P (p) && CALL_INSN_FUNCTION_USAGE (p)) |
369c7ab6 JW |
6944 | { |
6945 | rtx link; | |
6946 | ||
6947 | for (link = CALL_INSN_FUNCTION_USAGE (p); XEXP (link, 1) != 0; | |
6948 | link = XEXP (link, 1)) | |
6949 | { | |
6950 | pat = XEXP (link, 0); | |
6951 | if (GET_CODE (pat) == CLOBBER) | |
6952 | { | |
b3694847 | 6953 | rtx dest = SET_DEST (pat); |
f8cd4126 | 6954 | |
f8cfc6aa | 6955 | if (REG_P (dest)) |
369c7ab6 | 6956 | { |
b3694847 | 6957 | int xregno = REGNO (dest); |
f8cd4126 | 6958 | int xnregs |
66fd46b6 | 6959 | = hard_regno_nregs[xregno][GET_MODE (dest)]; |
f8cd4126 | 6960 | |
369c7ab6 JW |
6961 | if (xregno < regno + nregs |
6962 | && xregno + xnregs > regno) | |
6963 | return 0; | |
f8cd4126 | 6964 | else if (xregno < valueno + valuenregs |
4381f7c2 | 6965 | && xregno + xnregs > valueno) |
369c7ab6 | 6966 | return 0; |
f8cd4126 RK |
6967 | else if (goal_mem_addr_varies |
6968 | && reg_overlap_mentioned_for_reload_p (dest, | |
369c7ab6 JW |
6969 | goal)) |
6970 | return 0; | |
6971 | } | |
f8cd4126 | 6972 | |
3c0cb5de | 6973 | else if (goal_mem && MEM_P (dest) |
369c7ab6 JW |
6974 | && ! push_operand (dest, GET_MODE (dest))) |
6975 | return 0; | |
eab89b90 RK |
6976 | else if (need_stable_sp |
6977 | && push_operand (dest, GET_MODE (dest))) | |
6978 | return 0; | |
6979 | } | |
6980 | } | |
6981 | } | |
6982 | ||
6983 | #ifdef AUTO_INC_DEC | |
6984 | /* If this insn auto-increments or auto-decrements | |
6985 | either regno or valueno, return 0 now. | |
6986 | If GOAL is a memory ref and its address is not constant, | |
6987 | and this insn P increments a register used in GOAL, return 0. */ | |
6988 | { | |
b3694847 | 6989 | rtx link; |
eab89b90 RK |
6990 | |
6991 | for (link = REG_NOTES (p); link; link = XEXP (link, 1)) | |
6992 | if (REG_NOTE_KIND (link) == REG_INC | |
f8cfc6aa | 6993 | && REG_P (XEXP (link, 0))) |
eab89b90 | 6994 | { |
b3694847 | 6995 | int incno = REGNO (XEXP (link, 0)); |
eab89b90 RK |
6996 | if (incno < regno + nregs && incno >= regno) |
6997 | return 0; | |
6998 | if (incno < valueno + valuenregs && incno >= valueno) | |
6999 | return 0; | |
7000 | if (goal_mem_addr_varies | |
bfa30b22 RK |
7001 | && reg_overlap_mentioned_for_reload_p (XEXP (link, 0), |
7002 | goal)) | |
eab89b90 RK |
7003 | return 0; |
7004 | } | |
7005 | } | |
7006 | #endif | |
7007 | } | |
7008 | } | |
7009 | } | |
7010 | \f | |
7011 | /* Find a place where INCED appears in an increment or decrement operator | |
7012 | within X, and return the amount INCED is incremented or decremented by. | |
7013 | The value is always positive. */ | |
7014 | ||
7015 | static int | |
0c20a65f | 7016 | find_inc_amount (rtx x, rtx inced) |
eab89b90 | 7017 | { |
b3694847 SS |
7018 | enum rtx_code code = GET_CODE (x); |
7019 | const char *fmt; | |
7020 | int i; | |
eab89b90 RK |
7021 | |
7022 | if (code == MEM) | |
7023 | { | |
b3694847 | 7024 | rtx addr = XEXP (x, 0); |
eab89b90 RK |
7025 | if ((GET_CODE (addr) == PRE_DEC |
7026 | || GET_CODE (addr) == POST_DEC | |
7027 | || GET_CODE (addr) == PRE_INC | |
7028 | || GET_CODE (addr) == POST_INC) | |
7029 | && XEXP (addr, 0) == inced) | |
7030 | return GET_MODE_SIZE (GET_MODE (x)); | |
4b983fdc RH |
7031 | else if ((GET_CODE (addr) == PRE_MODIFY |
7032 | || GET_CODE (addr) == POST_MODIFY) | |
7033 | && GET_CODE (XEXP (addr, 1)) == PLUS | |
7034 | && XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0) | |
7035 | && XEXP (addr, 0) == inced | |
7036 | && GET_CODE (XEXP (XEXP (addr, 1), 1)) == CONST_INT) | |
4381f7c2 KH |
7037 | { |
7038 | i = INTVAL (XEXP (XEXP (addr, 1), 1)); | |
7039 | return i < 0 ? -i : i; | |
7040 | } | |
7041 | } | |
eab89b90 RK |
7042 | |
7043 | fmt = GET_RTX_FORMAT (code); | |
7044 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7045 | { | |
7046 | if (fmt[i] == 'e') | |
7047 | { | |
b3694847 | 7048 | int tem = find_inc_amount (XEXP (x, i), inced); |
eab89b90 RK |
7049 | if (tem != 0) |
7050 | return tem; | |
7051 | } | |
7052 | if (fmt[i] == 'E') | |
7053 | { | |
b3694847 | 7054 | int j; |
eab89b90 RK |
7055 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
7056 | { | |
b3694847 | 7057 | int tem = find_inc_amount (XVECEXP (x, i, j), inced); |
eab89b90 RK |
7058 | if (tem != 0) |
7059 | return tem; | |
7060 | } | |
7061 | } | |
7062 | } | |
7063 | ||
7064 | return 0; | |
7065 | } | |
7066 | \f | |
d0236c3b DN |
7067 | /* Return 1 if registers from REGNO to ENDREGNO are the subjects of a |
7068 | REG_INC note in insn INSN. REGNO must refer to a hard register. */ | |
7069 | ||
7070 | #ifdef AUTO_INC_DEC | |
7071 | static int | |
7072 | reg_inc_found_and_valid_p (unsigned int regno, unsigned int endregno, | |
7073 | rtx insn) | |
7074 | { | |
7075 | rtx link; | |
7076 | ||
7077 | gcc_assert (insn); | |
7078 | ||
7079 | if (! INSN_P (insn)) | |
7080 | return 0; | |
7081 | ||
7082 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
7083 | if (REG_NOTE_KIND (link) == REG_INC) | |
7084 | { | |
7085 | unsigned int test = (int) REGNO (XEXP (link, 0)); | |
7086 | if (test >= regno && test < endregno) | |
7087 | return 1; | |
7088 | } | |
7089 | return 0; | |
7090 | } | |
7091 | #else | |
7092 | ||
7093 | #define reg_inc_found_and_valid_p(regno,endregno,insn) 0 | |
7094 | ||
7095 | #endif | |
7096 | ||
9532e31f | 7097 | /* Return 1 if register REGNO is the subject of a clobber in insn INSN. |
d0236c3b DN |
7098 | If SETS is 1, also consider SETs. If SETS is 2, enable checking |
7099 | REG_INC. REGNO must refer to a hard register. */ | |
eab89b90 RK |
7100 | |
7101 | int | |
0c20a65f AJ |
7102 | regno_clobbered_p (unsigned int regno, rtx insn, enum machine_mode mode, |
7103 | int sets) | |
eab89b90 | 7104 | { |
5b804e8a RS |
7105 | unsigned int nregs, endregno; |
7106 | ||
7107 | /* regno must be a hard register. */ | |
7108 | gcc_assert (regno < FIRST_PSEUDO_REGISTER); | |
7109 | ||
7110 | nregs = hard_regno_nregs[regno][mode]; | |
7111 | endregno = regno + nregs; | |
8441bc30 | 7112 | |
9532e31f | 7113 | if ((GET_CODE (PATTERN (insn)) == CLOBBER |
d0236c3b | 7114 | || (sets == 1 && GET_CODE (PATTERN (insn)) == SET)) |
f8cfc6aa | 7115 | && REG_P (XEXP (PATTERN (insn), 0))) |
8441bc30 | 7116 | { |
ae0ed63a | 7117 | unsigned int test = REGNO (XEXP (PATTERN (insn), 0)); |
8441bc30 | 7118 | |
e695931e | 7119 | return test >= regno && test < endregno; |
8441bc30 | 7120 | } |
eab89b90 | 7121 | |
d0236c3b DN |
7122 | if (sets == 2 && reg_inc_found_and_valid_p (regno, endregno, insn)) |
7123 | return 1; | |
7124 | ||
eab89b90 RK |
7125 | if (GET_CODE (PATTERN (insn)) == PARALLEL) |
7126 | { | |
7127 | int i = XVECLEN (PATTERN (insn), 0) - 1; | |
7128 | ||
7129 | for (; i >= 0; i--) | |
7130 | { | |
7131 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
9532e31f | 7132 | if ((GET_CODE (elt) == CLOBBER |
d0236c3b | 7133 | || (sets == 1 && GET_CODE (PATTERN (insn)) == SET)) |
f8cfc6aa | 7134 | && REG_P (XEXP (elt, 0))) |
8441bc30 | 7135 | { |
ae0ed63a | 7136 | unsigned int test = REGNO (XEXP (elt, 0)); |
a6a2274a | 7137 | |
e695931e | 7138 | if (test >= regno && test < endregno) |
8441bc30 BS |
7139 | return 1; |
7140 | } | |
d0236c3b DN |
7141 | if (sets == 2 |
7142 | && reg_inc_found_and_valid_p (regno, endregno, elt)) | |
7143 | return 1; | |
eab89b90 RK |
7144 | } |
7145 | } | |
7146 | ||
7147 | return 0; | |
7148 | } | |
10bcde0d | 7149 | |
f12448c8 AO |
7150 | /* Find the low part, with mode MODE, of a hard regno RELOADREG. */ |
7151 | rtx | |
0c20a65f | 7152 | reload_adjust_reg_for_mode (rtx reloadreg, enum machine_mode mode) |
f12448c8 AO |
7153 | { |
7154 | int regno; | |
7155 | ||
7156 | if (GET_MODE (reloadreg) == mode) | |
7157 | return reloadreg; | |
7158 | ||
7159 | regno = REGNO (reloadreg); | |
7160 | ||
7161 | if (WORDS_BIG_ENDIAN) | |
66fd46b6 JH |
7162 | regno += (int) hard_regno_nregs[regno][GET_MODE (reloadreg)] |
7163 | - (int) hard_regno_nregs[regno][mode]; | |
f12448c8 AO |
7164 | |
7165 | return gen_rtx_REG (mode, regno); | |
7166 | } | |
7167 | ||
27c38fbe | 7168 | static const char *const reload_when_needed_name[] = |
10bcde0d | 7169 | { |
05d10675 BS |
7170 | "RELOAD_FOR_INPUT", |
7171 | "RELOAD_FOR_OUTPUT", | |
10bcde0d | 7172 | "RELOAD_FOR_INSN", |
47c8cf91 ILT |
7173 | "RELOAD_FOR_INPUT_ADDRESS", |
7174 | "RELOAD_FOR_INPADDR_ADDRESS", | |
10bcde0d | 7175 | "RELOAD_FOR_OUTPUT_ADDRESS", |
47c8cf91 | 7176 | "RELOAD_FOR_OUTADDR_ADDRESS", |
05d10675 | 7177 | "RELOAD_FOR_OPERAND_ADDRESS", |
10bcde0d | 7178 | "RELOAD_FOR_OPADDR_ADDR", |
05d10675 | 7179 | "RELOAD_OTHER", |
10bcde0d RK |
7180 | "RELOAD_FOR_OTHER_ADDRESS" |
7181 | }; | |
7182 | ||
b8fb2d72 | 7183 | /* These functions are used to print the variables set by 'find_reloads' */ |
10bcde0d RK |
7184 | |
7185 | void | |
0c20a65f | 7186 | debug_reload_to_stream (FILE *f) |
10bcde0d RK |
7187 | { |
7188 | int r; | |
6f7d635c | 7189 | const char *prefix; |
10bcde0d | 7190 | |
b8fb2d72 CI |
7191 | if (! f) |
7192 | f = stderr; | |
10bcde0d RK |
7193 | for (r = 0; r < n_reloads; r++) |
7194 | { | |
b8fb2d72 | 7195 | fprintf (f, "Reload %d: ", r); |
10bcde0d | 7196 | |
eceef4c9 | 7197 | if (rld[r].in != 0) |
10bcde0d | 7198 | { |
b8fb2d72 | 7199 | fprintf (f, "reload_in (%s) = ", |
eceef4c9 BS |
7200 | GET_MODE_NAME (rld[r].inmode)); |
7201 | print_inline_rtx (f, rld[r].in, 24); | |
b8fb2d72 | 7202 | fprintf (f, "\n\t"); |
10bcde0d RK |
7203 | } |
7204 | ||
eceef4c9 | 7205 | if (rld[r].out != 0) |
10bcde0d | 7206 | { |
b8fb2d72 | 7207 | fprintf (f, "reload_out (%s) = ", |
eceef4c9 BS |
7208 | GET_MODE_NAME (rld[r].outmode)); |
7209 | print_inline_rtx (f, rld[r].out, 24); | |
b8fb2d72 | 7210 | fprintf (f, "\n\t"); |
10bcde0d RK |
7211 | } |
7212 | ||
eceef4c9 | 7213 | fprintf (f, "%s, ", reg_class_names[(int) rld[r].class]); |
10bcde0d | 7214 | |
b8fb2d72 | 7215 | fprintf (f, "%s (opnum = %d)", |
eceef4c9 BS |
7216 | reload_when_needed_name[(int) rld[r].when_needed], |
7217 | rld[r].opnum); | |
10bcde0d | 7218 | |
eceef4c9 | 7219 | if (rld[r].optional) |
b8fb2d72 | 7220 | fprintf (f, ", optional"); |
10bcde0d | 7221 | |
eceef4c9 | 7222 | if (rld[r].nongroup) |
b2ee8ec2 | 7223 | fprintf (f, ", nongroup"); |
f5963e61 | 7224 | |
eceef4c9 BS |
7225 | if (rld[r].inc != 0) |
7226 | fprintf (f, ", inc by %d", rld[r].inc); | |
10bcde0d | 7227 | |
eceef4c9 | 7228 | if (rld[r].nocombine) |
b8fb2d72 | 7229 | fprintf (f, ", can't combine"); |
10bcde0d | 7230 | |
eceef4c9 | 7231 | if (rld[r].secondary_p) |
b8fb2d72 | 7232 | fprintf (f, ", secondary_reload_p"); |
10bcde0d | 7233 | |
eceef4c9 | 7234 | if (rld[r].in_reg != 0) |
10bcde0d | 7235 | { |
b8fb2d72 | 7236 | fprintf (f, "\n\treload_in_reg: "); |
eceef4c9 | 7237 | print_inline_rtx (f, rld[r].in_reg, 24); |
10bcde0d RK |
7238 | } |
7239 | ||
eceef4c9 | 7240 | if (rld[r].out_reg != 0) |
cb2afeb3 R |
7241 | { |
7242 | fprintf (f, "\n\treload_out_reg: "); | |
eceef4c9 | 7243 | print_inline_rtx (f, rld[r].out_reg, 24); |
cb2afeb3 R |
7244 | } |
7245 | ||
eceef4c9 | 7246 | if (rld[r].reg_rtx != 0) |
10bcde0d | 7247 | { |
b8fb2d72 | 7248 | fprintf (f, "\n\treload_reg_rtx: "); |
eceef4c9 | 7249 | print_inline_rtx (f, rld[r].reg_rtx, 24); |
10bcde0d RK |
7250 | } |
7251 | ||
505923a0 | 7252 | prefix = "\n\t"; |
eceef4c9 | 7253 | if (rld[r].secondary_in_reload != -1) |
10bcde0d | 7254 | { |
b8fb2d72 | 7255 | fprintf (f, "%ssecondary_in_reload = %d", |
eceef4c9 | 7256 | prefix, rld[r].secondary_in_reload); |
505923a0 | 7257 | prefix = ", "; |
10bcde0d RK |
7258 | } |
7259 | ||
eceef4c9 | 7260 | if (rld[r].secondary_out_reload != -1) |
b8fb2d72 | 7261 | fprintf (f, "%ssecondary_out_reload = %d\n", |
eceef4c9 | 7262 | prefix, rld[r].secondary_out_reload); |
10bcde0d | 7263 | |
505923a0 | 7264 | prefix = "\n\t"; |
eceef4c9 | 7265 | if (rld[r].secondary_in_icode != CODE_FOR_nothing) |
10bcde0d | 7266 | { |
b2ee8ec2 | 7267 | fprintf (f, "%ssecondary_in_icode = %s", prefix, |
eceef4c9 | 7268 | insn_data[rld[r].secondary_in_icode].name); |
505923a0 | 7269 | prefix = ", "; |
10bcde0d RK |
7270 | } |
7271 | ||
eceef4c9 | 7272 | if (rld[r].secondary_out_icode != CODE_FOR_nothing) |
b2ee8ec2 | 7273 | fprintf (f, "%ssecondary_out_icode = %s", prefix, |
eceef4c9 | 7274 | insn_data[rld[r].secondary_out_icode].name); |
10bcde0d | 7275 | |
b8fb2d72 | 7276 | fprintf (f, "\n"); |
10bcde0d | 7277 | } |
10bcde0d | 7278 | } |
b8fb2d72 CI |
7279 | |
7280 | void | |
0c20a65f | 7281 | debug_reload (void) |
b8fb2d72 CI |
7282 | { |
7283 | debug_reload_to_stream (stderr); | |
7284 | } |