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42c63e4d | 1 | /* Search an insn for pseudo regs that must be in hard regs and are not. |
9daf6266 | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
5ae82d58 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
3072d30e | 4 | Free Software Foundation, Inc. |
42c63e4d | 5 | |
f12b58b3 | 6 | This file is part of GCC. |
42c63e4d | 7 | |
f12b58b3 | 8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 10 | Software Foundation; either version 3, or (at your option) any later |
f12b58b3 | 11 | version. |
42c63e4d | 12 | |
f12b58b3 | 13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
42c63e4d | 17 | |
18 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
42c63e4d | 21 | |
42c63e4d | 22 | /* This file contains subroutines used only from the file reload1.c. |
23 | It knows how to scan one insn for operands and values | |
24 | that need to be copied into registers to make valid code. | |
25 | It also finds other operands and values which are valid | |
26 | but for which equivalent values in registers exist and | |
27 | ought to be used instead. | |
28 | ||
29 | Before processing the first insn of the function, call `init_reload'. | |
2bc9fc53 | 30 | init_reload actually has to be called earlier anyway. |
42c63e4d | 31 | |
32 | To scan an insn, call `find_reloads'. This does two things: | |
33 | 1. sets up tables describing which values must be reloaded | |
34 | for this insn, and what kind of hard regs they must be reloaded into; | |
35 | 2. optionally record the locations where those values appear in | |
36 | the data, so they can be replaced properly later. | |
37 | This is done only if the second arg to `find_reloads' is nonzero. | |
38 | ||
39 | The third arg to `find_reloads' specifies the number of levels | |
40 | of indirect addressing supported by the machine. If it is zero, | |
41 | indirect addressing is not valid. If it is one, (MEM (REG n)) | |
42 | is valid even if (REG n) did not get a hard register; if it is two, | |
43 | (MEM (MEM (REG n))) is also valid even if (REG n) did not get a | |
44 | hard register, and similarly for higher values. | |
45 | ||
46 | Then you must choose the hard regs to reload those pseudo regs into, | |
47 | and generate appropriate load insns before this insn and perhaps | |
48 | also store insns after this insn. Set up the array `reload_reg_rtx' | |
49 | to contain the REG rtx's for the registers you used. In some | |
50 | cases `find_reloads' will return a nonzero value in `reload_reg_rtx' | |
51 | for certain reloads. Then that tells you which register to use, | |
52 | so you do not need to allocate one. But you still do need to add extra | |
53 | instructions to copy the value into and out of that register. | |
54 | ||
55 | Finally you must call `subst_reloads' to substitute the reload reg rtx's | |
56 | into the locations already recorded. | |
57 | ||
58 | NOTE SIDE EFFECTS: | |
59 | ||
60 | find_reloads can alter the operands of the instruction it is called on. | |
61 | ||
62 | 1. Two operands of any sort may be interchanged, if they are in a | |
63 | commutative instruction. | |
64 | This happens only if find_reloads thinks the instruction will compile | |
65 | better that way. | |
66 | ||
67 | 2. Pseudo-registers that are equivalent to constants are replaced | |
68 | with those constants if they are not in hard registers. | |
69 | ||
70 | 1 happens every time find_reloads is called. | |
71 | 2 happens only when REPLACE is 1, which is only when | |
72 | actually doing the reloads, not when just counting them. | |
73 | ||
42c63e4d | 74 | Using a reload register for several reloads in one insn: |
75 | ||
76 | When an insn has reloads, it is considered as having three parts: | |
77 | the input reloads, the insn itself after reloading, and the output reloads. | |
78 | Reloads of values used in memory addresses are often needed for only one part. | |
79 | ||
80 | When this is so, reload_when_needed records which part needs the reload. | |
81 | Two reloads for different parts of the insn can share the same reload | |
82 | register. | |
83 | ||
84 | When a reload is used for addresses in multiple parts, or when it is | |
85 | an ordinary operand, it is classified as RELOAD_OTHER, and cannot share | |
86 | a register with any other reload. */ | |
87 | ||
88 | #define REG_OK_STRICT | |
89 | ||
455ca9be | 90 | /* We do not enable this with ENABLE_CHECKING, since it is awfully slow. */ |
91 | #undef DEBUG_RELOAD | |
92 | ||
42c63e4d | 93 | #include "config.h" |
405711de | 94 | #include "system.h" |
805e22b2 | 95 | #include "coretypes.h" |
96 | #include "tm.h" | |
d7091a76 | 97 | #include "rtl-error.h" |
7953c610 | 98 | #include "tm_p.h" |
42c63e4d | 99 | #include "insn-config.h" |
d8fc4d0b | 100 | #include "expr.h" |
101 | #include "optabs.h" | |
42c63e4d | 102 | #include "recog.h" |
0f71a633 | 103 | #include "df.h" |
42c63e4d | 104 | #include "reload.h" |
105 | #include "regs.h" | |
00cb30dc | 106 | #include "addresses.h" |
42c63e4d | 107 | #include "hard-reg-set.h" |
108 | #include "flags.h" | |
43bdb1fa | 109 | #include "output.h" |
0a893c29 | 110 | #include "function.h" |
c15bc0ce | 111 | #include "params.h" |
3e7f6cce | 112 | #include "target.h" |
a7dcf969 | 113 | #include "ira.h" |
42c63e4d | 114 | |
7d7d7bd2 | 115 | /* True if X is a constant that can be forced into the constant pool. |
116 | MODE is the mode of the operand, or VOIDmode if not known. */ | |
117 | #define CONST_POOL_OK_P(MODE, X) \ | |
118 | ((MODE) != VOIDmode \ | |
119 | && CONSTANT_P (X) \ | |
3e7f6cce | 120 | && GET_CODE (X) != HIGH \ |
7d7d7bd2 | 121 | && !targetm.cannot_force_const_mem (MODE, X)) |
be77efb1 | 122 | |
123 | /* True if C is a non-empty register class that has too few registers | |
124 | to be safely used as a reload target class. */ | |
24dd0668 | 125 | |
126 | static inline bool | |
127 | small_register_class_p (reg_class_t rclass) | |
128 | { | |
129 | return (reg_class_size [(int) rclass] == 1 | |
130 | || (reg_class_size [(int) rclass] >= 1 | |
131 | && targetm.class_likely_spilled_p (rclass))); | |
132 | } | |
be77efb1 | 133 | |
42c63e4d | 134 | \f |
48666d2c | 135 | /* All reloads of the current insn are recorded here. See reload.h for |
136 | comments. */ | |
42c63e4d | 137 | int n_reloads; |
48666d2c | 138 | struct reload rld[MAX_RELOADS]; |
42c63e4d | 139 | |
140 | /* All the "earlyclobber" operands of the current insn | |
141 | are recorded here. */ | |
142 | int n_earlyclobbers; | |
143 | rtx reload_earlyclobbers[MAX_RECOG_OPERANDS]; | |
144 | ||
70457512 | 145 | int reload_n_operands; |
146 | ||
42c63e4d | 147 | /* Replacing reloads. |
148 | ||
149 | If `replace_reloads' is nonzero, then as each reload is recorded | |
150 | an entry is made for it in the table `replacements'. | |
151 | Then later `subst_reloads' can look through that table and | |
152 | perform all the replacements needed. */ | |
153 | ||
154 | /* Nonzero means record the places to replace. */ | |
155 | static int replace_reloads; | |
156 | ||
157 | /* Each replacement is recorded with a structure like this. */ | |
158 | struct replacement | |
159 | { | |
160 | rtx *where; /* Location to store in */ | |
42c63e4d | 161 | int what; /* which reload this is for */ |
162 | enum machine_mode mode; /* mode it must have */ | |
163 | }; | |
164 | ||
165 | static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; | |
166 | ||
167 | /* Number of replacements currently recorded. */ | |
168 | static int n_replacements; | |
169 | ||
70457512 | 170 | /* Used to track what is modified by an operand. */ |
171 | struct decomposition | |
172 | { | |
a92771b8 | 173 | int reg_flag; /* Nonzero if referencing a register. */ |
174 | int safe; /* Nonzero if this can't conflict with anything. */ | |
175 | rtx base; /* Base address for MEM. */ | |
176 | HOST_WIDE_INT start; /* Starting offset or register number. */ | |
569bf6ab | 177 | HOST_WIDE_INT end; /* Ending offset or register number. */ |
70457512 | 178 | }; |
179 | ||
c538053c | 180 | #ifdef SECONDARY_MEMORY_NEEDED |
181 | ||
182 | /* Save MEMs needed to copy from one class of registers to another. One MEM | |
5bb2f919 | 183 | is used per mode, but normally only one or two modes are ever used. |
c538053c | 184 | |
5bb2f919 | 185 | We keep two versions, before and after register elimination. The one |
70457512 | 186 | after register elimination is record separately for each operand. This |
187 | is done in case the address is not valid to be sure that we separately | |
188 | reload each. */ | |
c538053c | 189 | |
190 | static rtx secondary_memlocs[NUM_MACHINE_MODES]; | |
ac9ae2ad | 191 | static rtx secondary_memlocs_elim[NUM_MACHINE_MODES][MAX_RECOG_OPERANDS]; |
605e65d9 | 192 | static int secondary_memlocs_elim_used = 0; |
c538053c | 193 | #endif |
194 | ||
42c63e4d | 195 | /* The instruction we are doing reloads for; |
196 | so we can test whether a register dies in it. */ | |
197 | static rtx this_insn; | |
198 | ||
199 | /* Nonzero if this instruction is a user-specified asm with operands. */ | |
200 | static int this_insn_is_asm; | |
201 | ||
202 | /* If hard_regs_live_known is nonzero, | |
203 | we can tell which hard regs are currently live, | |
204 | at least enough to succeed in choosing dummy reloads. */ | |
205 | static int hard_regs_live_known; | |
206 | ||
207 | /* Indexed by hard reg number, | |
ad87de1e | 208 | element is nonnegative if hard reg has been spilled. |
42c63e4d | 209 | This vector is passed to `find_reloads' as an argument |
210 | and is not changed here. */ | |
211 | static short *static_reload_reg_p; | |
212 | ||
213 | /* Set to 1 in subst_reg_equivs if it changes anything. */ | |
214 | static int subst_reg_equivs_changed; | |
215 | ||
216 | /* On return from push_reload, holds the reload-number for the OUT | |
217 | operand, which can be different for that from the input operand. */ | |
218 | static int output_reloadnum; | |
219 | ||
7b9a997f | 220 | /* Compare two RTX's. */ |
221 | #define MATCHES(x, y) \ | |
8ad4c111 | 222 | (x == y || (x != 0 && (REG_P (x) \ |
223 | ? REG_P (y) && REGNO (x) == REGNO (y) \ | |
7b9a997f | 224 | : rtx_equal_p (x, y) && ! side_effects_p (x)))) |
225 | ||
226 | /* Indicates if two reloads purposes are for similar enough things that we | |
227 | can merge their reloads. */ | |
228 | #define MERGABLE_RELOADS(when1, when2, op1, op2) \ | |
229 | ((when1) == RELOAD_OTHER || (when2) == RELOAD_OTHER \ | |
230 | || ((when1) == (when2) && (op1) == (op2)) \ | |
231 | || ((when1) == RELOAD_FOR_INPUT && (when2) == RELOAD_FOR_INPUT) \ | |
232 | || ((when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
233 | && (when2) == RELOAD_FOR_OPERAND_ADDRESS) \ | |
234 | || ((when1) == RELOAD_FOR_OTHER_ADDRESS \ | |
235 | && (when2) == RELOAD_FOR_OTHER_ADDRESS)) | |
236 | ||
237 | /* Nonzero if these two reload purposes produce RELOAD_OTHER when merged. */ | |
238 | #define MERGE_TO_OTHER(when1, when2, op1, op2) \ | |
239 | ((when1) != (when2) \ | |
240 | || ! ((op1) == (op2) \ | |
241 | || (when1) == RELOAD_FOR_INPUT \ | |
242 | || (when1) == RELOAD_FOR_OPERAND_ADDRESS \ | |
243 | || (when1) == RELOAD_FOR_OTHER_ADDRESS)) | |
244 | ||
9e53d777 | 245 | /* If we are going to reload an address, compute the reload type to |
246 | use. */ | |
247 | #define ADDR_TYPE(type) \ | |
248 | ((type) == RELOAD_FOR_INPUT_ADDRESS \ | |
249 | ? RELOAD_FOR_INPADDR_ADDRESS \ | |
250 | : ((type) == RELOAD_FOR_OUTPUT_ADDRESS \ | |
251 | ? RELOAD_FOR_OUTADDR_ADDRESS \ | |
252 | : (type))) | |
253 | ||
3ad4992f | 254 | static int push_secondary_reload (int, rtx, int, int, enum reg_class, |
255 | enum machine_mode, enum reload_type, | |
4d58fa46 | 256 | enum insn_code *, secondary_reload_info *); |
8f3b70dd | 257 | static enum reg_class find_valid_class (enum machine_mode, enum machine_mode, |
258 | int, unsigned int); | |
3ad4992f | 259 | static void push_replacement (rtx *, int, enum machine_mode); |
260 | static void dup_replacements (rtx *, rtx *); | |
261 | static void combine_reloads (void); | |
262 | static int find_reusable_reload (rtx *, rtx, enum reg_class, | |
263 | enum reload_type, int, int); | |
264 | static rtx find_dummy_reload (rtx, rtx, rtx *, rtx *, enum machine_mode, | |
71db0d8b | 265 | enum machine_mode, reg_class_t, int, int); |
3ad4992f | 266 | static int hard_reg_set_here_p (unsigned int, unsigned int, rtx); |
267 | static struct decomposition decompose (rtx); | |
268 | static int immune_p (rtx, rtx, struct decomposition); | |
53716799 | 269 | static bool alternative_allows_const_pool_ref (rtx, const char *, int); |
3ad4992f | 270 | static rtx find_reloads_toplev (rtx, int, enum reload_type, int, int, rtx, |
271 | int *); | |
272 | static rtx make_memloc (rtx, int); | |
bd1a81f7 | 273 | static int maybe_memory_address_addr_space_p (enum machine_mode, rtx, |
274 | addr_space_t, rtx *); | |
3ad4992f | 275 | static int find_reloads_address (enum machine_mode, rtx *, rtx, rtx *, |
276 | int, enum reload_type, int, rtx); | |
277 | static rtx subst_reg_equivs (rtx, rtx); | |
278 | static rtx subst_indexed_address (rtx); | |
279 | static void update_auto_inc_notes (rtx, int, int); | |
f8a8fc7b | 280 | static int find_reloads_address_1 (enum machine_mode, addr_space_t, rtx, int, |
00cb30dc | 281 | enum rtx_code, enum rtx_code, rtx *, |
3ad4992f | 282 | int, enum reload_type,int, rtx); |
283 | static void find_reloads_address_part (rtx, rtx *, enum reg_class, | |
284 | enum machine_mode, int, | |
285 | enum reload_type, int); | |
286 | static rtx find_reloads_subreg_address (rtx, int, int, enum reload_type, | |
b5fe590a | 287 | int, rtx, int *); |
3ad4992f | 288 | static void copy_replacements_1 (rtx *, rtx *, int); |
289 | static int find_inc_amount (rtx, rtx); | |
6e707336 | 290 | static int refers_to_mem_for_reload_p (rtx); |
291 | static int refers_to_regno_for_reload_p (unsigned int, unsigned int, | |
292 | rtx, rtx *); | |
d51b37c2 | 293 | |
294 | /* Add NEW to reg_equiv_alt_mem_list[REGNO] if it's not present in the | |
295 | list yet. */ | |
296 | ||
297 | static void | |
298 | push_reg_equiv_alt_mem (int regno, rtx mem) | |
299 | { | |
300 | rtx it; | |
301 | ||
1c654ff1 | 302 | for (it = reg_equiv_alt_mem_list (regno); it; it = XEXP (it, 1)) |
d51b37c2 | 303 | if (rtx_equal_p (XEXP (it, 0), mem)) |
304 | return; | |
305 | ||
1c654ff1 | 306 | reg_equiv_alt_mem_list (regno) |
d51b37c2 | 307 | = alloc_EXPR_LIST (REG_EQUIV, mem, |
1c654ff1 | 308 | reg_equiv_alt_mem_list (regno)); |
d51b37c2 | 309 | } |
42c63e4d | 310 | \f |
42c63e4d | 311 | /* Determine if any secondary reloads are needed for loading (if IN_P is |
7fd957fe | 312 | nonzero) or storing (if IN_P is zero) X to or from a reload register of |
7b9a997f | 313 | register class RELOAD_CLASS in mode RELOAD_MODE. If secondary reloads |
314 | are needed, push them. | |
315 | ||
316 | Return the reload number of the secondary reload we made, or -1 if | |
317 | we didn't need one. *PICODE is set to the insn_code to use if we do | |
318 | need a secondary reload. */ | |
319 | ||
320 | static int | |
3ad4992f | 321 | push_secondary_reload (int in_p, rtx x, int opnum, int optional, |
322 | enum reg_class reload_class, | |
323 | enum machine_mode reload_mode, enum reload_type type, | |
4d58fa46 | 324 | enum insn_code *picode, secondary_reload_info *prev_sri) |
42c63e4d | 325 | { |
47cfb7f4 | 326 | enum reg_class rclass = NO_REGS; |
4d58fa46 | 327 | enum reg_class scratch_class; |
42c63e4d | 328 | enum machine_mode mode = reload_mode; |
329 | enum insn_code icode = CODE_FOR_nothing; | |
4196778e | 330 | enum insn_code t_icode = CODE_FOR_nothing; |
d6d6e221 | 331 | enum reload_type secondary_type; |
7b9a997f | 332 | int s_reload, t_reload = -1; |
4d58fa46 | 333 | const char *scratch_constraint; |
334 | char letter; | |
335 | secondary_reload_info sri; | |
7b9a997f | 336 | |
9e53d777 | 337 | if (type == RELOAD_FOR_INPUT_ADDRESS |
338 | || type == RELOAD_FOR_OUTPUT_ADDRESS | |
339 | || type == RELOAD_FOR_INPADDR_ADDRESS | |
340 | || type == RELOAD_FOR_OUTADDR_ADDRESS) | |
d6d6e221 | 341 | secondary_type = type; |
342 | else | |
343 | secondary_type = in_p ? RELOAD_FOR_INPUT_ADDRESS : RELOAD_FOR_OUTPUT_ADDRESS; | |
344 | ||
7b9a997f | 345 | *picode = CODE_FOR_nothing; |
42c63e4d | 346 | |
50fad108 | 347 | /* If X is a paradoxical SUBREG, use the inner value to determine both the |
348 | mode and object being reloaded. */ | |
b537bfdb | 349 | if (paradoxical_subreg_p (x)) |
50fad108 | 350 | { |
351 | x = SUBREG_REG (x); | |
352 | reload_mode = GET_MODE (x); | |
353 | } | |
354 | ||
f9e15121 | 355 | /* If X is a pseudo-register that has an equivalent MEM (actually, if it |
356 | is still a pseudo-register by now, it *must* have an equivalent MEM | |
357 | but we don't want to assume that), use that equivalent when seeing if | |
358 | a secondary reload is needed since whether or not a reload is needed | |
359 | might be sensitive to the form of the MEM. */ | |
360 | ||
8ad4c111 | 361 | if (REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER |
1c654ff1 | 362 | && reg_equiv_mem (REGNO (x))) |
363 | x = reg_equiv_mem (REGNO (x)); | |
f9e15121 | 364 | |
4d58fa46 | 365 | sri.icode = CODE_FOR_nothing; |
366 | sri.prev_sri = prev_sri; | |
964229b7 | 367 | rclass = (enum reg_class) targetm.secondary_reload (in_p, x, reload_class, |
368 | reload_mode, &sri); | |
8458f4ca | 369 | icode = (enum insn_code) sri.icode; |
42c63e4d | 370 | |
7b9a997f | 371 | /* If we don't need any secondary registers, done. */ |
47cfb7f4 | 372 | if (rclass == NO_REGS && icode == CODE_FOR_nothing) |
7b9a997f | 373 | return -1; |
42c63e4d | 374 | |
47cfb7f4 | 375 | if (rclass != NO_REGS) |
376 | t_reload = push_secondary_reload (in_p, x, opnum, optional, rclass, | |
4d58fa46 | 377 | reload_mode, type, &t_icode, &sri); |
42c63e4d | 378 | |
4d58fa46 | 379 | /* If we will be using an insn, the secondary reload is for a |
380 | scratch register. */ | |
42c63e4d | 381 | |
382 | if (icode != CODE_FOR_nothing) | |
383 | { | |
7fd957fe | 384 | /* If IN_P is nonzero, the reload register will be the output in |
42c63e4d | 385 | operand 0. If IN_P is zero, the reload register will be the input |
386 | in operand 1. Outputs should have an initial "=", which we must | |
387 | skip. */ | |
388 | ||
4d58fa46 | 389 | /* ??? It would be useful to be able to handle only two, or more than |
390 | three, operands, but for now we can only handle the case of having | |
391 | exactly three: output, input and one temp/scratch. */ | |
392 | gcc_assert (insn_data[(int) icode].n_operands == 3); | |
393 | ||
394 | /* ??? We currently have no way to represent a reload that needs | |
191ec5a2 | 395 | an icode to reload from an intermediate tertiary reload register. |
4d58fa46 | 396 | We should probably have a new field in struct reload to tag a |
397 | chain of scratch operand reloads onto. */ | |
47cfb7f4 | 398 | gcc_assert (rclass == NO_REGS); |
4d58fa46 | 399 | |
400 | scratch_constraint = insn_data[(int) icode].operand[2].constraint; | |
401 | gcc_assert (*scratch_constraint == '='); | |
402 | scratch_constraint++; | |
403 | if (*scratch_constraint == '&') | |
404 | scratch_constraint++; | |
405 | letter = *scratch_constraint; | |
406 | scratch_class = (letter == 'r' ? GENERAL_REGS | |
407 | : REG_CLASS_FROM_CONSTRAINT ((unsigned char) letter, | |
6c045f8e | 408 | scratch_constraint)); |
4d58fa46 | 409 | |
47cfb7f4 | 410 | rclass = scratch_class; |
4d58fa46 | 411 | mode = insn_data[(int) icode].operand[2].mode; |
42c63e4d | 412 | } |
413 | ||
7b9a997f | 414 | /* This case isn't valid, so fail. Reload is allowed to use the same |
415 | register for RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT reloads, but | |
416 | in the case of a secondary register, we actually need two different | |
417 | registers for correct code. We fail here to prevent the possibility of | |
418 | silently generating incorrect code later. | |
419 | ||
420 | The convention is that secondary input reloads are valid only if the | |
dc31aba7 | 421 | secondary_class is different from class. If you have such a case, you |
422 | can not use secondary reloads, you must work around the problem some | |
423 | other way. | |
7b9a997f | 424 | |
d428a20f | 425 | Allow this when a reload_in/out pattern is being used. I.e. assume |
426 | that the generated code handles this case. */ | |
7b9a997f | 427 | |
47cfb7f4 | 428 | gcc_assert (!in_p || rclass != reload_class || icode != CODE_FOR_nothing |
04e579b6 | 429 | || t_icode != CODE_FOR_nothing); |
7b9a997f | 430 | |
7b9a997f | 431 | /* See if we can reuse an existing secondary reload. */ |
432 | for (s_reload = 0; s_reload < n_reloads; s_reload++) | |
48666d2c | 433 | if (rld[s_reload].secondary_p |
c32319fc | 434 | && (reg_class_subset_p (rclass, rld[s_reload].rclass) |
435 | || reg_class_subset_p (rld[s_reload].rclass, rclass)) | |
48666d2c | 436 | && ((in_p && rld[s_reload].inmode == mode) |
437 | || (! in_p && rld[s_reload].outmode == mode)) | |
438 | && ((in_p && rld[s_reload].secondary_in_reload == t_reload) | |
439 | || (! in_p && rld[s_reload].secondary_out_reload == t_reload)) | |
440 | && ((in_p && rld[s_reload].secondary_in_icode == t_icode) | |
441 | || (! in_p && rld[s_reload].secondary_out_icode == t_icode)) | |
24dd0668 | 442 | && (small_register_class_p (rclass) |
ed5527ca | 443 | || targetm.small_register_classes_for_mode_p (VOIDmode)) |
48666d2c | 444 | && MERGABLE_RELOADS (secondary_type, rld[s_reload].when_needed, |
445 | opnum, rld[s_reload].opnum)) | |
7b9a997f | 446 | { |
447 | if (in_p) | |
48666d2c | 448 | rld[s_reload].inmode = mode; |
7b9a997f | 449 | if (! in_p) |
48666d2c | 450 | rld[s_reload].outmode = mode; |
7b9a997f | 451 | |
c32319fc | 452 | if (reg_class_subset_p (rclass, rld[s_reload].rclass)) |
453 | rld[s_reload].rclass = rclass; | |
7b9a997f | 454 | |
48666d2c | 455 | rld[s_reload].opnum = MIN (rld[s_reload].opnum, opnum); |
456 | rld[s_reload].optional &= optional; | |
457 | rld[s_reload].secondary_p = 1; | |
458 | if (MERGE_TO_OTHER (secondary_type, rld[s_reload].when_needed, | |
459 | opnum, rld[s_reload].opnum)) | |
460 | rld[s_reload].when_needed = RELOAD_OTHER; | |
92d21e32 | 461 | |
462 | break; | |
7b9a997f | 463 | } |
42c63e4d | 464 | |
7b9a997f | 465 | if (s_reload == n_reloads) |
466 | { | |
0dbd1c74 | 467 | #ifdef SECONDARY_MEMORY_NEEDED |
468 | /* If we need a memory location to copy between the two reload regs, | |
469 | set it up now. Note that we do the input case before making | |
5bb2f919 | 470 | the reload and the output case after. This is due to the |
0dbd1c74 | 471 | way reloads are output. */ |
472 | ||
473 | if (in_p && icode == CODE_FOR_nothing | |
47cfb7f4 | 474 | && SECONDARY_MEMORY_NEEDED (rclass, reload_class, mode)) |
fc2da810 | 475 | { |
476 | get_secondary_mem (x, reload_mode, opnum, type); | |
477 | ||
478 | /* We may have just added new reloads. Make sure we add | |
479 | the new reload at the end. */ | |
480 | s_reload = n_reloads; | |
481 | } | |
0dbd1c74 | 482 | #endif |
483 | ||
7b9a997f | 484 | /* We need to make a new secondary reload for this register class. */ |
48666d2c | 485 | rld[s_reload].in = rld[s_reload].out = 0; |
c32319fc | 486 | rld[s_reload].rclass = rclass; |
48666d2c | 487 | |
488 | rld[s_reload].inmode = in_p ? mode : VOIDmode; | |
489 | rld[s_reload].outmode = ! in_p ? mode : VOIDmode; | |
490 | rld[s_reload].reg_rtx = 0; | |
491 | rld[s_reload].optional = optional; | |
48666d2c | 492 | rld[s_reload].inc = 0; |
7b9a997f | 493 | /* Maybe we could combine these, but it seems too tricky. */ |
48666d2c | 494 | rld[s_reload].nocombine = 1; |
495 | rld[s_reload].in_reg = 0; | |
496 | rld[s_reload].out_reg = 0; | |
497 | rld[s_reload].opnum = opnum; | |
498 | rld[s_reload].when_needed = secondary_type; | |
499 | rld[s_reload].secondary_in_reload = in_p ? t_reload : -1; | |
500 | rld[s_reload].secondary_out_reload = ! in_p ? t_reload : -1; | |
501 | rld[s_reload].secondary_in_icode = in_p ? t_icode : CODE_FOR_nothing; | |
502 | rld[s_reload].secondary_out_icode | |
7b9a997f | 503 | = ! in_p ? t_icode : CODE_FOR_nothing; |
48666d2c | 504 | rld[s_reload].secondary_p = 1; |
7b9a997f | 505 | |
506 | n_reloads++; | |
507 | ||
508 | #ifdef SECONDARY_MEMORY_NEEDED | |
7b9a997f | 509 | if (! in_p && icode == CODE_FOR_nothing |
47cfb7f4 | 510 | && SECONDARY_MEMORY_NEEDED (reload_class, rclass, mode)) |
c0300174 | 511 | get_secondary_mem (x, mode, opnum, type); |
7b9a997f | 512 | #endif |
513 | } | |
514 | ||
515 | *picode = icode; | |
516 | return s_reload; | |
42c63e4d | 517 | } |
4d58fa46 | 518 | |
519 | /* If a secondary reload is needed, return its class. If both an intermediate | |
520 | register and a scratch register is needed, we return the class of the | |
521 | intermediate register. */ | |
2dfa2c74 | 522 | reg_class_t |
523 | secondary_reload_class (bool in_p, reg_class_t rclass, enum machine_mode mode, | |
524 | rtx x) | |
4d58fa46 | 525 | { |
526 | enum insn_code icode; | |
527 | secondary_reload_info sri; | |
528 | ||
529 | sri.icode = CODE_FOR_nothing; | |
530 | sri.prev_sri = NULL; | |
964229b7 | 531 | rclass |
532 | = (enum reg_class) targetm.secondary_reload (in_p, x, rclass, mode, &sri); | |
8458f4ca | 533 | icode = (enum insn_code) sri.icode; |
4d58fa46 | 534 | |
535 | /* If there are no secondary reloads at all, we return NO_REGS. | |
536 | If an intermediate register is needed, we return its class. */ | |
47cfb7f4 | 537 | if (icode == CODE_FOR_nothing || rclass != NO_REGS) |
538 | return rclass; | |
4d58fa46 | 539 | |
540 | /* No intermediate register is needed, but we have a special reload | |
541 | pattern, which we assume for now needs a scratch register. */ | |
542 | return scratch_reload_class (icode); | |
543 | } | |
544 | ||
545 | /* ICODE is the insn_code of a reload pattern. Check that it has exactly | |
546 | three operands, verify that operand 2 is an output operand, and return | |
547 | its register class. | |
548 | ??? We'd like to be able to handle any pattern with at least 2 operands, | |
549 | for zero or more scratch registers, but that needs more infrastructure. */ | |
550 | enum reg_class | |
551 | scratch_reload_class (enum insn_code icode) | |
552 | { | |
553 | const char *scratch_constraint; | |
554 | char scratch_letter; | |
47cfb7f4 | 555 | enum reg_class rclass; |
4d58fa46 | 556 | |
557 | gcc_assert (insn_data[(int) icode].n_operands == 3); | |
558 | scratch_constraint = insn_data[(int) icode].operand[2].constraint; | |
559 | gcc_assert (*scratch_constraint == '='); | |
560 | scratch_constraint++; | |
561 | if (*scratch_constraint == '&') | |
562 | scratch_constraint++; | |
563 | scratch_letter = *scratch_constraint; | |
564 | if (scratch_letter == 'r') | |
565 | return GENERAL_REGS; | |
47cfb7f4 | 566 | rclass = REG_CLASS_FROM_CONSTRAINT ((unsigned char) scratch_letter, |
4d58fa46 | 567 | scratch_constraint); |
47cfb7f4 | 568 | gcc_assert (rclass != NO_REGS); |
569 | return rclass; | |
4d58fa46 | 570 | } |
42c63e4d | 571 | \f |
c538053c | 572 | #ifdef SECONDARY_MEMORY_NEEDED |
573 | ||
5bb2f919 | 574 | /* Return a memory location that will be used to copy X in mode MODE. |
c538053c | 575 | If we haven't already made a location for this mode in this insn, |
576 | call find_reloads_address on the location being returned. */ | |
577 | ||
578 | rtx | |
3ad4992f | 579 | get_secondary_mem (rtx x ATTRIBUTE_UNUSED, enum machine_mode mode, |
580 | int opnum, enum reload_type type) | |
c538053c | 581 | { |
582 | rtx loc; | |
583 | int mem_valid; | |
584 | ||
c2fdde21 | 585 | /* By default, if MODE is narrower than a word, widen it to a word. |
586 | This is required because most machines that require these memory | |
587 | locations do not support short load and stores from all registers | |
588 | (e.g., FP registers). */ | |
589 | ||
590 | #ifdef SECONDARY_MEMORY_NEEDED_MODE | |
591 | mode = SECONDARY_MEMORY_NEEDED_MODE (mode); | |
592 | #else | |
96ff0372 | 593 | if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD && INTEGRAL_MODE_P (mode)) |
c538053c | 594 | mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0); |
c2fdde21 | 595 | #endif |
c538053c | 596 | |
ac9ae2ad | 597 | /* If we already have made a MEM for this operand in MODE, return it. */ |
598 | if (secondary_memlocs_elim[(int) mode][opnum] != 0) | |
599 | return secondary_memlocs_elim[(int) mode][opnum]; | |
c538053c | 600 | |
5bb2f919 | 601 | /* If this is the first time we've tried to get a MEM for this mode, |
c538053c | 602 | allocate a new one. `something_changed' in reload will get set |
603 | by noticing that the frame size has changed. */ | |
604 | ||
605 | if (secondary_memlocs[(int) mode] == 0) | |
3bcf63ee | 606 | { |
607 | #ifdef SECONDARY_MEMORY_NEEDED_RTX | |
608 | secondary_memlocs[(int) mode] = SECONDARY_MEMORY_NEEDED_RTX (mode); | |
609 | #else | |
610 | secondary_memlocs[(int) mode] | |
611 | = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); | |
612 | #endif | |
613 | } | |
c538053c | 614 | |
615 | /* Get a version of the address doing any eliminations needed. If that | |
616 | didn't give us a new MEM, make a new one if it isn't valid. */ | |
617 | ||
6182a80f | 618 | loc = eliminate_regs (secondary_memlocs[(int) mode], VOIDmode, NULL_RTX); |
bd1a81f7 | 619 | mem_valid = strict_memory_address_addr_space_p (mode, XEXP (loc, 0), |
620 | MEM_ADDR_SPACE (loc)); | |
c538053c | 621 | |
622 | if (! mem_valid && loc == secondary_memlocs[(int) mode]) | |
623 | loc = copy_rtx (loc); | |
624 | ||
625 | /* The only time the call below will do anything is if the stack | |
626 | offset is too large. In that case IND_LEVELS doesn't matter, so we | |
70457512 | 627 | can just pass a zero. Adjust the type to be the address of the |
628 | corresponding object. If the address was valid, save the eliminated | |
629 | address. If it wasn't valid, we need to make a reload each time, so | |
630 | don't save it. */ | |
c538053c | 631 | |
70457512 | 632 | if (! mem_valid) |
633 | { | |
634 | type = (type == RELOAD_FOR_INPUT ? RELOAD_FOR_INPUT_ADDRESS | |
635 | : type == RELOAD_FOR_OUTPUT ? RELOAD_FOR_OUTPUT_ADDRESS | |
636 | : RELOAD_OTHER); | |
958e9e7e | 637 | |
e9bf6953 | 638 | find_reloads_address (mode, &loc, XEXP (loc, 0), &XEXP (loc, 0), |
d59f2d23 | 639 | opnum, type, 0, 0); |
70457512 | 640 | } |
c538053c | 641 | |
ac9ae2ad | 642 | secondary_memlocs_elim[(int) mode][opnum] = loc; |
88b8887c | 643 | if (secondary_memlocs_elim_used <= (int)mode) |
644 | secondary_memlocs_elim_used = (int)mode + 1; | |
c538053c | 645 | return loc; |
646 | } | |
647 | ||
648 | /* Clear any secondary memory locations we've made. */ | |
649 | ||
650 | void | |
3ad4992f | 651 | clear_secondary_mem (void) |
c538053c | 652 | { |
f0af5a88 | 653 | memset (secondary_memlocs, 0, sizeof secondary_memlocs); |
c538053c | 654 | } |
655 | #endif /* SECONDARY_MEMORY_NEEDED */ | |
656 | \f | |
8f3b70dd | 657 | |
658 | /* Find the largest class which has at least one register valid in | |
659 | mode INNER, and which for every such register, that register number | |
660 | plus N is also valid in OUTER (if in range) and is cheap to move | |
1fa3a8f6 | 661 | into REGNO. Such a class must exist. */ |
95969b77 | 662 | |
663 | static enum reg_class | |
8f3b70dd | 664 | find_valid_class (enum machine_mode outer ATTRIBUTE_UNUSED, |
665 | enum machine_mode inner ATTRIBUTE_UNUSED, int n, | |
3ad4992f | 666 | unsigned int dest_regno ATTRIBUTE_UNUSED) |
95969b77 | 667 | { |
35e2e148 | 668 | int best_cost = -1; |
47cfb7f4 | 669 | int rclass; |
95969b77 | 670 | int regno; |
d844aacc | 671 | enum reg_class best_class = NO_REGS; |
805e22b2 | 672 | enum reg_class dest_class ATTRIBUTE_UNUSED = REGNO_REG_CLASS (dest_regno); |
02e7a332 | 673 | unsigned int best_size = 0; |
53a53cbe | 674 | int cost; |
95969b77 | 675 | |
47cfb7f4 | 676 | for (rclass = 1; rclass < N_REG_CLASSES; rclass++) |
95969b77 | 677 | { |
678 | int bad = 0; | |
8f3b70dd | 679 | int good = 0; |
680 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER - n && ! bad; regno++) | |
47cfb7f4 | 681 | if (TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)) |
8f3b70dd | 682 | { |
683 | if (HARD_REGNO_MODE_OK (regno, inner)) | |
684 | { | |
685 | good = 1; | |
47cfb7f4 | 686 | if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], regno + n) |
8f3b70dd | 687 | || ! HARD_REGNO_MODE_OK (regno + n, outer)) |
688 | bad = 1; | |
689 | } | |
690 | } | |
95969b77 | 691 | |
8f3b70dd | 692 | if (bad || !good) |
53a53cbe | 693 | continue; |
e6078fbb | 694 | cost = register_move_cost (outer, (enum reg_class) rclass, dest_class); |
53a53cbe | 695 | |
47cfb7f4 | 696 | if ((reg_class_size[rclass] > best_size |
53a53cbe | 697 | && (best_cost < 0 || best_cost >= cost)) |
698 | || best_cost > cost) | |
35e2e148 | 699 | { |
8458f4ca | 700 | best_class = (enum reg_class) rclass; |
47cfb7f4 | 701 | best_size = reg_class_size[rclass]; |
e6078fbb | 702 | best_cost = register_move_cost (outer, (enum reg_class) rclass, |
b9c74b4d | 703 | dest_class); |
35e2e148 | 704 | } |
95969b77 | 705 | } |
706 | ||
04e579b6 | 707 | gcc_assert (best_size != 0); |
95969b77 | 708 | |
709 | return best_class; | |
710 | } | |
711 | \f | |
00205cbc | 712 | /* Return the number of a previously made reload that can be combined with |
713 | a new one, or n_reloads if none of the existing reloads can be used. | |
47cfb7f4 | 714 | OUT, RCLASS, TYPE and OPNUM are the same arguments as passed to |
00205cbc | 715 | push_reload, they determine the kind of the new reload that we try to |
716 | combine. P_IN points to the corresponding value of IN, which can be | |
717 | modified by this function. | |
718 | DONT_SHARE is nonzero if we can't share any input-only reload for IN. */ | |
1b4f35b9 | 719 | |
00205cbc | 720 | static int |
47cfb7f4 | 721 | find_reusable_reload (rtx *p_in, rtx out, enum reg_class rclass, |
3ad4992f | 722 | enum reload_type type, int opnum, int dont_share) |
00205cbc | 723 | { |
724 | rtx in = *p_in; | |
725 | int i; | |
726 | /* We can't merge two reloads if the output of either one is | |
727 | earlyclobbered. */ | |
728 | ||
729 | if (earlyclobber_operand_p (out)) | |
730 | return n_reloads; | |
731 | ||
732 | /* We can use an existing reload if the class is right | |
733 | and at least one of IN and OUT is a match | |
734 | and the other is at worst neutral. | |
5bb2f919 | 735 | (A zero compared against anything is neutral.) |
00205cbc | 736 | |
ed5527ca | 737 | For targets with small register classes, don't use existing reloads |
738 | unless they are for the same thing since that can cause us to need | |
739 | more reload registers than we otherwise would. */ | |
5bb2f919 | 740 | |
00205cbc | 741 | for (i = 0; i < n_reloads; i++) |
c32319fc | 742 | if ((reg_class_subset_p (rclass, rld[i].rclass) |
743 | || reg_class_subset_p (rld[i].rclass, rclass)) | |
00205cbc | 744 | /* If the existing reload has a register, it must fit our class. */ |
48666d2c | 745 | && (rld[i].reg_rtx == 0 |
47cfb7f4 | 746 | || TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], |
48666d2c | 747 | true_regnum (rld[i].reg_rtx))) |
748 | && ((in != 0 && MATCHES (rld[i].in, in) && ! dont_share | |
749 | && (out == 0 || rld[i].out == 0 || MATCHES (rld[i].out, out))) | |
750 | || (out != 0 && MATCHES (rld[i].out, out) | |
751 | && (in == 0 || rld[i].in == 0 || MATCHES (rld[i].in, in)))) | |
752 | && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out)) | |
24dd0668 | 753 | && (small_register_class_p (rclass) |
ed5527ca | 754 | || targetm.small_register_classes_for_mode_p (VOIDmode)) |
48666d2c | 755 | && MERGABLE_RELOADS (type, rld[i].when_needed, opnum, rld[i].opnum)) |
00205cbc | 756 | return i; |
757 | ||
758 | /* Reloading a plain reg for input can match a reload to postincrement | |
759 | that reg, since the postincrement's value is the right value. | |
760 | Likewise, it can match a preincrement reload, since we regard | |
761 | the preincrementation as happening before any ref in this insn | |
762 | to that register. */ | |
763 | for (i = 0; i < n_reloads; i++) | |
c32319fc | 764 | if ((reg_class_subset_p (rclass, rld[i].rclass) |
765 | || reg_class_subset_p (rld[i].rclass, rclass)) | |
00205cbc | 766 | /* If the existing reload has a register, it must fit our |
767 | class. */ | |
48666d2c | 768 | && (rld[i].reg_rtx == 0 |
47cfb7f4 | 769 | || TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], |
48666d2c | 770 | true_regnum (rld[i].reg_rtx))) |
771 | && out == 0 && rld[i].out == 0 && rld[i].in != 0 | |
8ad4c111 | 772 | && ((REG_P (in) |
6720e96c | 773 | && GET_RTX_CLASS (GET_CODE (rld[i].in)) == RTX_AUTOINC |
48666d2c | 774 | && MATCHES (XEXP (rld[i].in, 0), in)) |
8ad4c111 | 775 | || (REG_P (rld[i].in) |
6720e96c | 776 | && GET_RTX_CLASS (GET_CODE (in)) == RTX_AUTOINC |
40988080 | 777 | && MATCHES (XEXP (in, 0), rld[i].in))) |
48666d2c | 778 | && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out)) |
24dd0668 | 779 | && (small_register_class_p (rclass) |
ed5527ca | 780 | || targetm.small_register_classes_for_mode_p (VOIDmode)) |
48666d2c | 781 | && MERGABLE_RELOADS (type, rld[i].when_needed, |
782 | opnum, rld[i].opnum)) | |
00205cbc | 783 | { |
784 | /* Make sure reload_in ultimately has the increment, | |
785 | not the plain register. */ | |
8ad4c111 | 786 | if (REG_P (in)) |
48666d2c | 787 | *p_in = rld[i].in; |
00205cbc | 788 | return i; |
789 | } | |
790 | return n_reloads; | |
791 | } | |
792 | ||
8ffd11f4 | 793 | /* Return true if X is a SUBREG that will need reloading of its SUBREG_REG |
794 | expression. MODE is the mode that X will be used in. OUTPUT is true if | |
795 | the function is invoked for the output part of an enclosing reload. */ | |
239eff68 | 796 | |
8ffd11f4 | 797 | static bool |
798 | reload_inner_reg_of_subreg (rtx x, enum machine_mode mode, bool output) | |
239eff68 | 799 | { |
800 | rtx inner; | |
801 | ||
802 | /* Only SUBREGs are problematical. */ | |
803 | if (GET_CODE (x) != SUBREG) | |
8ffd11f4 | 804 | return false; |
239eff68 | 805 | |
806 | inner = SUBREG_REG (x); | |
807 | ||
8ffd11f4 | 808 | /* If INNER is a constant or PLUS, then INNER will need reloading. */ |
1b4f35b9 | 809 | if (CONSTANT_P (inner) || GET_CODE (inner) == PLUS) |
8ffd11f4 | 810 | return true; |
239eff68 | 811 | |
8ffd11f4 | 812 | /* If INNER is not a hard register, then INNER will not need reloading. */ |
813 | if (!(REG_P (inner) && HARD_REGISTER_P (inner))) | |
814 | return false; | |
239eff68 | 815 | |
816 | /* If INNER is not ok for MODE, then INNER will need reloading. */ | |
8ffd11f4 | 817 | if (!HARD_REGNO_MODE_OK (subreg_regno (x), mode)) |
818 | return true; | |
819 | ||
820 | /* If this is for an output, and the outer part is a word or smaller, | |
821 | INNER is larger than a word and the number of registers in INNER is | |
822 | not the same as the number of words in INNER, then INNER will need | |
823 | reloading (with an in-out reload). */ | |
824 | return (output | |
825 | && GET_MODE_SIZE (mode) <= UNITS_PER_WORD | |
239eff68 | 826 | && GET_MODE_SIZE (GET_MODE (inner)) > UNITS_PER_WORD |
827 | && ((GET_MODE_SIZE (GET_MODE (inner)) / UNITS_PER_WORD) | |
67d6c12b | 828 | != (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)])); |
239eff68 | 829 | } |
830 | ||
ec6e4b23 | 831 | /* Return nonzero if IN can be reloaded into REGNO with mode MODE without |
832 | requiring an extra reload register. The caller has already found that | |
833 | IN contains some reference to REGNO, so check that we can produce the | |
834 | new value in a single step. E.g. if we have | |
835 | (set (reg r13) (plus (reg r13) (const int 1))), and there is an | |
836 | instruction that adds one to a register, this should succeed. | |
837 | However, if we have something like | |
838 | (set (reg r13) (plus (reg r13) (const int 999))), and the constant 999 | |
839 | needs to be loaded into a register first, we need a separate reload | |
840 | register. | |
841 | Such PLUS reloads are generated by find_reload_address_part. | |
842 | The out-of-range PLUS expressions are usually introduced in the instruction | |
843 | patterns by register elimination and substituting pseudos without a home | |
844 | by their function-invariant equivalences. */ | |
845 | static int | |
846 | can_reload_into (rtx in, int regno, enum machine_mode mode) | |
847 | { | |
848 | rtx dst, test_insn; | |
849 | int r = 0; | |
850 | struct recog_data save_recog_data; | |
851 | ||
852 | /* For matching constraints, we often get notional input reloads where | |
853 | we want to use the original register as the reload register. I.e. | |
854 | technically this is a non-optional input-output reload, but IN is | |
855 | already a valid register, and has been chosen as the reload register. | |
856 | Speed this up, since it trivially works. */ | |
8ad4c111 | 857 | if (REG_P (in)) |
ec6e4b23 | 858 | return 1; |
859 | ||
860 | /* To test MEMs properly, we'd have to take into account all the reloads | |
861 | that are already scheduled, which can become quite complicated. | |
862 | And since we've already handled address reloads for this MEM, it | |
863 | should always succeed anyway. */ | |
e16ceb8e | 864 | if (MEM_P (in)) |
ec6e4b23 | 865 | return 1; |
866 | ||
867 | /* If we can make a simple SET insn that does the job, everything should | |
868 | be fine. */ | |
869 | dst = gen_rtx_REG (mode, regno); | |
870 | test_insn = make_insn_raw (gen_rtx_SET (VOIDmode, dst, in)); | |
871 | save_recog_data = recog_data; | |
872 | if (recog_memoized (test_insn) >= 0) | |
873 | { | |
874 | extract_insn (test_insn); | |
875 | r = constrain_operands (1); | |
876 | } | |
877 | recog_data = save_recog_data; | |
878 | return r; | |
879 | } | |
880 | ||
70457512 | 881 | /* Record one reload that needs to be performed. |
42c63e4d | 882 | IN is an rtx saying where the data are to be found before this instruction. |
883 | OUT says where they must be stored after the instruction. | |
884 | (IN is zero for data not read, and OUT is zero for data not written.) | |
885 | INLOC and OUTLOC point to the places in the instructions where | |
886 | IN and OUT were found. | |
7fd957fe | 887 | If IN and OUT are both nonzero, it means the same register must be used |
70457512 | 888 | to reload both IN and OUT. |
889 | ||
47cfb7f4 | 890 | RCLASS is a register class required for the reloaded data. |
42c63e4d | 891 | INMODE is the machine mode that the instruction requires |
892 | for the reg that replaces IN and OUTMODE is likewise for OUT. | |
893 | ||
894 | If IN is zero, then OUT's location and mode should be passed as | |
895 | INLOC and INMODE. | |
896 | ||
897 | STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx. | |
898 | ||
899 | OPTIONAL nonzero means this reload does not need to be performed: | |
900 | it can be discarded if that is more convenient. | |
901 | ||
70457512 | 902 | OPNUM and TYPE say what the purpose of this reload is. |
903 | ||
42c63e4d | 904 | The return value is the reload-number for this reload. |
905 | ||
906 | If both IN and OUT are nonzero, in some rare cases we might | |
907 | want to make two separate reloads. (Actually we never do this now.) | |
908 | Therefore, the reload-number for OUT is stored in | |
909 | output_reloadnum when we return; the return value applies to IN. | |
910 | Usually (presently always), when IN and OUT are nonzero, | |
911 | the two reload-numbers are equal, but the caller should be careful to | |
912 | distinguish them. */ | |
913 | ||
0d50f0b7 | 914 | int |
3ad4992f | 915 | push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc, |
47cfb7f4 | 916 | enum reg_class rclass, enum machine_mode inmode, |
3ad4992f | 917 | enum machine_mode outmode, int strict_low, int optional, |
918 | int opnum, enum reload_type type) | |
42c63e4d | 919 | { |
19cb6b50 | 920 | int i; |
42c63e4d | 921 | int dont_share = 0; |
76f1a77f | 922 | int dont_remove_subreg = 0; |
7257cc4d | 923 | #ifdef LIMIT_RELOAD_CLASS |
42c63e4d | 924 | rtx *in_subreg_loc = 0, *out_subreg_loc = 0; |
7257cc4d | 925 | #endif |
7b9a997f | 926 | int secondary_in_reload = -1, secondary_out_reload = -1; |
aaa8b713 | 927 | enum insn_code secondary_in_icode = CODE_FOR_nothing; |
928 | enum insn_code secondary_out_icode = CODE_FOR_nothing; | |
70457512 | 929 | |
42c63e4d | 930 | /* INMODE and/or OUTMODE could be VOIDmode if no mode |
931 | has been specified for the operand. In that case, | |
932 | use the operand's mode as the mode to reload. */ | |
933 | if (inmode == VOIDmode && in != 0) | |
934 | inmode = GET_MODE (in); | |
935 | if (outmode == VOIDmode && out != 0) | |
936 | outmode = GET_MODE (out); | |
937 | ||
cd6659e3 | 938 | /* If find_reloads and friends until now missed to replace a pseudo |
939 | with a constant of reg_equiv_constant something went wrong | |
940 | beforehand. | |
941 | Note that it can't simply be done here if we missed it earlier | |
942 | since the constant might need to be pushed into the literal pool | |
943 | and the resulting memref would probably need further | |
944 | reloading. */ | |
8ad4c111 | 945 | if (in != 0 && REG_P (in)) |
42c63e4d | 946 | { |
19cb6b50 | 947 | int regno = REGNO (in); |
42c63e4d | 948 | |
cd6659e3 | 949 | gcc_assert (regno < FIRST_PSEUDO_REGISTER |
950 | || reg_renumber[regno] >= 0 | |
1c654ff1 | 951 | || reg_equiv_constant (regno) == NULL_RTX); |
42c63e4d | 952 | } |
953 | ||
cd6659e3 | 954 | /* reg_equiv_constant only contains constants which are obviously |
955 | not appropriate as destination. So if we would need to replace | |
956 | the destination pseudo with a constant we are in real | |
957 | trouble. */ | |
8ad4c111 | 958 | if (out != 0 && REG_P (out)) |
42c63e4d | 959 | { |
19cb6b50 | 960 | int regno = REGNO (out); |
42c63e4d | 961 | |
cd6659e3 | 962 | gcc_assert (regno < FIRST_PSEUDO_REGISTER |
963 | || reg_renumber[regno] >= 0 | |
1c654ff1 | 964 | || reg_equiv_constant (regno) == NULL_RTX); |
42c63e4d | 965 | } |
966 | ||
967 | /* If we have a read-write operand with an address side-effect, | |
968 | change either IN or OUT so the side-effect happens only once. */ | |
e16ceb8e | 969 | if (in != 0 && out != 0 && MEM_P (in) && rtx_equal_p (in, out)) |
e4e86ec5 | 970 | switch (GET_CODE (XEXP (in, 0))) |
971 | { | |
972 | case POST_INC: case POST_DEC: case POST_MODIFY: | |
973 | in = replace_equiv_address_nv (in, XEXP (XEXP (in, 0), 0)); | |
974 | break; | |
f7c44134 | 975 | |
e4e86ec5 | 976 | case PRE_INC: case PRE_DEC: case PRE_MODIFY: |
977 | out = replace_equiv_address_nv (out, XEXP (XEXP (out, 0), 0)); | |
978 | break; | |
f7c44134 | 979 | |
e4e86ec5 | 980 | default: |
981 | break; | |
33181afc | 982 | } |
42c63e4d | 983 | |
cbcb19b7 | 984 | /* If we are reloading a (SUBREG constant ...), really reload just the |
7bc1bb34 | 985 | inside expression in its own mode. Similarly for (SUBREG (PLUS ...)). |
cbcb19b7 | 986 | If we have (SUBREG:M1 (MEM:M2 ...) ...) (or an inner REG that is still |
987 | a pseudo and hence will become a MEM) with M1 wider than M2 and the | |
988 | register is a pseudo, also reload the inside expression. | |
cbbca02e | 989 | For machines that extend byte loads, do this for any SUBREG of a pseudo |
bfdb517e | 990 | where both M1 and M2 are a word or smaller, M1 is wider than M2, and |
991 | M2 is an integral mode that gets extended when loaded. | |
8ffd11f4 | 992 | Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R |
993 | where either M1 is not valid for R or M2 is wider than a word but we | |
994 | only need one register to store an M2-sized quantity in R. | |
2b6ccac4 | 995 | (However, if OUT is nonzero, we need to reload the reg *and* |
996 | the subreg, so do nothing here, and let following statement handle it.) | |
997 | ||
42c63e4d | 998 | Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere; |
999 | we can't handle it here because CONST_INT does not indicate a mode. | |
1000 | ||
1001 | Similarly, we must reload the inside expression if we have a | |
f0b5f617 | 1002 | STRICT_LOW_PART (presumably, in == out in this case). |
a77b65e2 | 1003 | |
1004 | Also reload the inner expression if it does not require a secondary | |
bfdb517e | 1005 | reload but the SUBREG does. |
1006 | ||
1007 | Finally, reload the inner expression if it is a register that is in | |
1008 | the class whose registers cannot be referenced in a different size | |
9685f2a4 | 1009 | and M1 is not the same size as M2. If subreg_lowpart_p is false, we |
d8bdfb5a | 1010 | cannot reload just the inside since we might end up with the wrong |
be2828ce | 1011 | register class. But if it is inside a STRICT_LOW_PART, we have |
1012 | no choice, so we hope we do get the right register class there. */ | |
42c63e4d | 1013 | |
be2828ce | 1014 | if (in != 0 && GET_CODE (in) == SUBREG |
9685f2a4 | 1015 | && (subreg_lowpart_p (in) || strict_low) |
897118e8 | 1016 | #ifdef CANNOT_CHANGE_MODE_CLASS |
47cfb7f4 | 1017 | && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (in)), inmode, rclass) |
4c9ebf15 | 1018 | #endif |
b128b22f | 1019 | && contains_reg_of_mode[(int) rclass][(int) GET_MODE (SUBREG_REG (in))] |
cbcb19b7 | 1020 | && (CONSTANT_P (SUBREG_REG (in)) |
7bc1bb34 | 1021 | || GET_CODE (SUBREG_REG (in)) == PLUS |
42c63e4d | 1022 | || strict_low |
8ad4c111 | 1023 | || (((REG_P (SUBREG_REG (in)) |
cbcb19b7 | 1024 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER) |
e16ceb8e | 1025 | || MEM_P (SUBREG_REG (in))) |
b537bfdb | 1026 | && ((GET_MODE_PRECISION (inmode) |
1027 | > GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in)))) | |
c05e2779 | 1028 | #ifdef LOAD_EXTEND_OP |
011d1afd | 1029 | || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD |
1030 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1031 | <= UNITS_PER_WORD) | |
b537bfdb | 1032 | && (GET_MODE_PRECISION (inmode) |
1033 | > GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in)))) | |
bfdb517e | 1034 | && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in))) |
21f1e711 | 1035 | && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != UNKNOWN) |
50cbc1ef | 1036 | #endif |
1037 | #ifdef WORD_REGISTER_OPERATIONS | |
b537bfdb | 1038 | || ((GET_MODE_PRECISION (inmode) |
1039 | < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in)))) | |
50cbc1ef | 1040 | && ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD == |
1041 | ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) - 1) | |
1042 | / UNITS_PER_WORD))) | |
cbbca02e | 1043 | #endif |
011d1afd | 1044 | )) |
8ad4c111 | 1045 | || (REG_P (SUBREG_REG (in)) |
cbcb19b7 | 1046 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER |
2b6ccac4 | 1047 | /* The case where out is nonzero |
1048 | is handled differently in the following statement. */ | |
9685f2a4 | 1049 | && (out == 0 || subreg_lowpart_p (in)) |
cbbca02e | 1050 | && ((GET_MODE_SIZE (inmode) <= UNITS_PER_WORD |
1051 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1052 | > UNITS_PER_WORD) | |
1053 | && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1054 | / UNITS_PER_WORD) | |
67d6c12b | 1055 | != (int) hard_regno_nregs[REGNO (SUBREG_REG (in))] |
1056 | [GET_MODE (SUBREG_REG (in))])) | |
701e46d0 | 1057 | || ! HARD_REGNO_MODE_OK (subreg_regno (in), inmode))) |
47cfb7f4 | 1058 | || (secondary_reload_class (1, rclass, inmode, in) != NO_REGS |
1059 | && (secondary_reload_class (1, rclass, GET_MODE (SUBREG_REG (in)), | |
4d58fa46 | 1060 | SUBREG_REG (in)) |
a77b65e2 | 1061 | == NO_REGS)) |
897118e8 | 1062 | #ifdef CANNOT_CHANGE_MODE_CLASS |
8ad4c111 | 1063 | || (REG_P (SUBREG_REG (in)) |
bfdb517e | 1064 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER |
897118e8 | 1065 | && REG_CANNOT_CHANGE_MODE_P |
1066 | (REGNO (SUBREG_REG (in)), GET_MODE (SUBREG_REG (in)), inmode)) | |
a77b65e2 | 1067 | #endif |
1068 | )) | |
42c63e4d | 1069 | { |
7257cc4d | 1070 | #ifdef LIMIT_RELOAD_CLASS |
42c63e4d | 1071 | in_subreg_loc = inloc; |
7257cc4d | 1072 | #endif |
42c63e4d | 1073 | inloc = &SUBREG_REG (in); |
1074 | in = *inloc; | |
50cbc1ef | 1075 | #if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS) |
e16ceb8e | 1076 | if (MEM_P (in)) |
42c63e4d | 1077 | /* This is supposed to happen only for paradoxical subregs made by |
1078 | combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */ | |
04e579b6 | 1079 | gcc_assert (GET_MODE_SIZE (GET_MODE (in)) <= GET_MODE_SIZE (inmode)); |
2a8658e5 | 1080 | #endif |
42c63e4d | 1081 | inmode = GET_MODE (in); |
1082 | } | |
1083 | ||
8ffd11f4 | 1084 | /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R |
1085 | where M1 is not valid for R if it was not handled by the code above. | |
1086 | ||
1087 | Similar issue for (SUBREG constant ...) if it was not handled by the | |
1088 | code above. This can happen if SUBREG_BYTE != 0. | |
2b6ccac4 | 1089 | |
1090 | However, we must reload the inner reg *as well as* the subreg in | |
1091 | that case. */ | |
1092 | ||
8ffd11f4 | 1093 | if (in != 0 && reload_inner_reg_of_subreg (in, inmode, false)) |
2b6ccac4 | 1094 | { |
47cfb7f4 | 1095 | enum reg_class in_class = rclass; |
1b4f35b9 | 1096 | |
8ad4c111 | 1097 | if (REG_P (SUBREG_REG (in))) |
1b4f35b9 | 1098 | in_class |
8f3b70dd | 1099 | = find_valid_class (inmode, GET_MODE (SUBREG_REG (in)), |
1b4f35b9 | 1100 | subreg_regno_offset (REGNO (SUBREG_REG (in)), |
1101 | GET_MODE (SUBREG_REG (in)), | |
1102 | SUBREG_BYTE (in), | |
35e2e148 | 1103 | GET_MODE (in)), |
1104 | REGNO (SUBREG_REG (in))); | |
1b4f35b9 | 1105 | |
9b3dc0cb | 1106 | /* This relies on the fact that emit_reload_insns outputs the |
1107 | instructions for input reloads of type RELOAD_OTHER in the same | |
1108 | order as the reloads. Thus if the outer reload is also of type | |
1109 | RELOAD_OTHER, we are guaranteed that this inner reload will be | |
1110 | output before the outer reload. */ | |
33181afc | 1111 | push_reload (SUBREG_REG (in), NULL_RTX, &SUBREG_REG (in), (rtx *) 0, |
1b4f35b9 | 1112 | in_class, VOIDmode, VOIDmode, 0, 0, opnum, type); |
76f1a77f | 1113 | dont_remove_subreg = 1; |
2b6ccac4 | 1114 | } |
1115 | ||
42c63e4d | 1116 | /* Similarly for paradoxical and problematical SUBREGs on the output. |
1117 | Note that there is no reason we need worry about the previous value | |
6211b3f4 | 1118 | of SUBREG_REG (out); even if wider than out, storing in a subreg is |
1119 | entitled to clobber it all (except in the case of a word mode subreg | |
1120 | or of a STRICT_LOW_PART, in that latter case the constraint should | |
1121 | label it input-output.) */ | |
be2828ce | 1122 | if (out != 0 && GET_CODE (out) == SUBREG |
9685f2a4 | 1123 | && (subreg_lowpart_p (out) || strict_low) |
897118e8 | 1124 | #ifdef CANNOT_CHANGE_MODE_CLASS |
47cfb7f4 | 1125 | && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (out)), outmode, rclass) |
4c9ebf15 | 1126 | #endif |
b128b22f | 1127 | && contains_reg_of_mode[(int) rclass][(int) GET_MODE (SUBREG_REG (out))] |
cbcb19b7 | 1128 | && (CONSTANT_P (SUBREG_REG (out)) |
42c63e4d | 1129 | || strict_low |
8ad4c111 | 1130 | || (((REG_P (SUBREG_REG (out)) |
cbcb19b7 | 1131 | && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER) |
e16ceb8e | 1132 | || MEM_P (SUBREG_REG (out))) |
b537bfdb | 1133 | && ((GET_MODE_PRECISION (outmode) |
1134 | > GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out)))) | |
6182a80f | 1135 | #ifdef WORD_REGISTER_OPERATIONS |
b537bfdb | 1136 | || ((GET_MODE_PRECISION (outmode) |
1137 | < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out)))) | |
ebbb4987 | 1138 | && ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD == |
1139 | ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) - 1) | |
1140 | / UNITS_PER_WORD))) | |
6182a80f | 1141 | #endif |
5bb2f919 | 1142 | )) |
99bef0c5 | 1143 | || (REG_P (SUBREG_REG (out)) |
1144 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER | |
1145 | /* The case of a word mode subreg | |
1146 | is handled differently in the following statement. */ | |
1147 | && ! (GET_MODE_SIZE (outmode) <= UNITS_PER_WORD | |
1148 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) | |
1149 | > UNITS_PER_WORD)) | |
1150 | && ! HARD_REGNO_MODE_OK (subreg_regno (out), outmode)) | |
47cfb7f4 | 1151 | || (secondary_reload_class (0, rclass, outmode, out) != NO_REGS |
1152 | && (secondary_reload_class (0, rclass, GET_MODE (SUBREG_REG (out)), | |
4d58fa46 | 1153 | SUBREG_REG (out)) |
a77b65e2 | 1154 | == NO_REGS)) |
897118e8 | 1155 | #ifdef CANNOT_CHANGE_MODE_CLASS |
8ad4c111 | 1156 | || (REG_P (SUBREG_REG (out)) |
bfdb517e | 1157 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER |
897118e8 | 1158 | && REG_CANNOT_CHANGE_MODE_P (REGNO (SUBREG_REG (out)), |
3ad4992f | 1159 | GET_MODE (SUBREG_REG (out)), |
897118e8 | 1160 | outmode)) |
a77b65e2 | 1161 | #endif |
1162 | )) | |
42c63e4d | 1163 | { |
7257cc4d | 1164 | #ifdef LIMIT_RELOAD_CLASS |
42c63e4d | 1165 | out_subreg_loc = outloc; |
7257cc4d | 1166 | #endif |
42c63e4d | 1167 | outloc = &SUBREG_REG (out); |
5bb2f919 | 1168 | out = *outloc; |
50cbc1ef | 1169 | #if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS) |
04e579b6 | 1170 | gcc_assert (!MEM_P (out) |
1171 | || GET_MODE_SIZE (GET_MODE (out)) | |
1172 | <= GET_MODE_SIZE (outmode)); | |
2a8658e5 | 1173 | #endif |
42c63e4d | 1174 | outmode = GET_MODE (out); |
1175 | } | |
1176 | ||
8ffd11f4 | 1177 | /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R |
1178 | where either M1 is not valid for R or M2 is wider than a word but we | |
1179 | only need one register to store an M2-sized quantity in R. | |
76f1a77f | 1180 | |
1181 | However, we must reload the inner reg *as well as* the subreg in | |
8ffd11f4 | 1182 | that case and the inner reg is an in-out reload. */ |
76f1a77f | 1183 | |
8ffd11f4 | 1184 | if (out != 0 && reload_inner_reg_of_subreg (out, outmode, true)) |
76f1a77f | 1185 | { |
8ffd11f4 | 1186 | enum reg_class in_out_class |
1187 | = find_valid_class (outmode, GET_MODE (SUBREG_REG (out)), | |
1188 | subreg_regno_offset (REGNO (SUBREG_REG (out)), | |
1189 | GET_MODE (SUBREG_REG (out)), | |
1190 | SUBREG_BYTE (out), | |
1191 | GET_MODE (out)), | |
1192 | REGNO (SUBREG_REG (out))); | |
1193 | ||
9b3dc0cb | 1194 | /* This relies on the fact that emit_reload_insns outputs the |
1195 | instructions for output reloads of type RELOAD_OTHER in reverse | |
1196 | order of the reloads. Thus if the outer reload is also of type | |
1197 | RELOAD_OTHER, we are guaranteed that this inner reload will be | |
1198 | output after the outer reload. */ | |
76f1a77f | 1199 | push_reload (SUBREG_REG (out), SUBREG_REG (out), &SUBREG_REG (out), |
8ffd11f4 | 1200 | &SUBREG_REG (out), in_out_class, VOIDmode, VOIDmode, |
1201 | 0, 0, opnum, RELOAD_OTHER); | |
1202 | dont_remove_subreg = 1; | |
76f1a77f | 1203 | } |
1204 | ||
42c63e4d | 1205 | /* If IN appears in OUT, we can't share any input-only reload for IN. */ |
e16ceb8e | 1206 | if (in != 0 && out != 0 && MEM_P (out) |
1121ac6f | 1207 | && (REG_P (in) || MEM_P (in) || GET_CODE (in) == PLUS) |
d3862ba2 | 1208 | && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0))) |
42c63e4d | 1209 | dont_share = 1; |
1210 | ||
c538053c | 1211 | /* If IN is a SUBREG of a hard register, make a new REG. This |
1212 | simplifies some of the cases below. */ | |
1213 | ||
8ad4c111 | 1214 | if (in != 0 && GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in)) |
76f1a77f | 1215 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER |
1216 | && ! dont_remove_subreg) | |
701e46d0 | 1217 | in = gen_rtx_REG (GET_MODE (in), subreg_regno (in)); |
c538053c | 1218 | |
1219 | /* Similarly for OUT. */ | |
1220 | if (out != 0 && GET_CODE (out) == SUBREG | |
8ad4c111 | 1221 | && REG_P (SUBREG_REG (out)) |
76f1a77f | 1222 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER |
1223 | && ! dont_remove_subreg) | |
701e46d0 | 1224 | out = gen_rtx_REG (GET_MODE (out), subreg_regno (out)); |
c538053c | 1225 | |
42c63e4d | 1226 | /* Narrow down the class of register wanted if that is |
1227 | desirable on this machine for efficiency. */ | |
897f76b2 | 1228 | { |
71db0d8b | 1229 | reg_class_t preferred_class = rclass; |
897f76b2 | 1230 | |
1231 | if (in != 0) | |
71db0d8b | 1232 | preferred_class = targetm.preferred_reload_class (in, rclass); |
42c63e4d | 1233 | |
71db0d8b | 1234 | /* Output reloads may need analogous treatment, different in detail. */ |
897f76b2 | 1235 | if (out != 0) |
71db0d8b | 1236 | preferred_class |
1237 | = targetm.preferred_output_reload_class (out, preferred_class); | |
2b9f2488 | 1238 | |
897f76b2 | 1239 | /* Discard what the target said if we cannot do it. */ |
1240 | if (preferred_class != NO_REGS | |
1241 | || (optional && type == RELOAD_FOR_OUTPUT)) | |
71db0d8b | 1242 | rclass = (enum reg_class) preferred_class; |
897f76b2 | 1243 | } |
1244 | ||
42c63e4d | 1245 | /* Make sure we use a class that can handle the actual pseudo |
1246 | inside any subreg. For example, on the 386, QImode regs | |
1247 | can appear within SImode subregs. Although GENERAL_REGS | |
1248 | can handle SImode, QImode needs a smaller class. */ | |
1249 | #ifdef LIMIT_RELOAD_CLASS | |
1250 | if (in_subreg_loc) | |
47cfb7f4 | 1251 | rclass = LIMIT_RELOAD_CLASS (inmode, rclass); |
42c63e4d | 1252 | else if (in != 0 && GET_CODE (in) == SUBREG) |
47cfb7f4 | 1253 | rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), rclass); |
42c63e4d | 1254 | |
1255 | if (out_subreg_loc) | |
47cfb7f4 | 1256 | rclass = LIMIT_RELOAD_CLASS (outmode, rclass); |
42c63e4d | 1257 | if (out != 0 && GET_CODE (out) == SUBREG) |
47cfb7f4 | 1258 | rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), rclass); |
42c63e4d | 1259 | #endif |
1260 | ||
42c63e4d | 1261 | /* Verify that this class is at least possible for the mode that |
1262 | is specified. */ | |
1263 | if (this_insn_is_asm) | |
1264 | { | |
1265 | enum machine_mode mode; | |
1266 | if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) | |
1267 | mode = inmode; | |
1268 | else | |
1269 | mode = outmode; | |
7ddfb054 | 1270 | if (mode == VOIDmode) |
1271 | { | |
eb586f2c | 1272 | error_for_asm (this_insn, "cannot reload integer constant " |
1273 | "operand in %<asm%>"); | |
7ddfb054 | 1274 | mode = word_mode; |
1275 | if (in != 0) | |
1276 | inmode = word_mode; | |
1277 | if (out != 0) | |
1278 | outmode = word_mode; | |
1279 | } | |
42c63e4d | 1280 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1281 | if (HARD_REGNO_MODE_OK (i, mode) | |
47cfb7f4 | 1282 | && in_hard_reg_set_p (reg_class_contents[(int) rclass], mode, i)) |
a2c6f0b7 | 1283 | break; |
42c63e4d | 1284 | if (i == FIRST_PSEUDO_REGISTER) |
1285 | { | |
eb586f2c | 1286 | error_for_asm (this_insn, "impossible register constraint " |
1287 | "in %<asm%>"); | |
7c679c65 | 1288 | /* Avoid further trouble with this insn. */ |
1289 | PATTERN (this_insn) = gen_rtx_USE (VOIDmode, const0_rtx); | |
1290 | /* We used to continue here setting class to ALL_REGS, but it triggers | |
1291 | sanity check on i386 for: | |
1292 | void foo(long double d) | |
1293 | { | |
1294 | asm("" :: "a" (d)); | |
1295 | } | |
1296 | Returning zero here ought to be safe as we take care in | |
1297 | find_reloads to not process the reloads when instruction was | |
1298 | replaced by USE. */ | |
48e1416a | 1299 | |
7c679c65 | 1300 | return 0; |
42c63e4d | 1301 | } |
1302 | } | |
1303 | ||
93c7b06e | 1304 | /* Optional output reloads are always OK even if we have no register class, |
1305 | since the function of these reloads is only to have spill_reg_store etc. | |
1306 | set, so that the storing insn can be deleted later. */ | |
47cfb7f4 | 1307 | gcc_assert (rclass != NO_REGS |
04e579b6 | 1308 | || (optional != 0 && type == RELOAD_FOR_OUTPUT)); |
7ddfb054 | 1309 | |
47cfb7f4 | 1310 | i = find_reusable_reload (&in, out, rclass, type, opnum, dont_share); |
42c63e4d | 1311 | |
1312 | if (i == n_reloads) | |
1313 | { | |
7b9a997f | 1314 | /* See if we need a secondary reload register to move between CLASS |
1315 | and IN or CLASS and OUT. Get the icode and push any required reloads | |
1316 | needed for each of them if so. */ | |
42c63e4d | 1317 | |
42c63e4d | 1318 | if (in != 0) |
7b9a997f | 1319 | secondary_in_reload |
47cfb7f4 | 1320 | = push_secondary_reload (1, in, opnum, optional, rclass, inmode, type, |
4d58fa46 | 1321 | &secondary_in_icode, NULL); |
42c63e4d | 1322 | if (out != 0 && GET_CODE (out) != SCRATCH) |
7b9a997f | 1323 | secondary_out_reload |
47cfb7f4 | 1324 | = push_secondary_reload (0, out, opnum, optional, rclass, outmode, |
4d58fa46 | 1325 | type, &secondary_out_icode, NULL); |
42c63e4d | 1326 | |
1327 | /* We found no existing reload suitable for re-use. | |
1328 | So add an additional reload. */ | |
1329 | ||
0dbd1c74 | 1330 | #ifdef SECONDARY_MEMORY_NEEDED |
1331 | /* If a memory location is needed for the copy, make one. */ | |
b870fa03 | 1332 | if (in != 0 |
1333 | && (REG_P (in) | |
1334 | || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in)))) | |
b627bae7 | 1335 | && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER |
1336 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)), | |
47cfb7f4 | 1337 | rclass, inmode)) |
0dbd1c74 | 1338 | get_secondary_mem (in, inmode, opnum, type); |
1339 | #endif | |
1340 | ||
7b9a997f | 1341 | i = n_reloads; |
48666d2c | 1342 | rld[i].in = in; |
1343 | rld[i].out = out; | |
c32319fc | 1344 | rld[i].rclass = rclass; |
48666d2c | 1345 | rld[i].inmode = inmode; |
1346 | rld[i].outmode = outmode; | |
1347 | rld[i].reg_rtx = 0; | |
1348 | rld[i].optional = optional; | |
48666d2c | 1349 | rld[i].inc = 0; |
1350 | rld[i].nocombine = 0; | |
1351 | rld[i].in_reg = inloc ? *inloc : 0; | |
1352 | rld[i].out_reg = outloc ? *outloc : 0; | |
1353 | rld[i].opnum = opnum; | |
1354 | rld[i].when_needed = type; | |
1355 | rld[i].secondary_in_reload = secondary_in_reload; | |
1356 | rld[i].secondary_out_reload = secondary_out_reload; | |
1357 | rld[i].secondary_in_icode = secondary_in_icode; | |
1358 | rld[i].secondary_out_icode = secondary_out_icode; | |
1359 | rld[i].secondary_p = 0; | |
42c63e4d | 1360 | |
1361 | n_reloads++; | |
c538053c | 1362 | |
1363 | #ifdef SECONDARY_MEMORY_NEEDED | |
b870fa03 | 1364 | if (out != 0 |
1365 | && (REG_P (out) | |
1366 | || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out)))) | |
b627bae7 | 1367 | && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER |
47cfb7f4 | 1368 | && SECONDARY_MEMORY_NEEDED (rclass, |
b627bae7 | 1369 | REGNO_REG_CLASS (reg_or_subregno (out)), |
c538053c | 1370 | outmode)) |
70457512 | 1371 | get_secondary_mem (out, outmode, opnum, type); |
c538053c | 1372 | #endif |
42c63e4d | 1373 | } |
1374 | else | |
1375 | { | |
1376 | /* We are reusing an existing reload, | |
1377 | but we may have additional information for it. | |
1378 | For example, we may now have both IN and OUT | |
1379 | while the old one may have just one of them. */ | |
1380 | ||
4c178649 | 1381 | /* The modes can be different. If they are, we want to reload in |
1382 | the larger mode, so that the value is valid for both modes. */ | |
1383 | if (inmode != VOIDmode | |
48666d2c | 1384 | && GET_MODE_SIZE (inmode) > GET_MODE_SIZE (rld[i].inmode)) |
1385 | rld[i].inmode = inmode; | |
4c178649 | 1386 | if (outmode != VOIDmode |
48666d2c | 1387 | && GET_MODE_SIZE (outmode) > GET_MODE_SIZE (rld[i].outmode)) |
1388 | rld[i].outmode = outmode; | |
42c63e4d | 1389 | if (in != 0) |
93c7b06e | 1390 | { |
beb4ed48 | 1391 | rtx in_reg = inloc ? *inloc : 0; |
93c7b06e | 1392 | /* If we merge reloads for two distinct rtl expressions that |
1393 | are identical in content, there might be duplicate address | |
1394 | reloads. Remove the extra set now, so that if we later find | |
1395 | that we can inherit this reload, we can get rid of the | |
9065e42b | 1396 | address reloads altogether. |
1397 | ||
1398 | Do not do this if both reloads are optional since the result | |
1399 | would be an optional reload which could potentially leave | |
1400 | unresolved address replacements. | |
1401 | ||
1402 | It is not sufficient to call transfer_replacements since | |
1403 | choose_reload_regs will remove the replacements for address | |
1404 | reloads of inherited reloads which results in the same | |
1405 | problem. */ | |
48666d2c | 1406 | if (rld[i].in != in && rtx_equal_p (in, rld[i].in) |
1407 | && ! (rld[i].optional && optional)) | |
93c7b06e | 1408 | { |
1409 | /* We must keep the address reload with the lower operand | |
1410 | number alive. */ | |
48666d2c | 1411 | if (opnum > rld[i].opnum) |
93c7b06e | 1412 | { |
1413 | remove_address_replacements (in); | |
48666d2c | 1414 | in = rld[i].in; |
1415 | in_reg = rld[i].in_reg; | |
93c7b06e | 1416 | } |
1417 | else | |
48666d2c | 1418 | remove_address_replacements (rld[i].in); |
93c7b06e | 1419 | } |
16a3f6b8 | 1420 | /* When emitting reloads we don't necessarily look at the in- |
1421 | and outmode, but also directly at the operands (in and out). | |
1422 | So we can't simply overwrite them with whatever we have found | |
1423 | for this (to-be-merged) reload, we have to "merge" that too. | |
1424 | Reusing another reload already verified that we deal with the | |
1425 | same operands, just possibly in different modes. So we | |
1426 | overwrite the operands only when the new mode is larger. | |
1427 | See also PR33613. */ | |
1428 | if (!rld[i].in | |
1429 | || GET_MODE_SIZE (GET_MODE (in)) | |
1430 | > GET_MODE_SIZE (GET_MODE (rld[i].in))) | |
1431 | rld[i].in = in; | |
1432 | if (!rld[i].in_reg | |
1433 | || (in_reg | |
1434 | && GET_MODE_SIZE (GET_MODE (in_reg)) | |
1435 | > GET_MODE_SIZE (GET_MODE (rld[i].in_reg)))) | |
1436 | rld[i].in_reg = in_reg; | |
93c7b06e | 1437 | } |
42c63e4d | 1438 | if (out != 0) |
93c7b06e | 1439 | { |
16a3f6b8 | 1440 | if (!rld[i].out |
1441 | || (out | |
1442 | && GET_MODE_SIZE (GET_MODE (out)) | |
1443 | > GET_MODE_SIZE (GET_MODE (rld[i].out)))) | |
1444 | rld[i].out = out; | |
1445 | if (outloc | |
1446 | && (!rld[i].out_reg | |
1447 | || GET_MODE_SIZE (GET_MODE (*outloc)) | |
1448 | > GET_MODE_SIZE (GET_MODE (rld[i].out_reg)))) | |
1449 | rld[i].out_reg = *outloc; | |
93c7b06e | 1450 | } |
c32319fc | 1451 | if (reg_class_subset_p (rclass, rld[i].rclass)) |
1452 | rld[i].rclass = rclass; | |
48666d2c | 1453 | rld[i].optional &= optional; |
1454 | if (MERGE_TO_OTHER (type, rld[i].when_needed, | |
1455 | opnum, rld[i].opnum)) | |
1456 | rld[i].when_needed = RELOAD_OTHER; | |
1457 | rld[i].opnum = MIN (rld[i].opnum, opnum); | |
42c63e4d | 1458 | } |
1459 | ||
4822deca | 1460 | /* If the ostensible rtx being reloaded differs from the rtx found |
42c63e4d | 1461 | in the location to substitute, this reload is not safe to combine |
1462 | because we cannot reliably tell whether it appears in the insn. */ | |
1463 | ||
1464 | if (in != 0 && in != *inloc) | |
48666d2c | 1465 | rld[i].nocombine = 1; |
42c63e4d | 1466 | |
1467 | #if 0 | |
1468 | /* This was replaced by changes in find_reloads_address_1 and the new | |
1469 | function inc_for_reload, which go with a new meaning of reload_inc. */ | |
1470 | ||
1471 | /* If this is an IN/OUT reload in an insn that sets the CC, | |
1472 | it must be for an autoincrement. It doesn't work to store | |
1473 | the incremented value after the insn because that would clobber the CC. | |
1474 | So we must do the increment of the value reloaded from, | |
1475 | increment it, store it back, then decrement again. */ | |
1476 | if (out != 0 && sets_cc0_p (PATTERN (this_insn))) | |
1477 | { | |
1478 | out = 0; | |
48666d2c | 1479 | rld[i].out = 0; |
1480 | rld[i].inc = find_inc_amount (PATTERN (this_insn), in); | |
42c63e4d | 1481 | /* If we did not find a nonzero amount-to-increment-by, |
1482 | that contradicts the belief that IN is being incremented | |
1483 | in an address in this insn. */ | |
04e579b6 | 1484 | gcc_assert (rld[i].inc != 0); |
42c63e4d | 1485 | } |
1486 | #endif | |
1487 | ||
1488 | /* If we will replace IN and OUT with the reload-reg, | |
1489 | record where they are located so that substitution need | |
1490 | not do a tree walk. */ | |
1491 | ||
1492 | if (replace_reloads) | |
1493 | { | |
1494 | if (inloc != 0) | |
1495 | { | |
19cb6b50 | 1496 | struct replacement *r = &replacements[n_replacements++]; |
42c63e4d | 1497 | r->what = i; |
42c63e4d | 1498 | r->where = inloc; |
1499 | r->mode = inmode; | |
1500 | } | |
1501 | if (outloc != 0 && outloc != inloc) | |
1502 | { | |
19cb6b50 | 1503 | struct replacement *r = &replacements[n_replacements++]; |
42c63e4d | 1504 | r->what = i; |
1505 | r->where = outloc; | |
42c63e4d | 1506 | r->mode = outmode; |
1507 | } | |
1508 | } | |
1509 | ||
1510 | /* If this reload is just being introduced and it has both | |
1511 | an incoming quantity and an outgoing quantity that are | |
1512 | supposed to be made to match, see if either one of the two | |
1513 | can serve as the place to reload into. | |
1514 | ||
48666d2c | 1515 | If one of them is acceptable, set rld[i].reg_rtx |
42c63e4d | 1516 | to that one. */ |
1517 | ||
48666d2c | 1518 | if (in != 0 && out != 0 && in != out && rld[i].reg_rtx == 0) |
42c63e4d | 1519 | { |
48666d2c | 1520 | rld[i].reg_rtx = find_dummy_reload (in, out, inloc, outloc, |
1521 | inmode, outmode, | |
c32319fc | 1522 | rld[i].rclass, i, |
48666d2c | 1523 | earlyclobber_operand_p (out)); |
42c63e4d | 1524 | |
1525 | /* If the outgoing register already contains the same value | |
1526 | as the incoming one, we can dispense with loading it. | |
1527 | The easiest way to tell the caller that is to give a phony | |
1528 | value for the incoming operand (same as outgoing one). */ | |
48666d2c | 1529 | if (rld[i].reg_rtx == out |
8ad4c111 | 1530 | && (REG_P (in) || CONSTANT_P (in)) |
b9c74b4d | 1531 | && 0 != find_equiv_reg (in, this_insn, NO_REGS, REGNO (out), |
42c63e4d | 1532 | static_reload_reg_p, i, inmode)) |
48666d2c | 1533 | rld[i].in = out; |
42c63e4d | 1534 | } |
1535 | ||
1536 | /* If this is an input reload and the operand contains a register that | |
1537 | dies in this insn and is used nowhere else, see if it is the right class | |
1538 | to be used for this reload. Use it if so. (This occurs most commonly | |
1539 | in the case of paradoxical SUBREGs and in-out reloads). We cannot do | |
1540 | this if it is also an output reload that mentions the register unless | |
1541 | the output is a SUBREG that clobbers an entire register. | |
1542 | ||
1543 | Note that the operand might be one of the spill regs, if it is a | |
1544 | pseudo reg and we are in a block where spilling has not taken place. | |
1545 | But if there is no spilling in this block, that is OK. | |
1546 | An explicitly used hard reg cannot be a spill reg. */ | |
1547 | ||
1ef37f89 | 1548 | if (rld[i].reg_rtx == 0 && in != 0 && hard_regs_live_known) |
42c63e4d | 1549 | { |
1550 | rtx note; | |
1551 | int regno; | |
59c1ea57 | 1552 | enum machine_mode rel_mode = inmode; |
1553 | ||
1554 | if (out && GET_MODE_SIZE (outmode) > GET_MODE_SIZE (inmode)) | |
1555 | rel_mode = outmode; | |
42c63e4d | 1556 | |
1557 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1558 | if (REG_NOTE_KIND (note) == REG_DEAD | |
8ad4c111 | 1559 | && REG_P (XEXP (note, 0)) |
42c63e4d | 1560 | && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER |
1561 | && reg_mentioned_p (XEXP (note, 0), in) | |
0565d6c8 | 1562 | /* Check that a former pseudo is valid; see find_dummy_reload. */ |
1ef37f89 | 1563 | && (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER |
2dd81ece | 1564 | || (! bitmap_bit_p (DF_LR_OUT (ENTRY_BLOCK_PTR), |
47dd2e78 | 1565 | ORIGINAL_REGNO (XEXP (note, 0))) |
0565d6c8 | 1566 | && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] == 1)) |
42c63e4d | 1567 | && ! refers_to_regno_for_reload_p (regno, |
a2c6f0b7 | 1568 | end_hard_regno (rel_mode, |
1569 | regno), | |
42c63e4d | 1570 | PATTERN (this_insn), inloc) |
de61866e | 1571 | /* If this is also an output reload, IN cannot be used as |
1572 | the reload register if it is set in this insn unless IN | |
1573 | is also OUT. */ | |
1574 | && (out == 0 || in == out | |
1575 | || ! hard_reg_set_here_p (regno, | |
a2c6f0b7 | 1576 | end_hard_regno (rel_mode, regno), |
de61866e | 1577 | PATTERN (this_insn))) |
1578 | /* ??? Why is this code so different from the previous? | |
1579 | Is there any simple coherent way to describe the two together? | |
1580 | What's going on here. */ | |
42c63e4d | 1581 | && (in != out |
1582 | || (GET_CODE (in) == SUBREG | |
1583 | && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1)) | |
1584 | / UNITS_PER_WORD) | |
1585 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) | |
1586 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
1587 | /* Make sure the operand fits in the reg that dies. */ | |
59c1ea57 | 1588 | && (GET_MODE_SIZE (rel_mode) |
1589 | <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))) | |
42c63e4d | 1590 | && HARD_REGNO_MODE_OK (regno, inmode) |
d4a0955d | 1591 | && HARD_REGNO_MODE_OK (regno, outmode)) |
42c63e4d | 1592 | { |
785d57a8 | 1593 | unsigned int offs; |
67d6c12b | 1594 | unsigned int nregs = MAX (hard_regno_nregs[regno][inmode], |
1595 | hard_regno_nregs[regno][outmode]); | |
785d57a8 | 1596 | |
d4a0955d | 1597 | for (offs = 0; offs < nregs; offs++) |
1598 | if (fixed_regs[regno + offs] | |
47cfb7f4 | 1599 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], |
d4a0955d | 1600 | regno + offs)) |
1601 | break; | |
1602 | ||
ec6e4b23 | 1603 | if (offs == nregs |
1604 | && (! (refers_to_regno_for_reload_p | |
a2c6f0b7 | 1605 | (regno, end_hard_regno (inmode, regno), in, (rtx *) 0)) |
ec6e4b23 | 1606 | || can_reload_into (in, regno, inmode))) |
d4a0955d | 1607 | { |
59c1ea57 | 1608 | rld[i].reg_rtx = gen_rtx_REG (rel_mode, regno); |
d4a0955d | 1609 | break; |
1610 | } | |
42c63e4d | 1611 | } |
1612 | } | |
1613 | ||
1614 | if (out) | |
1615 | output_reloadnum = i; | |
1616 | ||
1617 | return i; | |
1618 | } | |
1619 | ||
1620 | /* Record an additional place we must replace a value | |
1621 | for which we have already recorded a reload. | |
1622 | RELOADNUM is the value returned by push_reload | |
1623 | when the reload was recorded. | |
1624 | This is used in insn patterns that use match_dup. */ | |
1625 | ||
1626 | static void | |
3ad4992f | 1627 | push_replacement (rtx *loc, int reloadnum, enum machine_mode mode) |
42c63e4d | 1628 | { |
1629 | if (replace_reloads) | |
1630 | { | |
19cb6b50 | 1631 | struct replacement *r = &replacements[n_replacements++]; |
42c63e4d | 1632 | r->what = reloadnum; |
1633 | r->where = loc; | |
42c63e4d | 1634 | r->mode = mode; |
1635 | } | |
1636 | } | |
520be5a2 | 1637 | |
1638 | /* Duplicate any replacement we have recorded to apply at | |
1639 | location ORIG_LOC to also be performed at DUP_LOC. | |
1640 | This is used in insn patterns that use match_dup. */ | |
1641 | ||
1642 | static void | |
3ad4992f | 1643 | dup_replacements (rtx *dup_loc, rtx *orig_loc) |
520be5a2 | 1644 | { |
1645 | int i, n = n_replacements; | |
1646 | ||
1647 | for (i = 0; i < n; i++) | |
1648 | { | |
1649 | struct replacement *r = &replacements[i]; | |
1650 | if (r->where == orig_loc) | |
1651 | push_replacement (dup_loc, r->what, r->mode); | |
1652 | } | |
1653 | } | |
42c63e4d | 1654 | \f |
70457512 | 1655 | /* Transfer all replacements that used to be in reload FROM to be in |
1656 | reload TO. */ | |
1657 | ||
1658 | void | |
3ad4992f | 1659 | transfer_replacements (int to, int from) |
70457512 | 1660 | { |
1661 | int i; | |
1662 | ||
1663 | for (i = 0; i < n_replacements; i++) | |
1664 | if (replacements[i].what == from) | |
1665 | replacements[i].what = to; | |
1666 | } | |
1667 | \f | |
93c7b06e | 1668 | /* IN_RTX is the value loaded by a reload that we now decided to inherit, |
1669 | or a subpart of it. If we have any replacements registered for IN_RTX, | |
1670 | cancel the reloads that were supposed to load them. | |
7fd957fe | 1671 | Return nonzero if we canceled any reloads. */ |
93c7b06e | 1672 | int |
3ad4992f | 1673 | remove_address_replacements (rtx in_rtx) |
524613c6 | 1674 | { |
1675 | int i, j; | |
93c7b06e | 1676 | char reload_flags[MAX_RELOADS]; |
1677 | int something_changed = 0; | |
524613c6 | 1678 | |
93d3b7de | 1679 | memset (reload_flags, 0, sizeof reload_flags); |
524613c6 | 1680 | for (i = 0, j = 0; i < n_replacements; i++) |
1681 | { | |
93c7b06e | 1682 | if (loc_mentioned_in_p (replacements[i].where, in_rtx)) |
1683 | reload_flags[replacements[i].what] |= 1; | |
1684 | else | |
1685 | { | |
1686 | replacements[j++] = replacements[i]; | |
1687 | reload_flags[replacements[i].what] |= 2; | |
1688 | } | |
1689 | } | |
1690 | /* Note that the following store must be done before the recursive calls. */ | |
1691 | n_replacements = j; | |
1692 | ||
1693 | for (i = n_reloads - 1; i >= 0; i--) | |
1694 | { | |
1695 | if (reload_flags[i] == 1) | |
1696 | { | |
1697 | deallocate_reload_reg (i); | |
48666d2c | 1698 | remove_address_replacements (rld[i].in); |
1699 | rld[i].in = 0; | |
93c7b06e | 1700 | something_changed = 1; |
1701 | } | |
1702 | } | |
1703 | return something_changed; | |
1704 | } | |
524613c6 | 1705 | \f |
42c63e4d | 1706 | /* If there is only one output reload, and it is not for an earlyclobber |
1707 | operand, try to combine it with a (logically unrelated) input reload | |
1708 | to reduce the number of reload registers needed. | |
1709 | ||
1710 | This is safe if the input reload does not appear in | |
1711 | the value being output-reloaded, because this implies | |
1712 | it is not needed any more once the original insn completes. | |
1713 | ||
1714 | If that doesn't work, see we can use any of the registers that | |
1715 | die in this insn as a reload register. We can if it is of the right | |
1716 | class and does not appear in the value being output-reloaded. */ | |
1717 | ||
1718 | static void | |
3ad4992f | 1719 | combine_reloads (void) |
42c63e4d | 1720 | { |
0565d6c8 | 1721 | int i, regno; |
42c63e4d | 1722 | int output_reload = -1; |
cd0c2d6d | 1723 | int secondary_out = -1; |
42c63e4d | 1724 | rtx note; |
1725 | ||
1726 | /* Find the output reload; return unless there is exactly one | |
1727 | and that one is mandatory. */ | |
1728 | ||
1729 | for (i = 0; i < n_reloads; i++) | |
48666d2c | 1730 | if (rld[i].out != 0) |
42c63e4d | 1731 | { |
1732 | if (output_reload >= 0) | |
1733 | return; | |
1734 | output_reload = i; | |
1735 | } | |
1736 | ||
48666d2c | 1737 | if (output_reload < 0 || rld[output_reload].optional) |
42c63e4d | 1738 | return; |
1739 | ||
1740 | /* An input-output reload isn't combinable. */ | |
1741 | ||
48666d2c | 1742 | if (rld[output_reload].in != 0) |
42c63e4d | 1743 | return; |
1744 | ||
4bbea254 | 1745 | /* If this reload is for an earlyclobber operand, we can't do anything. */ |
48666d2c | 1746 | if (earlyclobber_operand_p (rld[output_reload].out)) |
3e561fd5 | 1747 | return; |
42c63e4d | 1748 | |
aa0db1ad | 1749 | /* If there is a reload for part of the address of this operand, we would |
f2b32076 | 1750 | need to change it to RELOAD_FOR_OTHER_ADDRESS. But that would extend |
aa0db1ad | 1751 | its life to the point where doing this combine would not lower the |
1752 | number of spill registers needed. */ | |
1753 | for (i = 0; i < n_reloads; i++) | |
1754 | if ((rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
1755 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
1756 | && rld[i].opnum == rld[output_reload].opnum) | |
1757 | return; | |
1758 | ||
42c63e4d | 1759 | /* Check each input reload; can we combine it? */ |
1760 | ||
1761 | for (i = 0; i < n_reloads; i++) | |
48666d2c | 1762 | if (rld[i].in && ! rld[i].optional && ! rld[i].nocombine |
42c63e4d | 1763 | /* Life span of this reload must not extend past main insn. */ |
48666d2c | 1764 | && rld[i].when_needed != RELOAD_FOR_OUTPUT_ADDRESS |
1765 | && rld[i].when_needed != RELOAD_FOR_OUTADDR_ADDRESS | |
1766 | && rld[i].when_needed != RELOAD_OTHER | |
d3ba22dc | 1767 | && (ira_reg_class_max_nregs [(int)rld[i].rclass][(int) rld[i].inmode] |
1768 | == ira_reg_class_max_nregs [(int) rld[output_reload].rclass] | |
1769 | [(int) rld[output_reload].outmode]) | |
48666d2c | 1770 | && rld[i].inc == 0 |
1771 | && rld[i].reg_rtx == 0 | |
70457512 | 1772 | #ifdef SECONDARY_MEMORY_NEEDED |
7b9a997f | 1773 | /* Don't combine two reloads with different secondary |
1774 | memory locations. */ | |
48666d2c | 1775 | && (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum] == 0 |
1776 | || secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum] == 0 | |
1777 | || rtx_equal_p (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum], | |
1778 | secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum])) | |
70457512 | 1779 | #endif |
ed5527ca | 1780 | && (targetm.small_register_classes_for_mode_p (VOIDmode) |
c32319fc | 1781 | ? (rld[i].rclass == rld[output_reload].rclass) |
1782 | : (reg_class_subset_p (rld[i].rclass, | |
1783 | rld[output_reload].rclass) | |
1784 | || reg_class_subset_p (rld[output_reload].rclass, | |
1785 | rld[i].rclass))) | |
48666d2c | 1786 | && (MATCHES (rld[i].in, rld[output_reload].out) |
42c63e4d | 1787 | /* Args reversed because the first arg seems to be |
1788 | the one that we imagine being modified | |
1789 | while the second is the one that might be affected. */ | |
48666d2c | 1790 | || (! reg_overlap_mentioned_for_reload_p (rld[output_reload].out, |
1791 | rld[i].in) | |
42c63e4d | 1792 | /* However, if the input is a register that appears inside |
1793 | the output, then we also can't share. | |
1794 | Imagine (set (mem (reg 69)) (plus (reg 69) ...)). | |
1795 | If the same reload reg is used for both reg 69 and the | |
1796 | result to be stored in memory, then that result | |
1797 | will clobber the address of the memory ref. */ | |
8ad4c111 | 1798 | && ! (REG_P (rld[i].in) |
48666d2c | 1799 | && reg_overlap_mentioned_for_reload_p (rld[i].in, |
1800 | rld[output_reload].out)))) | |
6ac19489 | 1801 | && ! reload_inner_reg_of_subreg (rld[i].in, rld[i].inmode, |
1802 | rld[i].when_needed != RELOAD_FOR_INPUT) | |
c32319fc | 1803 | && (reg_class_size[(int) rld[i].rclass] |
ed5527ca | 1804 | || targetm.small_register_classes_for_mode_p (VOIDmode)) |
70457512 | 1805 | /* We will allow making things slightly worse by combining an |
1806 | input and an output, but no worse than that. */ | |
48666d2c | 1807 | && (rld[i].when_needed == RELOAD_FOR_INPUT |
1808 | || rld[i].when_needed == RELOAD_FOR_OUTPUT)) | |
42c63e4d | 1809 | { |
1810 | int j; | |
1811 | ||
1812 | /* We have found a reload to combine with! */ | |
48666d2c | 1813 | rld[i].out = rld[output_reload].out; |
1814 | rld[i].out_reg = rld[output_reload].out_reg; | |
1815 | rld[i].outmode = rld[output_reload].outmode; | |
42c63e4d | 1816 | /* Mark the old output reload as inoperative. */ |
48666d2c | 1817 | rld[output_reload].out = 0; |
42c63e4d | 1818 | /* The combined reload is needed for the entire insn. */ |
48666d2c | 1819 | rld[i].when_needed = RELOAD_OTHER; |
a92771b8 | 1820 | /* If the output reload had a secondary reload, copy it. */ |
48666d2c | 1821 | if (rld[output_reload].secondary_out_reload != -1) |
7b9a997f | 1822 | { |
48666d2c | 1823 | rld[i].secondary_out_reload |
1824 | = rld[output_reload].secondary_out_reload; | |
1825 | rld[i].secondary_out_icode | |
1826 | = rld[output_reload].secondary_out_icode; | |
7b9a997f | 1827 | } |
1828 | ||
70457512 | 1829 | #ifdef SECONDARY_MEMORY_NEEDED |
1830 | /* Copy any secondary MEM. */ | |
48666d2c | 1831 | if (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum] != 0) |
1832 | secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum] | |
1833 | = secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum]; | |
70457512 | 1834 | #endif |
a92771b8 | 1835 | /* If required, minimize the register class. */ |
c32319fc | 1836 | if (reg_class_subset_p (rld[output_reload].rclass, |
1837 | rld[i].rclass)) | |
1838 | rld[i].rclass = rld[output_reload].rclass; | |
42c63e4d | 1839 | |
1840 | /* Transfer all replacements from the old reload to the combined. */ | |
1841 | for (j = 0; j < n_replacements; j++) | |
1842 | if (replacements[j].what == output_reload) | |
1843 | replacements[j].what = i; | |
1844 | ||
1845 | return; | |
1846 | } | |
1847 | ||
1848 | /* If this insn has only one operand that is modified or written (assumed | |
1849 | to be the first), it must be the one corresponding to this reload. It | |
1850 | is safe to use anything that dies in this insn for that output provided | |
1851 | that it does not occur in the output (we already know it isn't an | |
1852 | earlyclobber. If this is an asm insn, give up. */ | |
1853 | ||
c6649d6f | 1854 | if (INSN_CODE (this_insn) == -1) |
42c63e4d | 1855 | return; |
1856 | ||
6357eaae | 1857 | for (i = 1; i < insn_data[INSN_CODE (this_insn)].n_operands; i++) |
1858 | if (insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '=' | |
1859 | || insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '+') | |
42c63e4d | 1860 | return; |
1861 | ||
1862 | /* See if some hard register that dies in this insn and is not used in | |
1863 | the output is the right class. Only works if the register we pick | |
1864 | up can fully hold our output reload. */ | |
1865 | for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) | |
1866 | if (REG_NOTE_KIND (note) == REG_DEAD | |
8ad4c111 | 1867 | && REG_P (XEXP (note, 0)) |
0565d6c8 | 1868 | && !reg_overlap_mentioned_for_reload_p (XEXP (note, 0), |
1869 | rld[output_reload].out) | |
1870 | && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER | |
1871 | && HARD_REGNO_MODE_OK (regno, rld[output_reload].outmode) | |
c32319fc | 1872 | && TEST_HARD_REG_BIT (reg_class_contents[(int) rld[output_reload].rclass], |
0565d6c8 | 1873 | regno) |
1874 | && (hard_regno_nregs[regno][rld[output_reload].outmode] | |
1875 | <= hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))]) | |
cd0c2d6d | 1876 | /* Ensure that a secondary or tertiary reload for this output |
1877 | won't want this register. */ | |
48666d2c | 1878 | && ((secondary_out = rld[output_reload].secondary_out_reload) == -1 |
0565d6c8 | 1879 | || (!(TEST_HARD_REG_BIT |
c32319fc | 1880 | (reg_class_contents[(int) rld[secondary_out].rclass], regno)) |
48666d2c | 1881 | && ((secondary_out = rld[secondary_out].secondary_out_reload) == -1 |
0565d6c8 | 1882 | || !(TEST_HARD_REG_BIT |
c32319fc | 1883 | (reg_class_contents[(int) rld[secondary_out].rclass], |
0565d6c8 | 1884 | regno))))) |
1885 | && !fixed_regs[regno] | |
1886 | /* Check that a former pseudo is valid; see find_dummy_reload. */ | |
efb8c784 | 1887 | && (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER |
0565d6c8 | 1888 | || (!bitmap_bit_p (DF_LR_OUT (ENTRY_BLOCK_PTR), |
1889 | ORIGINAL_REGNO (XEXP (note, 0))) | |
1890 | && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] == 1))) | |
42c63e4d | 1891 | { |
48666d2c | 1892 | rld[output_reload].reg_rtx |
0565d6c8 | 1893 | = gen_rtx_REG (rld[output_reload].outmode, regno); |
42c63e4d | 1894 | return; |
1895 | } | |
1896 | } | |
1897 | \f | |
1898 | /* Try to find a reload register for an in-out reload (expressions IN and OUT). | |
1899 | See if one of IN and OUT is a register that may be used; | |
1900 | this is desirable since a spill-register won't be needed. | |
1901 | If so, return the register rtx that proves acceptable. | |
1902 | ||
1903 | INLOC and OUTLOC are locations where IN and OUT appear in the insn. | |
47cfb7f4 | 1904 | RCLASS is the register class required for the reload. |
42c63e4d | 1905 | |
1906 | If FOR_REAL is >= 0, it is the number of the reload, | |
1907 | and in some cases when it can be discovered that OUT doesn't need | |
48666d2c | 1908 | to be computed, clear out rld[FOR_REAL].out. |
42c63e4d | 1909 | |
1910 | If FOR_REAL is -1, this should not be done, because this call | |
2f39ee7a | 1911 | is just to see if a register can be found, not to find and install it. |
1912 | ||
7fd957fe | 1913 | EARLYCLOBBER is nonzero if OUT is an earlyclobber operand. This |
2f39ee7a | 1914 | puts an additional constraint on being able to use IN for OUT since |
1915 | IN must not appear elsewhere in the insn (it is assumed that IN itself | |
1916 | is safe from the earlyclobber). */ | |
42c63e4d | 1917 | |
1918 | static rtx | |
3ad4992f | 1919 | find_dummy_reload (rtx real_in, rtx real_out, rtx *inloc, rtx *outloc, |
1920 | enum machine_mode inmode, enum machine_mode outmode, | |
71db0d8b | 1921 | reg_class_t rclass, int for_real, int earlyclobber) |
42c63e4d | 1922 | { |
1923 | rtx in = real_in; | |
1924 | rtx out = real_out; | |
1925 | int in_offset = 0; | |
1926 | int out_offset = 0; | |
1927 | rtx value = 0; | |
1928 | ||
1929 | /* If operands exceed a word, we can't use either of them | |
1930 | unless they have the same size. */ | |
1b224b20 | 1931 | if (GET_MODE_SIZE (outmode) != GET_MODE_SIZE (inmode) |
1932 | && (GET_MODE_SIZE (outmode) > UNITS_PER_WORD | |
1933 | || GET_MODE_SIZE (inmode) > UNITS_PER_WORD)) | |
42c63e4d | 1934 | return 0; |
1935 | ||
701e46d0 | 1936 | /* Note that {in,out}_offset are needed only when 'in' or 'out' |
1937 | respectively refers to a hard register. */ | |
1938 | ||
42c63e4d | 1939 | /* Find the inside of any subregs. */ |
1940 | while (GET_CODE (out) == SUBREG) | |
1941 | { | |
8ad4c111 | 1942 | if (REG_P (SUBREG_REG (out)) |
701e46d0 | 1943 | && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER) |
1944 | out_offset += subreg_regno_offset (REGNO (SUBREG_REG (out)), | |
1945 | GET_MODE (SUBREG_REG (out)), | |
1946 | SUBREG_BYTE (out), | |
1947 | GET_MODE (out)); | |
42c63e4d | 1948 | out = SUBREG_REG (out); |
1949 | } | |
1950 | while (GET_CODE (in) == SUBREG) | |
1951 | { | |
8ad4c111 | 1952 | if (REG_P (SUBREG_REG (in)) |
701e46d0 | 1953 | && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER) |
1954 | in_offset += subreg_regno_offset (REGNO (SUBREG_REG (in)), | |
1955 | GET_MODE (SUBREG_REG (in)), | |
1956 | SUBREG_BYTE (in), | |
1957 | GET_MODE (in)); | |
42c63e4d | 1958 | in = SUBREG_REG (in); |
1959 | } | |
1960 | ||
1961 | /* Narrow down the reg class, the same way push_reload will; | |
1962 | otherwise we might find a dummy now, but push_reload won't. */ | |
897f76b2 | 1963 | { |
09a17585 | 1964 | reg_class_t preferred_class = targetm.preferred_reload_class (in, rclass); |
7781f014 | 1965 | if (preferred_class != NO_REGS) |
09a17585 | 1966 | rclass = (enum reg_class) preferred_class; |
897f76b2 | 1967 | } |
42c63e4d | 1968 | |
1969 | /* See if OUT will do. */ | |
8ad4c111 | 1970 | if (REG_P (out) |
42c63e4d | 1971 | && REGNO (out) < FIRST_PSEUDO_REGISTER) |
1972 | { | |
02e7a332 | 1973 | unsigned int regno = REGNO (out) + out_offset; |
67d6c12b | 1974 | unsigned int nwords = hard_regno_nregs[regno][outmode]; |
eb1e4177 | 1975 | rtx saved_rtx; |
42c63e4d | 1976 | |
1977 | /* When we consider whether the insn uses OUT, | |
1978 | ignore references within IN. They don't prevent us | |
1979 | from copying IN into OUT, because those refs would | |
1980 | move into the insn that reloads IN. | |
1981 | ||
1982 | However, we only ignore IN in its role as this reload. | |
1983 | If the insn uses IN elsewhere and it contains OUT, | |
1984 | that counts. We can't be sure it's the "same" operand | |
1985 | so it might not go through this reload. */ | |
eb1e4177 | 1986 | saved_rtx = *inloc; |
42c63e4d | 1987 | *inloc = const0_rtx; |
1988 | ||
1989 | if (regno < FIRST_PSEUDO_REGISTER | |
b2656069 | 1990 | && HARD_REGNO_MODE_OK (regno, outmode) |
42c63e4d | 1991 | && ! refers_to_regno_for_reload_p (regno, regno + nwords, |
1992 | PATTERN (this_insn), outloc)) | |
1993 | { | |
02e7a332 | 1994 | unsigned int i; |
1995 | ||
42c63e4d | 1996 | for (i = 0; i < nwords; i++) |
47cfb7f4 | 1997 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], |
42c63e4d | 1998 | regno + i)) |
1999 | break; | |
2000 | ||
2001 | if (i == nwords) | |
2002 | { | |
8ad4c111 | 2003 | if (REG_P (real_out)) |
42c63e4d | 2004 | value = real_out; |
2005 | else | |
941522d6 | 2006 | value = gen_rtx_REG (outmode, regno); |
42c63e4d | 2007 | } |
2008 | } | |
2009 | ||
eb1e4177 | 2010 | *inloc = saved_rtx; |
42c63e4d | 2011 | } |
2012 | ||
2013 | /* Consider using IN if OUT was not acceptable | |
2014 | or if OUT dies in this insn (like the quotient in a divmod insn). | |
2015 | We can't use IN unless it is dies in this insn, | |
2016 | which means we must know accurately which hard regs are live. | |
2f39ee7a | 2017 | Also, the result can't go in IN if IN is used within OUT, |
2018 | or if OUT is an earlyclobber and IN appears elsewhere in the insn. */ | |
42c63e4d | 2019 | if (hard_regs_live_known |
8ad4c111 | 2020 | && REG_P (in) |
42c63e4d | 2021 | && REGNO (in) < FIRST_PSEUDO_REGISTER |
2022 | && (value == 0 | |
2023 | || find_reg_note (this_insn, REG_UNUSED, real_out)) | |
2024 | && find_reg_note (this_insn, REG_DEAD, real_in) | |
2025 | && !fixed_regs[REGNO (in)] | |
1b224b20 | 2026 | && HARD_REGNO_MODE_OK (REGNO (in), |
2027 | /* The only case where out and real_out might | |
2028 | have different modes is where real_out | |
2029 | is a subreg, and in that case, out | |
2030 | has a real mode. */ | |
2031 | (GET_MODE (out) != VOIDmode | |
1ef37f89 | 2032 | ? GET_MODE (out) : outmode)) |
1ef37f89 | 2033 | && (ORIGINAL_REGNO (in) < FIRST_PSEUDO_REGISTER |
0565d6c8 | 2034 | /* However only do this if we can be sure that this input |
2035 | operand doesn't correspond with an uninitialized pseudo. | |
2036 | global can assign some hardreg to it that is the same as | |
2037 | the one assigned to a different, also live pseudo (as it | |
2038 | can ignore the conflict). We must never introduce writes | |
2039 | to such hardregs, as they would clobber the other live | |
2040 | pseudo. See PR 20973. */ | |
2dd81ece | 2041 | || (!bitmap_bit_p (DF_LR_OUT (ENTRY_BLOCK_PTR), |
0565d6c8 | 2042 | ORIGINAL_REGNO (in)) |
2043 | /* Similarly, only do this if we can be sure that the death | |
2044 | note is still valid. global can assign some hardreg to | |
2045 | the pseudo referenced in the note and simultaneously a | |
2046 | subword of this hardreg to a different, also live pseudo, | |
2047 | because only another subword of the hardreg is actually | |
2048 | used in the insn. This cannot happen if the pseudo has | |
2049 | been assigned exactly one hardreg. See PR 33732. */ | |
2050 | && hard_regno_nregs[REGNO (in)][GET_MODE (in)] == 1))) | |
42c63e4d | 2051 | { |
02e7a332 | 2052 | unsigned int regno = REGNO (in) + in_offset; |
67d6c12b | 2053 | unsigned int nwords = hard_regno_nregs[regno][inmode]; |
42c63e4d | 2054 | |
33181afc | 2055 | if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, (rtx*) 0) |
42c63e4d | 2056 | && ! hard_reg_set_here_p (regno, regno + nwords, |
2f39ee7a | 2057 | PATTERN (this_insn)) |
2058 | && (! earlyclobber | |
2059 | || ! refers_to_regno_for_reload_p (regno, regno + nwords, | |
2060 | PATTERN (this_insn), inloc))) | |
42c63e4d | 2061 | { |
02e7a332 | 2062 | unsigned int i; |
2063 | ||
42c63e4d | 2064 | for (i = 0; i < nwords; i++) |
47cfb7f4 | 2065 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], |
42c63e4d | 2066 | regno + i)) |
2067 | break; | |
2068 | ||
2069 | if (i == nwords) | |
2070 | { | |
2071 | /* If we were going to use OUT as the reload reg | |
2072 | and changed our mind, it means OUT is a dummy that | |
2073 | dies here. So don't bother copying value to it. */ | |
2074 | if (for_real >= 0 && value == real_out) | |
48666d2c | 2075 | rld[for_real].out = 0; |
8ad4c111 | 2076 | if (REG_P (real_in)) |
42c63e4d | 2077 | value = real_in; |
2078 | else | |
941522d6 | 2079 | value = gen_rtx_REG (inmode, regno); |
42c63e4d | 2080 | } |
2081 | } | |
2082 | } | |
2083 | ||
2084 | return value; | |
2085 | } | |
2086 | \f | |
2087 | /* This page contains subroutines used mainly for determining | |
2088 | whether the IN or an OUT of a reload can serve as the | |
2089 | reload register. */ | |
2090 | ||
3e561fd5 | 2091 | /* Return 1 if X is an operand of an insn that is being earlyclobbered. */ |
2092 | ||
92c7a85c | 2093 | int |
3ad4992f | 2094 | earlyclobber_operand_p (rtx x) |
3e561fd5 | 2095 | { |
2096 | int i; | |
2097 | ||
2098 | for (i = 0; i < n_earlyclobbers; i++) | |
2099 | if (reload_earlyclobbers[i] == x) | |
2100 | return 1; | |
2101 | ||
2102 | return 0; | |
2103 | } | |
2104 | ||
42c63e4d | 2105 | /* Return 1 if expression X alters a hard reg in the range |
2106 | from BEG_REGNO (inclusive) to END_REGNO (exclusive), | |
2107 | either explicitly or in the guise of a pseudo-reg allocated to REGNO. | |
2108 | X should be the body of an instruction. */ | |
2109 | ||
2110 | static int | |
3ad4992f | 2111 | hard_reg_set_here_p (unsigned int beg_regno, unsigned int end_regno, rtx x) |
42c63e4d | 2112 | { |
2113 | if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
2114 | { | |
19cb6b50 | 2115 | rtx op0 = SET_DEST (x); |
02e7a332 | 2116 | |
42c63e4d | 2117 | while (GET_CODE (op0) == SUBREG) |
2118 | op0 = SUBREG_REG (op0); | |
8ad4c111 | 2119 | if (REG_P (op0)) |
42c63e4d | 2120 | { |
02e7a332 | 2121 | unsigned int r = REGNO (op0); |
2122 | ||
42c63e4d | 2123 | /* See if this reg overlaps range under consideration. */ |
2124 | if (r < end_regno | |
a2c6f0b7 | 2125 | && end_hard_regno (GET_MODE (op0), r) > beg_regno) |
42c63e4d | 2126 | return 1; |
2127 | } | |
2128 | } | |
2129 | else if (GET_CODE (x) == PARALLEL) | |
2130 | { | |
19cb6b50 | 2131 | int i = XVECLEN (x, 0) - 1; |
02e7a332 | 2132 | |
42c63e4d | 2133 | for (; i >= 0; i--) |
2134 | if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i))) | |
2135 | return 1; | |
2136 | } | |
2137 | ||
2138 | return 0; | |
2139 | } | |
2140 | ||
bd1a81f7 | 2141 | /* Return 1 if ADDR is a valid memory address for mode MODE |
2142 | in address space AS, and check that each pseudo reg has the | |
2143 | proper kind of hard reg. */ | |
42c63e4d | 2144 | |
2145 | int | |
bd1a81f7 | 2146 | strict_memory_address_addr_space_p (enum machine_mode mode ATTRIBUTE_UNUSED, |
2147 | rtx addr, addr_space_t as) | |
42c63e4d | 2148 | { |
fd50b071 | 2149 | #ifdef GO_IF_LEGITIMATE_ADDRESS |
bd1a81f7 | 2150 | gcc_assert (ADDR_SPACE_GENERIC_P (as)); |
42c63e4d | 2151 | GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); |
2152 | return 0; | |
2153 | ||
2154 | win: | |
2155 | return 1; | |
fd50b071 | 2156 | #else |
bd1a81f7 | 2157 | return targetm.addr_space.legitimate_address_p (mode, addr, 1, as); |
fd50b071 | 2158 | #endif |
42c63e4d | 2159 | } |
42c63e4d | 2160 | \f |
2161 | /* Like rtx_equal_p except that it allows a REG and a SUBREG to match | |
2162 | if they are the same hard reg, and has special hacks for | |
2163 | autoincrement and autodecrement. | |
2164 | This is specifically intended for find_reloads to use | |
2165 | in determining whether two operands match. | |
2166 | X is the operand whose number is the lower of the two. | |
2167 | ||
2168 | The value is 2 if Y contains a pre-increment that matches | |
2169 | a non-incrementing address in X. */ | |
2170 | ||
2171 | /* ??? To be completely correct, we should arrange to pass | |
2172 | for X the output operand and for Y the input operand. | |
2173 | For now, we assume that the output operand has the lower number | |
2174 | because that is natural in (SET output (... input ...)). */ | |
2175 | ||
2176 | int | |
3ad4992f | 2177 | operands_match_p (rtx x, rtx y) |
42c63e4d | 2178 | { |
19cb6b50 | 2179 | int i; |
2180 | RTX_CODE code = GET_CODE (x); | |
2181 | const char *fmt; | |
42c63e4d | 2182 | int success_2; |
5bb2f919 | 2183 | |
42c63e4d | 2184 | if (x == y) |
2185 | return 1; | |
8ad4c111 | 2186 | if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) |
2187 | && (REG_P (y) || (GET_CODE (y) == SUBREG | |
2188 | && REG_P (SUBREG_REG (y))))) | |
42c63e4d | 2189 | { |
19cb6b50 | 2190 | int j; |
42c63e4d | 2191 | |
2192 | if (code == SUBREG) | |
2193 | { | |
2194 | i = REGNO (SUBREG_REG (x)); | |
2195 | if (i >= FIRST_PSEUDO_REGISTER) | |
2196 | goto slow; | |
701e46d0 | 2197 | i += subreg_regno_offset (REGNO (SUBREG_REG (x)), |
2198 | GET_MODE (SUBREG_REG (x)), | |
2199 | SUBREG_BYTE (x), | |
2200 | GET_MODE (x)); | |
42c63e4d | 2201 | } |
2202 | else | |
2203 | i = REGNO (x); | |
2204 | ||
2205 | if (GET_CODE (y) == SUBREG) | |
2206 | { | |
2207 | j = REGNO (SUBREG_REG (y)); | |
2208 | if (j >= FIRST_PSEUDO_REGISTER) | |
2209 | goto slow; | |
701e46d0 | 2210 | j += subreg_regno_offset (REGNO (SUBREG_REG (y)), |
2211 | GET_MODE (SUBREG_REG (y)), | |
2212 | SUBREG_BYTE (y), | |
2213 | GET_MODE (y)); | |
42c63e4d | 2214 | } |
2215 | else | |
2216 | j = REGNO (y); | |
2217 | ||
76c64076 | 2218 | /* On a REG_WORDS_BIG_ENDIAN machine, point to the last register of a |
627decb0 | 2219 | multiple hard register group of scalar integer registers, so that |
2220 | for example (reg:DI 0) and (reg:SI 1) will be considered the same | |
2221 | register. */ | |
76c64076 | 2222 | if (REG_WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD |
627decb0 | 2223 | && SCALAR_INT_MODE_P (GET_MODE (x)) |
98c941f7 | 2224 | && i < FIRST_PSEUDO_REGISTER) |
67d6c12b | 2225 | i += hard_regno_nregs[i][GET_MODE (x)] - 1; |
76c64076 | 2226 | if (REG_WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (y)) > UNITS_PER_WORD |
627decb0 | 2227 | && SCALAR_INT_MODE_P (GET_MODE (y)) |
98c941f7 | 2228 | && j < FIRST_PSEUDO_REGISTER) |
67d6c12b | 2229 | j += hard_regno_nregs[j][GET_MODE (y)] - 1; |
98c941f7 | 2230 | |
42c63e4d | 2231 | return i == j; |
2232 | } | |
2233 | /* If two operands must match, because they are really a single | |
2234 | operand of an assembler insn, then two postincrements are invalid | |
2235 | because the assembler insn would increment only once. | |
edc2a478 | 2236 | On the other hand, a postincrement matches ordinary indexing |
42c63e4d | 2237 | if the postincrement is the output operand. */ |
40988080 | 2238 | if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) |
42c63e4d | 2239 | return operands_match_p (XEXP (x, 0), y); |
2240 | /* Two preincrements are invalid | |
2241 | because the assembler insn would increment only once. | |
edc2a478 | 2242 | On the other hand, a preincrement matches ordinary indexing |
42c63e4d | 2243 | if the preincrement is the input operand. |
2244 | In this case, return 2, since some callers need to do special | |
2245 | things when this happens. */ | |
40988080 | 2246 | if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC |
2247 | || GET_CODE (y) == PRE_MODIFY) | |
42c63e4d | 2248 | return operands_match_p (x, XEXP (y, 0)) ? 2 : 0; |
2249 | ||
2250 | slow: | |
2251 | ||
d618034b | 2252 | /* Now we have disposed of all the cases in which different rtx codes |
2253 | can match. */ | |
42c63e4d | 2254 | if (code != GET_CODE (y)) |
2255 | return 0; | |
42c63e4d | 2256 | |
2257 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
42c63e4d | 2258 | if (GET_MODE (x) != GET_MODE (y)) |
2259 | return 0; | |
2260 | ||
bd1a81f7 | 2261 | /* MEMs refering to different address space are not equivalent. */ |
2262 | if (code == MEM && MEM_ADDR_SPACE (x) != MEM_ADDR_SPACE (y)) | |
2263 | return 0; | |
2264 | ||
d618034b | 2265 | switch (code) |
2266 | { | |
2267 | case CONST_INT: | |
2268 | case CONST_DOUBLE: | |
e397ad8e | 2269 | case CONST_FIXED: |
d618034b | 2270 | return 0; |
2271 | ||
2272 | case LABEL_REF: | |
2273 | return XEXP (x, 0) == XEXP (y, 0); | |
2274 | case SYMBOL_REF: | |
2275 | return XSTR (x, 0) == XSTR (y, 0); | |
2276 | ||
2277 | default: | |
2278 | break; | |
2279 | } | |
2280 | ||
42c63e4d | 2281 | /* Compare the elements. If any pair of corresponding elements |
2282 | fail to match, return 0 for the whole things. */ | |
2283 | ||
2284 | success_2 = 0; | |
2285 | fmt = GET_RTX_FORMAT (code); | |
2286 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2287 | { | |
4e39a270 | 2288 | int val, j; |
42c63e4d | 2289 | switch (fmt[i]) |
2290 | { | |
e5fdd564 | 2291 | case 'w': |
2292 | if (XWINT (x, i) != XWINT (y, i)) | |
2293 | return 0; | |
2294 | break; | |
2295 | ||
42c63e4d | 2296 | case 'i': |
2297 | if (XINT (x, i) != XINT (y, i)) | |
2298 | return 0; | |
2299 | break; | |
2300 | ||
2301 | case 'e': | |
2302 | val = operands_match_p (XEXP (x, i), XEXP (y, i)); | |
2303 | if (val == 0) | |
2304 | return 0; | |
2305 | /* If any subexpression returns 2, | |
2306 | we should return 2 if we are successful. */ | |
2307 | if (val == 2) | |
2308 | success_2 = 1; | |
2309 | break; | |
2310 | ||
2311 | case '0': | |
2312 | break; | |
2313 | ||
4e39a270 | 2314 | case 'E': |
2315 | if (XVECLEN (x, i) != XVECLEN (y, i)) | |
2316 | return 0; | |
2317 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
2318 | { | |
2319 | val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j)); | |
2320 | if (val == 0) | |
2321 | return 0; | |
2322 | if (val == 2) | |
2323 | success_2 = 1; | |
2324 | } | |
2325 | break; | |
2326 | ||
42c63e4d | 2327 | /* It is believed that rtx's at this level will never |
2328 | contain anything but integers and other rtx's, | |
2329 | except for within LABEL_REFs and SYMBOL_REFs. */ | |
2330 | default: | |
04e579b6 | 2331 | gcc_unreachable (); |
42c63e4d | 2332 | } |
2333 | } | |
2334 | return 1 + success_2; | |
2335 | } | |
2336 | \f | |
42c63e4d | 2337 | /* Describe the range of registers or memory referenced by X. |
5bb2f919 | 2338 | If X is a register, set REG_FLAG and put the first register |
42c63e4d | 2339 | number into START and the last plus one into END. |
5bb2f919 | 2340 | If X is a memory reference, put a base address into BASE |
42c63e4d | 2341 | and a range of integer offsets into START and END. |
5bb2f919 | 2342 | If X is pushing on the stack, we can assume it causes no trouble, |
42c63e4d | 2343 | so we set the SAFE field. */ |
2344 | ||
2345 | static struct decomposition | |
3ad4992f | 2346 | decompose (rtx x) |
42c63e4d | 2347 | { |
2348 | struct decomposition val; | |
2349 | int all_const = 0; | |
2350 | ||
4ee9c684 | 2351 | memset (&val, 0, sizeof (val)); |
2352 | ||
04e579b6 | 2353 | switch (GET_CODE (x)) |
42c63e4d | 2354 | { |
04e579b6 | 2355 | case MEM: |
2356 | { | |
2357 | rtx base = NULL_RTX, offset = 0; | |
2358 | rtx addr = XEXP (x, 0); | |
48e1416a | 2359 | |
04e579b6 | 2360 | if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC |
2361 | || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC) | |
2362 | { | |
2363 | val.base = XEXP (addr, 0); | |
2364 | val.start = -GET_MODE_SIZE (GET_MODE (x)); | |
2365 | val.end = GET_MODE_SIZE (GET_MODE (x)); | |
2366 | val.safe = REGNO (val.base) == STACK_POINTER_REGNUM; | |
2367 | return val; | |
2368 | } | |
48e1416a | 2369 | |
04e579b6 | 2370 | if (GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY) |
2371 | { | |
2372 | if (GET_CODE (XEXP (addr, 1)) == PLUS | |
2373 | && XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0) | |
2374 | && CONSTANT_P (XEXP (XEXP (addr, 1), 1))) | |
2375 | { | |
2376 | val.base = XEXP (addr, 0); | |
2377 | val.start = -INTVAL (XEXP (XEXP (addr, 1), 1)); | |
2378 | val.end = INTVAL (XEXP (XEXP (addr, 1), 1)); | |
2379 | val.safe = REGNO (val.base) == STACK_POINTER_REGNUM; | |
2380 | return val; | |
2381 | } | |
2382 | } | |
48e1416a | 2383 | |
04e579b6 | 2384 | if (GET_CODE (addr) == CONST) |
2385 | { | |
2386 | addr = XEXP (addr, 0); | |
2387 | all_const = 1; | |
2388 | } | |
2389 | if (GET_CODE (addr) == PLUS) | |
2390 | { | |
2391 | if (CONSTANT_P (XEXP (addr, 0))) | |
2392 | { | |
2393 | base = XEXP (addr, 1); | |
2394 | offset = XEXP (addr, 0); | |
2395 | } | |
2396 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2397 | { | |
2398 | base = XEXP (addr, 0); | |
2399 | offset = XEXP (addr, 1); | |
2400 | } | |
2401 | } | |
48e1416a | 2402 | |
04e579b6 | 2403 | if (offset == 0) |
2404 | { | |
2405 | base = addr; | |
2406 | offset = const0_rtx; | |
2407 | } | |
2408 | if (GET_CODE (offset) == CONST) | |
2409 | offset = XEXP (offset, 0); | |
2410 | if (GET_CODE (offset) == PLUS) | |
2411 | { | |
971ba038 | 2412 | if (CONST_INT_P (XEXP (offset, 0))) |
04e579b6 | 2413 | { |
2414 | base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 1)); | |
2415 | offset = XEXP (offset, 0); | |
2416 | } | |
971ba038 | 2417 | else if (CONST_INT_P (XEXP (offset, 1))) |
04e579b6 | 2418 | { |
2419 | base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 0)); | |
2420 | offset = XEXP (offset, 1); | |
2421 | } | |
2422 | else | |
2423 | { | |
2424 | base = gen_rtx_PLUS (GET_MODE (base), base, offset); | |
2425 | offset = const0_rtx; | |
2426 | } | |
2427 | } | |
971ba038 | 2428 | else if (!CONST_INT_P (offset)) |
04e579b6 | 2429 | { |
2430 | base = gen_rtx_PLUS (GET_MODE (base), base, offset); | |
2431 | offset = const0_rtx; | |
2432 | } | |
48e1416a | 2433 | |
04e579b6 | 2434 | if (all_const && GET_CODE (base) == PLUS) |
2435 | base = gen_rtx_CONST (GET_MODE (base), base); | |
48e1416a | 2436 | |
971ba038 | 2437 | gcc_assert (CONST_INT_P (offset)); |
48e1416a | 2438 | |
04e579b6 | 2439 | val.start = INTVAL (offset); |
2440 | val.end = val.start + GET_MODE_SIZE (GET_MODE (x)); | |
2441 | val.base = base; | |
2442 | } | |
2443 | break; | |
48e1416a | 2444 | |
04e579b6 | 2445 | case REG: |
42c63e4d | 2446 | val.reg_flag = 1; |
5bb2f919 | 2447 | val.start = true_regnum (x); |
0ed5554e | 2448 | if (val.start < 0 || val.start >= FIRST_PSEUDO_REGISTER) |
42c63e4d | 2449 | { |
2450 | /* A pseudo with no hard reg. */ | |
2451 | val.start = REGNO (x); | |
2452 | val.end = val.start + 1; | |
2453 | } | |
2454 | else | |
2455 | /* A hard reg. */ | |
a2c6f0b7 | 2456 | val.end = end_hard_regno (GET_MODE (x), val.start); |
04e579b6 | 2457 | break; |
2458 | ||
2459 | case SUBREG: | |
8ad4c111 | 2460 | if (!REG_P (SUBREG_REG (x))) |
42c63e4d | 2461 | /* This could be more precise, but it's good enough. */ |
2462 | return decompose (SUBREG_REG (x)); | |
2463 | val.reg_flag = 1; | |
5bb2f919 | 2464 | val.start = true_regnum (x); |
0ed5554e | 2465 | if (val.start < 0 || val.start >= FIRST_PSEUDO_REGISTER) |
42c63e4d | 2466 | return decompose (SUBREG_REG (x)); |
2467 | else | |
2468 | /* A hard reg. */ | |
fe2ebfc8 | 2469 | val.end = val.start + subreg_nregs (x); |
04e579b6 | 2470 | break; |
2471 | ||
2472 | case SCRATCH: | |
2473 | /* This hasn't been assigned yet, so it can't conflict yet. */ | |
2474 | val.safe = 1; | |
2475 | break; | |
2476 | ||
2477 | default: | |
2478 | gcc_assert (CONSTANT_P (x)); | |
2479 | val.safe = 1; | |
2480 | break; | |
42c63e4d | 2481 | } |
42c63e4d | 2482 | return val; |
2483 | } | |
2484 | ||
2485 | /* Return 1 if altering Y will not modify the value of X. | |
2486 | Y is also described by YDATA, which should be decompose (Y). */ | |
2487 | ||
2488 | static int | |
3ad4992f | 2489 | immune_p (rtx x, rtx y, struct decomposition ydata) |
42c63e4d | 2490 | { |
2491 | struct decomposition xdata; | |
2492 | ||
2493 | if (ydata.reg_flag) | |
33181afc | 2494 | return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, (rtx*) 0); |
42c63e4d | 2495 | if (ydata.safe) |
2496 | return 1; | |
2497 | ||
04e579b6 | 2498 | gcc_assert (MEM_P (y)); |
42c63e4d | 2499 | /* If Y is memory and X is not, Y can't affect X. */ |
e16ceb8e | 2500 | if (!MEM_P (x)) |
42c63e4d | 2501 | return 1; |
2502 | ||
67610d42 | 2503 | xdata = decompose (x); |
42c63e4d | 2504 | |
2505 | if (! rtx_equal_p (xdata.base, ydata.base)) | |
2506 | { | |
2507 | /* If bases are distinct symbolic constants, there is no overlap. */ | |
2508 | if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base)) | |
2509 | return 1; | |
2510 | /* Constants and stack slots never overlap. */ | |
2511 | if (CONSTANT_P (xdata.base) | |
2512 | && (ydata.base == frame_pointer_rtx | |
7c4f6442 | 2513 | || ydata.base == hard_frame_pointer_rtx |
42c63e4d | 2514 | || ydata.base == stack_pointer_rtx)) |
2515 | return 1; | |
2516 | if (CONSTANT_P (ydata.base) | |
2517 | && (xdata.base == frame_pointer_rtx | |
7c4f6442 | 2518 | || xdata.base == hard_frame_pointer_rtx |
42c63e4d | 2519 | || xdata.base == stack_pointer_rtx)) |
2520 | return 1; | |
2521 | /* If either base is variable, we don't know anything. */ | |
2522 | return 0; | |
2523 | } | |
2524 | ||
42c63e4d | 2525 | return (xdata.start >= ydata.end || ydata.start >= xdata.end); |
2526 | } | |
d7acad9f | 2527 | |
eb2f80f3 | 2528 | /* Similar, but calls decompose. */ |
d7acad9f | 2529 | |
2530 | int | |
3ad4992f | 2531 | safe_from_earlyclobber (rtx op, rtx clobber) |
d7acad9f | 2532 | { |
2533 | struct decomposition early_data; | |
2534 | ||
2535 | early_data = decompose (clobber); | |
2536 | return immune_p (op, clobber, early_data); | |
2537 | } | |
42c63e4d | 2538 | \f |
2539 | /* Main entry point of this file: search the body of INSN | |
2540 | for values that need reloading and record them with push_reload. | |
2541 | REPLACE nonzero means record also where the values occur | |
2542 | so that subst_reloads can be used. | |
2543 | ||
2544 | IND_LEVELS says how many levels of indirection are supported by this | |
2545 | machine; a value of zero means that a memory reference is not a valid | |
2546 | memory address. | |
2547 | ||
2548 | LIVE_KNOWN says we have valid information about which hard | |
2549 | regs are live at each point in the program; this is true when | |
2550 | we are called from global_alloc but false when stupid register | |
2551 | allocation has been done. | |
2552 | ||
2553 | RELOAD_REG_P if nonzero is a vector indexed by hard reg number | |
2554 | which is nonnegative if the reg has been commandeered for reloading into. | |
2555 | It is copied into STATIC_RELOAD_REG_P and referenced from there | |
93c7b06e | 2556 | by various subroutines. |
42c63e4d | 2557 | |
93c7b06e | 2558 | Return TRUE if some operands need to be changed, because of swapping |
2559 | commutative operands, reg_equiv_address substitution, or whatever. */ | |
2560 | ||
2561 | int | |
3ad4992f | 2562 | find_reloads (rtx insn, int replace, int ind_levels, int live_known, |
2563 | short *reload_reg_p) | |
42c63e4d | 2564 | { |
19cb6b50 | 2565 | int insn_code_number; |
2566 | int i, j; | |
42c63e4d | 2567 | int noperands; |
42c63e4d | 2568 | /* These start out as the constraints for the insn |
2569 | and they are chewed up as we consider alternatives. */ | |
39a1a66f | 2570 | const char *constraints[MAX_RECOG_OPERANDS]; |
42c63e4d | 2571 | /* These are the preferred classes for an operand, or NO_REGS if it isn't |
2572 | a register. */ | |
2573 | enum reg_class preferred_class[MAX_RECOG_OPERANDS]; | |
2574 | char pref_or_nothing[MAX_RECOG_OPERANDS]; | |
48e1416a | 2575 | /* Nonzero for a MEM operand whose entire address needs a reload. |
e4542435 | 2576 | May be -1 to indicate the entire address may or may not need a reload. */ |
42c63e4d | 2577 | int address_reloaded[MAX_RECOG_OPERANDS]; |
e4542435 | 2578 | /* Nonzero for an address operand that needs to be completely reloaded. |
2579 | May be -1 to indicate the entire operand may or may not need a reload. */ | |
27d1c91f | 2580 | int address_operand_reloaded[MAX_RECOG_OPERANDS]; |
70457512 | 2581 | /* Value of enum reload_type to use for operand. */ |
2582 | enum reload_type operand_type[MAX_RECOG_OPERANDS]; | |
2583 | /* Value of enum reload_type to use within address of operand. */ | |
2584 | enum reload_type address_type[MAX_RECOG_OPERANDS]; | |
2585 | /* Save the usage of each operand. */ | |
2586 | enum reload_usage { RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE } modified[MAX_RECOG_OPERANDS]; | |
42c63e4d | 2587 | int no_input_reloads = 0, no_output_reloads = 0; |
2588 | int n_alternatives; | |
71db0d8b | 2589 | reg_class_t this_alternative[MAX_RECOG_OPERANDS]; |
1aa1d9da | 2590 | char this_alternative_match_win[MAX_RECOG_OPERANDS]; |
42c63e4d | 2591 | char this_alternative_win[MAX_RECOG_OPERANDS]; |
2592 | char this_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2593 | char this_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2594 | int this_alternative_matches[MAX_RECOG_OPERANDS]; | |
2595 | int swapped; | |
09a17585 | 2596 | reg_class_t goal_alternative[MAX_RECOG_OPERANDS]; |
42c63e4d | 2597 | int this_alternative_number; |
ef2c4a29 | 2598 | int goal_alternative_number = 0; |
42c63e4d | 2599 | int operand_reloadnum[MAX_RECOG_OPERANDS]; |
2600 | int goal_alternative_matches[MAX_RECOG_OPERANDS]; | |
2601 | int goal_alternative_matched[MAX_RECOG_OPERANDS]; | |
1aa1d9da | 2602 | char goal_alternative_match_win[MAX_RECOG_OPERANDS]; |
42c63e4d | 2603 | char goal_alternative_win[MAX_RECOG_OPERANDS]; |
2604 | char goal_alternative_offmemok[MAX_RECOG_OPERANDS]; | |
2605 | char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS]; | |
2606 | int goal_alternative_swapped; | |
42c63e4d | 2607 | int best; |
2608 | int commutative; | |
2609 | char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; | |
2610 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
2611 | rtx body = PATTERN (insn); | |
2612 | rtx set = single_set (insn); | |
ef2c4a29 | 2613 | int goal_earlyclobber = 0, this_earlyclobber; |
42c63e4d | 2614 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
93c7b06e | 2615 | int retval = 0; |
42c63e4d | 2616 | |
2617 | this_insn = insn; | |
42c63e4d | 2618 | n_reloads = 0; |
2619 | n_replacements = 0; | |
42c63e4d | 2620 | n_earlyclobbers = 0; |
2621 | replace_reloads = replace; | |
2622 | hard_regs_live_known = live_known; | |
2623 | static_reload_reg_p = reload_reg_p; | |
2624 | ||
2625 | /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads; | |
2626 | neither are insns that SET cc0. Insns that use CC0 are not allowed | |
2627 | to have any input reloads. */ | |
6d7dc5b9 | 2628 | if (JUMP_P (insn) || CALL_P (insn)) |
42c63e4d | 2629 | no_output_reloads = 1; |
2630 | ||
2631 | #ifdef HAVE_cc0 | |
2632 | if (reg_referenced_p (cc0_rtx, PATTERN (insn))) | |
2633 | no_input_reloads = 1; | |
2634 | if (reg_set_p (cc0_rtx, PATTERN (insn))) | |
2635 | no_output_reloads = 1; | |
2636 | #endif | |
5bb2f919 | 2637 | |
c538053c | 2638 | #ifdef SECONDARY_MEMORY_NEEDED |
2639 | /* The eliminated forms of any secondary memory locations are per-insn, so | |
2640 | clear them out here. */ | |
2641 | ||
605e65d9 | 2642 | if (secondary_memlocs_elim_used) |
2643 | { | |
2644 | memset (secondary_memlocs_elim, 0, | |
2645 | sizeof (secondary_memlocs_elim[0]) * secondary_memlocs_elim_used); | |
2646 | secondary_memlocs_elim_used = 0; | |
2647 | } | |
c538053c | 2648 | #endif |
2649 | ||
5d07813e | 2650 | /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it |
2651 | is cheap to move between them. If it is not, there may not be an insn | |
2652 | to do the copy, so we may need a reload. */ | |
2653 | if (GET_CODE (body) == SET | |
8ad4c111 | 2654 | && REG_P (SET_DEST (body)) |
5d07813e | 2655 | && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER |
8ad4c111 | 2656 | && REG_P (SET_SRC (body)) |
5d07813e | 2657 | && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER |
e6078fbb | 2658 | && register_move_cost (GET_MODE (SET_SRC (body)), |
0ac516dc | 2659 | REGNO_REG_CLASS (REGNO (SET_SRC (body))), |
5d07813e | 2660 | REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2) |
2661 | return 0; | |
42c63e4d | 2662 | |
5d07813e | 2663 | extract_insn (insn); |
42c63e4d | 2664 | |
ed420a25 | 2665 | noperands = reload_n_operands = recog_data.n_operands; |
2666 | n_alternatives = recog_data.n_alternatives; | |
42c63e4d | 2667 | |
5d07813e | 2668 | /* Just return "no reloads" if insn has no operands with constraints. */ |
2669 | if (noperands == 0 || n_alternatives == 0) | |
2670 | return 0; | |
42c63e4d | 2671 | |
5d07813e | 2672 | insn_code_number = INSN_CODE (insn); |
2673 | this_insn_is_asm = insn_code_number < 0; | |
42c63e4d | 2674 | |
d844aacc | 2675 | memcpy (operand_mode, recog_data.operand_mode, |
2676 | noperands * sizeof (enum machine_mode)); | |
39a1a66f | 2677 | memcpy (constraints, recog_data.constraints, |
2678 | noperands * sizeof (const char *)); | |
42c63e4d | 2679 | |
2680 | commutative = -1; | |
2681 | ||
2682 | /* If we will need to know, later, whether some pair of operands | |
2683 | are the same, we must compare them now and save the result. | |
2684 | Reloading the base and index registers will clobber them | |
2685 | and afterward they will fail to match. */ | |
2686 | ||
2687 | for (i = 0; i < noperands; i++) | |
2688 | { | |
39a1a66f | 2689 | const char *p; |
19cb6b50 | 2690 | int c; |
39a1a66f | 2691 | char *end; |
42c63e4d | 2692 | |
ed420a25 | 2693 | substed_operand[i] = recog_data.operand[i]; |
42c63e4d | 2694 | p = constraints[i]; |
2695 | ||
70457512 | 2696 | modified[i] = RELOAD_READ; |
2697 | ||
5bb2f919 | 2698 | /* Scan this operand's constraint to see if it is an output operand, |
70457512 | 2699 | an in-out operand, is commutative, or should match another. */ |
42c63e4d | 2700 | |
48ea5577 | 2701 | while ((c = *p)) |
70457512 | 2702 | { |
48ea5577 | 2703 | p += CONSTRAINT_LEN (c, p); |
adee86a0 | 2704 | switch (c) |
70457512 | 2705 | { |
adee86a0 | 2706 | case '=': |
2707 | modified[i] = RELOAD_WRITE; | |
2708 | break; | |
2709 | case '+': | |
2710 | modified[i] = RELOAD_READ_WRITE; | |
2711 | break; | |
2712 | case '%': | |
2713 | { | |
2714 | /* The last operand should not be marked commutative. */ | |
04e579b6 | 2715 | gcc_assert (i != noperands - 1); |
adee86a0 | 2716 | |
2717 | /* We currently only support one commutative pair of | |
2718 | operands. Some existing asm code currently uses more | |
2719 | than one pair. Previously, that would usually work, | |
2720 | but sometimes it would crash the compiler. We | |
2721 | continue supporting that case as well as we can by | |
2722 | silently ignoring all but the first pair. In the | |
2723 | future we may handle it correctly. */ | |
2724 | if (commutative < 0) | |
2725 | commutative = i; | |
04e579b6 | 2726 | else |
2727 | gcc_assert (this_insn_is_asm); | |
adee86a0 | 2728 | } |
2729 | break; | |
2730 | /* Use of ISDIGIT is tempting here, but it may get expensive because | |
2731 | of locale support we don't want. */ | |
2732 | case '0': case '1': case '2': case '3': case '4': | |
2733 | case '5': case '6': case '7': case '8': case '9': | |
2734 | { | |
39a1a66f | 2735 | c = strtoul (p - 1, &end, 10); |
2736 | p = end; | |
adee86a0 | 2737 | |
2738 | operands_match[c][i] | |
2739 | = operands_match_p (recog_data.operand[c], | |
2740 | recog_data.operand[i]); | |
2741 | ||
2742 | /* An operand may not match itself. */ | |
04e579b6 | 2743 | gcc_assert (c != i); |
adee86a0 | 2744 | |
2745 | /* If C can be commuted with C+1, and C might need to match I, | |
2746 | then C+1 might also need to match I. */ | |
2747 | if (commutative >= 0) | |
2748 | { | |
2749 | if (c == commutative || c == commutative + 1) | |
2750 | { | |
2751 | int other = c + (c == commutative ? 1 : -1); | |
2752 | operands_match[other][i] | |
2753 | = operands_match_p (recog_data.operand[other], | |
2754 | recog_data.operand[i]); | |
2755 | } | |
2756 | if (i == commutative || i == commutative + 1) | |
2757 | { | |
2758 | int other = i + (i == commutative ? 1 : -1); | |
2759 | operands_match[c][other] | |
2760 | = operands_match_p (recog_data.operand[c], | |
2761 | recog_data.operand[other]); | |
2762 | } | |
2763 | /* Note that C is supposed to be less than I. | |
2764 | No need to consider altering both C and I because in | |
2765 | that case we would alter one into the other. */ | |
2766 | } | |
2767 | } | |
70457512 | 2768 | } |
2769 | } | |
42c63e4d | 2770 | } |
2771 | ||
2772 | /* Examine each operand that is a memory reference or memory address | |
2773 | and reload parts of the addresses into index registers. | |
42c63e4d | 2774 | Also here any references to pseudo regs that didn't get hard regs |
2775 | but are equivalent to constants get replaced in the insn itself | |
5bb2f919 | 2776 | with those constants. Nobody will ever see them again. |
42c63e4d | 2777 | |
2778 | Finally, set up the preferred classes of each operand. */ | |
2779 | ||
2780 | for (i = 0; i < noperands; i++) | |
2781 | { | |
19cb6b50 | 2782 | RTX_CODE code = GET_CODE (recog_data.operand[i]); |
70457512 | 2783 | |
42c63e4d | 2784 | address_reloaded[i] = 0; |
27d1c91f | 2785 | address_operand_reloaded[i] = 0; |
70457512 | 2786 | operand_type[i] = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT |
2787 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT | |
2788 | : RELOAD_OTHER); | |
2789 | address_type[i] | |
2790 | = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT_ADDRESS | |
2791 | : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT_ADDRESS | |
2792 | : RELOAD_OTHER); | |
42c63e4d | 2793 | |
bfe0e25e | 2794 | if (*constraints[i] == 0) |
2795 | /* Ignore things like match_operator operands. */ | |
2796 | ; | |
a5004c3d | 2797 | else if (constraints[i][0] == 'p' |
48ea5577 | 2798 | || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i])) |
42c63e4d | 2799 | { |
27d1c91f | 2800 | address_operand_reloaded[i] |
2801 | = find_reloads_address (recog_data.operand_mode[i], (rtx*) 0, | |
2802 | recog_data.operand[i], | |
2803 | recog_data.operand_loc[i], | |
2804 | i, operand_type[i], ind_levels, insn); | |
1a922356 | 2805 | |
5bb2f919 | 2806 | /* If we now have a simple operand where we used to have a |
1a922356 | 2807 | PLUS or MULT, re-recognize and try again. */ |
6720e96c | 2808 | if ((OBJECT_P (*recog_data.operand_loc[i]) |
ed420a25 | 2809 | || GET_CODE (*recog_data.operand_loc[i]) == SUBREG) |
2810 | && (GET_CODE (recog_data.operand[i]) == MULT | |
2811 | || GET_CODE (recog_data.operand[i]) == PLUS)) | |
1a922356 | 2812 | { |
2813 | INSN_CODE (insn) = -1; | |
93c7b06e | 2814 | retval = find_reloads (insn, replace, ind_levels, live_known, |
2815 | reload_reg_p); | |
2816 | return retval; | |
1a922356 | 2817 | } |
2818 | ||
ed420a25 | 2819 | recog_data.operand[i] = *recog_data.operand_loc[i]; |
2820 | substed_operand[i] = recog_data.operand[i]; | |
27d1c91f | 2821 | |
2822 | /* Address operands are reloaded in their existing mode, | |
2823 | no matter what is specified in the machine description. */ | |
2824 | operand_mode[i] = GET_MODE (recog_data.operand[i]); | |
fe42ff4b | 2825 | |
2826 | /* If the address is a single CONST_INT pick address mode | |
2827 | instead otherwise we will later not know in which mode | |
2828 | the reload should be performed. */ | |
2829 | if (operand_mode[i] == VOIDmode) | |
2830 | operand_mode[i] = Pmode; | |
2831 | ||
42c63e4d | 2832 | } |
2833 | else if (code == MEM) | |
2834 | { | |
be2828ce | 2835 | address_reloaded[i] |
ed420a25 | 2836 | = find_reloads_address (GET_MODE (recog_data.operand[i]), |
2837 | recog_data.operand_loc[i], | |
2838 | XEXP (recog_data.operand[i], 0), | |
2839 | &XEXP (recog_data.operand[i], 0), | |
be2828ce | 2840 | i, address_type[i], ind_levels, insn); |
ed420a25 | 2841 | recog_data.operand[i] = *recog_data.operand_loc[i]; |
2842 | substed_operand[i] = recog_data.operand[i]; | |
42c63e4d | 2843 | } |
2844 | else if (code == SUBREG) | |
6aed5e78 | 2845 | { |
ed420a25 | 2846 | rtx reg = SUBREG_REG (recog_data.operand[i]); |
6aed5e78 | 2847 | rtx op |
ed420a25 | 2848 | = find_reloads_toplev (recog_data.operand[i], i, address_type[i], |
6aed5e78 | 2849 | ind_levels, |
2850 | set != 0 | |
ed420a25 | 2851 | && &SET_DEST (set) == recog_data.operand_loc[i], |
1aa90c62 | 2852 | insn, |
2853 | &address_reloaded[i]); | |
6aed5e78 | 2854 | |
2855 | /* If we made a MEM to load (a part of) the stackslot of a pseudo | |
2856 | that didn't get a hard register, emit a USE with a REG_EQUAL | |
2857 | note in front so that we might inherit a previous, possibly | |
2858 | wider reload. */ | |
5bb2f919 | 2859 | |
93c7b06e | 2860 | if (replace |
e16ceb8e | 2861 | && MEM_P (op) |
8ad4c111 | 2862 | && REG_P (reg) |
6aed5e78 | 2863 | && (GET_MODE_SIZE (GET_MODE (reg)) |
8a72adf4 | 2864 | >= GET_MODE_SIZE (GET_MODE (op))) |
1c654ff1 | 2865 | && reg_equiv_constant (REGNO (reg)) == 0) |
c080d8f0 | 2866 | set_unique_reg_note (emit_insn_before (gen_rtx_USE (VOIDmode, reg), |
2867 | insn), | |
1c654ff1 | 2868 | REG_EQUAL, reg_equiv_memory_loc (REGNO (reg))); |
6aed5e78 | 2869 | |
ed420a25 | 2870 | substed_operand[i] = recog_data.operand[i] = op; |
6aed5e78 | 2871 | } |
6720e96c | 2872 | else if (code == PLUS || GET_RTX_CLASS (code) == RTX_UNARY) |
de0fdb4f | 2873 | /* We can get a PLUS as an "operand" as a result of register |
2874 | elimination. See eliminate_regs and gen_reload. We handle | |
2875 | a unary operator by reloading the operand. */ | |
ed420a25 | 2876 | substed_operand[i] = recog_data.operand[i] |
2877 | = find_reloads_toplev (recog_data.operand[i], i, address_type[i], | |
1aa90c62 | 2878 | ind_levels, 0, insn, |
2879 | &address_reloaded[i]); | |
42c63e4d | 2880 | else if (code == REG) |
2881 | { | |
2882 | /* This is equivalent to calling find_reloads_toplev. | |
2883 | The code is duplicated for speed. | |
2884 | When we find a pseudo always equivalent to a constant, | |
2885 | we replace it by the constant. We must be sure, however, | |
2886 | that we don't try to replace it in the insn in which it | |
1e625a2e | 2887 | is being set. */ |
19cb6b50 | 2888 | int regno = REGNO (recog_data.operand[i]); |
1c654ff1 | 2889 | if (reg_equiv_constant (regno) != 0 |
ed420a25 | 2890 | && (set == 0 || &SET_DEST (set) != recog_data.operand_loc[i])) |
a6979111 | 2891 | { |
2892 | /* Record the existing mode so that the check if constants are | |
48666d2c | 2893 | allowed will work when operand_mode isn't specified. */ |
a6979111 | 2894 | |
2895 | if (operand_mode[i] == VOIDmode) | |
ed420a25 | 2896 | operand_mode[i] = GET_MODE (recog_data.operand[i]); |
a6979111 | 2897 | |
ed420a25 | 2898 | substed_operand[i] = recog_data.operand[i] |
1c654ff1 | 2899 | = reg_equiv_constant (regno); |
a6979111 | 2900 | } |
1c654ff1 | 2901 | if (reg_equiv_memory_loc (regno) != 0 |
2902 | && (reg_equiv_address (regno) != 0 || num_not_at_initial_offset)) | |
93c7b06e | 2903 | /* We need not give a valid is_set_dest argument since the case |
2904 | of a constant equivalence was checked above. */ | |
ed420a25 | 2905 | substed_operand[i] = recog_data.operand[i] |
2906 | = find_reloads_toplev (recog_data.operand[i], i, address_type[i], | |
1aa90c62 | 2907 | ind_levels, 0, insn, |
2908 | &address_reloaded[i]); | |
42c63e4d | 2909 | } |
41b91e61 | 2910 | /* If the operand is still a register (we didn't replace it with an |
2911 | equivalent), get the preferred class to reload it into. */ | |
ed420a25 | 2912 | code = GET_CODE (recog_data.operand[i]); |
41b91e61 | 2913 | preferred_class[i] |
ed420a25 | 2914 | = ((code == REG && REGNO (recog_data.operand[i]) |
2915 | >= FIRST_PSEUDO_REGISTER) | |
2916 | ? reg_preferred_class (REGNO (recog_data.operand[i])) | |
2917 | : NO_REGS); | |
41b91e61 | 2918 | pref_or_nothing[i] |
ed420a25 | 2919 | = (code == REG |
2920 | && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER | |
2921 | && reg_alternate_class (REGNO (recog_data.operand[i])) == NO_REGS); | |
42c63e4d | 2922 | } |
2923 | ||
2924 | /* If this is simply a copy from operand 1 to operand 0, merge the | |
2925 | preferred classes for the operands. */ | |
ed420a25 | 2926 | if (set != 0 && noperands >= 2 && recog_data.operand[0] == SET_DEST (set) |
2927 | && recog_data.operand[1] == SET_SRC (set)) | |
42c63e4d | 2928 | { |
2929 | preferred_class[0] = preferred_class[1] | |
2930 | = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]]; | |
2931 | pref_or_nothing[0] |= pref_or_nothing[1]; | |
2932 | pref_or_nothing[1] |= pref_or_nothing[0]; | |
2933 | } | |
2934 | ||
2935 | /* Now see what we need for pseudo-regs that didn't get hard regs | |
2936 | or got the wrong kind of hard reg. For this, we must consider | |
2937 | all the operands together against the register constraints. */ | |
2938 | ||
c988df6a | 2939 | best = MAX_RECOG_OPERANDS * 2 + 600; |
42c63e4d | 2940 | |
2941 | swapped = 0; | |
2942 | goal_alternative_swapped = 0; | |
2943 | try_swapped: | |
2944 | ||
2945 | /* The constraints are made of several alternatives. | |
2946 | Each operand's constraint looks like foo,bar,... with commas | |
2947 | separating the alternatives. The first alternatives for all | |
2948 | operands go together, the second alternatives go together, etc. | |
2949 | ||
2950 | First loop over alternatives. */ | |
2951 | ||
2952 | for (this_alternative_number = 0; | |
2953 | this_alternative_number < n_alternatives; | |
2954 | this_alternative_number++) | |
2955 | { | |
2956 | /* Loop over operands for one constraint alternative. */ | |
2957 | /* LOSERS counts those that don't fit this alternative | |
2958 | and would require loading. */ | |
2959 | int losers = 0; | |
2960 | /* BAD is set to 1 if it some operand can't fit this alternative | |
2961 | even after reloading. */ | |
2962 | int bad = 0; | |
2963 | /* REJECT is a count of how undesirable this alternative says it is | |
2964 | if any reloading is required. If the alternative matches exactly | |
2965 | then REJECT is ignored, but otherwise it gets this much | |
5bb2f919 | 2966 | counted against it in addition to the reloading needed. Each |
42c63e4d | 2967 | ? counts three times here since we want the disparaging caused by |
2968 | a bad register class to only count 1/3 as much. */ | |
2969 | int reject = 0; | |
2970 | ||
39a1a66f | 2971 | if (!recog_data.alternative_enabled_p[this_alternative_number]) |
2972 | { | |
2973 | int i; | |
2974 | ||
2975 | for (i = 0; i < recog_data.n_operands; i++) | |
2976 | constraints[i] = skip_alternative (constraints[i]); | |
2977 | ||
2978 | continue; | |
2979 | } | |
2980 | ||
42c63e4d | 2981 | this_earlyclobber = 0; |
2982 | ||
2983 | for (i = 0; i < noperands; i++) | |
2984 | { | |
39a1a66f | 2985 | const char *p = constraints[i]; |
48ea5577 | 2986 | char *end; |
2987 | int len; | |
19cb6b50 | 2988 | int win = 0; |
1aa1d9da | 2989 | int did_match = 0; |
aa35b87f | 2990 | /* 0 => this operand can be reloaded somehow for this alternative. */ |
42c63e4d | 2991 | int badop = 1; |
2992 | /* 0 => this operand can be reloaded if the alternative allows regs. */ | |
2993 | int winreg = 0; | |
2994 | int c; | |
48ea5577 | 2995 | int m; |
19cb6b50 | 2996 | rtx operand = recog_data.operand[i]; |
42c63e4d | 2997 | int offset = 0; |
2998 | /* Nonzero means this is a MEM that must be reloaded into a reg | |
2999 | regardless of what the constraint says. */ | |
3000 | int force_reload = 0; | |
3001 | int offmemok = 0; | |
f630a9b6 | 3002 | /* Nonzero if a constant forced into memory would be OK for this |
3003 | operand. */ | |
3004 | int constmemok = 0; | |
42c63e4d | 3005 | int earlyclobber = 0; |
3006 | ||
de0fdb4f | 3007 | /* If the predicate accepts a unary operator, it means that |
5bb2f919 | 3008 | we need to reload the operand, but do not do this for |
6c1df11b | 3009 | match_operator and friends. */ |
6720e96c | 3010 | if (UNARY_P (operand) && *p != 0) |
de0fdb4f | 3011 | operand = XEXP (operand, 0); |
3012 | ||
42c63e4d | 3013 | /* If the operand is a SUBREG, extract |
3014 | the REG or MEM (or maybe even a constant) within. | |
3015 | (Constants can occur as a result of reg_equiv_constant.) */ | |
3016 | ||
3017 | while (GET_CODE (operand) == SUBREG) | |
3018 | { | |
701e46d0 | 3019 | /* Offset only matters when operand is a REG and |
3020 | it is a hard reg. This is because it is passed | |
3021 | to reg_fits_class_p if it is a REG and all pseudos | |
3022 | return 0 from that function. */ | |
8ad4c111 | 3023 | if (REG_P (SUBREG_REG (operand)) |
701e46d0 | 3024 | && REGNO (SUBREG_REG (operand)) < FIRST_PSEUDO_REGISTER) |
3025 | { | |
5992d16a | 3026 | if (simplify_subreg_regno (REGNO (SUBREG_REG (operand)), |
3027 | GET_MODE (SUBREG_REG (operand)), | |
3028 | SUBREG_BYTE (operand), | |
3029 | GET_MODE (operand)) < 0) | |
3030 | force_reload = 1; | |
701e46d0 | 3031 | offset += subreg_regno_offset (REGNO (SUBREG_REG (operand)), |
3032 | GET_MODE (SUBREG_REG (operand)), | |
3033 | SUBREG_BYTE (operand), | |
3034 | GET_MODE (operand)); | |
3035 | } | |
42c63e4d | 3036 | operand = SUBREG_REG (operand); |
3398e91d | 3037 | /* Force reload if this is a constant or PLUS or if there may |
cbcb19b7 | 3038 | be a problem accessing OPERAND in the outer mode. */ |
3039 | if (CONSTANT_P (operand) | |
7bc1bb34 | 3040 | || GET_CODE (operand) == PLUS |
011d1afd | 3041 | /* We must force a reload of paradoxical SUBREGs |
3042 | of a MEM because the alignment of the inner value | |
1d793270 | 3043 | may not be enough to do the outer reference. On |
3044 | big-endian machines, it may also reference outside | |
3045 | the object. | |
011d1afd | 3046 | |
3047 | On machines that extend byte operations and we have a | |
bfdb517e | 3048 | SUBREG where both the inner and outer modes are no wider |
3049 | than a word and the inner mode is narrower, is integral, | |
3050 | and gets extended when loaded from memory, combine.c has | |
3051 | made assumptions about the behavior of the machine in such | |
011d1afd | 3052 | register access. If the data is, in fact, in memory we |
3053 | must always load using the size assumed to be in the | |
5bb2f919 | 3054 | register and let the insn do the different-sized |
d743d4f7 | 3055 | accesses. |
3056 | ||
5bb2f919 | 3057 | This is doubly true if WORD_REGISTER_OPERATIONS. In |
d743d4f7 | 3058 | this case eliminate_regs has left non-paradoxical |
5cd86fd9 | 3059 | subregs for push_reload to see. Make sure it does |
d743d4f7 | 3060 | by forcing the reload. |
3061 | ||
3062 | ??? When is it right at this stage to have a subreg | |
de132707 | 3063 | of a mem that is _not_ to be handled specially? IMO |
d743d4f7 | 3064 | those should have been reduced to just a mem. */ |
e16ceb8e | 3065 | || ((MEM_P (operand) |
8ad4c111 | 3066 | || (REG_P (operand) |
cbcb19b7 | 3067 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) |
d743d4f7 | 3068 | #ifndef WORD_REGISTER_OPERATIONS |
011d1afd | 3069 | && (((GET_MODE_BITSIZE (GET_MODE (operand)) |
3070 | < BIGGEST_ALIGNMENT) | |
3071 | && (GET_MODE_SIZE (operand_mode[i]) | |
3072 | > GET_MODE_SIZE (GET_MODE (operand)))) | |
9f00769c | 3073 | || BYTES_BIG_ENDIAN |
011d1afd | 3074 | #ifdef LOAD_EXTEND_OP |
3075 | || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD | |
3076 | && (GET_MODE_SIZE (GET_MODE (operand)) | |
3077 | <= UNITS_PER_WORD) | |
3078 | && (GET_MODE_SIZE (operand_mode[i]) | |
bfdb517e | 3079 | > GET_MODE_SIZE (GET_MODE (operand))) |
3080 | && INTEGRAL_MODE_P (GET_MODE (operand)) | |
21f1e711 | 3081 | && LOAD_EXTEND_OP (GET_MODE (operand)) != UNKNOWN) |
9d435639 | 3082 | #endif |
d743d4f7 | 3083 | ) |
3084 | #endif | |
3085 | ) | |
701e46d0 | 3086 | ) |
42c63e4d | 3087 | force_reload = 1; |
3088 | } | |
3089 | ||
b9c74b4d | 3090 | this_alternative[i] = NO_REGS; |
42c63e4d | 3091 | this_alternative_win[i] = 0; |
1aa1d9da | 3092 | this_alternative_match_win[i] = 0; |
42c63e4d | 3093 | this_alternative_offmemok[i] = 0; |
3094 | this_alternative_earlyclobber[i] = 0; | |
3095 | this_alternative_matches[i] = -1; | |
3096 | ||
3097 | /* An empty constraint or empty alternative | |
3098 | allows anything which matched the pattern. */ | |
3099 | if (*p == 0 || *p == ',') | |
3100 | win = 1, badop = 0; | |
3101 | ||
3102 | /* Scan this alternative's specs for this operand; | |
3103 | set WIN if the operand fits any letter in this alternative. | |
3104 | Otherwise, clear BADOP if this operand could | |
3105 | fit some letter after reloads, | |
3106 | or set WINREG if this operand could fit after reloads | |
3107 | provided the constraint allows some registers. */ | |
3108 | ||
48ea5577 | 3109 | do |
3110 | switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) | |
42c63e4d | 3111 | { |
48ea5577 | 3112 | case '\0': |
3113 | len = 0; | |
3114 | break; | |
3115 | case ',': | |
3116 | c = '\0'; | |
3117 | break; | |
3118 | ||
7014838c | 3119 | case '=': case '+': case '*': |
42c63e4d | 3120 | break; |
3121 | ||
3122 | case '%': | |
a336c79a | 3123 | /* We only support one commutative marker, the first |
3124 | one. We already set commutative above. */ | |
42c63e4d | 3125 | break; |
3126 | ||
3127 | case '?': | |
c988df6a | 3128 | reject += 6; |
42c63e4d | 3129 | break; |
3130 | ||
3131 | case '!': | |
c988df6a | 3132 | reject = 600; |
42c63e4d | 3133 | break; |
3134 | ||
3135 | case '#': | |
3136 | /* Ignore rest of this alternative as far as | |
3137 | reloading is concerned. */ | |
48ea5577 | 3138 | do |
67610d42 | 3139 | p++; |
48ea5577 | 3140 | while (*p && *p != ','); |
3141 | len = 0; | |
42c63e4d | 3142 | break; |
3143 | ||
7014838c | 3144 | case '0': case '1': case '2': case '3': case '4': |
3145 | case '5': case '6': case '7': case '8': case '9': | |
48ea5577 | 3146 | m = strtoul (p, &end, 10); |
3147 | p = end; | |
3148 | len = 0; | |
7014838c | 3149 | |
48ea5577 | 3150 | this_alternative_matches[i] = m; |
42c63e4d | 3151 | /* We are supposed to match a previous operand. |
3152 | If we do, we win if that one did. | |
3153 | If we do not, count both of the operands as losers. | |
3154 | (This is too conservative, since most of the time | |
3155 | only a single reload insn will be needed to make | |
3156 | the two operands win. As a result, this alternative | |
3157 | may be rejected when it is actually desirable.) */ | |
48ea5577 | 3158 | if ((swapped && (m != commutative || i != commutative + 1)) |
42c63e4d | 3159 | /* If we are matching as if two operands were swapped, |
3160 | also pretend that operands_match had been computed | |
3161 | with swapped. | |
3162 | But if I is the second of those and C is the first, | |
3163 | don't exchange them, because operands_match is valid | |
3164 | only on one side of its diagonal. */ | |
3165 | ? (operands_match | |
48ea5577 | 3166 | [(m == commutative || m == commutative + 1) |
3167 | ? 2 * commutative + 1 - m : m] | |
5bb2f919 | 3168 | [(i == commutative || i == commutative + 1) |
67610d42 | 3169 | ? 2 * commutative + 1 - i : i]) |
48ea5577 | 3170 | : operands_match[m][i]) |
7840126a | 3171 | { |
3172 | /* If we are matching a non-offsettable address where an | |
3173 | offsettable address was expected, then we must reject | |
3174 | this combination, because we can't reload it. */ | |
48ea5577 | 3175 | if (this_alternative_offmemok[m] |
e16ceb8e | 3176 | && MEM_P (recog_data.operand[m]) |
b9c74b4d | 3177 | && this_alternative[m] == NO_REGS |
48ea5577 | 3178 | && ! this_alternative_win[m]) |
7840126a | 3179 | bad = 1; |
3180 | ||
48ea5577 | 3181 | did_match = this_alternative_win[m]; |
7840126a | 3182 | } |
42c63e4d | 3183 | else |
3184 | { | |
3185 | /* Operands don't match. */ | |
3186 | rtx value; | |
c166bf3d | 3187 | int loc1, loc2; |
42c63e4d | 3188 | /* Retroactively mark the operand we had to match |
3189 | as a loser, if it wasn't already. */ | |
48ea5577 | 3190 | if (this_alternative_win[m]) |
42c63e4d | 3191 | losers++; |
48ea5577 | 3192 | this_alternative_win[m] = 0; |
b9c74b4d | 3193 | if (this_alternative[m] == NO_REGS) |
42c63e4d | 3194 | bad = 1; |
3195 | /* But count the pair only once in the total badness of | |
c166bf3d | 3196 | this alternative, if the pair can be a dummy reload. |
3197 | The pointers in operand_loc are not swapped; swap | |
3198 | them by hand if necessary. */ | |
3199 | if (swapped && i == commutative) | |
3200 | loc1 = commutative + 1; | |
3201 | else if (swapped && i == commutative + 1) | |
3202 | loc1 = commutative; | |
3203 | else | |
3204 | loc1 = i; | |
3205 | if (swapped && m == commutative) | |
3206 | loc2 = commutative + 1; | |
3207 | else if (swapped && m == commutative + 1) | |
3208 | loc2 = commutative; | |
3209 | else | |
3210 | loc2 = m; | |
42c63e4d | 3211 | value |
ed420a25 | 3212 | = find_dummy_reload (recog_data.operand[i], |
48ea5577 | 3213 | recog_data.operand[m], |
c166bf3d | 3214 | recog_data.operand_loc[loc1], |
3215 | recog_data.operand_loc[loc2], | |
48ea5577 | 3216 | operand_mode[i], operand_mode[m], |
3217 | this_alternative[m], -1, | |
3218 | this_alternative_earlyclobber[m]); | |
42c63e4d | 3219 | |
3220 | if (value != 0) | |
3221 | losers--; | |
3222 | } | |
3223 | /* This can be fixed with reloads if the operand | |
3224 | we are supposed to match can be fixed with reloads. */ | |
3225 | badop = 0; | |
48ea5577 | 3226 | this_alternative[i] = this_alternative[m]; |
8fe0deab | 3227 | |
3228 | /* If we have to reload this operand and some previous | |
3229 | operand also had to match the same thing as this | |
3230 | operand, we don't know how to do that. So reject this | |
3231 | alternative. */ | |
1aa1d9da | 3232 | if (! did_match || force_reload) |
8fe0deab | 3233 | for (j = 0; j < i; j++) |
3234 | if (this_alternative_matches[j] | |
3235 | == this_alternative_matches[i]) | |
3236 | badop = 1; | |
42c63e4d | 3237 | break; |
3238 | ||
3239 | case 'p': | |
3240 | /* All necessary reloads for an address_operand | |
3241 | were handled in find_reloads_address. */ | |
f8a8fc7b | 3242 | this_alternative[i] |
3243 | = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
3244 | ADDRESS, SCRATCH); | |
42c63e4d | 3245 | win = 1; |
7d262d85 | 3246 | badop = 0; |
42c63e4d | 3247 | break; |
3248 | ||
e9ff93b1 | 3249 | case TARGET_MEM_CONSTRAINT: |
42c63e4d | 3250 | if (force_reload) |
3251 | break; | |
e16ceb8e | 3252 | if (MEM_P (operand) |
8ad4c111 | 3253 | || (REG_P (operand) |
42c63e4d | 3254 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER |
3255 | && reg_renumber[REGNO (operand)] < 0)) | |
3256 | win = 1; | |
7d7d7bd2 | 3257 | if (CONST_POOL_OK_P (operand_mode[i], operand)) |
42c63e4d | 3258 | badop = 0; |
f630a9b6 | 3259 | constmemok = 1; |
42c63e4d | 3260 | break; |
3261 | ||
3262 | case '<': | |
e16ceb8e | 3263 | if (MEM_P (operand) |
42c63e4d | 3264 | && ! address_reloaded[i] |
3265 | && (GET_CODE (XEXP (operand, 0)) == PRE_DEC | |
3266 | || GET_CODE (XEXP (operand, 0)) == POST_DEC)) | |
3267 | win = 1; | |
3268 | break; | |
3269 | ||
3270 | case '>': | |
e16ceb8e | 3271 | if (MEM_P (operand) |
42c63e4d | 3272 | && ! address_reloaded[i] |
3273 | && (GET_CODE (XEXP (operand, 0)) == PRE_INC | |
3274 | || GET_CODE (XEXP (operand, 0)) == POST_INC)) | |
3275 | win = 1; | |
3276 | break; | |
3277 | ||
3278 | /* Memory operand whose address is not offsettable. */ | |
3279 | case 'V': | |
3280 | if (force_reload) | |
3281 | break; | |
e16ceb8e | 3282 | if (MEM_P (operand) |
42c63e4d | 3283 | && ! (ind_levels ? offsettable_memref_p (operand) |
3284 | : offsettable_nonstrict_memref_p (operand)) | |
3285 | /* Certain mem addresses will become offsettable | |
3286 | after they themselves are reloaded. This is important; | |
3287 | we don't want our own handling of unoffsettables | |
3288 | to override the handling of reg_equiv_address. */ | |
8ad4c111 | 3289 | && !(REG_P (XEXP (operand, 0)) |
42c63e4d | 3290 | && (ind_levels == 0 |
1c654ff1 | 3291 | || reg_equiv_address (REGNO (XEXP (operand, 0))) != 0))) |
42c63e4d | 3292 | win = 1; |
3293 | break; | |
3294 | ||
3295 | /* Memory operand whose address is offsettable. */ | |
3296 | case 'o': | |
3297 | if (force_reload) | |
3298 | break; | |
e16ceb8e | 3299 | if ((MEM_P (operand) |
42c63e4d | 3300 | /* If IND_LEVELS, find_reloads_address won't reload a |
3301 | pseudo that didn't get a hard reg, so we have to | |
3302 | reject that case. */ | |
be2828ce | 3303 | && ((ind_levels ? offsettable_memref_p (operand) |
3304 | : offsettable_nonstrict_memref_p (operand)) | |
3305 | /* A reloaded address is offsettable because it is now | |
3306 | just a simple register indirect. */ | |
e4542435 | 3307 | || address_reloaded[i] == 1)) |
8ad4c111 | 3308 | || (REG_P (operand) |
42c63e4d | 3309 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER |
f57d22b8 | 3310 | && reg_renumber[REGNO (operand)] < 0 |
3311 | /* If reg_equiv_address is nonzero, we will be | |
3312 | loading it into a register; hence it will be | |
3313 | offsettable, but we cannot say that reg_equiv_mem | |
3314 | is offsettable without checking. */ | |
1c654ff1 | 3315 | && ((reg_equiv_mem (REGNO (operand)) != 0 |
3316 | && offsettable_memref_p (reg_equiv_mem (REGNO (operand)))) | |
3317 | || (reg_equiv_address (REGNO (operand)) != 0)))) | |
42c63e4d | 3318 | win = 1; |
7d7d7bd2 | 3319 | if (CONST_POOL_OK_P (operand_mode[i], operand) |
e16ceb8e | 3320 | || MEM_P (operand)) |
42c63e4d | 3321 | badop = 0; |
f630a9b6 | 3322 | constmemok = 1; |
42c63e4d | 3323 | offmemok = 1; |
3324 | break; | |
3325 | ||
3326 | case '&': | |
3327 | /* Output operand that is stored before the need for the | |
3328 | input operands (and their index registers) is over. */ | |
3329 | earlyclobber = 1, this_earlyclobber = 1; | |
3330 | break; | |
3331 | ||
3332 | case 'E': | |
42c63e4d | 3333 | case 'F': |
22dd8d0e | 3334 | if (GET_CODE (operand) == CONST_DOUBLE |
3335 | || (GET_CODE (operand) == CONST_VECTOR | |
3336 | && (GET_MODE_CLASS (GET_MODE (operand)) | |
3337 | == MODE_VECTOR_FLOAT))) | |
42c63e4d | 3338 | win = 1; |
3339 | break; | |
3340 | ||
3341 | case 'G': | |
3342 | case 'H': | |
3343 | if (GET_CODE (operand) == CONST_DOUBLE | |
48ea5577 | 3344 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (operand, c, p)) |
42c63e4d | 3345 | win = 1; |
3346 | break; | |
3347 | ||
3348 | case 's': | |
971ba038 | 3349 | if (CONST_INT_P (operand) |
42c63e4d | 3350 | || (GET_CODE (operand) == CONST_DOUBLE |
3351 | && GET_MODE (operand) == VOIDmode)) | |
3352 | break; | |
3353 | case 'i': | |
3354 | if (CONSTANT_P (operand) | |
7151fd0e | 3355 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand))) |
42c63e4d | 3356 | win = 1; |
3357 | break; | |
3358 | ||
3359 | case 'n': | |
971ba038 | 3360 | if (CONST_INT_P (operand) |
42c63e4d | 3361 | || (GET_CODE (operand) == CONST_DOUBLE |
3362 | && GET_MODE (operand) == VOIDmode)) | |
3363 | win = 1; | |
3364 | break; | |
3365 | ||
3366 | case 'I': | |
3367 | case 'J': | |
3368 | case 'K': | |
3369 | case 'L': | |
3370 | case 'M': | |
3371 | case 'N': | |
3372 | case 'O': | |
3373 | case 'P': | |
971ba038 | 3374 | if (CONST_INT_P (operand) |
48ea5577 | 3375 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operand), c, p)) |
42c63e4d | 3376 | win = 1; |
3377 | break; | |
3378 | ||
3379 | case 'X': | |
5f2bd98f | 3380 | force_reload = 0; |
42c63e4d | 3381 | win = 1; |
3382 | break; | |
3383 | ||
3384 | case 'g': | |
3385 | if (! force_reload | |
3386 | /* A PLUS is never a valid operand, but reload can make | |
3387 | it from a register when eliminating registers. */ | |
3388 | && GET_CODE (operand) != PLUS | |
3389 | /* A SCRATCH is not a valid operand. */ | |
3390 | && GET_CODE (operand) != SCRATCH | |
5bb2f919 | 3391 | && (! CONSTANT_P (operand) |
3392 | || ! flag_pic | |
42c63e4d | 3393 | || LEGITIMATE_PIC_OPERAND_P (operand)) |
42c63e4d | 3394 | && (GENERAL_REGS == ALL_REGS |
8ad4c111 | 3395 | || !REG_P (operand) |
42c63e4d | 3396 | || (REGNO (operand) >= FIRST_PSEUDO_REGISTER |
3397 | && reg_renumber[REGNO (operand)] < 0))) | |
3398 | win = 1; | |
aa35b87f | 3399 | /* Drop through into 'r' case. */ |
42c63e4d | 3400 | |
3401 | case 'r': | |
3402 | this_alternative[i] | |
b9c74b4d | 3403 | = reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS]; |
42c63e4d | 3404 | goto reg; |
3405 | ||
f3653a64 | 3406 | default: |
48ea5577 | 3407 | if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS) |
f3653a64 | 3408 | { |
48ea5577 | 3409 | #ifdef EXTRA_CONSTRAINT_STR |
3410 | if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
a5004c3d | 3411 | { |
3412 | if (force_reload) | |
3413 | break; | |
48ea5577 | 3414 | if (EXTRA_CONSTRAINT_STR (operand, c, p)) |
a5004c3d | 3415 | win = 1; |
3416 | /* If the address was already reloaded, | |
3417 | we win as well. */ | |
e16ceb8e | 3418 | else if (MEM_P (operand) |
e4542435 | 3419 | && address_reloaded[i] == 1) |
a5004c3d | 3420 | win = 1; |
3421 | /* Likewise if the address will be reloaded because | |
3422 | reg_equiv_address is nonzero. For reg_equiv_mem | |
3423 | we have to check. */ | |
8ad4c111 | 3424 | else if (REG_P (operand) |
76cfd4f9 | 3425 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER |
3426 | && reg_renumber[REGNO (operand)] < 0 | |
1c654ff1 | 3427 | && ((reg_equiv_mem (REGNO (operand)) != 0 |
3428 | && EXTRA_CONSTRAINT_STR (reg_equiv_mem (REGNO (operand)), c, p)) | |
3429 | || (reg_equiv_address (REGNO (operand)) != 0))) | |
a5004c3d | 3430 | win = 1; |
3431 | ||
3432 | /* If we didn't already win, we can reload | |
3433 | constants via force_const_mem, and other | |
3434 | MEMs by reloading the address like for 'o'. */ | |
7d7d7bd2 | 3435 | if (CONST_POOL_OK_P (operand_mode[i], operand) |
e16ceb8e | 3436 | || MEM_P (operand)) |
a5004c3d | 3437 | badop = 0; |
3438 | constmemok = 1; | |
3439 | offmemok = 1; | |
3440 | break; | |
3441 | } | |
48ea5577 | 3442 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) |
a5004c3d | 3443 | { |
48ea5577 | 3444 | if (EXTRA_CONSTRAINT_STR (operand, c, p)) |
a5004c3d | 3445 | win = 1; |
3446 | ||
3447 | /* If we didn't already win, we can reload | |
3448 | the address into a base register. */ | |
f8a8fc7b | 3449 | this_alternative[i] |
3450 | = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, | |
3451 | ADDRESS, SCRATCH); | |
a5004c3d | 3452 | badop = 0; |
3453 | break; | |
3454 | } | |
3455 | ||
48ea5577 | 3456 | if (EXTRA_CONSTRAINT_STR (operand, c, p)) |
f3653a64 | 3457 | win = 1; |
42c63e4d | 3458 | #endif |
f3653a64 | 3459 | break; |
3460 | } | |
5bb2f919 | 3461 | |
42c63e4d | 3462 | this_alternative[i] |
b9c74b4d | 3463 | = (reg_class_subunion |
3464 | [this_alternative[i]] | |
3465 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]); | |
42c63e4d | 3466 | reg: |
3467 | if (GET_MODE (operand) == BLKmode) | |
3468 | break; | |
3469 | winreg = 1; | |
8ad4c111 | 3470 | if (REG_P (operand) |
42c63e4d | 3471 | && reg_fits_class_p (operand, this_alternative[i], |
ed420a25 | 3472 | offset, GET_MODE (recog_data.operand[i]))) |
42c63e4d | 3473 | win = 1; |
3474 | break; | |
3475 | } | |
48ea5577 | 3476 | while ((p += len), c); |
42c63e4d | 3477 | |
3478 | constraints[i] = p; | |
3479 | ||
3480 | /* If this operand could be handled with a reg, | |
3481 | and some reg is allowed, then this operand can be handled. */ | |
bccb5444 | 3482 | if (winreg && this_alternative[i] != NO_REGS |
3483 | && (win || !class_only_fixed_regs[this_alternative[i]])) | |
42c63e4d | 3484 | badop = 0; |
3485 | ||
3486 | /* Record which operands fit this alternative. */ | |
3487 | this_alternative_earlyclobber[i] = earlyclobber; | |
3488 | if (win && ! force_reload) | |
3489 | this_alternative_win[i] = 1; | |
1aa1d9da | 3490 | else if (did_match && ! force_reload) |
3491 | this_alternative_match_win[i] = 1; | |
42c63e4d | 3492 | else |
3493 | { | |
f630a9b6 | 3494 | int const_to_mem = 0; |
3495 | ||
42c63e4d | 3496 | this_alternative_offmemok[i] = offmemok; |
3497 | losers++; | |
3498 | if (badop) | |
3499 | bad = 1; | |
3500 | /* Alternative loses if it has no regs for a reg operand. */ | |
8ad4c111 | 3501 | if (REG_P (operand) |
b9c74b4d | 3502 | && this_alternative[i] == NO_REGS |
42c63e4d | 3503 | && this_alternative_matches[i] < 0) |
3504 | bad = 1; | |
3505 | ||
f57d22b8 | 3506 | /* If this is a constant that is reloaded into the desired |
3507 | class by copying it to memory first, count that as another | |
3508 | reload. This is consistent with other code and is | |
df4c0ecd | 3509 | required to avoid choosing another alternative when |
f57d22b8 | 3510 | the constant is moved into memory by this function on |
5bb2f919 | 3511 | an early reload pass. Note that the test here is |
f57d22b8 | 3512 | precisely the same as in the code below that calls |
3513 | force_const_mem. */ | |
7d7d7bd2 | 3514 | if (CONST_POOL_OK_P (operand_mode[i], operand) |
09a17585 | 3515 | && ((targetm.preferred_reload_class (operand, |
3516 | this_alternative[i]) | |
997d68fe | 3517 | == NO_REGS) |
7d7d7bd2 | 3518 | || no_input_reloads)) |
f630a9b6 | 3519 | { |
3520 | const_to_mem = 1; | |
b9c74b4d | 3521 | if (this_alternative[i] != NO_REGS) |
f630a9b6 | 3522 | losers++; |
3523 | } | |
f57d22b8 | 3524 | |
997d68fe | 3525 | /* Alternative loses if it requires a type of reload not |
3526 | permitted for this insn. We can always reload SCRATCH | |
3527 | and objects with a REG_UNUSED note. */ | |
897f76b2 | 3528 | if (GET_CODE (operand) != SCRATCH |
5bb2f919 | 3529 | && modified[i] != RELOAD_READ && no_output_reloads |
3530 | && ! find_reg_note (insn, REG_UNUSED, operand)) | |
997d68fe | 3531 | bad = 1; |
3532 | else if (modified[i] != RELOAD_WRITE && no_input_reloads | |
3533 | && ! const_to_mem) | |
3534 | bad = 1; | |
3535 | ||
897f76b2 | 3536 | /* If we can't reload this value at all, reject this |
3537 | alternative. Note that we could also lose due to | |
3538 | LIMIT_RELOAD_CLASS, but we don't check that | |
3539 | here. */ | |
3540 | ||
b9c74b4d | 3541 | if (! CONSTANT_P (operand) && this_alternative[i] != NO_REGS) |
897f76b2 | 3542 | { |
09a17585 | 3543 | if (targetm.preferred_reload_class (operand, this_alternative[i]) |
897f76b2 | 3544 | == NO_REGS) |
3545 | reject = 600; | |
3546 | ||
897f76b2 | 3547 | if (operand_type[i] == RELOAD_FOR_OUTPUT |
71db0d8b | 3548 | && (targetm.preferred_output_reload_class (operand, |
3549 | this_alternative[i]) | |
b9c74b4d | 3550 | == NO_REGS)) |
897f76b2 | 3551 | reject = 600; |
897f76b2 | 3552 | } |
3553 | ||
42c63e4d | 3554 | /* We prefer to reload pseudos over reloading other things, |
3555 | since such reloads may be able to be eliminated later. | |
3556 | If we are reloading a SCRATCH, we won't be generating any | |
5bb2f919 | 3557 | insns, just using a register, so it is also preferred. |
f630a9b6 | 3558 | So bump REJECT in other cases. Don't do this in the |
3559 | case where we are forcing a constant into memory and | |
3560 | it will then win since we don't want to have a different | |
3561 | alternative match then. */ | |
8ad4c111 | 3562 | if (! (REG_P (operand) |
9f27e2b4 | 3563 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER) |
f630a9b6 | 3564 | && GET_CODE (operand) != SCRATCH |
3565 | && ! (const_to_mem && constmemok)) | |
c988df6a | 3566 | reject += 2; |
3567 | ||
3568 | /* Input reloads can be inherited more often than output | |
3569 | reloads can be removed, so penalize output reloads. */ | |
c63a4c84 | 3570 | if (operand_type[i] != RELOAD_FOR_INPUT |
3571 | && GET_CODE (operand) != SCRATCH) | |
42c63e4d | 3572 | reject++; |
3573 | } | |
3574 | ||
5bb2f919 | 3575 | /* If this operand is a pseudo register that didn't get a hard |
42c63e4d | 3576 | reg and this alternative accepts some register, see if the |
3577 | class that we want is a subset of the preferred class for this | |
3578 | register. If not, but it intersects that class, use the | |
3579 | preferred class instead. If it does not intersect the preferred | |
3580 | class, show that usage of this alternative should be discouraged; | |
3581 | it will be discouraged more still if the register is `preferred | |
3582 | or nothing'. We do this because it increases the chance of | |
3583 | reusing our spill register in a later insn and avoiding a pair | |
3584 | of memory stores and loads. | |
3585 | ||
3586 | Don't bother with this if this alternative will accept this | |
3587 | operand. | |
3588 | ||
d5705e3f | 3589 | Don't do this for a multiword operand, since it is only a |
3590 | small win and has the risk of requiring more spill registers, | |
3591 | which could cause a large loss. | |
a2f33c6e | 3592 | |
42c63e4d | 3593 | Don't do this if the preferred class has only one register |
3594 | because we might otherwise exhaust the class. */ | |
3595 | ||
1aa1d9da | 3596 | if (! win && ! did_match |
b9c74b4d | 3597 | && this_alternative[i] != NO_REGS |
a2f33c6e | 3598 | && GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD |
be77efb1 | 3599 | && reg_class_size [(int) preferred_class[i]] > 0 |
24dd0668 | 3600 | && ! small_register_class_p (preferred_class[i])) |
42c63e4d | 3601 | { |
3602 | if (! reg_class_subset_p (this_alternative[i], | |
3603 | preferred_class[i])) | |
3604 | { | |
3605 | /* Since we don't have a way of forming the intersection, | |
3606 | we just do something special if the preferred class | |
5bb2f919 | 3607 | is a subset of the class we have; that's the most |
42c63e4d | 3608 | common case anyway. */ |
3609 | if (reg_class_subset_p (preferred_class[i], | |
3610 | this_alternative[i])) | |
b9c74b4d | 3611 | this_alternative[i] = preferred_class[i]; |
42c63e4d | 3612 | else |
c988df6a | 3613 | reject += (2 + 2 * pref_or_nothing[i]); |
42c63e4d | 3614 | } |
3615 | } | |
3616 | } | |
3617 | ||
3618 | /* Now see if any output operands that are marked "earlyclobber" | |
3619 | in this alternative conflict with any input operands | |
3620 | or any memory addresses. */ | |
3621 | ||
3622 | for (i = 0; i < noperands; i++) | |
3623 | if (this_alternative_earlyclobber[i] | |
1aa1d9da | 3624 | && (this_alternative_win[i] || this_alternative_match_win[i])) |
42c63e4d | 3625 | { |
5bb2f919 | 3626 | struct decomposition early_data; |
42c63e4d | 3627 | |
ed420a25 | 3628 | early_data = decompose (recog_data.operand[i]); |
42c63e4d | 3629 | |
04e579b6 | 3630 | gcc_assert (modified[i] != RELOAD_READ); |
5bb2f919 | 3631 | |
42c63e4d | 3632 | if (this_alternative[i] == NO_REGS) |
3633 | { | |
3634 | this_alternative_earlyclobber[i] = 0; | |
04e579b6 | 3635 | gcc_assert (this_insn_is_asm); |
3636 | error_for_asm (this_insn, | |
eb586f2c | 3637 | "%<&%> constraint used with no register class"); |
42c63e4d | 3638 | } |
3639 | ||
3640 | for (j = 0; j < noperands; j++) | |
3641 | /* Is this an input operand or a memory ref? */ | |
e16ceb8e | 3642 | if ((MEM_P (recog_data.operand[j]) |
42c63e4d | 3643 | || modified[j] != RELOAD_WRITE) |
3644 | && j != i | |
3645 | /* Ignore things like match_operator operands. */ | |
a67a82ef | 3646 | && !recog_data.is_operator[j] |
42c63e4d | 3647 | /* Don't count an input operand that is constrained to match |
3648 | the early clobber operand. */ | |
3649 | && ! (this_alternative_matches[j] == i | |
ed420a25 | 3650 | && rtx_equal_p (recog_data.operand[i], |
3651 | recog_data.operand[j])) | |
42c63e4d | 3652 | /* Is it altered by storing the earlyclobber operand? */ |
ed420a25 | 3653 | && !immune_p (recog_data.operand[j], recog_data.operand[i], |
3654 | early_data)) | |
42c63e4d | 3655 | { |
be77efb1 | 3656 | /* If the output is in a non-empty few-regs class, |
42c63e4d | 3657 | it's costly to reload it, so reload the input instead. */ |
24dd0668 | 3658 | if (small_register_class_p (this_alternative[i]) |
8ad4c111 | 3659 | && (REG_P (recog_data.operand[j]) |
ed420a25 | 3660 | || GET_CODE (recog_data.operand[j]) == SUBREG)) |
42c63e4d | 3661 | { |
3662 | losers++; | |
3663 | this_alternative_win[j] = 0; | |
1aa1d9da | 3664 | this_alternative_match_win[j] = 0; |
42c63e4d | 3665 | } |
3666 | else | |
3667 | break; | |
3668 | } | |
3669 | /* If an earlyclobber operand conflicts with something, | |
3670 | it must be reloaded, so request this and count the cost. */ | |
3671 | if (j != noperands) | |
3672 | { | |
3673 | losers++; | |
3674 | this_alternative_win[i] = 0; | |
1aa1d9da | 3675 | this_alternative_match_win[j] = 0; |
42c63e4d | 3676 | for (j = 0; j < noperands; j++) |
3677 | if (this_alternative_matches[j] == i | |
1aa1d9da | 3678 | && this_alternative_match_win[j]) |
42c63e4d | 3679 | { |
3680 | this_alternative_win[j] = 0; | |
1aa1d9da | 3681 | this_alternative_match_win[j] = 0; |
42c63e4d | 3682 | losers++; |
3683 | } | |
3684 | } | |
3685 | } | |
3686 | ||
3687 | /* If one alternative accepts all the operands, no reload required, | |
3688 | choose that alternative; don't consider the remaining ones. */ | |
3689 | if (losers == 0) | |
3690 | { | |
3691 | /* Unswap these so that they are never swapped at `finish'. */ | |
3692 | if (commutative >= 0) | |
3693 | { | |
ed420a25 | 3694 | recog_data.operand[commutative] = substed_operand[commutative]; |
3695 | recog_data.operand[commutative + 1] | |
42c63e4d | 3696 | = substed_operand[commutative + 1]; |
3697 | } | |
3698 | for (i = 0; i < noperands; i++) | |
3699 | { | |
1aa1d9da | 3700 | goal_alternative_win[i] = this_alternative_win[i]; |
3701 | goal_alternative_match_win[i] = this_alternative_match_win[i]; | |
71db0d8b | 3702 | goal_alternative[i] = this_alternative[i]; |
42c63e4d | 3703 | goal_alternative_offmemok[i] = this_alternative_offmemok[i]; |
3704 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3705 | goal_alternative_earlyclobber[i] | |
3706 | = this_alternative_earlyclobber[i]; | |
3707 | } | |
3708 | goal_alternative_number = this_alternative_number; | |
3709 | goal_alternative_swapped = swapped; | |
3710 | goal_earlyclobber = this_earlyclobber; | |
3711 | goto finish; | |
3712 | } | |
3713 | ||
3714 | /* REJECT, set by the ! and ? constraint characters and when a register | |
3715 | would be reloaded into a non-preferred class, discourages the use of | |
c988df6a | 3716 | this alternative for a reload goal. REJECT is incremented by six |
3717 | for each ? and two for each non-preferred class. */ | |
3718 | losers = losers * 6 + reject; | |
42c63e4d | 3719 | |
3720 | /* If this alternative can be made to work by reloading, | |
3721 | and it needs less reloading than the others checked so far, | |
3722 | record it as the chosen goal for reloading. */ | |
a7dcf969 | 3723 | if (! bad) |
42c63e4d | 3724 | { |
9b14e0fd | 3725 | if (best > losers) |
a7dcf969 | 3726 | { |
3727 | for (i = 0; i < noperands; i++) | |
3728 | { | |
71db0d8b | 3729 | goal_alternative[i] = this_alternative[i]; |
a7dcf969 | 3730 | goal_alternative_win[i] = this_alternative_win[i]; |
3731 | goal_alternative_match_win[i] | |
3732 | = this_alternative_match_win[i]; | |
3733 | goal_alternative_offmemok[i] | |
3734 | = this_alternative_offmemok[i]; | |
3735 | goal_alternative_matches[i] = this_alternative_matches[i]; | |
3736 | goal_alternative_earlyclobber[i] | |
3737 | = this_alternative_earlyclobber[i]; | |
3738 | } | |
3739 | goal_alternative_swapped = swapped; | |
3740 | best = losers; | |
a7dcf969 | 3741 | goal_alternative_number = this_alternative_number; |
3742 | goal_earlyclobber = this_earlyclobber; | |
42c63e4d | 3743 | } |
42c63e4d | 3744 | } |
3745 | } | |
3746 | ||
3747 | /* If insn is commutative (it's safe to exchange a certain pair of operands) | |
3748 | then we need to try each alternative twice, | |
3749 | the second time matching those two operands | |
3750 | as if we had exchanged them. | |
3751 | To do this, really exchange them in operands. | |
3752 | ||
3753 | If we have just tried the alternatives the second time, | |
3754 | return operands to normal and drop through. */ | |
3755 | ||
3756 | if (commutative >= 0) | |
3757 | { | |
3758 | swapped = !swapped; | |
3759 | if (swapped) | |
3760 | { | |
19cb6b50 | 3761 | enum reg_class tclass; |
3762 | int t; | |
42c63e4d | 3763 | |
ed420a25 | 3764 | recog_data.operand[commutative] = substed_operand[commutative + 1]; |
3765 | recog_data.operand[commutative + 1] = substed_operand[commutative]; | |
6964f998 | 3766 | /* Swap the duplicates too. */ |
3767 | for (i = 0; i < recog_data.n_dups; i++) | |
3768 | if (recog_data.dup_num[i] == commutative | |
3769 | || recog_data.dup_num[i] == commutative + 1) | |
3770 | *recog_data.dup_loc[i] | |
3771 | = recog_data.operand[(int) recog_data.dup_num[i]]; | |
42c63e4d | 3772 | |
3773 | tclass = preferred_class[commutative]; | |
3774 | preferred_class[commutative] = preferred_class[commutative + 1]; | |
3775 | preferred_class[commutative + 1] = tclass; | |
3776 | ||
3777 | t = pref_or_nothing[commutative]; | |
3778 | pref_or_nothing[commutative] = pref_or_nothing[commutative + 1]; | |
3779 | pref_or_nothing[commutative + 1] = t; | |
3780 | ||
565720f3 | 3781 | t = address_reloaded[commutative]; |
3782 | address_reloaded[commutative] = address_reloaded[commutative + 1]; | |
3783 | address_reloaded[commutative + 1] = t; | |
3784 | ||
d844aacc | 3785 | memcpy (constraints, recog_data.constraints, |
39a1a66f | 3786 | noperands * sizeof (const char *)); |
42c63e4d | 3787 | goto try_swapped; |
3788 | } | |
3789 | else | |
3790 | { | |
ed420a25 | 3791 | recog_data.operand[commutative] = substed_operand[commutative]; |
3792 | recog_data.operand[commutative + 1] | |
3793 | = substed_operand[commutative + 1]; | |
6964f998 | 3794 | /* Unswap the duplicates too. */ |
3795 | for (i = 0; i < recog_data.n_dups; i++) | |
3796 | if (recog_data.dup_num[i] == commutative | |
3797 | || recog_data.dup_num[i] == commutative + 1) | |
3798 | *recog_data.dup_loc[i] | |
3799 | = recog_data.operand[(int) recog_data.dup_num[i]]; | |
42c63e4d | 3800 | } |
3801 | } | |
3802 | ||
3803 | /* The operands don't meet the constraints. | |
3804 | goal_alternative describes the alternative | |
3805 | that we could reach by reloading the fewest operands. | |
3806 | Reload so as to fit it. */ | |
3807 | ||
9c74cd6d | 3808 | if (best == MAX_RECOG_OPERANDS * 2 + 600) |
42c63e4d | 3809 | { |
3810 | /* No alternative works with reloads?? */ | |
3811 | if (insn_code_number >= 0) | |
cb8bacb6 | 3812 | fatal_insn ("unable to generate reloads for:", insn); |
eb586f2c | 3813 | error_for_asm (insn, "inconsistent operand constraints in an %<asm%>"); |
42c63e4d | 3814 | /* Avoid further trouble with this insn. */ |
941522d6 | 3815 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
42c63e4d | 3816 | n_reloads = 0; |
93c7b06e | 3817 | return 0; |
42c63e4d | 3818 | } |
3819 | ||
3820 | /* Jump to `finish' from above if all operands are valid already. | |
3821 | In that case, goal_alternative_win is all 1. */ | |
3822 | finish: | |
3823 | ||
3824 | /* Right now, for any pair of operands I and J that are required to match, | |
3825 | with I < J, | |
3826 | goal_alternative_matches[J] is I. | |
3827 | Set up goal_alternative_matched as the inverse function: | |
3828 | goal_alternative_matched[I] = J. */ | |
3829 | ||
3830 | for (i = 0; i < noperands; i++) | |
3831 | goal_alternative_matched[i] = -1; | |
2617fe26 | 3832 | |
42c63e4d | 3833 | for (i = 0; i < noperands; i++) |
3834 | if (! goal_alternative_win[i] | |
3835 | && goal_alternative_matches[i] >= 0) | |
3836 | goal_alternative_matched[goal_alternative_matches[i]] = i; | |
3837 | ||
1aa1d9da | 3838 | for (i = 0; i < noperands; i++) |
3839 | goal_alternative_win[i] |= goal_alternative_match_win[i]; | |
3840 | ||
42c63e4d | 3841 | /* If the best alternative is with operands 1 and 2 swapped, |
70457512 | 3842 | consider them swapped before reporting the reloads. Update the |
3843 | operand numbers of any reloads already pushed. */ | |
42c63e4d | 3844 | |
3845 | if (goal_alternative_swapped) | |
3846 | { | |
19cb6b50 | 3847 | rtx tem; |
42c63e4d | 3848 | |
3849 | tem = substed_operand[commutative]; | |
3850 | substed_operand[commutative] = substed_operand[commutative + 1]; | |
3851 | substed_operand[commutative + 1] = tem; | |
ed420a25 | 3852 | tem = recog_data.operand[commutative]; |
3853 | recog_data.operand[commutative] = recog_data.operand[commutative + 1]; | |
3854 | recog_data.operand[commutative + 1] = tem; | |
3855 | tem = *recog_data.operand_loc[commutative]; | |
3856 | *recog_data.operand_loc[commutative] | |
3857 | = *recog_data.operand_loc[commutative + 1]; | |
67610d42 | 3858 | *recog_data.operand_loc[commutative + 1] = tem; |
70457512 | 3859 | |
3860 | for (i = 0; i < n_reloads; i++) | |
3861 | { | |
48666d2c | 3862 | if (rld[i].opnum == commutative) |
3863 | rld[i].opnum = commutative + 1; | |
3864 | else if (rld[i].opnum == commutative + 1) | |
3865 | rld[i].opnum = commutative; | |
70457512 | 3866 | } |
42c63e4d | 3867 | } |
3868 | ||
42c63e4d | 3869 | for (i = 0; i < noperands; i++) |
3870 | { | |
42c63e4d | 3871 | operand_reloadnum[i] = -1; |
70457512 | 3872 | |
3873 | /* If this is an earlyclobber operand, we need to widen the scope. | |
3874 | The reload must remain valid from the start of the insn being | |
3875 | reloaded until after the operand is stored into its destination. | |
3876 | We approximate this with RELOAD_OTHER even though we know that we | |
3877 | do not conflict with RELOAD_FOR_INPUT_ADDRESS reloads. | |
3878 | ||
3879 | One special case that is worth checking is when we have an | |
3880 | output that is earlyclobber but isn't used past the insn (typically | |
5bb2f919 | 3881 | a SCRATCH). In this case, we only need have the reload live |
70457512 | 3882 | through the insn itself, but not for any of our input or output |
5bb2f919 | 3883 | reloads. |
5596d410 | 3884 | But we must not accidentally narrow the scope of an existing |
3885 | RELOAD_OTHER reload - leave these alone. | |
70457512 | 3886 | |
3887 | In any case, anything needed to address this operand can remain | |
3888 | however they were previously categorized. */ | |
3889 | ||
5596d410 | 3890 | if (goal_alternative_earlyclobber[i] && operand_type[i] != RELOAD_OTHER) |
70457512 | 3891 | operand_type[i] |
ed420a25 | 3892 | = (find_reg_note (insn, REG_UNUSED, recog_data.operand[i]) |
70457512 | 3893 | ? RELOAD_FOR_INSN : RELOAD_OTHER); |
42c63e4d | 3894 | } |
3895 | ||
3896 | /* Any constants that aren't allowed and can't be reloaded | |
3897 | into registers are here changed into memory references. */ | |
3898 | for (i = 0; i < noperands; i++) | |
7721da81 | 3899 | if (! goal_alternative_win[i]) |
42c63e4d | 3900 | { |
7721da81 | 3901 | rtx op = recog_data.operand[i]; |
3902 | rtx subreg = NULL_RTX; | |
3903 | rtx plus = NULL_RTX; | |
3904 | enum machine_mode mode = operand_mode[i]; | |
3905 | ||
3906 | /* Reloads of SUBREGs of CONSTANT RTXs are handled later in | |
3907 | push_reload so we have to let them pass here. */ | |
3908 | if (GET_CODE (op) == SUBREG) | |
3909 | { | |
3910 | subreg = op; | |
3911 | op = SUBREG_REG (op); | |
3912 | mode = GET_MODE (op); | |
3913 | } | |
53716799 | 3914 | |
7721da81 | 3915 | if (GET_CODE (op) == PLUS) |
3916 | { | |
3917 | plus = op; | |
3918 | op = XEXP (op, 1); | |
3919 | } | |
42c63e4d | 3920 | |
7d7d7bd2 | 3921 | if (CONST_POOL_OK_P (mode, op) |
09a17585 | 3922 | && ((targetm.preferred_reload_class (op, goal_alternative[i]) |
7721da81 | 3923 | == NO_REGS) |
7d7d7bd2 | 3924 | || no_input_reloads)) |
7721da81 | 3925 | { |
3926 | int this_address_reloaded; | |
3927 | rtx tem = force_const_mem (mode, op); | |
b3c5ca3e | 3928 | |
7721da81 | 3929 | /* If we stripped a SUBREG or a PLUS above add it back. */ |
3930 | if (plus != NULL_RTX) | |
3931 | tem = gen_rtx_PLUS (mode, XEXP (plus, 0), tem); | |
3932 | ||
3933 | if (subreg != NULL_RTX) | |
3934 | tem = gen_rtx_SUBREG (operand_mode[i], tem, SUBREG_BYTE (subreg)); | |
3935 | ||
3936 | this_address_reloaded = 0; | |
3937 | substed_operand[i] = recog_data.operand[i] | |
3938 | = find_reloads_toplev (tem, i, address_type[i], ind_levels, | |
3939 | 0, insn, &this_address_reloaded); | |
3940 | ||
3941 | /* If the alternative accepts constant pool refs directly | |
3942 | there will be no reload needed at all. */ | |
3943 | if (plus == NULL_RTX | |
3944 | && subreg == NULL_RTX | |
3945 | && alternative_allows_const_pool_ref (this_address_reloaded == 0 | |
3946 | ? substed_operand[i] | |
3947 | : NULL, | |
3948 | recog_data.constraints[i], | |
3949 | goal_alternative_number)) | |
3950 | goal_alternative_win[i] = 1; | |
3951 | } | |
b3c5ca3e | 3952 | } |
3953 | ||
3e561fd5 | 3954 | /* Record the values of the earlyclobber operands for the caller. */ |
3955 | if (goal_earlyclobber) | |
3956 | for (i = 0; i < noperands; i++) | |
3957 | if (goal_alternative_earlyclobber[i]) | |
ed420a25 | 3958 | reload_earlyclobbers[n_earlyclobbers++] = recog_data.operand[i]; |
3e561fd5 | 3959 | |
42c63e4d | 3960 | /* Now record reloads for all the operands that need them. */ |
3961 | for (i = 0; i < noperands; i++) | |
3962 | if (! goal_alternative_win[i]) | |
3963 | { | |
3964 | /* Operands that match previous ones have already been handled. */ | |
3965 | if (goal_alternative_matches[i] >= 0) | |
3966 | ; | |
3967 | /* Handle an operand with a nonoffsettable address | |
3968 | appearing where an offsettable address will do | |
f57d22b8 | 3969 | by reloading the address into a base register. |
3970 | ||
3971 | ??? We can also do this when the operand is a register and | |
3972 | reg_equiv_mem is not offsettable, but this is a bit tricky, | |
3973 | so we don't bother with it. It may not be worth doing. */ | |
42c63e4d | 3974 | else if (goal_alternative_matched[i] == -1 |
3975 | && goal_alternative_offmemok[i] | |
e16ceb8e | 3976 | && MEM_P (recog_data.operand[i])) |
42c63e4d | 3977 | { |
91e1886d | 3978 | /* If the address to be reloaded is a VOIDmode constant, |
98155838 | 3979 | use the default address mode as mode of the reload register, |
3980 | as would have been done by find_reloads_address. */ | |
f8a8fc7b | 3981 | addr_space_t as = MEM_ADDR_SPACE (recog_data.operand[i]); |
91e1886d | 3982 | enum machine_mode address_mode; |
3983 | address_mode = GET_MODE (XEXP (recog_data.operand[i], 0)); | |
3984 | if (address_mode == VOIDmode) | |
f8a8fc7b | 3985 | address_mode = targetm.addr_space.address_mode (as); |
91e1886d | 3986 | |
42c63e4d | 3987 | operand_reloadnum[i] |
ed420a25 | 3988 | = push_reload (XEXP (recog_data.operand[i], 0), NULL_RTX, |
33181afc | 3989 | &XEXP (recog_data.operand[i], 0), (rtx*) 0, |
f8a8fc7b | 3990 | base_reg_class (VOIDmode, as, MEM, SCRATCH), |
91e1886d | 3991 | address_mode, |
70457512 | 3992 | VOIDmode, 0, 0, i, RELOAD_FOR_INPUT); |
48666d2c | 3993 | rld[operand_reloadnum[i]].inc |
ed420a25 | 3994 | = GET_MODE_SIZE (GET_MODE (recog_data.operand[i])); |
70457512 | 3995 | |
3996 | /* If this operand is an output, we will have made any | |
3997 | reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but | |
3998 | now we are treating part of the operand as an input, so | |
3999 | we must change these to RELOAD_FOR_INPUT_ADDRESS. */ | |
4000 | ||
6d7ad5dc | 4001 | if (modified[i] == RELOAD_WRITE) |
9e53d777 | 4002 | { |
4003 | for (j = 0; j < n_reloads; j++) | |
4004 | { | |
48666d2c | 4005 | if (rld[j].opnum == i) |
9e53d777 | 4006 | { |
48666d2c | 4007 | if (rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS) |
4008 | rld[j].when_needed = RELOAD_FOR_INPUT_ADDRESS; | |
4009 | else if (rld[j].when_needed | |
9e53d777 | 4010 | == RELOAD_FOR_OUTADDR_ADDRESS) |
48666d2c | 4011 | rld[j].when_needed = RELOAD_FOR_INPADDR_ADDRESS; |
9e53d777 | 4012 | } |
4013 | } | |
4014 | } | |
42c63e4d | 4015 | } |
4016 | else if (goal_alternative_matched[i] == -1) | |
9e042f31 | 4017 | { |
4018 | operand_reloadnum[i] | |
4019 | = push_reload ((modified[i] != RELOAD_WRITE | |
ed420a25 | 4020 | ? recog_data.operand[i] : 0), |
4021 | (modified[i] != RELOAD_READ | |
4022 | ? recog_data.operand[i] : 0), | |
9e042f31 | 4023 | (modified[i] != RELOAD_WRITE |
ed420a25 | 4024 | ? recog_data.operand_loc[i] : 0), |
9e042f31 | 4025 | (modified[i] != RELOAD_READ |
ed420a25 | 4026 | ? recog_data.operand_loc[i] : 0), |
9e042f31 | 4027 | (enum reg_class) goal_alternative[i], |
4028 | (modified[i] == RELOAD_WRITE | |
4029 | ? VOIDmode : operand_mode[i]), | |
4030 | (modified[i] == RELOAD_READ | |
4031 | ? VOIDmode : operand_mode[i]), | |
4032 | (insn_code_number < 0 ? 0 | |
6357eaae | 4033 | : insn_data[insn_code_number].operand[i].strict_low), |
9e042f31 | 4034 | 0, i, operand_type[i]); |
9e042f31 | 4035 | } |
42c63e4d | 4036 | /* In a matching pair of operands, one must be input only |
4037 | and the other must be output only. | |
4038 | Pass the input operand as IN and the other as OUT. */ | |
4039 | else if (modified[i] == RELOAD_READ | |
4040 | && modified[goal_alternative_matched[i]] == RELOAD_WRITE) | |
4041 | { | |
4042 | operand_reloadnum[i] | |
ed420a25 | 4043 | = push_reload (recog_data.operand[i], |
4044 | recog_data.operand[goal_alternative_matched[i]], | |
4045 | recog_data.operand_loc[i], | |
4046 | recog_data.operand_loc[goal_alternative_matched[i]], | |
42c63e4d | 4047 | (enum reg_class) goal_alternative[i], |
4048 | operand_mode[i], | |
4049 | operand_mode[goal_alternative_matched[i]], | |
70457512 | 4050 | 0, 0, i, RELOAD_OTHER); |
42c63e4d | 4051 | operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum; |
4052 | } | |
4053 | else if (modified[i] == RELOAD_WRITE | |
4054 | && modified[goal_alternative_matched[i]] == RELOAD_READ) | |
4055 | { | |
4056 | operand_reloadnum[goal_alternative_matched[i]] | |
ed420a25 | 4057 | = push_reload (recog_data.operand[goal_alternative_matched[i]], |
4058 | recog_data.operand[i], | |
4059 | recog_data.operand_loc[goal_alternative_matched[i]], | |
4060 | recog_data.operand_loc[i], | |
42c63e4d | 4061 | (enum reg_class) goal_alternative[i], |
4062 | operand_mode[goal_alternative_matched[i]], | |
4063 | operand_mode[i], | |
70457512 | 4064 | 0, 0, i, RELOAD_OTHER); |
42c63e4d | 4065 | operand_reloadnum[i] = output_reloadnum; |
4066 | } | |
42c63e4d | 4067 | else |
4068 | { | |
04e579b6 | 4069 | gcc_assert (insn_code_number < 0); |
eb586f2c | 4070 | error_for_asm (insn, "inconsistent operand constraints " |
4071 | "in an %<asm%>"); | |
42c63e4d | 4072 | /* Avoid further trouble with this insn. */ |
941522d6 | 4073 | PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx); |
42c63e4d | 4074 | n_reloads = 0; |
93c7b06e | 4075 | return 0; |
42c63e4d | 4076 | } |
4077 | } | |
4078 | else if (goal_alternative_matched[i] < 0 | |
b43a3b62 | 4079 | && goal_alternative_matches[i] < 0 |
e4542435 | 4080 | && address_operand_reloaded[i] != 1 |
b43a3b62 | 4081 | && optimize) |
42c63e4d | 4082 | { |
5bb2f919 | 4083 | /* For each non-matching operand that's a MEM or a pseudo-register |
42c63e4d | 4084 | that didn't get a hard register, make an optional reload. |
4085 | This may get done even if the insn needs no reloads otherwise. */ | |
70457512 | 4086 | |
ed420a25 | 4087 | rtx operand = recog_data.operand[i]; |
70457512 | 4088 | |
42c63e4d | 4089 | while (GET_CODE (operand) == SUBREG) |
701e46d0 | 4090 | operand = SUBREG_REG (operand); |
e16ceb8e | 4091 | if ((MEM_P (operand) |
8ad4c111 | 4092 | || (REG_P (operand) |
70457512 | 4093 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) |
93c7b06e | 4094 | /* If this is only for an output, the optional reload would not |
4095 | actually cause us to use a register now, just note that | |
4096 | something is stored here. */ | |
09a17585 | 4097 | && (goal_alternative[i] != NO_REGS |
93c7b06e | 4098 | || modified[i] == RELOAD_WRITE) |
70457512 | 4099 | && ! no_input_reloads |
93c7b06e | 4100 | /* An optional output reload might allow to delete INSN later. |
4101 | We mustn't make in-out reloads on insns that are not permitted | |
4102 | output reloads. | |
4103 | If this is an asm, we can't delete it; we must not even call | |
4104 | push_reload for an optional output reload in this case, | |
4105 | because we can't be sure that the constraint allows a register, | |
4106 | and push_reload verifies the constraints for asms. */ | |
42c63e4d | 4107 | && (modified[i] == RELOAD_READ |
93c7b06e | 4108 | || (! no_output_reloads && ! this_insn_is_asm))) |
42c63e4d | 4109 | operand_reloadnum[i] |
ed420a25 | 4110 | = push_reload ((modified[i] != RELOAD_WRITE |
4111 | ? recog_data.operand[i] : 0), | |
4112 | (modified[i] != RELOAD_READ | |
4113 | ? recog_data.operand[i] : 0), | |
70457512 | 4114 | (modified[i] != RELOAD_WRITE |
ed420a25 | 4115 | ? recog_data.operand_loc[i] : 0), |
70457512 | 4116 | (modified[i] != RELOAD_READ |
ed420a25 | 4117 | ? recog_data.operand_loc[i] : 0), |
42c63e4d | 4118 | (enum reg_class) goal_alternative[i], |
70457512 | 4119 | (modified[i] == RELOAD_WRITE |
4120 | ? VOIDmode : operand_mode[i]), | |
4121 | (modified[i] == RELOAD_READ | |
4122 | ? VOIDmode : operand_mode[i]), | |
42c63e4d | 4123 | (insn_code_number < 0 ? 0 |
6357eaae | 4124 | : insn_data[insn_code_number].operand[i].strict_low), |
70457512 | 4125 | 1, i, operand_type[i]); |
b26819b2 | 4126 | /* If a memory reference remains (either as a MEM or a pseudo that |
4127 | did not get a hard register), yet we can't make an optional | |
93c7b06e | 4128 | reload, check if this is actually a pseudo register reference; |
4129 | we then need to emit a USE and/or a CLOBBER so that reload | |
4130 | inheritance will do the right thing. */ | |
b43a3b62 | 4131 | else if (replace |
e16ceb8e | 4132 | && (MEM_P (operand) |
8ad4c111 | 4133 | || (REG_P (operand) |
b43a3b62 | 4134 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER |
4135 | && reg_renumber [REGNO (operand)] < 0))) | |
93c7b06e | 4136 | { |
ed420a25 | 4137 | operand = *recog_data.operand_loc[i]; |
93c7b06e | 4138 | |
4139 | while (GET_CODE (operand) == SUBREG) | |
701e46d0 | 4140 | operand = SUBREG_REG (operand); |
8ad4c111 | 4141 | if (REG_P (operand)) |
93c7b06e | 4142 | { |
4143 | if (modified[i] != RELOAD_WRITE) | |
b2920130 | 4144 | /* We mark the USE with QImode so that we recognize |
4145 | it as one that can be safely deleted at the end | |
4146 | of reload. */ | |
4147 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, operand), | |
4148 | insn), QImode); | |
93c7b06e | 4149 | if (modified[i] != RELOAD_READ) |
18b42941 | 4150 | emit_insn_after (gen_clobber (operand), insn); |
93c7b06e | 4151 | } |
4152 | } | |
42c63e4d | 4153 | } |
70457512 | 4154 | else if (goal_alternative_matches[i] >= 0 |
4155 | && goal_alternative_win[goal_alternative_matches[i]] | |
4156 | && modified[i] == RELOAD_READ | |
4157 | && modified[goal_alternative_matches[i]] == RELOAD_WRITE | |
b43a3b62 | 4158 | && ! no_input_reloads && ! no_output_reloads |
4159 | && optimize) | |
70457512 | 4160 | { |
4161 | /* Similarly, make an optional reload for a pair of matching | |
4162 | objects that are in MEM or a pseudo that didn't get a hard reg. */ | |
42c63e4d | 4163 | |
ed420a25 | 4164 | rtx operand = recog_data.operand[i]; |
70457512 | 4165 | |
4166 | while (GET_CODE (operand) == SUBREG) | |
701e46d0 | 4167 | operand = SUBREG_REG (operand); |
e16ceb8e | 4168 | if ((MEM_P (operand) |
8ad4c111 | 4169 | || (REG_P (operand) |
70457512 | 4170 | && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) |
09a17585 | 4171 | && (goal_alternative[goal_alternative_matches[i]] != NO_REGS)) |
70457512 | 4172 | operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]] |
ed420a25 | 4173 | = push_reload (recog_data.operand[goal_alternative_matches[i]], |
4174 | recog_data.operand[i], | |
4175 | recog_data.operand_loc[goal_alternative_matches[i]], | |
4176 | recog_data.operand_loc[i], | |
70457512 | 4177 | (enum reg_class) goal_alternative[goal_alternative_matches[i]], |
4178 | operand_mode[goal_alternative_matches[i]], | |
4179 | operand_mode[i], | |
4180 | 0, 1, goal_alternative_matches[i], RELOAD_OTHER); | |
4181 | } | |
5bb2f919 | 4182 | |
93c7b06e | 4183 | /* Perform whatever substitutions on the operands we are supposed |
4184 | to make due to commutativity or replacement of registers | |
4185 | with equivalent constants or memory slots. */ | |
4186 | ||
4187 | for (i = 0; i < noperands; i++) | |
4188 | { | |
4189 | /* We only do this on the last pass through reload, because it is | |
5bb2f919 | 4190 | possible for some data (like reg_equiv_address) to be changed during |
caebd015 | 4191 | later passes. Moreover, we lose the opportunity to get a useful |
5bb2f919 | 4192 | reload_{in,out}_reg when we do these replacements. */ |
93c7b06e | 4193 | |
4194 | if (replace) | |
e32e621c | 4195 | { |
4196 | rtx substitution = substed_operand[i]; | |
4197 | ||
ed420a25 | 4198 | *recog_data.operand_loc[i] = substitution; |
e32e621c | 4199 | |
19d2fe05 | 4200 | /* If we're replacing an operand with a LABEL_REF, we need to |
4201 | make sure that there's a REG_LABEL_OPERAND note attached to | |
e32e621c | 4202 | this instruction. */ |
19d2fe05 | 4203 | if (GET_CODE (substitution) == LABEL_REF |
4204 | && !find_reg_note (insn, REG_LABEL_OPERAND, | |
4205 | XEXP (substitution, 0)) | |
4206 | /* For a JUMP_P, if it was a branch target it must have | |
4207 | already been recorded as such. */ | |
4208 | && (!JUMP_P (insn) | |
4209 | || !label_is_jump_target_p (XEXP (substitution, 0), | |
4210 | insn))) | |
a1ddb869 | 4211 | add_reg_note (insn, REG_LABEL_OPERAND, XEXP (substitution, 0)); |
e32e621c | 4212 | } |
93c7b06e | 4213 | else |
ed420a25 | 4214 | retval |= (substed_operand[i] != *recog_data.operand_loc[i]); |
93c7b06e | 4215 | } |
4216 | ||
42c63e4d | 4217 | /* If this insn pattern contains any MATCH_DUP's, make sure that |
4218 | they will be substituted if the operands they match are substituted. | |
4219 | Also do now any substitutions we already did on the operands. | |
4220 | ||
4221 | Don't do this if we aren't making replacements because we might be | |
4222 | propagating things allocated by frame pointer elimination into places | |
4223 | it doesn't expect. */ | |
4224 | ||
4225 | if (insn_code_number >= 0 && replace) | |
6357eaae | 4226 | for (i = insn_data[insn_code_number].n_dups - 1; i >= 0; i--) |
42c63e4d | 4227 | { |
ed420a25 | 4228 | int opno = recog_data.dup_num[i]; |
4229 | *recog_data.dup_loc[i] = *recog_data.operand_loc[opno]; | |
520be5a2 | 4230 | dup_replacements (recog_data.dup_loc[i], recog_data.operand_loc[opno]); |
42c63e4d | 4231 | } |
4232 | ||
4233 | #if 0 | |
4234 | /* This loses because reloading of prior insns can invalidate the equivalence | |
4235 | (or at least find_equiv_reg isn't smart enough to find it any more), | |
4236 | causing this insn to need more reload regs than it needed before. | |
4237 | It may be too late to make the reload regs available. | |
4238 | Now this optimization is done safely in choose_reload_regs. */ | |
4239 | ||
4240 | /* For each reload of a reg into some other class of reg, | |
4241 | search for an existing equivalent reg (same value now) in the right class. | |
4242 | We can use it as long as we don't need to change its contents. */ | |
4243 | for (i = 0; i < n_reloads; i++) | |
48666d2c | 4244 | if (rld[i].reg_rtx == 0 |
4245 | && rld[i].in != 0 | |
8ad4c111 | 4246 | && REG_P (rld[i].in) |
48666d2c | 4247 | && rld[i].out == 0) |
42c63e4d | 4248 | { |
48666d2c | 4249 | rld[i].reg_rtx |
c32319fc | 4250 | = find_equiv_reg (rld[i].in, insn, rld[i].rclass, -1, |
48666d2c | 4251 | static_reload_reg_p, 0, rld[i].inmode); |
42c63e4d | 4252 | /* Prevent generation of insn to load the value |
4253 | because the one we found already has the value. */ | |
48666d2c | 4254 | if (rld[i].reg_rtx) |
4255 | rld[i].in = rld[i].reg_rtx; | |
42c63e4d | 4256 | } |
4257 | #endif | |
4258 | ||
7c679c65 | 4259 | /* If we detected error and replaced asm instruction by USE, forget about the |
4260 | reloads. */ | |
4261 | if (GET_CODE (PATTERN (insn)) == USE | |
971ba038 | 4262 | && CONST_INT_P (XEXP (PATTERN (insn), 0))) |
7c679c65 | 4263 | n_reloads = 0; |
4264 | ||
70457512 | 4265 | /* Perhaps an output reload can be combined with another |
4266 | to reduce needs by one. */ | |
4267 | if (!goal_earlyclobber) | |
4268 | combine_reloads (); | |
4269 | ||
4270 | /* If we have a pair of reloads for parts of an address, they are reloading | |
4271 | the same object, the operands themselves were not reloaded, and they | |
4272 | are for two operands that are supposed to match, merge the reloads and | |
a92771b8 | 4273 | change the type of the surviving reload to RELOAD_FOR_OPERAND_ADDRESS. */ |
70457512 | 4274 | |
4275 | for (i = 0; i < n_reloads; i++) | |
4276 | { | |
4277 | int k; | |
4278 | ||
4279 | for (j = i + 1; j < n_reloads; j++) | |
48666d2c | 4280 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS |
4281 | || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
4282 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS | |
4283 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4284 | && (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
4285 | || rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
4286 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS | |
4287 | || rld[j].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4288 | && rtx_equal_p (rld[i].in, rld[j].in) | |
4289 | && (operand_reloadnum[rld[i].opnum] < 0 | |
4290 | || rld[operand_reloadnum[rld[i].opnum]].optional) | |
4291 | && (operand_reloadnum[rld[j].opnum] < 0 | |
4292 | || rld[operand_reloadnum[rld[j].opnum]].optional) | |
4293 | && (goal_alternative_matches[rld[i].opnum] == rld[j].opnum | |
4294 | || (goal_alternative_matches[rld[j].opnum] | |
4295 | == rld[i].opnum))) | |
70457512 | 4296 | { |
4297 | for (k = 0; k < n_replacements; k++) | |
4298 | if (replacements[k].what == j) | |
4299 | replacements[k].what = i; | |
4300 | ||
48666d2c | 4301 | if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS |
4302 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4303 | rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR; | |
9e53d777 | 4304 | else |
48666d2c | 4305 | rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS; |
4306 | rld[j].in = 0; | |
70457512 | 4307 | } |
4308 | } | |
4309 | ||
5bb2f919 | 4310 | /* Scan all the reloads and update their type. |
70457512 | 4311 | If a reload is for the address of an operand and we didn't reload |
4312 | that operand, change the type. Similarly, change the operand number | |
4313 | of a reload when two operands match. If a reload is optional, treat it | |
4314 | as though the operand isn't reloaded. | |
4315 | ||
4316 | ??? This latter case is somewhat odd because if we do the optional | |
4317 | reload, it means the object is hanging around. Thus we need only | |
4318 | do the address reload if the optional reload was NOT done. | |
4319 | ||
4320 | Change secondary reloads to be the address type of their operand, not | |
4321 | the normal type. | |
4322 | ||
4323 | If an operand's reload is now RELOAD_OTHER, change any | |
4324 | RELOAD_FOR_INPUT_ADDRESS reloads of that operand to | |
4325 | RELOAD_FOR_OTHER_ADDRESS. */ | |
4326 | ||
4327 | for (i = 0; i < n_reloads; i++) | |
4328 | { | |
48666d2c | 4329 | if (rld[i].secondary_p |
83669f96 | 4330 | && rld[i].when_needed == operand_type[rld[i].opnum]) |
4331 | rld[i].when_needed = address_type[rld[i].opnum]; | |
48666d2c | 4332 | |
4333 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
4334 | || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS | |
4335 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS | |
4336 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4337 | && (operand_reloadnum[rld[i].opnum] < 0 | |
4338 | || rld[operand_reloadnum[rld[i].opnum]].optional)) | |
4d998c92 | 4339 | { |
4340 | /* If we have a secondary reload to go along with this reload, | |
a92771b8 | 4341 | change its type to RELOAD_FOR_OPADDR_ADDR. */ |
4d998c92 | 4342 | |
48666d2c | 4343 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS |
4344 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
4345 | && rld[i].secondary_in_reload != -1) | |
4d998c92 | 4346 | { |
48666d2c | 4347 | int secondary_in_reload = rld[i].secondary_in_reload; |
4d998c92 | 4348 | |
67610d42 | 4349 | rld[secondary_in_reload].when_needed = RELOAD_FOR_OPADDR_ADDR; |
4d998c92 | 4350 | |
a92771b8 | 4351 | /* If there's a tertiary reload we have to change it also. */ |
4d998c92 | 4352 | if (secondary_in_reload > 0 |
48666d2c | 4353 | && rld[secondary_in_reload].secondary_in_reload != -1) |
4354 | rld[rld[secondary_in_reload].secondary_in_reload].when_needed | |
83669f96 | 4355 | = RELOAD_FOR_OPADDR_ADDR; |
4d998c92 | 4356 | } |
4357 | ||
48666d2c | 4358 | if ((rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS |
4359 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4360 | && rld[i].secondary_out_reload != -1) | |
4d998c92 | 4361 | { |
48666d2c | 4362 | int secondary_out_reload = rld[i].secondary_out_reload; |
4d998c92 | 4363 | |
67610d42 | 4364 | rld[secondary_out_reload].when_needed = RELOAD_FOR_OPADDR_ADDR; |
4d998c92 | 4365 | |
a92771b8 | 4366 | /* If there's a tertiary reload we have to change it also. */ |
4d998c92 | 4367 | if (secondary_out_reload |
48666d2c | 4368 | && rld[secondary_out_reload].secondary_out_reload != -1) |
4369 | rld[rld[secondary_out_reload].secondary_out_reload].when_needed | |
83669f96 | 4370 | = RELOAD_FOR_OPADDR_ADDR; |
4d998c92 | 4371 | } |
997d68fe | 4372 | |
48666d2c | 4373 | if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS |
4374 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) | |
4375 | rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR; | |
93c7b06e | 4376 | else |
48666d2c | 4377 | rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS; |
4d998c92 | 4378 | } |
70457512 | 4379 | |
48666d2c | 4380 | if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS |
4381 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
4382 | && operand_reloadnum[rld[i].opnum] >= 0 | |
4383 | && (rld[operand_reloadnum[rld[i].opnum]].when_needed | |
70457512 | 4384 | == RELOAD_OTHER)) |
48666d2c | 4385 | rld[i].when_needed = RELOAD_FOR_OTHER_ADDRESS; |
70457512 | 4386 | |
48666d2c | 4387 | if (goal_alternative_matches[rld[i].opnum] >= 0) |
4388 | rld[i].opnum = goal_alternative_matches[rld[i].opnum]; | |
70457512 | 4389 | } |
4390 | ||
4429ee8b | 4391 | /* Scan all the reloads, and check for RELOAD_FOR_OPERAND_ADDRESS reloads. |
4392 | If we have more than one, then convert all RELOAD_FOR_OPADDR_ADDR | |
4393 | reloads to RELOAD_FOR_OPERAND_ADDRESS reloads. | |
4394 | ||
4395 | choose_reload_regs assumes that RELOAD_FOR_OPADDR_ADDR reloads never | |
4396 | conflict with RELOAD_FOR_OPERAND_ADDRESS reloads. This is true for a | |
4397 | single pair of RELOAD_FOR_OPADDR_ADDR/RELOAD_FOR_OPERAND_ADDRESS reloads. | |
4398 | However, if there is more than one RELOAD_FOR_OPERAND_ADDRESS reload, | |
4399 | then a RELOAD_FOR_OPADDR_ADDR reload conflicts with all | |
4400 | RELOAD_FOR_OPERAND_ADDRESS reloads other than the one that uses it. | |
4401 | This is complicated by the fact that a single operand can have more | |
4402 | than one RELOAD_FOR_OPERAND_ADDRESS reload. It is very difficult to fix | |
4403 | choose_reload_regs without affecting code quality, and cases that | |
4404 | actually fail are extremely rare, so it turns out to be better to fix | |
4405 | the problem here by not generating cases that choose_reload_regs will | |
4406 | fail for. */ | |
ab3d0862 | 4407 | /* There is a similar problem with RELOAD_FOR_INPUT_ADDRESS / |
45700efb | 4408 | RELOAD_FOR_OUTPUT_ADDRESS when there is more than one of a kind for |
4409 | a single operand. | |
4410 | We can reduce the register pressure by exploiting that a | |
4411 | RELOAD_FOR_X_ADDR_ADDR that precedes all RELOAD_FOR_X_ADDRESS reloads | |
d2eaccc2 | 4412 | does not conflict with any of them, if it is only used for the first of |
4413 | the RELOAD_FOR_X_ADDRESS reloads. */ | |
4429ee8b | 4414 | { |
45700efb | 4415 | int first_op_addr_num = -2; |
4416 | int first_inpaddr_num[MAX_RECOG_OPERANDS]; | |
4417 | int first_outpaddr_num[MAX_RECOG_OPERANDS]; | |
67610d42 | 4418 | int need_change = 0; |
45700efb | 4419 | /* We use last_op_addr_reload and the contents of the above arrays |
4420 | first as flags - -2 means no instance encountered, -1 means exactly | |
4421 | one instance encountered. | |
4422 | If more than one instance has been encountered, we store the reload | |
4423 | number of the first reload of the kind in question; reload numbers | |
4424 | are known to be non-negative. */ | |
4425 | for (i = 0; i < noperands; i++) | |
4426 | first_inpaddr_num[i] = first_outpaddr_num[i] = -2; | |
4427 | for (i = n_reloads - 1; i >= 0; i--) | |
4428 | { | |
48666d2c | 4429 | switch (rld[i].when_needed) |
45700efb | 4430 | { |
4431 | case RELOAD_FOR_OPERAND_ADDRESS: | |
d2eaccc2 | 4432 | if (++first_op_addr_num >= 0) |
45700efb | 4433 | { |
d2eaccc2 | 4434 | first_op_addr_num = i; |
45700efb | 4435 | need_change = 1; |
4436 | } | |
4437 | break; | |
4438 | case RELOAD_FOR_INPUT_ADDRESS: | |
48666d2c | 4439 | if (++first_inpaddr_num[rld[i].opnum] >= 0) |
45700efb | 4440 | { |
48666d2c | 4441 | first_inpaddr_num[rld[i].opnum] = i; |
45700efb | 4442 | need_change = 1; |
4443 | } | |
4444 | break; | |
4445 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
48666d2c | 4446 | if (++first_outpaddr_num[rld[i].opnum] >= 0) |
45700efb | 4447 | { |
48666d2c | 4448 | first_outpaddr_num[rld[i].opnum] = i; |
45700efb | 4449 | need_change = 1; |
4450 | } | |
4451 | break; | |
4452 | default: | |
4453 | break; | |
4454 | } | |
4455 | } | |
4429ee8b | 4456 | |
45700efb | 4457 | if (need_change) |
4458 | { | |
4459 | for (i = 0; i < n_reloads; i++) | |
4460 | { | |
29768226 | 4461 | int first_num; |
4462 | enum reload_type type; | |
45700efb | 4463 | |
48666d2c | 4464 | switch (rld[i].when_needed) |
45700efb | 4465 | { |
4466 | case RELOAD_FOR_OPADDR_ADDR: | |
4467 | first_num = first_op_addr_num; | |
4468 | type = RELOAD_FOR_OPERAND_ADDRESS; | |
4469 | break; | |
4470 | case RELOAD_FOR_INPADDR_ADDRESS: | |
48666d2c | 4471 | first_num = first_inpaddr_num[rld[i].opnum]; |
45700efb | 4472 | type = RELOAD_FOR_INPUT_ADDRESS; |
4473 | break; | |
4474 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
48666d2c | 4475 | first_num = first_outpaddr_num[rld[i].opnum]; |
45700efb | 4476 | type = RELOAD_FOR_OUTPUT_ADDRESS; |
4477 | break; | |
4478 | default: | |
4479 | continue; | |
4480 | } | |
d2eaccc2 | 4481 | if (first_num < 0) |
4482 | continue; | |
4483 | else if (i > first_num) | |
48666d2c | 4484 | rld[i].when_needed = type; |
d2eaccc2 | 4485 | else |
4486 | { | |
4487 | /* Check if the only TYPE reload that uses reload I is | |
4488 | reload FIRST_NUM. */ | |
4489 | for (j = n_reloads - 1; j > first_num; j--) | |
4490 | { | |
48666d2c | 4491 | if (rld[j].when_needed == type |
4492 | && (rld[i].secondary_p | |
4493 | ? rld[j].secondary_in_reload == i | |
4494 | : reg_mentioned_p (rld[i].in, rld[j].in))) | |
d2eaccc2 | 4495 | { |
48666d2c | 4496 | rld[i].when_needed = type; |
d2eaccc2 | 4497 | break; |
4498 | } | |
4499 | } | |
4500 | } | |
45700efb | 4501 | } |
4502 | } | |
4429ee8b | 4503 | } |
4504 | ||
70457512 | 4505 | /* See if we have any reloads that are now allowed to be merged |
4506 | because we've changed when the reload is needed to | |
4507 | RELOAD_FOR_OPERAND_ADDRESS or RELOAD_FOR_OTHER_ADDRESS. Only | |
4508 | check for the most common cases. */ | |
4509 | ||
4510 | for (i = 0; i < n_reloads; i++) | |
48666d2c | 4511 | if (rld[i].in != 0 && rld[i].out == 0 |
4512 | && (rld[i].when_needed == RELOAD_FOR_OPERAND_ADDRESS | |
4513 | || rld[i].when_needed == RELOAD_FOR_OPADDR_ADDR | |
4514 | || rld[i].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
70457512 | 4515 | for (j = 0; j < n_reloads; j++) |
48666d2c | 4516 | if (i != j && rld[j].in != 0 && rld[j].out == 0 |
4517 | && rld[j].when_needed == rld[i].when_needed | |
4518 | && MATCHES (rld[i].in, rld[j].in) | |
c32319fc | 4519 | && rld[i].rclass == rld[j].rclass |
48666d2c | 4520 | && !rld[i].nocombine && !rld[j].nocombine |
4521 | && rld[i].reg_rtx == rld[j].reg_rtx) | |
70457512 | 4522 | { |
48666d2c | 4523 | rld[i].opnum = MIN (rld[i].opnum, rld[j].opnum); |
70457512 | 4524 | transfer_replacements (i, j); |
48666d2c | 4525 | rld[j].in = 0; |
70457512 | 4526 | } |
4527 | ||
155b05dc | 4528 | #ifdef HAVE_cc0 |
4529 | /* If we made any reloads for addresses, see if they violate a | |
4530 | "no input reloads" requirement for this insn. But loads that we | |
4531 | do after the insn (such as for output addresses) are fine. */ | |
4532 | if (no_input_reloads) | |
4533 | for (i = 0; i < n_reloads; i++) | |
04e579b6 | 4534 | gcc_assert (rld[i].in == 0 |
4535 | || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS | |
4536 | || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS); | |
155b05dc | 4537 | #endif |
4538 | ||
456b6b44 | 4539 | /* Compute reload_mode and reload_nregs. */ |
4540 | for (i = 0; i < n_reloads; i++) | |
4541 | { | |
4542 | rld[i].mode | |
4543 | = (rld[i].inmode == VOIDmode | |
4544 | || (GET_MODE_SIZE (rld[i].outmode) | |
4545 | > GET_MODE_SIZE (rld[i].inmode))) | |
4546 | ? rld[i].outmode : rld[i].inmode; | |
4547 | ||
d3ba22dc | 4548 | rld[i].nregs = ira_reg_class_max_nregs [rld[i].rclass][rld[i].mode]; |
456b6b44 | 4549 | } |
4550 | ||
483fd82f | 4551 | /* Special case a simple move with an input reload and a |
4552 | destination of a hard reg, if the hard reg is ok, use it. */ | |
4553 | for (i = 0; i < n_reloads; i++) | |
4554 | if (rld[i].when_needed == RELOAD_FOR_INPUT | |
4555 | && GET_CODE (PATTERN (insn)) == SET | |
8ad4c111 | 4556 | && REG_P (SET_DEST (PATTERN (insn))) |
a5f1b756 | 4557 | && (SET_SRC (PATTERN (insn)) == rld[i].in |
4558 | || SET_SRC (PATTERN (insn)) == rld[i].in_reg) | |
eca883d1 | 4559 | && !elimination_target_reg_p (SET_DEST (PATTERN (insn)))) |
483fd82f | 4560 | { |
3ad4992f | 4561 | rtx dest = SET_DEST (PATTERN (insn)); |
483fd82f | 4562 | unsigned int regno = REGNO (dest); |
4563 | ||
3ad4992f | 4564 | if (regno < FIRST_PSEUDO_REGISTER |
c32319fc | 4565 | && TEST_HARD_REG_BIT (reg_class_contents[rld[i].rclass], regno) |
3ad4992f | 4566 | && HARD_REGNO_MODE_OK (regno, rld[i].mode)) |
7497bc17 | 4567 | { |
67d6c12b | 4568 | int nr = hard_regno_nregs[regno][rld[i].mode]; |
7497bc17 | 4569 | int ok = 1, nri; |
4570 | ||
4571 | for (nri = 1; nri < nr; nri ++) | |
c32319fc | 4572 | if (! TEST_HARD_REG_BIT (reg_class_contents[rld[i].rclass], regno + nri)) |
7497bc17 | 4573 | ok = 0; |
4574 | ||
4575 | if (ok) | |
4576 | rld[i].reg_rtx = dest; | |
4577 | } | |
483fd82f | 4578 | } |
4579 | ||
93c7b06e | 4580 | return retval; |
42c63e4d | 4581 | } |
4582 | ||
53716799 | 4583 | /* Return true if alternative number ALTNUM in constraint-string |
4584 | CONSTRAINT is guaranteed to accept a reloaded constant-pool reference. | |
4585 | MEM gives the reference if it didn't need any reloads, otherwise it | |
4586 | is null. */ | |
42c63e4d | 4587 | |
53716799 | 4588 | static bool |
6577bf6b | 4589 | alternative_allows_const_pool_ref (rtx mem ATTRIBUTE_UNUSED, |
4590 | const char *constraint, int altnum) | |
42c63e4d | 4591 | { |
19cb6b50 | 4592 | int c; |
53716799 | 4593 | |
42c63e4d | 4594 | /* Skip alternatives before the one requested. */ |
4595 | while (altnum > 0) | |
4596 | { | |
3c802a1e | 4597 | while (*constraint++ != ',') |
4598 | ; | |
42c63e4d | 4599 | altnum--; |
4600 | } | |
e9ff93b1 | 4601 | /* Scan the requested alternative for TARGET_MEM_CONSTRAINT or 'o'. |
53716799 | 4602 | If one of them is present, this alternative accepts the result of |
4603 | passing a constant-pool reference through find_reloads_toplev. | |
4604 | ||
4605 | The same is true of extra memory constraints if the address | |
4606 | was reloaded into a register. However, the target may elect | |
4607 | to disallow the original constant address, forcing it to be | |
4608 | reloaded into a register instead. */ | |
48ea5577 | 4609 | for (; (c = *constraint) && c != ',' && c != '#'; |
4610 | constraint += CONSTRAINT_LEN (c, constraint)) | |
53716799 | 4611 | { |
e9ff93b1 | 4612 | if (c == TARGET_MEM_CONSTRAINT || c == 'o') |
53716799 | 4613 | return true; |
4614 | #ifdef EXTRA_CONSTRAINT_STR | |
4615 | if (EXTRA_MEMORY_CONSTRAINT (c, constraint) | |
4616 | && (mem == NULL || EXTRA_CONSTRAINT_STR (mem, c, constraint))) | |
4617 | return true; | |
4618 | #endif | |
4619 | } | |
4620 | return false; | |
42c63e4d | 4621 | } |
4622 | \f | |
4623 | /* Scan X for memory references and scan the addresses for reloading. | |
4624 | Also checks for references to "constant" regs that we want to eliminate | |
4625 | and replaces them with the values they stand for. | |
4bbea254 | 4626 | We may alter X destructively if it contains a reference to such. |
42c63e4d | 4627 | If X is just a constant reg, we return the equivalent value |
4628 | instead of X. | |
4629 | ||
4630 | IND_LEVELS says how many levels of indirect addressing this machine | |
4631 | supports. | |
4632 | ||
70457512 | 4633 | OPNUM and TYPE identify the purpose of the reload. |
4634 | ||
42c63e4d | 4635 | IS_SET_DEST is true if X is the destination of a SET, which is not |
93c7b06e | 4636 | appropriate to be replaced by a constant. |
4637 | ||
4638 | INSN, if nonzero, is the insn in which we do the reload. It is used | |
4639 | to determine if we may generate output reloads, and where to put USEs | |
1aa90c62 | 4640 | for pseudos that we have to replace with stack slots. |
4641 | ||
4642 | ADDRESS_RELOADED. If nonzero, is a pointer to where we put the | |
4643 | result of find_reloads_address. */ | |
42c63e4d | 4644 | |
4645 | static rtx | |
3ad4992f | 4646 | find_reloads_toplev (rtx x, int opnum, enum reload_type type, |
4647 | int ind_levels, int is_set_dest, rtx insn, | |
4648 | int *address_reloaded) | |
42c63e4d | 4649 | { |
19cb6b50 | 4650 | RTX_CODE code = GET_CODE (x); |
42c63e4d | 4651 | |
19cb6b50 | 4652 | const char *fmt = GET_RTX_FORMAT (code); |
4653 | int i; | |
a60f4869 | 4654 | int copied; |
42c63e4d | 4655 | |
4656 | if (code == REG) | |
4657 | { | |
4658 | /* This code is duplicated for speed in find_reloads. */ | |
19cb6b50 | 4659 | int regno = REGNO (x); |
1c654ff1 | 4660 | if (reg_equiv_constant (regno) != 0 && !is_set_dest) |
4661 | x = reg_equiv_constant (regno); | |
42c63e4d | 4662 | #if 0 |
5bb2f919 | 4663 | /* This creates (subreg (mem...)) which would cause an unnecessary |
4664 | reload of the mem. */ | |
1c654ff1 | 4665 | else if (reg_equiv_mem (regno) != 0) |
4666 | x = reg_equiv_mem (regno); | |
42c63e4d | 4667 | #endif |
1c654ff1 | 4668 | else if (reg_equiv_memory_loc (regno) |
4669 | && (reg_equiv_address (regno) != 0 || num_not_at_initial_offset)) | |
42c63e4d | 4670 | { |
93c7b06e | 4671 | rtx mem = make_memloc (x, regno); |
1c654ff1 | 4672 | if (reg_equiv_address (regno) |
4673 | || ! rtx_equal_p (mem, reg_equiv_mem (regno))) | |
93c7b06e | 4674 | { |
4675 | /* If this is not a toplevel operand, find_reloads doesn't see | |
4676 | this substitution. We have to emit a USE of the pseudo so | |
4677 | that delete_output_reload can see it. */ | |
ed420a25 | 4678 | if (replace_reloads && recog_data.operand[opnum] != x) |
b2920130 | 4679 | /* We mark the USE with QImode so that we recognize it |
4680 | as one that can be safely deleted at the end of | |
4681 | reload. */ | |
4682 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, x), insn), | |
4683 | QImode); | |
93c7b06e | 4684 | x = mem; |
1aa90c62 | 4685 | i = find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), &XEXP (x, 0), |
4686 | opnum, type, ind_levels, insn); | |
c89e828f | 4687 | if (!rtx_equal_p (x, mem)) |
d51b37c2 | 4688 | push_reg_equiv_alt_mem (regno, x); |
1aa90c62 | 4689 | if (address_reloaded) |
4690 | *address_reloaded = i; | |
93c7b06e | 4691 | } |
42c63e4d | 4692 | } |
4693 | return x; | |
4694 | } | |
4695 | if (code == MEM) | |
4696 | { | |
4697 | rtx tem = x; | |
1aa90c62 | 4698 | |
4699 | i = find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0), | |
4700 | opnum, type, ind_levels, insn); | |
4701 | if (address_reloaded) | |
4702 | *address_reloaded = i; | |
4703 | ||
42c63e4d | 4704 | return tem; |
4705 | } | |
4706 | ||
8ad4c111 | 4707 | if (code == SUBREG && REG_P (SUBREG_REG (x))) |
42c63e4d | 4708 | { |
1fa3a8f6 | 4709 | /* Check for SUBREG containing a REG that's equivalent to a |
4710 | constant. If the constant has a known value, truncate it | |
4711 | right now. Similarly if we are extracting a single-word of a | |
4712 | multi-word constant. If the constant is symbolic, allow it | |
4713 | to be substituted normally. push_reload will strip the | |
4714 | subreg later. The constant must not be VOIDmode, because we | |
4715 | will lose the mode of the register (this should never happen | |
4716 | because one of the cases above should handle it). */ | |
42c63e4d | 4717 | |
19cb6b50 | 4718 | int regno = REGNO (SUBREG_REG (x)); |
42c63e4d | 4719 | rtx tem; |
4720 | ||
9f1a815a | 4721 | if (regno >= FIRST_PSEUDO_REGISTER |
4722 | && reg_renumber[regno] < 0 | |
1c654ff1 | 4723 | && reg_equiv_constant (regno) != 0) |
c16f995d | 4724 | { |
c736a837 | 4725 | tem = |
1c654ff1 | 4726 | simplify_gen_subreg (GET_MODE (x), reg_equiv_constant (regno), |
c736a837 | 4727 | GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); |
04e579b6 | 4728 | gcc_assert (tem); |
ca316360 | 4729 | if (CONSTANT_P (tem) |
4730 | && !targetm.legitimate_constant_p (GET_MODE (x), tem)) | |
8a72adf4 | 4731 | { |
4732 | tem = force_const_mem (GET_MODE (x), tem); | |
4733 | i = find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), | |
4734 | &XEXP (tem, 0), opnum, type, | |
4735 | ind_levels, insn); | |
4736 | if (address_reloaded) | |
4737 | *address_reloaded = i; | |
4738 | } | |
622e3537 | 4739 | return tem; |
c16f995d | 4740 | } |
42c63e4d | 4741 | |
42c63e4d | 4742 | /* If the subreg contains a reg that will be converted to a mem, |
4743 | convert the subreg to a narrower memref now. | |
4744 | Otherwise, we would get (subreg (mem ...) ...), | |
4745 | which would force reload of the mem. | |
4746 | ||
4747 | We also need to do this if there is an equivalent MEM that is | |
4748 | not offsettable. In that case, alter_subreg would produce an | |
4749 | invalid address on big-endian machines. | |
4750 | ||
9d435639 | 4751 | For machines that extend byte loads, we must not reload using |
42c63e4d | 4752 | a wider mode if we have a paradoxical SUBREG. find_reloads will |
4753 | force a reload in that case. So we should not do anything here. */ | |
4754 | ||
9f1a815a | 4755 | if (regno >= FIRST_PSEUDO_REGISTER |
41619c31 | 4756 | #ifdef LOAD_EXTEND_OP |
b537bfdb | 4757 | && !paradoxical_subreg_p (x) |
42c63e4d | 4758 | #endif |
b537bfdb | 4759 | && (reg_equiv_address (regno) != 0 |
4760 | || (reg_equiv_mem (regno) != 0 | |
4761 | && (! strict_memory_address_addr_space_p | |
4762 | (GET_MODE (x), XEXP (reg_equiv_mem (regno), 0), | |
4763 | MEM_ADDR_SPACE (reg_equiv_mem (regno))) | |
4764 | || ! offsettable_memref_p (reg_equiv_mem (regno)) | |
4765 | || num_not_at_initial_offset)))) | |
37f7956e | 4766 | x = find_reloads_subreg_address (x, 1, opnum, type, ind_levels, |
b5fe590a | 4767 | insn, address_reloaded); |
42c63e4d | 4768 | } |
4769 | ||
a60f4869 | 4770 | for (copied = 0, i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
42c63e4d | 4771 | { |
4772 | if (fmt[i] == 'e') | |
a60f4869 | 4773 | { |
4774 | rtx new_part = find_reloads_toplev (XEXP (x, i), opnum, type, | |
1aa90c62 | 4775 | ind_levels, is_set_dest, insn, |
4776 | address_reloaded); | |
a60f4869 | 4777 | /* If we have replaced a reg with it's equivalent memory loc - |
4778 | that can still be handled here e.g. if it's in a paradoxical | |
4779 | subreg - we must make the change in a copy, rather than using | |
4780 | a destructive change. This way, find_reloads can still elect | |
4781 | not to do the change. */ | |
4782 | if (new_part != XEXP (x, i) && ! CONSTANT_P (new_part) && ! copied) | |
4783 | { | |
57ff0c05 | 4784 | x = shallow_copy_rtx (x); |
a60f4869 | 4785 | copied = 1; |
4786 | } | |
4787 | XEXP (x, i) = new_part; | |
4788 | } | |
42c63e4d | 4789 | } |
4790 | return x; | |
4791 | } | |
4792 | ||
b763f6ee | 4793 | /* Return a mem ref for the memory equivalent of reg REGNO. |
4794 | This mem ref is not shared with anything. */ | |
4795 | ||
42c63e4d | 4796 | static rtx |
3ad4992f | 4797 | make_memloc (rtx ad, int regno) |
42c63e4d | 4798 | { |
d4a46c88 | 4799 | /* We must rerun eliminate_regs, in case the elimination |
4800 | offsets have changed. */ | |
93c7b06e | 4801 | rtx tem |
1c654ff1 | 4802 | = XEXP (eliminate_regs (reg_equiv_memory_loc (regno), VOIDmode, NULL_RTX), |
b9c74b4d | 4803 | 0); |
42c63e4d | 4804 | |
4805 | /* If TEM might contain a pseudo, we must copy it to avoid | |
4806 | modifying it when we do the substitution for the reload. */ | |
ea087693 | 4807 | if (rtx_varies_p (tem, 0)) |
42c63e4d | 4808 | tem = copy_rtx (tem); |
4809 | ||
1c654ff1 | 4810 | tem = replace_equiv_address_nv (reg_equiv_memory_loc (regno), tem); |
f6ada591 | 4811 | tem = adjust_address_nv (tem, GET_MODE (ad), 0); |
4812 | ||
4813 | /* Copy the result if it's still the same as the equivalence, to avoid | |
4814 | modifying it when we do the substitution for the reload. */ | |
1c654ff1 | 4815 | if (tem == reg_equiv_memory_loc (regno)) |
f6ada591 | 4816 | tem = copy_rtx (tem); |
4817 | return tem; | |
42c63e4d | 4818 | } |
4819 | ||
b51061d4 | 4820 | /* Returns true if AD could be turned into a valid memory reference |
bd1a81f7 | 4821 | to mode MODE in address space AS by reloading the part pointed to |
4822 | by PART into a register. */ | |
b51061d4 | 4823 | |
4824 | static int | |
bd1a81f7 | 4825 | maybe_memory_address_addr_space_p (enum machine_mode mode, rtx ad, |
4826 | addr_space_t as, rtx *part) | |
b51061d4 | 4827 | { |
4828 | int retv; | |
4829 | rtx tem = *part; | |
4830 | rtx reg = gen_rtx_REG (GET_MODE (tem), max_reg_num ()); | |
4831 | ||
4832 | *part = reg; | |
bd1a81f7 | 4833 | retv = memory_address_addr_space_p (mode, ad, as); |
b51061d4 | 4834 | *part = tem; |
4835 | ||
4836 | return retv; | |
4837 | } | |
4838 | ||
42c63e4d | 4839 | /* Record all reloads needed for handling memory address AD |
4840 | which appears in *LOC in a memory reference to mode MODE | |
4841 | which itself is found in location *MEMREFLOC. | |
4842 | Note that we take shortcuts assuming that no multi-reg machine mode | |
4843 | occurs as part of an address. | |
4844 | ||
70457512 | 4845 | OPNUM and TYPE specify the purpose of this reload. |
42c63e4d | 4846 | |
4847 | IND_LEVELS says how many levels of indirect addressing this machine | |
4848 | supports. | |
4849 | ||
d59f2d23 | 4850 | INSN, if nonzero, is the insn in which we do the reload. It is used |
93c7b06e | 4851 | to determine if we may generate output reloads, and where to put USEs |
4852 | for pseudos that we have to replace with stack slots. | |
d59f2d23 | 4853 | |
e4542435 | 4854 | Value is one if this address is reloaded or replaced as a whole; it is |
4855 | zero if the top level of this address was not reloaded or replaced, and | |
4856 | it is -1 if it may or may not have been reloaded or replaced. | |
42c63e4d | 4857 | |
4858 | Note that there is no verification that the address will be valid after | |
4859 | this routine does its work. Instead, we rely on the fact that the address | |
4860 | was valid when reload started. So we need only undo things that reload | |
4861 | could have broken. These are wrong register types, pseudos not allocated | |
4862 | to a hard register, and frame pointer elimination. */ | |
4863 | ||
4864 | static int | |
3ad4992f | 4865 | find_reloads_address (enum machine_mode mode, rtx *memrefloc, rtx ad, |
4866 | rtx *loc, int opnum, enum reload_type type, | |
4867 | int ind_levels, rtx insn) | |
42c63e4d | 4868 | { |
bd1a81f7 | 4869 | addr_space_t as = memrefloc? MEM_ADDR_SPACE (*memrefloc) |
4870 | : ADDR_SPACE_GENERIC; | |
19cb6b50 | 4871 | int regno; |
be2828ce | 4872 | int removed_and = 0; |
f25bee5a | 4873 | int op_index; |
42c63e4d | 4874 | rtx tem; |
4875 | ||
4876 | /* If the address is a register, see if it is a legitimate address and | |
4877 | reload if not. We first handle the cases where we need not reload | |
4878 | or where we must reload in a non-standard way. */ | |
4879 | ||
8ad4c111 | 4880 | if (REG_P (ad)) |
42c63e4d | 4881 | { |
4882 | regno = REGNO (ad); | |
4883 | ||
1c654ff1 | 4884 | if (reg_equiv_constant (regno) != 0) |
42c63e4d | 4885 | { |
1c654ff1 | 4886 | find_reloads_address_part (reg_equiv_constant (regno), loc, |
f8a8fc7b | 4887 | base_reg_class (mode, as, MEM, SCRATCH), |
cd6659e3 | 4888 | GET_MODE (ad), opnum, type, ind_levels); |
4889 | return 1; | |
42c63e4d | 4890 | } |
4891 | ||
1c654ff1 | 4892 | tem = reg_equiv_memory_loc (regno); |
93c7b06e | 4893 | if (tem != 0) |
42c63e4d | 4894 | { |
1c654ff1 | 4895 | if (reg_equiv_address (regno) != 0 || num_not_at_initial_offset) |
93c7b06e | 4896 | { |
4897 | tem = make_memloc (ad, regno); | |
bd1a81f7 | 4898 | if (! strict_memory_address_addr_space_p (GET_MODE (tem), |
4899 | XEXP (tem, 0), | |
4900 | MEM_ADDR_SPACE (tem))) | |
93c7b06e | 4901 | { |
d51b37c2 | 4902 | rtx orig = tem; |
4903 | ||
e9bf6953 | 4904 | find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), |
4905 | &XEXP (tem, 0), opnum, | |
4906 | ADDR_TYPE (type), ind_levels, insn); | |
c89e828f | 4907 | if (!rtx_equal_p (tem, orig)) |
d51b37c2 | 4908 | push_reg_equiv_alt_mem (regno, tem); |
93c7b06e | 4909 | } |
4910 | /* We can avoid a reload if the register's equivalent memory | |
4911 | expression is valid as an indirect memory address. | |
4912 | But not all addresses are valid in a mem used as an indirect | |
4913 | address: only reg or reg+constant. */ | |
4914 | ||
4915 | if (ind_levels > 0 | |
bd1a81f7 | 4916 | && strict_memory_address_addr_space_p (mode, tem, as) |
8ad4c111 | 4917 | && (REG_P (XEXP (tem, 0)) |
93c7b06e | 4918 | || (GET_CODE (XEXP (tem, 0)) == PLUS |
8ad4c111 | 4919 | && REG_P (XEXP (XEXP (tem, 0), 0)) |
93c7b06e | 4920 | && CONSTANT_P (XEXP (XEXP (tem, 0), 1))))) |
4921 | { | |
4922 | /* TEM is not the same as what we'll be replacing the | |
4923 | pseudo with after reload, put a USE in front of INSN | |
4924 | in the final reload pass. */ | |
4925 | if (replace_reloads | |
4926 | && num_not_at_initial_offset | |
1c654ff1 | 4927 | && ! rtx_equal_p (tem, reg_equiv_mem (regno))) |
93c7b06e | 4928 | { |
4929 | *loc = tem; | |
b2920130 | 4930 | /* We mark the USE with QImode so that we |
4931 | recognize it as one that can be safely | |
4932 | deleted at the end of reload. */ | |
4933 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, ad), | |
4934 | insn), QImode); | |
4935 | ||
93c7b06e | 4936 | /* This doesn't really count as replacing the address |
4937 | as a whole, since it is still a memory access. */ | |
4938 | } | |
4939 | return 0; | |
4940 | } | |
4941 | ad = tem; | |
4942 | } | |
42c63e4d | 4943 | } |
4944 | ||
42c63e4d | 4945 | /* The only remaining case where we can avoid a reload is if this is a |
4946 | hard register that is valid as a base register and which is not the | |
4947 | subject of a CLOBBER in this insn. */ | |
4948 | ||
7166ebd0 | 4949 | else if (regno < FIRST_PSEUDO_REGISTER |
f8a8fc7b | 4950 | && regno_ok_for_base_p (regno, mode, as, MEM, SCRATCH) |
ab7883ae | 4951 | && ! regno_clobbered_p (regno, this_insn, mode, 0)) |
42c63e4d | 4952 | return 0; |
4953 | ||
4954 | /* If we do not have one of the cases above, we must do the reload. */ | |
f8a8fc7b | 4955 | push_reload (ad, NULL_RTX, loc, (rtx*) 0, |
4956 | base_reg_class (mode, as, MEM, SCRATCH), | |
70457512 | 4957 | GET_MODE (ad), VOIDmode, 0, 0, opnum, type); |
42c63e4d | 4958 | return 1; |
4959 | } | |
4960 | ||
bd1a81f7 | 4961 | if (strict_memory_address_addr_space_p (mode, ad, as)) |
42c63e4d | 4962 | { |
4963 | /* The address appears valid, so reloads are not needed. | |
4964 | But the address may contain an eliminable register. | |
4965 | This can happen because a machine with indirect addressing | |
4966 | may consider a pseudo register by itself a valid address even when | |
4967 | it has failed to get a hard reg. | |
4968 | So do a tree-walk to find and eliminate all such regs. */ | |
4969 | ||
4970 | /* But first quickly dispose of a common case. */ | |
4971 | if (GET_CODE (ad) == PLUS | |
971ba038 | 4972 | && CONST_INT_P (XEXP (ad, 1)) |
8ad4c111 | 4973 | && REG_P (XEXP (ad, 0)) |
1c654ff1 | 4974 | && reg_equiv_constant (REGNO (XEXP (ad, 0))) == 0) |
42c63e4d | 4975 | return 0; |
4976 | ||
4977 | subst_reg_equivs_changed = 0; | |
93c7b06e | 4978 | *loc = subst_reg_equivs (ad, insn); |
42c63e4d | 4979 | |
4980 | if (! subst_reg_equivs_changed) | |
4981 | return 0; | |
4982 | ||
4983 | /* Check result for validity after substitution. */ | |
bd1a81f7 | 4984 | if (strict_memory_address_addr_space_p (mode, ad, as)) |
42c63e4d | 4985 | return 0; |
4986 | } | |
4987 | ||
f64bc32a | 4988 | #ifdef LEGITIMIZE_RELOAD_ADDRESS |
4989 | do | |
4990 | { | |
bd1a81f7 | 4991 | if (memrefloc && ADDR_SPACE_GENERIC_P (as)) |
f64bc32a | 4992 | { |
4993 | LEGITIMIZE_RELOAD_ADDRESS (ad, GET_MODE (*memrefloc), opnum, type, | |
4994 | ind_levels, win); | |
4995 | } | |
4996 | break; | |
4997 | win: | |
4998 | *memrefloc = copy_rtx (*memrefloc); | |
4999 | XEXP (*memrefloc, 0) = ad; | |
5000 | move_replacements (&ad, &XEXP (*memrefloc, 0)); | |
e4542435 | 5001 | return -1; |
f64bc32a | 5002 | } |
5003 | while (0); | |
5004 | #endif | |
5005 | ||
be2828ce | 5006 | /* The address is not valid. We have to figure out why. First see if |
5007 | we have an outer AND and remove it if so. Then analyze what's inside. */ | |
5008 | ||
5009 | if (GET_CODE (ad) == AND) | |
5010 | { | |
5011 | removed_and = 1; | |
5012 | loc = &XEXP (ad, 0); | |
5013 | ad = *loc; | |
5014 | } | |
5015 | ||
5016 | /* One possibility for why the address is invalid is that it is itself | |
5017 | a MEM. This can happen when the frame pointer is being eliminated, a | |
5018 | pseudo is not allocated to a hard register, and the offset between the | |
5019 | frame and stack pointers is not its initial value. In that case the | |
5020 | pseudo will have been replaced by a MEM referring to the | |
5021 | stack pointer. */ | |
e16ceb8e | 5022 | if (MEM_P (ad)) |
42c63e4d | 5023 | { |
5024 | /* First ensure that the address in this MEM is valid. Then, unless | |
5025 | indirect addresses are valid, reload the MEM into a register. */ | |
5026 | tem = ad; | |
5027 | find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0), | |
9e53d777 | 5028 | opnum, ADDR_TYPE (type), |
d59f2d23 | 5029 | ind_levels == 0 ? 0 : ind_levels - 1, insn); |
e6d2ff12 | 5030 | |
5031 | /* If tem was changed, then we must create a new memory reference to | |
5032 | hold it and store it back into memrefloc. */ | |
5033 | if (tem != ad && memrefloc) | |
6949ad11 | 5034 | { |
6949ad11 | 5035 | *memrefloc = copy_rtx (*memrefloc); |
05c8c31e | 5036 | copy_replacements (tem, XEXP (*memrefloc, 0)); |
6949ad11 | 5037 | loc = &XEXP (*memrefloc, 0); |
be2828ce | 5038 | if (removed_and) |
5039 | loc = &XEXP (*loc, 0); | |
6949ad11 | 5040 | } |
e6d2ff12 | 5041 | |
42c63e4d | 5042 | /* Check similar cases as for indirect addresses as above except |
5043 | that we can allow pseudos and a MEM since they should have been | |
5044 | taken care of above. */ | |
5045 | ||
5046 | if (ind_levels == 0 | |
5047 | || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok) | |
e16ceb8e | 5048 | || MEM_P (XEXP (tem, 0)) |
8ad4c111 | 5049 | || ! (REG_P (XEXP (tem, 0)) |
42c63e4d | 5050 | || (GET_CODE (XEXP (tem, 0)) == PLUS |
8ad4c111 | 5051 | && REG_P (XEXP (XEXP (tem, 0), 0)) |
971ba038 | 5052 | && CONST_INT_P (XEXP (XEXP (tem, 0), 1))))) |
42c63e4d | 5053 | { |
5054 | /* Must use TEM here, not AD, since it is the one that will | |
5055 | have any subexpressions reloaded, if needed. */ | |
33181afc | 5056 | push_reload (tem, NULL_RTX, loc, (rtx*) 0, |
f8a8fc7b | 5057 | base_reg_class (mode, as, MEM, SCRATCH), GET_MODE (tem), |
494ebe4d | 5058 | VOIDmode, 0, |
70457512 | 5059 | 0, opnum, type); |
be2828ce | 5060 | return ! removed_and; |
42c63e4d | 5061 | } |
5062 | else | |
5063 | return 0; | |
5064 | } | |
5065 | ||
d9891733 | 5066 | /* If we have address of a stack slot but it's not valid because the |
5067 | displacement is too large, compute the sum in a register. | |
5068 | Handle all base registers here, not just fp/ap/sp, because on some | |
5069 | targets (namely SH) we can also get too large displacements from | |
5070 | big-endian corrections. */ | |
42c63e4d | 5071 | else if (GET_CODE (ad) == PLUS |
8ad4c111 | 5072 | && REG_P (XEXP (ad, 0)) |
d9891733 | 5073 | && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER |
971ba038 | 5074 | && CONST_INT_P (XEXP (ad, 1)) |
f8a8fc7b | 5075 | && (regno_ok_for_base_p (REGNO (XEXP (ad, 0)), mode, as, PLUS, |
8e4f36fa | 5076 | CONST_INT) |
5077 | /* Similarly, if we were to reload the base register and the | |
5078 | mem+offset address is still invalid, then we want to reload | |
5079 | the whole address, not just the base register. */ | |
5080 | || ! maybe_memory_address_addr_space_p | |
5081 | (mode, ad, as, &(XEXP (ad, 0))))) | |
00cb30dc | 5082 | |
42c63e4d | 5083 | { |
5084 | /* Unshare the MEM rtx so we can safely alter it. */ | |
5085 | if (memrefloc) | |
5086 | { | |
42c63e4d | 5087 | *memrefloc = copy_rtx (*memrefloc); |
5088 | loc = &XEXP (*memrefloc, 0); | |
be2828ce | 5089 | if (removed_and) |
5090 | loc = &XEXP (*loc, 0); | |
42c63e4d | 5091 | } |
be2828ce | 5092 | |
8e4f36fa | 5093 | if (double_reg_address_ok |
f8a8fc7b | 5094 | && regno_ok_for_base_p (REGNO (XEXP (ad, 0)), mode, as, |
8e4f36fa | 5095 | PLUS, CONST_INT)) |
42c63e4d | 5096 | { |
5097 | /* Unshare the sum as well. */ | |
5098 | *loc = ad = copy_rtx (ad); | |
be2828ce | 5099 | |
42c63e4d | 5100 | /* Reload the displacement into an index reg. |
5101 | We assume the frame pointer or arg pointer is a base reg. */ | |
5102 | find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), | |
dab171c5 | 5103 | INDEX_REG_CLASS, GET_MODE (ad), opnum, |
5104 | type, ind_levels); | |
be2828ce | 5105 | return 0; |
42c63e4d | 5106 | } |
5107 | else | |
5108 | { | |
5109 | /* If the sum of two regs is not necessarily valid, | |
5110 | reload the sum into a base reg. | |
5111 | That will at least work. */ | |
00cb30dc | 5112 | find_reloads_address_part (ad, loc, |
f8a8fc7b | 5113 | base_reg_class (mode, as, MEM, SCRATCH), |
98155838 | 5114 | GET_MODE (ad), opnum, type, ind_levels); |
42c63e4d | 5115 | } |
be2828ce | 5116 | return ! removed_and; |
42c63e4d | 5117 | } |
5118 | ||
5119 | /* If we have an indexed stack slot, there are three possible reasons why | |
5120 | it might be invalid: The index might need to be reloaded, the address | |
5121 | might have been made by frame pointer elimination and hence have a | |
5bb2f919 | 5122 | constant out of range, or both reasons might apply. |
42c63e4d | 5123 | |
5124 | We can easily check for an index needing reload, but even if that is the | |
5125 | case, we might also have an invalid constant. To avoid making the | |
5126 | conservative assumption and requiring two reloads, we see if this address | |
5127 | is valid when not interpreted strictly. If it is, the only problem is | |
5128 | that the index needs a reload and find_reloads_address_1 will take care | |
5129 | of it. | |
5130 | ||
ab2a6bdb | 5131 | Handle all base registers here, not just fp/ap/sp, because on some |
7ef5b942 | 5132 | targets (namely SPARC) we can also get invalid addresses from preventive |
f25bee5a | 5133 | subreg big-endian corrections made by find_reloads_toplev. We |
5134 | can also get expressions involving LO_SUM (rather than PLUS) from | |
5135 | find_reloads_subreg_address. | |
ab2a6bdb | 5136 | |
5137 | If we decide to do something, it must be that `double_reg_address_ok' | |
5138 | is true. We generate a reload of the base register + constant and | |
42c63e4d | 5139 | rework the sum so that the reload register will be added to the index. |
5140 | This is safe because we know the address isn't shared. | |
5141 | ||
ab2a6bdb | 5142 | We check for the base register as both the first and second operand of |
f25bee5a | 5143 | the innermost PLUS and/or LO_SUM. */ |
5144 | ||
5145 | for (op_index = 0; op_index < 2; ++op_index) | |
42c63e4d | 5146 | { |
00cb30dc | 5147 | rtx operand, addend; |
5148 | enum rtx_code inner_code; | |
5149 | ||
5150 | if (GET_CODE (ad) != PLUS) | |
5151 | continue; | |
42c63e4d | 5152 | |
00cb30dc | 5153 | inner_code = GET_CODE (XEXP (ad, 0)); |
48e1416a | 5154 | if (!(GET_CODE (ad) == PLUS |
971ba038 | 5155 | && CONST_INT_P (XEXP (ad, 1)) |
00cb30dc | 5156 | && (inner_code == PLUS || inner_code == LO_SUM))) |
f25bee5a | 5157 | continue; |
5bb2f919 | 5158 | |
f25bee5a | 5159 | operand = XEXP (XEXP (ad, 0), op_index); |
ee90634d | 5160 | if (!REG_P (operand) || REGNO (operand) >= FIRST_PSEUDO_REGISTER) |
f25bee5a | 5161 | continue; |
5162 | ||
00cb30dc | 5163 | addend = XEXP (XEXP (ad, 0), 1 - op_index); |
5164 | ||
f8a8fc7b | 5165 | if ((regno_ok_for_base_p (REGNO (operand), mode, as, inner_code, |
00cb30dc | 5166 | GET_CODE (addend)) |
f25bee5a | 5167 | || operand == frame_pointer_rtx |
5ae82d58 | 5168 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER |
f25bee5a | 5169 | || operand == hard_frame_pointer_rtx |
2843e223 | 5170 | #endif |
5171 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
f25bee5a | 5172 | || operand == arg_pointer_rtx |
2843e223 | 5173 | #endif |
f25bee5a | 5174 | || operand == stack_pointer_rtx) |
bd1a81f7 | 5175 | && ! maybe_memory_address_addr_space_p |
5176 | (mode, ad, as, &XEXP (XEXP (ad, 0), 1 - op_index))) | |
f25bee5a | 5177 | { |
5178 | rtx offset_reg; | |
00cb30dc | 5179 | enum reg_class cls; |
f25bee5a | 5180 | |
5181 | offset_reg = plus_constant (operand, INTVAL (XEXP (ad, 1))); | |
00cb30dc | 5182 | |
f25bee5a | 5183 | /* Form the adjusted address. */ |
5184 | if (GET_CODE (XEXP (ad, 0)) == PLUS) | |
48e1416a | 5185 | ad = gen_rtx_PLUS (GET_MODE (ad), |
5186 | op_index == 0 ? offset_reg : addend, | |
f25bee5a | 5187 | op_index == 0 ? addend : offset_reg); |
5188 | else | |
48e1416a | 5189 | ad = gen_rtx_LO_SUM (GET_MODE (ad), |
5190 | op_index == 0 ? offset_reg : addend, | |
f25bee5a | 5191 | op_index == 0 ? addend : offset_reg); |
5192 | *loc = ad; | |
5193 | ||
f8a8fc7b | 5194 | cls = base_reg_class (mode, as, MEM, GET_CODE (addend)); |
48e1416a | 5195 | find_reloads_address_part (XEXP (ad, op_index), |
00cb30dc | 5196 | &XEXP (ad, op_index), cls, |
f25bee5a | 5197 | GET_MODE (ad), opnum, type, ind_levels); |
f8a8fc7b | 5198 | find_reloads_address_1 (mode, as, |
00cb30dc | 5199 | XEXP (ad, 1 - op_index), 1, GET_CODE (ad), |
5200 | GET_CODE (XEXP (ad, op_index)), | |
f25bee5a | 5201 | &XEXP (ad, 1 - op_index), opnum, |
5202 | type, 0, insn); | |
42c63e4d | 5203 | |
f25bee5a | 5204 | return 0; |
5205 | } | |
42c63e4d | 5206 | } |
5bb2f919 | 5207 | |
42c63e4d | 5208 | /* See if address becomes valid when an eliminable register |
5209 | in a sum is replaced. */ | |
5210 | ||
5211 | tem = ad; | |
5212 | if (GET_CODE (ad) == PLUS) | |
5213 | tem = subst_indexed_address (ad); | |
bd1a81f7 | 5214 | if (tem != ad && strict_memory_address_addr_space_p (mode, tem, as)) |
42c63e4d | 5215 | { |
5216 | /* Ok, we win that way. Replace any additional eliminable | |
5217 | registers. */ | |
5218 | ||
5219 | subst_reg_equivs_changed = 0; | |
93c7b06e | 5220 | tem = subst_reg_equivs (tem, insn); |
42c63e4d | 5221 | |
5222 | /* Make sure that didn't make the address invalid again. */ | |
5223 | ||
bd1a81f7 | 5224 | if (! subst_reg_equivs_changed |
5225 | || strict_memory_address_addr_space_p (mode, tem, as)) | |
42c63e4d | 5226 | { |
5227 | *loc = tem; | |
5228 | return 0; | |
5229 | } | |
5230 | } | |
5231 | ||
5232 | /* If constants aren't valid addresses, reload the constant address | |
5233 | into a register. */ | |
bd1a81f7 | 5234 | if (CONSTANT_P (ad) && ! strict_memory_address_addr_space_p (mode, ad, as)) |
42c63e4d | 5235 | { |
98155838 | 5236 | enum machine_mode address_mode = GET_MODE (ad); |
7c079699 | 5237 | if (address_mode == VOIDmode) |
98155838 | 5238 | address_mode = targetm.addr_space.address_mode (as); |
5239 | ||
4822deca | 5240 | /* If AD is an address in the constant pool, the MEM rtx may be shared. |
42c63e4d | 5241 | Unshare it so we can safely alter it. */ |
5242 | if (memrefloc && GET_CODE (ad) == SYMBOL_REF | |
5243 | && CONSTANT_POOL_ADDRESS_P (ad)) | |
5244 | { | |
42c63e4d | 5245 | *memrefloc = copy_rtx (*memrefloc); |
5246 | loc = &XEXP (*memrefloc, 0); | |
be2828ce | 5247 | if (removed_and) |
5248 | loc = &XEXP (*loc, 0); | |
42c63e4d | 5249 | } |
5250 | ||
f8a8fc7b | 5251 | find_reloads_address_part (ad, loc, |
5252 | base_reg_class (mode, as, MEM, SCRATCH), | |
98155838 | 5253 | address_mode, opnum, type, ind_levels); |
be2828ce | 5254 | return ! removed_and; |
42c63e4d | 5255 | } |
5256 | ||
f8a8fc7b | 5257 | return find_reloads_address_1 (mode, as, ad, 0, MEM, SCRATCH, loc, |
5258 | opnum, type, ind_levels, insn); | |
42c63e4d | 5259 | } |
5260 | \f | |
5261 | /* Find all pseudo regs appearing in AD | |
5262 | that are eliminable in favor of equivalent values | |
93c7b06e | 5263 | and do not have hard regs; replace them by their equivalents. |
5264 | INSN, if nonzero, is the insn in which we do the reload. We put USEs in | |
5265 | front of it for pseudos that we have to replace with stack slots. */ | |
42c63e4d | 5266 | |
5267 | static rtx | |
3ad4992f | 5268 | subst_reg_equivs (rtx ad, rtx insn) |
42c63e4d | 5269 | { |
19cb6b50 | 5270 | RTX_CODE code = GET_CODE (ad); |
5271 | int i; | |
5272 | const char *fmt; | |
42c63e4d | 5273 | |
5274 | switch (code) | |
5275 | { | |
5276 | case HIGH: | |
5277 | case CONST_INT: | |
5278 | case CONST: | |
5279 | case CONST_DOUBLE: | |
e397ad8e | 5280 | case CONST_FIXED: |
886cfd4f | 5281 | case CONST_VECTOR: |
42c63e4d | 5282 | case SYMBOL_REF: |
5283 | case LABEL_REF: | |
5284 | case PC: | |
5285 | case CC0: | |
5286 | return ad; | |
5287 | ||
5288 | case REG: | |
5289 | { | |
19cb6b50 | 5290 | int regno = REGNO (ad); |
42c63e4d | 5291 | |
1c654ff1 | 5292 | if (reg_equiv_constant (regno) != 0) |
42c63e4d | 5293 | { |
5294 | subst_reg_equivs_changed = 1; | |
1c654ff1 | 5295 | return reg_equiv_constant (regno); |
42c63e4d | 5296 | } |
1c654ff1 | 5297 | if (reg_equiv_memory_loc (regno) && num_not_at_initial_offset) |
93c7b06e | 5298 | { |
5299 | rtx mem = make_memloc (ad, regno); | |
1c654ff1 | 5300 | if (! rtx_equal_p (mem, reg_equiv_mem (regno))) |
93c7b06e | 5301 | { |
5302 | subst_reg_equivs_changed = 1; | |
b2920130 | 5303 | /* We mark the USE with QImode so that we recognize it |
5304 | as one that can be safely deleted at the end of | |
5305 | reload. */ | |
5306 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, ad), insn), | |
5307 | QImode); | |
93c7b06e | 5308 | return mem; |
5309 | } | |
5310 | } | |
42c63e4d | 5311 | } |
5312 | return ad; | |
5313 | ||
5314 | case PLUS: | |
5315 | /* Quickly dispose of a common case. */ | |
5316 | if (XEXP (ad, 0) == frame_pointer_rtx | |
971ba038 | 5317 | && CONST_INT_P (XEXP (ad, 1))) |
42c63e4d | 5318 | return ad; |
0dbd1c74 | 5319 | break; |
5bb2f919 | 5320 | |
0dbd1c74 | 5321 | default: |
5322 | break; | |
42c63e4d | 5323 | } |
5324 | ||
5325 | fmt = GET_RTX_FORMAT (code); | |
5326 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5327 | if (fmt[i] == 'e') | |
93c7b06e | 5328 | XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i), insn); |
42c63e4d | 5329 | return ad; |
5330 | } | |
5331 | \f | |
5332 | /* Compute the sum of X and Y, making canonicalizations assumed in an | |
5333 | address, namely: sum constant integers, surround the sum of two | |
5334 | constants with a CONST, put the constant as the second operand, and | |
5335 | group the constant on the outermost sum. | |
5336 | ||
5337 | This routine assumes both inputs are already in canonical form. */ | |
5338 | ||
5339 | rtx | |
98155838 | 5340 | form_sum (enum machine_mode mode, rtx x, rtx y) |
42c63e4d | 5341 | { |
5342 | rtx tem; | |
5639a241 | 5343 | |
98155838 | 5344 | gcc_assert (GET_MODE (x) == mode || GET_MODE (x) == VOIDmode); |
5345 | gcc_assert (GET_MODE (y) == mode || GET_MODE (y) == VOIDmode); | |
42c63e4d | 5346 | |
971ba038 | 5347 | if (CONST_INT_P (x)) |
42c63e4d | 5348 | return plus_constant (y, INTVAL (x)); |
971ba038 | 5349 | else if (CONST_INT_P (y)) |
42c63e4d | 5350 | return plus_constant (x, INTVAL (y)); |
5351 | else if (CONSTANT_P (x)) | |
5352 | tem = x, x = y, y = tem; | |
5353 | ||
5354 | if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1))) | |
98155838 | 5355 | return form_sum (mode, XEXP (x, 0), form_sum (mode, XEXP (x, 1), y)); |
42c63e4d | 5356 | |
5357 | /* Note that if the operands of Y are specified in the opposite | |
5358 | order in the recursive calls below, infinite recursion will occur. */ | |
76fd2b65 | 5359 | if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1))) |
98155838 | 5360 | return form_sum (mode, form_sum (mode, x, XEXP (y, 0)), XEXP (y, 1)); |
42c63e4d | 5361 | |
5362 | /* If both constant, encapsulate sum. Otherwise, just form sum. A | |
5363 | constant will have been placed second. */ | |
5364 | if (CONSTANT_P (x) && CONSTANT_P (y)) | |
5365 | { | |
5366 | if (GET_CODE (x) == CONST) | |
5367 | x = XEXP (x, 0); | |
5368 | if (GET_CODE (y) == CONST) | |
5369 | y = XEXP (y, 0); | |
5370 | ||
941522d6 | 5371 | return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y)); |
42c63e4d | 5372 | } |
5373 | ||
941522d6 | 5374 | return gen_rtx_PLUS (mode, x, y); |
42c63e4d | 5375 | } |
5376 | \f | |
5377 | /* If ADDR is a sum containing a pseudo register that should be | |
5378 | replaced with a constant (from reg_equiv_constant), | |
5379 | return the result of doing so, and also apply the associative | |
5380 | law so that the result is more likely to be a valid address. | |
5381 | (But it is not guaranteed to be one.) | |
5382 | ||
5383 | Note that at most one register is replaced, even if more are | |
5384 | replaceable. Also, we try to put the result into a canonical form | |
5385 | so it is more likely to be a valid address. | |
5386 | ||
5387 | In all other cases, return ADDR. */ | |
5388 | ||
5389 | static rtx | |
3ad4992f | 5390 | subst_indexed_address (rtx addr) |
42c63e4d | 5391 | { |
5392 | rtx op0 = 0, op1 = 0, op2 = 0; | |
5393 | rtx tem; | |
5394 | int regno; | |
5395 | ||
5396 | if (GET_CODE (addr) == PLUS) | |
5397 | { | |
5398 | /* Try to find a register to replace. */ | |
5399 | op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0; | |
8ad4c111 | 5400 | if (REG_P (op0) |
42c63e4d | 5401 | && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER |
5402 | && reg_renumber[regno] < 0 | |
1c654ff1 | 5403 | && reg_equiv_constant (regno) != 0) |
5404 | op0 = reg_equiv_constant (regno); | |
8ad4c111 | 5405 | else if (REG_P (op1) |
5bb2f919 | 5406 | && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER |
5407 | && reg_renumber[regno] < 0 | |
1c654ff1 | 5408 | && reg_equiv_constant (regno) != 0) |
5409 | op1 = reg_equiv_constant (regno); | |
42c63e4d | 5410 | else if (GET_CODE (op0) == PLUS |
5411 | && (tem = subst_indexed_address (op0)) != op0) | |
5412 | op0 = tem; | |
5413 | else if (GET_CODE (op1) == PLUS | |
5414 | && (tem = subst_indexed_address (op1)) != op1) | |
5415 | op1 = tem; | |
5416 | else | |
5417 | return addr; | |
5418 | ||
5419 | /* Pick out up to three things to add. */ | |
5420 | if (GET_CODE (op1) == PLUS) | |
5421 | op2 = XEXP (op1, 1), op1 = XEXP (op1, 0); | |
5422 | else if (GET_CODE (op0) == PLUS) | |
5423 | op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
5424 | ||
5425 | /* Compute the sum. */ | |
5426 | if (op2 != 0) | |
98155838 | 5427 | op1 = form_sum (GET_MODE (addr), op1, op2); |
42c63e4d | 5428 | if (op1 != 0) |
98155838 | 5429 | op0 = form_sum (GET_MODE (addr), op0, op1); |
42c63e4d | 5430 | |
5431 | return op0; | |
5432 | } | |
5433 | return addr; | |
5434 | } | |
5435 | \f | |
f15e7e72 | 5436 | /* Update the REG_INC notes for an insn. It updates all REG_INC |
5437 | notes for the instruction which refer to REGNO the to refer | |
5438 | to the reload number. | |
5439 | ||
5440 | INSN is the insn for which any REG_INC notes need updating. | |
5441 | ||
5442 | REGNO is the register number which has been reloaded. | |
5443 | ||
5444 | RELOADNUM is the reload number. */ | |
5445 | ||
5446 | static void | |
3ad4992f | 5447 | update_auto_inc_notes (rtx insn ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED, |
5448 | int reloadnum ATTRIBUTE_UNUSED) | |
f15e7e72 | 5449 | { |
5450 | #ifdef AUTO_INC_DEC | |
5451 | rtx link; | |
5452 | ||
5453 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
5454 | if (REG_NOTE_KIND (link) == REG_INC | |
3473aefe | 5455 | && (int) REGNO (XEXP (link, 0)) == regno) |
f15e7e72 | 5456 | push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); |
5457 | #endif | |
5458 | } | |
5459 | \f | |
7166ebd0 | 5460 | /* Record the pseudo registers we must reload into hard registers in a |
5461 | subexpression of a would-be memory address, X referring to a value | |
5462 | in mode MODE. (This function is not called if the address we find | |
5463 | is strictly valid.) | |
5464 | ||
42c63e4d | 5465 | CONTEXT = 1 means we are considering regs as index regs, |
00cb30dc | 5466 | = 0 means we are considering them as base regs. |
5467 | OUTER_CODE is the code of the enclosing RTX, typically a MEM, a PLUS, | |
5468 | or an autoinc code. | |
5469 | If CONTEXT == 0 and OUTER_CODE is a PLUS or LO_SUM, then INDEX_CODE | |
5470 | is the code of the index part of the address. Otherwise, pass SCRATCH | |
5471 | for this argument. | |
70457512 | 5472 | OPNUM and TYPE specify the purpose of any reloads made. |
42c63e4d | 5473 | |
5474 | IND_LEVELS says how many levels of indirect addressing are | |
5475 | supported at this point in the address. | |
5476 | ||
d59f2d23 | 5477 | INSN, if nonzero, is the insn in which we do the reload. It is used |
5478 | to determine if we may generate output reloads. | |
5479 | ||
42c63e4d | 5480 | We return nonzero if X, as a whole, is reloaded or replaced. */ |
5481 | ||
5482 | /* Note that we take shortcuts assuming that no multi-reg machine mode | |
5483 | occurs as part of an address. | |
5484 | Also, this is not fully machine-customizable; it works for machines | |
6c842310 | 5485 | such as VAXen and 68000's and 32000's, but other possible machines |
6af46e97 | 5486 | could have addressing modes that this does not handle right. |
5487 | If you add push_reload calls here, you need to make sure gen_reload | |
5488 | handles those cases gracefully. */ | |
42c63e4d | 5489 | |
5490 | static int | |
f8a8fc7b | 5491 | find_reloads_address_1 (enum machine_mode mode, addr_space_t as, |
5492 | rtx x, int context, | |
00cb30dc | 5493 | enum rtx_code outer_code, enum rtx_code index_code, |
3ad4992f | 5494 | rtx *loc, int opnum, enum reload_type type, |
5495 | int ind_levels, rtx insn) | |
42c63e4d | 5496 | { |
f8a8fc7b | 5497 | #define REG_OK_FOR_CONTEXT(CONTEXT, REGNO, MODE, AS, OUTER, INDEX) \ |
00cb30dc | 5498 | ((CONTEXT) == 0 \ |
f8a8fc7b | 5499 | ? regno_ok_for_base_p (REGNO, MODE, AS, OUTER, INDEX) \ |
48e1416a | 5500 | : REGNO_OK_FOR_INDEX_P (REGNO)) |
6006f9fd | 5501 | |
5502 | enum reg_class context_reg_class; | |
19cb6b50 | 5503 | RTX_CODE code = GET_CODE (x); |
42c63e4d | 5504 | |
00cb30dc | 5505 | if (context == 1) |
6006f9fd | 5506 | context_reg_class = INDEX_REG_CLASS; |
5507 | else | |
f8a8fc7b | 5508 | context_reg_class = base_reg_class (mode, as, outer_code, index_code); |
6006f9fd | 5509 | |
d5705e3f | 5510 | switch (code) |
42c63e4d | 5511 | { |
d5705e3f | 5512 | case PLUS: |
5513 | { | |
19cb6b50 | 5514 | rtx orig_op0 = XEXP (x, 0); |
5515 | rtx orig_op1 = XEXP (x, 1); | |
5516 | RTX_CODE code0 = GET_CODE (orig_op0); | |
5517 | RTX_CODE code1 = GET_CODE (orig_op1); | |
5518 | rtx op0 = orig_op0; | |
5519 | rtx op1 = orig_op1; | |
d5705e3f | 5520 | |
5521 | if (GET_CODE (op0) == SUBREG) | |
5522 | { | |
5523 | op0 = SUBREG_REG (op0); | |
5524 | code0 = GET_CODE (op0); | |
d21539ca | 5525 | if (code0 == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER) |
941522d6 | 5526 | op0 = gen_rtx_REG (word_mode, |
701e46d0 | 5527 | (REGNO (op0) + |
5528 | subreg_regno_offset (REGNO (SUBREG_REG (orig_op0)), | |
5529 | GET_MODE (SUBREG_REG (orig_op0)), | |
5530 | SUBREG_BYTE (orig_op0), | |
5531 | GET_MODE (orig_op0)))); | |
d5705e3f | 5532 | } |
70c3bfbb | 5533 | |
d5705e3f | 5534 | if (GET_CODE (op1) == SUBREG) |
5535 | { | |
5536 | op1 = SUBREG_REG (op1); | |
5537 | code1 = GET_CODE (op1); | |
d21539ca | 5538 | if (code1 == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER) |
701e46d0 | 5539 | /* ??? Why is this given op1's mode and above for |
5540 | ??? op0 SUBREGs we use word_mode? */ | |
941522d6 | 5541 | op1 = gen_rtx_REG (GET_MODE (op1), |
701e46d0 | 5542 | (REGNO (op1) + |
5543 | subreg_regno_offset (REGNO (SUBREG_REG (orig_op1)), | |
5544 | GET_MODE (SUBREG_REG (orig_op1)), | |
5545 | SUBREG_BYTE (orig_op1), | |
5546 | GET_MODE (orig_op1)))); | |
d5705e3f | 5547 | } |
d9b3752c | 5548 | /* Plus in the index register may be created only as a result of |
554f2707 | 5549 | register rematerialization for expression like &localvar*4. Reload it. |
d9b3752c | 5550 | It may be possible to combine the displacement on the outer level, |
5551 | but it is probably not worthwhile to do so. */ | |
6006f9fd | 5552 | if (context == 1) |
d9b3752c | 5553 | { |
5554 | find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0), | |
5555 | opnum, ADDR_TYPE (type), ind_levels, insn); | |
5556 | push_reload (*loc, NULL_RTX, loc, (rtx*) 0, | |
6006f9fd | 5557 | context_reg_class, |
d9b3752c | 5558 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5559 | return 1; | |
5560 | } | |
d5705e3f | 5561 | |
5bb2f919 | 5562 | if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE |
0afe8fd5 | 5563 | || code0 == ZERO_EXTEND || code1 == MEM) |
d5705e3f | 5564 | { |
f8a8fc7b | 5565 | find_reloads_address_1 (mode, as, orig_op0, 1, PLUS, SCRATCH, |
00cb30dc | 5566 | &XEXP (x, 0), opnum, type, ind_levels, |
5567 | insn); | |
f8a8fc7b | 5568 | find_reloads_address_1 (mode, as, orig_op1, 0, PLUS, code0, |
00cb30dc | 5569 | &XEXP (x, 1), opnum, type, ind_levels, |
5570 | insn); | |
d5705e3f | 5571 | } |
5572 | ||
0afe8fd5 | 5573 | else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE |
5574 | || code1 == ZERO_EXTEND || code0 == MEM) | |
d5705e3f | 5575 | { |
f8a8fc7b | 5576 | find_reloads_address_1 (mode, as, orig_op0, 0, PLUS, code1, |
00cb30dc | 5577 | &XEXP (x, 0), opnum, type, ind_levels, |
5578 | insn); | |
f8a8fc7b | 5579 | find_reloads_address_1 (mode, as, orig_op1, 1, PLUS, SCRATCH, |
00cb30dc | 5580 | &XEXP (x, 1), opnum, type, ind_levels, |
5581 | insn); | |
d5705e3f | 5582 | } |
5583 | ||
5584 | else if (code0 == CONST_INT || code0 == CONST | |
5585 | || code0 == SYMBOL_REF || code0 == LABEL_REF) | |
f8a8fc7b | 5586 | find_reloads_address_1 (mode, as, orig_op1, 0, PLUS, code0, |
00cb30dc | 5587 | &XEXP (x, 1), opnum, type, ind_levels, |
5588 | insn); | |
d5705e3f | 5589 | |
5590 | else if (code1 == CONST_INT || code1 == CONST | |
5591 | || code1 == SYMBOL_REF || code1 == LABEL_REF) | |
f8a8fc7b | 5592 | find_reloads_address_1 (mode, as, orig_op0, 0, PLUS, code1, |
00cb30dc | 5593 | &XEXP (x, 0), opnum, type, ind_levels, |
5594 | insn); | |
d5705e3f | 5595 | |
5596 | else if (code0 == REG && code1 == REG) | |
5597 | { | |
ce0d0c3a | 5598 | if (REGNO_OK_FOR_INDEX_P (REGNO (op1)) |
f8a8fc7b | 5599 | && regno_ok_for_base_p (REGNO (op0), mode, as, PLUS, REG)) |
d5705e3f | 5600 | return 0; |
ce0d0c3a | 5601 | else if (REGNO_OK_FOR_INDEX_P (REGNO (op0)) |
f8a8fc7b | 5602 | && regno_ok_for_base_p (REGNO (op1), mode, as, PLUS, REG)) |
d5705e3f | 5603 | return 0; |
f8a8fc7b | 5604 | else if (regno_ok_for_base_p (REGNO (op0), mode, as, PLUS, REG)) |
5605 | find_reloads_address_1 (mode, as, orig_op1, 1, PLUS, SCRATCH, | |
00cb30dc | 5606 | &XEXP (x, 1), opnum, type, ind_levels, |
5607 | insn); | |
5608 | else if (REGNO_OK_FOR_INDEX_P (REGNO (op1))) | |
f8a8fc7b | 5609 | find_reloads_address_1 (mode, as, orig_op0, 0, PLUS, REG, |
00cb30dc | 5610 | &XEXP (x, 0), opnum, type, ind_levels, |
5611 | insn); | |
f8a8fc7b | 5612 | else if (regno_ok_for_base_p (REGNO (op1), mode, as, PLUS, REG)) |
5613 | find_reloads_address_1 (mode, as, orig_op0, 1, PLUS, SCRATCH, | |
ce0d0c3a | 5614 | &XEXP (x, 0), opnum, type, ind_levels, |
5615 | insn); | |
00cb30dc | 5616 | else if (REGNO_OK_FOR_INDEX_P (REGNO (op0))) |
f8a8fc7b | 5617 | find_reloads_address_1 (mode, as, orig_op1, 0, PLUS, REG, |
00cb30dc | 5618 | &XEXP (x, 1), opnum, type, ind_levels, |
5619 | insn); | |
d5705e3f | 5620 | else |
5621 | { | |
f8a8fc7b | 5622 | find_reloads_address_1 (mode, as, orig_op0, 0, PLUS, REG, |
00cb30dc | 5623 | &XEXP (x, 0), opnum, type, ind_levels, |
5624 | insn); | |
f8a8fc7b | 5625 | find_reloads_address_1 (mode, as, orig_op1, 1, PLUS, SCRATCH, |
00cb30dc | 5626 | &XEXP (x, 1), opnum, type, ind_levels, |
5627 | insn); | |
d5705e3f | 5628 | } |
5629 | } | |
5630 | ||
5631 | else if (code0 == REG) | |
5632 | { | |
f8a8fc7b | 5633 | find_reloads_address_1 (mode, as, orig_op0, 1, PLUS, SCRATCH, |
00cb30dc | 5634 | &XEXP (x, 0), opnum, type, ind_levels, |
5635 | insn); | |
f8a8fc7b | 5636 | find_reloads_address_1 (mode, as, orig_op1, 0, PLUS, REG, |
00cb30dc | 5637 | &XEXP (x, 1), opnum, type, ind_levels, |
5638 | insn); | |
d5705e3f | 5639 | } |
5640 | ||
5641 | else if (code1 == REG) | |
5642 | { | |
f8a8fc7b | 5643 | find_reloads_address_1 (mode, as, orig_op1, 1, PLUS, SCRATCH, |
00cb30dc | 5644 | &XEXP (x, 1), opnum, type, ind_levels, |
5645 | insn); | |
f8a8fc7b | 5646 | find_reloads_address_1 (mode, as, orig_op0, 0, PLUS, REG, |
00cb30dc | 5647 | &XEXP (x, 0), opnum, type, ind_levels, |
5648 | insn); | |
d5705e3f | 5649 | } |
5650 | } | |
5651 | ||
5652 | return 0; | |
5653 | ||
40988080 | 5654 | case POST_MODIFY: |
5655 | case PRE_MODIFY: | |
5656 | { | |
5657 | rtx op0 = XEXP (x, 0); | |
5658 | rtx op1 = XEXP (x, 1); | |
00cb30dc | 5659 | enum rtx_code index_code; |
04e579b6 | 5660 | int regno; |
5661 | int reloadnum; | |
40988080 | 5662 | |
5663 | if (GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS) | |
5664 | return 0; | |
5665 | ||
5666 | /* Currently, we only support {PRE,POST}_MODIFY constructs | |
5667 | where a base register is {inc,dec}remented by the contents | |
5668 | of another register or by a constant value. Thus, these | |
5669 | operands must match. */ | |
04e579b6 | 5670 | gcc_assert (op0 == XEXP (op1, 0)); |
40988080 | 5671 | |
5672 | /* Require index register (or constant). Let's just handle the | |
5673 | register case in the meantime... If the target allows | |
5674 | auto-modify by a constant then we could try replacing a pseudo | |
23c79c0f | 5675 | register with its equivalent constant where applicable. |
5676 | ||
cc6757ec | 5677 | We also handle the case where the register was eliminated |
5678 | resulting in a PLUS subexpression. | |
5679 | ||
23c79c0f | 5680 | If we later decide to reload the whole PRE_MODIFY or |
5681 | POST_MODIFY, inc_for_reload might clobber the reload register | |
5682 | before reading the index. The index register might therefore | |
5683 | need to live longer than a TYPE reload normally would, so be | |
5684 | conservative and class it as RELOAD_OTHER. */ | |
cc6757ec | 5685 | if ((REG_P (XEXP (op1, 1)) |
5686 | && !REGNO_OK_FOR_INDEX_P (REGNO (XEXP (op1, 1)))) | |
5687 | || GET_CODE (XEXP (op1, 1)) == PLUS) | |
f8a8fc7b | 5688 | find_reloads_address_1 (mode, as, XEXP (op1, 1), 1, code, SCRATCH, |
cc6757ec | 5689 | &XEXP (op1, 1), opnum, RELOAD_OTHER, |
5690 | ind_levels, insn); | |
40988080 | 5691 | |
04e579b6 | 5692 | gcc_assert (REG_P (XEXP (op1, 0))); |
40988080 | 5693 | |
04e579b6 | 5694 | regno = REGNO (XEXP (op1, 0)); |
00cb30dc | 5695 | index_code = GET_CODE (XEXP (op1, 1)); |
04e579b6 | 5696 | |
5697 | /* A register that is incremented cannot be constant! */ | |
5698 | gcc_assert (regno < FIRST_PSEUDO_REGISTER | |
1c654ff1 | 5699 | || reg_equiv_constant (regno) == 0); |
40988080 | 5700 | |
04e579b6 | 5701 | /* Handle a register that is equivalent to a memory location |
5702 | which cannot be addressed directly. */ | |
1c654ff1 | 5703 | if (reg_equiv_memory_loc (regno) != 0 |
5704 | && (reg_equiv_address (regno) != 0 | |
04e579b6 | 5705 | || num_not_at_initial_offset)) |
5706 | { | |
5707 | rtx tem = make_memloc (XEXP (x, 0), regno); | |
40988080 | 5708 | |
1c654ff1 | 5709 | if (reg_equiv_address (regno) |
5710 | || ! rtx_equal_p (tem, reg_equiv_mem (regno))) | |
40988080 | 5711 | { |
d51b37c2 | 5712 | rtx orig = tem; |
5713 | ||
04e579b6 | 5714 | /* First reload the memory location's address. |
5715 | We can't use ADDR_TYPE (type) here, because we need to | |
5716 | write back the value after reading it, hence we actually | |
5717 | need two registers. */ | |
5718 | find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), | |
5719 | &XEXP (tem, 0), opnum, | |
5720 | RELOAD_OTHER, | |
5721 | ind_levels, insn); | |
5722 | ||
c89e828f | 5723 | if (!rtx_equal_p (tem, orig)) |
d51b37c2 | 5724 | push_reg_equiv_alt_mem (regno, tem); |
5725 | ||
04e579b6 | 5726 | /* Then reload the memory location into a base |
00cb30dc | 5727 | register. */ |
04e579b6 | 5728 | reloadnum = push_reload (tem, tem, &XEXP (x, 0), |
00cb30dc | 5729 | &XEXP (op1, 0), |
f8a8fc7b | 5730 | base_reg_class (mode, as, |
5731 | code, index_code), | |
00cb30dc | 5732 | GET_MODE (x), GET_MODE (x), 0, |
5733 | 0, opnum, RELOAD_OTHER); | |
ab7883ae | 5734 | |
f15e7e72 | 5735 | update_auto_inc_notes (this_insn, regno, reloadnum); |
5736 | return 0; | |
5737 | } | |
40988080 | 5738 | } |
04e579b6 | 5739 | |
5740 | if (reg_renumber[regno] >= 0) | |
5741 | regno = reg_renumber[regno]; | |
5742 | ||
5743 | /* We require a base register here... */ | |
f8a8fc7b | 5744 | if (!regno_ok_for_base_p (regno, GET_MODE (x), as, code, index_code)) |
04e579b6 | 5745 | { |
5746 | reloadnum = push_reload (XEXP (op1, 0), XEXP (x, 0), | |
00cb30dc | 5747 | &XEXP (op1, 0), &XEXP (x, 0), |
f8a8fc7b | 5748 | base_reg_class (mode, as, |
5749 | code, index_code), | |
00cb30dc | 5750 | GET_MODE (x), GET_MODE (x), 0, 0, |
5751 | opnum, RELOAD_OTHER); | |
04e579b6 | 5752 | |
5753 | update_auto_inc_notes (this_insn, regno, reloadnum); | |
5754 | return 0; | |
5755 | } | |
40988080 | 5756 | } |
5757 | return 0; | |
5758 | ||
d5705e3f | 5759 | case POST_INC: |
5760 | case POST_DEC: | |
5761 | case PRE_INC: | |
5762 | case PRE_DEC: | |
8ad4c111 | 5763 | if (REG_P (XEXP (x, 0))) |
42c63e4d | 5764 | { |
19cb6b50 | 5765 | int regno = REGNO (XEXP (x, 0)); |
42c63e4d | 5766 | int value = 0; |
5767 | rtx x_orig = x; | |
5768 | ||
5769 | /* A register that is incremented cannot be constant! */ | |
04e579b6 | 5770 | gcc_assert (regno < FIRST_PSEUDO_REGISTER |
1c654ff1 | 5771 | || reg_equiv_constant (regno) == 0); |
42c63e4d | 5772 | |
5773 | /* Handle a register that is equivalent to a memory location | |
5774 | which cannot be addressed directly. */ | |
1c654ff1 | 5775 | if (reg_equiv_memory_loc (regno) != 0 |
5776 | && (reg_equiv_address (regno) != 0 || num_not_at_initial_offset)) | |
42c63e4d | 5777 | { |
5778 | rtx tem = make_memloc (XEXP (x, 0), regno); | |
1c654ff1 | 5779 | if (reg_equiv_address (regno) |
5780 | || ! rtx_equal_p (tem, reg_equiv_mem (regno))) | |
93c7b06e | 5781 | { |
d51b37c2 | 5782 | rtx orig = tem; |
5783 | ||
93c7b06e | 5784 | /* First reload the memory location's address. |
5785 | We can't use ADDR_TYPE (type) here, because we need to | |
5786 | write back the value after reading it, hence we actually | |
5787 | need two registers. */ | |
5788 | find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), | |
5789 | &XEXP (tem, 0), opnum, type, | |
5790 | ind_levels, insn); | |
c89e828f | 5791 | if (!rtx_equal_p (tem, orig)) |
d51b37c2 | 5792 | push_reg_equiv_alt_mem (regno, tem); |
93c7b06e | 5793 | /* Put this inside a new increment-expression. */ |
5794 | x = gen_rtx_fmt_e (GET_CODE (x), GET_MODE (x), tem); | |
5795 | /* Proceed to reload that, as if it contained a register. */ | |
5796 | } | |
42c63e4d | 5797 | } |
5798 | ||
d938b513 | 5799 | /* If we have a hard register that is ok in this incdec context, |
5800 | don't make a reload. If the register isn't nice enough for | |
5801 | autoincdec, we can reload it. But, if an autoincrement of a | |
5802 | register that we here verified as playing nice, still outside | |
42c63e4d | 5803 | isn't "valid", it must be that no autoincrement is "valid". |
5804 | If that is true and something made an autoincrement anyway, | |
5805 | this must be a special context where one is allowed. | |
5806 | (For example, a "push" instruction.) | |
5807 | We can't improve this address, so leave it alone. */ | |
5808 | ||
5809 | /* Otherwise, reload the autoincrement into a suitable hard reg | |
5810 | and record how much to increment by. */ | |
5811 | ||
5812 | if (reg_renumber[regno] >= 0) | |
5813 | regno = reg_renumber[regno]; | |
6006f9fd | 5814 | if (regno >= FIRST_PSEUDO_REGISTER |
f8a8fc7b | 5815 | || !REG_OK_FOR_CONTEXT (context, regno, mode, as, code, |
00cb30dc | 5816 | index_code)) |
42c63e4d | 5817 | { |
d59f2d23 | 5818 | int reloadnum; |
5819 | ||
5820 | /* If we can output the register afterwards, do so, this | |
5821 | saves the extra update. | |
5822 | We can do so if we have an INSN - i.e. no JUMP_INSN nor | |
5823 | CALL_INSN - and it does not set CC0. | |
5824 | But don't do this if we cannot directly address the | |
5825 | memory location, since this will make it harder to | |
ad87de1e | 5826 | reuse address reloads, and increases register pressure. |
d59f2d23 | 5827 | Also don't do this if we can probably update x directly. */ |
e16ceb8e | 5828 | rtx equiv = (MEM_P (XEXP (x, 0)) |
93c7b06e | 5829 | ? XEXP (x, 0) |
1c654ff1 | 5830 | : reg_equiv_mem (regno)); |
39c56a89 | 5831 | enum insn_code icode = optab_handler (add_optab, GET_MODE (x)); |
6d7dc5b9 | 5832 | if (insn && NONJUMP_INSN_P (insn) && equiv |
93c7b06e | 5833 | && memory_operand (equiv, GET_MODE (equiv)) |
d59f2d23 | 5834 | #ifdef HAVE_cc0 |
5835 | && ! sets_cc0_p (PATTERN (insn)) | |
5836 | #endif | |
5837 | && ! (icode != CODE_FOR_nothing | |
39c56a89 | 5838 | && insn_operand_matches (icode, 0, equiv) |
5839 | && insn_operand_matches (icode, 1, equiv))) | |
d59f2d23 | 5840 | { |
2b1e2054 | 5841 | /* We use the original pseudo for loc, so that |
5842 | emit_reload_insns() knows which pseudo this | |
5843 | reload refers to and updates the pseudo rtx, not | |
5844 | its equivalent memory location, as well as the | |
5845 | corresponding entry in reg_last_reload_reg. */ | |
5846 | loc = &XEXP (x_orig, 0); | |
d59f2d23 | 5847 | x = XEXP (x, 0); |
5848 | reloadnum | |
5849 | = push_reload (x, x, loc, loc, | |
6006f9fd | 5850 | context_reg_class, |
5bb2f919 | 5851 | GET_MODE (x), GET_MODE (x), 0, 0, |
5852 | opnum, RELOAD_OTHER); | |
d59f2d23 | 5853 | } |
5854 | else | |
5855 | { | |
5856 | reloadnum | |
45a0ce77 | 5857 | = push_reload (x, x, loc, (rtx*) 0, |
6006f9fd | 5858 | context_reg_class, |
0dbd1c74 | 5859 | GET_MODE (x), GET_MODE (x), 0, 0, |
d59f2d23 | 5860 | opnum, type); |
48666d2c | 5861 | rld[reloadnum].inc |
d59f2d23 | 5862 | = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0)); |
5bb2f919 | 5863 | |
d59f2d23 | 5864 | value = 1; |
5865 | } | |
42c63e4d | 5866 | |
f15e7e72 | 5867 | update_auto_inc_notes (this_insn, REGNO (XEXP (x_orig, 0)), |
5868 | reloadnum); | |
42c63e4d | 5869 | } |
5870 | return value; | |
5871 | } | |
d5705e3f | 5872 | return 0; |
5873 | ||
d4b16ceb | 5874 | case TRUNCATE: |
5875 | case SIGN_EXTEND: | |
5876 | case ZERO_EXTEND: | |
5877 | /* Look for parts to reload in the inner expression and reload them | |
5878 | too, in addition to this operation. Reloading all inner parts in | |
5879 | addition to this one shouldn't be necessary, but at this point, | |
5880 | we don't know if we can possibly omit any part that *can* be | |
5881 | reloaded. Targets that are better off reloading just either part | |
5882 | (or perhaps even a different part of an outer expression), should | |
5883 | define LEGITIMIZE_RELOAD_ADDRESS. */ | |
f8a8fc7b | 5884 | find_reloads_address_1 (GET_MODE (XEXP (x, 0)), as, XEXP (x, 0), |
00cb30dc | 5885 | context, code, SCRATCH, &XEXP (x, 0), opnum, |
d4b16ceb | 5886 | type, ind_levels, insn); |
5887 | push_reload (x, NULL_RTX, loc, (rtx*) 0, | |
5888 | context_reg_class, | |
5889 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); | |
5890 | return 1; | |
5891 | ||
d5705e3f | 5892 | case MEM: |
5893 | /* This is probably the result of a substitution, by eliminate_regs, of | |
5894 | an equivalent address for a pseudo that was not allocated to a hard | |
5895 | register. Verify that the specified address is valid and reload it | |
5896 | into a register. | |
42c63e4d | 5897 | |
d5705e3f | 5898 | Since we know we are going to reload this item, don't decrement for |
5899 | the indirection level. | |
42c63e4d | 5900 | |
5901 | Note that this is actually conservative: it would be slightly more | |
5902 | efficient to use the value of SPILL_INDIRECT_LEVELS from | |
5903 | reload1.c here. */ | |
5904 | ||
5905 | find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0), | |
d59f2d23 | 5906 | opnum, ADDR_TYPE (type), ind_levels, insn); |
33181afc | 5907 | push_reload (*loc, NULL_RTX, loc, (rtx*) 0, |
6006f9fd | 5908 | context_reg_class, |
70457512 | 5909 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
42c63e4d | 5910 | return 1; |
42c63e4d | 5911 | |
d5705e3f | 5912 | case REG: |
5913 | { | |
19cb6b50 | 5914 | int regno = REGNO (x); |
d5705e3f | 5915 | |
1c654ff1 | 5916 | if (reg_equiv_constant (regno) != 0) |
d5705e3f | 5917 | { |
1c654ff1 | 5918 | find_reloads_address_part (reg_equiv_constant (regno), loc, |
6006f9fd | 5919 | context_reg_class, |
d5705e3f | 5920 | GET_MODE (x), opnum, type, ind_levels); |
5921 | return 1; | |
5922 | } | |
42c63e4d | 5923 | |
5924 | #if 0 /* This might screw code in reload1.c to delete prior output-reload | |
5925 | that feeds this insn. */ | |
1c654ff1 | 5926 | if (reg_equiv_mem (regno) != 0) |
d5705e3f | 5927 | { |
1c654ff1 | 5928 | push_reload (reg_equiv_mem (regno), NULL_RTX, loc, (rtx*) 0, |
6006f9fd | 5929 | context_reg_class, |
d5705e3f | 5930 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5931 | return 1; | |
5932 | } | |
42c63e4d | 5933 | #endif |
42c63e4d | 5934 | |
1c654ff1 | 5935 | if (reg_equiv_memory_loc (regno) |
5936 | && (reg_equiv_address (regno) != 0 || num_not_at_initial_offset)) | |
d5705e3f | 5937 | { |
93c7b06e | 5938 | rtx tem = make_memloc (x, regno); |
1c654ff1 | 5939 | if (reg_equiv_address (regno) != 0 |
5940 | || ! rtx_equal_p (tem, reg_equiv_mem (regno))) | |
93c7b06e | 5941 | { |
5942 | x = tem; | |
5943 | find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), | |
5944 | &XEXP (x, 0), opnum, ADDR_TYPE (type), | |
5945 | ind_levels, insn); | |
c89e828f | 5946 | if (!rtx_equal_p (x, tem)) |
d51b37c2 | 5947 | push_reg_equiv_alt_mem (regno, x); |
93c7b06e | 5948 | } |
d5705e3f | 5949 | } |
42c63e4d | 5950 | |
d5705e3f | 5951 | if (reg_renumber[regno] >= 0) |
5952 | regno = reg_renumber[regno]; | |
5953 | ||
6006f9fd | 5954 | if (regno >= FIRST_PSEUDO_REGISTER |
f8a8fc7b | 5955 | || !REG_OK_FOR_CONTEXT (context, regno, mode, as, outer_code, |
00cb30dc | 5956 | index_code)) |
d5705e3f | 5957 | { |
33181afc | 5958 | push_reload (x, NULL_RTX, loc, (rtx*) 0, |
6006f9fd | 5959 | context_reg_class, |
d5705e3f | 5960 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5961 | return 1; | |
5962 | } | |
5963 | ||
5964 | /* If a register appearing in an address is the subject of a CLOBBER | |
5965 | in this insn, reload it into some other register to be safe. | |
5966 | The CLOBBER is supposed to make the register unavailable | |
5967 | from before this insn to after it. */ | |
ab7883ae | 5968 | if (regno_clobbered_p (regno, this_insn, GET_MODE (x), 0)) |
d5705e3f | 5969 | { |
33181afc | 5970 | push_reload (x, NULL_RTX, loc, (rtx*) 0, |
6006f9fd | 5971 | context_reg_class, |
d5705e3f | 5972 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5973 | return 1; | |
5974 | } | |
5975 | } | |
5976 | return 0; | |
5977 | ||
5978 | case SUBREG: | |
8ad4c111 | 5979 | if (REG_P (SUBREG_REG (x))) |
42c63e4d | 5980 | { |
d21539ca | 5981 | /* If this is a SUBREG of a hard register and the resulting register |
5982 | is of the wrong class, reload the whole SUBREG. This avoids | |
5983 | needless copies if SUBREG_REG is multi-word. */ | |
5984 | if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) | |
5985 | { | |
805e22b2 | 5986 | int regno ATTRIBUTE_UNUSED = subreg_regno (x); |
d5705e3f | 5987 | |
f8a8fc7b | 5988 | if (!REG_OK_FOR_CONTEXT (context, regno, mode, as, outer_code, |
00cb30dc | 5989 | index_code)) |
d21539ca | 5990 | { |
33181afc | 5991 | push_reload (x, NULL_RTX, loc, (rtx*) 0, |
6006f9fd | 5992 | context_reg_class, |
d21539ca | 5993 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
5994 | return 1; | |
5995 | } | |
5996 | } | |
b090827b | 5997 | /* If this is a SUBREG of a pseudo-register, and the pseudo-register |
d21539ca | 5998 | is larger than the class size, then reload the whole SUBREG. */ |
5999 | else | |
d5705e3f | 6000 | { |
47cfb7f4 | 6001 | enum reg_class rclass = context_reg_class; |
d3ba22dc | 6002 | if (ira_reg_class_max_nregs [rclass][GET_MODE (SUBREG_REG (x))] |
6003 | > reg_class_size[(int) rclass]) | |
d21539ca | 6004 | { |
48e1416a | 6005 | x = find_reloads_subreg_address (x, 0, opnum, |
b3425ed6 | 6006 | ADDR_TYPE (type), |
b5fe590a | 6007 | ind_levels, insn, NULL); |
47cfb7f4 | 6008 | push_reload (x, NULL_RTX, loc, (rtx*) 0, rclass, |
d21539ca | 6009 | GET_MODE (x), VOIDmode, 0, 0, opnum, type); |
6010 | return 1; | |
6011 | } | |
d5705e3f | 6012 | } |
42c63e4d | 6013 | } |
d5705e3f | 6014 | break; |
5bb2f919 | 6015 | |
0dbd1c74 | 6016 | default: |
6017 | break; | |
42c63e4d | 6018 | } |
6019 | ||
d5705e3f | 6020 | { |
19cb6b50 | 6021 | const char *fmt = GET_RTX_FORMAT (code); |
6022 | int i; | |
d5705e3f | 6023 | |
6024 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6025 | { | |
6026 | if (fmt[i] == 'e') | |
00cb30dc | 6027 | /* Pass SCRATCH for INDEX_CODE, since CODE can never be a PLUS once |
6028 | we get here. */ | |
f8a8fc7b | 6029 | find_reloads_address_1 (mode, as, XEXP (x, i), context, |
6030 | code, SCRATCH, &XEXP (x, i), | |
6031 | opnum, type, ind_levels, insn); | |
d5705e3f | 6032 | } |
6033 | } | |
6034 | ||
6006f9fd | 6035 | #undef REG_OK_FOR_CONTEXT |
42c63e4d | 6036 | return 0; |
6037 | } | |
6038 | \f | |
6039 | /* X, which is found at *LOC, is a part of an address that needs to be | |
47cfb7f4 | 6040 | reloaded into a register of class RCLASS. If X is a constant, or if |
42c63e4d | 6041 | X is a PLUS that contains a constant, check that the constant is a |
6042 | legitimate operand and that we are supposed to be able to load | |
6043 | it into the register. | |
6044 | ||
6045 | If not, force the constant into memory and reload the MEM instead. | |
6046 | ||
6047 | MODE is the mode to use, in case X is an integer constant. | |
6048 | ||
70457512 | 6049 | OPNUM and TYPE describe the purpose of any reloads made. |
42c63e4d | 6050 | |
6051 | IND_LEVELS says how many levels of indirect addressing this machine | |
6052 | supports. */ | |
6053 | ||
6054 | static void | |
47cfb7f4 | 6055 | find_reloads_address_part (rtx x, rtx *loc, enum reg_class rclass, |
3ad4992f | 6056 | enum machine_mode mode, int opnum, |
6057 | enum reload_type type, int ind_levels) | |
42c63e4d | 6058 | { |
6059 | if (CONSTANT_P (x) | |
ca316360 | 6060 | && (!targetm.legitimate_constant_p (mode, x) |
09a17585 | 6061 | || targetm.preferred_reload_class (x, rclass) == NO_REGS)) |
42c63e4d | 6062 | { |
7c88646f | 6063 | x = force_const_mem (mode, x); |
6064 | find_reloads_address (mode, &x, XEXP (x, 0), &XEXP (x, 0), | |
d59f2d23 | 6065 | opnum, type, ind_levels, 0); |
42c63e4d | 6066 | } |
6067 | ||
6068 | else if (GET_CODE (x) == PLUS | |
6069 | && CONSTANT_P (XEXP (x, 1)) | |
ca316360 | 6070 | && (!targetm.legitimate_constant_p (GET_MODE (x), XEXP (x, 1)) |
09a17585 | 6071 | || targetm.preferred_reload_class (XEXP (x, 1), rclass) |
6072 | == NO_REGS)) | |
42c63e4d | 6073 | { |
10b31fee | 6074 | rtx tem; |
6075 | ||
1ab50266 | 6076 | tem = force_const_mem (GET_MODE (x), XEXP (x, 1)); |
941522d6 | 6077 | x = gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), tem); |
7c88646f | 6078 | find_reloads_address (mode, &XEXP (x, 1), XEXP (tem, 0), &XEXP (tem, 0), |
d59f2d23 | 6079 | opnum, type, ind_levels, 0); |
42c63e4d | 6080 | } |
6081 | ||
47cfb7f4 | 6082 | push_reload (x, NULL_RTX, loc, (rtx*) 0, rclass, |
70457512 | 6083 | mode, VOIDmode, 0, 0, opnum, type); |
42c63e4d | 6084 | } |
6085 | \f | |
37f7956e | 6086 | /* X, a subreg of a pseudo, is a part of an address that needs to be |
6087 | reloaded. | |
6088 | ||
6089 | If the pseudo is equivalent to a memory location that cannot be directly | |
6090 | addressed, make the necessary address reloads. | |
6091 | ||
6092 | If address reloads have been necessary, or if the address is changed | |
6093 | by register elimination, return the rtx of the memory location; | |
6094 | otherwise, return X. | |
6095 | ||
6096 | If FORCE_REPLACE is nonzero, unconditionally replace the subreg with the | |
6097 | memory location. | |
6098 | ||
6099 | OPNUM and TYPE identify the purpose of the reload. | |
6100 | ||
6101 | IND_LEVELS says how many levels of indirect addressing are | |
6102 | supported at this point in the address. | |
6103 | ||
6104 | INSN, if nonzero, is the insn in which we do the reload. It is used | |
6105 | to determine where to put USEs for pseudos that we have to replace with | |
6106 | stack slots. */ | |
6107 | ||
6108 | static rtx | |
3ad4992f | 6109 | find_reloads_subreg_address (rtx x, int force_replace, int opnum, |
b5fe590a | 6110 | enum reload_type type, int ind_levels, rtx insn, |
6111 | int *address_reloaded) | |
37f7956e | 6112 | { |
6113 | int regno = REGNO (SUBREG_REG (x)); | |
b5fe590a | 6114 | int reloaded = 0; |
37f7956e | 6115 | |
1c654ff1 | 6116 | if (reg_equiv_memory_loc (regno)) |
37f7956e | 6117 | { |
6118 | /* If the address is not directly addressable, or if the address is not | |
6119 | offsettable, then it must be replaced. */ | |
6120 | if (! force_replace | |
1c654ff1 | 6121 | && (reg_equiv_address (regno) |
6122 | || ! offsettable_memref_p (reg_equiv_mem (regno)))) | |
37f7956e | 6123 | force_replace = 1; |
6124 | ||
6125 | if (force_replace || num_not_at_initial_offset) | |
6126 | { | |
6127 | rtx tem = make_memloc (SUBREG_REG (x), regno); | |
6128 | ||
6129 | /* If the address changes because of register elimination, then | |
f94acda8 | 6130 | it must be replaced. */ |
37f7956e | 6131 | if (force_replace |
1c654ff1 | 6132 | || ! rtx_equal_p (tem, reg_equiv_mem (regno))) |
37f7956e | 6133 | { |
2eceb392 | 6134 | unsigned outer_size = GET_MODE_SIZE (GET_MODE (x)); |
6135 | unsigned inner_size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))); | |
0afbf57d | 6136 | int offset; |
d51b37c2 | 6137 | rtx orig = tem; |
0afbf57d | 6138 | |
6139 | /* For big-endian paradoxical subregs, SUBREG_BYTE does not | |
6140 | hold the correct (negative) byte offset. */ | |
6141 | if (BYTES_BIG_ENDIAN && outer_size > inner_size) | |
6142 | offset = inner_size - outer_size; | |
6143 | else | |
6144 | offset = SUBREG_BYTE (x); | |
37f7956e | 6145 | |
37f7956e | 6146 | XEXP (tem, 0) = plus_constant (XEXP (tem, 0), offset); |
6147 | PUT_MODE (tem, GET_MODE (x)); | |
da443c27 | 6148 | if (MEM_OFFSET_KNOWN_P (tem)) |
6149 | set_mem_offset (tem, MEM_OFFSET (tem) + offset); | |
5b2a69fa | 6150 | if (MEM_SIZE_KNOWN_P (tem) |
6151 | && MEM_SIZE (tem) != (HOST_WIDE_INT) outer_size) | |
6152 | set_mem_size (tem, outer_size); | |
2eceb392 | 6153 | |
6154 | /* If this was a paradoxical subreg that we replaced, the | |
6155 | resulting memory must be sufficiently aligned to allow | |
6156 | us to widen the mode of the memory. */ | |
c2c4c18b | 6157 | if (outer_size > inner_size) |
2eceb392 | 6158 | { |
6159 | rtx base; | |
6160 | ||
6161 | base = XEXP (tem, 0); | |
6162 | if (GET_CODE (base) == PLUS) | |
6163 | { | |
971ba038 | 6164 | if (CONST_INT_P (XEXP (base, 1)) |
2eceb392 | 6165 | && INTVAL (XEXP (base, 1)) % outer_size != 0) |
6166 | return x; | |
6167 | base = XEXP (base, 0); | |
6168 | } | |
8ad4c111 | 6169 | if (!REG_P (base) |
2eceb392 | 6170 | || (REGNO_POINTER_ALIGN (REGNO (base)) |
6171 | < outer_size * BITS_PER_UNIT)) | |
6172 | return x; | |
6173 | } | |
6174 | ||
8d91a9b7 | 6175 | reloaded = find_reloads_address (GET_MODE (tem), &tem, |
6176 | XEXP (tem, 0), &XEXP (tem, 0), | |
6177 | opnum, type, ind_levels, insn); | |
d51b37c2 | 6178 | /* ??? Do we need to handle nonzero offsets somehow? */ |
c89e828f | 6179 | if (!offset && !rtx_equal_p (tem, orig)) |
d51b37c2 | 6180 | push_reg_equiv_alt_mem (regno, tem); |
2eceb392 | 6181 | |
8d91a9b7 | 6182 | /* For some processors an address may be valid in the |
6183 | original mode but not in a smaller mode. For | |
6184 | example, ARM accepts a scaled index register in | |
79141aaa | 6185 | SImode but not in HImode. Note that this is only |
6186 | a problem if the address in reg_equiv_mem is already | |
6187 | invalid in the new mode; other cases would be fixed | |
6188 | by find_reloads_address as usual. | |
6189 | ||
6190 | ??? We attempt to handle such cases here by doing an | |
6191 | additional reload of the full address after the | |
6192 | usual processing by find_reloads_address. Note that | |
6193 | this may not work in the general case, but it seems | |
6194 | to cover the cases where this situation currently | |
6195 | occurs. A more general fix might be to reload the | |
6196 | *value* instead of the address, but this would not | |
6197 | be expected by the callers of this routine as-is. | |
6198 | ||
6199 | If find_reloads_address already completed replaced | |
6200 | the address, there is nothing further to do. */ | |
25fe2cca | 6201 | if (reloaded == 0 |
1c654ff1 | 6202 | && reg_equiv_mem (regno) != 0 |
bd1a81f7 | 6203 | && !strict_memory_address_addr_space_p |
1c654ff1 | 6204 | (GET_MODE (x), XEXP (reg_equiv_mem (regno), 0), |
6205 | MEM_ADDR_SPACE (reg_equiv_mem (regno)))) | |
b5fe590a | 6206 | { |
6207 | push_reload (XEXP (tem, 0), NULL_RTX, &XEXP (tem, 0), (rtx*) 0, | |
f8a8fc7b | 6208 | base_reg_class (GET_MODE (tem), |
6209 | MEM_ADDR_SPACE (tem), | |
6210 | MEM, SCRATCH), | |
b5fe590a | 6211 | GET_MODE (XEXP (tem, 0)), VOIDmode, 0, 0, |
6212 | opnum, type); | |
6213 | reloaded = 1; | |
6214 | } | |
37f7956e | 6215 | /* If this is not a toplevel operand, find_reloads doesn't see |
6216 | this substitution. We have to emit a USE of the pseudo so | |
6217 | that delete_output_reload can see it. */ | |
ed420a25 | 6218 | if (replace_reloads && recog_data.operand[opnum] != x) |
b2920130 | 6219 | /* We mark the USE with QImode so that we recognize it |
6220 | as one that can be safely deleted at the end of | |
6221 | reload. */ | |
6222 | PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, | |
6223 | SUBREG_REG (x)), | |
6224 | insn), QImode); | |
85afee82 | 6225 | x = tem; |
37f7956e | 6226 | } |
6227 | } | |
6228 | } | |
b5fe590a | 6229 | if (reloaded && address_reloaded) |
6230 | *address_reloaded = 1; | |
6231 | ||
37f7956e | 6232 | return x; |
6233 | } | |
6234 | \f | |
70457512 | 6235 | /* Substitute into the current INSN the registers into which we have reloaded |
42c63e4d | 6236 | the things that need reloading. The array `replacements' |
f2382343 | 6237 | contains the locations of all pointers that must be changed |
42c63e4d | 6238 | and says what to replace them with. |
6239 | ||
6240 | Return the rtx that X translates into; usually X, but modified. */ | |
6241 | ||
6242 | void | |
3ad4992f | 6243 | subst_reloads (rtx insn) |
42c63e4d | 6244 | { |
19cb6b50 | 6245 | int i; |
42c63e4d | 6246 | |
6247 | for (i = 0; i < n_replacements; i++) | |
6248 | { | |
19cb6b50 | 6249 | struct replacement *r = &replacements[i]; |
6250 | rtx reloadreg = rld[r->what].reg_rtx; | |
42c63e4d | 6251 | if (reloadreg) |
6252 | { | |
455ca9be | 6253 | #ifdef DEBUG_RELOAD |
6254 | /* This checking takes a very long time on some platforms | |
6255 | causing the gcc.c-torture/compile/limits-fnargs.c test | |
6256 | to time out during testing. See PR 31850. | |
6257 | ||
6258 | Internal consistency test. Check that we don't modify | |
f6ada591 | 6259 | anything in the equivalence arrays. Whenever something from |
6260 | those arrays needs to be reloaded, it must be unshared before | |
6261 | being substituted into; the equivalence must not be modified. | |
6262 | Otherwise, if the equivalence is used after that, it will | |
6263 | have been modified, and the thing substituted (probably a | |
6264 | register) is likely overwritten and not a usable equivalence. */ | |
6265 | int check_regno; | |
6266 | ||
6267 | for (check_regno = 0; check_regno < max_regno; check_regno++) | |
6268 | { | |
6269 | #define CHECK_MODF(ARRAY) \ | |
1c654ff1 | 6270 | gcc_assert (!VEC_index (reg_equivs_t, reg_equivs, check_regno).ARRAY \ |
04e579b6 | 6271 | || !loc_mentioned_in_p (r->where, \ |
1c654ff1 | 6272 | VEC_index (reg_equivs_t, reg_equivs, check_regno).ARRAY)) |
f6ada591 | 6273 | |
1c654ff1 | 6274 | CHECK_MODF (equiv_constant); |
6275 | CHECK_MODF (equiv_memory_loc); | |
6276 | CHECK_MODF (equiv_address); | |
6277 | CHECK_MODF (equiv_mem); | |
f6ada591 | 6278 | #undef CHECK_MODF |
6279 | } | |
455ca9be | 6280 | #endif /* DEBUG_RELOAD */ |
f6ada591 | 6281 | |
19d2fe05 | 6282 | /* If we're replacing a LABEL_REF with a register, there must |
6283 | already be an indication (to e.g. flow) which label this | |
d3ff0f75 | 6284 | register refers to. */ |
19d2fe05 | 6285 | gcc_assert (GET_CODE (*r->where) != LABEL_REF |
6286 | || !JUMP_P (insn) | |
6287 | || find_reg_note (insn, | |
6288 | REG_LABEL_OPERAND, | |
6289 | XEXP (*r->where, 0)) | |
6290 | || label_is_jump_target_p (XEXP (*r->where, 0), insn)); | |
d3ff0f75 | 6291 | |
42c63e4d | 6292 | /* Encapsulate RELOADREG so its machine mode matches what |
d971a7cf | 6293 | used to be there. Note that gen_lowpart_common will |
6294 | do the wrong thing if RELOADREG is multi-word. RELOADREG | |
6295 | will always be a REG here. */ | |
42c63e4d | 6296 | if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode) |
fd3ac62f | 6297 | reloadreg = reload_adjust_reg_for_mode (reloadreg, r->mode); |
42c63e4d | 6298 | |
41356f5a | 6299 | *r->where = reloadreg; |
42c63e4d | 6300 | } |
6301 | /* If reload got no reg and isn't optional, something's wrong. */ | |
04e579b6 | 6302 | else |
6303 | gcc_assert (rld[r->what].optional); | |
42c63e4d | 6304 | } |
6305 | } | |
6306 | \f | |
8e2f6d6b | 6307 | /* Make a copy of any replacements being done into X and move those |
6308 | copies to locations in Y, a copy of X. */ | |
42c63e4d | 6309 | |
6310 | void | |
3ad4992f | 6311 | copy_replacements (rtx x, rtx y) |
42c63e4d | 6312 | { |
8e2f6d6b | 6313 | copy_replacements_1 (&x, &y, n_replacements); |
6314 | } | |
6315 | ||
6316 | static void | |
3ad4992f | 6317 | copy_replacements_1 (rtx *px, rtx *py, int orig_replacements) |
8e2f6d6b | 6318 | { |
6319 | int i, j; | |
6320 | rtx x, y; | |
6321 | struct replacement *r; | |
6322 | enum rtx_code code; | |
6323 | const char *fmt; | |
6324 | ||
6325 | for (j = 0; j < orig_replacements; j++) | |
41356f5a | 6326 | if (replacements[j].where == px) |
6327 | { | |
6328 | r = &replacements[n_replacements++]; | |
6329 | r->where = py; | |
6330 | r->what = replacements[j].what; | |
6331 | r->mode = replacements[j].mode; | |
6332 | } | |
8e2f6d6b | 6333 | |
6334 | x = *px; | |
6335 | y = *py; | |
6336 | code = GET_CODE (x); | |
6337 | fmt = GET_RTX_FORMAT (code); | |
6338 | ||
6339 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6340 | { | |
6341 | if (fmt[i] == 'e') | |
6342 | copy_replacements_1 (&XEXP (x, i), &XEXP (y, i), orig_replacements); | |
6343 | else if (fmt[i] == 'E') | |
6344 | for (j = XVECLEN (x, i); --j >= 0; ) | |
6345 | copy_replacements_1 (&XVECEXP (x, i, j), &XVECEXP (y, i, j), | |
6346 | orig_replacements); | |
6347 | } | |
42c63e4d | 6348 | } |
f64bc32a | 6349 | |
45498ea1 | 6350 | /* Change any replacements being done to *X to be done to *Y. */ |
f64bc32a | 6351 | |
6352 | void | |
3ad4992f | 6353 | move_replacements (rtx *x, rtx *y) |
f64bc32a | 6354 | { |
6355 | int i; | |
6356 | ||
6357 | for (i = 0; i < n_replacements; i++) | |
41356f5a | 6358 | if (replacements[i].where == x) |
6359 | replacements[i].where = y; | |
f64bc32a | 6360 | } |
42c63e4d | 6361 | \f |
8a7a0a5a | 6362 | /* If LOC was scheduled to be replaced by something, return the replacement. |
6363 | Otherwise, return *LOC. */ | |
6364 | ||
6365 | rtx | |
3ad4992f | 6366 | find_replacement (rtx *loc) |
8a7a0a5a | 6367 | { |
6368 | struct replacement *r; | |
6369 | ||
6370 | for (r = &replacements[0]; r < &replacements[n_replacements]; r++) | |
6371 | { | |
48666d2c | 6372 | rtx reloadreg = rld[r->what].reg_rtx; |
8a7a0a5a | 6373 | |
6374 | if (reloadreg && r->where == loc) | |
6375 | { | |
6376 | if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode) | |
41356f5a | 6377 | reloadreg = reload_adjust_reg_for_mode (reloadreg, r->mode); |
8a7a0a5a | 6378 | |
6379 | return reloadreg; | |
6380 | } | |
41356f5a | 6381 | else if (reloadreg && GET_CODE (*loc) == SUBREG |
6382 | && r->where == &SUBREG_REG (*loc)) | |
8a7a0a5a | 6383 | { |
41356f5a | 6384 | if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode) |
6385 | reloadreg = reload_adjust_reg_for_mode (reloadreg, r->mode); | |
6386 | ||
6387 | return simplify_gen_subreg (GET_MODE (*loc), reloadreg, | |
6388 | GET_MODE (SUBREG_REG (*loc)), | |
6389 | SUBREG_BYTE (*loc)); | |
8a7a0a5a | 6390 | } |
6391 | } | |
6392 | ||
ad87de1e | 6393 | /* If *LOC is a PLUS, MINUS, or MULT, see if a replacement is scheduled for |
6394 | what's inside and make a new rtl if so. */ | |
6395 | if (GET_CODE (*loc) == PLUS || GET_CODE (*loc) == MINUS | |
6396 | || GET_CODE (*loc) == MULT) | |
6397 | { | |
6398 | rtx x = find_replacement (&XEXP (*loc, 0)); | |
6399 | rtx y = find_replacement (&XEXP (*loc, 1)); | |
6400 | ||
6401 | if (x != XEXP (*loc, 0) || y != XEXP (*loc, 1)) | |
941522d6 | 6402 | return gen_rtx_fmt_ee (GET_CODE (*loc), GET_MODE (*loc), x, y); |
ad87de1e | 6403 | } |
6404 | ||
8a7a0a5a | 6405 | return *loc; |
6406 | } | |
6407 | \f | |
42c63e4d | 6408 | /* Return nonzero if register in range [REGNO, ENDREGNO) |
6409 | appears either explicitly or implicitly in X | |
3e561fd5 | 6410 | other than being stored into (except for earlyclobber operands). |
42c63e4d | 6411 | |
6412 | References contained within the substructure at LOC do not count. | |
6413 | LOC may be zero, meaning don't ignore anything. | |
6414 | ||
6415 | This is similar to refers_to_regno_p in rtlanal.c except that we | |
6416 | look at equivalences for pseudos that didn't get hard registers. */ | |
6417 | ||
6e707336 | 6418 | static int |
3ad4992f | 6419 | refers_to_regno_for_reload_p (unsigned int regno, unsigned int endregno, |
6420 | rtx x, rtx *loc) | |
42c63e4d | 6421 | { |
02e7a332 | 6422 | int i; |
6423 | unsigned int r; | |
6424 | RTX_CODE code; | |
6425 | const char *fmt; | |
42c63e4d | 6426 | |
6427 | if (x == 0) | |
6428 | return 0; | |
6429 | ||
6430 | repeat: | |
6431 | code = GET_CODE (x); | |
6432 | ||
6433 | switch (code) | |
6434 | { | |
6435 | case REG: | |
02e7a332 | 6436 | r = REGNO (x); |
42c63e4d | 6437 | |
c548e550 | 6438 | /* If this is a pseudo, a hard register must not have been allocated. |
6439 | X must therefore either be a constant or be in memory. */ | |
02e7a332 | 6440 | if (r >= FIRST_PSEUDO_REGISTER) |
c548e550 | 6441 | { |
1c654ff1 | 6442 | if (reg_equiv_memory_loc (r)) |
c548e550 | 6443 | return refers_to_regno_for_reload_p (regno, endregno, |
1c654ff1 | 6444 | reg_equiv_memory_loc (r), |
33181afc | 6445 | (rtx*) 0); |
c548e550 | 6446 | |
1c654ff1 | 6447 | gcc_assert (reg_equiv_constant (r) || reg_equiv_invariant (r)); |
04e579b6 | 6448 | return 0; |
c548e550 | 6449 | } |
42c63e4d | 6450 | |
02e7a332 | 6451 | return (endregno > r |
6452 | && regno < r + (r < FIRST_PSEUDO_REGISTER | |
67d6c12b | 6453 | ? hard_regno_nregs[r][GET_MODE (x)] |
42c63e4d | 6454 | : 1)); |
6455 | ||
6456 | case SUBREG: | |
6457 | /* If this is a SUBREG of a hard reg, we can see exactly which | |
6458 | registers are being modified. Otherwise, handle normally. */ | |
8ad4c111 | 6459 | if (REG_P (SUBREG_REG (x)) |
42c63e4d | 6460 | && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) |
6461 | { | |
701e46d0 | 6462 | unsigned int inner_regno = subreg_regno (x); |
02e7a332 | 6463 | unsigned int inner_endregno |
aee171c8 | 6464 | = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER |
fe2ebfc8 | 6465 | ? subreg_nregs (x) : 1); |
42c63e4d | 6466 | |
6467 | return endregno > inner_regno && regno < inner_endregno; | |
6468 | } | |
6469 | break; | |
6470 | ||
6471 | case CLOBBER: | |
6472 | case SET: | |
6473 | if (&SET_DEST (x) != loc | |
6474 | /* Note setting a SUBREG counts as referring to the REG it is in for | |
6475 | a pseudo but not for hard registers since we can | |
6476 | treat each word individually. */ | |
6477 | && ((GET_CODE (SET_DEST (x)) == SUBREG | |
6478 | && loc != &SUBREG_REG (SET_DEST (x)) | |
8ad4c111 | 6479 | && REG_P (SUBREG_REG (SET_DEST (x))) |
42c63e4d | 6480 | && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER |
6481 | && refers_to_regno_for_reload_p (regno, endregno, | |
6482 | SUBREG_REG (SET_DEST (x)), | |
6483 | loc)) | |
b090827b | 6484 | /* If the output is an earlyclobber operand, this is |
3e561fd5 | 6485 | a conflict. */ |
8ad4c111 | 6486 | || ((!REG_P (SET_DEST (x)) |
3e561fd5 | 6487 | || earlyclobber_operand_p (SET_DEST (x))) |
42c63e4d | 6488 | && refers_to_regno_for_reload_p (regno, endregno, |
6489 | SET_DEST (x), loc)))) | |
6490 | return 1; | |
6491 | ||
6492 | if (code == CLOBBER || loc == &SET_SRC (x)) | |
6493 | return 0; | |
6494 | x = SET_SRC (x); | |
6495 | goto repeat; | |
5bb2f919 | 6496 | |
0dbd1c74 | 6497 | default: |
6498 | break; | |
42c63e4d | 6499 | } |
6500 | ||
6501 | /* X does not match, so try its subexpressions. */ | |
6502 | ||
6503 | fmt = GET_RTX_FORMAT (code); | |
6504 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6505 | { | |
6506 | if (fmt[i] == 'e' && loc != &XEXP (x, i)) | |
6507 | { | |
6508 | if (i == 0) | |
6509 | { | |
6510 | x = XEXP (x, 0); | |
6511 | goto repeat; | |
6512 | } | |
6513 | else | |
6514 | if (refers_to_regno_for_reload_p (regno, endregno, | |
6515 | XEXP (x, i), loc)) | |
6516 | return 1; | |
6517 | } | |
6518 | else if (fmt[i] == 'E') | |
6519 | { | |
19cb6b50 | 6520 | int j; |
67610d42 | 6521 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
42c63e4d | 6522 | if (loc != &XVECEXP (x, i, j) |
6523 | && refers_to_regno_for_reload_p (regno, endregno, | |
6524 | XVECEXP (x, i, j), loc)) | |
6525 | return 1; | |
6526 | } | |
6527 | } | |
6528 | return 0; | |
6529 | } | |
d3862ba2 | 6530 | |
6531 | /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG, | |
6532 | we check if any register number in X conflicts with the relevant register | |
6533 | numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN | |
6534 | contains a MEM (we don't bother checking for memory addresses that can't | |
5bb2f919 | 6535 | conflict because we expect this to be a rare case. |
d3862ba2 | 6536 | |
4822deca | 6537 | This function is similar to reg_overlap_mentioned_p in rtlanal.c except |
d3862ba2 | 6538 | that we look at equivalences for pseudos that didn't get hard registers. */ |
6539 | ||
6540 | int | |
3ad4992f | 6541 | reg_overlap_mentioned_for_reload_p (rtx x, rtx in) |
d3862ba2 | 6542 | { |
6543 | int regno, endregno; | |
6544 | ||
8eb7d6fc | 6545 | /* Overly conservative. */ |
57148e48 | 6546 | if (GET_CODE (x) == STRICT_LOW_PART |
6720e96c | 6547 | || GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC) |
8eb7d6fc | 6548 | x = XEXP (x, 0); |
6549 | ||
6550 | /* If either argument is a constant, then modifying X can not affect IN. */ | |
6551 | if (CONSTANT_P (x) || CONSTANT_P (in)) | |
6552 | return 0; | |
971ba038 | 6553 | else if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x))) |
f31ff3d8 | 6554 | return refers_to_mem_for_reload_p (in); |
8eb7d6fc | 6555 | else if (GET_CODE (x) == SUBREG) |
d3862ba2 | 6556 | { |
6557 | regno = REGNO (SUBREG_REG (x)); | |
6558 | if (regno < FIRST_PSEUDO_REGISTER) | |
701e46d0 | 6559 | regno += subreg_regno_offset (REGNO (SUBREG_REG (x)), |
6560 | GET_MODE (SUBREG_REG (x)), | |
6561 | SUBREG_BYTE (x), | |
6562 | GET_MODE (x)); | |
fe2ebfc8 | 6563 | endregno = regno + (regno < FIRST_PSEUDO_REGISTER |
6564 | ? subreg_nregs (x) : 1); | |
6565 | ||
6566 | return refers_to_regno_for_reload_p (regno, endregno, in, (rtx*) 0); | |
d3862ba2 | 6567 | } |
8ad4c111 | 6568 | else if (REG_P (x)) |
d3862ba2 | 6569 | { |
6570 | regno = REGNO (x); | |
c548e550 | 6571 | |
6572 | /* If this is a pseudo, it must not have been assigned a hard register. | |
6573 | Therefore, it must either be in memory or be a constant. */ | |
6574 | ||
6575 | if (regno >= FIRST_PSEUDO_REGISTER) | |
6576 | { | |
1c654ff1 | 6577 | if (reg_equiv_memory_loc (regno)) |
c548e550 | 6578 | return refers_to_mem_for_reload_p (in); |
1c654ff1 | 6579 | gcc_assert (reg_equiv_constant (regno)); |
04e579b6 | 6580 | return 0; |
c548e550 | 6581 | } |
fe2ebfc8 | 6582 | |
a2c6f0b7 | 6583 | endregno = END_HARD_REGNO (x); |
fe2ebfc8 | 6584 | |
6585 | return refers_to_regno_for_reload_p (regno, endregno, in, (rtx*) 0); | |
d3862ba2 | 6586 | } |
e16ceb8e | 6587 | else if (MEM_P (x)) |
c548e550 | 6588 | return refers_to_mem_for_reload_p (in); |
d3862ba2 | 6589 | else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC |
6590 | || GET_CODE (x) == CC0) | |
6591 | return reg_mentioned_p (x, in); | |
48e1416a | 6592 | else |
821e1d0d | 6593 | { |
04e579b6 | 6594 | gcc_assert (GET_CODE (x) == PLUS); |
6595 | ||
821e1d0d | 6596 | /* We actually want to know if X is mentioned somewhere inside IN. |
6597 | We must not say that (plus (sp) (const_int 124)) is in | |
6598 | (plus (sp) (const_int 64)), since that can lead to incorrect reload | |
6599 | allocation when spuriously changing a RELOAD_FOR_OUTPUT_ADDRESS | |
6600 | into a RELOAD_OTHER on behalf of another RELOAD_OTHER. */ | |
e16ceb8e | 6601 | while (MEM_P (in)) |
821e1d0d | 6602 | in = XEXP (in, 0); |
8ad4c111 | 6603 | if (REG_P (in)) |
821e1d0d | 6604 | return 0; |
6605 | else if (GET_CODE (in) == PLUS) | |
1121ac6f | 6606 | return (rtx_equal_p (x, in) |
6607 | || reg_overlap_mentioned_for_reload_p (x, XEXP (in, 0)) | |
821e1d0d | 6608 | || reg_overlap_mentioned_for_reload_p (x, XEXP (in, 1))); |
6609 | else return (reg_overlap_mentioned_for_reload_p (XEXP (x, 0), in) | |
6610 | || reg_overlap_mentioned_for_reload_p (XEXP (x, 1), in)); | |
6611 | } | |
d3862ba2 | 6612 | |
fe2ebfc8 | 6613 | gcc_unreachable (); |
d3862ba2 | 6614 | } |
c548e550 | 6615 | |
6616 | /* Return nonzero if anything in X contains a MEM. Look also for pseudo | |
6617 | registers. */ | |
6618 | ||
6e707336 | 6619 | static int |
3ad4992f | 6620 | refers_to_mem_for_reload_p (rtx x) |
c548e550 | 6621 | { |
d2ca078f | 6622 | const char *fmt; |
c548e550 | 6623 | int i; |
6624 | ||
e16ceb8e | 6625 | if (MEM_P (x)) |
c548e550 | 6626 | return 1; |
6627 | ||
8ad4c111 | 6628 | if (REG_P (x)) |
c548e550 | 6629 | return (REGNO (x) >= FIRST_PSEUDO_REGISTER |
1c654ff1 | 6630 | && reg_equiv_memory_loc (REGNO (x))); |
5bb2f919 | 6631 | |
c548e550 | 6632 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
6633 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
6634 | if (fmt[i] == 'e' | |
e16ceb8e | 6635 | && (MEM_P (XEXP (x, i)) |
c548e550 | 6636 | || refers_to_mem_for_reload_p (XEXP (x, i)))) |
6637 | return 1; | |
5bb2f919 | 6638 | |
c548e550 | 6639 | return 0; |
6640 | } | |
42c63e4d | 6641 | \f |
42c63e4d | 6642 | /* Check the insns before INSN to see if there is a suitable register |
6643 | containing the same value as GOAL. | |
47cfb7f4 | 6644 | If OTHER is -1, look for a register in class RCLASS. |
42c63e4d | 6645 | Otherwise, just see if register number OTHER shares GOAL's value. |
6646 | ||
6647 | Return an rtx for the register found, or zero if none is found. | |
6648 | ||
6649 | If RELOAD_REG_P is (short *)1, | |
6650 | we reject any hard reg that appears in reload_reg_rtx | |
6651 | because such a hard reg is also needed coming into this insn. | |
6652 | ||
6653 | If RELOAD_REG_P is any other nonzero value, | |
6654 | it is a vector indexed by hard reg number | |
6655 | and we reject any hard reg whose element in the vector is nonnegative | |
6656 | as well as any that appears in reload_reg_rtx. | |
6657 | ||
6658 | If GOAL is zero, then GOALREG is a register number; we look | |
6659 | for an equivalent for that register. | |
6660 | ||
6661 | MODE is the machine mode of the value we want an equivalence for. | |
6662 | If GOAL is nonzero and not VOIDmode, then it must have mode MODE. | |
6663 | ||
6664 | This function is used by jump.c as well as in the reload pass. | |
6665 | ||
6666 | If GOAL is the sum of the stack pointer and a constant, we treat it | |
6667 | as if it were a constant except that sp is required to be unchanging. */ | |
6668 | ||
6669 | rtx | |
47cfb7f4 | 6670 | find_equiv_reg (rtx goal, rtx insn, enum reg_class rclass, int other, |
3ad4992f | 6671 | short *reload_reg_p, int goalreg, enum machine_mode mode) |
42c63e4d | 6672 | { |
19cb6b50 | 6673 | rtx p = insn; |
1fbf42c7 | 6674 | rtx goaltry, valtry, value, where; |
19cb6b50 | 6675 | rtx pat; |
6676 | int regno = -1; | |
42c63e4d | 6677 | int valueno; |
6678 | int goal_mem = 0; | |
6679 | int goal_const = 0; | |
6680 | int goal_mem_addr_varies = 0; | |
6681 | int need_stable_sp = 0; | |
6682 | int nregs; | |
6683 | int valuenregs; | |
c15bc0ce | 6684 | int num = 0; |
42c63e4d | 6685 | |
6686 | if (goal == 0) | |
6687 | regno = goalreg; | |
8ad4c111 | 6688 | else if (REG_P (goal)) |
42c63e4d | 6689 | regno = REGNO (goal); |
e16ceb8e | 6690 | else if (MEM_P (goal)) |
42c63e4d | 6691 | { |
6692 | enum rtx_code code = GET_CODE (XEXP (goal, 0)); | |
6693 | if (MEM_VOLATILE_P (goal)) | |
6694 | return 0; | |
cee7491d | 6695 | if (flag_float_store && SCALAR_FLOAT_MODE_P (GET_MODE (goal))) |
42c63e4d | 6696 | return 0; |
6697 | /* An address with side effects must be reexecuted. */ | |
6698 | switch (code) | |
6699 | { | |
6700 | case POST_INC: | |
6701 | case PRE_INC: | |
6702 | case POST_DEC: | |
6703 | case PRE_DEC: | |
40988080 | 6704 | case POST_MODIFY: |
6705 | case PRE_MODIFY: | |
42c63e4d | 6706 | return 0; |
0dbd1c74 | 6707 | default: |
6708 | break; | |
42c63e4d | 6709 | } |
6710 | goal_mem = 1; | |
6711 | } | |
6712 | else if (CONSTANT_P (goal)) | |
6713 | goal_const = 1; | |
6714 | else if (GET_CODE (goal) == PLUS | |
6715 | && XEXP (goal, 0) == stack_pointer_rtx | |
6716 | && CONSTANT_P (XEXP (goal, 1))) | |
6717 | goal_const = need_stable_sp = 1; | |
c988df6a | 6718 | else if (GET_CODE (goal) == PLUS |
6719 | && XEXP (goal, 0) == frame_pointer_rtx | |
6720 | && CONSTANT_P (XEXP (goal, 1))) | |
6721 | goal_const = 1; | |
42c63e4d | 6722 | else |
6723 | return 0; | |
6724 | ||
c15bc0ce | 6725 | num = 0; |
42c63e4d | 6726 | /* Scan insns back from INSN, looking for one that copies |
6727 | a value into or out of GOAL. | |
6728 | Stop and give up if we reach a label. */ | |
6729 | ||
6730 | while (1) | |
6731 | { | |
6732 | p = PREV_INSN (p); | |
9845d120 | 6733 | if (p && DEBUG_INSN_P (p)) |
6734 | continue; | |
c15bc0ce | 6735 | num++; |
6d7dc5b9 | 6736 | if (p == 0 || LABEL_P (p) |
c15bc0ce | 6737 | || num > PARAM_VALUE (PARAM_MAX_RELOAD_SEARCH_INSNS)) |
42c63e4d | 6738 | return 0; |
02e7a332 | 6739 | |
fd7a154d | 6740 | /* Don't reuse register contents from before a setjmp-type |
6741 | function call; on the second return (from the longjmp) it | |
6742 | might have been clobbered by a later reuse. It doesn't | |
6743 | seem worthwhile to actually go and see if it is actually | |
6744 | reused even if that information would be readily available; | |
6745 | just don't reuse it across the setjmp call. */ | |
6746 | if (CALL_P (p) && find_reg_note (p, REG_SETJMP, NULL_RTX)) | |
6747 | return 0; | |
6748 | ||
6d7dc5b9 | 6749 | if (NONJUMP_INSN_P (p) |
a92771b8 | 6750 | /* If we don't want spill regs ... */ |
70457512 | 6751 | && (! (reload_reg_p != 0 |
6752 | && reload_reg_p != (short *) (HOST_WIDE_INT) 1) | |
02e7a332 | 6753 | /* ... then ignore insns introduced by reload; they aren't |
6754 | useful and can cause results in reload_as_needed to be | |
6755 | different from what they were when calculating the need for | |
6756 | spills. If we notice an input-reload insn here, we will | |
6757 | reject it below, but it might hide a usable equivalent. | |
1fa3a8f6 | 6758 | That makes bad code. It may even fail: perhaps no reg was |
02e7a332 | 6759 | spilled for this insn because it was assumed we would find |
6760 | that equivalent. */ | |
42c63e4d | 6761 | || INSN_UID (p) < reload_first_uid)) |
6762 | { | |
f22495be | 6763 | rtx tem; |
42c63e4d | 6764 | pat = single_set (p); |
02e7a332 | 6765 | |
42c63e4d | 6766 | /* First check for something that sets some reg equal to GOAL. */ |
6767 | if (pat != 0 | |
6768 | && ((regno >= 0 | |
6769 | && true_regnum (SET_SRC (pat)) == regno | |
6770 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
6771 | || | |
6772 | (regno >= 0 | |
6773 | && true_regnum (SET_DEST (pat)) == regno | |
6774 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0) | |
6775 | || | |
6776 | (goal_const && rtx_equal_p (SET_SRC (pat), goal) | |
c9814adb | 6777 | /* When looking for stack pointer + const, |
6778 | make sure we don't use a stack adjust. */ | |
6779 | && !reg_overlap_mentioned_for_reload_p (SET_DEST (pat), goal) | |
42c63e4d | 6780 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) |
6781 | || (goal_mem | |
6782 | && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0 | |
6783 | && rtx_renumbered_equal_p (goal, SET_SRC (pat))) | |
6784 | || (goal_mem | |
6785 | && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0 | |
f22495be | 6786 | && rtx_renumbered_equal_p (goal, SET_DEST (pat))) |
6787 | /* If we are looking for a constant, | |
6788 | and something equivalent to that constant was copied | |
6789 | into a reg, we can use that reg. */ | |
d6cb6164 | 6790 | || (goal_const && REG_NOTES (p) != 0 |
6791 | && (tem = find_reg_note (p, REG_EQUIV, NULL_RTX)) | |
6792 | && ((rtx_equal_p (XEXP (tem, 0), goal) | |
6793 | && (valueno | |
6794 | = true_regnum (valtry = SET_DEST (pat))) >= 0) | |
8ad4c111 | 6795 | || (REG_P (SET_DEST (pat)) |
d6cb6164 | 6796 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE |
cee7491d | 6797 | && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0))) |
971ba038 | 6798 | && CONST_INT_P (goal) |
d6cb6164 | 6799 | && 0 != (goaltry |
6800 | = operand_subword (XEXP (tem, 0), 0, 0, | |
1fbf42c7 | 6801 | VOIDmode)) |
d6cb6164 | 6802 | && rtx_equal_p (goal, goaltry) |
6803 | && (valtry | |
6804 | = operand_subword (SET_DEST (pat), 0, 0, | |
6805 | VOIDmode)) | |
6806 | && (valueno = true_regnum (valtry)) >= 0))) | |
e5fdd564 | 6807 | || (goal_const && (tem = find_reg_note (p, REG_EQUIV, |
6808 | NULL_RTX)) | |
8ad4c111 | 6809 | && REG_P (SET_DEST (pat)) |
f22495be | 6810 | && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE |
cee7491d | 6811 | && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0))) |
971ba038 | 6812 | && CONST_INT_P (goal) |
1fbf42c7 | 6813 | && 0 != (goaltry = operand_subword (XEXP (tem, 0), 1, 0, |
6814 | VOIDmode)) | |
6815 | && rtx_equal_p (goal, goaltry) | |
f22495be | 6816 | && (valtry |
6817 | = operand_subword (SET_DEST (pat), 1, 0, VOIDmode)) | |
03604f92 | 6818 | && (valueno = true_regnum (valtry)) >= 0))) |
066034a1 | 6819 | { |
6820 | if (other >= 0) | |
6821 | { | |
6822 | if (valueno != other) | |
6823 | continue; | |
6824 | } | |
6825 | else if ((unsigned) valueno >= FIRST_PSEUDO_REGISTER) | |
6826 | continue; | |
47cfb7f4 | 6827 | else if (!in_hard_reg_set_p (reg_class_contents[(int) rclass], |
a2c6f0b7 | 6828 | mode, valueno)) |
6829 | continue; | |
066034a1 | 6830 | value = valtry; |
6831 | where = p; | |
6832 | break; | |
6833 | } | |
42c63e4d | 6834 | } |
6835 | } | |
6836 | ||
6837 | /* We found a previous insn copying GOAL into a suitable other reg VALUE | |
6838 | (or copying VALUE into GOAL, if GOAL is also a register). | |
6839 | Now verify that VALUE is really valid. */ | |
6840 | ||
6841 | /* VALUENO is the register number of VALUE; a hard register. */ | |
6842 | ||
6843 | /* Don't try to re-use something that is killed in this insn. We want | |
6844 | to be able to trust REG_UNUSED notes. */ | |
d6cb6164 | 6845 | if (REG_NOTES (where) != 0 && find_reg_note (where, REG_UNUSED, value)) |
42c63e4d | 6846 | return 0; |
6847 | ||
6848 | /* If we propose to get the value from the stack pointer or if GOAL is | |
6849 | a MEM based on the stack pointer, we need a stable SP. */ | |
d8e97895 | 6850 | if (valueno == STACK_POINTER_REGNUM || regno == STACK_POINTER_REGNUM |
d3862ba2 | 6851 | || (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx, |
6852 | goal))) | |
42c63e4d | 6853 | need_stable_sp = 1; |
6854 | ||
6855 | /* Reject VALUE if the copy-insn moved the wrong sort of datum. */ | |
6856 | if (GET_MODE (value) != mode) | |
6857 | return 0; | |
6858 | ||
6859 | /* Reject VALUE if it was loaded from GOAL | |
6860 | and is also a register that appears in the address of GOAL. */ | |
6861 | ||
5aee73e6 | 6862 | if (goal_mem && value == SET_DEST (single_set (where)) |
a2c6f0b7 | 6863 | && refers_to_regno_for_reload_p (valueno, end_hard_regno (mode, valueno), |
33181afc | 6864 | goal, (rtx*) 0)) |
42c63e4d | 6865 | return 0; |
6866 | ||
6867 | /* Reject registers that overlap GOAL. */ | |
6868 | ||
67d6c12b | 6869 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER) |
6870 | nregs = hard_regno_nregs[regno][mode]; | |
6871 | else | |
6872 | nregs = 1; | |
6873 | valuenregs = hard_regno_nregs[valueno][mode]; | |
54741f4a | 6874 | |
900c3c49 | 6875 | if (!goal_mem && !goal_const |
6876 | && regno + nregs > valueno && regno < valueno + valuenregs) | |
6877 | return 0; | |
6878 | ||
42c63e4d | 6879 | /* Reject VALUE if it is one of the regs reserved for reloads. |
6880 | Reload1 knows how to reuse them anyway, and it would get | |
6881 | confused if we allocated one without its knowledge. | |
6882 | (Now that insns introduced by reload are ignored above, | |
6883 | this case shouldn't happen, but I'm not positive.) */ | |
6884 | ||
54741f4a | 6885 | if (reload_reg_p != 0 && reload_reg_p != (short *) (HOST_WIDE_INT) 1) |
6886 | { | |
6887 | int i; | |
6888 | for (i = 0; i < valuenregs; ++i) | |
6889 | if (reload_reg_p[valueno + i] >= 0) | |
6890 | return 0; | |
6891 | } | |
42c63e4d | 6892 | |
6893 | /* Reject VALUE if it is a register being used for an input reload | |
6894 | even if it is not one of those reserved. */ | |
6895 | ||
6896 | if (reload_reg_p != 0) | |
6897 | { | |
6898 | int i; | |
6899 | for (i = 0; i < n_reloads; i++) | |
48666d2c | 6900 | if (rld[i].reg_rtx != 0 && rld[i].in) |
42c63e4d | 6901 | { |
48666d2c | 6902 | int regno1 = REGNO (rld[i].reg_rtx); |
67d6c12b | 6903 | int nregs1 = hard_regno_nregs[regno1] |
6904 | [GET_MODE (rld[i].reg_rtx)]; | |
42c63e4d | 6905 | if (regno1 < valueno + valuenregs |
6906 | && regno1 + nregs1 > valueno) | |
6907 | return 0; | |
6908 | } | |
6909 | } | |
6910 | ||
6911 | if (goal_mem) | |
f7f0a0c6 | 6912 | /* We must treat frame pointer as varying here, |
6913 | since it can vary--in a nonlocal goto as generated by expand_goto. */ | |
6914 | goal_mem_addr_varies = !CONSTANT_ADDRESS_P (XEXP (goal, 0)); | |
42c63e4d | 6915 | |
6916 | /* Now verify that the values of GOAL and VALUE remain unaltered | |
6917 | until INSN is reached. */ | |
6918 | ||
6919 | p = insn; | |
6920 | while (1) | |
6921 | { | |
6922 | p = PREV_INSN (p); | |
6923 | if (p == where) | |
6924 | return value; | |
6925 | ||
6926 | /* Don't trust the conversion past a function call | |
6927 | if either of the two is in a call-clobbered register, or memory. */ | |
6d7dc5b9 | 6928 | if (CALL_P (p)) |
517c712f | 6929 | { |
6930 | int i; | |
67610d42 | 6931 | |
517c712f | 6932 | if (goal_mem || need_stable_sp) |
6933 | return 0; | |
67610d42 | 6934 | |
517c712f | 6935 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER) |
6936 | for (i = 0; i < nregs; ++i) | |
154bfd13 | 6937 | if (call_used_regs[regno + i] |
6938 | || HARD_REGNO_CALL_PART_CLOBBERED (regno + i, mode)) | |
517c712f | 6939 | return 0; |
6940 | ||
6941 | if (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER) | |
6942 | for (i = 0; i < valuenregs; ++i) | |
154bfd13 | 6943 | if (call_used_regs[valueno + i] |
6944 | || HARD_REGNO_CALL_PART_CLOBBERED (valueno + i, mode)) | |
517c712f | 6945 | return 0; |
9239aee6 | 6946 | } |
99ea4b55 | 6947 | |
9204e736 | 6948 | if (INSN_P (p)) |
42c63e4d | 6949 | { |
e5da2403 | 6950 | pat = PATTERN (p); |
6951 | ||
5bb2f919 | 6952 | /* Watch out for unspec_volatile, and volatile asms. */ |
6953 | if (volatile_insn_p (pat)) | |
e5da2403 | 6954 | return 0; |
6955 | ||
42c63e4d | 6956 | /* If this insn P stores in either GOAL or VALUE, return 0. |
6957 | If GOAL is a memory ref and this insn writes memory, return 0. | |
6958 | If GOAL is a memory ref and its address is not constant, | |
6959 | and this insn P changes a register used in GOAL, return 0. */ | |
6960 | ||
406034fa | 6961 | if (GET_CODE (pat) == COND_EXEC) |
6962 | pat = COND_EXEC_CODE (pat); | |
42c63e4d | 6963 | if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER) |
6964 | { | |
19cb6b50 | 6965 | rtx dest = SET_DEST (pat); |
42c63e4d | 6966 | while (GET_CODE (dest) == SUBREG |
6967 | || GET_CODE (dest) == ZERO_EXTRACT | |
42c63e4d | 6968 | || GET_CODE (dest) == STRICT_LOW_PART) |
6969 | dest = XEXP (dest, 0); | |
8ad4c111 | 6970 | if (REG_P (dest)) |
42c63e4d | 6971 | { |
19cb6b50 | 6972 | int xregno = REGNO (dest); |
42c63e4d | 6973 | int xnregs; |
6974 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
67d6c12b | 6975 | xnregs = hard_regno_nregs[xregno][GET_MODE (dest)]; |
42c63e4d | 6976 | else |
6977 | xnregs = 1; | |
6978 | if (xregno < regno + nregs && xregno + xnregs > regno) | |
6979 | return 0; | |
6980 | if (xregno < valueno + valuenregs | |
6981 | && xregno + xnregs > valueno) | |
6982 | return 0; | |
6983 | if (goal_mem_addr_varies | |
d3862ba2 | 6984 | && reg_overlap_mentioned_for_reload_p (dest, goal)) |
42c63e4d | 6985 | return 0; |
e43114ec | 6986 | if (xregno == STACK_POINTER_REGNUM && need_stable_sp) |
6987 | return 0; | |
42c63e4d | 6988 | } |
e16ceb8e | 6989 | else if (goal_mem && MEM_P (dest) |
42c63e4d | 6990 | && ! push_operand (dest, GET_MODE (dest))) |
6991 | return 0; | |
e16ceb8e | 6992 | else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER |
1c654ff1 | 6993 | && reg_equiv_memory_loc (regno) != 0) |
4c0fba30 | 6994 | return 0; |
42c63e4d | 6995 | else if (need_stable_sp && push_operand (dest, GET_MODE (dest))) |
6996 | return 0; | |
6997 | } | |
6998 | else if (GET_CODE (pat) == PARALLEL) | |
6999 | { | |
19cb6b50 | 7000 | int i; |
42c63e4d | 7001 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) |
7002 | { | |
19cb6b50 | 7003 | rtx v1 = XVECEXP (pat, 0, i); |
406034fa | 7004 | if (GET_CODE (v1) == COND_EXEC) |
7005 | v1 = COND_EXEC_CODE (v1); | |
42c63e4d | 7006 | if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER) |
7007 | { | |
19cb6b50 | 7008 | rtx dest = SET_DEST (v1); |
42c63e4d | 7009 | while (GET_CODE (dest) == SUBREG |
7010 | || GET_CODE (dest) == ZERO_EXTRACT | |
42c63e4d | 7011 | || GET_CODE (dest) == STRICT_LOW_PART) |
7012 | dest = XEXP (dest, 0); | |
8ad4c111 | 7013 | if (REG_P (dest)) |
42c63e4d | 7014 | { |
19cb6b50 | 7015 | int xregno = REGNO (dest); |
42c63e4d | 7016 | int xnregs; |
7017 | if (REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
67d6c12b | 7018 | xnregs = hard_regno_nregs[xregno][GET_MODE (dest)]; |
42c63e4d | 7019 | else |
7020 | xnregs = 1; | |
7021 | if (xregno < regno + nregs | |
7022 | && xregno + xnregs > regno) | |
7023 | return 0; | |
7024 | if (xregno < valueno + valuenregs | |
7025 | && xregno + xnregs > valueno) | |
7026 | return 0; | |
7027 | if (goal_mem_addr_varies | |
d3862ba2 | 7028 | && reg_overlap_mentioned_for_reload_p (dest, |
7029 | goal)) | |
42c63e4d | 7030 | return 0; |
a7657823 | 7031 | if (xregno == STACK_POINTER_REGNUM && need_stable_sp) |
7032 | return 0; | |
42c63e4d | 7033 | } |
e16ceb8e | 7034 | else if (goal_mem && MEM_P (dest) |
42c63e4d | 7035 | && ! push_operand (dest, GET_MODE (dest))) |
7036 | return 0; | |
e16ceb8e | 7037 | else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER |
1c654ff1 | 7038 | && reg_equiv_memory_loc (regno) != 0) |
0dbd1c74 | 7039 | return 0; |
99b6f742 | 7040 | else if (need_stable_sp |
7041 | && push_operand (dest, GET_MODE (dest))) | |
7042 | return 0; | |
7043 | } | |
7044 | } | |
7045 | } | |
7046 | ||
6d7dc5b9 | 7047 | if (CALL_P (p) && CALL_INSN_FUNCTION_USAGE (p)) |
99b6f742 | 7048 | { |
7049 | rtx link; | |
7050 | ||
7051 | for (link = CALL_INSN_FUNCTION_USAGE (p); XEXP (link, 1) != 0; | |
7052 | link = XEXP (link, 1)) | |
7053 | { | |
7054 | pat = XEXP (link, 0); | |
7055 | if (GET_CODE (pat) == CLOBBER) | |
7056 | { | |
19cb6b50 | 7057 | rtx dest = SET_DEST (pat); |
38219f2f | 7058 | |
8ad4c111 | 7059 | if (REG_P (dest)) |
99b6f742 | 7060 | { |
19cb6b50 | 7061 | int xregno = REGNO (dest); |
38219f2f | 7062 | int xnregs |
67d6c12b | 7063 | = hard_regno_nregs[xregno][GET_MODE (dest)]; |
38219f2f | 7064 | |
99b6f742 | 7065 | if (xregno < regno + nregs |
7066 | && xregno + xnregs > regno) | |
7067 | return 0; | |
38219f2f | 7068 | else if (xregno < valueno + valuenregs |
67610d42 | 7069 | && xregno + xnregs > valueno) |
99b6f742 | 7070 | return 0; |
38219f2f | 7071 | else if (goal_mem_addr_varies |
7072 | && reg_overlap_mentioned_for_reload_p (dest, | |
99b6f742 | 7073 | goal)) |
7074 | return 0; | |
7075 | } | |
38219f2f | 7076 | |
e16ceb8e | 7077 | else if (goal_mem && MEM_P (dest) |
99b6f742 | 7078 | && ! push_operand (dest, GET_MODE (dest))) |
7079 | return 0; | |
42c63e4d | 7080 | else if (need_stable_sp |
7081 | && push_operand (dest, GET_MODE (dest))) | |
7082 | return 0; | |
7083 | } | |
7084 | } | |
7085 | } | |
7086 | ||
7087 | #ifdef AUTO_INC_DEC | |
7088 | /* If this insn auto-increments or auto-decrements | |
7089 | either regno or valueno, return 0 now. | |
7090 | If GOAL is a memory ref and its address is not constant, | |
7091 | and this insn P increments a register used in GOAL, return 0. */ | |
7092 | { | |
19cb6b50 | 7093 | rtx link; |
42c63e4d | 7094 | |
7095 | for (link = REG_NOTES (p); link; link = XEXP (link, 1)) | |
7096 | if (REG_NOTE_KIND (link) == REG_INC | |
8ad4c111 | 7097 | && REG_P (XEXP (link, 0))) |
42c63e4d | 7098 | { |
19cb6b50 | 7099 | int incno = REGNO (XEXP (link, 0)); |
42c63e4d | 7100 | if (incno < regno + nregs && incno >= regno) |
7101 | return 0; | |
7102 | if (incno < valueno + valuenregs && incno >= valueno) | |
7103 | return 0; | |
7104 | if (goal_mem_addr_varies | |
d3862ba2 | 7105 | && reg_overlap_mentioned_for_reload_p (XEXP (link, 0), |
7106 | goal)) | |
42c63e4d | 7107 | return 0; |
7108 | } | |
7109 | } | |
7110 | #endif | |
7111 | } | |
7112 | } | |
7113 | } | |
7114 | \f | |
7115 | /* Find a place where INCED appears in an increment or decrement operator | |
7116 | within X, and return the amount INCED is incremented or decremented by. | |
7117 | The value is always positive. */ | |
7118 | ||
7119 | static int | |
3ad4992f | 7120 | find_inc_amount (rtx x, rtx inced) |
42c63e4d | 7121 | { |
19cb6b50 | 7122 | enum rtx_code code = GET_CODE (x); |
7123 | const char *fmt; | |
7124 | int i; | |
42c63e4d | 7125 | |
7126 | if (code == MEM) | |
7127 | { | |
19cb6b50 | 7128 | rtx addr = XEXP (x, 0); |
42c63e4d | 7129 | if ((GET_CODE (addr) == PRE_DEC |
7130 | || GET_CODE (addr) == POST_DEC | |
7131 | || GET_CODE (addr) == PRE_INC | |
7132 | || GET_CODE (addr) == POST_INC) | |
7133 | && XEXP (addr, 0) == inced) | |
7134 | return GET_MODE_SIZE (GET_MODE (x)); | |
40988080 | 7135 | else if ((GET_CODE (addr) == PRE_MODIFY |
7136 | || GET_CODE (addr) == POST_MODIFY) | |
7137 | && GET_CODE (XEXP (addr, 1)) == PLUS | |
7138 | && XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0) | |
7139 | && XEXP (addr, 0) == inced | |
971ba038 | 7140 | && CONST_INT_P (XEXP (XEXP (addr, 1), 1))) |
67610d42 | 7141 | { |
7142 | i = INTVAL (XEXP (XEXP (addr, 1), 1)); | |
7143 | return i < 0 ? -i : i; | |
7144 | } | |
7145 | } | |
42c63e4d | 7146 | |
7147 | fmt = GET_RTX_FORMAT (code); | |
7148 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7149 | { | |
7150 | if (fmt[i] == 'e') | |
7151 | { | |
19cb6b50 | 7152 | int tem = find_inc_amount (XEXP (x, i), inced); |
42c63e4d | 7153 | if (tem != 0) |
7154 | return tem; | |
7155 | } | |
7156 | if (fmt[i] == 'E') | |
7157 | { | |
19cb6b50 | 7158 | int j; |
42c63e4d | 7159 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
7160 | { | |
19cb6b50 | 7161 | int tem = find_inc_amount (XVECEXP (x, i, j), inced); |
42c63e4d | 7162 | if (tem != 0) |
7163 | return tem; | |
7164 | } | |
7165 | } | |
7166 | } | |
7167 | ||
7168 | return 0; | |
7169 | } | |
7170 | \f | |
a80cd853 | 7171 | /* Return 1 if registers from REGNO to ENDREGNO are the subjects of a |
7172 | REG_INC note in insn INSN. REGNO must refer to a hard register. */ | |
7173 | ||
7174 | #ifdef AUTO_INC_DEC | |
48e1416a | 7175 | static int |
a80cd853 | 7176 | reg_inc_found_and_valid_p (unsigned int regno, unsigned int endregno, |
7177 | rtx insn) | |
7178 | { | |
7179 | rtx link; | |
7180 | ||
7181 | gcc_assert (insn); | |
7182 | ||
7183 | if (! INSN_P (insn)) | |
7184 | return 0; | |
48e1416a | 7185 | |
a80cd853 | 7186 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
7187 | if (REG_NOTE_KIND (link) == REG_INC) | |
7188 | { | |
7189 | unsigned int test = (int) REGNO (XEXP (link, 0)); | |
7190 | if (test >= regno && test < endregno) | |
48e1416a | 7191 | return 1; |
a80cd853 | 7192 | } |
7193 | return 0; | |
7194 | } | |
7195 | #else | |
7196 | ||
7197 | #define reg_inc_found_and_valid_p(regno,endregno,insn) 0 | |
7198 | ||
48e1416a | 7199 | #endif |
a80cd853 | 7200 | |
ab7883ae | 7201 | /* Return 1 if register REGNO is the subject of a clobber in insn INSN. |
a80cd853 | 7202 | If SETS is 1, also consider SETs. If SETS is 2, enable checking |
7203 | REG_INC. REGNO must refer to a hard register. */ | |
42c63e4d | 7204 | |
7205 | int | |
3ad4992f | 7206 | regno_clobbered_p (unsigned int regno, rtx insn, enum machine_mode mode, |
7207 | int sets) | |
42c63e4d | 7208 | { |
3b1e12de | 7209 | unsigned int nregs, endregno; |
7210 | ||
7211 | /* regno must be a hard register. */ | |
7212 | gcc_assert (regno < FIRST_PSEUDO_REGISTER); | |
7213 | ||
7214 | nregs = hard_regno_nregs[regno][mode]; | |
7215 | endregno = regno + nregs; | |
0d40c9f5 | 7216 | |
ab7883ae | 7217 | if ((GET_CODE (PATTERN (insn)) == CLOBBER |
a80cd853 | 7218 | || (sets == 1 && GET_CODE (PATTERN (insn)) == SET)) |
8ad4c111 | 7219 | && REG_P (XEXP (PATTERN (insn), 0))) |
0d40c9f5 | 7220 | { |
97b330ca | 7221 | unsigned int test = REGNO (XEXP (PATTERN (insn), 0)); |
0d40c9f5 | 7222 | |
9a86bc1b | 7223 | return test >= regno && test < endregno; |
0d40c9f5 | 7224 | } |
42c63e4d | 7225 | |
a80cd853 | 7226 | if (sets == 2 && reg_inc_found_and_valid_p (regno, endregno, insn)) |
48e1416a | 7227 | return 1; |
7228 | ||
42c63e4d | 7229 | if (GET_CODE (PATTERN (insn)) == PARALLEL) |
7230 | { | |
7231 | int i = XVECLEN (PATTERN (insn), 0) - 1; | |
7232 | ||
7233 | for (; i >= 0; i--) | |
7234 | { | |
7235 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
ab7883ae | 7236 | if ((GET_CODE (elt) == CLOBBER |
3ea04b3a | 7237 | || (sets == 1 && GET_CODE (elt) == SET)) |
8ad4c111 | 7238 | && REG_P (XEXP (elt, 0))) |
0d40c9f5 | 7239 | { |
97b330ca | 7240 | unsigned int test = REGNO (XEXP (elt, 0)); |
2617fe26 | 7241 | |
9a86bc1b | 7242 | if (test >= regno && test < endregno) |
0d40c9f5 | 7243 | return 1; |
7244 | } | |
a80cd853 | 7245 | if (sets == 2 |
7246 | && reg_inc_found_and_valid_p (regno, endregno, elt)) | |
48e1416a | 7247 | return 1; |
42c63e4d | 7248 | } |
7249 | } | |
7250 | ||
7251 | return 0; | |
7252 | } | |
00e753ce | 7253 | |
fd3ac62f | 7254 | /* Find the low part, with mode MODE, of a hard regno RELOADREG. */ |
7255 | rtx | |
3ad4992f | 7256 | reload_adjust_reg_for_mode (rtx reloadreg, enum machine_mode mode) |
fd3ac62f | 7257 | { |
7258 | int regno; | |
7259 | ||
7260 | if (GET_MODE (reloadreg) == mode) | |
7261 | return reloadreg; | |
7262 | ||
7263 | regno = REGNO (reloadreg); | |
7264 | ||
76c64076 | 7265 | if (REG_WORDS_BIG_ENDIAN) |
67d6c12b | 7266 | regno += (int) hard_regno_nregs[regno][GET_MODE (reloadreg)] |
7267 | - (int) hard_regno_nregs[regno][mode]; | |
fd3ac62f | 7268 | |
7269 | return gen_rtx_REG (mode, regno); | |
7270 | } | |
7271 | ||
35823b64 | 7272 | static const char *const reload_when_needed_name[] = |
00e753ce | 7273 | { |
5bb2f919 | 7274 | "RELOAD_FOR_INPUT", |
7275 | "RELOAD_FOR_OUTPUT", | |
00e753ce | 7276 | "RELOAD_FOR_INSN", |
9e53d777 | 7277 | "RELOAD_FOR_INPUT_ADDRESS", |
7278 | "RELOAD_FOR_INPADDR_ADDRESS", | |
00e753ce | 7279 | "RELOAD_FOR_OUTPUT_ADDRESS", |
9e53d777 | 7280 | "RELOAD_FOR_OUTADDR_ADDRESS", |
5bb2f919 | 7281 | "RELOAD_FOR_OPERAND_ADDRESS", |
00e753ce | 7282 | "RELOAD_FOR_OPADDR_ADDR", |
5bb2f919 | 7283 | "RELOAD_OTHER", |
00e753ce | 7284 | "RELOAD_FOR_OTHER_ADDRESS" |
7285 | }; | |
7286 | ||
2d35393b | 7287 | /* These functions are used to print the variables set by 'find_reloads' */ |
00e753ce | 7288 | |
4b987fac | 7289 | DEBUG_FUNCTION void |
3ad4992f | 7290 | debug_reload_to_stream (FILE *f) |
00e753ce | 7291 | { |
7292 | int r; | |
d2ca078f | 7293 | const char *prefix; |
00e753ce | 7294 | |
2d35393b | 7295 | if (! f) |
7296 | f = stderr; | |
00e753ce | 7297 | for (r = 0; r < n_reloads; r++) |
7298 | { | |
2d35393b | 7299 | fprintf (f, "Reload %d: ", r); |
00e753ce | 7300 | |
48666d2c | 7301 | if (rld[r].in != 0) |
00e753ce | 7302 | { |
2d35393b | 7303 | fprintf (f, "reload_in (%s) = ", |
48666d2c | 7304 | GET_MODE_NAME (rld[r].inmode)); |
7305 | print_inline_rtx (f, rld[r].in, 24); | |
2d35393b | 7306 | fprintf (f, "\n\t"); |
00e753ce | 7307 | } |
7308 | ||
48666d2c | 7309 | if (rld[r].out != 0) |
00e753ce | 7310 | { |
2d35393b | 7311 | fprintf (f, "reload_out (%s) = ", |
48666d2c | 7312 | GET_MODE_NAME (rld[r].outmode)); |
7313 | print_inline_rtx (f, rld[r].out, 24); | |
2d35393b | 7314 | fprintf (f, "\n\t"); |
00e753ce | 7315 | } |
7316 | ||
c32319fc | 7317 | fprintf (f, "%s, ", reg_class_names[(int) rld[r].rclass]); |
00e753ce | 7318 | |
2d35393b | 7319 | fprintf (f, "%s (opnum = %d)", |
48666d2c | 7320 | reload_when_needed_name[(int) rld[r].when_needed], |
7321 | rld[r].opnum); | |
00e753ce | 7322 | |
48666d2c | 7323 | if (rld[r].optional) |
2d35393b | 7324 | fprintf (f, ", optional"); |
00e753ce | 7325 | |
48666d2c | 7326 | if (rld[r].nongroup) |
e4c251eb | 7327 | fprintf (f, ", nongroup"); |
c5aa1e92 | 7328 | |
48666d2c | 7329 | if (rld[r].inc != 0) |
7330 | fprintf (f, ", inc by %d", rld[r].inc); | |
00e753ce | 7331 | |
48666d2c | 7332 | if (rld[r].nocombine) |
2d35393b | 7333 | fprintf (f, ", can't combine"); |
00e753ce | 7334 | |
48666d2c | 7335 | if (rld[r].secondary_p) |
2d35393b | 7336 | fprintf (f, ", secondary_reload_p"); |
00e753ce | 7337 | |
48666d2c | 7338 | if (rld[r].in_reg != 0) |
00e753ce | 7339 | { |
2d35393b | 7340 | fprintf (f, "\n\treload_in_reg: "); |
48666d2c | 7341 | print_inline_rtx (f, rld[r].in_reg, 24); |
00e753ce | 7342 | } |
7343 | ||
48666d2c | 7344 | if (rld[r].out_reg != 0) |
93c7b06e | 7345 | { |
7346 | fprintf (f, "\n\treload_out_reg: "); | |
48666d2c | 7347 | print_inline_rtx (f, rld[r].out_reg, 24); |
93c7b06e | 7348 | } |
7349 | ||
48666d2c | 7350 | if (rld[r].reg_rtx != 0) |
00e753ce | 7351 | { |
2d35393b | 7352 | fprintf (f, "\n\treload_reg_rtx: "); |
48666d2c | 7353 | print_inline_rtx (f, rld[r].reg_rtx, 24); |
00e753ce | 7354 | } |
7355 | ||
b1aaeff9 | 7356 | prefix = "\n\t"; |
48666d2c | 7357 | if (rld[r].secondary_in_reload != -1) |
00e753ce | 7358 | { |
2d35393b | 7359 | fprintf (f, "%ssecondary_in_reload = %d", |
48666d2c | 7360 | prefix, rld[r].secondary_in_reload); |
b1aaeff9 | 7361 | prefix = ", "; |
00e753ce | 7362 | } |
7363 | ||
48666d2c | 7364 | if (rld[r].secondary_out_reload != -1) |
2d35393b | 7365 | fprintf (f, "%ssecondary_out_reload = %d\n", |
48666d2c | 7366 | prefix, rld[r].secondary_out_reload); |
00e753ce | 7367 | |
b1aaeff9 | 7368 | prefix = "\n\t"; |
48666d2c | 7369 | if (rld[r].secondary_in_icode != CODE_FOR_nothing) |
00e753ce | 7370 | { |
e4c251eb | 7371 | fprintf (f, "%ssecondary_in_icode = %s", prefix, |
48666d2c | 7372 | insn_data[rld[r].secondary_in_icode].name); |
b1aaeff9 | 7373 | prefix = ", "; |
00e753ce | 7374 | } |
7375 | ||
48666d2c | 7376 | if (rld[r].secondary_out_icode != CODE_FOR_nothing) |
e4c251eb | 7377 | fprintf (f, "%ssecondary_out_icode = %s", prefix, |
48666d2c | 7378 | insn_data[rld[r].secondary_out_icode].name); |
00e753ce | 7379 | |
2d35393b | 7380 | fprintf (f, "\n"); |
00e753ce | 7381 | } |
00e753ce | 7382 | } |
2d35393b | 7383 | |
4b987fac | 7384 | DEBUG_FUNCTION void |
3ad4992f | 7385 | debug_reload (void) |
2d35393b | 7386 | { |
7387 | debug_reload_to_stream (stderr); | |
7388 | } |