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32131a9c | 1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
af841dbd | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
f4f4d0f8 | 3 | 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
32131a9c | 4 | |
1322177d | 5 | This file is part of GCC. |
32131a9c | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
32131a9c | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
32131a9c RK |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
32131a9c | 21 | |
32131a9c | 22 | #include "config.h" |
670ee920 | 23 | #include "system.h" |
cab634f2 KG |
24 | |
25 | #include "machmode.h" | |
26 | #include "hard-reg-set.h" | |
32131a9c | 27 | #include "rtl.h" |
6baf1cc8 | 28 | #include "tm_p.h" |
32131a9c RK |
29 | #include "obstack.h" |
30 | #include "insn-config.h" | |
32131a9c | 31 | #include "flags.h" |
49ad7cfa | 32 | #include "function.h" |
32131a9c | 33 | #include "expr.h" |
e78d8e51 | 34 | #include "optabs.h" |
32131a9c | 35 | #include "regs.h" |
cad6f7d0 | 36 | #include "basic-block.h" |
32131a9c RK |
37 | #include "reload.h" |
38 | #include "recog.h" | |
32131a9c | 39 | #include "output.h" |
eab5c70a | 40 | #include "cselib.h" |
a9c366bf | 41 | #include "real.h" |
10f0ad3d | 42 | #include "toplev.h" |
39f95a2c | 43 | #include "except.h" |
a20fd5ac | 44 | #include "tree.h" |
32131a9c RK |
45 | |
46 | /* This file contains the reload pass of the compiler, which is | |
47 | run after register allocation has been done. It checks that | |
48 | each insn is valid (operands required to be in registers really | |
49 | are in registers of the proper class) and fixes up invalid ones | |
50 | by copying values temporarily into registers for the insns | |
51 | that need them. | |
52 | ||
53 | The results of register allocation are described by the vector | |
54 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
55 | can be used to find which hard reg, if any, a pseudo reg is in. | |
56 | ||
57 | The technique we always use is to free up a few hard regs that are | |
58 | called ``reload regs'', and for each place where a pseudo reg | |
59 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
60 | ||
03acd8f8 BS |
61 | Reload regs are allocated locally for every instruction that needs |
62 | reloads. When there are pseudos which are allocated to a register that | |
63 | has been chosen as a reload reg, such pseudos must be ``spilled''. | |
64 | This means that they go to other hard regs, or to stack slots if no other | |
32131a9c RK |
65 | available hard regs can be found. Spilling can invalidate more |
66 | insns, requiring additional need for reloads, so we must keep checking | |
67 | until the process stabilizes. | |
68 | ||
69 | For machines with different classes of registers, we must keep track | |
70 | of the register class needed for each reload, and make sure that | |
71 | we allocate enough reload registers of each class. | |
72 | ||
73 | The file reload.c contains the code that checks one insn for | |
74 | validity and reports the reloads that it needs. This file | |
75 | is in charge of scanning the entire rtl code, accumulating the | |
76 | reload needs, spilling, assigning reload registers to use for | |
77 | fixing up each insn, and generating the new insns to copy values | |
78 | into the reload registers. */ | |
546b63fb | 79 | |
546b63fb | 80 | #ifndef REGISTER_MOVE_COST |
e56b4594 | 81 | #define REGISTER_MOVE_COST(m, x, y) 2 |
546b63fb | 82 | #endif |
2a3e384f RH |
83 | |
84 | #ifndef LOCAL_REGNO | |
85 | #define LOCAL_REGNO(REGNO) 0 | |
86 | #endif | |
32131a9c RK |
87 | \f |
88 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
0f41302f | 89 | into which reg N has been reloaded (perhaps for a previous insn). */ |
32131a9c RK |
90 | static rtx *reg_last_reload_reg; |
91 | ||
92 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
93 | for an output reload that stores into reg N. */ | |
94 | static char *reg_has_output_reload; | |
95 | ||
96 | /* Indicates which hard regs are reload-registers for an output reload | |
97 | in the current insn. */ | |
98 | static HARD_REG_SET reg_is_output_reload; | |
99 | ||
100 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
101 | or zero if pseudo reg N is not equivalent to a constant. | |
102 | find_reloads looks at this in order to replace pseudo reg N | |
103 | with the constant it stands for. */ | |
104 | rtx *reg_equiv_constant; | |
105 | ||
106 | /* Element N is a memory location to which pseudo reg N is equivalent, | |
107 | prior to any register elimination (such as frame pointer to stack | |
108 | pointer). Depending on whether or not it is a valid address, this value | |
109 | is transferred to either reg_equiv_address or reg_equiv_mem. */ | |
4803a34a | 110 | rtx *reg_equiv_memory_loc; |
32131a9c RK |
111 | |
112 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. | |
113 | This is used when the address is not valid as a memory address | |
114 | (because its displacement is too big for the machine.) */ | |
115 | rtx *reg_equiv_address; | |
116 | ||
117 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
118 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
119 | rtx *reg_equiv_mem; | |
120 | ||
121 | /* Widest width in which each pseudo reg is referred to (via subreg). */ | |
770ae6cc | 122 | static unsigned int *reg_max_ref_width; |
32131a9c | 123 | |
135eb61c | 124 | /* Element N is the list of insns that initialized reg N from its equivalent |
32131a9c RK |
125 | constant or memory slot. */ |
126 | static rtx *reg_equiv_init; | |
127 | ||
03acd8f8 BS |
128 | /* Vector to remember old contents of reg_renumber before spilling. */ |
129 | static short *reg_old_renumber; | |
130 | ||
e6e52be0 | 131 | /* During reload_as_needed, element N contains the last pseudo regno reloaded |
03acd8f8 | 132 | into hard register N. If that pseudo reg occupied more than one register, |
32131a9c RK |
133 | reg_reloaded_contents points to that pseudo for each spill register in |
134 | use; all of these must remain set for an inheritance to occur. */ | |
135 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
136 | ||
137 | /* During reload_as_needed, element N contains the insn for which | |
e6e52be0 R |
138 | hard register N was last used. Its contents are significant only |
139 | when reg_reloaded_valid is set for this register. */ | |
32131a9c RK |
140 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; |
141 | ||
e6e52be0 R |
142 | /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */ |
143 | static HARD_REG_SET reg_reloaded_valid; | |
144 | /* Indicate if the register was dead at the end of the reload. | |
145 | This is only valid if reg_reloaded_contents is set and valid. */ | |
146 | static HARD_REG_SET reg_reloaded_dead; | |
147 | ||
32131a9c RK |
148 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ |
149 | static int n_spills; | |
150 | ||
151 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
152 | Holds the last rtx used for any given reg, or 0 if it has never | |
153 | been used for spilling yet. This rtx is reused, provided it has | |
154 | the proper mode. */ | |
155 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
156 | ||
157 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
158 | that was stored after the last time it was used. | |
159 | The precise value is the insn generated to do the store. */ | |
160 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
161 | ||
cb2afeb3 R |
162 | /* This is the register that was stored with spill_reg_store. This is a |
163 | copy of reload_out / reload_out_reg when the value was stored; if | |
164 | reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ | |
165 | static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; | |
166 | ||
32131a9c RK |
167 | /* This table is the inverse mapping of spill_regs: |
168 | indexed by hard reg number, | |
169 | it contains the position of that reg in spill_regs, | |
05d10675 | 170 | or -1 for something that is not in spill_regs. |
13c8e8e3 JL |
171 | |
172 | ?!? This is no longer accurate. */ | |
32131a9c RK |
173 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; |
174 | ||
03acd8f8 BS |
175 | /* This reg set indicates registers that can't be used as spill registers for |
176 | the currently processed insn. These are the hard registers which are live | |
177 | during the insn, but not allocated to pseudos, as well as fixed | |
178 | registers. */ | |
32131a9c RK |
179 | static HARD_REG_SET bad_spill_regs; |
180 | ||
03acd8f8 BS |
181 | /* These are the hard registers that can't be used as spill register for any |
182 | insn. This includes registers used for user variables and registers that | |
183 | we can't eliminate. A register that appears in this set also can't be used | |
184 | to retry register allocation. */ | |
185 | static HARD_REG_SET bad_spill_regs_global; | |
186 | ||
32131a9c | 187 | /* Describes order of use of registers for reloading |
03acd8f8 BS |
188 | of spilled pseudo-registers. `n_spills' is the number of |
189 | elements that are actually valid; new ones are added at the end. | |
190 | ||
191 | Both spill_regs and spill_reg_order are used on two occasions: | |
192 | once during find_reload_regs, where they keep track of the spill registers | |
193 | for a single insn, but also during reload_as_needed where they show all | |
194 | the registers ever used by reload. For the latter case, the information | |
195 | is calculated during finish_spills. */ | |
32131a9c RK |
196 | static short spill_regs[FIRST_PSEUDO_REGISTER]; |
197 | ||
03acd8f8 BS |
198 | /* This vector of reg sets indicates, for each pseudo, which hard registers |
199 | may not be used for retrying global allocation because the register was | |
200 | formerly spilled from one of them. If we allowed reallocating a pseudo to | |
201 | a register that it was already allocated to, reload might not | |
202 | terminate. */ | |
203 | static HARD_REG_SET *pseudo_previous_regs; | |
204 | ||
205 | /* This vector of reg sets indicates, for each pseudo, which hard | |
206 | registers may not be used for retrying global allocation because they | |
207 | are used as spill registers during one of the insns in which the | |
208 | pseudo is live. */ | |
209 | static HARD_REG_SET *pseudo_forbidden_regs; | |
210 | ||
211 | /* All hard regs that have been used as spill registers for any insn are | |
212 | marked in this set. */ | |
213 | static HARD_REG_SET used_spill_regs; | |
8b4f9969 | 214 | |
4079cd63 JW |
215 | /* Index of last register assigned as a spill register. We allocate in |
216 | a round-robin fashion. */ | |
4079cd63 JW |
217 | static int last_spill_reg; |
218 | ||
32131a9c RK |
219 | /* Nonzero if indirect addressing is supported on the machine; this means |
220 | that spilling (REG n) does not require reloading it into a register in | |
221 | order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The | |
222 | value indicates the level of indirect addressing supported, e.g., two | |
223 | means that (MEM (MEM (REG n))) is also valid if (REG n) does not get | |
224 | a hard register. */ | |
32131a9c RK |
225 | static char spill_indirect_levels; |
226 | ||
227 | /* Nonzero if indirect addressing is supported when the innermost MEM is | |
228 | of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to | |
6d2f8887 | 229 | which these are valid is the same as spill_indirect_levels, above. */ |
32131a9c RK |
230 | char indirect_symref_ok; |
231 | ||
232 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
32131a9c RK |
233 | char double_reg_address_ok; |
234 | ||
235 | /* Record the stack slot for each spilled hard register. */ | |
32131a9c RK |
236 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; |
237 | ||
238 | /* Width allocated so far for that stack slot. */ | |
770ae6cc | 239 | static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; |
32131a9c | 240 | |
7609e720 | 241 | /* Record which pseudos needed to be spilled. */ |
f5d8c9f4 BS |
242 | static regset_head spilled_pseudos; |
243 | ||
244 | /* Used for communication between order_regs_for_reload and count_pseudo. | |
245 | Used to avoid counting one pseudo twice. */ | |
246 | static regset_head pseudos_counted; | |
7609e720 | 247 | |
32131a9c RK |
248 | /* First uid used by insns created by reload in this function. |
249 | Used in find_equiv_reg. */ | |
250 | int reload_first_uid; | |
251 | ||
252 | /* Flag set by local-alloc or global-alloc if anything is live in | |
253 | a call-clobbered reg across calls. */ | |
32131a9c RK |
254 | int caller_save_needed; |
255 | ||
256 | /* Set to 1 while reload_as_needed is operating. | |
257 | Required by some machines to handle any generated moves differently. */ | |
32131a9c RK |
258 | int reload_in_progress = 0; |
259 | ||
260 | /* These arrays record the insn_code of insns that may be needed to | |
261 | perform input and output reloads of special objects. They provide a | |
262 | place to pass a scratch register. */ | |
32131a9c RK |
263 | enum insn_code reload_in_optab[NUM_MACHINE_MODES]; |
264 | enum insn_code reload_out_optab[NUM_MACHINE_MODES]; | |
265 | ||
d45cf215 | 266 | /* This obstack is used for allocation of rtl during register elimination. |
32131a9c RK |
267 | The allocated storage can be freed once find_reloads has processed the |
268 | insn. */ | |
32131a9c | 269 | struct obstack reload_obstack; |
cad6f7d0 BS |
270 | |
271 | /* Points to the beginning of the reload_obstack. All insn_chain structures | |
272 | are allocated first. */ | |
273 | char *reload_startobj; | |
274 | ||
275 | /* The point after all insn_chain structures. Used to quickly deallocate | |
f5d8c9f4 | 276 | memory allocated in copy_reloads during calculate_needs_all_insns. */ |
32131a9c RK |
277 | char *reload_firstobj; |
278 | ||
f5d8c9f4 BS |
279 | /* This points before all local rtl generated by register elimination. |
280 | Used to quickly free all memory after processing one insn. */ | |
281 | static char *reload_insn_firstobj; | |
282 | ||
cad6f7d0 BS |
283 | /* List of insn_chain instructions, one for every insn that reload needs to |
284 | examine. */ | |
285 | struct insn_chain *reload_insn_chain; | |
7609e720 | 286 | |
dfb7c80f JL |
287 | #ifdef TREE_CODE |
288 | extern tree current_function_decl; | |
289 | #else | |
122a860e | 290 | extern union tree_node *current_function_decl; |
dfb7c80f JL |
291 | #endif |
292 | ||
03acd8f8 | 293 | /* List of all insns needing reloads. */ |
7609e720 | 294 | static struct insn_chain *insns_need_reload; |
32131a9c RK |
295 | \f |
296 | /* This structure is used to record information about register eliminations. | |
297 | Each array entry describes one possible way of eliminating a register | |
298 | in favor of another. If there is more than one way of eliminating a | |
299 | particular register, the most preferred should be specified first. */ | |
300 | ||
590cf94d | 301 | struct elim_table |
32131a9c | 302 | { |
0f41302f MS |
303 | int from; /* Register number to be eliminated. */ |
304 | int to; /* Register number used as replacement. */ | |
305 | int initial_offset; /* Initial difference between values. */ | |
306 | int can_eliminate; /* Non-zero if this elimination can be done. */ | |
32131a9c | 307 | int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over |
0f41302f MS |
308 | insns made by reload. */ |
309 | int offset; /* Current offset between the two regs. */ | |
0f41302f MS |
310 | int previous_offset; /* Offset at end of previous insn. */ |
311 | int ref_outside_mem; /* "to" has been referenced outside a MEM. */ | |
32131a9c RK |
312 | rtx from_rtx; /* REG rtx for the register to be eliminated. |
313 | We cannot simply compare the number since | |
314 | we might then spuriously replace a hard | |
315 | register corresponding to a pseudo | |
0f41302f MS |
316 | assigned to the reg to be eliminated. */ |
317 | rtx to_rtx; /* REG rtx for the replacement. */ | |
590cf94d KG |
318 | }; |
319 | ||
1d7254c5 | 320 | static struct elim_table *reg_eliminate = 0; |
590cf94d KG |
321 | |
322 | /* This is an intermediate structure to initialize the table. It has | |
1d7254c5 | 323 | exactly the members provided by ELIMINABLE_REGS. */ |
0b5826ac | 324 | static const struct elim_table_1 |
590cf94d | 325 | { |
0b5826ac KG |
326 | const int from; |
327 | const int to; | |
590cf94d | 328 | } reg_eliminate_1[] = |
32131a9c RK |
329 | |
330 | /* If a set of eliminable registers was specified, define the table from it. | |
331 | Otherwise, default to the normal case of the frame pointer being | |
332 | replaced by the stack pointer. */ | |
333 | ||
334 | #ifdef ELIMINABLE_REGS | |
335 | ELIMINABLE_REGS; | |
336 | #else | |
337 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
338 | #endif | |
339 | ||
b6a1cbae | 340 | #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) |
32131a9c RK |
341 | |
342 | /* Record the number of pending eliminations that have an offset not equal | |
343 | to their initial offset. If non-zero, we use a new copy of each | |
344 | replacement result in any insns encountered. */ | |
cb2afeb3 | 345 | int num_not_at_initial_offset; |
32131a9c RK |
346 | |
347 | /* Count the number of registers that we may be able to eliminate. */ | |
348 | static int num_eliminable; | |
2b49ee39 R |
349 | /* And the number of registers that are equivalent to a constant that |
350 | can be eliminated to frame_pointer / arg_pointer + constant. */ | |
351 | static int num_eliminable_invariants; | |
32131a9c RK |
352 | |
353 | /* For each label, we record the offset of each elimination. If we reach | |
354 | a label by more than one path and an offset differs, we cannot do the | |
355 | elimination. This information is indexed by the number of the label. | |
356 | The first table is an array of flags that records whether we have yet | |
357 | encountered a label and the second table is an array of arrays, one | |
358 | entry in the latter array for each elimination. */ | |
359 | ||
360 | static char *offsets_known_at; | |
361 | static int (*offsets_at)[NUM_ELIMINABLE_REGS]; | |
362 | ||
363 | /* Number of labels in the current function. */ | |
364 | ||
365 | static int num_labels; | |
366 | \f | |
8e2e89f7 KH |
367 | static void replace_pseudos_in_call_usage PARAMS ((rtx *, |
368 | enum machine_mode, | |
369 | rtx)); | |
cdadb1dd KG |
370 | static void maybe_fix_stack_asms PARAMS ((void)); |
371 | static void copy_reloads PARAMS ((struct insn_chain *)); | |
372 | static void calculate_needs_all_insns PARAMS ((int)); | |
e04ca094 JL |
373 | static int find_reg PARAMS ((struct insn_chain *, int)); |
374 | static void find_reload_regs PARAMS ((struct insn_chain *)); | |
375 | static void select_reload_regs PARAMS ((void)); | |
cdadb1dd KG |
376 | static void delete_caller_save_insns PARAMS ((void)); |
377 | ||
378 | static void spill_failure PARAMS ((rtx, enum reg_class)); | |
379 | static void count_spilled_pseudo PARAMS ((int, int, int)); | |
380 | static void delete_dead_insn PARAMS ((rtx)); | |
174fa2c4 | 381 | static void alter_reg PARAMS ((int, int)); |
cdadb1dd KG |
382 | static void set_label_offsets PARAMS ((rtx, rtx, int)); |
383 | static void check_eliminable_occurrences PARAMS ((rtx)); | |
384 | static void elimination_effects PARAMS ((rtx, enum machine_mode)); | |
385 | static int eliminate_regs_in_insn PARAMS ((rtx, int)); | |
386 | static void update_eliminable_offsets PARAMS ((void)); | |
387 | static void mark_not_eliminable PARAMS ((rtx, rtx, void *)); | |
388 | static void set_initial_elim_offsets PARAMS ((void)); | |
389 | static void verify_initial_elim_offsets PARAMS ((void)); | |
390 | static void set_initial_label_offsets PARAMS ((void)); | |
391 | static void set_offsets_for_label PARAMS ((rtx)); | |
392 | static void init_elim_table PARAMS ((void)); | |
393 | static void update_eliminables PARAMS ((HARD_REG_SET *)); | |
e04ca094 JL |
394 | static void spill_hard_reg PARAMS ((unsigned int, int)); |
395 | static int finish_spills PARAMS ((int)); | |
cdadb1dd KG |
396 | static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *)); |
397 | static void scan_paradoxical_subregs PARAMS ((rtx)); | |
398 | static void count_pseudo PARAMS ((int)); | |
399 | static void order_regs_for_reload PARAMS ((struct insn_chain *)); | |
e04ca094 | 400 | static void reload_as_needed PARAMS ((int)); |
cdadb1dd KG |
401 | static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *)); |
402 | static int reload_reg_class_lower PARAMS ((const PTR, const PTR)); | |
770ae6cc RK |
403 | static void mark_reload_reg_in_use PARAMS ((unsigned int, int, |
404 | enum reload_type, | |
405 | enum machine_mode)); | |
406 | static void clear_reload_reg_in_use PARAMS ((unsigned int, int, | |
407 | enum reload_type, | |
408 | enum machine_mode)); | |
409 | static int reload_reg_free_p PARAMS ((unsigned int, int, | |
410 | enum reload_type)); | |
304a22dd R |
411 | static int reload_reg_free_for_value_p PARAMS ((int, int, int, |
412 | enum reload_type, | |
770ae6cc | 413 | rtx, rtx, int, int)); |
c02cad8f BS |
414 | static int free_for_value_p PARAMS ((int, enum machine_mode, int, |
415 | enum reload_type, rtx, rtx, | |
416 | int, int)); | |
770ae6cc RK |
417 | static int reload_reg_reaches_end_p PARAMS ((unsigned int, int, |
418 | enum reload_type)); | |
419 | static int allocate_reload_reg PARAMS ((struct insn_chain *, int, | |
420 | int)); | |
ff6534ad | 421 | static int conflicts_with_override PARAMS ((rtx)); |
cdadb1dd KG |
422 | static void failed_reload PARAMS ((rtx, int)); |
423 | static int set_reload_reg PARAMS ((int, int)); | |
424 | static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *)); | |
425 | static void choose_reload_regs PARAMS ((struct insn_chain *)); | |
426 | static void merge_assigned_reloads PARAMS ((rtx)); | |
427 | static void emit_input_reload_insns PARAMS ((struct insn_chain *, | |
770ae6cc | 428 | struct reload *, rtx, int)); |
cdadb1dd | 429 | static void emit_output_reload_insns PARAMS ((struct insn_chain *, |
770ae6cc | 430 | struct reload *, int)); |
cdadb1dd | 431 | static void do_input_reload PARAMS ((struct insn_chain *, |
770ae6cc | 432 | struct reload *, int)); |
cdadb1dd | 433 | static void do_output_reload PARAMS ((struct insn_chain *, |
770ae6cc | 434 | struct reload *, int)); |
e04ca094 | 435 | static void emit_reload_insns PARAMS ((struct insn_chain *)); |
cdadb1dd KG |
436 | static void delete_output_reload PARAMS ((rtx, int, int)); |
437 | static void delete_address_reloads PARAMS ((rtx, rtx)); | |
438 | static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx)); | |
439 | static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int)); | |
cdadb1dd | 440 | static void reload_cse_regs_1 PARAMS ((rtx)); |
eab5c70a | 441 | static int reload_cse_noop_set_p PARAMS ((rtx)); |
cdadb1dd | 442 | static int reload_cse_simplify_set PARAMS ((rtx, rtx)); |
bf1660a6 | 443 | static int reload_cse_simplify_operands PARAMS ((rtx, rtx)); |
770ae6cc RK |
444 | static void reload_combine PARAMS ((void)); |
445 | static void reload_combine_note_use PARAMS ((rtx *, rtx)); | |
446 | static void reload_combine_note_store PARAMS ((rtx, rtx, void *)); | |
447 | static void reload_cse_move2add PARAMS ((rtx)); | |
448 | static void move2add_note_store PARAMS ((rtx, rtx, void *)); | |
2dfa9a87 | 449 | #ifdef AUTO_INC_DEC |
770ae6cc | 450 | static void add_auto_inc_notes PARAMS ((rtx, rtx)); |
2dfa9a87 | 451 | #endif |
94bd63e5 | 452 | static void copy_eh_notes PARAMS ((rtx, rtx)); |
61f5625b | 453 | static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode, |
770ae6cc | 454 | HOST_WIDE_INT)); |
cdadb1dd KG |
455 | static void failed_reload PARAMS ((rtx, int)); |
456 | static int set_reload_reg PARAMS ((int, int)); | |
bf1660a6 | 457 | static void reload_cse_simplify PARAMS ((rtx, rtx)); |
068473ec | 458 | void fixup_abnormal_edges PARAMS ((void)); |
e04ca094 | 459 | extern void dump_needs PARAMS ((struct insn_chain *)); |
32131a9c | 460 | \f |
546b63fb RK |
461 | /* Initialize the reload pass once per compilation. */ |
462 | ||
32131a9c RK |
463 | void |
464 | init_reload () | |
465 | { | |
b3694847 | 466 | int i; |
32131a9c RK |
467 | |
468 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
469 | Set spill_indirect_levels to the number of levels such addressing is | |
470 | permitted, zero if it is not permitted at all. */ | |
471 | ||
b3694847 | 472 | rtx tem |
38a448ca RH |
473 | = gen_rtx_MEM (Pmode, |
474 | gen_rtx_PLUS (Pmode, | |
c5c76735 JL |
475 | gen_rtx_REG (Pmode, |
476 | LAST_VIRTUAL_REGISTER + 1), | |
38a448ca | 477 | GEN_INT (4))); |
32131a9c RK |
478 | spill_indirect_levels = 0; |
479 | ||
480 | while (memory_address_p (QImode, tem)) | |
481 | { | |
482 | spill_indirect_levels++; | |
38a448ca | 483 | tem = gen_rtx_MEM (Pmode, tem); |
32131a9c RK |
484 | } |
485 | ||
486 | /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ | |
487 | ||
38a448ca | 488 | tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); |
32131a9c RK |
489 | indirect_symref_ok = memory_address_p (QImode, tem); |
490 | ||
491 | /* See if reg+reg is a valid (and offsettable) address. */ | |
492 | ||
65701fd2 | 493 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
57caa638 | 494 | { |
38a448ca RH |
495 | tem = gen_rtx_PLUS (Pmode, |
496 | gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), | |
497 | gen_rtx_REG (Pmode, i)); | |
c5c76735 | 498 | |
57caa638 RS |
499 | /* This way, we make sure that reg+reg is an offsettable address. */ |
500 | tem = plus_constant (tem, 4); | |
501 | ||
502 | if (memory_address_p (QImode, tem)) | |
503 | { | |
504 | double_reg_address_ok = 1; | |
505 | break; | |
506 | } | |
507 | } | |
32131a9c | 508 | |
0f41302f | 509 | /* Initialize obstack for our rtl allocation. */ |
32131a9c | 510 | gcc_obstack_init (&reload_obstack); |
cad6f7d0 | 511 | reload_startobj = (char *) obstack_alloc (&reload_obstack, 0); |
f5d8c9f4 BS |
512 | |
513 | INIT_REG_SET (&spilled_pseudos); | |
514 | INIT_REG_SET (&pseudos_counted); | |
32131a9c RK |
515 | } |
516 | ||
cad6f7d0 BS |
517 | /* List of insn chains that are currently unused. */ |
518 | static struct insn_chain *unused_insn_chains = 0; | |
519 | ||
520 | /* Allocate an empty insn_chain structure. */ | |
521 | struct insn_chain * | |
522 | new_insn_chain () | |
523 | { | |
524 | struct insn_chain *c; | |
525 | ||
526 | if (unused_insn_chains == 0) | |
527 | { | |
8db99db2 KG |
528 | c = (struct insn_chain *) |
529 | obstack_alloc (&reload_obstack, sizeof (struct insn_chain)); | |
239a0f5b BS |
530 | INIT_REG_SET (&c->live_throughout); |
531 | INIT_REG_SET (&c->dead_or_set); | |
cad6f7d0 BS |
532 | } |
533 | else | |
534 | { | |
535 | c = unused_insn_chains; | |
536 | unused_insn_chains = c->next; | |
537 | } | |
538 | c->is_caller_save_insn = 0; | |
03acd8f8 | 539 | c->need_operand_change = 0; |
cad6f7d0 BS |
540 | c->need_reload = 0; |
541 | c->need_elim = 0; | |
542 | return c; | |
543 | } | |
544 | ||
7609e720 BS |
545 | /* Small utility function to set all regs in hard reg set TO which are |
546 | allocated to pseudos in regset FROM. */ | |
770ae6cc | 547 | |
7609e720 BS |
548 | void |
549 | compute_use_by_pseudos (to, from) | |
550 | HARD_REG_SET *to; | |
551 | regset from; | |
552 | { | |
770ae6cc RK |
553 | unsigned int regno; |
554 | ||
7609e720 BS |
555 | EXECUTE_IF_SET_IN_REG_SET |
556 | (from, FIRST_PSEUDO_REGISTER, regno, | |
557 | { | |
558 | int r = reg_renumber[regno]; | |
559 | int nregs; | |
770ae6cc | 560 | |
7609e720 | 561 | if (r < 0) |
404d95c4 R |
562 | { |
563 | /* reload_combine uses the information from | |
e881bb1b RH |
564 | BASIC_BLOCK->global_live_at_start, which might still |
565 | contain registers that have not actually been allocated | |
566 | since they have an equivalence. */ | |
404d95c4 R |
567 | if (! reload_completed) |
568 | abort (); | |
569 | } | |
570 | else | |
571 | { | |
572 | nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno)); | |
573 | while (nregs-- > 0) | |
574 | SET_HARD_REG_BIT (*to, r + nregs); | |
575 | } | |
7609e720 BS |
576 | }); |
577 | } | |
f474c6f8 AO |
578 | |
579 | /* Replace all pseudos found in LOC with their corresponding | |
580 | equivalences. */ | |
581 | ||
582 | static void | |
583 | replace_pseudos_in_call_usage (loc, mem_mode, usage) | |
584 | rtx *loc; | |
585 | enum machine_mode mem_mode; | |
586 | rtx usage; | |
587 | { | |
588 | rtx x = *loc; | |
589 | enum rtx_code code; | |
590 | const char *fmt; | |
591 | int i, j; | |
592 | ||
593 | if (! x) | |
594 | return; | |
174fa2c4 | 595 | |
f474c6f8 AO |
596 | code = GET_CODE (x); |
597 | if (code == REG) | |
598 | { | |
ae0ed63a | 599 | unsigned int regno = REGNO (x); |
086fef9e AO |
600 | |
601 | if (regno < FIRST_PSEUDO_REGISTER) | |
f474c6f8 AO |
602 | return; |
603 | ||
604 | x = eliminate_regs (x, mem_mode, usage); | |
605 | if (x != *loc) | |
606 | { | |
607 | *loc = x; | |
608 | replace_pseudos_in_call_usage (loc, mem_mode, usage); | |
609 | return; | |
610 | } | |
611 | ||
086fef9e AO |
612 | if (reg_equiv_constant[regno]) |
613 | *loc = reg_equiv_constant[regno]; | |
614 | else if (reg_equiv_mem[regno]) | |
615 | *loc = reg_equiv_mem[regno]; | |
616 | else if (reg_equiv_address[regno]) | |
617 | *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]); | |
618 | else if (GET_CODE (regno_reg_rtx[regno]) != REG | |
619 | || REGNO (regno_reg_rtx[regno]) != regno) | |
620 | *loc = regno_reg_rtx[regno]; | |
f474c6f8 AO |
621 | else |
622 | abort (); | |
623 | ||
624 | return; | |
625 | } | |
626 | else if (code == MEM) | |
627 | { | |
628 | replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage); | |
629 | return; | |
630 | } | |
174fa2c4 | 631 | |
f474c6f8 AO |
632 | /* Process each of our operands recursively. */ |
633 | fmt = GET_RTX_FORMAT (code); | |
634 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
635 | if (*fmt == 'e') | |
636 | replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage); | |
637 | else if (*fmt == 'E') | |
638 | for (j = 0; j < XVECLEN (x, i); j++) | |
639 | replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage); | |
640 | } | |
641 | ||
03acd8f8 | 642 | \f |
1e5bd841 BS |
643 | /* Global variables used by reload and its subroutines. */ |
644 | ||
1e5bd841 BS |
645 | /* Set during calculate_needs if an insn needs register elimination. */ |
646 | static int something_needs_elimination; | |
cb2afeb3 R |
647 | /* Set during calculate_needs if an insn needs an operand changed. */ |
648 | int something_needs_operands_changed; | |
1e5bd841 | 649 | |
1e5bd841 BS |
650 | /* Nonzero means we couldn't get enough spill regs. */ |
651 | static int failure; | |
652 | ||
546b63fb | 653 | /* Main entry point for the reload pass. |
32131a9c RK |
654 | |
655 | FIRST is the first insn of the function being compiled. | |
656 | ||
657 | GLOBAL nonzero means we were called from global_alloc | |
658 | and should attempt to reallocate any pseudoregs that we | |
659 | displace from hard regs we will use for reloads. | |
660 | If GLOBAL is zero, we do not have enough information to do that, | |
661 | so any pseudo reg that is spilled must go to the stack. | |
662 | ||
5352b11a RS |
663 | Return value is nonzero if reload failed |
664 | and we must not do any more for this function. */ | |
665 | ||
666 | int | |
e04ca094 | 667 | reload (first, global) |
32131a9c RK |
668 | rtx first; |
669 | int global; | |
32131a9c | 670 | { |
b3694847 SS |
671 | int i; |
672 | rtx insn; | |
673 | struct elim_table *ep; | |
e0082a72 | 674 | basic_block bb; |
32131a9c | 675 | |
a68d4b75 BK |
676 | /* The two pointers used to track the true location of the memory used |
677 | for label offsets. */ | |
9714cf43 | 678 | char *real_known_ptr = NULL; |
a68d4b75 BK |
679 | int (*real_at_ptr)[NUM_ELIMINABLE_REGS]; |
680 | ||
32131a9c RK |
681 | /* Make sure even insns with volatile mem refs are recognizable. */ |
682 | init_recog (); | |
683 | ||
1e5bd841 BS |
684 | failure = 0; |
685 | ||
cad6f7d0 BS |
686 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); |
687 | ||
437a710d BS |
688 | /* Make sure that the last insn in the chain |
689 | is not something that needs reloading. */ | |
6496a589 | 690 | emit_note (NULL, NOTE_INSN_DELETED); |
437a710d | 691 | |
32131a9c RK |
692 | /* Enable find_equiv_reg to distinguish insns made by reload. */ |
693 | reload_first_uid = get_max_uid (); | |
694 | ||
0dadecf6 RK |
695 | #ifdef SECONDARY_MEMORY_NEEDED |
696 | /* Initialize the secondary memory table. */ | |
697 | clear_secondary_mem (); | |
698 | #endif | |
699 | ||
32131a9c | 700 | /* We don't have a stack slot for any spill reg yet. */ |
961192e1 JM |
701 | memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot); |
702 | memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width); | |
32131a9c | 703 | |
a8efe40d RK |
704 | /* Initialize the save area information for caller-save, in case some |
705 | are needed. */ | |
706 | init_save_areas (); | |
a8fdc208 | 707 | |
32131a9c RK |
708 | /* Compute which hard registers are now in use |
709 | as homes for pseudo registers. | |
710 | This is done here rather than (eg) in global_alloc | |
711 | because this point is reached even if not optimizing. */ | |
32131a9c RK |
712 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
713 | mark_home_live (i); | |
714 | ||
8dddd002 RK |
715 | /* A function that receives a nonlocal goto must save all call-saved |
716 | registers. */ | |
717 | if (current_function_has_nonlocal_label) | |
718 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2a3e384f RH |
719 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) |
720 | regs_ever_live[i] = 1; | |
8dddd002 | 721 | |
32131a9c RK |
722 | /* Find all the pseudo registers that didn't get hard regs |
723 | but do have known equivalent constants or memory slots. | |
724 | These include parameters (known equivalent to parameter slots) | |
725 | and cse'd or loop-moved constant memory addresses. | |
726 | ||
727 | Record constant equivalents in reg_equiv_constant | |
728 | so they will be substituted by find_reloads. | |
729 | Record memory equivalents in reg_mem_equiv so they can | |
730 | be substituted eventually by altering the REG-rtx's. */ | |
731 | ||
ad85216e | 732 | reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
ad85216e KG |
733 | reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
734 | reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
735 | reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
f9e158c3 | 736 | reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int)); |
ad85216e | 737 | reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short)); |
4e135bdd | 738 | memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); |
03acd8f8 BS |
739 | pseudo_forbidden_regs |
740 | = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET)); | |
741 | pseudo_previous_regs | |
ad85216e | 742 | = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET)); |
32131a9c | 743 | |
03acd8f8 | 744 | CLEAR_HARD_REG_SET (bad_spill_regs_global); |
56f58d3a | 745 | |
32131a9c | 746 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. |
56f58d3a RK |
747 | Also find all paradoxical subregs and find largest such for each pseudo. |
748 | On machines with small register classes, record hard registers that | |
05d10675 | 749 | are used for user variables. These can never be used for spills. |
570a98eb | 750 | Also look for a "constant" REG_SETJMP. This means that all |
b453cb0b | 751 | caller-saved registers must be marked live. */ |
32131a9c | 752 | |
2b49ee39 | 753 | num_eliminable_invariants = 0; |
32131a9c RK |
754 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
755 | { | |
756 | rtx set = single_set (insn); | |
757 | ||
3d17d93d AO |
758 | /* We may introduce USEs that we want to remove at the end, so |
759 | we'll mark them with QImode. Make sure there are no | |
760 | previously-marked insns left by say regmove. */ | |
761 | if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE | |
762 | && GET_MODE (insn) != VOIDmode) | |
763 | PUT_MODE (insn, VOIDmode); | |
764 | ||
19652adf ZW |
765 | if (GET_CODE (insn) == CALL_INSN |
766 | && find_reg_note (insn, REG_SETJMP, NULL)) | |
b453cb0b RK |
767 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
768 | if (! call_used_regs[i]) | |
769 | regs_ever_live[i] = 1; | |
770 | ||
32131a9c RK |
771 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG) |
772 | { | |
fb3821f7 | 773 | rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
a8efe40d RK |
774 | if (note |
775 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
2b49ee39 R |
776 | && (! function_invariant_p (XEXP (note, 0)) |
777 | || ! flag_pic | |
129c0899 HPN |
778 | /* A function invariant is often CONSTANT_P but may |
779 | include a register. We promise to only pass | |
780 | CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ | |
781 | || (CONSTANT_P (XEXP (note, 0)) | |
782 | && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))) | |
a8efe40d RK |
783 | #endif |
784 | ) | |
32131a9c RK |
785 | { |
786 | rtx x = XEXP (note, 0); | |
787 | i = REGNO (SET_DEST (set)); | |
788 | if (i > LAST_VIRTUAL_REGISTER) | |
789 | { | |
6a45951f UW |
790 | /* It can happen that a REG_EQUIV note contains a MEM |
791 | that is not a legitimate memory operand. As later | |
792 | stages of reload assume that all addresses found | |
793 | in the reg_equiv_* arrays were originally legitimate, | |
794 | we ignore such REG_EQUIV notes. */ | |
795 | if (memory_operand (x, VOIDmode)) | |
956d6950 | 796 | { |
cf728d61 HPN |
797 | /* Always unshare the equivalence, so we can |
798 | substitute into this insn without touching the | |
2ba84f36 | 799 | equivalence. */ |
cf728d61 | 800 | reg_equiv_memory_loc[i] = copy_rtx (x); |
956d6950 | 801 | } |
2b49ee39 | 802 | else if (function_invariant_p (x)) |
32131a9c | 803 | { |
2b49ee39 R |
804 | if (GET_CODE (x) == PLUS) |
805 | { | |
806 | /* This is PLUS of frame pointer and a constant, | |
807 | and might be shared. Unshare it. */ | |
808 | reg_equiv_constant[i] = copy_rtx (x); | |
809 | num_eliminable_invariants++; | |
810 | } | |
811 | else if (x == frame_pointer_rtx | |
812 | || x == arg_pointer_rtx) | |
813 | { | |
814 | reg_equiv_constant[i] = x; | |
815 | num_eliminable_invariants++; | |
816 | } | |
817 | else if (LEGITIMATE_CONSTANT_P (x)) | |
32131a9c RK |
818 | reg_equiv_constant[i] = x; |
819 | else | |
820 | reg_equiv_memory_loc[i] | |
d445b551 | 821 | = force_const_mem (GET_MODE (SET_DEST (set)), x); |
32131a9c RK |
822 | } |
823 | else | |
824 | continue; | |
825 | ||
826 | /* If this register is being made equivalent to a MEM | |
827 | and the MEM is not SET_SRC, the equivalencing insn | |
828 | is one with the MEM as a SET_DEST and it occurs later. | |
829 | So don't mark this insn now. */ | |
830 | if (GET_CODE (x) != MEM | |
831 | || rtx_equal_p (SET_SRC (set), x)) | |
135eb61c R |
832 | reg_equiv_init[i] |
833 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]); | |
32131a9c RK |
834 | } |
835 | } | |
836 | } | |
837 | ||
838 | /* If this insn is setting a MEM from a register equivalent to it, | |
839 | this is the equivalencing insn. */ | |
840 | else if (set && GET_CODE (SET_DEST (set)) == MEM | |
841 | && GET_CODE (SET_SRC (set)) == REG | |
842 | && reg_equiv_memory_loc[REGNO (SET_SRC (set))] | |
843 | && rtx_equal_p (SET_DEST (set), | |
844 | reg_equiv_memory_loc[REGNO (SET_SRC (set))])) | |
135eb61c R |
845 | reg_equiv_init[REGNO (SET_SRC (set))] |
846 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
847 | reg_equiv_init[REGNO (SET_SRC (set))]); | |
32131a9c | 848 | |
2c3c49de | 849 | if (INSN_P (insn)) |
32131a9c RK |
850 | scan_paradoxical_subregs (PATTERN (insn)); |
851 | } | |
852 | ||
09dd1133 | 853 | init_elim_table (); |
32131a9c RK |
854 | |
855 | num_labels = max_label_num () - get_first_label_num (); | |
856 | ||
857 | /* Allocate the tables used to store offset information at labels. */ | |
a68d4b75 BK |
858 | /* We used to use alloca here, but the size of what it would try to |
859 | allocate would occasionally cause it to exceed the stack limit and | |
860 | cause a core dump. */ | |
861 | real_known_ptr = xmalloc (num_labels); | |
862 | real_at_ptr | |
32131a9c | 863 | = (int (*)[NUM_ELIMINABLE_REGS]) |
a68d4b75 | 864 | xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int)); |
32131a9c | 865 | |
a68d4b75 BK |
866 | offsets_known_at = real_known_ptr - get_first_label_num (); |
867 | offsets_at | |
868 | = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ()); | |
32131a9c RK |
869 | |
870 | /* Alter each pseudo-reg rtx to contain its hard reg number. | |
871 | Assign stack slots to the pseudos that lack hard regs or equivalents. | |
872 | Do not touch virtual registers. */ | |
873 | ||
874 | for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) | |
875 | alter_reg (i, -1); | |
876 | ||
32131a9c RK |
877 | /* If we have some registers we think can be eliminated, scan all insns to |
878 | see if there is an insn that sets one of these registers to something | |
879 | other than itself plus a constant. If so, the register cannot be | |
880 | eliminated. Doing this scan here eliminates an extra pass through the | |
881 | main reload loop in the most common case where register elimination | |
882 | cannot be done. */ | |
883 | for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) | |
884 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN | |
885 | || GET_CODE (insn) == CALL_INSN) | |
84832317 | 886 | note_stores (PATTERN (insn), mark_not_eliminable, NULL); |
32131a9c | 887 | |
18a90182 BS |
888 | maybe_fix_stack_asms (); |
889 | ||
03acd8f8 BS |
890 | insns_need_reload = 0; |
891 | something_needs_elimination = 0; | |
05d10675 | 892 | |
4079cd63 JW |
893 | /* Initialize to -1, which means take the first spill register. */ |
894 | last_spill_reg = -1; | |
895 | ||
32131a9c | 896 | /* Spill any hard regs that we know we can't eliminate. */ |
03acd8f8 | 897 | CLEAR_HARD_REG_SET (used_spill_regs); |
32131a9c RK |
898 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
899 | if (! ep->can_eliminate) | |
e04ca094 | 900 | spill_hard_reg (ep->from, 1); |
9ff3516a RK |
901 | |
902 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
903 | if (frame_pointer_needed) | |
e04ca094 | 904 | spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1); |
9ff3516a | 905 | #endif |
e04ca094 | 906 | finish_spills (global); |
7609e720 | 907 | |
f1db3576 JL |
908 | /* From now on, we may need to generate moves differently. We may also |
909 | allow modifications of insns which cause them to not be recognized. | |
910 | Any such modifications will be cleaned up during reload itself. */ | |
b2f15f94 RK |
911 | reload_in_progress = 1; |
912 | ||
32131a9c RK |
913 | /* This loop scans the entire function each go-round |
914 | and repeats until one repetition spills no additional hard regs. */ | |
03acd8f8 | 915 | for (;;) |
32131a9c | 916 | { |
03acd8f8 BS |
917 | int something_changed; |
918 | int did_spill; | |
32131a9c | 919 | |
03acd8f8 | 920 | HOST_WIDE_INT starting_frame_size; |
32131a9c | 921 | |
665792eb | 922 | /* Round size of stack frame to stack_alignment_needed. This must be done |
7657bf2f JW |
923 | here because the stack size may be a part of the offset computation |
924 | for register elimination, and there might have been new stack slots | |
6d2f8887 | 925 | created in the last iteration of this loop. */ |
665792eb JH |
926 | if (cfun->stack_alignment_needed) |
927 | assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed); | |
7657bf2f JW |
928 | |
929 | starting_frame_size = get_frame_size (); | |
930 | ||
09dd1133 | 931 | set_initial_elim_offsets (); |
1f3b1e1a | 932 | set_initial_label_offsets (); |
03acd8f8 | 933 | |
32131a9c RK |
934 | /* For each pseudo register that has an equivalent location defined, |
935 | try to eliminate any eliminable registers (such as the frame pointer) | |
936 | assuming initial offsets for the replacement register, which | |
937 | is the normal case. | |
938 | ||
939 | If the resulting location is directly addressable, substitute | |
940 | the MEM we just got directly for the old REG. | |
941 | ||
942 | If it is not addressable but is a constant or the sum of a hard reg | |
943 | and constant, it is probably not addressable because the constant is | |
944 | out of range, in that case record the address; we will generate | |
945 | hairy code to compute the address in a register each time it is | |
6491dbbb RK |
946 | needed. Similarly if it is a hard register, but one that is not |
947 | valid as an address register. | |
32131a9c RK |
948 | |
949 | If the location is not addressable, but does not have one of the | |
950 | above forms, assign a stack slot. We have to do this to avoid the | |
951 | potential of producing lots of reloads if, e.g., a location involves | |
952 | a pseudo that didn't get a hard register and has an equivalent memory | |
953 | location that also involves a pseudo that didn't get a hard register. | |
954 | ||
955 | Perhaps at some point we will improve reload_when_needed handling | |
956 | so this problem goes away. But that's very hairy. */ | |
957 | ||
958 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
959 | if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) | |
960 | { | |
1914f5da | 961 | rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); |
32131a9c RK |
962 | |
963 | if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), | |
964 | XEXP (x, 0))) | |
965 | reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; | |
966 | else if (CONSTANT_P (XEXP (x, 0)) | |
6491dbbb RK |
967 | || (GET_CODE (XEXP (x, 0)) == REG |
968 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
969 | || (GET_CODE (XEXP (x, 0)) == PLUS |
970 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
971 | && (REGNO (XEXP (XEXP (x, 0), 0)) | |
972 | < FIRST_PSEUDO_REGISTER) | |
973 | && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) | |
974 | reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; | |
975 | else | |
976 | { | |
977 | /* Make a new stack slot. Then indicate that something | |
a8fdc208 | 978 | changed so we go back and recompute offsets for |
32131a9c RK |
979 | eliminable registers because the allocation of memory |
980 | below might change some offset. reg_equiv_{mem,address} | |
981 | will be set up for this pseudo on the next pass around | |
982 | the loop. */ | |
983 | reg_equiv_memory_loc[i] = 0; | |
984 | reg_equiv_init[i] = 0; | |
985 | alter_reg (i, -1); | |
32131a9c RK |
986 | } |
987 | } | |
a8fdc208 | 988 | |
437a710d BS |
989 | if (caller_save_needed) |
990 | setup_save_areas (); | |
991 | ||
03acd8f8 | 992 | /* If we allocated another stack slot, redo elimination bookkeeping. */ |
437a710d | 993 | if (starting_frame_size != get_frame_size ()) |
32131a9c RK |
994 | continue; |
995 | ||
437a710d | 996 | if (caller_save_needed) |
a8efe40d | 997 | { |
437a710d BS |
998 | save_call_clobbered_regs (); |
999 | /* That might have allocated new insn_chain structures. */ | |
1000 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
a8efe40d RK |
1001 | } |
1002 | ||
03acd8f8 BS |
1003 | calculate_needs_all_insns (global); |
1004 | ||
f5d8c9f4 | 1005 | CLEAR_REG_SET (&spilled_pseudos); |
03acd8f8 BS |
1006 | did_spill = 0; |
1007 | ||
1008 | something_changed = 0; | |
32131a9c | 1009 | |
0dadecf6 RK |
1010 | /* If we allocated any new memory locations, make another pass |
1011 | since it might have changed elimination offsets. */ | |
1012 | if (starting_frame_size != get_frame_size ()) | |
1013 | something_changed = 1; | |
1014 | ||
09dd1133 BS |
1015 | { |
1016 | HARD_REG_SET to_spill; | |
1017 | CLEAR_HARD_REG_SET (to_spill); | |
1018 | update_eliminables (&to_spill); | |
1019 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1020 | if (TEST_HARD_REG_BIT (to_spill, i)) | |
32131a9c | 1021 | { |
e04ca094 | 1022 | spill_hard_reg (i, 1); |
03acd8f8 | 1023 | did_spill = 1; |
8f5db3c1 JL |
1024 | |
1025 | /* Regardless of the state of spills, if we previously had | |
1026 | a register that we thought we could eliminate, but no can | |
1027 | not eliminate, we must run another pass. | |
1028 | ||
1029 | Consider pseudos which have an entry in reg_equiv_* which | |
1030 | reference an eliminable register. We must make another pass | |
1031 | to update reg_equiv_* so that we do not substitute in the | |
1032 | old value from when we thought the elimination could be | |
1033 | performed. */ | |
1034 | something_changed = 1; | |
32131a9c | 1035 | } |
09dd1133 | 1036 | } |
9ff3516a | 1037 | |
e04ca094 | 1038 | select_reload_regs (); |
e483bf9c BS |
1039 | if (failure) |
1040 | goto failed; | |
437a710d | 1041 | |
e483bf9c | 1042 | if (insns_need_reload != 0 || did_spill) |
e04ca094 | 1043 | something_changed |= finish_spills (global); |
7609e720 | 1044 | |
03acd8f8 BS |
1045 | if (! something_changed) |
1046 | break; | |
1047 | ||
1048 | if (caller_save_needed) | |
7609e720 | 1049 | delete_caller_save_insns (); |
f5d8c9f4 BS |
1050 | |
1051 | obstack_free (&reload_obstack, reload_firstobj); | |
32131a9c RK |
1052 | } |
1053 | ||
1054 | /* If global-alloc was run, notify it of any register eliminations we have | |
1055 | done. */ | |
1056 | if (global) | |
1057 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1058 | if (ep->can_eliminate) | |
1059 | mark_elimination (ep->from, ep->to); | |
1060 | ||
32131a9c RK |
1061 | /* If a pseudo has no hard reg, delete the insns that made the equivalence. |
1062 | If that insn didn't set the register (i.e., it copied the register to | |
1063 | memory), just delete that insn instead of the equivalencing insn plus | |
1064 | anything now dead. If we call delete_dead_insn on that insn, we may | |
135eb61c | 1065 | delete the insn that actually sets the register if the register dies |
32131a9c RK |
1066 | there and that is incorrect. */ |
1067 | ||
1068 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
135eb61c R |
1069 | { |
1070 | if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) | |
1071 | { | |
1072 | rtx list; | |
1073 | for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) | |
1074 | { | |
1075 | rtx equiv_insn = XEXP (list, 0); | |
78571511 RK |
1076 | |
1077 | /* If we already deleted the insn or if it may trap, we can't | |
1078 | delete it. The latter case shouldn't happen, but can | |
1079 | if an insn has a variable address, gets a REG_EH_REGION | |
1080 | note added to it, and then gets converted into an load | |
1081 | from a constant address. */ | |
1082 | if (GET_CODE (equiv_insn) == NOTE | |
1083 | || can_throw_internal (equiv_insn)) | |
1084 | ; | |
1085 | else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) | |
135eb61c R |
1086 | delete_dead_insn (equiv_insn); |
1087 | else | |
1088 | { | |
1089 | PUT_CODE (equiv_insn, NOTE); | |
1090 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
1091 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
1092 | } | |
1093 | } | |
1094 | } | |
1095 | } | |
32131a9c RK |
1096 | |
1097 | /* Use the reload registers where necessary | |
1098 | by generating move instructions to move the must-be-register | |
1099 | values into or out of the reload registers. */ | |
1100 | ||
03acd8f8 BS |
1101 | if (insns_need_reload != 0 || something_needs_elimination |
1102 | || something_needs_operands_changed) | |
c47f5ea5 | 1103 | { |
102870fb | 1104 | HOST_WIDE_INT old_frame_size = get_frame_size (); |
c47f5ea5 | 1105 | |
e04ca094 | 1106 | reload_as_needed (global); |
c47f5ea5 BS |
1107 | |
1108 | if (old_frame_size != get_frame_size ()) | |
1109 | abort (); | |
1110 | ||
1111 | if (num_eliminable) | |
1112 | verify_initial_elim_offsets (); | |
1113 | } | |
32131a9c | 1114 | |
2a1f8b6b | 1115 | /* If we were able to eliminate the frame pointer, show that it is no |
546b63fb | 1116 | longer live at the start of any basic block. If it ls live by |
2a1f8b6b RK |
1117 | virtue of being in a pseudo, that pseudo will be marked live |
1118 | and hence the frame pointer will be known to be live via that | |
1119 | pseudo. */ | |
1120 | ||
1121 | if (! frame_pointer_needed) | |
e0082a72 ZD |
1122 | FOR_EACH_BB (bb) |
1123 | CLEAR_REGNO_REG_SET (bb->global_live_at_start, | |
8e08106d | 1124 | HARD_FRAME_POINTER_REGNUM); |
2a1f8b6b | 1125 | |
5352b11a RS |
1126 | /* Come here (with failure set nonzero) if we can't get enough spill regs |
1127 | and we decide not to abort about it. */ | |
1128 | failed: | |
1129 | ||
f5d8c9f4 | 1130 | CLEAR_REG_SET (&spilled_pseudos); |
a3ec87a8 RS |
1131 | reload_in_progress = 0; |
1132 | ||
32131a9c RK |
1133 | /* Now eliminate all pseudo regs by modifying them into |
1134 | their equivalent memory references. | |
1135 | The REG-rtx's for the pseudos are modified in place, | |
1136 | so all insns that used to refer to them now refer to memory. | |
1137 | ||
1138 | For a reg that has a reg_equiv_address, all those insns | |
1139 | were changed by reloading so that no insns refer to it any longer; | |
1140 | but the DECL_RTL of a variable decl may refer to it, | |
1141 | and if so this causes the debugging info to mention the variable. */ | |
1142 | ||
1143 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1144 | { | |
1145 | rtx addr = 0; | |
9ec36da5 JL |
1146 | |
1147 | if (reg_equiv_mem[i]) | |
1148 | addr = XEXP (reg_equiv_mem[i], 0); | |
1149 | ||
32131a9c RK |
1150 | if (reg_equiv_address[i]) |
1151 | addr = reg_equiv_address[i]; | |
9ec36da5 | 1152 | |
32131a9c RK |
1153 | if (addr) |
1154 | { | |
1155 | if (reg_renumber[i] < 0) | |
1156 | { | |
1157 | rtx reg = regno_reg_rtx[i]; | |
173b24b9 | 1158 | |
5a63e069 | 1159 | REG_USERVAR_P (reg) = 0; |
ef178af3 | 1160 | PUT_CODE (reg, MEM); |
32131a9c | 1161 | XEXP (reg, 0) = addr; |
173b24b9 RK |
1162 | if (reg_equiv_memory_loc[i]) |
1163 | MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]); | |
1164 | else | |
1165 | { | |
1166 | RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg) | |
1167 | = MEM_SCALAR_P (reg) = 0; | |
1168 | MEM_ATTRS (reg) = 0; | |
1169 | } | |
32131a9c RK |
1170 | } |
1171 | else if (reg_equiv_mem[i]) | |
1172 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1173 | } | |
1174 | } | |
1175 | ||
2ae74651 JL |
1176 | /* We must set reload_completed now since the cleanup_subreg_operands call |
1177 | below will re-recognize each insn and reload may have generated insns | |
1178 | which are only valid during and after reload. */ | |
1179 | reload_completed = 1; | |
1180 | ||
bd695e1e RH |
1181 | /* Make a pass over all the insns and delete all USEs which we inserted |
1182 | only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED | |
1183 | notes. Delete all CLOBBER insns that don't refer to the return value | |
260f91c2 DJ |
1184 | or to memory (mem:BLK CLOBBERs must be retained to prevent the scheduler |
1185 | from misarranging variable-array code) and simplify (subreg (reg)) | |
1186 | operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they | |
1187 | are no longer useful or accurate. Strip and regenerate REG_INC notes | |
1188 | that may have been moved around. */ | |
32131a9c RK |
1189 | |
1190 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 1191 | if (INSN_P (insn)) |
32131a9c | 1192 | { |
6764d250 | 1193 | rtx *pnote; |
32131a9c | 1194 | |
f474c6f8 AO |
1195 | if (GET_CODE (insn) == CALL_INSN) |
1196 | replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn), | |
1197 | VOIDmode, | |
1198 | CALL_INSN_FUNCTION_USAGE (insn)); | |
1199 | ||
0304f787 | 1200 | if ((GET_CODE (PATTERN (insn)) == USE |
3d17d93d AO |
1201 | /* We mark with QImode USEs introduced by reload itself. */ |
1202 | && (GET_MODE (insn) == QImode | |
1203 | || find_reg_note (insn, REG_EQUAL, NULL_RTX))) | |
bd695e1e | 1204 | || (GET_CODE (PATTERN (insn)) == CLOBBER |
260f91c2 DJ |
1205 | && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM |
1206 | || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode) | |
bd695e1e RH |
1207 | && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG |
1208 | || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) | |
b60a8416 | 1209 | { |
e5eac8ef | 1210 | delete_insn (insn); |
b60a8416 R |
1211 | continue; |
1212 | } | |
6764d250 BS |
1213 | |
1214 | pnote = ®_NOTES (insn); | |
1215 | while (*pnote != 0) | |
32131a9c | 1216 | { |
6764d250 | 1217 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
80599fd9 | 1218 | || REG_NOTE_KIND (*pnote) == REG_UNUSED |
2dfa9a87 | 1219 | || REG_NOTE_KIND (*pnote) == REG_INC |
80599fd9 NC |
1220 | || REG_NOTE_KIND (*pnote) == REG_RETVAL |
1221 | || REG_NOTE_KIND (*pnote) == REG_LIBCALL) | |
6764d250 BS |
1222 | *pnote = XEXP (*pnote, 1); |
1223 | else | |
1224 | pnote = &XEXP (*pnote, 1); | |
32131a9c | 1225 | } |
0304f787 | 1226 | |
2dfa9a87 MH |
1227 | #ifdef AUTO_INC_DEC |
1228 | add_auto_inc_notes (insn, PATTERN (insn)); | |
1229 | #endif | |
1230 | ||
0304f787 JL |
1231 | /* And simplify (subreg (reg)) if it appears as an operand. */ |
1232 | cleanup_subreg_operands (insn); | |
b60a8416 | 1233 | } |
32131a9c | 1234 | |
ab87f8c8 JL |
1235 | /* If we are doing stack checking, give a warning if this function's |
1236 | frame size is larger than we expect. */ | |
1237 | if (flag_stack_check && ! STACK_CHECK_BUILTIN) | |
1238 | { | |
1239 | HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; | |
05d10675 BS |
1240 | static int verbose_warned = 0; |
1241 | ||
ab87f8c8 JL |
1242 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1243 | if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i]) | |
1244 | size += UNITS_PER_WORD; | |
1245 | ||
1246 | if (size > STACK_CHECK_MAX_FRAME_SIZE) | |
05d10675 | 1247 | { |
ab87f8c8 JL |
1248 | warning ("frame size too large for reliable stack checking"); |
1249 | if (! verbose_warned) | |
1250 | { | |
1251 | warning ("try reducing the number of local variables"); | |
1252 | verbose_warned = 1; | |
1253 | } | |
1254 | } | |
1255 | } | |
1256 | ||
32131a9c | 1257 | /* Indicate that we no longer have known memory locations or constants. */ |
58d9f9d9 JL |
1258 | if (reg_equiv_constant) |
1259 | free (reg_equiv_constant); | |
32131a9c | 1260 | reg_equiv_constant = 0; |
58d9f9d9 JL |
1261 | if (reg_equiv_memory_loc) |
1262 | free (reg_equiv_memory_loc); | |
32131a9c | 1263 | reg_equiv_memory_loc = 0; |
5352b11a | 1264 | |
a68d4b75 BK |
1265 | if (real_known_ptr) |
1266 | free (real_known_ptr); | |
1267 | if (real_at_ptr) | |
1268 | free (real_at_ptr); | |
1269 | ||
56a65848 DB |
1270 | free (reg_equiv_mem); |
1271 | free (reg_equiv_init); | |
1272 | free (reg_equiv_address); | |
1273 | free (reg_max_ref_width); | |
03acd8f8 BS |
1274 | free (reg_old_renumber); |
1275 | free (pseudo_previous_regs); | |
1276 | free (pseudo_forbidden_regs); | |
56a65848 | 1277 | |
8b4f9969 JW |
1278 | CLEAR_HARD_REG_SET (used_spill_regs); |
1279 | for (i = 0; i < n_spills; i++) | |
1280 | SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); | |
1281 | ||
7609e720 BS |
1282 | /* Free all the insn_chain structures at once. */ |
1283 | obstack_free (&reload_obstack, reload_startobj); | |
1284 | unused_insn_chains = 0; | |
f1330226 | 1285 | fixup_abnormal_edges (); |
7609e720 | 1286 | |
e16e3291 UW |
1287 | /* Replacing pseudos with their memory equivalents might have |
1288 | created shared rtx. Subsequent passes would get confused | |
1289 | by this, so unshare everything here. */ | |
1290 | unshare_all_rtl_again (first); | |
1291 | ||
5352b11a | 1292 | return failure; |
32131a9c | 1293 | } |
1e5bd841 | 1294 | |
18a90182 BS |
1295 | /* Yet another special case. Unfortunately, reg-stack forces people to |
1296 | write incorrect clobbers in asm statements. These clobbers must not | |
1297 | cause the register to appear in bad_spill_regs, otherwise we'll call | |
1298 | fatal_insn later. We clear the corresponding regnos in the live | |
1299 | register sets to avoid this. | |
1300 | The whole thing is rather sick, I'm afraid. */ | |
efc9bd41 | 1301 | |
18a90182 BS |
1302 | static void |
1303 | maybe_fix_stack_asms () | |
1304 | { | |
1305 | #ifdef STACK_REGS | |
392dccb7 | 1306 | const char *constraints[MAX_RECOG_OPERANDS]; |
18a90182 BS |
1307 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
1308 | struct insn_chain *chain; | |
1309 | ||
1310 | for (chain = reload_insn_chain; chain != 0; chain = chain->next) | |
1311 | { | |
1312 | int i, noperands; | |
1313 | HARD_REG_SET clobbered, allowed; | |
1314 | rtx pat; | |
1315 | ||
2c3c49de | 1316 | if (! INSN_P (chain->insn) |
18a90182 BS |
1317 | || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) |
1318 | continue; | |
1319 | pat = PATTERN (chain->insn); | |
1320 | if (GET_CODE (pat) != PARALLEL) | |
1321 | continue; | |
1322 | ||
1323 | CLEAR_HARD_REG_SET (clobbered); | |
1324 | CLEAR_HARD_REG_SET (allowed); | |
1325 | ||
1326 | /* First, make a mask of all stack regs that are clobbered. */ | |
1327 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
1328 | { | |
1329 | rtx t = XVECEXP (pat, 0, i); | |
1330 | if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) | |
1331 | SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); | |
1332 | } | |
1333 | ||
1334 | /* Get the operand values and constraints out of the insn. */ | |
1ccbefce | 1335 | decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, |
18a90182 BS |
1336 | constraints, operand_mode); |
1337 | ||
1338 | /* For every operand, see what registers are allowed. */ | |
1339 | for (i = 0; i < noperands; i++) | |
1340 | { | |
6b9c6f4f | 1341 | const char *p = constraints[i]; |
18a90182 BS |
1342 | /* For every alternative, we compute the class of registers allowed |
1343 | for reloading in CLS, and merge its contents into the reg set | |
1344 | ALLOWED. */ | |
1345 | int cls = (int) NO_REGS; | |
1346 | ||
1347 | for (;;) | |
1348 | { | |
1349 | char c = *p++; | |
1350 | ||
1351 | if (c == '\0' || c == ',' || c == '#') | |
1352 | { | |
1353 | /* End of one alternative - mark the regs in the current | |
1354 | class, and reset the class. */ | |
1355 | IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); | |
1356 | cls = NO_REGS; | |
1357 | if (c == '#') | |
1358 | do { | |
1359 | c = *p++; | |
1360 | } while (c != '\0' && c != ','); | |
1361 | if (c == '\0') | |
1362 | break; | |
1363 | continue; | |
1364 | } | |
1365 | ||
1366 | switch (c) | |
1367 | { | |
1368 | case '=': case '+': case '*': case '%': case '?': case '!': | |
1369 | case '0': case '1': case '2': case '3': case '4': case 'm': | |
1370 | case '<': case '>': case 'V': case 'o': case '&': case 'E': | |
1371 | case 'F': case 's': case 'i': case 'n': case 'X': case 'I': | |
1372 | case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': | |
1373 | case 'P': | |
18a90182 BS |
1374 | break; |
1375 | ||
1376 | case 'p': | |
3dcc68a4 NC |
1377 | cls = (int) reg_class_subunion[cls] |
1378 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
18a90182 BS |
1379 | break; |
1380 | ||
1381 | case 'g': | |
1382 | case 'r': | |
1383 | cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; | |
1384 | break; | |
1385 | ||
1386 | default: | |
ccfc6cc8 UW |
1387 | if (EXTRA_ADDRESS_CONSTRAINT (c)) |
1388 | cls = (int) reg_class_subunion[cls] | |
1389 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
1390 | else | |
1391 | cls = (int) reg_class_subunion[cls] | |
1392 | [(int) REG_CLASS_FROM_LETTER (c)]; | |
18a90182 BS |
1393 | } |
1394 | } | |
1395 | } | |
1396 | /* Those of the registers which are clobbered, but allowed by the | |
1397 | constraints, must be usable as reload registers. So clear them | |
1398 | out of the life information. */ | |
1399 | AND_HARD_REG_SET (allowed, clobbered); | |
1400 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1401 | if (TEST_HARD_REG_BIT (allowed, i)) | |
1402 | { | |
239a0f5b BS |
1403 | CLEAR_REGNO_REG_SET (&chain->live_throughout, i); |
1404 | CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); | |
18a90182 BS |
1405 | } |
1406 | } | |
1407 | ||
1408 | #endif | |
1409 | } | |
03acd8f8 | 1410 | \f |
f5d8c9f4 BS |
1411 | /* Copy the global variables n_reloads and rld into the corresponding elts |
1412 | of CHAIN. */ | |
1413 | static void | |
1414 | copy_reloads (chain) | |
1415 | struct insn_chain *chain; | |
1416 | { | |
1417 | chain->n_reloads = n_reloads; | |
1418 | chain->rld | |
1419 | = (struct reload *) obstack_alloc (&reload_obstack, | |
1420 | n_reloads * sizeof (struct reload)); | |
1421 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); | |
1422 | reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
1423 | } | |
1424 | ||
03acd8f8 BS |
1425 | /* Walk the chain of insns, and determine for each whether it needs reloads |
1426 | and/or eliminations. Build the corresponding insns_need_reload list, and | |
1427 | set something_needs_elimination as appropriate. */ | |
1428 | static void | |
7609e720 | 1429 | calculate_needs_all_insns (global) |
1e5bd841 BS |
1430 | int global; |
1431 | { | |
7609e720 | 1432 | struct insn_chain **pprev_reload = &insns_need_reload; |
462561b7 | 1433 | struct insn_chain *chain, *next = 0; |
1e5bd841 | 1434 | |
03acd8f8 BS |
1435 | something_needs_elimination = 0; |
1436 | ||
f5d8c9f4 | 1437 | reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); |
462561b7 | 1438 | for (chain = reload_insn_chain; chain != 0; chain = next) |
1e5bd841 | 1439 | { |
67e61fe7 | 1440 | rtx insn = chain->insn; |
03acd8f8 | 1441 | |
462561b7 JJ |
1442 | next = chain->next; |
1443 | ||
f5d8c9f4 BS |
1444 | /* Clear out the shortcuts. */ |
1445 | chain->n_reloads = 0; | |
67e61fe7 BS |
1446 | chain->need_elim = 0; |
1447 | chain->need_reload = 0; | |
1448 | chain->need_operand_change = 0; | |
1e5bd841 | 1449 | |
03acd8f8 BS |
1450 | /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might |
1451 | include REG_LABEL), we need to see what effects this has on the | |
1452 | known offsets at labels. */ | |
1e5bd841 BS |
1453 | |
1454 | if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN | |
2c3c49de | 1455 | || (INSN_P (insn) && REG_NOTES (insn) != 0)) |
1e5bd841 BS |
1456 | set_label_offsets (insn, insn, 0); |
1457 | ||
2c3c49de | 1458 | if (INSN_P (insn)) |
1e5bd841 BS |
1459 | { |
1460 | rtx old_body = PATTERN (insn); | |
1461 | int old_code = INSN_CODE (insn); | |
1462 | rtx old_notes = REG_NOTES (insn); | |
1463 | int did_elimination = 0; | |
cb2afeb3 | 1464 | int operands_changed = 0; |
2b49ee39 R |
1465 | rtx set = single_set (insn); |
1466 | ||
1467 | /* Skip insns that only set an equivalence. */ | |
1468 | if (set && GET_CODE (SET_DEST (set)) == REG | |
1469 | && reg_renumber[REGNO (SET_DEST (set))] < 0 | |
1470 | && reg_equiv_constant[REGNO (SET_DEST (set))]) | |
67e61fe7 | 1471 | continue; |
1e5bd841 | 1472 | |
1e5bd841 | 1473 | /* If needed, eliminate any eliminable registers. */ |
2b49ee39 | 1474 | if (num_eliminable || num_eliminable_invariants) |
1e5bd841 BS |
1475 | did_elimination = eliminate_regs_in_insn (insn, 0); |
1476 | ||
1477 | /* Analyze the instruction. */ | |
cb2afeb3 R |
1478 | operands_changed = find_reloads (insn, 0, spill_indirect_levels, |
1479 | global, spill_reg_order); | |
1480 | ||
1481 | /* If a no-op set needs more than one reload, this is likely | |
1482 | to be something that needs input address reloads. We | |
1483 | can't get rid of this cleanly later, and it is of no use | |
1484 | anyway, so discard it now. | |
1485 | We only do this when expensive_optimizations is enabled, | |
1486 | since this complements reload inheritance / output | |
1487 | reload deletion, and it can make debugging harder. */ | |
1488 | if (flag_expensive_optimizations && n_reloads > 1) | |
1489 | { | |
1490 | rtx set = single_set (insn); | |
1491 | if (set | |
1492 | && SET_SRC (set) == SET_DEST (set) | |
1493 | && GET_CODE (SET_SRC (set)) == REG | |
1494 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1495 | { | |
ca6c03ca | 1496 | delete_insn (insn); |
462561b7 JJ |
1497 | /* Delete it from the reload chain */ |
1498 | if (chain->prev) | |
1499 | chain->prev->next = next; | |
1500 | else | |
1501 | reload_insn_chain = next; | |
1502 | if (next) | |
1503 | next->prev = chain->prev; | |
1504 | chain->next = unused_insn_chains; | |
1505 | unused_insn_chains = chain; | |
cb2afeb3 R |
1506 | continue; |
1507 | } | |
1508 | } | |
1509 | if (num_eliminable) | |
1510 | update_eliminable_offsets (); | |
1e5bd841 BS |
1511 | |
1512 | /* Remember for later shortcuts which insns had any reloads or | |
7609e720 BS |
1513 | register eliminations. */ |
1514 | chain->need_elim = did_elimination; | |
03acd8f8 BS |
1515 | chain->need_reload = n_reloads > 0; |
1516 | chain->need_operand_change = operands_changed; | |
1e5bd841 BS |
1517 | |
1518 | /* Discard any register replacements done. */ | |
1519 | if (did_elimination) | |
1520 | { | |
f5d8c9f4 | 1521 | obstack_free (&reload_obstack, reload_insn_firstobj); |
1e5bd841 BS |
1522 | PATTERN (insn) = old_body; |
1523 | INSN_CODE (insn) = old_code; | |
1524 | REG_NOTES (insn) = old_notes; | |
1525 | something_needs_elimination = 1; | |
1526 | } | |
1527 | ||
cb2afeb3 R |
1528 | something_needs_operands_changed |= operands_changed; |
1529 | ||
437a710d | 1530 | if (n_reloads != 0) |
7609e720 | 1531 | { |
f5d8c9f4 | 1532 | copy_reloads (chain); |
7609e720 BS |
1533 | *pprev_reload = chain; |
1534 | pprev_reload = &chain->next_need_reload; | |
7609e720 | 1535 | } |
1e5bd841 | 1536 | } |
1e5bd841 | 1537 | } |
7609e720 | 1538 | *pprev_reload = 0; |
1e5bd841 | 1539 | } |
f5d8c9f4 BS |
1540 | \f |
1541 | /* Comparison function for qsort to decide which of two reloads | |
1542 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
1e5bd841 | 1543 | |
f5d8c9f4 BS |
1544 | static int |
1545 | reload_reg_class_lower (r1p, r2p) | |
1546 | const PTR r1p; | |
1547 | const PTR r2p; | |
1e5bd841 | 1548 | { |
b3694847 SS |
1549 | int r1 = *(const short *) r1p, r2 = *(const short *) r2p; |
1550 | int t; | |
1e5bd841 | 1551 | |
f5d8c9f4 BS |
1552 | /* Consider required reloads before optional ones. */ |
1553 | t = rld[r1].optional - rld[r2].optional; | |
1554 | if (t != 0) | |
1555 | return t; | |
1e5bd841 | 1556 | |
f5d8c9f4 BS |
1557 | /* Count all solitary classes before non-solitary ones. */ |
1558 | t = ((reg_class_size[(int) rld[r2].class] == 1) | |
1559 | - (reg_class_size[(int) rld[r1].class] == 1)); | |
1560 | if (t != 0) | |
1561 | return t; | |
1e5bd841 | 1562 | |
f5d8c9f4 BS |
1563 | /* Aside from solitaires, consider all multi-reg groups first. */ |
1564 | t = rld[r2].nregs - rld[r1].nregs; | |
1565 | if (t != 0) | |
1566 | return t; | |
1e5bd841 | 1567 | |
f5d8c9f4 BS |
1568 | /* Consider reloads in order of increasing reg-class number. */ |
1569 | t = (int) rld[r1].class - (int) rld[r2].class; | |
1570 | if (t != 0) | |
1571 | return t; | |
1e5bd841 | 1572 | |
f5d8c9f4 BS |
1573 | /* If reloads are equally urgent, sort by reload number, |
1574 | so that the results of qsort leave nothing to chance. */ | |
1575 | return r1 - r2; | |
1576 | } | |
1577 | \f | |
1578 | /* The cost of spilling each hard reg. */ | |
1579 | static int spill_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1580 | |
f5d8c9f4 BS |
1581 | /* When spilling multiple hard registers, we use SPILL_COST for the first |
1582 | spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST | |
1583 | only the first hard reg for a multi-reg pseudo. */ | |
1584 | static int spill_add_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1585 | |
f5d8c9f4 | 1586 | /* Update the spill cost arrays, considering that pseudo REG is live. */ |
770ae6cc | 1587 | |
f5d8c9f4 BS |
1588 | static void |
1589 | count_pseudo (reg) | |
1590 | int reg; | |
1591 | { | |
b2aec5c0 | 1592 | int freq = REG_FREQ (reg); |
f5d8c9f4 BS |
1593 | int r = reg_renumber[reg]; |
1594 | int nregs; | |
1e5bd841 | 1595 | |
f5d8c9f4 BS |
1596 | if (REGNO_REG_SET_P (&pseudos_counted, reg) |
1597 | || REGNO_REG_SET_P (&spilled_pseudos, reg)) | |
1598 | return; | |
1e5bd841 | 1599 | |
f5d8c9f4 | 1600 | SET_REGNO_REG_SET (&pseudos_counted, reg); |
1e5bd841 | 1601 | |
f5d8c9f4 BS |
1602 | if (r < 0) |
1603 | abort (); | |
1d7254c5 | 1604 | |
b2aec5c0 | 1605 | spill_add_cost[r] += freq; |
1e5bd841 | 1606 | |
f5d8c9f4 BS |
1607 | nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); |
1608 | while (nregs-- > 0) | |
b2aec5c0 | 1609 | spill_cost[r + nregs] += freq; |
f5d8c9f4 | 1610 | } |
1e5bd841 | 1611 | |
f5d8c9f4 BS |
1612 | /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the |
1613 | contents of BAD_SPILL_REGS for the insn described by CHAIN. */ | |
efc9bd41 | 1614 | |
f5d8c9f4 BS |
1615 | static void |
1616 | order_regs_for_reload (chain) | |
1617 | struct insn_chain *chain; | |
1618 | { | |
fbd40359 | 1619 | int i; |
efc9bd41 RK |
1620 | HARD_REG_SET used_by_pseudos; |
1621 | HARD_REG_SET used_by_pseudos2; | |
1e5bd841 | 1622 | |
efc9bd41 | 1623 | COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set); |
1e5bd841 | 1624 | |
f5d8c9f4 BS |
1625 | memset (spill_cost, 0, sizeof spill_cost); |
1626 | memset (spill_add_cost, 0, sizeof spill_add_cost); | |
1e5bd841 | 1627 | |
f5d8c9f4 | 1628 | /* Count number of uses of each hard reg by pseudo regs allocated to it |
efc9bd41 RK |
1629 | and then order them by decreasing use. First exclude hard registers |
1630 | that are live in or across this insn. */ | |
1631 | ||
1632 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); | |
1633 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
1634 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos); | |
1635 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2); | |
1e5bd841 | 1636 | |
f5d8c9f4 BS |
1637 | /* Now find out which pseudos are allocated to it, and update |
1638 | hard_reg_n_uses. */ | |
1639 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1640 | |
f5d8c9f4 | 1641 | EXECUTE_IF_SET_IN_REG_SET |
fbd40359 | 1642 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, |
f5d8c9f4 | 1643 | { |
fbd40359 | 1644 | count_pseudo (i); |
f5d8c9f4 BS |
1645 | }); |
1646 | EXECUTE_IF_SET_IN_REG_SET | |
fbd40359 | 1647 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, |
f5d8c9f4 | 1648 | { |
fbd40359 | 1649 | count_pseudo (i); |
f5d8c9f4 BS |
1650 | }); |
1651 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1652 | } |
03acd8f8 | 1653 | \f |
f5d8c9f4 BS |
1654 | /* Vector of reload-numbers showing the order in which the reloads should |
1655 | be processed. */ | |
1656 | static short reload_order[MAX_RELOADS]; | |
1e5bd841 | 1657 | |
f5d8c9f4 BS |
1658 | /* This is used to keep track of the spill regs used in one insn. */ |
1659 | static HARD_REG_SET used_spill_regs_local; | |
03acd8f8 | 1660 | |
f5d8c9f4 BS |
1661 | /* We decided to spill hard register SPILLED, which has a size of |
1662 | SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, | |
1663 | is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will | |
1664 | update SPILL_COST/SPILL_ADD_COST. */ | |
770ae6cc | 1665 | |
03acd8f8 | 1666 | static void |
f5d8c9f4 BS |
1667 | count_spilled_pseudo (spilled, spilled_nregs, reg) |
1668 | int spilled, spilled_nregs, reg; | |
1e5bd841 | 1669 | { |
f5d8c9f4 BS |
1670 | int r = reg_renumber[reg]; |
1671 | int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); | |
1e5bd841 | 1672 | |
f5d8c9f4 BS |
1673 | if (REGNO_REG_SET_P (&spilled_pseudos, reg) |
1674 | || spilled + spilled_nregs <= r || r + nregs <= spilled) | |
1675 | return; | |
1e5bd841 | 1676 | |
f5d8c9f4 | 1677 | SET_REGNO_REG_SET (&spilled_pseudos, reg); |
1e5bd841 | 1678 | |
b2aec5c0 | 1679 | spill_add_cost[r] -= REG_FREQ (reg); |
f5d8c9f4 | 1680 | while (nregs-- > 0) |
b2aec5c0 | 1681 | spill_cost[r + nregs] -= REG_FREQ (reg); |
1e5bd841 BS |
1682 | } |
1683 | ||
f5d8c9f4 | 1684 | /* Find reload register to use for reload number ORDER. */ |
03acd8f8 | 1685 | |
f5d8c9f4 | 1686 | static int |
e04ca094 | 1687 | find_reg (chain, order) |
03acd8f8 | 1688 | struct insn_chain *chain; |
f5d8c9f4 | 1689 | int order; |
1e5bd841 | 1690 | { |
f5d8c9f4 BS |
1691 | int rnum = reload_order[order]; |
1692 | struct reload *rl = rld + rnum; | |
1693 | int best_cost = INT_MAX; | |
1694 | int best_reg = -1; | |
770ae6cc RK |
1695 | unsigned int i, j; |
1696 | int k; | |
f5d8c9f4 BS |
1697 | HARD_REG_SET not_usable; |
1698 | HARD_REG_SET used_by_other_reload; | |
1e5bd841 | 1699 | |
f5d8c9f4 BS |
1700 | COPY_HARD_REG_SET (not_usable, bad_spill_regs); |
1701 | IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); | |
1702 | IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]); | |
1703 | ||
1704 | CLEAR_HARD_REG_SET (used_by_other_reload); | |
770ae6cc | 1705 | for (k = 0; k < order; k++) |
1e5bd841 | 1706 | { |
770ae6cc RK |
1707 | int other = reload_order[k]; |
1708 | ||
f5d8c9f4 BS |
1709 | if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) |
1710 | for (j = 0; j < rld[other].nregs; j++) | |
1711 | SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); | |
1712 | } | |
1e5bd841 | 1713 | |
f5d8c9f4 BS |
1714 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1715 | { | |
770ae6cc RK |
1716 | unsigned int regno = i; |
1717 | ||
f5d8c9f4 BS |
1718 | if (! TEST_HARD_REG_BIT (not_usable, regno) |
1719 | && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) | |
1720 | && HARD_REGNO_MODE_OK (regno, rl->mode)) | |
1e5bd841 | 1721 | { |
f5d8c9f4 BS |
1722 | int this_cost = spill_cost[regno]; |
1723 | int ok = 1; | |
770ae6cc | 1724 | unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode); |
1e5bd841 | 1725 | |
f5d8c9f4 BS |
1726 | for (j = 1; j < this_nregs; j++) |
1727 | { | |
1728 | this_cost += spill_add_cost[regno + j]; | |
1729 | if ((TEST_HARD_REG_BIT (not_usable, regno + j)) | |
1730 | || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) | |
1731 | ok = 0; | |
1732 | } | |
1733 | if (! ok) | |
1734 | continue; | |
1735 | if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno) | |
1736 | this_cost--; | |
1737 | if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno) | |
1738 | this_cost--; | |
1739 | if (this_cost < best_cost | |
1740 | /* Among registers with equal cost, prefer caller-saved ones, or | |
1741 | use REG_ALLOC_ORDER if it is defined. */ | |
1742 | || (this_cost == best_cost | |
1743 | #ifdef REG_ALLOC_ORDER | |
1744 | && (inv_reg_alloc_order[regno] | |
1745 | < inv_reg_alloc_order[best_reg]) | |
1746 | #else | |
1747 | && call_used_regs[regno] | |
1748 | && ! call_used_regs[best_reg] | |
1749 | #endif | |
1750 | )) | |
1751 | { | |
1752 | best_reg = regno; | |
1753 | best_cost = this_cost; | |
1e5bd841 BS |
1754 | } |
1755 | } | |
1756 | } | |
f5d8c9f4 BS |
1757 | if (best_reg == -1) |
1758 | return 0; | |
770ae6cc | 1759 | |
e04ca094 JL |
1760 | if (rtl_dump_file) |
1761 | fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum); | |
770ae6cc | 1762 | |
f5d8c9f4 BS |
1763 | rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode); |
1764 | rl->regno = best_reg; | |
1e5bd841 | 1765 | |
f5d8c9f4 | 1766 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1767 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1768 | { |
1769 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1770 | }); | |
770ae6cc | 1771 | |
f5d8c9f4 | 1772 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1773 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1774 | { |
1775 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1776 | }); | |
03acd8f8 | 1777 | |
f5d8c9f4 BS |
1778 | for (i = 0; i < rl->nregs; i++) |
1779 | { | |
1780 | if (spill_cost[best_reg + i] != 0 | |
1781 | || spill_add_cost[best_reg + i] != 0) | |
1782 | abort (); | |
1783 | SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); | |
1784 | } | |
1785 | return 1; | |
03acd8f8 BS |
1786 | } |
1787 | ||
1788 | /* Find more reload regs to satisfy the remaining need of an insn, which | |
1789 | is given by CHAIN. | |
1e5bd841 BS |
1790 | Do it by ascending class number, since otherwise a reg |
1791 | might be spilled for a big class and might fail to count | |
f5d8c9f4 | 1792 | for a smaller class even though it belongs to that class. */ |
1e5bd841 | 1793 | |
03acd8f8 | 1794 | static void |
e04ca094 | 1795 | find_reload_regs (chain) |
03acd8f8 | 1796 | struct insn_chain *chain; |
1e5bd841 | 1797 | { |
f5d8c9f4 | 1798 | int i; |
1e5bd841 | 1799 | |
f5d8c9f4 BS |
1800 | /* In order to be certain of getting the registers we need, |
1801 | we must sort the reloads into order of increasing register class. | |
1802 | Then our grabbing of reload registers will parallel the process | |
1803 | that provided the reload registers. */ | |
1804 | for (i = 0; i < chain->n_reloads; i++) | |
1e5bd841 | 1805 | { |
f5d8c9f4 BS |
1806 | /* Show whether this reload already has a hard reg. */ |
1807 | if (chain->rld[i].reg_rtx) | |
1e5bd841 | 1808 | { |
f5d8c9f4 BS |
1809 | int regno = REGNO (chain->rld[i].reg_rtx); |
1810 | chain->rld[i].regno = regno; | |
770ae6cc RK |
1811 | chain->rld[i].nregs |
1812 | = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx)); | |
1e5bd841 | 1813 | } |
f5d8c9f4 BS |
1814 | else |
1815 | chain->rld[i].regno = -1; | |
1816 | reload_order[i] = i; | |
1817 | } | |
1e5bd841 | 1818 | |
f5d8c9f4 BS |
1819 | n_reloads = chain->n_reloads; |
1820 | memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); | |
1e5bd841 | 1821 | |
f5d8c9f4 | 1822 | CLEAR_HARD_REG_SET (used_spill_regs_local); |
03acd8f8 | 1823 | |
e04ca094 JL |
1824 | if (rtl_dump_file) |
1825 | fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn)); | |
1e5bd841 | 1826 | |
f5d8c9f4 | 1827 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); |
1e5bd841 | 1828 | |
f5d8c9f4 | 1829 | /* Compute the order of preference for hard registers to spill. */ |
1e5bd841 | 1830 | |
f5d8c9f4 | 1831 | order_regs_for_reload (chain); |
1e5bd841 | 1832 | |
f5d8c9f4 BS |
1833 | for (i = 0; i < n_reloads; i++) |
1834 | { | |
1835 | int r = reload_order[i]; | |
1e5bd841 | 1836 | |
f5d8c9f4 BS |
1837 | /* Ignore reloads that got marked inoperative. */ |
1838 | if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) | |
1839 | && ! rld[r].optional | |
1840 | && rld[r].regno == -1) | |
e04ca094 | 1841 | if (! find_reg (chain, i)) |
f5d8c9f4 | 1842 | { |
ecf3151a | 1843 | spill_failure (chain->insn, rld[r].class); |
f5d8c9f4 | 1844 | failure = 1; |
03acd8f8 | 1845 | return; |
f5d8c9f4 | 1846 | } |
1e5bd841 | 1847 | } |
05d10675 | 1848 | |
f5d8c9f4 BS |
1849 | COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local); |
1850 | IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local); | |
03acd8f8 | 1851 | |
f5d8c9f4 | 1852 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
1e5bd841 BS |
1853 | } |
1854 | ||
f5d8c9f4 | 1855 | static void |
e04ca094 | 1856 | select_reload_regs () |
09dd1133 | 1857 | { |
f5d8c9f4 | 1858 | struct insn_chain *chain; |
09dd1133 | 1859 | |
f5d8c9f4 BS |
1860 | /* Try to satisfy the needs for each insn. */ |
1861 | for (chain = insns_need_reload; chain != 0; | |
1862 | chain = chain->next_need_reload) | |
e04ca094 | 1863 | find_reload_regs (chain); |
09dd1133 | 1864 | } |
32131a9c | 1865 | \f |
437a710d BS |
1866 | /* Delete all insns that were inserted by emit_caller_save_insns during |
1867 | this iteration. */ | |
1868 | static void | |
7609e720 | 1869 | delete_caller_save_insns () |
437a710d | 1870 | { |
7609e720 | 1871 | struct insn_chain *c = reload_insn_chain; |
437a710d | 1872 | |
7609e720 | 1873 | while (c != 0) |
437a710d | 1874 | { |
7609e720 | 1875 | while (c != 0 && c->is_caller_save_insn) |
437a710d | 1876 | { |
7609e720 BS |
1877 | struct insn_chain *next = c->next; |
1878 | rtx insn = c->insn; | |
1879 | ||
7609e720 BS |
1880 | if (c == reload_insn_chain) |
1881 | reload_insn_chain = next; | |
ca6c03ca | 1882 | delete_insn (insn); |
7609e720 BS |
1883 | |
1884 | if (next) | |
1885 | next->prev = c->prev; | |
1886 | if (c->prev) | |
1887 | c->prev->next = next; | |
1888 | c->next = unused_insn_chains; | |
1889 | unused_insn_chains = c; | |
1890 | c = next; | |
437a710d | 1891 | } |
7609e720 BS |
1892 | if (c != 0) |
1893 | c = c->next; | |
437a710d BS |
1894 | } |
1895 | } | |
1896 | \f | |
5352b11a RS |
1897 | /* Handle the failure to find a register to spill. |
1898 | INSN should be one of the insns which needed this particular spill reg. */ | |
1899 | ||
1900 | static void | |
ecf3151a | 1901 | spill_failure (insn, class) |
5352b11a | 1902 | rtx insn; |
ecf3151a | 1903 | enum reg_class class; |
5352b11a | 1904 | { |
ecf3151a | 1905 | static const char *const reg_class_names[] = REG_CLASS_NAMES; |
5352b11a | 1906 | if (asm_noperands (PATTERN (insn)) >= 0) |
1f978f5f | 1907 | error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'", |
ecf3151a | 1908 | reg_class_names[class]); |
5352b11a | 1909 | else |
ecf3151a | 1910 | { |
1f978f5f | 1911 | error ("unable to find a register to spill in class `%s'", |
ecf3151a | 1912 | reg_class_names[class]); |
1f978f5f | 1913 | fatal_insn ("this is the insn:", insn); |
ecf3151a | 1914 | } |
5352b11a | 1915 | } |
32131a9c RK |
1916 | \f |
1917 | /* Delete an unneeded INSN and any previous insns who sole purpose is loading | |
1918 | data that is dead in INSN. */ | |
1919 | ||
1920 | static void | |
1921 | delete_dead_insn (insn) | |
1922 | rtx insn; | |
1923 | { | |
1924 | rtx prev = prev_real_insn (insn); | |
1925 | rtx prev_dest; | |
1926 | ||
1927 | /* If the previous insn sets a register that dies in our insn, delete it | |
1928 | too. */ | |
1929 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
1930 | && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) | |
1931 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
b294ca38 R |
1932 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) |
1933 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
32131a9c RK |
1934 | delete_dead_insn (prev); |
1935 | ||
1936 | PUT_CODE (insn, NOTE); | |
1937 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1938 | NOTE_SOURCE_FILE (insn) = 0; | |
1939 | } | |
1940 | ||
1941 | /* Modify the home of pseudo-reg I. | |
1942 | The new home is present in reg_renumber[I]. | |
1943 | ||
1944 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
1945 | or it may be -1, meaning there is none or it is not relevant. | |
1946 | This is used so that all pseudos spilled from a given hard reg | |
1947 | can share one stack slot. */ | |
1948 | ||
1949 | static void | |
1950 | alter_reg (i, from_reg) | |
b3694847 | 1951 | int i; |
32131a9c RK |
1952 | int from_reg; |
1953 | { | |
1954 | /* When outputting an inline function, this can happen | |
1955 | for a reg that isn't actually used. */ | |
1956 | if (regno_reg_rtx[i] == 0) | |
1957 | return; | |
1958 | ||
1959 | /* If the reg got changed to a MEM at rtl-generation time, | |
1960 | ignore it. */ | |
1961 | if (GET_CODE (regno_reg_rtx[i]) != REG) | |
1962 | return; | |
1963 | ||
1964 | /* Modify the reg-rtx to contain the new hard reg | |
1965 | number or else to contain its pseudo reg number. */ | |
1966 | REGNO (regno_reg_rtx[i]) | |
1967 | = reg_renumber[i] >= 0 ? reg_renumber[i] : i; | |
1968 | ||
1969 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
1970 | allocate a stack slot for it. */ | |
1971 | ||
1972 | if (reg_renumber[i] < 0 | |
b1f21e0a | 1973 | && REG_N_REFS (i) > 0 |
32131a9c RK |
1974 | && reg_equiv_constant[i] == 0 |
1975 | && reg_equiv_memory_loc[i] == 0) | |
1976 | { | |
b3694847 | 1977 | rtx x; |
770ae6cc RK |
1978 | unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); |
1979 | unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]); | |
32131a9c RK |
1980 | int adjust = 0; |
1981 | ||
1982 | /* Each pseudo reg has an inherent size which comes from its own mode, | |
1983 | and a total size which provides room for paradoxical subregs | |
1984 | which refer to the pseudo reg in wider modes. | |
1985 | ||
1986 | We can use a slot already allocated if it provides both | |
1987 | enough inherent space and enough total space. | |
1988 | Otherwise, we allocate a new slot, making sure that it has no less | |
1989 | inherent space, and no less total space, then the previous slot. */ | |
1990 | if (from_reg == -1) | |
1991 | { | |
1992 | /* No known place to spill from => no slot to reuse. */ | |
cabcf079 ILT |
1993 | x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, |
1994 | inherent_size == total_size ? 0 : -1); | |
f76b9db2 | 1995 | if (BYTES_BIG_ENDIAN) |
02db8dd0 RK |
1996 | /* Cancel the big-endian correction done in assign_stack_local. |
1997 | Get the address of the beginning of the slot. | |
1998 | This is so we can do a big-endian correction unconditionally | |
1999 | below. */ | |
2000 | adjust = inherent_size - total_size; | |
2001 | ||
2002 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); | |
3bdf5ad1 RK |
2003 | |
2004 | /* Nothing can alias this slot except this pseudo. */ | |
ba4828e0 | 2005 | set_mem_alias_set (x, new_alias_set ()); |
32131a9c | 2006 | } |
3bdf5ad1 | 2007 | |
32131a9c RK |
2008 | /* Reuse a stack slot if possible. */ |
2009 | else if (spill_stack_slot[from_reg] != 0 | |
2010 | && spill_stack_slot_width[from_reg] >= total_size | |
2011 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
2012 | >= inherent_size)) | |
2013 | x = spill_stack_slot[from_reg]; | |
3bdf5ad1 | 2014 | |
32131a9c RK |
2015 | /* Allocate a bigger slot. */ |
2016 | else | |
2017 | { | |
2018 | /* Compute maximum size needed, both for inherent size | |
2019 | and for total size. */ | |
2020 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); | |
4f2d3674 | 2021 | rtx stack_slot; |
3bdf5ad1 | 2022 | |
32131a9c RK |
2023 | if (spill_stack_slot[from_reg]) |
2024 | { | |
2025 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
2026 | > inherent_size) | |
2027 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
2028 | if (spill_stack_slot_width[from_reg] > total_size) | |
2029 | total_size = spill_stack_slot_width[from_reg]; | |
2030 | } | |
3bdf5ad1 | 2031 | |
32131a9c | 2032 | /* Make a slot with that size. */ |
cabcf079 ILT |
2033 | x = assign_stack_local (mode, total_size, |
2034 | inherent_size == total_size ? 0 : -1); | |
4f2d3674 | 2035 | stack_slot = x; |
3bdf5ad1 RK |
2036 | |
2037 | /* All pseudos mapped to this slot can alias each other. */ | |
2038 | if (spill_stack_slot[from_reg]) | |
ba4828e0 | 2039 | set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg])); |
3bdf5ad1 | 2040 | else |
ba4828e0 | 2041 | set_mem_alias_set (x, new_alias_set ()); |
3bdf5ad1 | 2042 | |
f76b9db2 ILT |
2043 | if (BYTES_BIG_ENDIAN) |
2044 | { | |
2045 | /* Cancel the big-endian correction done in assign_stack_local. | |
2046 | Get the address of the beginning of the slot. | |
2047 | This is so we can do a big-endian correction unconditionally | |
2048 | below. */ | |
2049 | adjust = GET_MODE_SIZE (mode) - total_size; | |
4f2d3674 | 2050 | if (adjust) |
8ac61af7 RK |
2051 | stack_slot |
2052 | = adjust_address_nv (x, mode_for_size (total_size | |
38a448ca RH |
2053 | * BITS_PER_UNIT, |
2054 | MODE_INT, 1), | |
8ac61af7 | 2055 | adjust); |
f76b9db2 | 2056 | } |
3bdf5ad1 | 2057 | |
4f2d3674 | 2058 | spill_stack_slot[from_reg] = stack_slot; |
32131a9c RK |
2059 | spill_stack_slot_width[from_reg] = total_size; |
2060 | } | |
2061 | ||
32131a9c RK |
2062 | /* On a big endian machine, the "address" of the slot |
2063 | is the address of the low part that fits its inherent mode. */ | |
f76b9db2 | 2064 | if (BYTES_BIG_ENDIAN && inherent_size < total_size) |
32131a9c | 2065 | adjust += (total_size - inherent_size); |
32131a9c RK |
2066 | |
2067 | /* If we have any adjustment to make, or if the stack slot is the | |
2068 | wrong mode, make a new stack slot. */ | |
1285011e RK |
2069 | x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); |
2070 | ||
2071 | /* If we have a decl for the original register, set it for the | |
2072 | memory. If this is a shared MEM, make a copy. */ | |
2073 | if (REGNO_DECL (i)) | |
2074 | { | |
a20fd5ac | 2075 | rtx decl = DECL_RTL_IF_SET (REGNO_DECL (i)); |
1285011e | 2076 | |
a20fd5ac JJ |
2077 | /* We can do this only for the DECLs home pseudo, not for |
2078 | any copies of it, since otherwise when the stack slot | |
2079 | is reused, nonoverlapping_memrefs_p might think they | |
2080 | cannot overlap. */ | |
2081 | if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i) | |
2082 | { | |
2083 | if (from_reg != -1 && spill_stack_slot[from_reg] == x) | |
2084 | x = copy_rtx (x); | |
2085 | ||
2086 | set_mem_expr (x, REGNO_DECL (i)); | |
2087 | } | |
1285011e | 2088 | } |
32131a9c | 2089 | |
6d2f8887 | 2090 | /* Save the stack slot for later. */ |
32131a9c RK |
2091 | reg_equiv_memory_loc[i] = x; |
2092 | } | |
2093 | } | |
2094 | ||
2095 | /* Mark the slots in regs_ever_live for the hard regs | |
2096 | used by pseudo-reg number REGNO. */ | |
2097 | ||
2098 | void | |
2099 | mark_home_live (regno) | |
2100 | int regno; | |
2101 | { | |
b3694847 | 2102 | int i, lim; |
770ae6cc | 2103 | |
32131a9c RK |
2104 | i = reg_renumber[regno]; |
2105 | if (i < 0) | |
2106 | return; | |
2107 | lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); | |
2108 | while (i < lim) | |
2109 | regs_ever_live[i++] = 1; | |
2110 | } | |
2111 | \f | |
2112 | /* This function handles the tracking of elimination offsets around branches. | |
2113 | ||
2114 | X is a piece of RTL being scanned. | |
2115 | ||
2116 | INSN is the insn that it came from, if any. | |
2117 | ||
2118 | INITIAL_P is non-zero if we are to set the offset to be the initial | |
2119 | offset and zero if we are setting the offset of the label to be the | |
2120 | current offset. */ | |
2121 | ||
2122 | static void | |
2123 | set_label_offsets (x, insn, initial_p) | |
2124 | rtx x; | |
2125 | rtx insn; | |
2126 | int initial_p; | |
2127 | { | |
2128 | enum rtx_code code = GET_CODE (x); | |
2129 | rtx tem; | |
e51712db | 2130 | unsigned int i; |
32131a9c RK |
2131 | struct elim_table *p; |
2132 | ||
2133 | switch (code) | |
2134 | { | |
2135 | case LABEL_REF: | |
8be386d9 RS |
2136 | if (LABEL_REF_NONLOCAL_P (x)) |
2137 | return; | |
2138 | ||
32131a9c RK |
2139 | x = XEXP (x, 0); |
2140 | ||
0f41302f | 2141 | /* ... fall through ... */ |
32131a9c RK |
2142 | |
2143 | case CODE_LABEL: | |
2144 | /* If we know nothing about this label, set the desired offsets. Note | |
2145 | that this sets the offset at a label to be the offset before a label | |
2146 | if we don't know anything about the label. This is not correct for | |
2147 | the label after a BARRIER, but is the best guess we can make. If | |
2148 | we guessed wrong, we will suppress an elimination that might have | |
2149 | been possible had we been able to guess correctly. */ | |
2150 | ||
2151 | if (! offsets_known_at[CODE_LABEL_NUMBER (x)]) | |
2152 | { | |
2153 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
2154 | offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2155 | = (initial_p ? reg_eliminate[i].initial_offset | |
2156 | : reg_eliminate[i].offset); | |
2157 | offsets_known_at[CODE_LABEL_NUMBER (x)] = 1; | |
2158 | } | |
2159 | ||
2160 | /* Otherwise, if this is the definition of a label and it is | |
d45cf215 | 2161 | preceded by a BARRIER, set our offsets to the known offset of |
32131a9c RK |
2162 | that label. */ |
2163 | ||
2164 | else if (x == insn | |
2165 | && (tem = prev_nonnote_insn (insn)) != 0 | |
2166 | && GET_CODE (tem) == BARRIER) | |
1f3b1e1a | 2167 | set_offsets_for_label (insn); |
32131a9c RK |
2168 | else |
2169 | /* If neither of the above cases is true, compare each offset | |
2170 | with those previously recorded and suppress any eliminations | |
2171 | where the offsets disagree. */ | |
a8fdc208 | 2172 | |
32131a9c RK |
2173 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) |
2174 | if (offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2175 | != (initial_p ? reg_eliminate[i].initial_offset | |
2176 | : reg_eliminate[i].offset)) | |
2177 | reg_eliminate[i].can_eliminate = 0; | |
2178 | ||
2179 | return; | |
2180 | ||
2181 | case JUMP_INSN: | |
2182 | set_label_offsets (PATTERN (insn), insn, initial_p); | |
2183 | ||
0f41302f | 2184 | /* ... fall through ... */ |
32131a9c RK |
2185 | |
2186 | case INSN: | |
2187 | case CALL_INSN: | |
2188 | /* Any labels mentioned in REG_LABEL notes can be branched to indirectly | |
2189 | and hence must have all eliminations at their initial offsets. */ | |
2190 | for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) | |
2191 | if (REG_NOTE_KIND (tem) == REG_LABEL) | |
2192 | set_label_offsets (XEXP (tem, 0), insn, 1); | |
2193 | return; | |
2194 | ||
0c0ba09c | 2195 | case PARALLEL: |
32131a9c RK |
2196 | case ADDR_VEC: |
2197 | case ADDR_DIFF_VEC: | |
0c0ba09c JJ |
2198 | /* Each of the labels in the parallel or address vector must be |
2199 | at their initial offsets. We want the first field for PARALLEL | |
2200 | and ADDR_VEC and the second field for ADDR_DIFF_VEC. */ | |
32131a9c | 2201 | |
e51712db | 2202 | for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) |
32131a9c RK |
2203 | set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), |
2204 | insn, initial_p); | |
2205 | return; | |
2206 | ||
2207 | case SET: | |
2208 | /* We only care about setting PC. If the source is not RETURN, | |
2209 | IF_THEN_ELSE, or a label, disable any eliminations not at | |
2210 | their initial offsets. Similarly if any arm of the IF_THEN_ELSE | |
2211 | isn't one of those possibilities. For branches to a label, | |
2212 | call ourselves recursively. | |
2213 | ||
2214 | Note that this can disable elimination unnecessarily when we have | |
2215 | a non-local goto since it will look like a non-constant jump to | |
2216 | someplace in the current function. This isn't a significant | |
2217 | problem since such jumps will normally be when all elimination | |
2218 | pairs are back to their initial offsets. */ | |
2219 | ||
2220 | if (SET_DEST (x) != pc_rtx) | |
2221 | return; | |
2222 | ||
2223 | switch (GET_CODE (SET_SRC (x))) | |
2224 | { | |
2225 | case PC: | |
2226 | case RETURN: | |
2227 | return; | |
2228 | ||
2229 | case LABEL_REF: | |
2230 | set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); | |
2231 | return; | |
2232 | ||
2233 | case IF_THEN_ELSE: | |
2234 | tem = XEXP (SET_SRC (x), 1); | |
2235 | if (GET_CODE (tem) == LABEL_REF) | |
2236 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2237 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2238 | break; | |
2239 | ||
2240 | tem = XEXP (SET_SRC (x), 2); | |
2241 | if (GET_CODE (tem) == LABEL_REF) | |
2242 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2243 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2244 | break; | |
2245 | return; | |
e9a25f70 JL |
2246 | |
2247 | default: | |
2248 | break; | |
32131a9c RK |
2249 | } |
2250 | ||
2251 | /* If we reach here, all eliminations must be at their initial | |
2252 | offset because we are doing a jump to a variable address. */ | |
2253 | for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) | |
2254 | if (p->offset != p->initial_offset) | |
2255 | p->can_eliminate = 0; | |
e9a25f70 | 2256 | break; |
05d10675 | 2257 | |
e9a25f70 JL |
2258 | default: |
2259 | break; | |
32131a9c RK |
2260 | } |
2261 | } | |
2262 | \f | |
a8fdc208 | 2263 | /* Scan X and replace any eliminable registers (such as fp) with a |
32131a9c RK |
2264 | replacement (such as sp), plus an offset. |
2265 | ||
2266 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
2267 | much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a | |
2268 | MEM, we are allowed to replace a sum of a register and the constant zero | |
2269 | with the register, which we cannot do outside a MEM. In addition, we need | |
2270 | to record the fact that a register is referenced outside a MEM. | |
2271 | ||
ff32812a | 2272 | If INSN is an insn, it is the insn containing X. If we replace a REG |
32131a9c RK |
2273 | in a SET_DEST with an equivalent MEM and INSN is non-zero, write a |
2274 | CLOBBER of the pseudo after INSN so find_equiv_regs will know that | |
38e01259 | 2275 | the REG is being modified. |
32131a9c | 2276 | |
ff32812a RS |
2277 | Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). |
2278 | That's used when we eliminate in expressions stored in notes. | |
2279 | This means, do not set ref_outside_mem even if the reference | |
2280 | is outside of MEMs. | |
2281 | ||
32131a9c RK |
2282 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had |
2283 | replacements done assuming all offsets are at their initial values. If | |
2284 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | |
2285 | encounter, return the actual location so that find_reloads will do | |
2286 | the proper thing. */ | |
2287 | ||
2288 | rtx | |
1914f5da | 2289 | eliminate_regs (x, mem_mode, insn) |
32131a9c RK |
2290 | rtx x; |
2291 | enum machine_mode mem_mode; | |
2292 | rtx insn; | |
2293 | { | |
2294 | enum rtx_code code = GET_CODE (x); | |
2295 | struct elim_table *ep; | |
2296 | int regno; | |
2297 | rtx new; | |
2298 | int i, j; | |
6f7d635c | 2299 | const char *fmt; |
32131a9c RK |
2300 | int copied = 0; |
2301 | ||
d6633f01 NS |
2302 | if (! current_function_decl) |
2303 | return x; | |
9969bb2c | 2304 | |
32131a9c RK |
2305 | switch (code) |
2306 | { | |
2307 | case CONST_INT: | |
2308 | case CONST_DOUBLE: | |
69ef87e2 | 2309 | case CONST_VECTOR: |
32131a9c RK |
2310 | case CONST: |
2311 | case SYMBOL_REF: | |
2312 | case CODE_LABEL: | |
2313 | case PC: | |
2314 | case CC0: | |
2315 | case ASM_INPUT: | |
2316 | case ADDR_VEC: | |
2317 | case ADDR_DIFF_VEC: | |
2318 | case RETURN: | |
2319 | return x; | |
2320 | ||
e9a25f70 JL |
2321 | case ADDRESSOF: |
2322 | /* This is only for the benefit of the debugging backends, which call | |
2323 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2324 | removed after CSE. */ | |
1914f5da | 2325 | new = eliminate_regs (XEXP (x, 0), 0, insn); |
e9a25f70 JL |
2326 | if (GET_CODE (new) == MEM) |
2327 | return XEXP (new, 0); | |
2328 | return x; | |
2329 | ||
32131a9c RK |
2330 | case REG: |
2331 | regno = REGNO (x); | |
2332 | ||
2333 | /* First handle the case where we encounter a bare register that | |
2334 | is eliminable. Replace it with a PLUS. */ | |
2335 | if (regno < FIRST_PSEUDO_REGISTER) | |
2336 | { | |
2337 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2338 | ep++) | |
2339 | if (ep->from_rtx == x && ep->can_eliminate) | |
dfac187e | 2340 | return plus_constant (ep->to_rtx, ep->previous_offset); |
32131a9c RK |
2341 | |
2342 | } | |
cd7c9015 RK |
2343 | else if (reg_renumber && reg_renumber[regno] < 0 |
2344 | && reg_equiv_constant && reg_equiv_constant[regno] | |
2b49ee39 R |
2345 | && ! CONSTANT_P (reg_equiv_constant[regno])) |
2346 | return eliminate_regs (copy_rtx (reg_equiv_constant[regno]), | |
2347 | mem_mode, insn); | |
32131a9c RK |
2348 | return x; |
2349 | ||
c5c76735 JL |
2350 | /* You might think handling MINUS in a manner similar to PLUS is a |
2351 | good idea. It is not. It has been tried multiple times and every | |
2352 | time the change has had to have been reverted. | |
2353 | ||
2354 | Other parts of reload know a PLUS is special (gen_reload for example) | |
2355 | and require special code to handle code a reloaded PLUS operand. | |
2356 | ||
2357 | Also consider backends where the flags register is clobbered by a | |
2358 | MINUS, but we can emit a PLUS that does not clobber flags (ia32, | |
2359 | lea instruction comes to mind). If we try to reload a MINUS, we | |
2360 | may kill the flags register that was holding a useful value. | |
2361 | ||
2362 | So, please before trying to handle MINUS, consider reload as a | |
2363 | whole instead of this little section as well as the backend issues. */ | |
32131a9c RK |
2364 | case PLUS: |
2365 | /* If this is the sum of an eliminable register and a constant, rework | |
6d2f8887 | 2366 | the sum. */ |
32131a9c RK |
2367 | if (GET_CODE (XEXP (x, 0)) == REG |
2368 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2369 | && CONSTANT_P (XEXP (x, 1))) | |
2370 | { | |
2371 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2372 | ep++) | |
2373 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2374 | { | |
32131a9c RK |
2375 | /* The only time we want to replace a PLUS with a REG (this |
2376 | occurs when the constant operand of the PLUS is the negative | |
2377 | of the offset) is when we are inside a MEM. We won't want | |
2378 | to do so at other times because that would change the | |
2379 | structure of the insn in a way that reload can't handle. | |
2380 | We special-case the commonest situation in | |
2381 | eliminate_regs_in_insn, so just replace a PLUS with a | |
2382 | PLUS here, unless inside a MEM. */ | |
a23b64d5 | 2383 | if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT |
32131a9c RK |
2384 | && INTVAL (XEXP (x, 1)) == - ep->previous_offset) |
2385 | return ep->to_rtx; | |
2386 | else | |
38a448ca RH |
2387 | return gen_rtx_PLUS (Pmode, ep->to_rtx, |
2388 | plus_constant (XEXP (x, 1), | |
2389 | ep->previous_offset)); | |
32131a9c RK |
2390 | } |
2391 | ||
2392 | /* If the register is not eliminable, we are done since the other | |
2393 | operand is a constant. */ | |
2394 | return x; | |
2395 | } | |
2396 | ||
2397 | /* If this is part of an address, we want to bring any constant to the | |
2398 | outermost PLUS. We will do this by doing register replacement in | |
2399 | our operands and seeing if a constant shows up in one of them. | |
2400 | ||
dfac187e BS |
2401 | Note that there is no risk of modifying the structure of the insn, |
2402 | since we only get called for its operands, thus we are either | |
2403 | modifying the address inside a MEM, or something like an address | |
2404 | operand of a load-address insn. */ | |
32131a9c RK |
2405 | |
2406 | { | |
1914f5da RH |
2407 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
2408 | rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn); | |
32131a9c | 2409 | |
cd7c9015 | 2410 | if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))) |
32131a9c RK |
2411 | { |
2412 | /* If one side is a PLUS and the other side is a pseudo that | |
a8fdc208 | 2413 | didn't get a hard register but has a reg_equiv_constant, |
32131a9c RK |
2414 | we must replace the constant here since it may no longer |
2415 | be in the position of any operand. */ | |
2416 | if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG | |
2417 | && REGNO (new1) >= FIRST_PSEUDO_REGISTER | |
2418 | && reg_renumber[REGNO (new1)] < 0 | |
2419 | && reg_equiv_constant != 0 | |
2420 | && reg_equiv_constant[REGNO (new1)] != 0) | |
2421 | new1 = reg_equiv_constant[REGNO (new1)]; | |
2422 | else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG | |
2423 | && REGNO (new0) >= FIRST_PSEUDO_REGISTER | |
2424 | && reg_renumber[REGNO (new0)] < 0 | |
2425 | && reg_equiv_constant[REGNO (new0)] != 0) | |
2426 | new0 = reg_equiv_constant[REGNO (new0)]; | |
2427 | ||
2428 | new = form_sum (new0, new1); | |
2429 | ||
2430 | /* As above, if we are not inside a MEM we do not want to | |
2431 | turn a PLUS into something else. We might try to do so here | |
2432 | for an addition of 0 if we aren't optimizing. */ | |
2433 | if (! mem_mode && GET_CODE (new) != PLUS) | |
38a448ca | 2434 | return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx); |
32131a9c RK |
2435 | else |
2436 | return new; | |
2437 | } | |
2438 | } | |
2439 | return x; | |
2440 | ||
981c7390 | 2441 | case MULT: |
05d10675 | 2442 | /* If this is the product of an eliminable register and a |
981c7390 RK |
2443 | constant, apply the distribute law and move the constant out |
2444 | so that we have (plus (mult ..) ..). This is needed in order | |
9faa82d8 | 2445 | to keep load-address insns valid. This case is pathological. |
981c7390 RK |
2446 | We ignore the possibility of overflow here. */ |
2447 | if (GET_CODE (XEXP (x, 0)) == REG | |
2448 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2449 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2450 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2451 | ep++) | |
2452 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2453 | { | |
2454 | if (! mem_mode | |
2455 | /* Refs inside notes don't count for this purpose. */ | |
2456 | && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST | |
2457 | || GET_CODE (insn) == INSN_LIST))) | |
2458 | ep->ref_outside_mem = 1; | |
2459 | ||
2460 | return | |
38a448ca | 2461 | plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), |
981c7390 RK |
2462 | ep->previous_offset * INTVAL (XEXP (x, 1))); |
2463 | } | |
32131a9c | 2464 | |
0f41302f | 2465 | /* ... fall through ... */ |
32131a9c | 2466 | |
32131a9c RK |
2467 | case CALL: |
2468 | case COMPARE: | |
c5c76735 | 2469 | /* See comments before PLUS about handling MINUS. */ |
930aeef3 | 2470 | case MINUS: |
32131a9c RK |
2471 | case DIV: case UDIV: |
2472 | case MOD: case UMOD: | |
2473 | case AND: case IOR: case XOR: | |
45620ed4 RK |
2474 | case ROTATERT: case ROTATE: |
2475 | case ASHIFTRT: case LSHIFTRT: case ASHIFT: | |
32131a9c RK |
2476 | case NE: case EQ: |
2477 | case GE: case GT: case GEU: case GTU: | |
2478 | case LE: case LT: case LEU: case LTU: | |
2479 | { | |
1914f5da | 2480 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
fb3821f7 | 2481 | rtx new1 |
1914f5da | 2482 | = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0; |
32131a9c RK |
2483 | |
2484 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
38a448ca | 2485 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); |
32131a9c RK |
2486 | } |
2487 | return x; | |
2488 | ||
981c7390 RK |
2489 | case EXPR_LIST: |
2490 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | |
2491 | if (XEXP (x, 0)) | |
2492 | { | |
1914f5da | 2493 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
981c7390 | 2494 | if (new != XEXP (x, 0)) |
13bb79d4 R |
2495 | { |
2496 | /* If this is a REG_DEAD note, it is not valid anymore. | |
2497 | Using the eliminated version could result in creating a | |
2498 | REG_DEAD note for the stack or frame pointer. */ | |
2499 | if (GET_MODE (x) == REG_DEAD) | |
2500 | return (XEXP (x, 1) | |
2501 | ? eliminate_regs (XEXP (x, 1), mem_mode, insn) | |
2502 | : NULL_RTX); | |
2503 | ||
2504 | x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1)); | |
2505 | } | |
981c7390 RK |
2506 | } |
2507 | ||
0f41302f | 2508 | /* ... fall through ... */ |
981c7390 RK |
2509 | |
2510 | case INSN_LIST: | |
2511 | /* Now do eliminations in the rest of the chain. If this was | |
2512 | an EXPR_LIST, this might result in allocating more memory than is | |
2513 | strictly needed, but it simplifies the code. */ | |
2514 | if (XEXP (x, 1)) | |
2515 | { | |
1914f5da | 2516 | new = eliminate_regs (XEXP (x, 1), mem_mode, insn); |
981c7390 | 2517 | if (new != XEXP (x, 1)) |
cd7c9015 RK |
2518 | return |
2519 | gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new); | |
981c7390 RK |
2520 | } |
2521 | return x; | |
2522 | ||
32131a9c RK |
2523 | case PRE_INC: |
2524 | case POST_INC: | |
2525 | case PRE_DEC: | |
2526 | case POST_DEC: | |
32131a9c RK |
2527 | case STRICT_LOW_PART: |
2528 | case NEG: case NOT: | |
2529 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2530 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2531 | case FLOAT: case FIX: | |
2532 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2533 | case ABS: | |
2534 | case SQRT: | |
2535 | case FFS: | |
1914f5da | 2536 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
32131a9c | 2537 | if (new != XEXP (x, 0)) |
38a448ca | 2538 | return gen_rtx_fmt_e (code, GET_MODE (x), new); |
32131a9c RK |
2539 | return x; |
2540 | ||
2541 | case SUBREG: | |
ddef6bc7 | 2542 | /* Similar to above processing, but preserve SUBREG_BYTE. |
32131a9c RK |
2543 | Convert (subreg (mem)) to (mem) if not paradoxical. |
2544 | Also, if we have a non-paradoxical (subreg (pseudo)) and the | |
2545 | pseudo didn't get a hard reg, we must replace this with the | |
2546 | eliminated version of the memory location because push_reloads | |
2547 | may do the replacement in certain circumstances. */ | |
2548 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2549 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2550 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2551 | && reg_equiv_memory_loc != 0 | |
2552 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2553 | { | |
cb2afeb3 | 2554 | new = SUBREG_REG (x); |
32131a9c RK |
2555 | } |
2556 | else | |
1914f5da | 2557 | new = eliminate_regs (SUBREG_REG (x), mem_mode, insn); |
32131a9c | 2558 | |
ddef6bc7 | 2559 | if (new != SUBREG_REG (x)) |
32131a9c | 2560 | { |
29ae5012 RK |
2561 | int x_size = GET_MODE_SIZE (GET_MODE (x)); |
2562 | int new_size = GET_MODE_SIZE (GET_MODE (new)); | |
2563 | ||
1914f5da | 2564 | if (GET_CODE (new) == MEM |
6d49a073 | 2565 | && ((x_size < new_size |
1914f5da | 2566 | #ifdef WORD_REGISTER_OPERATIONS |
6d49a073 JW |
2567 | /* On these machines, combine can create rtl of the form |
2568 | (set (subreg:m1 (reg:m2 R) 0) ...) | |
05d10675 | 2569 | where m1 < m2, and expects something interesting to |
6d49a073 JW |
2570 | happen to the entire word. Moreover, it will use the |
2571 | (reg:m2 R) later, expecting all bits to be preserved. | |
05d10675 | 2572 | So if the number of words is the same, preserve the |
6d49a073 | 2573 | subreg so that push_reloads can see it. */ |
5d9669fd RK |
2574 | && ! ((x_size - 1) / UNITS_PER_WORD |
2575 | == (new_size -1 ) / UNITS_PER_WORD) | |
1914f5da | 2576 | #endif |
6d49a073 | 2577 | ) |
5d9669fd | 2578 | || x_size == new_size) |
1914f5da | 2579 | ) |
a2ff290c | 2580 | return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x)); |
32131a9c | 2581 | else |
ddef6bc7 | 2582 | return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x)); |
32131a9c RK |
2583 | } |
2584 | ||
2585 | return x; | |
2586 | ||
32131a9c | 2587 | case MEM: |
e9a25f70 JL |
2588 | /* This is only for the benefit of the debugging backends, which call |
2589 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2590 | removed after CSE. */ | |
2591 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
1914f5da | 2592 | return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn); |
e9a25f70 | 2593 | |
32131a9c RK |
2594 | /* Our only special processing is to pass the mode of the MEM to our |
2595 | recursive call and copy the flags. While we are here, handle this | |
2596 | case more efficiently. */ | |
f1ec5147 RK |
2597 | return |
2598 | replace_equiv_address_nv (x, | |
2599 | eliminate_regs (XEXP (x, 0), | |
2600 | GET_MODE (x), insn)); | |
05d10675 | 2601 | |
dfac187e | 2602 | case USE: |
055c7759 JDA |
2603 | /* Handle insn_list USE that a call to a pure function may generate. */ |
2604 | new = eliminate_regs (XEXP (x, 0), 0, insn); | |
2605 | if (new != XEXP (x, 0)) | |
2606 | return gen_rtx_USE (GET_MODE (x), new); | |
2607 | return x; | |
2608 | ||
dfac187e BS |
2609 | case CLOBBER: |
2610 | case ASM_OPERANDS: | |
2611 | case SET: | |
2612 | abort (); | |
2613 | ||
e9a25f70 JL |
2614 | default: |
2615 | break; | |
32131a9c RK |
2616 | } |
2617 | ||
2618 | /* Process each of our operands recursively. If any have changed, make a | |
2619 | copy of the rtx. */ | |
2620 | fmt = GET_RTX_FORMAT (code); | |
2621 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2622 | { | |
2623 | if (*fmt == 'e') | |
2624 | { | |
1914f5da | 2625 | new = eliminate_regs (XEXP (x, i), mem_mode, insn); |
32131a9c RK |
2626 | if (new != XEXP (x, i) && ! copied) |
2627 | { | |
2628 | rtx new_x = rtx_alloc (code); | |
4e135bdd KG |
2629 | memcpy (new_x, x, |
2630 | (sizeof (*new_x) - sizeof (new_x->fld) | |
2631 | + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code))); | |
32131a9c RK |
2632 | x = new_x; |
2633 | copied = 1; | |
2634 | } | |
2635 | XEXP (x, i) = new; | |
2636 | } | |
2637 | else if (*fmt == 'E') | |
2638 | { | |
2639 | int copied_vec = 0; | |
2640 | for (j = 0; j < XVECLEN (x, i); j++) | |
2641 | { | |
1914f5da | 2642 | new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); |
32131a9c RK |
2643 | if (new != XVECEXP (x, i, j) && ! copied_vec) |
2644 | { | |
8f985ec4 ZW |
2645 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), |
2646 | XVEC (x, i)->elem); | |
32131a9c RK |
2647 | if (! copied) |
2648 | { | |
2649 | rtx new_x = rtx_alloc (code); | |
4e135bdd KG |
2650 | memcpy (new_x, x, |
2651 | (sizeof (*new_x) - sizeof (new_x->fld) | |
2652 | + (sizeof (new_x->fld[0]) | |
2653 | * GET_RTX_LENGTH (code)))); | |
32131a9c RK |
2654 | x = new_x; |
2655 | copied = 1; | |
2656 | } | |
2657 | XVEC (x, i) = new_v; | |
2658 | copied_vec = 1; | |
2659 | } | |
2660 | XVECEXP (x, i, j) = new; | |
2661 | } | |
2662 | } | |
2663 | } | |
2664 | ||
2665 | return x; | |
2666 | } | |
dfac187e BS |
2667 | |
2668 | /* Scan rtx X for modifications of elimination target registers. Update | |
2669 | the table of eliminables to reflect the changed state. MEM_MODE is | |
2670 | the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ | |
2671 | ||
2672 | static void | |
2673 | elimination_effects (x, mem_mode) | |
2674 | rtx x; | |
2675 | enum machine_mode mem_mode; | |
2676 | ||
2677 | { | |
2678 | enum rtx_code code = GET_CODE (x); | |
2679 | struct elim_table *ep; | |
2680 | int regno; | |
2681 | int i, j; | |
2682 | const char *fmt; | |
2683 | ||
2684 | switch (code) | |
2685 | { | |
2686 | case CONST_INT: | |
2687 | case CONST_DOUBLE: | |
69ef87e2 | 2688 | case CONST_VECTOR: |
dfac187e BS |
2689 | case CONST: |
2690 | case SYMBOL_REF: | |
2691 | case CODE_LABEL: | |
2692 | case PC: | |
2693 | case CC0: | |
2694 | case ASM_INPUT: | |
2695 | case ADDR_VEC: | |
2696 | case ADDR_DIFF_VEC: | |
2697 | case RETURN: | |
2698 | return; | |
2699 | ||
2700 | case ADDRESSOF: | |
2701 | abort (); | |
2702 | ||
2703 | case REG: | |
2704 | regno = REGNO (x); | |
2705 | ||
2706 | /* First handle the case where we encounter a bare register that | |
2707 | is eliminable. Replace it with a PLUS. */ | |
2708 | if (regno < FIRST_PSEUDO_REGISTER) | |
2709 | { | |
2710 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2711 | ep++) | |
2712 | if (ep->from_rtx == x && ep->can_eliminate) | |
2713 | { | |
2714 | if (! mem_mode) | |
2715 | ep->ref_outside_mem = 1; | |
2716 | return; | |
2717 | } | |
2718 | ||
2719 | } | |
2720 | else if (reg_renumber[regno] < 0 && reg_equiv_constant | |
2721 | && reg_equiv_constant[regno] | |
92a21141 | 2722 | && ! function_invariant_p (reg_equiv_constant[regno])) |
dfac187e BS |
2723 | elimination_effects (reg_equiv_constant[regno], mem_mode); |
2724 | return; | |
2725 | ||
2726 | case PRE_INC: | |
2727 | case POST_INC: | |
2728 | case PRE_DEC: | |
2729 | case POST_DEC: | |
4b983fdc RH |
2730 | case POST_MODIFY: |
2731 | case PRE_MODIFY: | |
dfac187e BS |
2732 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
2733 | if (ep->to_rtx == XEXP (x, 0)) | |
2734 | { | |
2735 | int size = GET_MODE_SIZE (mem_mode); | |
2736 | ||
2737 | /* If more bytes than MEM_MODE are pushed, account for them. */ | |
2738 | #ifdef PUSH_ROUNDING | |
2739 | if (ep->to_rtx == stack_pointer_rtx) | |
2740 | size = PUSH_ROUNDING (size); | |
2741 | #endif | |
2742 | if (code == PRE_DEC || code == POST_DEC) | |
2743 | ep->offset += size; | |
4b983fdc | 2744 | else if (code == PRE_INC || code == POST_INC) |
dfac187e | 2745 | ep->offset -= size; |
4b983fdc RH |
2746 | else if ((code == PRE_MODIFY || code == POST_MODIFY) |
2747 | && GET_CODE (XEXP (x, 1)) == PLUS | |
2748 | && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) | |
2749 | && CONSTANT_P (XEXP (XEXP (x, 1), 1))) | |
2750 | ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1)); | |
dfac187e BS |
2751 | } |
2752 | ||
4b983fdc RH |
2753 | /* These two aren't unary operators. */ |
2754 | if (code == POST_MODIFY || code == PRE_MODIFY) | |
2755 | break; | |
2756 | ||
dfac187e BS |
2757 | /* Fall through to generic unary operation case. */ |
2758 | case STRICT_LOW_PART: | |
2759 | case NEG: case NOT: | |
2760 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2761 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2762 | case FLOAT: case FIX: | |
2763 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2764 | case ABS: | |
2765 | case SQRT: | |
2766 | case FFS: | |
2767 | elimination_effects (XEXP (x, 0), mem_mode); | |
2768 | return; | |
2769 | ||
2770 | case SUBREG: | |
2771 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2772 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2773 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2774 | && reg_equiv_memory_loc != 0 | |
2775 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2776 | return; | |
2777 | ||
2778 | elimination_effects (SUBREG_REG (x), mem_mode); | |
2779 | return; | |
2780 | ||
2781 | case USE: | |
2782 | /* If using a register that is the source of an eliminate we still | |
2783 | think can be performed, note it cannot be performed since we don't | |
2784 | know how this register is used. */ | |
2785 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2786 | if (ep->from_rtx == XEXP (x, 0)) | |
2787 | ep->can_eliminate = 0; | |
2788 | ||
2789 | elimination_effects (XEXP (x, 0), mem_mode); | |
2790 | return; | |
2791 | ||
2792 | case CLOBBER: | |
2793 | /* If clobbering a register that is the replacement register for an | |
2794 | elimination we still think can be performed, note that it cannot | |
2795 | be performed. Otherwise, we need not be concerned about it. */ | |
2796 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2797 | if (ep->to_rtx == XEXP (x, 0)) | |
2798 | ep->can_eliminate = 0; | |
2799 | ||
2800 | elimination_effects (XEXP (x, 0), mem_mode); | |
2801 | return; | |
2802 | ||
2803 | case SET: | |
2804 | /* Check for setting a register that we know about. */ | |
2805 | if (GET_CODE (SET_DEST (x)) == REG) | |
2806 | { | |
2807 | /* See if this is setting the replacement register for an | |
2808 | elimination. | |
2809 | ||
2810 | If DEST is the hard frame pointer, we do nothing because we | |
2811 | assume that all assignments to the frame pointer are for | |
2812 | non-local gotos and are being done at a time when they are valid | |
2813 | and do not disturb anything else. Some machines want to | |
2814 | eliminate a fake argument pointer (or even a fake frame pointer) | |
2815 | with either the real frame or the stack pointer. Assignments to | |
2816 | the hard frame pointer must not prevent this elimination. */ | |
2817 | ||
2818 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2819 | ep++) | |
2820 | if (ep->to_rtx == SET_DEST (x) | |
2821 | && SET_DEST (x) != hard_frame_pointer_rtx) | |
2822 | { | |
2823 | /* If it is being incremented, adjust the offset. Otherwise, | |
2824 | this elimination can't be done. */ | |
2825 | rtx src = SET_SRC (x); | |
2826 | ||
2827 | if (GET_CODE (src) == PLUS | |
2828 | && XEXP (src, 0) == SET_DEST (x) | |
2829 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2830 | ep->offset -= INTVAL (XEXP (src, 1)); | |
2831 | else | |
2832 | ep->can_eliminate = 0; | |
2833 | } | |
2834 | } | |
2835 | ||
2836 | elimination_effects (SET_DEST (x), 0); | |
2837 | elimination_effects (SET_SRC (x), 0); | |
2838 | return; | |
2839 | ||
2840 | case MEM: | |
2841 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
2842 | abort (); | |
2843 | ||
2844 | /* Our only special processing is to pass the mode of the MEM to our | |
2845 | recursive call. */ | |
2846 | elimination_effects (XEXP (x, 0), GET_MODE (x)); | |
2847 | return; | |
2848 | ||
2849 | default: | |
2850 | break; | |
2851 | } | |
2852 | ||
2853 | fmt = GET_RTX_FORMAT (code); | |
2854 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2855 | { | |
2856 | if (*fmt == 'e') | |
2857 | elimination_effects (XEXP (x, i), mem_mode); | |
2858 | else if (*fmt == 'E') | |
2859 | for (j = 0; j < XVECLEN (x, i); j++) | |
2860 | elimination_effects (XVECEXP (x, i, j), mem_mode); | |
2861 | } | |
2862 | } | |
2863 | ||
2864 | /* Descend through rtx X and verify that no references to eliminable registers | |
2865 | remain. If any do remain, mark the involved register as not | |
2866 | eliminable. */ | |
1d813780 | 2867 | |
dfac187e BS |
2868 | static void |
2869 | check_eliminable_occurrences (x) | |
2870 | rtx x; | |
2871 | { | |
2872 | const char *fmt; | |
2873 | int i; | |
2874 | enum rtx_code code; | |
2875 | ||
2876 | if (x == 0) | |
2877 | return; | |
1d7254c5 | 2878 | |
dfac187e BS |
2879 | code = GET_CODE (x); |
2880 | ||
2881 | if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
2882 | { | |
2883 | struct elim_table *ep; | |
2884 | ||
2885 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2886 | if (ep->from_rtx == x && ep->can_eliminate) | |
2887 | ep->can_eliminate = 0; | |
2888 | return; | |
2889 | } | |
1d7254c5 | 2890 | |
dfac187e BS |
2891 | fmt = GET_RTX_FORMAT (code); |
2892 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2893 | { | |
2894 | if (*fmt == 'e') | |
2895 | check_eliminable_occurrences (XEXP (x, i)); | |
2896 | else if (*fmt == 'E') | |
2897 | { | |
2898 | int j; | |
2899 | for (j = 0; j < XVECLEN (x, i); j++) | |
2900 | check_eliminable_occurrences (XVECEXP (x, i, j)); | |
2901 | } | |
2902 | } | |
2903 | } | |
32131a9c RK |
2904 | \f |
2905 | /* Scan INSN and eliminate all eliminable registers in it. | |
2906 | ||
2907 | If REPLACE is nonzero, do the replacement destructively. Also | |
2908 | delete the insn as dead it if it is setting an eliminable register. | |
2909 | ||
2910 | If REPLACE is zero, do all our allocations in reload_obstack. | |
2911 | ||
2912 | If no eliminations were done and this insn doesn't require any elimination | |
2913 | processing (these are not identical conditions: it might be updating sp, | |
2914 | but not referencing fp; this needs to be seen during reload_as_needed so | |
2915 | that the offset between fp and sp can be taken into consideration), zero | |
2916 | is returned. Otherwise, 1 is returned. */ | |
2917 | ||
2918 | static int | |
2919 | eliminate_regs_in_insn (insn, replace) | |
2920 | rtx insn; | |
2921 | int replace; | |
2922 | { | |
dfac187e | 2923 | int icode = recog_memoized (insn); |
32131a9c | 2924 | rtx old_body = PATTERN (insn); |
dfac187e | 2925 | int insn_is_asm = asm_noperands (old_body) >= 0; |
774672d2 | 2926 | rtx old_set = single_set (insn); |
32131a9c RK |
2927 | rtx new_body; |
2928 | int val = 0; | |
dfac187e BS |
2929 | int i, any_changes; |
2930 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
2931 | rtx orig_operand[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
2932 | struct elim_table *ep; |
2933 | ||
dfac187e BS |
2934 | if (! insn_is_asm && icode < 0) |
2935 | { | |
2936 | if (GET_CODE (PATTERN (insn)) == USE | |
2937 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
2938 | || GET_CODE (PATTERN (insn)) == ADDR_VEC | |
2939 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
2940 | || GET_CODE (PATTERN (insn)) == ASM_INPUT) | |
2941 | return 0; | |
2942 | abort (); | |
2943 | } | |
2944 | ||
774672d2 RK |
2945 | if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG |
2946 | && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
2947 | { |
2948 | /* Check for setting an eliminable register. */ | |
2949 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
774672d2 | 2950 | if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) |
32131a9c | 2951 | { |
dd1eab0a RK |
2952 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
2953 | /* If this is setting the frame pointer register to the | |
2954 | hardware frame pointer register and this is an elimination | |
2955 | that will be done (tested above), this insn is really | |
2956 | adjusting the frame pointer downward to compensate for | |
2957 | the adjustment done before a nonlocal goto. */ | |
2958 | if (ep->from == FRAME_POINTER_REGNUM | |
2959 | && ep->to == HARD_FRAME_POINTER_REGNUM) | |
2960 | { | |
75eefe3f UW |
2961 | rtx base = SET_SRC (old_set); |
2962 | rtx base_insn = insn; | |
2963 | int offset = 0; | |
2964 | ||
2965 | while (base != ep->to_rtx) | |
8026ebba | 2966 | { |
75eefe3f UW |
2967 | rtx prev_insn, prev_set; |
2968 | ||
2969 | if (GET_CODE (base) == PLUS | |
2970 | && GET_CODE (XEXP (base, 1)) == CONST_INT) | |
2971 | { | |
2972 | offset += INTVAL (XEXP (base, 1)); | |
2973 | base = XEXP (base, 0); | |
2974 | } | |
2975 | else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0 | |
2976 | && (prev_set = single_set (prev_insn)) != 0 | |
2977 | && rtx_equal_p (SET_DEST (prev_set), base)) | |
2978 | { | |
2979 | base = SET_SRC (prev_set); | |
2980 | base_insn = prev_insn; | |
2981 | } | |
2982 | else | |
2983 | break; | |
8026ebba | 2984 | } |
dd1eab0a | 2985 | |
75eefe3f | 2986 | if (base == ep->to_rtx) |
dd1eab0a | 2987 | { |
c77fbfbe GK |
2988 | rtx src |
2989 | = plus_constant (ep->to_rtx, offset - ep->offset); | |
2990 | ||
2991 | new_body = old_body; | |
2992 | if (! replace) | |
2993 | { | |
2994 | new_body = copy_insn (old_body); | |
2995 | if (REG_NOTES (insn)) | |
2996 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
2997 | } | |
2998 | PATTERN (insn) = new_body; | |
2999 | old_set = single_set (insn); | |
3000 | ||
3001 | /* First see if this insn remains valid when we | |
3002 | make the change. If not, keep the INSN_CODE | |
3003 | the same and let reload fit it up. */ | |
3004 | validate_change (insn, &SET_SRC (old_set), src, 1); | |
3005 | validate_change (insn, &SET_DEST (old_set), | |
3006 | ep->to_rtx, 1); | |
3007 | if (! apply_change_group ()) | |
dd1eab0a | 3008 | { |
c77fbfbe GK |
3009 | SET_SRC (old_set) = src; |
3010 | SET_DEST (old_set) = ep->to_rtx; | |
dd1eab0a RK |
3011 | } |
3012 | ||
3013 | val = 1; | |
3014 | goto done; | |
3015 | } | |
3016 | } | |
3017 | #endif | |
3018 | ||
32131a9c RK |
3019 | /* In this case this insn isn't serving a useful purpose. We |
3020 | will delete it in reload_as_needed once we know that this | |
3021 | elimination is, in fact, being done. | |
3022 | ||
abc95ed3 | 3023 | If REPLACE isn't set, we can't delete this insn, but needn't |
32131a9c RK |
3024 | process it since it won't be used unless something changes. */ |
3025 | if (replace) | |
8a34409d | 3026 | { |
1d7254c5 | 3027 | delete_dead_insn (insn); |
8a34409d RH |
3028 | return 1; |
3029 | } | |
32131a9c RK |
3030 | val = 1; |
3031 | goto done; | |
3032 | } | |
aa5524a9 | 3033 | } |
32131a9c | 3034 | |
aa5524a9 BS |
3035 | /* We allow one special case which happens to work on all machines we |
3036 | currently support: a single set with the source being a PLUS of an | |
3037 | eliminable register and a constant. */ | |
3038 | if (old_set | |
1abdf5e7 | 3039 | && GET_CODE (SET_DEST (old_set)) == REG |
aa5524a9 BS |
3040 | && GET_CODE (SET_SRC (old_set)) == PLUS |
3041 | && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG | |
3042 | && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT | |
3043 | && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER) | |
3044 | { | |
3045 | rtx reg = XEXP (SET_SRC (old_set), 0); | |
3046 | int offset = INTVAL (XEXP (SET_SRC (old_set), 1)); | |
32131a9c | 3047 | |
aa5524a9 BS |
3048 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3049 | if (ep->from_rtx == reg && ep->can_eliminate) | |
3050 | { | |
3051 | offset += ep->offset; | |
32131a9c | 3052 | |
aa5524a9 BS |
3053 | if (offset == 0) |
3054 | { | |
f34c06e5 R |
3055 | int num_clobbers; |
3056 | /* We assume here that if we need a PARALLEL with | |
3057 | CLOBBERs for this assignment, we can do with the | |
3058 | MATCH_SCRATCHes that add_clobbers allocates. | |
3059 | There's not much we can do if that doesn't work. */ | |
aa5524a9 BS |
3060 | PATTERN (insn) = gen_rtx_SET (VOIDmode, |
3061 | SET_DEST (old_set), | |
3062 | ep->to_rtx); | |
f34c06e5 R |
3063 | num_clobbers = 0; |
3064 | INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers); | |
3065 | if (num_clobbers) | |
3066 | { | |
3067 | rtvec vec = rtvec_alloc (num_clobbers + 1); | |
3068 | ||
3069 | vec->elem[0] = PATTERN (insn); | |
3070 | PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); | |
3071 | add_clobbers (PATTERN (insn), INSN_CODE (insn)); | |
3072 | } | |
aa5524a9 BS |
3073 | if (INSN_CODE (insn) < 0) |
3074 | abort (); | |
3075 | } | |
3076 | else | |
3077 | { | |
3078 | new_body = old_body; | |
3079 | if (! replace) | |
3080 | { | |
3081 | new_body = copy_insn (old_body); | |
3082 | if (REG_NOTES (insn)) | |
3083 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3084 | } | |
3085 | PATTERN (insn) = new_body; | |
3086 | old_set = single_set (insn); | |
922d9d40 | 3087 | |
aa5524a9 BS |
3088 | XEXP (SET_SRC (old_set), 0) = ep->to_rtx; |
3089 | XEXP (SET_SRC (old_set), 1) = GEN_INT (offset); | |
3090 | } | |
3091 | val = 1; | |
3092 | /* This can't have an effect on elimination offsets, so skip right | |
3093 | to the end. */ | |
3094 | goto done; | |
3095 | } | |
32131a9c RK |
3096 | } |
3097 | ||
dfac187e BS |
3098 | /* Determine the effects of this insn on elimination offsets. */ |
3099 | elimination_effects (old_body, 0); | |
3100 | ||
3101 | /* Eliminate all eliminable registers occurring in operands that | |
3102 | can be handled by reload. */ | |
3103 | extract_insn (insn); | |
3104 | any_changes = 0; | |
3105 | for (i = 0; i < recog_data.n_operands; i++) | |
3106 | { | |
3107 | orig_operand[i] = recog_data.operand[i]; | |
3108 | substed_operand[i] = recog_data.operand[i]; | |
3109 | ||
3110 | /* For an asm statement, every operand is eliminable. */ | |
3111 | if (insn_is_asm || insn_data[icode].operand[i].eliminable) | |
3112 | { | |
3113 | /* Check for setting a register that we know about. */ | |
3114 | if (recog_data.operand_type[i] != OP_IN | |
3115 | && GET_CODE (orig_operand[i]) == REG) | |
3116 | { | |
3117 | /* If we are assigning to a register that can be eliminated, it | |
3118 | must be as part of a PARALLEL, since the code above handles | |
3119 | single SETs. We must indicate that we can no longer | |
3120 | eliminate this reg. */ | |
3121 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
3122 | ep++) | |
3123 | if (ep->from_rtx == orig_operand[i] && ep->can_eliminate) | |
3124 | ep->can_eliminate = 0; | |
3125 | } | |
3126 | ||
3127 | substed_operand[i] = eliminate_regs (recog_data.operand[i], 0, | |
3128 | replace ? insn : NULL_RTX); | |
3129 | if (substed_operand[i] != orig_operand[i]) | |
3130 | val = any_changes = 1; | |
3131 | /* Terminate the search in check_eliminable_occurrences at | |
3132 | this point. */ | |
3133 | *recog_data.operand_loc[i] = 0; | |
3134 | ||
3135 | /* If an output operand changed from a REG to a MEM and INSN is an | |
3136 | insn, write a CLOBBER insn. */ | |
3137 | if (recog_data.operand_type[i] != OP_IN | |
3138 | && GET_CODE (orig_operand[i]) == REG | |
3139 | && GET_CODE (substed_operand[i]) == MEM | |
3140 | && replace) | |
3141 | emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]), | |
3142 | insn); | |
3143 | } | |
3144 | } | |
3145 | ||
3146 | for (i = 0; i < recog_data.n_dups; i++) | |
3147 | *recog_data.dup_loc[i] | |
1d7254c5 | 3148 | = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; |
dfac187e BS |
3149 | |
3150 | /* If any eliminable remain, they aren't eliminable anymore. */ | |
3151 | check_eliminable_occurrences (old_body); | |
32131a9c | 3152 | |
dfac187e BS |
3153 | /* Substitute the operands; the new values are in the substed_operand |
3154 | array. */ | |
3155 | for (i = 0; i < recog_data.n_operands; i++) | |
3156 | *recog_data.operand_loc[i] = substed_operand[i]; | |
3157 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3158 | *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3159 | |
dfac187e | 3160 | /* If we are replacing a body that was a (set X (plus Y Z)), try to |
32131a9c RK |
3161 | re-recognize the insn. We do this in case we had a simple addition |
3162 | but now can do this as a load-address. This saves an insn in this | |
dfac187e BS |
3163 | common case. |
3164 | If re-recognition fails, the old insn code number will still be used, | |
3165 | and some register operands may have changed into PLUS expressions. | |
3166 | These will be handled by find_reloads by loading them into a register | |
1d7254c5 | 3167 | again. */ |
32131a9c | 3168 | |
dfac187e | 3169 | if (val) |
32131a9c | 3170 | { |
7c791b13 RK |
3171 | /* If we aren't replacing things permanently and we changed something, |
3172 | make another copy to ensure that all the RTL is new. Otherwise | |
3173 | things can go wrong if find_reload swaps commutative operands | |
0f41302f | 3174 | and one is inside RTL that has been copied while the other is not. */ |
dfac187e BS |
3175 | new_body = old_body; |
3176 | if (! replace) | |
1b3b5765 BS |
3177 | { |
3178 | new_body = copy_insn (old_body); | |
3179 | if (REG_NOTES (insn)) | |
3180 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3181 | } | |
dfac187e | 3182 | PATTERN (insn) = new_body; |
7c791b13 | 3183 | |
774672d2 RK |
3184 | /* If we had a move insn but now we don't, rerecognize it. This will |
3185 | cause spurious re-recognition if the old move had a PARALLEL since | |
3186 | the new one still will, but we can't call single_set without | |
3187 | having put NEW_BODY into the insn and the re-recognition won't | |
3188 | hurt in this rare case. */ | |
dfac187e BS |
3189 | /* ??? Why this huge if statement - why don't we just rerecognize the |
3190 | thing always? */ | |
3191 | if (! insn_is_asm | |
3192 | && old_set != 0 | |
774672d2 RK |
3193 | && ((GET_CODE (SET_SRC (old_set)) == REG |
3194 | && (GET_CODE (new_body) != SET | |
3195 | || GET_CODE (SET_SRC (new_body)) != REG)) | |
3196 | /* If this was a load from or store to memory, compare | |
1ccbefce RH |
3197 | the MEM in recog_data.operand to the one in the insn. |
3198 | If they are not equal, then rerecognize the insn. */ | |
774672d2 RK |
3199 | || (old_set != 0 |
3200 | && ((GET_CODE (SET_SRC (old_set)) == MEM | |
1ccbefce | 3201 | && SET_SRC (old_set) != recog_data.operand[1]) |
774672d2 | 3202 | || (GET_CODE (SET_DEST (old_set)) == MEM |
1ccbefce | 3203 | && SET_DEST (old_set) != recog_data.operand[0]))) |
774672d2 RK |
3204 | /* If this was an add insn before, rerecognize. */ |
3205 | || GET_CODE (SET_SRC (old_set)) == PLUS)) | |
4a5d0fb5 | 3206 | { |
dfac187e BS |
3207 | int new_icode = recog (PATTERN (insn), insn, 0); |
3208 | if (new_icode < 0) | |
3209 | INSN_CODE (insn) = icode; | |
4a5d0fb5 | 3210 | } |
dfac187e | 3211 | } |
32131a9c | 3212 | |
dfac187e BS |
3213 | /* Restore the old body. If there were any changes to it, we made a copy |
3214 | of it while the changes were still in place, so we'll correctly return | |
3215 | a modified insn below. */ | |
3216 | if (! replace) | |
3217 | { | |
3218 | /* Restore the old body. */ | |
3219 | for (i = 0; i < recog_data.n_operands; i++) | |
3220 | *recog_data.operand_loc[i] = orig_operand[i]; | |
3221 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3222 | *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3223 | } |
a8fdc208 | 3224 | |
dfac187e BS |
3225 | /* Update all elimination pairs to reflect the status after the current |
3226 | insn. The changes we make were determined by the earlier call to | |
3227 | elimination_effects. | |
a8efe40d | 3228 | |
32131a9c RK |
3229 | We also detect a cases where register elimination cannot be done, |
3230 | namely, if a register would be both changed and referenced outside a MEM | |
3231 | in the resulting insn since such an insn is often undefined and, even if | |
3232 | not, we cannot know what meaning will be given to it. Note that it is | |
3233 | valid to have a register used in an address in an insn that changes it | |
3234 | (presumably with a pre- or post-increment or decrement). | |
3235 | ||
3236 | If anything changes, return nonzero. */ | |
3237 | ||
32131a9c RK |
3238 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3239 | { | |
3240 | if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | |
3241 | ep->can_eliminate = 0; | |
3242 | ||
3243 | ep->ref_outside_mem = 0; | |
3244 | ||
3245 | if (ep->previous_offset != ep->offset) | |
3246 | val = 1; | |
32131a9c RK |
3247 | } |
3248 | ||
3249 | done: | |
9faa82d8 | 3250 | /* If we changed something, perform elimination in REG_NOTES. This is |
05b4c365 RK |
3251 | needed even when REPLACE is zero because a REG_DEAD note might refer |
3252 | to a register that we eliminate and could cause a different number | |
3253 | of spill registers to be needed in the final reload pass than in | |
3254 | the pre-passes. */ | |
20748cab | 3255 | if (val && REG_NOTES (insn) != 0) |
1914f5da | 3256 | REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn)); |
05b4c365 | 3257 | |
32131a9c RK |
3258 | return val; |
3259 | } | |
3260 | ||
cb2afeb3 R |
3261 | /* Loop through all elimination pairs. |
3262 | Recalculate the number not at initial offset. | |
3263 | ||
3264 | Compute the maximum offset (minimum offset if the stack does not | |
3265 | grow downward) for each elimination pair. */ | |
3266 | ||
3267 | static void | |
3268 | update_eliminable_offsets () | |
3269 | { | |
3270 | struct elim_table *ep; | |
3271 | ||
3272 | num_not_at_initial_offset = 0; | |
3273 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3274 | { | |
3275 | ep->previous_offset = ep->offset; | |
3276 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3277 | num_not_at_initial_offset++; | |
cb2afeb3 R |
3278 | } |
3279 | } | |
3280 | ||
32131a9c RK |
3281 | /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register |
3282 | replacement we currently believe is valid, mark it as not eliminable if X | |
3283 | modifies DEST in any way other than by adding a constant integer to it. | |
3284 | ||
3285 | If DEST is the frame pointer, we do nothing because we assume that | |
3ec2ea3e DE |
3286 | all assignments to the hard frame pointer are nonlocal gotos and are being |
3287 | done at a time when they are valid and do not disturb anything else. | |
32131a9c | 3288 | Some machines want to eliminate a fake argument pointer with either the |
3ec2ea3e DE |
3289 | frame or stack pointer. Assignments to the hard frame pointer must not |
3290 | prevent this elimination. | |
32131a9c RK |
3291 | |
3292 | Called via note_stores from reload before starting its passes to scan | |
3293 | the insns of the function. */ | |
3294 | ||
3295 | static void | |
84832317 | 3296 | mark_not_eliminable (dest, x, data) |
32131a9c RK |
3297 | rtx dest; |
3298 | rtx x; | |
84832317 | 3299 | void *data ATTRIBUTE_UNUSED; |
32131a9c | 3300 | { |
b3694847 | 3301 | unsigned int i; |
32131a9c RK |
3302 | |
3303 | /* A SUBREG of a hard register here is just changing its mode. We should | |
3304 | not see a SUBREG of an eliminable hard register, but check just in | |
3305 | case. */ | |
3306 | if (GET_CODE (dest) == SUBREG) | |
3307 | dest = SUBREG_REG (dest); | |
3308 | ||
3ec2ea3e | 3309 | if (dest == hard_frame_pointer_rtx) |
32131a9c RK |
3310 | return; |
3311 | ||
3312 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3313 | if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx | |
3314 | && (GET_CODE (x) != SET | |
3315 | || GET_CODE (SET_SRC (x)) != PLUS | |
3316 | || XEXP (SET_SRC (x), 0) != dest | |
3317 | || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) | |
3318 | { | |
3319 | reg_eliminate[i].can_eliminate_previous | |
3320 | = reg_eliminate[i].can_eliminate = 0; | |
3321 | num_eliminable--; | |
3322 | } | |
3323 | } | |
09dd1133 | 3324 | |
c47f5ea5 BS |
3325 | /* Verify that the initial elimination offsets did not change since the |
3326 | last call to set_initial_elim_offsets. This is used to catch cases | |
3327 | where something illegal happened during reload_as_needed that could | |
3328 | cause incorrect code to be generated if we did not check for it. */ | |
c8d8ed65 | 3329 | |
c47f5ea5 BS |
3330 | static void |
3331 | verify_initial_elim_offsets () | |
3332 | { | |
3333 | int t; | |
3334 | ||
3335 | #ifdef ELIMINABLE_REGS | |
3336 | struct elim_table *ep; | |
3337 | ||
3338 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3339 | { | |
3340 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); | |
3341 | if (t != ep->initial_offset) | |
3342 | abort (); | |
3343 | } | |
3344 | #else | |
3345 | INITIAL_FRAME_POINTER_OFFSET (t); | |
3346 | if (t != reg_eliminate[0].initial_offset) | |
3347 | abort (); | |
05d10675 | 3348 | #endif |
c47f5ea5 BS |
3349 | } |
3350 | ||
09dd1133 | 3351 | /* Reset all offsets on eliminable registers to their initial values. */ |
1d813780 | 3352 | |
09dd1133 BS |
3353 | static void |
3354 | set_initial_elim_offsets () | |
3355 | { | |
1f3b1e1a | 3356 | struct elim_table *ep = reg_eliminate; |
09dd1133 BS |
3357 | |
3358 | #ifdef ELIMINABLE_REGS | |
1f3b1e1a | 3359 | for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
09dd1133 BS |
3360 | { |
3361 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); | |
1f3b1e1a | 3362 | ep->previous_offset = ep->offset = ep->initial_offset; |
09dd1133 BS |
3363 | } |
3364 | #else | |
1f3b1e1a JL |
3365 | INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); |
3366 | ep->previous_offset = ep->offset = ep->initial_offset; | |
09dd1133 BS |
3367 | #endif |
3368 | ||
3369 | num_not_at_initial_offset = 0; | |
1f3b1e1a | 3370 | } |
09dd1133 | 3371 | |
1f3b1e1a JL |
3372 | /* Initialize the known label offsets. |
3373 | Set a known offset for each forced label to be at the initial offset | |
3374 | of each elimination. We do this because we assume that all | |
3375 | computed jumps occur from a location where each elimination is | |
3376 | at its initial offset. | |
3377 | For all other labels, show that we don't know the offsets. */ | |
09dd1133 | 3378 | |
1f3b1e1a JL |
3379 | static void |
3380 | set_initial_label_offsets () | |
3381 | { | |
3382 | rtx x; | |
961192e1 | 3383 | memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels); |
09dd1133 BS |
3384 | |
3385 | for (x = forced_labels; x; x = XEXP (x, 1)) | |
3386 | if (XEXP (x, 0)) | |
3387 | set_label_offsets (XEXP (x, 0), NULL_RTX, 1); | |
3388 | } | |
3389 | ||
1f3b1e1a JL |
3390 | /* Set all elimination offsets to the known values for the code label given |
3391 | by INSN. */ | |
1d813780 | 3392 | |
1f3b1e1a JL |
3393 | static void |
3394 | set_offsets_for_label (insn) | |
3395 | rtx insn; | |
3396 | { | |
973838fd | 3397 | unsigned int i; |
1f3b1e1a JL |
3398 | int label_nr = CODE_LABEL_NUMBER (insn); |
3399 | struct elim_table *ep; | |
3400 | ||
3401 | num_not_at_initial_offset = 0; | |
3402 | for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) | |
3403 | { | |
3404 | ep->offset = ep->previous_offset = offsets_at[label_nr][i]; | |
3405 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3406 | num_not_at_initial_offset++; | |
3407 | } | |
3408 | } | |
3409 | ||
09dd1133 BS |
3410 | /* See if anything that happened changes which eliminations are valid. |
3411 | For example, on the Sparc, whether or not the frame pointer can | |
3412 | be eliminated can depend on what registers have been used. We need | |
3413 | not check some conditions again (such as flag_omit_frame_pointer) | |
3414 | since they can't have changed. */ | |
3415 | ||
3416 | static void | |
3417 | update_eliminables (pset) | |
3418 | HARD_REG_SET *pset; | |
3419 | { | |
3420 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
3421 | int previous_frame_pointer_needed = frame_pointer_needed; | |
3422 | #endif | |
3423 | struct elim_table *ep; | |
3424 | ||
3425 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3426 | if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) | |
3427 | #ifdef ELIMINABLE_REGS | |
3428 | || ! CAN_ELIMINATE (ep->from, ep->to) | |
3429 | #endif | |
3430 | ) | |
3431 | ep->can_eliminate = 0; | |
3432 | ||
3433 | /* Look for the case where we have discovered that we can't replace | |
3434 | register A with register B and that means that we will now be | |
3435 | trying to replace register A with register C. This means we can | |
3436 | no longer replace register C with register B and we need to disable | |
3437 | such an elimination, if it exists. This occurs often with A == ap, | |
3438 | B == sp, and C == fp. */ | |
3439 | ||
3440 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3441 | { | |
3442 | struct elim_table *op; | |
b3694847 | 3443 | int new_to = -1; |
09dd1133 BS |
3444 | |
3445 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3446 | { | |
3447 | /* Find the current elimination for ep->from, if there is a | |
3448 | new one. */ | |
3449 | for (op = reg_eliminate; | |
3450 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3451 | if (op->from == ep->from && op->can_eliminate) | |
3452 | { | |
3453 | new_to = op->to; | |
3454 | break; | |
3455 | } | |
3456 | ||
3457 | /* See if there is an elimination of NEW_TO -> EP->TO. If so, | |
3458 | disable it. */ | |
3459 | for (op = reg_eliminate; | |
3460 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3461 | if (op->from == new_to && op->to == ep->to) | |
3462 | op->can_eliminate = 0; | |
3463 | } | |
3464 | } | |
3465 | ||
3466 | /* See if any registers that we thought we could eliminate the previous | |
3467 | time are no longer eliminable. If so, something has changed and we | |
3468 | must spill the register. Also, recompute the number of eliminable | |
3469 | registers and see if the frame pointer is needed; it is if there is | |
3470 | no elimination of the frame pointer that we can perform. */ | |
3471 | ||
3472 | frame_pointer_needed = 1; | |
3473 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3474 | { | |
3475 | if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM | |
3476 | && ep->to != HARD_FRAME_POINTER_REGNUM) | |
3477 | frame_pointer_needed = 0; | |
3478 | ||
3479 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3480 | { | |
3481 | ep->can_eliminate_previous = 0; | |
3482 | SET_HARD_REG_BIT (*pset, ep->from); | |
3483 | num_eliminable--; | |
3484 | } | |
3485 | } | |
3486 | ||
3487 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
3488 | /* If we didn't need a frame pointer last time, but we do now, spill | |
3489 | the hard frame pointer. */ | |
3490 | if (frame_pointer_needed && ! previous_frame_pointer_needed) | |
3491 | SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); | |
3492 | #endif | |
3493 | } | |
3494 | ||
3495 | /* Initialize the table of registers to eliminate. */ | |
1d813780 | 3496 | |
09dd1133 BS |
3497 | static void |
3498 | init_elim_table () | |
3499 | { | |
3500 | struct elim_table *ep; | |
590cf94d | 3501 | #ifdef ELIMINABLE_REGS |
0b5826ac | 3502 | const struct elim_table_1 *ep1; |
590cf94d | 3503 | #endif |
09dd1133 | 3504 | |
590cf94d | 3505 | if (!reg_eliminate) |
ad85216e | 3506 | reg_eliminate = (struct elim_table *) |
1d7254c5 | 3507 | xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS); |
05d10675 | 3508 | |
09dd1133 BS |
3509 | /* Does this function require a frame pointer? */ |
3510 | ||
3511 | frame_pointer_needed = (! flag_omit_frame_pointer | |
3512 | #ifdef EXIT_IGNORE_STACK | |
3513 | /* ?? If EXIT_IGNORE_STACK is set, we will not save | |
3514 | and restore sp for alloca. So we can't eliminate | |
3515 | the frame pointer in that case. At some point, | |
3516 | we should improve this by emitting the | |
3517 | sp-adjusting insns for this case. */ | |
3518 | || (current_function_calls_alloca | |
3519 | && EXIT_IGNORE_STACK) | |
3520 | #endif | |
3521 | || FRAME_POINTER_REQUIRED); | |
3522 | ||
3523 | num_eliminable = 0; | |
3524 | ||
3525 | #ifdef ELIMINABLE_REGS | |
590cf94d KG |
3526 | for (ep = reg_eliminate, ep1 = reg_eliminate_1; |
3527 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) | |
09dd1133 | 3528 | { |
590cf94d KG |
3529 | ep->from = ep1->from; |
3530 | ep->to = ep1->to; | |
09dd1133 BS |
3531 | ep->can_eliminate = ep->can_eliminate_previous |
3532 | = (CAN_ELIMINATE (ep->from, ep->to) | |
3533 | && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed)); | |
3534 | } | |
3535 | #else | |
590cf94d KG |
3536 | reg_eliminate[0].from = reg_eliminate_1[0].from; |
3537 | reg_eliminate[0].to = reg_eliminate_1[0].to; | |
09dd1133 BS |
3538 | reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous |
3539 | = ! frame_pointer_needed; | |
3540 | #endif | |
3541 | ||
3542 | /* Count the number of eliminable registers and build the FROM and TO | |
3543 | REG rtx's. Note that code in gen_rtx will cause, e.g., | |
3544 | gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. | |
3545 | We depend on this. */ | |
3546 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3547 | { | |
3548 | num_eliminable += ep->can_eliminate; | |
3549 | ep->from_rtx = gen_rtx_REG (Pmode, ep->from); | |
3550 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | |
3551 | } | |
3552 | } | |
32131a9c RK |
3553 | \f |
3554 | /* Kick all pseudos out of hard register REGNO. | |
32131a9c RK |
3555 | |
3556 | If CANT_ELIMINATE is nonzero, it means that we are doing this spill | |
3557 | because we found we can't eliminate some register. In the case, no pseudos | |
3558 | are allowed to be in the register, even if they are only in a block that | |
3559 | doesn't require spill registers, unlike the case when we are spilling this | |
3560 | hard reg to produce another spill register. | |
3561 | ||
3562 | Return nonzero if any pseudos needed to be kicked out. */ | |
3563 | ||
03acd8f8 | 3564 | static void |
e04ca094 | 3565 | spill_hard_reg (regno, cant_eliminate) |
770ae6cc | 3566 | unsigned int regno; |
32131a9c RK |
3567 | int cant_eliminate; |
3568 | { | |
b3694847 | 3569 | int i; |
32131a9c | 3570 | |
9ff3516a | 3571 | if (cant_eliminate) |
03acd8f8 BS |
3572 | { |
3573 | SET_HARD_REG_BIT (bad_spill_regs_global, regno); | |
3574 | regs_ever_live[regno] = 1; | |
3575 | } | |
9ff3516a | 3576 | |
32131a9c RK |
3577 | /* Spill every pseudo reg that was allocated to this reg |
3578 | or to something that overlaps this reg. */ | |
3579 | ||
3580 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3581 | if (reg_renumber[i] >= 0 | |
770ae6cc RK |
3582 | && (unsigned int) reg_renumber[i] <= regno |
3583 | && ((unsigned int) reg_renumber[i] | |
3584 | + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i], | |
32131a9c RK |
3585 | PSEUDO_REGNO_MODE (i)) |
3586 | > regno)) | |
f5d8c9f4 | 3587 | SET_REGNO_REG_SET (&spilled_pseudos, i); |
03acd8f8 | 3588 | } |
32131a9c | 3589 | |
03acd8f8 BS |
3590 | /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET |
3591 | from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */ | |
770ae6cc | 3592 | |
03acd8f8 BS |
3593 | static void |
3594 | ior_hard_reg_set (set1, set2) | |
3595 | HARD_REG_SET *set1, *set2; | |
3596 | { | |
3597 | IOR_HARD_REG_SET (*set1, *set2); | |
3598 | } | |
05d10675 | 3599 | |
03acd8f8 BS |
3600 | /* After find_reload_regs has been run for all insn that need reloads, |
3601 | and/or spill_hard_regs was called, this function is used to actually | |
3602 | spill pseudo registers and try to reallocate them. It also sets up the | |
3603 | spill_regs array for use by choose_reload_regs. */ | |
a8fdc208 | 3604 | |
03acd8f8 | 3605 | static int |
e04ca094 | 3606 | finish_spills (global) |
03acd8f8 | 3607 | int global; |
03acd8f8 BS |
3608 | { |
3609 | struct insn_chain *chain; | |
3610 | int something_changed = 0; | |
3611 | int i; | |
3612 | ||
3613 | /* Build the spill_regs array for the function. */ | |
3614 | /* If there are some registers still to eliminate and one of the spill regs | |
3615 | wasn't ever used before, additional stack space may have to be | |
3616 | allocated to store this register. Thus, we may have changed the offset | |
3617 | between the stack and frame pointers, so mark that something has changed. | |
32131a9c | 3618 | |
03acd8f8 BS |
3619 | One might think that we need only set VAL to 1 if this is a call-used |
3620 | register. However, the set of registers that must be saved by the | |
3621 | prologue is not identical to the call-used set. For example, the | |
3622 | register used by the call insn for the return PC is a call-used register, | |
3623 | but must be saved by the prologue. */ | |
3624 | ||
3625 | n_spills = 0; | |
3626 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3627 | if (TEST_HARD_REG_BIT (used_spill_regs, i)) | |
3628 | { | |
3629 | spill_reg_order[i] = n_spills; | |
3630 | spill_regs[n_spills++] = i; | |
3631 | if (num_eliminable && ! regs_ever_live[i]) | |
3632 | something_changed = 1; | |
3633 | regs_ever_live[i] = 1; | |
3634 | } | |
3635 | else | |
3636 | spill_reg_order[i] = -1; | |
3637 | ||
efc9bd41 RK |
3638 | EXECUTE_IF_SET_IN_REG_SET |
3639 | (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, | |
3640 | { | |
3641 | /* Record the current hard register the pseudo is allocated to in | |
3642 | pseudo_previous_regs so we avoid reallocating it to the same | |
3643 | hard reg in a later pass. */ | |
3644 | if (reg_renumber[i] < 0) | |
3645 | abort (); | |
3646 | ||
3647 | SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); | |
3648 | /* Mark it as no longer having a hard register home. */ | |
3649 | reg_renumber[i] = -1; | |
3650 | /* We will need to scan everything again. */ | |
3651 | something_changed = 1; | |
3652 | }); | |
7609e720 | 3653 | |
03acd8f8 BS |
3654 | /* Retry global register allocation if possible. */ |
3655 | if (global) | |
3656 | { | |
961192e1 | 3657 | memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET)); |
03acd8f8 BS |
3658 | /* For every insn that needs reloads, set the registers used as spill |
3659 | regs in pseudo_forbidden_regs for every pseudo live across the | |
3660 | insn. */ | |
3661 | for (chain = insns_need_reload; chain; chain = chain->next_need_reload) | |
3662 | { | |
3663 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3664 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3665 | { |
3666 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3667 | &chain->used_spill_regs); | |
3668 | }); | |
3669 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3670 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3671 | { |
3672 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3673 | &chain->used_spill_regs); | |
3674 | }); | |
3675 | } | |
7609e720 | 3676 | |
03acd8f8 BS |
3677 | /* Retry allocating the spilled pseudos. For each reg, merge the |
3678 | various reg sets that indicate which hard regs can't be used, | |
3679 | and call retry_global_alloc. | |
05d10675 | 3680 | We change spill_pseudos here to only contain pseudos that did not |
03acd8f8 BS |
3681 | get a new hard register. */ |
3682 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3683 | if (reg_old_renumber[i] != reg_renumber[i]) | |
32131a9c | 3684 | { |
03acd8f8 BS |
3685 | HARD_REG_SET forbidden; |
3686 | COPY_HARD_REG_SET (forbidden, bad_spill_regs_global); | |
3687 | IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]); | |
3688 | IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]); | |
3689 | retry_global_alloc (i, forbidden); | |
3690 | if (reg_renumber[i] >= 0) | |
f5d8c9f4 | 3691 | CLEAR_REGNO_REG_SET (&spilled_pseudos, i); |
32131a9c | 3692 | } |
03acd8f8 | 3693 | } |
7609e720 | 3694 | |
03acd8f8 BS |
3695 | /* Fix up the register information in the insn chain. |
3696 | This involves deleting those of the spilled pseudos which did not get | |
3697 | a new hard register home from the live_{before,after} sets. */ | |
7609e720 BS |
3698 | for (chain = reload_insn_chain; chain; chain = chain->next) |
3699 | { | |
03acd8f8 BS |
3700 | HARD_REG_SET used_by_pseudos; |
3701 | HARD_REG_SET used_by_pseudos2; | |
3702 | ||
239a0f5b BS |
3703 | AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); |
3704 | AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); | |
03acd8f8 BS |
3705 | |
3706 | /* Mark any unallocated hard regs as available for spills. That | |
3707 | makes inheritance work somewhat better. */ | |
3708 | if (chain->need_reload) | |
3709 | { | |
239a0f5b BS |
3710 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); |
3711 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
03acd8f8 BS |
3712 | IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); |
3713 | ||
3714 | /* Save the old value for the sanity test below. */ | |
3715 | COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs); | |
3716 | ||
239a0f5b BS |
3717 | compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); |
3718 | compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); | |
03acd8f8 BS |
3719 | COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); |
3720 | AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); | |
3721 | ||
3722 | /* Make sure we only enlarge the set. */ | |
3723 | GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok); | |
3724 | abort (); | |
3725 | ok:; | |
3726 | } | |
7609e720 | 3727 | } |
03acd8f8 BS |
3728 | |
3729 | /* Let alter_reg modify the reg rtx's for the modified pseudos. */ | |
3730 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3731 | { | |
3732 | int regno = reg_renumber[i]; | |
3733 | if (reg_old_renumber[i] == regno) | |
3734 | continue; | |
05d10675 | 3735 | |
03acd8f8 BS |
3736 | alter_reg (i, reg_old_renumber[i]); |
3737 | reg_old_renumber[i] = regno; | |
e04ca094 | 3738 | if (rtl_dump_file) |
03acd8f8 BS |
3739 | { |
3740 | if (regno == -1) | |
e04ca094 | 3741 | fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i); |
03acd8f8 | 3742 | else |
e04ca094 | 3743 | fprintf (rtl_dump_file, " Register %d now in %d.\n\n", |
03acd8f8 BS |
3744 | i, reg_renumber[i]); |
3745 | } | |
3746 | } | |
3747 | ||
3748 | return something_changed; | |
7609e720 | 3749 | } |
32131a9c | 3750 | \f |
05d10675 | 3751 | /* Find all paradoxical subregs within X and update reg_max_ref_width. |
56f58d3a RK |
3752 | Also mark any hard registers used to store user variables as |
3753 | forbidden from being used for spill registers. */ | |
32131a9c RK |
3754 | |
3755 | static void | |
3756 | scan_paradoxical_subregs (x) | |
b3694847 | 3757 | rtx x; |
32131a9c | 3758 | { |
b3694847 SS |
3759 | int i; |
3760 | const char *fmt; | |
3761 | enum rtx_code code = GET_CODE (x); | |
32131a9c RK |
3762 | |
3763 | switch (code) | |
3764 | { | |
56f58d3a | 3765 | case REG: |
03acd8f8 | 3766 | #if 0 |
e9a25f70 | 3767 | if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER |
f95182a4 | 3768 | && REG_USERVAR_P (x)) |
03acd8f8 BS |
3769 | SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x)); |
3770 | #endif | |
56f58d3a RK |
3771 | return; |
3772 | ||
32131a9c RK |
3773 | case CONST_INT: |
3774 | case CONST: | |
3775 | case SYMBOL_REF: | |
3776 | case LABEL_REF: | |
3777 | case CONST_DOUBLE: | |
69ef87e2 | 3778 | case CONST_VECTOR: /* shouldn't happen, but just in case. */ |
32131a9c RK |
3779 | case CC0: |
3780 | case PC: | |
32131a9c RK |
3781 | case USE: |
3782 | case CLOBBER: | |
3783 | return; | |
3784 | ||
3785 | case SUBREG: | |
3786 | if (GET_CODE (SUBREG_REG (x)) == REG | |
3787 | && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
3788 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
3789 | = GET_MODE_SIZE (GET_MODE (x)); | |
3790 | return; | |
05d10675 | 3791 | |
e9a25f70 JL |
3792 | default: |
3793 | break; | |
32131a9c RK |
3794 | } |
3795 | ||
3796 | fmt = GET_RTX_FORMAT (code); | |
3797 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3798 | { | |
3799 | if (fmt[i] == 'e') | |
3800 | scan_paradoxical_subregs (XEXP (x, i)); | |
3801 | else if (fmt[i] == 'E') | |
3802 | { | |
b3694847 | 3803 | int j; |
1d7254c5 | 3804 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
32131a9c RK |
3805 | scan_paradoxical_subregs (XVECEXP (x, i, j)); |
3806 | } | |
3807 | } | |
3808 | } | |
3809 | \f | |
32131a9c RK |
3810 | /* Reload pseudo-registers into hard regs around each insn as needed. |
3811 | Additional register load insns are output before the insn that needs it | |
3812 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
3813 | ||
3814 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
d08ea79f | 3815 | which registers are already available in reload registers. |
32131a9c RK |
3816 | We update these for the reloads that we perform, |
3817 | as the insns are scanned. */ | |
3818 | ||
3819 | static void | |
e04ca094 | 3820 | reload_as_needed (live_known) |
32131a9c RK |
3821 | int live_known; |
3822 | { | |
7609e720 | 3823 | struct insn_chain *chain; |
553687c9 | 3824 | #if defined (AUTO_INC_DEC) |
b3694847 | 3825 | int i; |
973838fd | 3826 | #endif |
32131a9c | 3827 | rtx x; |
32131a9c | 3828 | |
961192e1 JM |
3829 | memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx); |
3830 | memset ((char *) spill_reg_store, 0, sizeof spill_reg_store); | |
ff154f78 MM |
3831 | reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
3832 | reg_has_output_reload = (char *) xmalloc (max_regno); | |
e6e52be0 | 3833 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c | 3834 | |
1f3b1e1a | 3835 | set_initial_elim_offsets (); |
32131a9c | 3836 | |
7609e720 | 3837 | for (chain = reload_insn_chain; chain; chain = chain->next) |
32131a9c | 3838 | { |
03acd8f8 | 3839 | rtx prev; |
7609e720 BS |
3840 | rtx insn = chain->insn; |
3841 | rtx old_next = NEXT_INSN (insn); | |
32131a9c RK |
3842 | |
3843 | /* If we pass a label, copy the offsets from the label information | |
3844 | into the current offsets of each elimination. */ | |
3845 | if (GET_CODE (insn) == CODE_LABEL) | |
1f3b1e1a | 3846 | set_offsets_for_label (insn); |
32131a9c | 3847 | |
2c3c49de | 3848 | else if (INSN_P (insn)) |
32131a9c | 3849 | { |
449655a6 | 3850 | rtx oldpat = copy_rtx (PATTERN (insn)); |
32131a9c | 3851 | |
2758481d RS |
3852 | /* If this is a USE and CLOBBER of a MEM, ensure that any |
3853 | references to eliminable registers have been removed. */ | |
3854 | ||
3855 | if ((GET_CODE (PATTERN (insn)) == USE | |
3856 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
3857 | && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) | |
3858 | XEXP (XEXP (PATTERN (insn), 0), 0) | |
3859 | = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), | |
29ae5012 | 3860 | GET_MODE (XEXP (PATTERN (insn), 0)), |
1914f5da | 3861 | NULL_RTX); |
2758481d | 3862 | |
32131a9c RK |
3863 | /* If we need to do register elimination processing, do so. |
3864 | This might delete the insn, in which case we are done. */ | |
2b49ee39 | 3865 | if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) |
32131a9c RK |
3866 | { |
3867 | eliminate_regs_in_insn (insn, 1); | |
3868 | if (GET_CODE (insn) == NOTE) | |
cb2afeb3 R |
3869 | { |
3870 | update_eliminable_offsets (); | |
3871 | continue; | |
3872 | } | |
32131a9c RK |
3873 | } |
3874 | ||
7609e720 BS |
3875 | /* If need_elim is nonzero but need_reload is zero, one might think |
3876 | that we could simply set n_reloads to 0. However, find_reloads | |
3877 | could have done some manipulation of the insn (such as swapping | |
3878 | commutative operands), and these manipulations are lost during | |
3879 | the first pass for every insn that needs register elimination. | |
3880 | So the actions of find_reloads must be redone here. */ | |
3881 | ||
03acd8f8 BS |
3882 | if (! chain->need_elim && ! chain->need_reload |
3883 | && ! chain->need_operand_change) | |
32131a9c RK |
3884 | n_reloads = 0; |
3885 | /* First find the pseudo regs that must be reloaded for this insn. | |
3886 | This info is returned in the tables reload_... (see reload.h). | |
3887 | Also modify the body of INSN by substituting RELOAD | |
3888 | rtx's for those pseudo regs. */ | |
3889 | else | |
3890 | { | |
961192e1 | 3891 | memset (reg_has_output_reload, 0, max_regno); |
32131a9c RK |
3892 | CLEAR_HARD_REG_SET (reg_is_output_reload); |
3893 | ||
3894 | find_reloads (insn, 1, spill_indirect_levels, live_known, | |
3895 | spill_reg_order); | |
3896 | } | |
3897 | ||
3898 | if (n_reloads > 0) | |
3899 | { | |
cb2afeb3 | 3900 | rtx next = NEXT_INSN (insn); |
3c3eeea6 | 3901 | rtx p; |
32131a9c | 3902 | |
cb2afeb3 R |
3903 | prev = PREV_INSN (insn); |
3904 | ||
32131a9c RK |
3905 | /* Now compute which reload regs to reload them into. Perhaps |
3906 | reusing reload regs from previous insns, or else output | |
3907 | load insns to reload them. Maybe output store insns too. | |
3908 | Record the choices of reload reg in reload_reg_rtx. */ | |
03acd8f8 | 3909 | choose_reload_regs (chain); |
32131a9c | 3910 | |
05d10675 | 3911 | /* Merge any reloads that we didn't combine for fear of |
546b63fb RK |
3912 | increasing the number of spill registers needed but now |
3913 | discover can be safely merged. */ | |
f95182a4 ILT |
3914 | if (SMALL_REGISTER_CLASSES) |
3915 | merge_assigned_reloads (insn); | |
546b63fb | 3916 | |
32131a9c RK |
3917 | /* Generate the insns to reload operands into or out of |
3918 | their reload regs. */ | |
e04ca094 | 3919 | emit_reload_insns (chain); |
32131a9c RK |
3920 | |
3921 | /* Substitute the chosen reload regs from reload_reg_rtx | |
3922 | into the insn's body (or perhaps into the bodies of other | |
3923 | load and store insn that we just made for reloading | |
3924 | and that we moved the structure into). */ | |
f759eb8b | 3925 | subst_reloads (insn); |
3c3eeea6 RK |
3926 | |
3927 | /* If this was an ASM, make sure that all the reload insns | |
3928 | we have generated are valid. If not, give an error | |
3929 | and delete them. */ | |
3930 | ||
3931 | if (asm_noperands (PATTERN (insn)) >= 0) | |
3932 | for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) | |
2c3c49de | 3933 | if (p != insn && INSN_P (p) |
3c3eeea6 | 3934 | && (recog_memoized (p) < 0 |
0eadeb15 | 3935 | || (extract_insn (p), ! constrain_operands (1)))) |
3c3eeea6 RK |
3936 | { |
3937 | error_for_asm (insn, | |
3938 | "`asm' operand requires impossible reload"); | |
ca6c03ca | 3939 | delete_insn (p); |
3c3eeea6 | 3940 | } |
32131a9c | 3941 | } |
5d7ef82a BS |
3942 | |
3943 | if (num_eliminable && chain->need_elim) | |
3944 | update_eliminable_offsets (); | |
3945 | ||
32131a9c RK |
3946 | /* Any previously reloaded spilled pseudo reg, stored in this insn, |
3947 | is no longer validly lying around to save a future reload. | |
3948 | Note that this does not detect pseudos that were reloaded | |
3949 | for this insn in order to be stored in | |
3950 | (obeying register constraints). That is correct; such reload | |
3951 | registers ARE still valid. */ | |
84832317 | 3952 | note_stores (oldpat, forget_old_reloads_1, NULL); |
32131a9c RK |
3953 | |
3954 | /* There may have been CLOBBER insns placed after INSN. So scan | |
3955 | between INSN and NEXT and use them to forget old reloads. */ | |
7609e720 | 3956 | for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) |
32131a9c | 3957 | if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) |
84832317 | 3958 | note_stores (PATTERN (x), forget_old_reloads_1, NULL); |
32131a9c RK |
3959 | |
3960 | #ifdef AUTO_INC_DEC | |
cb2afeb3 R |
3961 | /* Likewise for regs altered by auto-increment in this insn. |
3962 | REG_INC notes have been changed by reloading: | |
3963 | find_reloads_address_1 records substitutions for them, | |
3964 | which have been performed by subst_reloads above. */ | |
3965 | for (i = n_reloads - 1; i >= 0; i--) | |
3966 | { | |
eceef4c9 | 3967 | rtx in_reg = rld[i].in_reg; |
cb2afeb3 R |
3968 | if (in_reg) |
3969 | { | |
3970 | enum rtx_code code = GET_CODE (in_reg); | |
3971 | /* PRE_INC / PRE_DEC will have the reload register ending up | |
3972 | with the same value as the stack slot, but that doesn't | |
3973 | hold true for POST_INC / POST_DEC. Either we have to | |
3974 | convert the memory access to a true POST_INC / POST_DEC, | |
3975 | or we can't use the reload register for inheritance. */ | |
3976 | if ((code == POST_INC || code == POST_DEC) | |
3977 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 3978 | REGNO (rld[i].reg_rtx)) |
04bbb0c5 JW |
3979 | /* Make sure it is the inc/dec pseudo, and not |
3980 | some other (e.g. output operand) pseudo. */ | |
eceef4c9 | 3981 | && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
04bbb0c5 | 3982 | == REGNO (XEXP (in_reg, 0)))) |
05d10675 | 3983 | |
cb2afeb3 | 3984 | { |
eceef4c9 | 3985 | rtx reload_reg = rld[i].reg_rtx; |
cb2afeb3 R |
3986 | enum machine_mode mode = GET_MODE (reload_reg); |
3987 | int n = 0; | |
3988 | rtx p; | |
3989 | ||
3990 | for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) | |
3991 | { | |
3992 | /* We really want to ignore REG_INC notes here, so | |
3993 | use PATTERN (p) as argument to reg_set_p . */ | |
3994 | if (reg_set_p (reload_reg, PATTERN (p))) | |
3995 | break; | |
4b983fdc | 3996 | n = count_occurrences (PATTERN (p), reload_reg, 0); |
cb2afeb3 R |
3997 | if (! n) |
3998 | continue; | |
3999 | if (n == 1) | |
f67c2384 JL |
4000 | { |
4001 | n = validate_replace_rtx (reload_reg, | |
4002 | gen_rtx (code, mode, | |
4003 | reload_reg), | |
4004 | p); | |
4005 | ||
4006 | /* We must also verify that the constraints | |
4007 | are met after the replacement. */ | |
4008 | extract_insn (p); | |
4009 | if (n) | |
4010 | n = constrain_operands (1); | |
4011 | else | |
4012 | break; | |
4013 | ||
4014 | /* If the constraints were not met, then | |
4015 | undo the replacement. */ | |
4016 | if (!n) | |
4017 | { | |
4018 | validate_replace_rtx (gen_rtx (code, mode, | |
4019 | reload_reg), | |
4020 | reload_reg, p); | |
4021 | break; | |
4022 | } | |
05d10675 | 4023 | |
f67c2384 | 4024 | } |
cb2afeb3 R |
4025 | break; |
4026 | } | |
4027 | if (n == 1) | |
02eb1393 R |
4028 | { |
4029 | REG_NOTES (p) | |
4030 | = gen_rtx_EXPR_LIST (REG_INC, reload_reg, | |
4031 | REG_NOTES (p)); | |
4032 | /* Mark this as having an output reload so that the | |
4033 | REG_INC processing code below won't invalidate | |
4034 | the reload for inheritance. */ | |
4035 | SET_HARD_REG_BIT (reg_is_output_reload, | |
4036 | REGNO (reload_reg)); | |
4037 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; | |
4038 | } | |
cb2afeb3 | 4039 | else |
1d7254c5 | 4040 | forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, |
84832317 | 4041 | NULL); |
cb2afeb3 | 4042 | } |
02eb1393 R |
4043 | else if ((code == PRE_INC || code == PRE_DEC) |
4044 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 4045 | REGNO (rld[i].reg_rtx)) |
02eb1393 R |
4046 | /* Make sure it is the inc/dec pseudo, and not |
4047 | some other (e.g. output operand) pseudo. */ | |
eceef4c9 | 4048 | && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
02eb1393 R |
4049 | == REGNO (XEXP (in_reg, 0)))) |
4050 | { | |
4051 | SET_HARD_REG_BIT (reg_is_output_reload, | |
eceef4c9 | 4052 | REGNO (rld[i].reg_rtx)); |
02eb1393 R |
4053 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; |
4054 | } | |
cb2afeb3 R |
4055 | } |
4056 | } | |
02eb1393 R |
4057 | /* If a pseudo that got a hard register is auto-incremented, |
4058 | we must purge records of copying it into pseudos without | |
4059 | hard registers. */ | |
32131a9c RK |
4060 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) |
4061 | if (REG_NOTE_KIND (x) == REG_INC) | |
4062 | { | |
4063 | /* See if this pseudo reg was reloaded in this insn. | |
4064 | If so, its last-reload info is still valid | |
4065 | because it is based on this insn's reload. */ | |
4066 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 4067 | if (rld[i].out == XEXP (x, 0)) |
32131a9c RK |
4068 | break; |
4069 | ||
08fb99fa | 4070 | if (i == n_reloads) |
84832317 | 4071 | forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); |
32131a9c RK |
4072 | } |
4073 | #endif | |
4074 | } | |
4075 | /* A reload reg's contents are unknown after a label. */ | |
4076 | if (GET_CODE (insn) == CODE_LABEL) | |
e6e52be0 | 4077 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c RK |
4078 | |
4079 | /* Don't assume a reload reg is still good after a call insn | |
4080 | if it is a call-used reg. */ | |
546b63fb | 4081 | else if (GET_CODE (insn) == CALL_INSN) |
8e2e89f7 | 4082 | AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set); |
32131a9c | 4083 | } |
ff154f78 MM |
4084 | |
4085 | /* Clean up. */ | |
4086 | free (reg_last_reload_reg); | |
4087 | free (reg_has_output_reload); | |
32131a9c RK |
4088 | } |
4089 | ||
4090 | /* Discard all record of any value reloaded from X, | |
4091 | or reloaded in X from someplace else; | |
4092 | unless X is an output reload reg of the current insn. | |
4093 | ||
4094 | X may be a hard reg (the reload reg) | |
4095 | or it may be a pseudo reg that was reloaded from. */ | |
4096 | ||
4097 | static void | |
84832317 | 4098 | forget_old_reloads_1 (x, ignored, data) |
32131a9c | 4099 | rtx x; |
487a6e06 | 4100 | rtx ignored ATTRIBUTE_UNUSED; |
84832317 | 4101 | void *data ATTRIBUTE_UNUSED; |
32131a9c | 4102 | { |
770ae6cc RK |
4103 | unsigned int regno; |
4104 | unsigned int nr; | |
0a2e51a9 | 4105 | |
ddef6bc7 JJ |
4106 | /* note_stores does give us subregs of hard regs, |
4107 | subreg_regno_offset will abort if it is not a hard reg. */ | |
0a2e51a9 RS |
4108 | while (GET_CODE (x) == SUBREG) |
4109 | { | |
fefac463 AH |
4110 | /* We ignore the subreg offset when calculating the regno, |
4111 | because we are using the entire underlying hard register | |
4112 | below. */ | |
0a2e51a9 RS |
4113 | x = SUBREG_REG (x); |
4114 | } | |
32131a9c RK |
4115 | |
4116 | if (GET_CODE (x) != REG) | |
4117 | return; | |
4118 | ||
fefac463 | 4119 | regno = REGNO (x); |
32131a9c RK |
4120 | |
4121 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4122 | nr = 1; | |
4123 | else | |
4124 | { | |
770ae6cc RK |
4125 | unsigned int i; |
4126 | ||
32131a9c RK |
4127 | nr = HARD_REGNO_NREGS (regno, GET_MODE (x)); |
4128 | /* Storing into a spilled-reg invalidates its contents. | |
4129 | This can happen if a block-local pseudo is allocated to that reg | |
4130 | and it wasn't spilled because this block's total need is 0. | |
4131 | Then some insn might have an optional reload and use this reg. */ | |
4132 | for (i = 0; i < nr; i++) | |
e6e52be0 R |
4133 | /* But don't do this if the reg actually serves as an output |
4134 | reload reg in the current instruction. */ | |
4135 | if (n_reloads == 0 | |
4136 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) | |
5d77a50c BS |
4137 | { |
4138 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); | |
4139 | spill_reg_store[regno + i] = 0; | |
4140 | } | |
32131a9c RK |
4141 | } |
4142 | ||
4143 | /* Since value of X has changed, | |
4144 | forget any value previously copied from it. */ | |
4145 | ||
4146 | while (nr-- > 0) | |
4147 | /* But don't forget a copy if this is the output reload | |
4148 | that establishes the copy's validity. */ | |
4149 | if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) | |
4150 | reg_last_reload_reg[regno + nr] = 0; | |
4151 | } | |
4152 | \f | |
32131a9c RK |
4153 | /* The following HARD_REG_SETs indicate when each hard register is |
4154 | used for a reload of various parts of the current insn. */ | |
4155 | ||
9e3a9cf2 BS |
4156 | /* If reg is unavailable for all reloads. */ |
4157 | static HARD_REG_SET reload_reg_unavailable; | |
32131a9c RK |
4158 | /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ |
4159 | static HARD_REG_SET reload_reg_used; | |
546b63fb RK |
4160 | /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ |
4161 | static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4162 | /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ |
4163 | static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4164 | /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ |
4165 | static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4166 | /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ |
4167 | static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4168 | /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ |
4169 | static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; | |
4170 | /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ | |
4171 | static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
4172 | /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ |
4173 | static HARD_REG_SET reload_reg_used_in_op_addr; | |
893bc853 RK |
4174 | /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ |
4175 | static HARD_REG_SET reload_reg_used_in_op_addr_reload; | |
546b63fb RK |
4176 | /* If reg is in use for a RELOAD_FOR_INSN reload. */ |
4177 | static HARD_REG_SET reload_reg_used_in_insn; | |
4178 | /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ | |
4179 | static HARD_REG_SET reload_reg_used_in_other_addr; | |
32131a9c RK |
4180 | |
4181 | /* If reg is in use as a reload reg for any sort of reload. */ | |
4182 | static HARD_REG_SET reload_reg_used_at_all; | |
4183 | ||
be7ae2a4 RK |
4184 | /* If reg is use as an inherited reload. We just mark the first register |
4185 | in the group. */ | |
4186 | static HARD_REG_SET reload_reg_used_for_inherit; | |
4187 | ||
f1db3576 JL |
4188 | /* Records which hard regs are used in any way, either as explicit use or |
4189 | by being allocated to a pseudo during any point of the current insn. */ | |
4190 | static HARD_REG_SET reg_used_in_insn; | |
297927a8 | 4191 | |
546b63fb RK |
4192 | /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and |
4193 | TYPE. MODE is used to indicate how many consecutive regs are | |
4194 | actually used. */ | |
32131a9c RK |
4195 | |
4196 | static void | |
546b63fb | 4197 | mark_reload_reg_in_use (regno, opnum, type, mode) |
770ae6cc | 4198 | unsigned int regno; |
546b63fb RK |
4199 | int opnum; |
4200 | enum reload_type type; | |
32131a9c RK |
4201 | enum machine_mode mode; |
4202 | { | |
770ae6cc RK |
4203 | unsigned int nregs = HARD_REGNO_NREGS (regno, mode); |
4204 | unsigned int i; | |
32131a9c RK |
4205 | |
4206 | for (i = regno; i < nregs + regno; i++) | |
4207 | { | |
546b63fb | 4208 | switch (type) |
32131a9c RK |
4209 | { |
4210 | case RELOAD_OTHER: | |
4211 | SET_HARD_REG_BIT (reload_reg_used, i); | |
4212 | break; | |
4213 | ||
546b63fb RK |
4214 | case RELOAD_FOR_INPUT_ADDRESS: |
4215 | SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); | |
32131a9c RK |
4216 | break; |
4217 | ||
47c8cf91 ILT |
4218 | case RELOAD_FOR_INPADDR_ADDRESS: |
4219 | SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); | |
4220 | break; | |
4221 | ||
546b63fb RK |
4222 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4223 | SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); | |
32131a9c RK |
4224 | break; |
4225 | ||
47c8cf91 ILT |
4226 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4227 | SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); | |
4228 | break; | |
4229 | ||
32131a9c RK |
4230 | case RELOAD_FOR_OPERAND_ADDRESS: |
4231 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
4232 | break; | |
4233 | ||
893bc853 RK |
4234 | case RELOAD_FOR_OPADDR_ADDR: |
4235 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); | |
4236 | break; | |
4237 | ||
546b63fb RK |
4238 | case RELOAD_FOR_OTHER_ADDRESS: |
4239 | SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); | |
4240 | break; | |
4241 | ||
32131a9c | 4242 | case RELOAD_FOR_INPUT: |
546b63fb | 4243 | SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); |
32131a9c RK |
4244 | break; |
4245 | ||
4246 | case RELOAD_FOR_OUTPUT: | |
546b63fb RK |
4247 | SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); |
4248 | break; | |
4249 | ||
4250 | case RELOAD_FOR_INSN: | |
4251 | SET_HARD_REG_BIT (reload_reg_used_in_insn, i); | |
32131a9c RK |
4252 | break; |
4253 | } | |
4254 | ||
4255 | SET_HARD_REG_BIT (reload_reg_used_at_all, i); | |
4256 | } | |
4257 | } | |
4258 | ||
be7ae2a4 RK |
4259 | /* Similarly, but show REGNO is no longer in use for a reload. */ |
4260 | ||
4261 | static void | |
4262 | clear_reload_reg_in_use (regno, opnum, type, mode) | |
770ae6cc | 4263 | unsigned int regno; |
be7ae2a4 RK |
4264 | int opnum; |
4265 | enum reload_type type; | |
4266 | enum machine_mode mode; | |
4267 | { | |
770ae6cc RK |
4268 | unsigned int nregs = HARD_REGNO_NREGS (regno, mode); |
4269 | unsigned int start_regno, end_regno, r; | |
be7ae2a4 | 4270 | int i; |
cb2afeb3 R |
4271 | /* A complication is that for some reload types, inheritance might |
4272 | allow multiple reloads of the same types to share a reload register. | |
4273 | We set check_opnum if we have to check only reloads with the same | |
4274 | operand number, and check_any if we have to check all reloads. */ | |
4275 | int check_opnum = 0; | |
4276 | int check_any = 0; | |
4277 | HARD_REG_SET *used_in_set; | |
be7ae2a4 | 4278 | |
cb2afeb3 | 4279 | switch (type) |
be7ae2a4 | 4280 | { |
cb2afeb3 R |
4281 | case RELOAD_OTHER: |
4282 | used_in_set = &reload_reg_used; | |
4283 | break; | |
be7ae2a4 | 4284 | |
cb2afeb3 R |
4285 | case RELOAD_FOR_INPUT_ADDRESS: |
4286 | used_in_set = &reload_reg_used_in_input_addr[opnum]; | |
4287 | break; | |
be7ae2a4 | 4288 | |
cb2afeb3 R |
4289 | case RELOAD_FOR_INPADDR_ADDRESS: |
4290 | check_opnum = 1; | |
4291 | used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; | |
4292 | break; | |
47c8cf91 | 4293 | |
cb2afeb3 R |
4294 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4295 | used_in_set = &reload_reg_used_in_output_addr[opnum]; | |
4296 | break; | |
be7ae2a4 | 4297 | |
cb2afeb3 R |
4298 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4299 | check_opnum = 1; | |
4300 | used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; | |
4301 | break; | |
47c8cf91 | 4302 | |
cb2afeb3 R |
4303 | case RELOAD_FOR_OPERAND_ADDRESS: |
4304 | used_in_set = &reload_reg_used_in_op_addr; | |
4305 | break; | |
be7ae2a4 | 4306 | |
cb2afeb3 R |
4307 | case RELOAD_FOR_OPADDR_ADDR: |
4308 | check_any = 1; | |
4309 | used_in_set = &reload_reg_used_in_op_addr_reload; | |
4310 | break; | |
893bc853 | 4311 | |
cb2afeb3 R |
4312 | case RELOAD_FOR_OTHER_ADDRESS: |
4313 | used_in_set = &reload_reg_used_in_other_addr; | |
4314 | check_any = 1; | |
4315 | break; | |
be7ae2a4 | 4316 | |
cb2afeb3 R |
4317 | case RELOAD_FOR_INPUT: |
4318 | used_in_set = &reload_reg_used_in_input[opnum]; | |
4319 | break; | |
be7ae2a4 | 4320 | |
cb2afeb3 R |
4321 | case RELOAD_FOR_OUTPUT: |
4322 | used_in_set = &reload_reg_used_in_output[opnum]; | |
4323 | break; | |
be7ae2a4 | 4324 | |
cb2afeb3 R |
4325 | case RELOAD_FOR_INSN: |
4326 | used_in_set = &reload_reg_used_in_insn; | |
4327 | break; | |
4328 | default: | |
4329 | abort (); | |
4330 | } | |
4331 | /* We resolve conflicts with remaining reloads of the same type by | |
68e82b83 | 4332 | excluding the intervals of reload registers by them from the |
cb2afeb3 R |
4333 | interval of freed reload registers. Since we only keep track of |
4334 | one set of interval bounds, we might have to exclude somewhat | |
3e92902c | 4335 | more than what would be necessary if we used a HARD_REG_SET here. |
cb2afeb3 R |
4336 | But this should only happen very infrequently, so there should |
4337 | be no reason to worry about it. */ | |
05d10675 | 4338 | |
cb2afeb3 R |
4339 | start_regno = regno; |
4340 | end_regno = regno + nregs; | |
4341 | if (check_opnum || check_any) | |
4342 | { | |
4343 | for (i = n_reloads - 1; i >= 0; i--) | |
4344 | { | |
eceef4c9 BS |
4345 | if (rld[i].when_needed == type |
4346 | && (check_any || rld[i].opnum == opnum) | |
4347 | && rld[i].reg_rtx) | |
cb2afeb3 | 4348 | { |
770ae6cc RK |
4349 | unsigned int conflict_start = true_regnum (rld[i].reg_rtx); |
4350 | unsigned int conflict_end | |
cb2afeb3 | 4351 | = (conflict_start |
8ec450a4 | 4352 | + HARD_REGNO_NREGS (conflict_start, rld[i].mode)); |
cb2afeb3 R |
4353 | |
4354 | /* If there is an overlap with the first to-be-freed register, | |
4355 | adjust the interval start. */ | |
4356 | if (conflict_start <= start_regno && conflict_end > start_regno) | |
4357 | start_regno = conflict_end; | |
4358 | /* Otherwise, if there is a conflict with one of the other | |
4359 | to-be-freed registers, adjust the interval end. */ | |
4360 | if (conflict_start > start_regno && conflict_start < end_regno) | |
4361 | end_regno = conflict_start; | |
4362 | } | |
be7ae2a4 RK |
4363 | } |
4364 | } | |
770ae6cc RK |
4365 | |
4366 | for (r = start_regno; r < end_regno; r++) | |
4367 | CLEAR_HARD_REG_BIT (*used_in_set, r); | |
be7ae2a4 RK |
4368 | } |
4369 | ||
32131a9c | 4370 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort |
546b63fb | 4371 | specified by OPNUM and TYPE. */ |
32131a9c RK |
4372 | |
4373 | static int | |
546b63fb | 4374 | reload_reg_free_p (regno, opnum, type) |
770ae6cc | 4375 | unsigned int regno; |
546b63fb RK |
4376 | int opnum; |
4377 | enum reload_type type; | |
32131a9c | 4378 | { |
546b63fb RK |
4379 | int i; |
4380 | ||
2edc8d65 | 4381 | /* In use for a RELOAD_OTHER means it's not available for anything. */ |
9e3a9cf2 BS |
4382 | if (TEST_HARD_REG_BIT (reload_reg_used, regno) |
4383 | || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) | |
32131a9c | 4384 | return 0; |
546b63fb RK |
4385 | |
4386 | switch (type) | |
32131a9c RK |
4387 | { |
4388 | case RELOAD_OTHER: | |
2edc8d65 RK |
4389 | /* In use for anything means we can't use it for RELOAD_OTHER. */ |
4390 | if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) | |
224f1d71 RK |
4391 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4392 | || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) | |
4393 | return 0; | |
4394 | ||
4395 | for (i = 0; i < reload_n_operands; i++) | |
4396 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4397 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
224f1d71 | 4398 | || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
47c8cf91 | 4399 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
224f1d71 RK |
4400 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) |
4401 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4402 | return 0; | |
4403 | ||
4404 | return 1; | |
32131a9c | 4405 | |
32131a9c | 4406 | case RELOAD_FOR_INPUT: |
546b63fb RK |
4407 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4408 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
4409 | return 0; | |
4410 | ||
893bc853 RK |
4411 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4412 | return 0; | |
4413 | ||
546b63fb RK |
4414 | /* If it is used for some other input, can't use it. */ |
4415 | for (i = 0; i < reload_n_operands; i++) | |
4416 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4417 | return 0; | |
4418 | ||
4419 | /* If it is used in a later operand's address, can't use it. */ | |
4420 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4421 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4422 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4423 | return 0; |
4424 | ||
4425 | return 1; | |
4426 | ||
4427 | case RELOAD_FOR_INPUT_ADDRESS: | |
4428 | /* Can't use a register if it is used for an input address for this | |
4429 | operand or used as an input in an earlier one. */ | |
47c8cf91 ILT |
4430 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) |
4431 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) | |
4432 | return 0; | |
4433 | ||
4434 | for (i = 0; i < opnum; i++) | |
4435 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4436 | return 0; | |
4437 | ||
4438 | return 1; | |
4439 | ||
4440 | case RELOAD_FOR_INPADDR_ADDRESS: | |
4441 | /* Can't use a register if it is used for an input address | |
05d10675 BS |
4442 | for this operand or used as an input in an earlier |
4443 | one. */ | |
47c8cf91 | 4444 | if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) |
546b63fb RK |
4445 | return 0; |
4446 | ||
4447 | for (i = 0; i < opnum; i++) | |
4448 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4449 | return 0; | |
4450 | ||
4451 | return 1; | |
4452 | ||
4453 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
4454 | /* Can't use a register if it is used for an output address for this | |
d1d18b46 DJ |
4455 | operand or used as an output in this or a later operand. Note |
4456 | that multiple output operands are emitted in reverse order, so | |
4457 | the conflicting ones are those with lower indices. */ | |
546b63fb RK |
4458 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) |
4459 | return 0; | |
4460 | ||
d1d18b46 | 4461 | for (i = 0; i <= opnum; i++) |
546b63fb RK |
4462 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4463 | return 0; | |
4464 | ||
4465 | return 1; | |
4466 | ||
47c8cf91 ILT |
4467 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4468 | /* Can't use a register if it is used for an output address | |
05d10675 | 4469 | for this operand or used as an output in this or a |
d1d18b46 DJ |
4470 | later operand. Note that multiple output operands are |
4471 | emitted in reverse order, so the conflicting ones are | |
4472 | those with lower indices. */ | |
47c8cf91 ILT |
4473 | if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) |
4474 | return 0; | |
4475 | ||
d1d18b46 | 4476 | for (i = 0; i <= opnum; i++) |
47c8cf91 ILT |
4477 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4478 | return 0; | |
4479 | ||
4480 | return 1; | |
4481 | ||
32131a9c | 4482 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4483 | for (i = 0; i < reload_n_operands; i++) |
4484 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4485 | return 0; | |
4486 | ||
4487 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4488 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4489 | ||
893bc853 RK |
4490 | case RELOAD_FOR_OPADDR_ADDR: |
4491 | for (i = 0; i < reload_n_operands; i++) | |
05d10675 BS |
4492 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4493 | return 0; | |
893bc853 | 4494 | |
a94ce333 | 4495 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); |
893bc853 | 4496 | |
32131a9c | 4497 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4498 | /* This cannot share a register with RELOAD_FOR_INSN reloads, other |
d1d18b46 DJ |
4499 | outputs, or an operand address for this or an earlier output. |
4500 | Note that multiple output operands are emitted in reverse order, | |
4501 | so the conflicting ones are those with higher indices. */ | |
546b63fb RK |
4502 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) |
4503 | return 0; | |
4504 | ||
4505 | for (i = 0; i < reload_n_operands; i++) | |
4506 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4507 | return 0; | |
4508 | ||
d1d18b46 | 4509 | for (i = opnum; i < reload_n_operands; i++) |
47c8cf91 ILT |
4510 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4511 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4512 | return 0; |
4513 | ||
4514 | return 1; | |
4515 | ||
4516 | case RELOAD_FOR_INSN: | |
4517 | for (i = 0; i < reload_n_operands; i++) | |
4518 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) | |
4519 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4520 | return 0; | |
4521 | ||
4522 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4523 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4524 | ||
4525 | case RELOAD_FOR_OTHER_ADDRESS: | |
4526 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
32131a9c RK |
4527 | } |
4528 | abort (); | |
4529 | } | |
4530 | ||
32131a9c | 4531 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
546b63fb | 4532 | needed for the part of the insn specified by OPNUM and TYPE, |
32131a9c RK |
4533 | is still available in REGNO at the end of the insn. |
4534 | ||
4535 | We can assume that the reload reg was already tested for availability | |
4536 | at the time it is needed, and we should not check this again, | |
4537 | in case the reg has already been marked in use. */ | |
4538 | ||
4539 | static int | |
546b63fb | 4540 | reload_reg_reaches_end_p (regno, opnum, type) |
770ae6cc | 4541 | unsigned int regno; |
546b63fb RK |
4542 | int opnum; |
4543 | enum reload_type type; | |
32131a9c | 4544 | { |
546b63fb RK |
4545 | int i; |
4546 | ||
4547 | switch (type) | |
32131a9c RK |
4548 | { |
4549 | case RELOAD_OTHER: | |
4550 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
4551 | its value must reach the end. */ | |
4552 | return 1; | |
4553 | ||
4554 | /* If this use is for part of the insn, | |
05d10675 | 4555 | its value reaches if no subsequent part uses the same register. |
546b63fb RK |
4556 | Just like the above function, don't try to do this with lots |
4557 | of fallthroughs. */ | |
4558 | ||
4559 | case RELOAD_FOR_OTHER_ADDRESS: | |
4560 | /* Here we check for everything else, since these don't conflict | |
4561 | with anything else and everything comes later. */ | |
4562 | ||
4563 | for (i = 0; i < reload_n_operands; i++) | |
4564 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4565 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4566 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) |
4567 | || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4568 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4569 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4570 | return 0; | |
4571 | ||
4572 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
4573 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4574 | && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
4575 | ||
4576 | case RELOAD_FOR_INPUT_ADDRESS: | |
47c8cf91 | 4577 | case RELOAD_FOR_INPADDR_ADDRESS: |
546b63fb RK |
4578 | /* Similar, except that we check only for this and subsequent inputs |
4579 | and the address of only subsequent inputs and we do not need | |
4580 | to check for RELOAD_OTHER objects since they are known not to | |
4581 | conflict. */ | |
4582 | ||
4583 | for (i = opnum; i < reload_n_operands; i++) | |
4584 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4585 | return 0; | |
4586 | ||
4587 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4588 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4589 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4590 | return 0; |
4591 | ||
4592 | for (i = 0; i < reload_n_operands; i++) | |
4593 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4594 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4595 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4596 | return 0; | |
4597 | ||
893bc853 RK |
4598 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4599 | return 0; | |
4600 | ||
2af88768 GK |
4601 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4602 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4603 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
546b63fb | 4604 | |
32131a9c | 4605 | case RELOAD_FOR_INPUT: |
546b63fb | 4606 | /* Similar to input address, except we start at the next operand for |
05d10675 | 4607 | both input and input address and we do not check for |
546b63fb RK |
4608 | RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these |
4609 | would conflict. */ | |
4610 | ||
4611 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4612 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4613 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4614 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4615 | return 0; | |
4616 | ||
0f41302f | 4617 | /* ... fall through ... */ |
546b63fb | 4618 | |
32131a9c | 4619 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4620 | /* Check outputs and their addresses. */ |
4621 | ||
4622 | for (i = 0; i < reload_n_operands; i++) | |
4623 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4624 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4625 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4626 | return 0; | |
4627 | ||
2af88768 | 4628 | return (!TEST_HARD_REG_BIT (reload_reg_used, regno)); |
546b63fb | 4629 | |
893bc853 RK |
4630 | case RELOAD_FOR_OPADDR_ADDR: |
4631 | for (i = 0; i < reload_n_operands; i++) | |
4632 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4633 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
893bc853 RK |
4634 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4635 | return 0; | |
4636 | ||
2af88768 GK |
4637 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4638 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4639 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
893bc853 | 4640 | |
546b63fb | 4641 | case RELOAD_FOR_INSN: |
893bc853 | 4642 | /* These conflict with other outputs with RELOAD_OTHER. So |
546b63fb RK |
4643 | we need only check for output addresses. */ |
4644 | ||
d1d18b46 | 4645 | opnum = reload_n_operands; |
546b63fb | 4646 | |
0f41302f | 4647 | /* ... fall through ... */ |
546b63fb | 4648 | |
32131a9c | 4649 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4650 | case RELOAD_FOR_OUTPUT_ADDRESS: |
47c8cf91 | 4651 | case RELOAD_FOR_OUTADDR_ADDRESS: |
546b63fb | 4652 | /* We already know these can't conflict with a later output. So the |
d1d18b46 DJ |
4653 | only thing to check are later output addresses. |
4654 | Note that multiple output operands are emitted in reverse order, | |
4655 | so the conflicting ones are those with lower indices. */ | |
4656 | for (i = 0; i < opnum; i++) | |
47c8cf91 ILT |
4657 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4658 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4659 | return 0; |
4660 | ||
32131a9c RK |
4661 | return 1; |
4662 | } | |
546b63fb | 4663 | |
32131a9c RK |
4664 | abort (); |
4665 | } | |
4666 | \f | |
351aa1c1 RK |
4667 | /* Return 1 if the reloads denoted by R1 and R2 cannot share a register. |
4668 | Return 0 otherwise. | |
4669 | ||
4670 | This function uses the same algorithm as reload_reg_free_p above. */ | |
4671 | ||
f5963e61 | 4672 | int |
351aa1c1 RK |
4673 | reloads_conflict (r1, r2) |
4674 | int r1, r2; | |
4675 | { | |
eceef4c9 BS |
4676 | enum reload_type r1_type = rld[r1].when_needed; |
4677 | enum reload_type r2_type = rld[r2].when_needed; | |
4678 | int r1_opnum = rld[r1].opnum; | |
4679 | int r2_opnum = rld[r2].opnum; | |
351aa1c1 | 4680 | |
2edc8d65 RK |
4681 | /* RELOAD_OTHER conflicts with everything. */ |
4682 | if (r2_type == RELOAD_OTHER) | |
351aa1c1 RK |
4683 | return 1; |
4684 | ||
4685 | /* Otherwise, check conflicts differently for each type. */ | |
4686 | ||
4687 | switch (r1_type) | |
4688 | { | |
4689 | case RELOAD_FOR_INPUT: | |
05d10675 | 4690 | return (r2_type == RELOAD_FOR_INSN |
351aa1c1 | 4691 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS |
893bc853 | 4692 | || r2_type == RELOAD_FOR_OPADDR_ADDR |
351aa1c1 | 4693 | || r2_type == RELOAD_FOR_INPUT |
47c8cf91 ILT |
4694 | || ((r2_type == RELOAD_FOR_INPUT_ADDRESS |
4695 | || r2_type == RELOAD_FOR_INPADDR_ADDRESS) | |
4696 | && r2_opnum > r1_opnum)); | |
351aa1c1 RK |
4697 | |
4698 | case RELOAD_FOR_INPUT_ADDRESS: | |
4699 | return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) | |
4700 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4701 | ||
47c8cf91 ILT |
4702 | case RELOAD_FOR_INPADDR_ADDRESS: |
4703 | return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) | |
4704 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4705 | ||
351aa1c1 RK |
4706 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4707 | return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 4708 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
351aa1c1 | 4709 | |
47c8cf91 ILT |
4710 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4711 | return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 4712 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
47c8cf91 | 4713 | |
351aa1c1 RK |
4714 | case RELOAD_FOR_OPERAND_ADDRESS: |
4715 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN | |
a94ce333 | 4716 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); |
351aa1c1 | 4717 | |
893bc853 | 4718 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 | 4719 | return (r2_type == RELOAD_FOR_INPUT |
a94ce333 | 4720 | || r2_type == RELOAD_FOR_OPADDR_ADDR); |
893bc853 | 4721 | |
351aa1c1 RK |
4722 | case RELOAD_FOR_OUTPUT: |
4723 | return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT | |
47c8cf91 ILT |
4724 | || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS |
4725 | || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) | |
d1d18b46 | 4726 | && r2_opnum >= r1_opnum)); |
351aa1c1 RK |
4727 | |
4728 | case RELOAD_FOR_INSN: | |
4729 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT | |
4730 | || r2_type == RELOAD_FOR_INSN | |
4731 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); | |
4732 | ||
4733 | case RELOAD_FOR_OTHER_ADDRESS: | |
4734 | return r2_type == RELOAD_FOR_OTHER_ADDRESS; | |
4735 | ||
adab4fc5 | 4736 | case RELOAD_OTHER: |
2edc8d65 | 4737 | return 1; |
adab4fc5 | 4738 | |
351aa1c1 RK |
4739 | default: |
4740 | abort (); | |
4741 | } | |
4742 | } | |
4743 | \f | |
32131a9c RK |
4744 | /* Indexed by reload number, 1 if incoming value |
4745 | inherited from previous insns. */ | |
4746 | char reload_inherited[MAX_RELOADS]; | |
4747 | ||
4748 | /* For an inherited reload, this is the insn the reload was inherited from, | |
4749 | if we know it. Otherwise, this is 0. */ | |
4750 | rtx reload_inheritance_insn[MAX_RELOADS]; | |
4751 | ||
4752 | /* If non-zero, this is a place to get the value of the reload, | |
4753 | rather than using reload_in. */ | |
4754 | rtx reload_override_in[MAX_RELOADS]; | |
4755 | ||
e6e52be0 R |
4756 | /* For each reload, the hard register number of the register used, |
4757 | or -1 if we did not need a register for this reload. */ | |
32131a9c RK |
4758 | int reload_spill_index[MAX_RELOADS]; |
4759 | ||
304a22dd R |
4760 | /* Subroutine of free_for_value_p, used to check a single register. |
4761 | START_REGNO is the starting regno of the full reload register | |
4762 | (possibly comprising multiple hard registers) that we are considering. */ | |
f5470689 | 4763 | |
6e684430 | 4764 | static int |
304a22dd R |
4765 | reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out, |
4766 | reloadnum, ignore_address_reloads) | |
4767 | int start_regno, regno; | |
6e684430 R |
4768 | int opnum; |
4769 | enum reload_type type; | |
f5470689 R |
4770 | rtx value, out; |
4771 | int reloadnum; | |
5828374f | 4772 | int ignore_address_reloads; |
6e684430 R |
4773 | { |
4774 | int time1; | |
09a308fe R |
4775 | /* Set if we see an input reload that must not share its reload register |
4776 | with any new earlyclobber, but might otherwise share the reload | |
4777 | register with an output or input-output reload. */ | |
4778 | int check_earlyclobber = 0; | |
6e684430 | 4779 | int i; |
dfe96118 R |
4780 | int copy = 0; |
4781 | ||
9e3a9cf2 | 4782 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) |
dc8842bf AH |
4783 | return 0; |
4784 | ||
dfe96118 R |
4785 | if (out == const0_rtx) |
4786 | { | |
4787 | copy = 1; | |
4788 | out = NULL_RTX; | |
4789 | } | |
6e684430 R |
4790 | |
4791 | /* We use some pseudo 'time' value to check if the lifetimes of the | |
4792 | new register use would overlap with the one of a previous reload | |
4793 | that is not read-only or uses a different value. | |
4794 | The 'time' used doesn't have to be linear in any shape or form, just | |
4795 | monotonic. | |
4796 | Some reload types use different 'buckets' for each operand. | |
4797 | So there are MAX_RECOG_OPERANDS different time values for each | |
cecbf6e2 R |
4798 | such reload type. |
4799 | We compute TIME1 as the time when the register for the prospective | |
4800 | new reload ceases to be live, and TIME2 for each existing | |
4801 | reload as the time when that the reload register of that reload | |
4802 | becomes live. | |
4803 | Where there is little to be gained by exact lifetime calculations, | |
4804 | we just make conservative assumptions, i.e. a longer lifetime; | |
4805 | this is done in the 'default:' cases. */ | |
6e684430 R |
4806 | switch (type) |
4807 | { | |
4808 | case RELOAD_FOR_OTHER_ADDRESS: | |
203588e7 | 4809 | /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ |
c2b4b171 | 4810 | time1 = copy ? 0 : 1; |
6e684430 | 4811 | break; |
dfe96118 R |
4812 | case RELOAD_OTHER: |
4813 | time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; | |
4814 | break; | |
05d10675 BS |
4815 | /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, |
4816 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , | |
4817 | respectively, to the time values for these, we get distinct time | |
4818 | values. To get distinct time values for each operand, we have to | |
4819 | multiply opnum by at least three. We round that up to four because | |
4820 | multiply by four is often cheaper. */ | |
6e684430 | 4821 | case RELOAD_FOR_INPADDR_ADDRESS: |
dfe96118 | 4822 | time1 = opnum * 4 + 2; |
6e684430 R |
4823 | break; |
4824 | case RELOAD_FOR_INPUT_ADDRESS: | |
dfe96118 R |
4825 | time1 = opnum * 4 + 3; |
4826 | break; | |
4827 | case RELOAD_FOR_INPUT: | |
4828 | /* All RELOAD_FOR_INPUT reloads remain live till the instruction | |
4829 | executes (inclusive). */ | |
4830 | time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; | |
6e684430 | 4831 | break; |
cb2afeb3 | 4832 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 BS |
4833 | /* opnum * 4 + 4 |
4834 | <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ | |
cb2afeb3 R |
4835 | time1 = MAX_RECOG_OPERANDS * 4 + 1; |
4836 | break; | |
4837 | case RELOAD_FOR_OPERAND_ADDRESS: | |
4838 | /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn | |
4839 | is executed. */ | |
dfe96118 R |
4840 | time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; |
4841 | break; | |
4842 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
4843 | time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; | |
6e684430 | 4844 | break; |
6e684430 | 4845 | case RELOAD_FOR_OUTPUT_ADDRESS: |
dfe96118 | 4846 | time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; |
6e684430 R |
4847 | break; |
4848 | default: | |
dfe96118 | 4849 | time1 = MAX_RECOG_OPERANDS * 5 + 5; |
6e684430 R |
4850 | } |
4851 | ||
4852 | for (i = 0; i < n_reloads; i++) | |
4853 | { | |
eceef4c9 | 4854 | rtx reg = rld[i].reg_rtx; |
6e684430 R |
4855 | if (reg && GET_CODE (reg) == REG |
4856 | && ((unsigned) regno - true_regnum (reg) | |
f4f4d0f8 | 4857 | <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1) |
f5470689 | 4858 | && i != reloadnum) |
6e684430 | 4859 | { |
304a22dd R |
4860 | rtx other_input = rld[i].in; |
4861 | ||
4862 | /* If the other reload loads the same input value, that | |
4863 | will not cause a conflict only if it's loading it into | |
4864 | the same register. */ | |
4865 | if (true_regnum (reg) != start_regno) | |
4866 | other_input = NULL_RTX; | |
4867 | if (! other_input || ! rtx_equal_p (other_input, value) | |
eceef4c9 | 4868 | || rld[i].out || out) |
6e684430 | 4869 | { |
09a308fe | 4870 | int time2; |
eceef4c9 | 4871 | switch (rld[i].when_needed) |
f5470689 R |
4872 | { |
4873 | case RELOAD_FOR_OTHER_ADDRESS: | |
4874 | time2 = 0; | |
4875 | break; | |
4876 | case RELOAD_FOR_INPADDR_ADDRESS: | |
cb2afeb3 R |
4877 | /* find_reloads makes sure that a |
4878 | RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used | |
4879 | by at most one - the first - | |
4880 | RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the | |
4881 | address reload is inherited, the address address reload | |
4882 | goes away, so we can ignore this conflict. */ | |
dfe96118 R |
4883 | if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 |
4884 | && ignore_address_reloads | |
4885 | /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. | |
4886 | Then the address address is still needed to store | |
4887 | back the new address. */ | |
eceef4c9 | 4888 | && ! rld[reloadnum].out) |
cb2afeb3 | 4889 | continue; |
dfe96118 R |
4890 | /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its |
4891 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS | |
4892 | reloads go away. */ | |
eceef4c9 | 4893 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 R |
4894 | && ignore_address_reloads |
4895 | /* Unless we are reloading an auto_inc expression. */ | |
eceef4c9 | 4896 | && ! rld[reloadnum].out) |
dfe96118 | 4897 | continue; |
eceef4c9 | 4898 | time2 = rld[i].opnum * 4 + 2; |
f5470689 R |
4899 | break; |
4900 | case RELOAD_FOR_INPUT_ADDRESS: | |
eceef4c9 | 4901 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 | 4902 | && ignore_address_reloads |
eceef4c9 | 4903 | && ! rld[reloadnum].out) |
dfe96118 | 4904 | continue; |
eceef4c9 | 4905 | time2 = rld[i].opnum * 4 + 3; |
f5470689 R |
4906 | break; |
4907 | case RELOAD_FOR_INPUT: | |
eceef4c9 | 4908 | time2 = rld[i].opnum * 4 + 4; |
09a308fe | 4909 | check_earlyclobber = 1; |
f5470689 | 4910 | break; |
eceef4c9 | 4911 | /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 |
05d10675 | 4912 | == MAX_RECOG_OPERAND * 4 */ |
cb2afeb3 | 4913 | case RELOAD_FOR_OPADDR_ADDR: |
dfe96118 R |
4914 | if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 |
4915 | && ignore_address_reloads | |
eceef4c9 | 4916 | && ! rld[reloadnum].out) |
cb2afeb3 | 4917 | continue; |
dfe96118 | 4918 | time2 = MAX_RECOG_OPERANDS * 4 + 1; |
cb2afeb3 R |
4919 | break; |
4920 | case RELOAD_FOR_OPERAND_ADDRESS: | |
dfe96118 | 4921 | time2 = MAX_RECOG_OPERANDS * 4 + 2; |
09a308fe | 4922 | check_earlyclobber = 1; |
dfe96118 R |
4923 | break; |
4924 | case RELOAD_FOR_INSN: | |
4925 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
cb2afeb3 | 4926 | break; |
f5470689 | 4927 | case RELOAD_FOR_OUTPUT: |
05d10675 BS |
4928 | /* All RELOAD_FOR_OUTPUT reloads become live just after the |
4929 | instruction is executed. */ | |
dfe96118 | 4930 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
f5470689 | 4931 | break; |
05d10675 BS |
4932 | /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with |
4933 | the RELOAD_FOR_OUTPUT reloads, so assign it the same time | |
4934 | value. */ | |
cb2afeb3 | 4935 | case RELOAD_FOR_OUTADDR_ADDRESS: |
dfe96118 R |
4936 | if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 |
4937 | && ignore_address_reloads | |
eceef4c9 | 4938 | && ! rld[reloadnum].out) |
cb2afeb3 | 4939 | continue; |
eceef4c9 | 4940 | time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; |
dfe96118 | 4941 | break; |
f5470689 | 4942 | case RELOAD_FOR_OUTPUT_ADDRESS: |
eceef4c9 | 4943 | time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; |
f5470689 R |
4944 | break; |
4945 | case RELOAD_OTHER: | |
dfe96118 R |
4946 | /* If there is no conflict in the input part, handle this |
4947 | like an output reload. */ | |
304a22dd | 4948 | if (! rld[i].in || rtx_equal_p (other_input, value)) |
f5470689 | 4949 | { |
dfe96118 | 4950 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
57850c85 | 4951 | /* Earlyclobbered outputs must conflict with inputs. */ |
09a308fe R |
4952 | if (earlyclobber_operand_p (rld[i].out)) |
4953 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
1d7254c5 | 4954 | |
f5470689 R |
4955 | break; |
4956 | } | |
dfe96118 R |
4957 | time2 = 1; |
4958 | /* RELOAD_OTHER might be live beyond instruction execution, | |
4959 | but this is not obvious when we set time2 = 1. So check | |
4960 | here if there might be a problem with the new reload | |
4961 | clobbering the register used by the RELOAD_OTHER. */ | |
4962 | if (out) | |
4963 | return 0; | |
4964 | break; | |
f5470689 | 4965 | default: |
dfe96118 | 4966 | return 0; |
f5470689 | 4967 | } |
25963977 | 4968 | if ((time1 >= time2 |
eceef4c9 | 4969 | && (! rld[i].in || rld[i].out |
304a22dd | 4970 | || ! rtx_equal_p (other_input, value))) |
eceef4c9 | 4971 | || (out && rld[reloadnum].out_reg |
701d55e8 | 4972 | && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) |
f5470689 | 4973 | return 0; |
6e684430 | 4974 | } |
6e684430 R |
4975 | } |
4976 | } | |
09a308fe R |
4977 | |
4978 | /* Earlyclobbered outputs must conflict with inputs. */ | |
4979 | if (check_earlyclobber && out && earlyclobber_operand_p (out)) | |
4980 | return 0; | |
4981 | ||
6e684430 R |
4982 | return 1; |
4983 | } | |
4984 | ||
c02cad8f BS |
4985 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
4986 | needed for the part of the insn specified by OPNUM and TYPE, | |
4987 | may be used to load VALUE into it. | |
4988 | ||
4989 | MODE is the mode in which the register is used, this is needed to | |
4990 | determine how many hard regs to test. | |
4991 | ||
4992 | Other read-only reloads with the same value do not conflict | |
4993 | unless OUT is non-zero and these other reloads have to live while | |
4994 | output reloads live. | |
4995 | If OUT is CONST0_RTX, this is a special case: it means that the | |
4996 | test should not be for using register REGNO as reload register, but | |
4997 | for copying from register REGNO into the reload register. | |
4998 | ||
4999 | RELOADNUM is the number of the reload we want to load this value for; | |
5000 | a reload does not conflict with itself. | |
5001 | ||
5002 | When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with | |
5003 | reloads that load an address for the very reload we are considering. | |
5004 | ||
5005 | The caller has to make sure that there is no conflict with the return | |
5006 | register. */ | |
5007 | ||
5008 | static int | |
5009 | free_for_value_p (regno, mode, opnum, type, value, out, reloadnum, | |
5010 | ignore_address_reloads) | |
5011 | int regno; | |
5012 | enum machine_mode mode; | |
5013 | int opnum; | |
5014 | enum reload_type type; | |
5015 | rtx value, out; | |
5016 | int reloadnum; | |
5017 | int ignore_address_reloads; | |
5018 | { | |
5019 | int nregs = HARD_REGNO_NREGS (regno, mode); | |
5020 | while (nregs-- > 0) | |
304a22dd R |
5021 | if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type, |
5022 | value, out, reloadnum, | |
5023 | ignore_address_reloads)) | |
c02cad8f BS |
5024 | return 0; |
5025 | return 1; | |
5026 | } | |
5027 | ||
ff6534ad BS |
5028 | /* Determine whether the reload reg X overlaps any rtx'es used for |
5029 | overriding inheritance. Return nonzero if so. */ | |
5030 | ||
5031 | static int | |
5032 | conflicts_with_override (x) | |
5033 | rtx x; | |
5034 | { | |
5035 | int i; | |
5036 | for (i = 0; i < n_reloads; i++) | |
5037 | if (reload_override_in[i] | |
5038 | && reg_overlap_mentioned_p (x, reload_override_in[i])) | |
5039 | return 1; | |
5040 | return 0; | |
5041 | } | |
5042 | \f | |
67e61fe7 BS |
5043 | /* Give an error message saying we failed to find a reload for INSN, |
5044 | and clear out reload R. */ | |
5045 | static void | |
5046 | failed_reload (insn, r) | |
5047 | rtx insn; | |
5048 | int r; | |
5049 | { | |
5050 | if (asm_noperands (PATTERN (insn)) < 0) | |
5051 | /* It's the compiler's fault. */ | |
1f978f5f | 5052 | fatal_insn ("could not find a spill register", insn); |
67e61fe7 BS |
5053 | |
5054 | /* It's the user's fault; the operand's mode and constraint | |
5055 | don't match. Disable this reload so we don't crash in final. */ | |
5056 | error_for_asm (insn, | |
5057 | "`asm' operand constraint incompatible with operand size"); | |
5058 | rld[r].in = 0; | |
5059 | rld[r].out = 0; | |
5060 | rld[r].reg_rtx = 0; | |
5061 | rld[r].optional = 1; | |
5062 | rld[r].secondary_p = 1; | |
5063 | } | |
5064 | ||
5065 | /* I is the index in SPILL_REG_RTX of the reload register we are to allocate | |
5066 | for reload R. If it's valid, get an rtx for it. Return nonzero if | |
5067 | successful. */ | |
5068 | static int | |
5069 | set_reload_reg (i, r) | |
5070 | int i, r; | |
5071 | { | |
5072 | int regno; | |
5073 | rtx reg = spill_reg_rtx[i]; | |
5074 | ||
5075 | if (reg == 0 || GET_MODE (reg) != rld[r].mode) | |
5076 | spill_reg_rtx[i] = reg | |
5077 | = gen_rtx_REG (rld[r].mode, spill_regs[i]); | |
5078 | ||
5079 | regno = true_regnum (reg); | |
5080 | ||
5081 | /* Detect when the reload reg can't hold the reload mode. | |
5082 | This used to be one `if', but Sequent compiler can't handle that. */ | |
5083 | if (HARD_REGNO_MODE_OK (regno, rld[r].mode)) | |
5084 | { | |
5085 | enum machine_mode test_mode = VOIDmode; | |
5086 | if (rld[r].in) | |
5087 | test_mode = GET_MODE (rld[r].in); | |
5088 | /* If rld[r].in has VOIDmode, it means we will load it | |
5089 | in whatever mode the reload reg has: to wit, rld[r].mode. | |
5090 | We have already tested that for validity. */ | |
5091 | /* Aside from that, we need to test that the expressions | |
5092 | to reload from or into have modes which are valid for this | |
5093 | reload register. Otherwise the reload insns would be invalid. */ | |
5094 | if (! (rld[r].in != 0 && test_mode != VOIDmode | |
5095 | && ! HARD_REGNO_MODE_OK (regno, test_mode))) | |
5096 | if (! (rld[r].out != 0 | |
5097 | && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out)))) | |
5098 | { | |
5099 | /* The reg is OK. */ | |
5100 | last_spill_reg = i; | |
5101 | ||
5102 | /* Mark as in use for this insn the reload regs we use | |
5103 | for this. */ | |
5104 | mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, | |
5105 | rld[r].when_needed, rld[r].mode); | |
5106 | ||
5107 | rld[r].reg_rtx = reg; | |
5108 | reload_spill_index[r] = spill_regs[i]; | |
5109 | return 1; | |
5110 | } | |
5111 | } | |
5112 | return 0; | |
5113 | } | |
5114 | ||
32131a9c RK |
5115 | /* Find a spill register to use as a reload register for reload R. |
5116 | LAST_RELOAD is non-zero if this is the last reload for the insn being | |
5117 | processed. | |
5118 | ||
eceef4c9 | 5119 | Set rld[R].reg_rtx to the register allocated. |
32131a9c | 5120 | |
f5d8c9f4 BS |
5121 | We return 1 if successful, or 0 if we couldn't find a spill reg and |
5122 | we didn't change anything. */ | |
32131a9c RK |
5123 | |
5124 | static int | |
f5d8c9f4 | 5125 | allocate_reload_reg (chain, r, last_reload) |
272df862 | 5126 | struct insn_chain *chain ATTRIBUTE_UNUSED; |
32131a9c | 5127 | int r; |
32131a9c | 5128 | int last_reload; |
32131a9c | 5129 | { |
67e61fe7 | 5130 | int i, pass, count; |
32131a9c RK |
5131 | |
5132 | /* If we put this reload ahead, thinking it is a group, | |
5133 | then insist on finding a group. Otherwise we can grab a | |
a8fdc208 | 5134 | reg that some other reload needs. |
32131a9c RK |
5135 | (That can happen when we have a 68000 DATA_OR_FP_REG |
5136 | which is a group of data regs or one fp reg.) | |
5137 | We need not be so restrictive if there are no more reloads | |
5138 | for this insn. | |
5139 | ||
5140 | ??? Really it would be nicer to have smarter handling | |
5141 | for that kind of reg class, where a problem like this is normal. | |
5142 | Perhaps those classes should be avoided for reloading | |
5143 | by use of more alternatives. */ | |
5144 | ||
8ec450a4 | 5145 | int force_group = rld[r].nregs > 1 && ! last_reload; |
32131a9c RK |
5146 | |
5147 | /* If we want a single register and haven't yet found one, | |
5148 | take any reg in the right class and not in use. | |
5149 | If we want a consecutive group, here is where we look for it. | |
5150 | ||
5151 | We use two passes so we can first look for reload regs to | |
5152 | reuse, which are already in use for other reloads in this insn, | |
5153 | and only then use additional registers. | |
5154 | I think that maximizing reuse is needed to make sure we don't | |
5155 | run out of reload regs. Suppose we have three reloads, and | |
5156 | reloads A and B can share regs. These need two regs. | |
5157 | Suppose A and B are given different regs. | |
5158 | That leaves none for C. */ | |
5159 | for (pass = 0; pass < 2; pass++) | |
5160 | { | |
5161 | /* I is the index in spill_regs. | |
5162 | We advance it round-robin between insns to use all spill regs | |
5163 | equally, so that inherited reloads have a chance | |
f5d8c9f4 BS |
5164 | of leapfrogging each other. */ |
5165 | ||
5166 | i = last_spill_reg; | |
05d10675 | 5167 | |
a5339699 | 5168 | for (count = 0; count < n_spills; count++) |
32131a9c | 5169 | { |
eceef4c9 | 5170 | int class = (int) rld[r].class; |
03acd8f8 | 5171 | int regnum; |
32131a9c | 5172 | |
03acd8f8 BS |
5173 | i++; |
5174 | if (i >= n_spills) | |
5175 | i -= n_spills; | |
5176 | regnum = spill_regs[i]; | |
32131a9c | 5177 | |
eceef4c9 BS |
5178 | if ((reload_reg_free_p (regnum, rld[r].opnum, |
5179 | rld[r].when_needed) | |
5180 | || (rld[r].in | |
05d10675 BS |
5181 | /* We check reload_reg_used to make sure we |
5182 | don't clobber the return register. */ | |
03acd8f8 | 5183 | && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) |
c02cad8f BS |
5184 | && free_for_value_p (regnum, rld[r].mode, rld[r].opnum, |
5185 | rld[r].when_needed, rld[r].in, | |
5186 | rld[r].out, r, 1))) | |
03acd8f8 | 5187 | && TEST_HARD_REG_BIT (reg_class_contents[class], regnum) |
8ec450a4 | 5188 | && HARD_REGNO_MODE_OK (regnum, rld[r].mode) |
be7ae2a4 RK |
5189 | /* Look first for regs to share, then for unshared. But |
5190 | don't share regs used for inherited reloads; they are | |
5191 | the ones we want to preserve. */ | |
5192 | && (pass | |
5193 | || (TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
03acd8f8 | 5194 | regnum) |
be7ae2a4 | 5195 | && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, |
03acd8f8 | 5196 | regnum)))) |
32131a9c | 5197 | { |
8ec450a4 | 5198 | int nr = HARD_REGNO_NREGS (regnum, rld[r].mode); |
32131a9c RK |
5199 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG |
5200 | (on 68000) got us two FP regs. If NR is 1, | |
5201 | we would reject both of them. */ | |
5202 | if (force_group) | |
67e61fe7 | 5203 | nr = rld[r].nregs; |
32131a9c RK |
5204 | /* If we need only one reg, we have already won. */ |
5205 | if (nr == 1) | |
5206 | { | |
5207 | /* But reject a single reg if we demand a group. */ | |
5208 | if (force_group) | |
5209 | continue; | |
5210 | break; | |
5211 | } | |
5212 | /* Otherwise check that as many consecutive regs as we need | |
f5d8c9f4 BS |
5213 | are available here. */ |
5214 | while (nr > 1) | |
5215 | { | |
5216 | int regno = regnum + nr - 1; | |
5217 | if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
5218 | && spill_reg_order[regno] >= 0 | |
5219 | && reload_reg_free_p (regno, rld[r].opnum, | |
5220 | rld[r].when_needed))) | |
5221 | break; | |
5222 | nr--; | |
5223 | } | |
32131a9c RK |
5224 | if (nr == 1) |
5225 | break; | |
5226 | } | |
5227 | } | |
5228 | ||
5229 | /* If we found something on pass 1, omit pass 2. */ | |
5230 | if (count < n_spills) | |
5231 | break; | |
5232 | } | |
1d7254c5 | 5233 | |
32131a9c | 5234 | /* We should have found a spill register by now. */ |
f5d8c9f4 | 5235 | if (count >= n_spills) |
32131a9c RK |
5236 | return 0; |
5237 | ||
f5d8c9f4 BS |
5238 | /* I is the index in SPILL_REG_RTX of the reload register we are to |
5239 | allocate. Get an rtx for it and find its register number. */ | |
32131a9c | 5240 | |
f5d8c9f4 | 5241 | return set_reload_reg (i, r); |
32131a9c RK |
5242 | } |
5243 | \f | |
67e61fe7 BS |
5244 | /* Initialize all the tables needed to allocate reload registers. |
5245 | CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX | |
5246 | is the array we use to restore the reg_rtx field for every reload. */ | |
efc9bd41 | 5247 | |
32131a9c | 5248 | static void |
67e61fe7 | 5249 | choose_reload_regs_init (chain, save_reload_reg_rtx) |
7609e720 | 5250 | struct insn_chain *chain; |
67e61fe7 | 5251 | rtx *save_reload_reg_rtx; |
32131a9c | 5252 | { |
67e61fe7 | 5253 | int i; |
32131a9c | 5254 | |
67e61fe7 BS |
5255 | for (i = 0; i < n_reloads; i++) |
5256 | rld[i].reg_rtx = save_reload_reg_rtx[i]; | |
32131a9c | 5257 | |
961192e1 JM |
5258 | memset (reload_inherited, 0, MAX_RELOADS); |
5259 | memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx)); | |
5260 | memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx)); | |
32131a9c RK |
5261 | |
5262 | CLEAR_HARD_REG_SET (reload_reg_used); | |
5263 | CLEAR_HARD_REG_SET (reload_reg_used_at_all); | |
32131a9c | 5264 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); |
893bc853 | 5265 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); |
546b63fb RK |
5266 | CLEAR_HARD_REG_SET (reload_reg_used_in_insn); |
5267 | CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); | |
32131a9c | 5268 | |
f1db3576 JL |
5269 | CLEAR_HARD_REG_SET (reg_used_in_insn); |
5270 | { | |
5271 | HARD_REG_SET tmp; | |
239a0f5b | 5272 | REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); |
f1db3576 | 5273 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b | 5274 | REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); |
f1db3576 | 5275 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b BS |
5276 | compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); |
5277 | compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); | |
f1db3576 | 5278 | } |
efc9bd41 | 5279 | |
546b63fb RK |
5280 | for (i = 0; i < reload_n_operands; i++) |
5281 | { | |
5282 | CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); | |
5283 | CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); | |
5284 | CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); | |
47c8cf91 | 5285 | CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); |
546b63fb | 5286 | CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); |
47c8cf91 | 5287 | CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); |
546b63fb | 5288 | } |
32131a9c | 5289 | |
9e3a9cf2 | 5290 | COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs); |
05d10675 | 5291 | |
67e61fe7 | 5292 | CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); |
32131a9c | 5293 | |
67e61fe7 BS |
5294 | for (i = 0; i < n_reloads; i++) |
5295 | /* If we have already decided to use a certain register, | |
5296 | don't use it in another way. */ | |
5297 | if (rld[i].reg_rtx) | |
5298 | mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, | |
5299 | rld[i].when_needed, rld[i].mode); | |
5300 | } | |
32131a9c | 5301 | |
67e61fe7 BS |
5302 | /* Assign hard reg targets for the pseudo-registers we must reload |
5303 | into hard regs for this insn. | |
5304 | Also output the instructions to copy them in and out of the hard regs. | |
5305 | ||
5306 | For machines with register classes, we are responsible for | |
5307 | finding a reload reg in the proper class. */ | |
5308 | ||
5309 | static void | |
5310 | choose_reload_regs (chain) | |
5311 | struct insn_chain *chain; | |
5312 | { | |
5313 | rtx insn = chain->insn; | |
b3694847 | 5314 | int i, j; |
770ae6cc | 5315 | unsigned int max_group_size = 1; |
67e61fe7 | 5316 | enum reg_class group_class = NO_REGS; |
f5d8c9f4 | 5317 | int pass, win, inheritance; |
67e61fe7 BS |
5318 | |
5319 | rtx save_reload_reg_rtx[MAX_RELOADS]; | |
32131a9c | 5320 | |
32131a9c RK |
5321 | /* In order to be certain of getting the registers we need, |
5322 | we must sort the reloads into order of increasing register class. | |
5323 | Then our grabbing of reload registers will parallel the process | |
a8fdc208 | 5324 | that provided the reload registers. |
32131a9c RK |
5325 | |
5326 | Also note whether any of the reloads wants a consecutive group of regs. | |
5327 | If so, record the maximum size of the group desired and what | |
5328 | register class contains all the groups needed by this insn. */ | |
5329 | ||
5330 | for (j = 0; j < n_reloads; j++) | |
5331 | { | |
5332 | reload_order[j] = j; | |
5333 | reload_spill_index[j] = -1; | |
5334 | ||
8ec450a4 | 5335 | if (rld[j].nregs > 1) |
32131a9c | 5336 | { |
8ec450a4 | 5337 | max_group_size = MAX (rld[j].nregs, max_group_size); |
770ae6cc | 5338 | group_class |
8e2e89f7 | 5339 | = reg_class_superunion[(int) rld[j].class][(int) group_class]; |
32131a9c RK |
5340 | } |
5341 | ||
eceef4c9 | 5342 | save_reload_reg_rtx[j] = rld[j].reg_rtx; |
32131a9c RK |
5343 | } |
5344 | ||
5345 | if (n_reloads > 1) | |
5346 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
5347 | ||
58b1581b RS |
5348 | /* If -O, try first with inheritance, then turning it off. |
5349 | If not -O, don't do inheritance. | |
5350 | Using inheritance when not optimizing leads to paradoxes | |
5351 | with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves | |
5352 | because one side of the comparison might be inherited. */ | |
f5d8c9f4 | 5353 | win = 0; |
58b1581b | 5354 | for (inheritance = optimize > 0; inheritance >= 0; inheritance--) |
32131a9c | 5355 | { |
67e61fe7 BS |
5356 | choose_reload_regs_init (chain, save_reload_reg_rtx); |
5357 | ||
32131a9c RK |
5358 | /* Process the reloads in order of preference just found. |
5359 | Beyond this point, subregs can be found in reload_reg_rtx. | |
5360 | ||
770ae6cc RK |
5361 | This used to look for an existing reloaded home for all of the |
5362 | reloads, and only then perform any new reloads. But that could lose | |
5363 | if the reloads were done out of reg-class order because a later | |
5364 | reload with a looser constraint might have an old home in a register | |
5365 | needed by an earlier reload with a tighter constraint. | |
32131a9c RK |
5366 | |
5367 | To solve this, we make two passes over the reloads, in the order | |
5368 | described above. In the first pass we try to inherit a reload | |
5369 | from a previous insn. If there is a later reload that needs a | |
5370 | class that is a proper subset of the class being processed, we must | |
5371 | also allocate a spill register during the first pass. | |
5372 | ||
5373 | Then make a second pass over the reloads to allocate any reloads | |
5374 | that haven't been given registers yet. */ | |
5375 | ||
5376 | for (j = 0; j < n_reloads; j++) | |
5377 | { | |
b3694847 | 5378 | int r = reload_order[j]; |
8593b745 | 5379 | rtx search_equiv = NULL_RTX; |
32131a9c RK |
5380 | |
5381 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 BS |
5382 | if (rld[r].out == 0 && rld[r].in == 0 |
5383 | && ! rld[r].secondary_p) | |
32131a9c RK |
5384 | continue; |
5385 | ||
b29514ee | 5386 | /* If find_reloads chose to use reload_in or reload_out as a reload |
b080c137 RK |
5387 | register, we don't need to chose one. Otherwise, try even if it |
5388 | found one since we might save an insn if we find the value lying | |
b29514ee R |
5389 | around. |
5390 | Try also when reload_in is a pseudo without a hard reg. */ | |
eceef4c9 BS |
5391 | if (rld[r].in != 0 && rld[r].reg_rtx != 0 |
5392 | && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) | |
5393 | || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) | |
5394 | && GET_CODE (rld[r].in) != MEM | |
5395 | && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) | |
32131a9c RK |
5396 | continue; |
5397 | ||
5398 | #if 0 /* No longer needed for correct operation. | |
5399 | It might give better code, or might not; worth an experiment? */ | |
5400 | /* If this is an optional reload, we can't inherit from earlier insns | |
5401 | until we are sure that any non-optional reloads have been allocated. | |
5402 | The following code takes advantage of the fact that optional reloads | |
5403 | are at the end of reload_order. */ | |
eceef4c9 | 5404 | if (rld[r].optional != 0) |
32131a9c | 5405 | for (i = 0; i < j; i++) |
eceef4c9 BS |
5406 | if ((rld[reload_order[i]].out != 0 |
5407 | || rld[reload_order[i]].in != 0 | |
5408 | || rld[reload_order[i]].secondary_p) | |
5409 | && ! rld[reload_order[i]].optional | |
5410 | && rld[reload_order[i]].reg_rtx == 0) | |
f5d8c9f4 | 5411 | allocate_reload_reg (chain, reload_order[i], 0); |
32131a9c RK |
5412 | #endif |
5413 | ||
5414 | /* First see if this pseudo is already available as reloaded | |
5415 | for a previous insn. We cannot try to inherit for reloads | |
5416 | that are smaller than the maximum number of registers needed | |
5417 | for groups unless the register we would allocate cannot be used | |
5418 | for the groups. | |
5419 | ||
5420 | We could check here to see if this is a secondary reload for | |
5421 | an object that is already in a register of the desired class. | |
5422 | This would avoid the need for the secondary reload register. | |
5423 | But this is complex because we can't easily determine what | |
b080c137 RK |
5424 | objects might want to be loaded via this reload. So let a |
5425 | register be allocated here. In `emit_reload_insns' we suppress | |
5426 | one of the loads in the case described above. */ | |
32131a9c RK |
5427 | |
5428 | if (inheritance) | |
5429 | { | |
ddef6bc7 | 5430 | int byte = 0; |
b3694847 | 5431 | int regno = -1; |
6a651371 | 5432 | enum machine_mode mode = VOIDmode; |
32131a9c | 5433 | |
eceef4c9 | 5434 | if (rld[r].in == 0) |
32131a9c | 5435 | ; |
eceef4c9 | 5436 | else if (GET_CODE (rld[r].in) == REG) |
db660765 | 5437 | { |
eceef4c9 BS |
5438 | regno = REGNO (rld[r].in); |
5439 | mode = GET_MODE (rld[r].in); | |
db660765 | 5440 | } |
eceef4c9 | 5441 | else if (GET_CODE (rld[r].in_reg) == REG) |
db660765 | 5442 | { |
eceef4c9 BS |
5443 | regno = REGNO (rld[r].in_reg); |
5444 | mode = GET_MODE (rld[r].in_reg); | |
db660765 | 5445 | } |
eceef4c9 BS |
5446 | else if (GET_CODE (rld[r].in_reg) == SUBREG |
5447 | && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG) | |
b60a8416 | 5448 | { |
ddef6bc7 | 5449 | byte = SUBREG_BYTE (rld[r].in_reg); |
eceef4c9 | 5450 | regno = REGNO (SUBREG_REG (rld[r].in_reg)); |
cb2afeb3 | 5451 | if (regno < FIRST_PSEUDO_REGISTER) |
ddef6bc7 | 5452 | regno = subreg_regno (rld[r].in_reg); |
eceef4c9 | 5453 | mode = GET_MODE (rld[r].in_reg); |
cb2afeb3 R |
5454 | } |
5455 | #ifdef AUTO_INC_DEC | |
eceef4c9 BS |
5456 | else if ((GET_CODE (rld[r].in_reg) == PRE_INC |
5457 | || GET_CODE (rld[r].in_reg) == PRE_DEC | |
5458 | || GET_CODE (rld[r].in_reg) == POST_INC | |
5459 | || GET_CODE (rld[r].in_reg) == POST_DEC) | |
5460 | && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG) | |
cb2afeb3 | 5461 | { |
eceef4c9 BS |
5462 | regno = REGNO (XEXP (rld[r].in_reg, 0)); |
5463 | mode = GET_MODE (XEXP (rld[r].in_reg, 0)); | |
5464 | rld[r].out = rld[r].in; | |
b60a8416 | 5465 | } |
cb2afeb3 | 5466 | #endif |
32131a9c RK |
5467 | #if 0 |
5468 | /* This won't work, since REGNO can be a pseudo reg number. | |
5469 | Also, it takes much more hair to keep track of all the things | |
5470 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
eceef4c9 BS |
5471 | else if (GET_CODE (rld[r].in) == SUBREG |
5472 | && GET_CODE (SUBREG_REG (rld[r].in)) == REG) | |
ddef6bc7 | 5473 | regno = subreg_regno (rld[r].in); |
32131a9c RK |
5474 | #endif |
5475 | ||
5476 | if (regno >= 0 && reg_last_reload_reg[regno] != 0) | |
5477 | { | |
eceef4c9 | 5478 | enum reg_class class = rld[r].class, last_class; |
cb2afeb3 | 5479 | rtx last_reg = reg_last_reload_reg[regno]; |
02188693 | 5480 | enum machine_mode need_mode; |
05d10675 | 5481 | |
ddef6bc7 JJ |
5482 | i = REGNO (last_reg); |
5483 | i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode); | |
cb2afeb3 | 5484 | last_class = REGNO_REG_CLASS (i); |
02188693 | 5485 | |
ddef6bc7 | 5486 | if (byte == 0) |
ce701d1b BS |
5487 | need_mode = mode; |
5488 | else | |
5489 | need_mode | |
ddef6bc7 | 5490 | = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte, |
ce701d1b | 5491 | GET_MODE_CLASS (mode)); |
02188693 | 5492 | |
c9d8a813 | 5493 | if ( |
02188693 | 5494 | #ifdef CLASS_CANNOT_CHANGE_MODE |
c9d8a813 | 5495 | (TEST_HARD_REG_BIT |
02188693 | 5496 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i) |
1d7254c5 | 5497 | ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg), |
02188693 | 5498 | need_mode) |
c9d8a813 | 5499 | : (GET_MODE_SIZE (GET_MODE (last_reg)) |
02188693 | 5500 | >= GET_MODE_SIZE (need_mode))) |
c9d8a813 RH |
5501 | #else |
5502 | (GET_MODE_SIZE (GET_MODE (last_reg)) | |
02188693 | 5503 | >= GET_MODE_SIZE (need_mode)) |
c9d8a813 | 5504 | #endif |
cb2afeb3 | 5505 | && reg_reloaded_contents[i] == regno |
e6e52be0 | 5506 | && TEST_HARD_REG_BIT (reg_reloaded_valid, i) |
8ec450a4 | 5507 | && HARD_REGNO_MODE_OK (i, rld[r].mode) |
cb2afeb3 R |
5508 | && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i) |
5509 | /* Even if we can't use this register as a reload | |
5510 | register, we might use it for reload_override_in, | |
5511 | if copying it to the desired class is cheap | |
5512 | enough. */ | |
e56b4594 | 5513 | || ((REGISTER_MOVE_COST (mode, last_class, class) |
cb2afeb3 R |
5514 | < MEMORY_MOVE_COST (mode, class, 1)) |
5515 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
5516 | && (SECONDARY_INPUT_RELOAD_CLASS (class, mode, | |
5517 | last_reg) | |
5518 | == NO_REGS) | |
5519 | #endif | |
5520 | #ifdef SECONDARY_MEMORY_NEEDED | |
5521 | && ! SECONDARY_MEMORY_NEEDED (last_class, class, | |
5522 | mode) | |
5523 | #endif | |
5524 | )) | |
5525 | ||
8ec450a4 | 5526 | && (rld[r].nregs == max_group_size |
32131a9c | 5527 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], |
e6e52be0 | 5528 | i)) |
c02cad8f BS |
5529 | && free_for_value_p (i, rld[r].mode, rld[r].opnum, |
5530 | rld[r].when_needed, rld[r].in, | |
5531 | const0_rtx, r, 1)) | |
32131a9c RK |
5532 | { |
5533 | /* If a group is needed, verify that all the subsequent | |
0f41302f | 5534 | registers still have their values intact. */ |
1d7254c5 | 5535 | int nr = HARD_REGNO_NREGS (i, rld[r].mode); |
32131a9c RK |
5536 | int k; |
5537 | ||
5538 | for (k = 1; k < nr; k++) | |
e6e52be0 R |
5539 | if (reg_reloaded_contents[i + k] != regno |
5540 | || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) | |
32131a9c RK |
5541 | break; |
5542 | ||
5543 | if (k == nr) | |
5544 | { | |
c74fa651 | 5545 | int i1; |
eb4d554e | 5546 | int bad_for_class; |
c74fa651 | 5547 | |
cb2afeb3 R |
5548 | last_reg = (GET_MODE (last_reg) == mode |
5549 | ? last_reg : gen_rtx_REG (mode, i)); | |
5550 | ||
eb4d554e GK |
5551 | bad_for_class = 0; |
5552 | for (k = 0; k < nr; k++) | |
5553 | bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], | |
5554 | i+k); | |
5555 | ||
c74fa651 RS |
5556 | /* We found a register that contains the |
5557 | value we need. If this register is the | |
5558 | same as an `earlyclobber' operand of the | |
5559 | current insn, just mark it as a place to | |
5560 | reload from since we can't use it as the | |
5561 | reload register itself. */ | |
5562 | ||
5563 | for (i1 = 0; i1 < n_earlyclobbers; i1++) | |
5564 | if (reg_overlap_mentioned_for_reload_p | |
5565 | (reg_last_reload_reg[regno], | |
5566 | reload_earlyclobbers[i1])) | |
5567 | break; | |
5568 | ||
8908158d | 5569 | if (i1 != n_earlyclobbers |
c02cad8f BS |
5570 | || ! (free_for_value_p (i, rld[r].mode, |
5571 | rld[r].opnum, | |
5572 | rld[r].when_needed, rld[r].in, | |
5573 | rld[r].out, r, 1)) | |
e6e52be0 | 5574 | /* Don't use it if we'd clobber a pseudo reg. */ |
f1db3576 | 5575 | || (TEST_HARD_REG_BIT (reg_used_in_insn, i) |
eceef4c9 | 5576 | && rld[r].out |
e6e52be0 | 5577 | && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) |
0c7f2259 | 5578 | /* Don't clobber the frame pointer. */ |
1d7254c5 | 5579 | || (i == HARD_FRAME_POINTER_REGNUM |
2f460a0a | 5580 | && frame_pointer_needed |
1d7254c5 | 5581 | && rld[r].out) |
8908158d RS |
5582 | /* Don't really use the inherited spill reg |
5583 | if we need it wider than we've got it. */ | |
8ec450a4 | 5584 | || (GET_MODE_SIZE (rld[r].mode) |
b29514ee | 5585 | > GET_MODE_SIZE (mode)) |
eb4d554e | 5586 | || bad_for_class |
cb2afeb3 | 5587 | |
b29514ee R |
5588 | /* If find_reloads chose reload_out as reload |
5589 | register, stay with it - that leaves the | |
5590 | inherited register for subsequent reloads. */ | |
eceef4c9 | 5591 | || (rld[r].out && rld[r].reg_rtx |
67e61fe7 | 5592 | && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) |
cb2afeb3 | 5593 | { |
4c3a2649 BS |
5594 | if (! rld[r].optional) |
5595 | { | |
5596 | reload_override_in[r] = last_reg; | |
5597 | reload_inheritance_insn[r] | |
5598 | = reg_reloaded_insn[i]; | |
5599 | } | |
cb2afeb3 | 5600 | } |
c74fa651 RS |
5601 | else |
5602 | { | |
54c40e68 | 5603 | int k; |
c74fa651 RS |
5604 | /* We can use this as a reload reg. */ |
5605 | /* Mark the register as in use for this part of | |
5606 | the insn. */ | |
e6e52be0 | 5607 | mark_reload_reg_in_use (i, |
eceef4c9 BS |
5608 | rld[r].opnum, |
5609 | rld[r].when_needed, | |
8ec450a4 | 5610 | rld[r].mode); |
eceef4c9 | 5611 | rld[r].reg_rtx = last_reg; |
c74fa651 RS |
5612 | reload_inherited[r] = 1; |
5613 | reload_inheritance_insn[r] | |
5614 | = reg_reloaded_insn[i]; | |
5615 | reload_spill_index[r] = i; | |
54c40e68 RS |
5616 | for (k = 0; k < nr; k++) |
5617 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, | |
e6e52be0 | 5618 | i + k); |
c74fa651 | 5619 | } |
32131a9c RK |
5620 | } |
5621 | } | |
5622 | } | |
5623 | } | |
5624 | ||
5625 | /* Here's another way to see if the value is already lying around. */ | |
5626 | if (inheritance | |
eceef4c9 | 5627 | && rld[r].in != 0 |
32131a9c | 5628 | && ! reload_inherited[r] |
eceef4c9 BS |
5629 | && rld[r].out == 0 |
5630 | && (CONSTANT_P (rld[r].in) | |
5631 | || GET_CODE (rld[r].in) == PLUS | |
5632 | || GET_CODE (rld[r].in) == REG | |
5633 | || GET_CODE (rld[r].in) == MEM) | |
8ec450a4 | 5634 | && (rld[r].nregs == max_group_size |
eceef4c9 BS |
5635 | || ! reg_classes_intersect_p (rld[r].class, group_class))) |
5636 | search_equiv = rld[r].in; | |
8593b745 R |
5637 | /* If this is an output reload from a simple move insn, look |
5638 | if an equivalence for the input is available. */ | |
eceef4c9 | 5639 | else if (inheritance && rld[r].in == 0 && rld[r].out != 0) |
8593b745 R |
5640 | { |
5641 | rtx set = single_set (insn); | |
5642 | ||
5643 | if (set | |
eceef4c9 | 5644 | && rtx_equal_p (rld[r].out, SET_DEST (set)) |
8593b745 R |
5645 | && CONSTANT_P (SET_SRC (set))) |
5646 | search_equiv = SET_SRC (set); | |
5647 | } | |
5648 | ||
5649 | if (search_equiv) | |
32131a9c | 5650 | { |
b3694847 | 5651 | rtx equiv |
eceef4c9 | 5652 | = find_equiv_reg (search_equiv, insn, rld[r].class, |
9714cf43 | 5653 | -1, NULL, 0, rld[r].mode); |
f428f252 | 5654 | int regno = 0; |
32131a9c RK |
5655 | |
5656 | if (equiv != 0) | |
5657 | { | |
5658 | if (GET_CODE (equiv) == REG) | |
5659 | regno = REGNO (equiv); | |
5660 | else if (GET_CODE (equiv) == SUBREG) | |
5661 | { | |
f8a9e02b RK |
5662 | /* This must be a SUBREG of a hard register. |
5663 | Make a new REG since this might be used in an | |
5664 | address and not all machines support SUBREGs | |
5665 | there. */ | |
ddef6bc7 | 5666 | regno = subreg_regno (equiv); |
8ec450a4 | 5667 | equiv = gen_rtx_REG (rld[r].mode, regno); |
32131a9c RK |
5668 | } |
5669 | else | |
5670 | abort (); | |
5671 | } | |
5672 | ||
5673 | /* If we found a spill reg, reject it unless it is free | |
5674 | and of the desired class. */ | |
5675 | if (equiv != 0 | |
cb2afeb3 | 5676 | && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno) |
c02cad8f BS |
5677 | && ! free_for_value_p (regno, rld[r].mode, |
5678 | rld[r].opnum, rld[r].when_needed, | |
5679 | rld[r].in, rld[r].out, r, 1)) | |
eceef4c9 | 5680 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], |
32131a9c RK |
5681 | regno))) |
5682 | equiv = 0; | |
5683 | ||
8ec450a4 | 5684 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) |
32131a9c RK |
5685 | equiv = 0; |
5686 | ||
5687 | /* We found a register that contains the value we need. | |
5688 | If this register is the same as an `earlyclobber' operand | |
5689 | of the current insn, just mark it as a place to reload from | |
5690 | since we can't use it as the reload register itself. */ | |
5691 | ||
5692 | if (equiv != 0) | |
5693 | for (i = 0; i < n_earlyclobbers; i++) | |
bfa30b22 RK |
5694 | if (reg_overlap_mentioned_for_reload_p (equiv, |
5695 | reload_earlyclobbers[i])) | |
32131a9c | 5696 | { |
4c3a2649 BS |
5697 | if (! rld[r].optional) |
5698 | reload_override_in[r] = equiv; | |
32131a9c RK |
5699 | equiv = 0; |
5700 | break; | |
5701 | } | |
5702 | ||
3c785e47 R |
5703 | /* If the equiv register we have found is explicitly clobbered |
5704 | in the current insn, it depends on the reload type if we | |
5705 | can use it, use it for reload_override_in, or not at all. | |
5706 | In particular, we then can't use EQUIV for a | |
5707 | RELOAD_FOR_OUTPUT_ADDRESS reload. */ | |
32131a9c | 5708 | |
9532e31f | 5709 | if (equiv != 0) |
174fa2c4 | 5710 | { |
9532e31f BS |
5711 | if (regno_clobbered_p (regno, insn, rld[r].mode, 0)) |
5712 | switch (rld[r].when_needed) | |
5713 | { | |
5714 | case RELOAD_FOR_OTHER_ADDRESS: | |
5715 | case RELOAD_FOR_INPADDR_ADDRESS: | |
5716 | case RELOAD_FOR_INPUT_ADDRESS: | |
5717 | case RELOAD_FOR_OPADDR_ADDR: | |
5718 | break; | |
5719 | case RELOAD_OTHER: | |
5720 | case RELOAD_FOR_INPUT: | |
5721 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5722 | if (! rld[r].optional) | |
5723 | reload_override_in[r] = equiv; | |
5724 | /* Fall through. */ | |
5725 | default: | |
5726 | equiv = 0; | |
5727 | break; | |
5728 | } | |
5729 | else if (regno_clobbered_p (regno, insn, rld[r].mode, 1)) | |
5730 | switch (rld[r].when_needed) | |
5731 | { | |
5732 | case RELOAD_FOR_OTHER_ADDRESS: | |
5733 | case RELOAD_FOR_INPADDR_ADDRESS: | |
5734 | case RELOAD_FOR_INPUT_ADDRESS: | |
5735 | case RELOAD_FOR_OPADDR_ADDR: | |
5736 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5737 | case RELOAD_FOR_INPUT: | |
5738 | break; | |
5739 | case RELOAD_OTHER: | |
5740 | if (! rld[r].optional) | |
5741 | reload_override_in[r] = equiv; | |
5742 | /* Fall through. */ | |
5743 | default: | |
5744 | equiv = 0; | |
5745 | break; | |
5746 | } | |
32131a9c RK |
5747 | } |
5748 | ||
5749 | /* If we found an equivalent reg, say no code need be generated | |
5750 | to load it, and use it as our reload reg. */ | |
a6a2274a KH |
5751 | if (equiv != 0 |
5752 | && (regno != HARD_FRAME_POINTER_REGNUM | |
2f460a0a | 5753 | || !frame_pointer_needed)) |
32131a9c | 5754 | { |
8ec450a4 | 5755 | int nr = HARD_REGNO_NREGS (regno, rld[r].mode); |
100338df | 5756 | int k; |
eceef4c9 | 5757 | rld[r].reg_rtx = equiv; |
32131a9c | 5758 | reload_inherited[r] = 1; |
100338df | 5759 | |
91d7e7ac R |
5760 | /* If reg_reloaded_valid is not set for this register, |
5761 | there might be a stale spill_reg_store lying around. | |
5762 | We must clear it, since otherwise emit_reload_insns | |
5763 | might delete the store. */ | |
5764 | if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) | |
5765 | spill_reg_store[regno] = NULL_RTX; | |
100338df JL |
5766 | /* If any of the hard registers in EQUIV are spill |
5767 | registers, mark them as in use for this insn. */ | |
5768 | for (k = 0; k < nr; k++) | |
be7ae2a4 | 5769 | { |
100338df JL |
5770 | i = spill_reg_order[regno + k]; |
5771 | if (i >= 0) | |
5772 | { | |
eceef4c9 BS |
5773 | mark_reload_reg_in_use (regno, rld[r].opnum, |
5774 | rld[r].when_needed, | |
8ec450a4 | 5775 | rld[r].mode); |
100338df JL |
5776 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, |
5777 | regno + k); | |
5778 | } | |
be7ae2a4 | 5779 | } |
32131a9c RK |
5780 | } |
5781 | } | |
5782 | ||
5783 | /* If we found a register to use already, or if this is an optional | |
5784 | reload, we are done. */ | |
eceef4c9 | 5785 | if (rld[r].reg_rtx != 0 || rld[r].optional != 0) |
32131a9c RK |
5786 | continue; |
5787 | ||
1d7254c5 KH |
5788 | #if 0 |
5789 | /* No longer needed for correct operation. Might or might | |
5790 | not give better code on the average. Want to experiment? */ | |
32131a9c RK |
5791 | |
5792 | /* See if there is a later reload that has a class different from our | |
5793 | class that intersects our class or that requires less register | |
5794 | than our reload. If so, we must allocate a register to this | |
5795 | reload now, since that reload might inherit a previous reload | |
5796 | and take the only available register in our class. Don't do this | |
5797 | for optional reloads since they will force all previous reloads | |
5798 | to be allocated. Also don't do this for reloads that have been | |
5799 | turned off. */ | |
5800 | ||
5801 | for (i = j + 1; i < n_reloads; i++) | |
5802 | { | |
5803 | int s = reload_order[i]; | |
5804 | ||
eceef4c9 BS |
5805 | if ((rld[s].in == 0 && rld[s].out == 0 |
5806 | && ! rld[s].secondary_p) | |
5807 | || rld[s].optional) | |
32131a9c RK |
5808 | continue; |
5809 | ||
eceef4c9 BS |
5810 | if ((rld[s].class != rld[r].class |
5811 | && reg_classes_intersect_p (rld[r].class, | |
5812 | rld[s].class)) | |
8ec450a4 | 5813 | || rld[s].nregs < rld[r].nregs) |
05d10675 | 5814 | break; |
32131a9c RK |
5815 | } |
5816 | ||
5817 | if (i == n_reloads) | |
5818 | continue; | |
5819 | ||
f5d8c9f4 | 5820 | allocate_reload_reg (chain, r, j == n_reloads - 1); |
32131a9c RK |
5821 | #endif |
5822 | } | |
5823 | ||
5824 | /* Now allocate reload registers for anything non-optional that | |
5825 | didn't get one yet. */ | |
5826 | for (j = 0; j < n_reloads; j++) | |
5827 | { | |
b3694847 | 5828 | int r = reload_order[j]; |
32131a9c RK |
5829 | |
5830 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 | 5831 | if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) |
32131a9c RK |
5832 | continue; |
5833 | ||
5834 | /* Skip reloads that already have a register allocated or are | |
0f41302f | 5835 | optional. */ |
eceef4c9 | 5836 | if (rld[r].reg_rtx != 0 || rld[r].optional) |
32131a9c RK |
5837 | continue; |
5838 | ||
f5d8c9f4 | 5839 | if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) |
32131a9c RK |
5840 | break; |
5841 | } | |
5842 | ||
5843 | /* If that loop got all the way, we have won. */ | |
5844 | if (j == n_reloads) | |
f5d8c9f4 BS |
5845 | { |
5846 | win = 1; | |
5847 | break; | |
5848 | } | |
32131a9c | 5849 | |
32131a9c | 5850 | /* Loop around and try without any inheritance. */ |
32131a9c RK |
5851 | } |
5852 | ||
f5d8c9f4 BS |
5853 | if (! win) |
5854 | { | |
5855 | /* First undo everything done by the failed attempt | |
5856 | to allocate with inheritance. */ | |
5857 | choose_reload_regs_init (chain, save_reload_reg_rtx); | |
5858 | ||
5859 | /* Some sanity tests to verify that the reloads found in the first | |
5860 | pass are identical to the ones we have now. */ | |
5861 | if (chain->n_reloads != n_reloads) | |
5862 | abort (); | |
5863 | ||
5864 | for (i = 0; i < n_reloads; i++) | |
5865 | { | |
5866 | if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) | |
5867 | continue; | |
5868 | if (chain->rld[i].when_needed != rld[i].when_needed) | |
5869 | abort (); | |
5870 | for (j = 0; j < n_spills; j++) | |
5871 | if (spill_regs[j] == chain->rld[i].regno) | |
5872 | if (! set_reload_reg (j, i)) | |
5873 | failed_reload (chain->insn, i); | |
5874 | } | |
5875 | } | |
5876 | ||
32131a9c RK |
5877 | /* If we thought we could inherit a reload, because it seemed that |
5878 | nothing else wanted the same reload register earlier in the insn, | |
cb2afeb3 R |
5879 | verify that assumption, now that all reloads have been assigned. |
5880 | Likewise for reloads where reload_override_in has been set. */ | |
32131a9c | 5881 | |
cb2afeb3 R |
5882 | /* If doing expensive optimizations, do one preliminary pass that doesn't |
5883 | cancel any inheritance, but removes reloads that have been needed only | |
5884 | for reloads that we know can be inherited. */ | |
5885 | for (pass = flag_expensive_optimizations; pass >= 0; pass--) | |
32131a9c | 5886 | { |
cb2afeb3 | 5887 | for (j = 0; j < n_reloads; j++) |
029b38ff | 5888 | { |
b3694847 | 5889 | int r = reload_order[j]; |
cb2afeb3 | 5890 | rtx check_reg; |
eceef4c9 BS |
5891 | if (reload_inherited[r] && rld[r].reg_rtx) |
5892 | check_reg = rld[r].reg_rtx; | |
cb2afeb3 R |
5893 | else if (reload_override_in[r] |
5894 | && (GET_CODE (reload_override_in[r]) == REG | |
05d10675 | 5895 | || GET_CODE (reload_override_in[r]) == SUBREG)) |
cb2afeb3 R |
5896 | check_reg = reload_override_in[r]; |
5897 | else | |
5898 | continue; | |
c02cad8f BS |
5899 | if (! free_for_value_p (true_regnum (check_reg), rld[r].mode, |
5900 | rld[r].opnum, rld[r].when_needed, rld[r].in, | |
5901 | (reload_inherited[r] | |
5902 | ? rld[r].out : const0_rtx), | |
5903 | r, 1)) | |
029b38ff | 5904 | { |
cb2afeb3 R |
5905 | if (pass) |
5906 | continue; | |
5907 | reload_inherited[r] = 0; | |
5908 | reload_override_in[r] = 0; | |
029b38ff | 5909 | } |
cb2afeb3 R |
5910 | /* If we can inherit a RELOAD_FOR_INPUT, or can use a |
5911 | reload_override_in, then we do not need its related | |
5912 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; | |
5913 | likewise for other reload types. | |
5914 | We handle this by removing a reload when its only replacement | |
5915 | is mentioned in reload_in of the reload we are going to inherit. | |
5916 | A special case are auto_inc expressions; even if the input is | |
5917 | inherited, we still need the address for the output. We can | |
fe92fe26 | 5918 | recognize them because they have RELOAD_OUT set to RELOAD_IN. |
eaec9b3d | 5919 | If we succeeded removing some reload and we are doing a preliminary |
cb2afeb3 R |
5920 | pass just to remove such reloads, make another pass, since the |
5921 | removal of one reload might allow us to inherit another one. */ | |
eceef4c9 BS |
5922 | else if (rld[r].in |
5923 | && rld[r].out != rld[r].in | |
5924 | && remove_address_replacements (rld[r].in) && pass) | |
cb2afeb3 | 5925 | pass = 2; |
32131a9c RK |
5926 | } |
5927 | } | |
5928 | ||
5929 | /* Now that reload_override_in is known valid, | |
5930 | actually override reload_in. */ | |
5931 | for (j = 0; j < n_reloads; j++) | |
5932 | if (reload_override_in[j]) | |
eceef4c9 | 5933 | rld[j].in = reload_override_in[j]; |
32131a9c RK |
5934 | |
5935 | /* If this reload won't be done because it has been cancelled or is | |
5936 | optional and not inherited, clear reload_reg_rtx so other | |
5937 | routines (such as subst_reloads) don't get confused. */ | |
5938 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
5939 | if (rld[j].reg_rtx != 0 |
5940 | && ((rld[j].optional && ! reload_inherited[j]) | |
5941 | || (rld[j].in == 0 && rld[j].out == 0 | |
5942 | && ! rld[j].secondary_p))) | |
be7ae2a4 | 5943 | { |
eceef4c9 | 5944 | int regno = true_regnum (rld[j].reg_rtx); |
be7ae2a4 RK |
5945 | |
5946 | if (spill_reg_order[regno] >= 0) | |
eceef4c9 | 5947 | clear_reload_reg_in_use (regno, rld[j].opnum, |
8ec450a4 | 5948 | rld[j].when_needed, rld[j].mode); |
eceef4c9 | 5949 | rld[j].reg_rtx = 0; |
c0029be5 | 5950 | reload_spill_index[j] = -1; |
be7ae2a4 | 5951 | } |
32131a9c RK |
5952 | |
5953 | /* Record which pseudos and which spill regs have output reloads. */ | |
5954 | for (j = 0; j < n_reloads; j++) | |
5955 | { | |
b3694847 | 5956 | int r = reload_order[j]; |
32131a9c RK |
5957 | |
5958 | i = reload_spill_index[r]; | |
5959 | ||
e6e52be0 | 5960 | /* I is nonneg if this reload uses a register. |
eceef4c9 | 5961 | If rld[r].reg_rtx is 0, this is an optional reload |
32131a9c | 5962 | that we opted to ignore. */ |
eceef4c9 BS |
5963 | if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG |
5964 | && rld[r].reg_rtx != 0) | |
32131a9c | 5965 | { |
b3694847 | 5966 | int nregno = REGNO (rld[r].out_reg); |
372e033b RS |
5967 | int nr = 1; |
5968 | ||
5969 | if (nregno < FIRST_PSEUDO_REGISTER) | |
8ec450a4 | 5970 | nr = HARD_REGNO_NREGS (nregno, rld[r].mode); |
32131a9c RK |
5971 | |
5972 | while (--nr >= 0) | |
372e033b RS |
5973 | reg_has_output_reload[nregno + nr] = 1; |
5974 | ||
5975 | if (i >= 0) | |
32131a9c | 5976 | { |
8ec450a4 | 5977 | nr = HARD_REGNO_NREGS (i, rld[r].mode); |
372e033b | 5978 | while (--nr >= 0) |
e6e52be0 | 5979 | SET_HARD_REG_BIT (reg_is_output_reload, i + nr); |
32131a9c RK |
5980 | } |
5981 | ||
eceef4c9 BS |
5982 | if (rld[r].when_needed != RELOAD_OTHER |
5983 | && rld[r].when_needed != RELOAD_FOR_OUTPUT | |
5984 | && rld[r].when_needed != RELOAD_FOR_INSN) | |
32131a9c RK |
5985 | abort (); |
5986 | } | |
5987 | } | |
5988 | } | |
cb2afeb3 R |
5989 | |
5990 | /* Deallocate the reload register for reload R. This is called from | |
5991 | remove_address_replacements. */ | |
1d813780 | 5992 | |
cb2afeb3 R |
5993 | void |
5994 | deallocate_reload_reg (r) | |
5995 | int r; | |
5996 | { | |
5997 | int regno; | |
5998 | ||
eceef4c9 | 5999 | if (! rld[r].reg_rtx) |
cb2afeb3 | 6000 | return; |
eceef4c9 BS |
6001 | regno = true_regnum (rld[r].reg_rtx); |
6002 | rld[r].reg_rtx = 0; | |
cb2afeb3 | 6003 | if (spill_reg_order[regno] >= 0) |
eceef4c9 | 6004 | clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, |
8ec450a4 | 6005 | rld[r].mode); |
cb2afeb3 R |
6006 | reload_spill_index[r] = -1; |
6007 | } | |
32131a9c | 6008 | \f |
e9a25f70 | 6009 | /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two |
546b63fb RK |
6010 | reloads of the same item for fear that we might not have enough reload |
6011 | registers. However, normally they will get the same reload register | |
05d10675 | 6012 | and hence actually need not be loaded twice. |
546b63fb RK |
6013 | |
6014 | Here we check for the most common case of this phenomenon: when we have | |
6015 | a number of reloads for the same object, each of which were allocated | |
6016 | the same reload_reg_rtx, that reload_reg_rtx is not used for any other | |
6017 | reload, and is not modified in the insn itself. If we find such, | |
6018 | merge all the reloads and set the resulting reload to RELOAD_OTHER. | |
6019 | This will not increase the number of spill registers needed and will | |
6020 | prevent redundant code. */ | |
6021 | ||
546b63fb RK |
6022 | static void |
6023 | merge_assigned_reloads (insn) | |
6024 | rtx insn; | |
6025 | { | |
6026 | int i, j; | |
6027 | ||
6028 | /* Scan all the reloads looking for ones that only load values and | |
6029 | are not already RELOAD_OTHER and ones whose reload_reg_rtx are | |
6030 | assigned and not modified by INSN. */ | |
6031 | ||
6032 | for (i = 0; i < n_reloads; i++) | |
6033 | { | |
d668e863 R |
6034 | int conflicting_input = 0; |
6035 | int max_input_address_opnum = -1; | |
6036 | int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; | |
6037 | ||
eceef4c9 BS |
6038 | if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER |
6039 | || rld[i].out != 0 || rld[i].reg_rtx == 0 | |
6040 | || reg_set_p (rld[i].reg_rtx, insn)) | |
546b63fb RK |
6041 | continue; |
6042 | ||
6043 | /* Look at all other reloads. Ensure that the only use of this | |
6044 | reload_reg_rtx is in a reload that just loads the same value | |
6045 | as we do. Note that any secondary reloads must be of the identical | |
6046 | class since the values, modes, and result registers are the | |
6047 | same, so we need not do anything with any secondary reloads. */ | |
6048 | ||
6049 | for (j = 0; j < n_reloads; j++) | |
6050 | { | |
eceef4c9 BS |
6051 | if (i == j || rld[j].reg_rtx == 0 |
6052 | || ! reg_overlap_mentioned_p (rld[j].reg_rtx, | |
6053 | rld[i].reg_rtx)) | |
546b63fb RK |
6054 | continue; |
6055 | ||
eceef4c9 BS |
6056 | if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6057 | && rld[j].opnum > max_input_address_opnum) | |
6058 | max_input_address_opnum = rld[j].opnum; | |
d668e863 | 6059 | |
546b63fb | 6060 | /* If the reload regs aren't exactly the same (e.g, different modes) |
d668e863 R |
6061 | or if the values are different, we can't merge this reload. |
6062 | But if it is an input reload, we might still merge | |
6063 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ | |
546b63fb | 6064 | |
eceef4c9 BS |
6065 | if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) |
6066 | || rld[j].out != 0 || rld[j].in == 0 | |
6067 | || ! rtx_equal_p (rld[i].in, rld[j].in)) | |
d668e863 | 6068 | { |
eceef4c9 BS |
6069 | if (rld[j].when_needed != RELOAD_FOR_INPUT |
6070 | || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS | |
6071 | || rld[i].opnum > rld[j].opnum) | |
6072 | && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS)) | |
d668e863 R |
6073 | break; |
6074 | conflicting_input = 1; | |
eceef4c9 BS |
6075 | if (min_conflicting_input_opnum > rld[j].opnum) |
6076 | min_conflicting_input_opnum = rld[j].opnum; | |
d668e863 | 6077 | } |
546b63fb RK |
6078 | } |
6079 | ||
6080 | /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if | |
6081 | we, in fact, found any matching reloads. */ | |
6082 | ||
d668e863 R |
6083 | if (j == n_reloads |
6084 | && max_input_address_opnum <= min_conflicting_input_opnum) | |
546b63fb RK |
6085 | { |
6086 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
6087 | if (i != j && rld[j].reg_rtx != 0 |
6088 | && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) | |
d668e863 | 6089 | && (! conflicting_input |
eceef4c9 BS |
6090 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6091 | || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
546b63fb | 6092 | { |
eceef4c9 BS |
6093 | rld[i].when_needed = RELOAD_OTHER; |
6094 | rld[j].in = 0; | |
efdb3590 | 6095 | reload_spill_index[j] = -1; |
546b63fb RK |
6096 | transfer_replacements (i, j); |
6097 | } | |
6098 | ||
6099 | /* If this is now RELOAD_OTHER, look for any reloads that load | |
6100 | parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS | |
6101 | if they were for inputs, RELOAD_OTHER for outputs. Note that | |
6102 | this test is equivalent to looking for reloads for this operand | |
6103 | number. */ | |
dec0798e R |
6104 | /* We must take special care when there are two or more reloads to |
6105 | be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the | |
6106 | same value or a part of it; we must not change its type if there | |
6107 | is a conflicting input. */ | |
546b63fb | 6108 | |
eceef4c9 | 6109 | if (rld[i].when_needed == RELOAD_OTHER) |
546b63fb | 6110 | for (j = 0; j < n_reloads; j++) |
eceef4c9 | 6111 | if (rld[j].in != 0 |
91667711 | 6112 | && rld[j].when_needed != RELOAD_OTHER |
dec0798e R |
6113 | && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS |
6114 | && (! conflicting_input | |
6115 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
6116 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
eceef4c9 BS |
6117 | && reg_overlap_mentioned_for_reload_p (rld[j].in, |
6118 | rld[i].in)) | |
6119 | rld[j].when_needed | |
91667711 SC |
6120 | = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6121 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
47c8cf91 | 6122 | ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); |
546b63fb RK |
6123 | } |
6124 | } | |
05d10675 | 6125 | } |
546b63fb | 6126 | \f |
367b1cf5 BS |
6127 | /* These arrays are filled by emit_reload_insns and its subroutines. */ |
6128 | static rtx input_reload_insns[MAX_RECOG_OPERANDS]; | |
6129 | static rtx other_input_address_reload_insns = 0; | |
6130 | static rtx other_input_reload_insns = 0; | |
6131 | static rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6132 | static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6133 | static rtx output_reload_insns[MAX_RECOG_OPERANDS]; | |
6134 | static rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6135 | static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6136 | static rtx operand_reload_insns = 0; | |
6137 | static rtx other_operand_reload_insns = 0; | |
6138 | static rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; | |
6139 | ||
6140 | /* Values to be put in spill_reg_store are put here first. */ | |
6141 | static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
6142 | static HARD_REG_SET reg_reloaded_died; | |
6143 | ||
6144 | /* Generate insns to perform reload RL, which is for the insn in CHAIN and | |
6145 | has the number J. OLD contains the value to be used as input. */ | |
770ae6cc | 6146 | |
32131a9c | 6147 | static void |
367b1cf5 | 6148 | emit_input_reload_insns (chain, rl, old, j) |
7609e720 | 6149 | struct insn_chain *chain; |
367b1cf5 BS |
6150 | struct reload *rl; |
6151 | rtx old; | |
6152 | int j; | |
32131a9c | 6153 | { |
7609e720 | 6154 | rtx insn = chain->insn; |
b3694847 | 6155 | rtx reloadreg = rl->reg_rtx; |
367b1cf5 BS |
6156 | rtx oldequiv_reg = 0; |
6157 | rtx oldequiv = 0; | |
6158 | int special = 0; | |
6159 | enum machine_mode mode; | |
6160 | rtx *where; | |
6161 | ||
6162 | /* Determine the mode to reload in. | |
6163 | This is very tricky because we have three to choose from. | |
6164 | There is the mode the insn operand wants (rl->inmode). | |
6165 | There is the mode of the reload register RELOADREG. | |
6166 | There is the intrinsic mode of the operand, which we could find | |
6167 | by stripping some SUBREGs. | |
6168 | It turns out that RELOADREG's mode is irrelevant: | |
6169 | we can change that arbitrarily. | |
6170 | ||
6171 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
6172 | then the reload reg may not support QImode moves, so use SImode. | |
6173 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
6174 | because the QImode value is in the least significant part of a | |
6175 | slot big enough for a SImode. If foo is some other sort of | |
6176 | memory reference, then it is impossible to reload this case, | |
6177 | so previous passes had better make sure this never happens. | |
6178 | ||
6179 | Then consider a one-word union which has SImode and one of its | |
6180 | members is a float, being fetched as (SUBREG:SF union:SI). | |
6181 | We must fetch that as SFmode because we could be loading into | |
6182 | a float-only register. In this case OLD's mode is correct. | |
6183 | ||
6184 | Consider an immediate integer: it has VOIDmode. Here we need | |
6185 | to get a mode from something else. | |
6186 | ||
6187 | In some cases, there is a fourth mode, the operand's | |
6188 | containing mode. If the insn specifies a containing mode for | |
6189 | this operand, it overrides all others. | |
6190 | ||
6191 | I am not sure whether the algorithm here is always right, | |
6192 | but it does the right things in those cases. */ | |
6193 | ||
6194 | mode = GET_MODE (old); | |
6195 | if (mode == VOIDmode) | |
6196 | mode = rl->inmode; | |
7609e720 | 6197 | |
367b1cf5 BS |
6198 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
6199 | /* If we need a secondary register for this operation, see if | |
6200 | the value is already in a register in that class. Don't | |
6201 | do this if the secondary register will be used as a scratch | |
6202 | register. */ | |
6203 | ||
6204 | if (rl->secondary_in_reload >= 0 | |
6205 | && rl->secondary_in_icode == CODE_FOR_nothing | |
6206 | && optimize) | |
6207 | oldequiv | |
6208 | = find_equiv_reg (old, insn, | |
6209 | rld[rl->secondary_in_reload].class, | |
9714cf43 | 6210 | -1, NULL, 0, mode); |
367b1cf5 | 6211 | #endif |
e6e52be0 | 6212 | |
367b1cf5 BS |
6213 | /* If reloading from memory, see if there is a register |
6214 | that already holds the same value. If so, reload from there. | |
6215 | We can pass 0 as the reload_reg_p argument because | |
6216 | any other reload has either already been emitted, | |
6217 | in which case find_equiv_reg will see the reload-insn, | |
6218 | or has yet to be emitted, in which case it doesn't matter | |
6219 | because we will use this equiv reg right away. */ | |
6220 | ||
6221 | if (oldequiv == 0 && optimize | |
6222 | && (GET_CODE (old) == MEM | |
6223 | || (GET_CODE (old) == REG | |
6224 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
6225 | && reg_renumber[REGNO (old)] < 0))) | |
9714cf43 | 6226 | oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode); |
367b1cf5 BS |
6227 | |
6228 | if (oldequiv) | |
6229 | { | |
770ae6cc | 6230 | unsigned int regno = true_regnum (oldequiv); |
367b1cf5 BS |
6231 | |
6232 | /* Don't use OLDEQUIV if any other reload changes it at an | |
6233 | earlier stage of this insn or at this stage. */ | |
c02cad8f BS |
6234 | if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed, |
6235 | rl->in, const0_rtx, j, 0)) | |
367b1cf5 BS |
6236 | oldequiv = 0; |
6237 | ||
6238 | /* If it is no cheaper to copy from OLDEQUIV into the | |
6239 | reload register than it would be to move from memory, | |
6240 | don't use it. Likewise, if we need a secondary register | |
6d2f8887 | 6241 | or memory. */ |
367b1cf5 BS |
6242 | |
6243 | if (oldequiv != 0 | |
6244 | && ((REGNO_REG_CLASS (regno) != rl->class | |
e56b4594 | 6245 | && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno), |
367b1cf5 BS |
6246 | rl->class) |
6247 | >= MEMORY_MOVE_COST (mode, rl->class, 1))) | |
6248 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
6249 | || (SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
6250 | mode, oldequiv) | |
6251 | != NO_REGS) | |
6252 | #endif | |
6253 | #ifdef SECONDARY_MEMORY_NEEDED | |
6254 | || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno), | |
6255 | rl->class, | |
6256 | mode) | |
6257 | #endif | |
6258 | )) | |
6259 | oldequiv = 0; | |
6260 | } | |
32131a9c | 6261 | |
367b1cf5 BS |
6262 | /* delete_output_reload is only invoked properly if old contains |
6263 | the original pseudo register. Since this is replaced with a | |
6264 | hard reg when RELOAD_OVERRIDE_IN is set, see if we can | |
6265 | find the pseudo in RELOAD_IN_REG. */ | |
6266 | if (oldequiv == 0 | |
6267 | && reload_override_in[j] | |
6268 | && GET_CODE (rl->in_reg) == REG) | |
6269 | { | |
6270 | oldequiv = old; | |
6271 | old = rl->in_reg; | |
6272 | } | |
6273 | if (oldequiv == 0) | |
6274 | oldequiv = old; | |
6275 | else if (GET_CODE (oldequiv) == REG) | |
6276 | oldequiv_reg = oldequiv; | |
6277 | else if (GET_CODE (oldequiv) == SUBREG) | |
6278 | oldequiv_reg = SUBREG_REG (oldequiv); | |
6279 | ||
6280 | /* If we are reloading from a register that was recently stored in | |
6281 | with an output-reload, see if we can prove there was | |
6282 | actually no need to store the old value in it. */ | |
6283 | ||
6284 | if (optimize && GET_CODE (oldequiv) == REG | |
6285 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6286 | && spill_reg_store[REGNO (oldequiv)] | |
6287 | && GET_CODE (old) == REG | |
6288 | && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) | |
6289 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6290 | rl->out_reg))) | |
6291 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6292 | ||
6293 | /* Encapsulate both RELOADREG and OLDEQUIV into that mode, | |
6294 | then load RELOADREG from OLDEQUIV. Note that we cannot use | |
6295 | gen_lowpart_common since it can do the wrong thing when | |
6296 | RELOADREG has a multi-word mode. Note that RELOADREG | |
6297 | must always be a REG here. */ | |
6298 | ||
6299 | if (GET_MODE (reloadreg) != mode) | |
6300 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
6301 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) | |
6302 | oldequiv = SUBREG_REG (oldequiv); | |
6303 | if (GET_MODE (oldequiv) != VOIDmode | |
6304 | && mode != GET_MODE (oldequiv)) | |
ddef6bc7 | 6305 | oldequiv = gen_lowpart_SUBREG (mode, oldequiv); |
367b1cf5 BS |
6306 | |
6307 | /* Switch to the right place to emit the reload insns. */ | |
6308 | switch (rl->when_needed) | |
6309 | { | |
6310 | case RELOAD_OTHER: | |
6311 | where = &other_input_reload_insns; | |
6312 | break; | |
6313 | case RELOAD_FOR_INPUT: | |
6314 | where = &input_reload_insns[rl->opnum]; | |
6315 | break; | |
6316 | case RELOAD_FOR_INPUT_ADDRESS: | |
6317 | where = &input_address_reload_insns[rl->opnum]; | |
6318 | break; | |
6319 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6320 | where = &inpaddr_address_reload_insns[rl->opnum]; | |
6321 | break; | |
6322 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
6323 | where = &output_address_reload_insns[rl->opnum]; | |
6324 | break; | |
6325 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
6326 | where = &outaddr_address_reload_insns[rl->opnum]; | |
6327 | break; | |
6328 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6329 | where = &operand_reload_insns; | |
6330 | break; | |
6331 | case RELOAD_FOR_OPADDR_ADDR: | |
6332 | where = &other_operand_reload_insns; | |
6333 | break; | |
6334 | case RELOAD_FOR_OTHER_ADDRESS: | |
6335 | where = &other_input_address_reload_insns; | |
6336 | break; | |
6337 | default: | |
6338 | abort (); | |
6339 | } | |
546b63fb | 6340 | |
367b1cf5 | 6341 | push_to_sequence (*where); |
32131a9c | 6342 | |
367b1cf5 BS |
6343 | /* Auto-increment addresses must be reloaded in a special way. */ |
6344 | if (rl->out && ! rl->out_reg) | |
32131a9c | 6345 | { |
367b1cf5 BS |
6346 | /* We are not going to bother supporting the case where a |
6347 | incremented register can't be copied directly from | |
6348 | OLDEQUIV since this seems highly unlikely. */ | |
6349 | if (rl->secondary_in_reload >= 0) | |
6350 | abort (); | |
32131a9c | 6351 | |
367b1cf5 BS |
6352 | if (reload_inherited[j]) |
6353 | oldequiv = reloadreg; | |
cb2afeb3 | 6354 | |
367b1cf5 | 6355 | old = XEXP (rl->in_reg, 0); |
32131a9c | 6356 | |
367b1cf5 BS |
6357 | if (optimize && GET_CODE (oldequiv) == REG |
6358 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6359 | && spill_reg_store[REGNO (oldequiv)] | |
6360 | && GET_CODE (old) == REG | |
6361 | && (dead_or_set_p (insn, | |
6362 | spill_reg_stored_to[REGNO (oldequiv)]) | |
6363 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6364 | old))) | |
6365 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6366 | ||
6367 | /* Prevent normal processing of this reload. */ | |
6368 | special = 1; | |
6369 | /* Output a special code sequence for this case. */ | |
6370 | new_spill_reg_store[REGNO (reloadreg)] | |
6371 | = inc_for_reload (reloadreg, oldequiv, rl->out, | |
6372 | rl->inc); | |
6373 | } | |
32131a9c | 6374 | |
367b1cf5 BS |
6375 | /* If we are reloading a pseudo-register that was set by the previous |
6376 | insn, see if we can get rid of that pseudo-register entirely | |
6377 | by redirecting the previous insn into our reload register. */ | |
6378 | ||
6379 | else if (optimize && GET_CODE (old) == REG | |
6380 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
6381 | && dead_or_set_p (insn, old) | |
6382 | /* This is unsafe if some other reload | |
6383 | uses the same reg first. */ | |
ff6534ad | 6384 | && ! conflicts_with_override (reloadreg) |
c02cad8f BS |
6385 | && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum, |
6386 | rl->when_needed, old, rl->out, j, 0)) | |
367b1cf5 BS |
6387 | { |
6388 | rtx temp = PREV_INSN (insn); | |
6389 | while (temp && GET_CODE (temp) == NOTE) | |
6390 | temp = PREV_INSN (temp); | |
6391 | if (temp | |
6392 | && GET_CODE (temp) == INSN | |
6393 | && GET_CODE (PATTERN (temp)) == SET | |
6394 | && SET_DEST (PATTERN (temp)) == old | |
6395 | /* Make sure we can access insn_operand_constraint. */ | |
6396 | && asm_noperands (PATTERN (temp)) < 0 | |
367b1cf5 BS |
6397 | /* This is unsafe if operand occurs more than once in current |
6398 | insn. Perhaps some occurrences aren't reloaded. */ | |
10d1bb36 | 6399 | && count_occurrences (PATTERN (insn), old, 0) == 1) |
367b1cf5 | 6400 | { |
10d1bb36 | 6401 | rtx old = SET_DEST (PATTERN (temp)); |
367b1cf5 BS |
6402 | /* Store into the reload register instead of the pseudo. */ |
6403 | SET_DEST (PATTERN (temp)) = reloadreg; | |
6404 | ||
10d1bb36 JH |
6405 | /* Verify that resulting insn is valid. */ |
6406 | extract_insn (temp); | |
6407 | if (constrain_operands (1)) | |
32131a9c | 6408 | { |
10d1bb36 JH |
6409 | /* If the previous insn is an output reload, the source is |
6410 | a reload register, and its spill_reg_store entry will | |
6411 | contain the previous destination. This is now | |
6412 | invalid. */ | |
6413 | if (GET_CODE (SET_SRC (PATTERN (temp))) == REG | |
6414 | && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) | |
6415 | { | |
6416 | spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
6417 | spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
6418 | } | |
32131a9c | 6419 | |
10d1bb36 JH |
6420 | /* If these are the only uses of the pseudo reg, |
6421 | pretend for GDB it lives in the reload reg we used. */ | |
6422 | if (REG_N_DEATHS (REGNO (old)) == 1 | |
6423 | && REG_N_SETS (REGNO (old)) == 1) | |
6424 | { | |
6425 | reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx); | |
6426 | alter_reg (REGNO (old), -1); | |
6427 | } | |
6428 | special = 1; | |
6429 | } | |
6430 | else | |
cb2afeb3 | 6431 | { |
10d1bb36 | 6432 | SET_DEST (PATTERN (temp)) = old; |
32131a9c | 6433 | } |
367b1cf5 BS |
6434 | } |
6435 | } | |
32131a9c | 6436 | |
367b1cf5 | 6437 | /* We can't do that, so output an insn to load RELOADREG. */ |
32131a9c | 6438 | |
367b1cf5 BS |
6439 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
6440 | /* If we have a secondary reload, pick up the secondary register | |
6441 | and icode, if any. If OLDEQUIV and OLD are different or | |
6442 | if this is an in-out reload, recompute whether or not we | |
6443 | still need a secondary register and what the icode should | |
6444 | be. If we still need a secondary register and the class or | |
6445 | icode is different, go back to reloading from OLD if using | |
6446 | OLDEQUIV means that we got the wrong type of register. We | |
6447 | cannot have different class or icode due to an in-out reload | |
6448 | because we don't make such reloads when both the input and | |
6449 | output need secondary reload registers. */ | |
6450 | ||
07875628 | 6451 | if (! special && rl->secondary_in_reload >= 0) |
367b1cf5 BS |
6452 | { |
6453 | rtx second_reload_reg = 0; | |
6454 | int secondary_reload = rl->secondary_in_reload; | |
6455 | rtx real_oldequiv = oldequiv; | |
6456 | rtx real_old = old; | |
6457 | rtx tmp; | |
6458 | enum insn_code icode; | |
6459 | ||
6460 | /* If OLDEQUIV is a pseudo with a MEM, get the real MEM | |
6461 | and similarly for OLD. | |
6462 | See comments in get_secondary_reload in reload.c. */ | |
6463 | /* If it is a pseudo that cannot be replaced with its | |
6464 | equivalent MEM, we must fall back to reload_in, which | |
6465 | will have all the necessary substitutions registered. | |
6466 | Likewise for a pseudo that can't be replaced with its | |
6467 | equivalent constant. | |
6468 | ||
6469 | Take extra care for subregs of such pseudos. Note that | |
6470 | we cannot use reg_equiv_mem in this case because it is | |
6471 | not in the right mode. */ | |
6472 | ||
6473 | tmp = oldequiv; | |
6474 | if (GET_CODE (tmp) == SUBREG) | |
6475 | tmp = SUBREG_REG (tmp); | |
6476 | if (GET_CODE (tmp) == REG | |
6477 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6478 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6479 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6480 | { | |
6481 | if (! reg_equiv_mem[REGNO (tmp)] | |
6482 | || num_not_at_initial_offset | |
6483 | || GET_CODE (oldequiv) == SUBREG) | |
6484 | real_oldequiv = rl->in; | |
6485 | else | |
6486 | real_oldequiv = reg_equiv_mem[REGNO (tmp)]; | |
6487 | } | |
32131a9c | 6488 | |
367b1cf5 BS |
6489 | tmp = old; |
6490 | if (GET_CODE (tmp) == SUBREG) | |
6491 | tmp = SUBREG_REG (tmp); | |
6492 | if (GET_CODE (tmp) == REG | |
6493 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6494 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6495 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6496 | { | |
6497 | if (! reg_equiv_mem[REGNO (tmp)] | |
6498 | || num_not_at_initial_offset | |
6499 | || GET_CODE (old) == SUBREG) | |
6500 | real_old = rl->in; | |
6501 | else | |
6502 | real_old = reg_equiv_mem[REGNO (tmp)]; | |
6503 | } | |
6504 | ||
6505 | second_reload_reg = rld[secondary_reload].reg_rtx; | |
6506 | icode = rl->secondary_in_icode; | |
6507 | ||
6508 | if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) | |
6509 | || (rl->in != 0 && rl->out != 0)) | |
6510 | { | |
6511 | enum reg_class new_class | |
6512 | = SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
6513 | mode, real_oldequiv); | |
6514 | ||
6515 | if (new_class == NO_REGS) | |
6516 | second_reload_reg = 0; | |
6517 | else | |
32131a9c | 6518 | { |
367b1cf5 BS |
6519 | enum insn_code new_icode; |
6520 | enum machine_mode new_mode; | |
6521 | ||
6522 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], | |
6523 | REGNO (second_reload_reg))) | |
6524 | oldequiv = old, real_oldequiv = real_old; | |
6525 | else | |
32131a9c | 6526 | { |
367b1cf5 BS |
6527 | new_icode = reload_in_optab[(int) mode]; |
6528 | if (new_icode != CODE_FOR_nothing | |
6529 | && ((insn_data[(int) new_icode].operand[0].predicate | |
6530 | && ! ((*insn_data[(int) new_icode].operand[0].predicate) | |
6531 | (reloadreg, mode))) | |
6532 | || (insn_data[(int) new_icode].operand[1].predicate | |
6533 | && ! ((*insn_data[(int) new_icode].operand[1].predicate) | |
6534 | (real_oldequiv, mode))))) | |
6535 | new_icode = CODE_FOR_nothing; | |
6536 | ||
6537 | if (new_icode == CODE_FOR_nothing) | |
6538 | new_mode = mode; | |
6539 | else | |
6540 | new_mode = insn_data[(int) new_icode].operand[2].mode; | |
d30e8ef0 | 6541 | |
367b1cf5 | 6542 | if (GET_MODE (second_reload_reg) != new_mode) |
32131a9c | 6543 | { |
367b1cf5 BS |
6544 | if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), |
6545 | new_mode)) | |
6546 | oldequiv = old, real_oldequiv = real_old; | |
6547 | else | |
6548 | second_reload_reg | |
6549 | = gen_rtx_REG (new_mode, | |
6550 | REGNO (second_reload_reg)); | |
32131a9c | 6551 | } |
32131a9c RK |
6552 | } |
6553 | } | |
367b1cf5 | 6554 | } |
32131a9c | 6555 | |
367b1cf5 BS |
6556 | /* If we still need a secondary reload register, check |
6557 | to see if it is being used as a scratch or intermediate | |
6558 | register and generate code appropriately. If we need | |
6559 | a scratch register, use REAL_OLDEQUIV since the form of | |
6560 | the insn may depend on the actual address if it is | |
6561 | a MEM. */ | |
546b63fb | 6562 | |
367b1cf5 BS |
6563 | if (second_reload_reg) |
6564 | { | |
6565 | if (icode != CODE_FOR_nothing) | |
32131a9c | 6566 | { |
367b1cf5 BS |
6567 | emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, |
6568 | second_reload_reg)); | |
07875628 | 6569 | special = 1; |
367b1cf5 BS |
6570 | } |
6571 | else | |
6572 | { | |
6573 | /* See if we need a scratch register to load the | |
6574 | intermediate register (a tertiary reload). */ | |
6575 | enum insn_code tertiary_icode | |
6576 | = rld[secondary_reload].secondary_in_icode; | |
1554c2c6 | 6577 | |
367b1cf5 BS |
6578 | if (tertiary_icode != CODE_FOR_nothing) |
6579 | { | |
6580 | rtx third_reload_reg | |
6581 | = rld[rld[secondary_reload].secondary_in_reload].reg_rtx; | |
1554c2c6 | 6582 | |
367b1cf5 BS |
6583 | emit_insn ((GEN_FCN (tertiary_icode) |
6584 | (second_reload_reg, real_oldequiv, | |
6585 | third_reload_reg))); | |
6586 | } | |
6587 | else | |
6588 | gen_reload (second_reload_reg, real_oldequiv, | |
6589 | rl->opnum, | |
6590 | rl->when_needed); | |
32131a9c | 6591 | |
367b1cf5 BS |
6592 | oldequiv = second_reload_reg; |
6593 | } | |
6594 | } | |
6595 | } | |
6596 | #endif | |
32131a9c | 6597 | |
07875628 | 6598 | if (! special && ! rtx_equal_p (reloadreg, oldequiv)) |
367b1cf5 BS |
6599 | { |
6600 | rtx real_oldequiv = oldequiv; | |
6601 | ||
6602 | if ((GET_CODE (oldequiv) == REG | |
6603 | && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER | |
6604 | && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 | |
6605 | || reg_equiv_constant[REGNO (oldequiv)] != 0)) | |
6606 | || (GET_CODE (oldequiv) == SUBREG | |
6607 | && GET_CODE (SUBREG_REG (oldequiv)) == REG | |
6608 | && (REGNO (SUBREG_REG (oldequiv)) | |
6609 | >= FIRST_PSEUDO_REGISTER) | |
6610 | && ((reg_equiv_memory_loc | |
6611 | [REGNO (SUBREG_REG (oldequiv))] != 0) | |
6612 | || (reg_equiv_constant | |
716120a7 JJ |
6613 | [REGNO (SUBREG_REG (oldequiv))] != 0))) |
6614 | || (CONSTANT_P (oldequiv) | |
019d2e99 AS |
6615 | && (PREFERRED_RELOAD_CLASS (oldequiv, |
6616 | REGNO_REG_CLASS (REGNO (reloadreg))) | |
6617 | == NO_REGS))) | |
367b1cf5 BS |
6618 | real_oldequiv = rl->in; |
6619 | gen_reload (reloadreg, real_oldequiv, rl->opnum, | |
6620 | rl->when_needed); | |
6621 | } | |
32131a9c | 6622 | |
94bd63e5 AH |
6623 | if (flag_non_call_exceptions) |
6624 | copy_eh_notes (insn, get_insns ()); | |
6625 | ||
367b1cf5 BS |
6626 | /* End this sequence. */ |
6627 | *where = get_insns (); | |
6628 | end_sequence (); | |
a6a2274a | 6629 | |
367b1cf5 BS |
6630 | /* Update reload_override_in so that delete_address_reloads_1 |
6631 | can see the actual register usage. */ | |
6632 | if (oldequiv_reg) | |
6633 | reload_override_in[j] = oldequiv; | |
6634 | } | |
32131a9c | 6635 | |
367b1cf5 BS |
6636 | /* Generate insns to for the output reload RL, which is for the insn described |
6637 | by CHAIN and has the number J. */ | |
6638 | static void | |
6639 | emit_output_reload_insns (chain, rl, j) | |
6640 | struct insn_chain *chain; | |
6641 | struct reload *rl; | |
6642 | int j; | |
6643 | { | |
6644 | rtx reloadreg = rl->reg_rtx; | |
6645 | rtx insn = chain->insn; | |
6646 | int special = 0; | |
6647 | rtx old = rl->out; | |
6648 | enum machine_mode mode = GET_MODE (old); | |
6649 | rtx p; | |
32131a9c | 6650 | |
367b1cf5 BS |
6651 | if (rl->when_needed == RELOAD_OTHER) |
6652 | start_sequence (); | |
6653 | else | |
6654 | push_to_sequence (output_reload_insns[rl->opnum]); | |
32131a9c | 6655 | |
367b1cf5 BS |
6656 | /* Determine the mode to reload in. |
6657 | See comments above (for input reloading). */ | |
32131a9c | 6658 | |
367b1cf5 BS |
6659 | if (mode == VOIDmode) |
6660 | { | |
6661 | /* VOIDmode should never happen for an output. */ | |
6662 | if (asm_noperands (PATTERN (insn)) < 0) | |
6663 | /* It's the compiler's fault. */ | |
6664 | fatal_insn ("VOIDmode on an output", insn); | |
6665 | error_for_asm (insn, "output operand is constant in `asm'"); | |
6666 | /* Prevent crash--use something we know is valid. */ | |
6667 | mode = word_mode; | |
6668 | old = gen_rtx_REG (mode, REGNO (reloadreg)); | |
6669 | } | |
546b63fb | 6670 | |
367b1cf5 BS |
6671 | if (GET_MODE (reloadreg) != mode) |
6672 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
32131a9c | 6673 | |
367b1cf5 | 6674 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
32131a9c | 6675 | |
367b1cf5 BS |
6676 | /* If we need two reload regs, set RELOADREG to the intermediate |
6677 | one, since it will be stored into OLD. We might need a secondary | |
6678 | register only for an input reload, so check again here. */ | |
32131a9c | 6679 | |
367b1cf5 BS |
6680 | if (rl->secondary_out_reload >= 0) |
6681 | { | |
6682 | rtx real_old = old; | |
cb2afeb3 | 6683 | |
367b1cf5 BS |
6684 | if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER |
6685 | && reg_equiv_mem[REGNO (old)] != 0) | |
6686 | real_old = reg_equiv_mem[REGNO (old)]; | |
32131a9c | 6687 | |
367b1cf5 BS |
6688 | if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class, |
6689 | mode, real_old) | |
6690 | != NO_REGS)) | |
b60a8416 | 6691 | { |
367b1cf5 BS |
6692 | rtx second_reloadreg = reloadreg; |
6693 | reloadreg = rld[rl->secondary_out_reload].reg_rtx; | |
32131a9c | 6694 | |
367b1cf5 BS |
6695 | /* See if RELOADREG is to be used as a scratch register |
6696 | or as an intermediate register. */ | |
6697 | if (rl->secondary_out_icode != CODE_FOR_nothing) | |
6698 | { | |
6699 | emit_insn ((GEN_FCN (rl->secondary_out_icode) | |
6700 | (real_old, second_reloadreg, reloadreg))); | |
6701 | special = 1; | |
6702 | } | |
6703 | else | |
6704 | { | |
6705 | /* See if we need both a scratch and intermediate reload | |
6706 | register. */ | |
32131a9c | 6707 | |
367b1cf5 BS |
6708 | int secondary_reload = rl->secondary_out_reload; |
6709 | enum insn_code tertiary_icode | |
6710 | = rld[secondary_reload].secondary_out_icode; | |
32131a9c | 6711 | |
367b1cf5 BS |
6712 | if (GET_MODE (reloadreg) != mode) |
6713 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
cb2afeb3 | 6714 | |
367b1cf5 BS |
6715 | if (tertiary_icode != CODE_FOR_nothing) |
6716 | { | |
6717 | rtx third_reloadreg | |
6718 | = rld[rld[secondary_reload].secondary_out_reload].reg_rtx; | |
6719 | rtx tem; | |
6720 | ||
6721 | /* Copy primary reload reg to secondary reload reg. | |
6722 | (Note that these have been swapped above, then | |
78adc5a0 | 6723 | secondary reload reg to OLD using our insn.) */ |
367b1cf5 BS |
6724 | |
6725 | /* If REAL_OLD is a paradoxical SUBREG, remove it | |
6726 | and try to put the opposite SUBREG on | |
6727 | RELOADREG. */ | |
6728 | if (GET_CODE (real_old) == SUBREG | |
6729 | && (GET_MODE_SIZE (GET_MODE (real_old)) | |
6730 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) | |
6731 | && 0 != (tem = gen_lowpart_common | |
6732 | (GET_MODE (SUBREG_REG (real_old)), | |
6733 | reloadreg))) | |
6734 | real_old = SUBREG_REG (real_old), reloadreg = tem; | |
6735 | ||
6736 | gen_reload (reloadreg, second_reloadreg, | |
6737 | rl->opnum, rl->when_needed); | |
6738 | emit_insn ((GEN_FCN (tertiary_icode) | |
6739 | (real_old, reloadreg, third_reloadreg))); | |
6740 | special = 1; | |
6741 | } | |
05d10675 | 6742 | |
367b1cf5 BS |
6743 | else |
6744 | /* Copy between the reload regs here and then to | |
6745 | OUT later. */ | |
cb2afeb3 | 6746 | |
367b1cf5 BS |
6747 | gen_reload (reloadreg, second_reloadreg, |
6748 | rl->opnum, rl->when_needed); | |
a7911cd2 | 6749 | } |
367b1cf5 BS |
6750 | } |
6751 | } | |
32131a9c RK |
6752 | #endif |
6753 | ||
367b1cf5 BS |
6754 | /* Output the last reload insn. */ |
6755 | if (! special) | |
6756 | { | |
6757 | rtx set; | |
6758 | ||
6759 | /* Don't output the last reload if OLD is not the dest of | |
1d7254c5 | 6760 | INSN and is in the src and is clobbered by INSN. */ |
367b1cf5 BS |
6761 | if (! flag_expensive_optimizations |
6762 | || GET_CODE (old) != REG | |
6763 | || !(set = single_set (insn)) | |
6764 | || rtx_equal_p (old, SET_DEST (set)) | |
6765 | || !reg_mentioned_p (old, SET_SRC (set)) | |
9532e31f | 6766 | || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0)) |
367b1cf5 BS |
6767 | gen_reload (old, reloadreg, rl->opnum, |
6768 | rl->when_needed); | |
6769 | } | |
32131a9c | 6770 | |
367b1cf5 BS |
6771 | /* Look at all insns we emitted, just to be safe. */ |
6772 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2c3c49de | 6773 | if (INSN_P (p)) |
367b1cf5 BS |
6774 | { |
6775 | rtx pat = PATTERN (p); | |
546b63fb | 6776 | |
367b1cf5 BS |
6777 | /* If this output reload doesn't come from a spill reg, |
6778 | clear any memory of reloaded copies of the pseudo reg. | |
6779 | If this output reload comes from a spill reg, | |
6780 | reg_has_output_reload will make this do nothing. */ | |
6781 | note_stores (pat, forget_old_reloads_1, NULL); | |
cb2afeb3 | 6782 | |
367b1cf5 BS |
6783 | if (reg_mentioned_p (rl->reg_rtx, pat)) |
6784 | { | |
6785 | rtx set = single_set (insn); | |
6786 | if (reload_spill_index[j] < 0 | |
6787 | && set | |
6788 | && SET_SRC (set) == rl->reg_rtx) | |
6789 | { | |
6790 | int src = REGNO (SET_SRC (set)); | |
32131a9c | 6791 | |
367b1cf5 BS |
6792 | reload_spill_index[j] = src; |
6793 | SET_HARD_REG_BIT (reg_is_output_reload, src); | |
6794 | if (find_regno_note (insn, REG_DEAD, src)) | |
6795 | SET_HARD_REG_BIT (reg_reloaded_died, src); | |
6796 | } | |
6797 | if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER) | |
6798 | { | |
6799 | int s = rl->secondary_out_reload; | |
6800 | set = single_set (p); | |
6801 | /* If this reload copies only to the secondary reload | |
6802 | register, the secondary reload does the actual | |
6803 | store. */ | |
6804 | if (s >= 0 && set == NULL_RTX) | |
1d7254c5 KH |
6805 | /* We can't tell what function the secondary reload |
6806 | has and where the actual store to the pseudo is | |
6807 | made; leave new_spill_reg_store alone. */ | |
6808 | ; | |
367b1cf5 BS |
6809 | else if (s >= 0 |
6810 | && SET_SRC (set) == rl->reg_rtx | |
6811 | && SET_DEST (set) == rld[s].reg_rtx) | |
6812 | { | |
6813 | /* Usually the next instruction will be the | |
6814 | secondary reload insn; if we can confirm | |
6815 | that it is, setting new_spill_reg_store to | |
6816 | that insn will allow an extra optimization. */ | |
6817 | rtx s_reg = rld[s].reg_rtx; | |
6818 | rtx next = NEXT_INSN (p); | |
6819 | rld[s].out = rl->out; | |
6820 | rld[s].out_reg = rl->out_reg; | |
6821 | set = single_set (next); | |
6822 | if (set && SET_SRC (set) == s_reg | |
6823 | && ! new_spill_reg_store[REGNO (s_reg)]) | |
6824 | { | |
6825 | SET_HARD_REG_BIT (reg_is_output_reload, | |
6826 | REGNO (s_reg)); | |
6827 | new_spill_reg_store[REGNO (s_reg)] = next; | |
6828 | } | |
6829 | } | |
6830 | else | |
6831 | new_spill_reg_store[REGNO (rl->reg_rtx)] = p; | |
6832 | } | |
6833 | } | |
6834 | } | |
32131a9c | 6835 | |
367b1cf5 BS |
6836 | if (rl->when_needed == RELOAD_OTHER) |
6837 | { | |
2f937369 | 6838 | emit_insn (other_output_reload_insns[rl->opnum]); |
367b1cf5 BS |
6839 | other_output_reload_insns[rl->opnum] = get_insns (); |
6840 | } | |
6841 | else | |
6842 | output_reload_insns[rl->opnum] = get_insns (); | |
32131a9c | 6843 | |
94bd63e5 AH |
6844 | if (flag_non_call_exceptions) |
6845 | copy_eh_notes (insn, get_insns ()); | |
6846 | ||
1d7254c5 | 6847 | end_sequence (); |
367b1cf5 | 6848 | } |
32131a9c | 6849 | |
367b1cf5 BS |
6850 | /* Do input reloading for reload RL, which is for the insn described by CHAIN |
6851 | and has the number J. */ | |
6852 | static void | |
6853 | do_input_reload (chain, rl, j) | |
6854 | struct insn_chain *chain; | |
6855 | struct reload *rl; | |
6856 | int j; | |
6857 | { | |
6858 | int expect_occurrences = 1; | |
6859 | rtx insn = chain->insn; | |
6860 | rtx old = (rl->in && GET_CODE (rl->in) == MEM | |
6861 | ? rl->in_reg : rl->in); | |
6862 | ||
6863 | if (old != 0 | |
6864 | /* AUTO_INC reloads need to be handled even if inherited. We got an | |
6865 | AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ | |
6866 | && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) | |
6867 | && ! rtx_equal_p (rl->reg_rtx, old) | |
6868 | && rl->reg_rtx != 0) | |
1d813780 | 6869 | emit_input_reload_insns (chain, rld + j, old, j); |
32131a9c | 6870 | |
367b1cf5 BS |
6871 | /* When inheriting a wider reload, we have a MEM in rl->in, |
6872 | e.g. inheriting a SImode output reload for | |
6873 | (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ | |
6874 | if (optimize && reload_inherited[j] && rl->in | |
6875 | && GET_CODE (rl->in) == MEM | |
6876 | && GET_CODE (rl->in_reg) == MEM | |
6877 | && reload_spill_index[j] >= 0 | |
6878 | && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) | |
6879 | { | |
6880 | expect_occurrences | |
4b983fdc | 6881 | = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1; |
1d7254c5 | 6882 | rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; |
367b1cf5 | 6883 | } |
32131a9c | 6884 | |
367b1cf5 BS |
6885 | /* If we are reloading a register that was recently stored in with an |
6886 | output-reload, see if we can prove there was | |
6887 | actually no need to store the old value in it. */ | |
32131a9c | 6888 | |
367b1cf5 BS |
6889 | if (optimize |
6890 | && (reload_inherited[j] || reload_override_in[j]) | |
6891 | && rl->reg_rtx | |
6892 | && GET_CODE (rl->reg_rtx) == REG | |
6893 | && spill_reg_store[REGNO (rl->reg_rtx)] != 0 | |
6894 | #if 0 | |
6895 | /* There doesn't seem to be any reason to restrict this to pseudos | |
6896 | and doing so loses in the case where we are copying from a | |
6897 | register of the wrong class. */ | |
6898 | && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6899 | >= FIRST_PSEUDO_REGISTER) | |
6900 | #endif | |
6901 | /* The insn might have already some references to stackslots | |
6902 | replaced by MEMs, while reload_out_reg still names the | |
6903 | original pseudo. */ | |
6904 | && (dead_or_set_p (insn, | |
6905 | spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6906 | || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], | |
6907 | rl->out_reg))) | |
6908 | delete_output_reload (insn, j, REGNO (rl->reg_rtx)); | |
6909 | } | |
32131a9c | 6910 | |
367b1cf5 BS |
6911 | /* Do output reloading for reload RL, which is for the insn described by |
6912 | CHAIN and has the number J. | |
6913 | ??? At some point we need to support handling output reloads of | |
6914 | JUMP_INSNs or insns that set cc0. */ | |
6915 | static void | |
6916 | do_output_reload (chain, rl, j) | |
6917 | struct insn_chain *chain; | |
6918 | struct reload *rl; | |
6919 | int j; | |
6920 | { | |
6921 | rtx note, old; | |
6922 | rtx insn = chain->insn; | |
6923 | /* If this is an output reload that stores something that is | |
6924 | not loaded in this same reload, see if we can eliminate a previous | |
6925 | store. */ | |
6926 | rtx pseudo = rl->out_reg; | |
6927 | ||
6928 | if (pseudo | |
159d5964 | 6929 | && optimize |
367b1cf5 BS |
6930 | && GET_CODE (pseudo) == REG |
6931 | && ! rtx_equal_p (rl->in_reg, pseudo) | |
6932 | && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER | |
6933 | && reg_last_reload_reg[REGNO (pseudo)]) | |
6934 | { | |
6935 | int pseudo_no = REGNO (pseudo); | |
6936 | int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); | |
6937 | ||
6938 | /* We don't need to test full validity of last_regno for | |
6939 | inherit here; we only want to know if the store actually | |
6940 | matches the pseudo. */ | |
60ef417d GK |
6941 | if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno) |
6942 | && reg_reloaded_contents[last_regno] == pseudo_no | |
367b1cf5 BS |
6943 | && spill_reg_store[last_regno] |
6944 | && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) | |
6945 | delete_output_reload (insn, j, last_regno); | |
6946 | } | |
5e03c156 | 6947 | |
367b1cf5 BS |
6948 | old = rl->out_reg; |
6949 | if (old == 0 | |
6950 | || rl->reg_rtx == old | |
6951 | || rl->reg_rtx == 0) | |
6952 | return; | |
32131a9c | 6953 | |
367b1cf5 BS |
6954 | /* An output operand that dies right away does need a reload, |
6955 | but need not be copied from it. Show the new location in the | |
6956 | REG_UNUSED note. */ | |
6957 | if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) | |
6958 | && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) | |
6959 | { | |
6960 | XEXP (note, 0) = rl->reg_rtx; | |
6961 | return; | |
6962 | } | |
6963 | /* Likewise for a SUBREG of an operand that dies. */ | |
6964 | else if (GET_CODE (old) == SUBREG | |
6965 | && GET_CODE (SUBREG_REG (old)) == REG | |
6966 | && 0 != (note = find_reg_note (insn, REG_UNUSED, | |
6967 | SUBREG_REG (old)))) | |
6968 | { | |
6969 | XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), | |
6970 | rl->reg_rtx); | |
6971 | return; | |
6972 | } | |
6973 | else if (GET_CODE (old) == SCRATCH) | |
6974 | /* If we aren't optimizing, there won't be a REG_UNUSED note, | |
6975 | but we don't want to make an output reload. */ | |
6976 | return; | |
1554c2c6 | 6977 | |
367b1cf5 BS |
6978 | /* If is a JUMP_INSN, we can't support output reloads yet. */ |
6979 | if (GET_CODE (insn) == JUMP_INSN) | |
6980 | abort (); | |
5e03c156 | 6981 | |
367b1cf5 BS |
6982 | emit_output_reload_insns (chain, rld + j, j); |
6983 | } | |
1554c2c6 | 6984 | |
367b1cf5 | 6985 | /* Output insns to reload values in and out of the chosen reload regs. */ |
32131a9c | 6986 | |
367b1cf5 | 6987 | static void |
e04ca094 | 6988 | emit_reload_insns (chain) |
367b1cf5 BS |
6989 | struct insn_chain *chain; |
6990 | { | |
6991 | rtx insn = chain->insn; | |
32131a9c | 6992 | |
b3694847 | 6993 | int j; |
e6e52be0 | 6994 | |
367b1cf5 | 6995 | CLEAR_HARD_REG_SET (reg_reloaded_died); |
e6e52be0 | 6996 | |
367b1cf5 BS |
6997 | for (j = 0; j < reload_n_operands; j++) |
6998 | input_reload_insns[j] = input_address_reload_insns[j] | |
6999 | = inpaddr_address_reload_insns[j] | |
7000 | = output_reload_insns[j] = output_address_reload_insns[j] | |
7001 | = outaddr_address_reload_insns[j] | |
7002 | = other_output_reload_insns[j] = 0; | |
7003 | other_input_address_reload_insns = 0; | |
7004 | other_input_reload_insns = 0; | |
7005 | operand_reload_insns = 0; | |
7006 | other_operand_reload_insns = 0; | |
32131a9c | 7007 | |
850aac53 | 7008 | /* Dump reloads into the dump file. */ |
e04ca094 | 7009 | if (rtl_dump_file) |
850aac53 | 7010 | { |
e04ca094 JL |
7011 | fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); |
7012 | debug_reload_to_stream (rtl_dump_file); | |
850aac53 JL |
7013 | } |
7014 | ||
367b1cf5 BS |
7015 | /* Now output the instructions to copy the data into and out of the |
7016 | reload registers. Do these in the order that the reloads were reported, | |
7017 | since reloads of base and index registers precede reloads of operands | |
7018 | and the operands may need the base and index registers reloaded. */ | |
32131a9c | 7019 | |
367b1cf5 BS |
7020 | for (j = 0; j < n_reloads; j++) |
7021 | { | |
7022 | if (rld[j].reg_rtx | |
7023 | && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER) | |
7024 | new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0; | |
d7e0324f | 7025 | |
367b1cf5 BS |
7026 | do_input_reload (chain, rld + j, j); |
7027 | do_output_reload (chain, rld + j, j); | |
32131a9c RK |
7028 | } |
7029 | ||
546b63fb RK |
7030 | /* Now write all the insns we made for reloads in the order expected by |
7031 | the allocation functions. Prior to the insn being reloaded, we write | |
7032 | the following reloads: | |
7033 | ||
7034 | RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. | |
7035 | ||
2edc8d65 | 7036 | RELOAD_OTHER reloads. |
546b63fb | 7037 | |
47c8cf91 ILT |
7038 | For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed |
7039 | by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the | |
7040 | RELOAD_FOR_INPUT reload for the operand. | |
546b63fb | 7041 | |
893bc853 RK |
7042 | RELOAD_FOR_OPADDR_ADDRS reloads. |
7043 | ||
546b63fb RK |
7044 | RELOAD_FOR_OPERAND_ADDRESS reloads. |
7045 | ||
7046 | After the insn being reloaded, we write the following: | |
7047 | ||
47c8cf91 ILT |
7048 | For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed |
7049 | by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the | |
7050 | RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output | |
7051 | reloads for the operand. The RELOAD_OTHER output reloads are | |
7052 | output in descending order by reload number. */ | |
546b63fb | 7053 | |
2f937369 DM |
7054 | emit_insn_before (other_input_address_reload_insns, insn); |
7055 | emit_insn_before (other_input_reload_insns, insn); | |
546b63fb RK |
7056 | |
7057 | for (j = 0; j < reload_n_operands; j++) | |
7058 | { | |
2f937369 DM |
7059 | emit_insn_before (inpaddr_address_reload_insns[j], insn); |
7060 | emit_insn_before (input_address_reload_insns[j], insn); | |
7061 | emit_insn_before (input_reload_insns[j], insn); | |
546b63fb RK |
7062 | } |
7063 | ||
2f937369 DM |
7064 | emit_insn_before (other_operand_reload_insns, insn); |
7065 | emit_insn_before (operand_reload_insns, insn); | |
546b63fb RK |
7066 | |
7067 | for (j = 0; j < reload_n_operands; j++) | |
7068 | { | |
2f937369 DM |
7069 | rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn); |
7070 | x = emit_insn_after (output_address_reload_insns[j], x); | |
7071 | x = emit_insn_after (output_reload_insns[j], x); | |
7072 | emit_insn_after (other_output_reload_insns[j], x); | |
546b63fb RK |
7073 | } |
7074 | ||
32131a9c RK |
7075 | /* For all the spill regs newly reloaded in this instruction, |
7076 | record what they were reloaded from, so subsequent instructions | |
d445b551 RK |
7077 | can inherit the reloads. |
7078 | ||
7079 | Update spill_reg_store for the reloads of this insn. | |
e9e79d69 | 7080 | Copy the elements that were updated in the loop above. */ |
32131a9c RK |
7081 | |
7082 | for (j = 0; j < n_reloads; j++) | |
7083 | { | |
b3694847 SS |
7084 | int r = reload_order[j]; |
7085 | int i = reload_spill_index[r]; | |
32131a9c | 7086 | |
78a2bc08 | 7087 | /* If this is a non-inherited input reload from a pseudo, we must |
05d10675 BS |
7088 | clear any memory of a previous store to the same pseudo. Only do |
7089 | something if there will not be an output reload for the pseudo | |
7090 | being reloaded. */ | |
eceef4c9 | 7091 | if (rld[r].in_reg != 0 |
05d10675 BS |
7092 | && ! (reload_inherited[r] || reload_override_in[r])) |
7093 | { | |
eceef4c9 | 7094 | rtx reg = rld[r].in_reg; |
78a2bc08 | 7095 | |
05d10675 | 7096 | if (GET_CODE (reg) == SUBREG) |
78a2bc08 | 7097 | reg = SUBREG_REG (reg); |
05d10675 BS |
7098 | |
7099 | if (GET_CODE (reg) == REG | |
78a2bc08 R |
7100 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER |
7101 | && ! reg_has_output_reload[REGNO (reg)]) | |
7102 | { | |
7103 | int nregno = REGNO (reg); | |
7104 | ||
7105 | if (reg_last_reload_reg[nregno]) | |
05d10675 BS |
7106 | { |
7107 | int last_regno = REGNO (reg_last_reload_reg[nregno]); | |
78a2bc08 | 7108 | |
05d10675 | 7109 | if (reg_reloaded_contents[last_regno] == nregno) |
78a2bc08 | 7110 | spill_reg_store[last_regno] = 0; |
05d10675 | 7111 | } |
78a2bc08 R |
7112 | } |
7113 | } | |
05d10675 | 7114 | |
e6e52be0 | 7115 | /* I is nonneg if this reload used a register. |
eceef4c9 | 7116 | If rld[r].reg_rtx is 0, this is an optional reload |
51f0c3b7 | 7117 | that we opted to ignore. */ |
d445b551 | 7118 | |
eceef4c9 | 7119 | if (i >= 0 && rld[r].reg_rtx != 0) |
32131a9c | 7120 | { |
1d7254c5 | 7121 | int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx)); |
32131a9c | 7122 | int k; |
51f0c3b7 JW |
7123 | int part_reaches_end = 0; |
7124 | int all_reaches_end = 1; | |
32131a9c | 7125 | |
51f0c3b7 JW |
7126 | /* For a multi register reload, we need to check if all or part |
7127 | of the value lives to the end. */ | |
32131a9c RK |
7128 | for (k = 0; k < nr; k++) |
7129 | { | |
eceef4c9 BS |
7130 | if (reload_reg_reaches_end_p (i + k, rld[r].opnum, |
7131 | rld[r].when_needed)) | |
51f0c3b7 JW |
7132 | part_reaches_end = 1; |
7133 | else | |
7134 | all_reaches_end = 0; | |
32131a9c RK |
7135 | } |
7136 | ||
51f0c3b7 JW |
7137 | /* Ignore reloads that don't reach the end of the insn in |
7138 | entirety. */ | |
7139 | if (all_reaches_end) | |
32131a9c | 7140 | { |
51f0c3b7 JW |
7141 | /* First, clear out memory of what used to be in this spill reg. |
7142 | If consecutive registers are used, clear them all. */ | |
d08ea79f | 7143 | |
32131a9c | 7144 | for (k = 0; k < nr; k++) |
e6e52be0 | 7145 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
d08ea79f | 7146 | |
51f0c3b7 | 7147 | /* Maybe the spill reg contains a copy of reload_out. */ |
eceef4c9 BS |
7148 | if (rld[r].out != 0 |
7149 | && (GET_CODE (rld[r].out) == REG | |
cb2afeb3 | 7150 | #ifdef AUTO_INC_DEC |
eceef4c9 | 7151 | || ! rld[r].out_reg |
cb2afeb3 | 7152 | #endif |
eceef4c9 | 7153 | || GET_CODE (rld[r].out_reg) == REG)) |
51f0c3b7 | 7154 | { |
eceef4c9 BS |
7155 | rtx out = (GET_CODE (rld[r].out) == REG |
7156 | ? rld[r].out | |
7157 | : rld[r].out_reg | |
7158 | ? rld[r].out_reg | |
7159 | /* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); | |
b3694847 | 7160 | int nregno = REGNO (out); |
51f0c3b7 JW |
7161 | int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
7162 | : HARD_REGNO_NREGS (nregno, | |
eceef4c9 | 7163 | GET_MODE (rld[r].reg_rtx))); |
51f0c3b7 JW |
7164 | |
7165 | spill_reg_store[i] = new_spill_reg_store[i]; | |
cb2afeb3 | 7166 | spill_reg_stored_to[i] = out; |
eceef4c9 | 7167 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
7168 | |
7169 | /* If NREGNO is a hard register, it may occupy more than | |
05d10675 | 7170 | one register. If it does, say what is in the |
51f0c3b7 JW |
7171 | rest of the registers assuming that both registers |
7172 | agree on how many words the object takes. If not, | |
7173 | invalidate the subsequent registers. */ | |
7174 | ||
7175 | if (nregno < FIRST_PSEUDO_REGISTER) | |
7176 | for (k = 1; k < nnr; k++) | |
7177 | reg_last_reload_reg[nregno + k] | |
7178 | = (nr == nnr | |
39d31de8 | 7179 | ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k] |
51f0c3b7 JW |
7180 | : 0); |
7181 | ||
7182 | /* Now do the inverse operation. */ | |
7183 | for (k = 0; k < nr; k++) | |
7184 | { | |
e6e52be0 R |
7185 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7186 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
7187 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
7188 | ? nregno | |
7189 | : nregno + k); | |
e6e52be0 R |
7190 | reg_reloaded_insn[i + k] = insn; |
7191 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
51f0c3b7 JW |
7192 | } |
7193 | } | |
d08ea79f | 7194 | |
51f0c3b7 JW |
7195 | /* Maybe the spill reg contains a copy of reload_in. Only do |
7196 | something if there will not be an output reload for | |
7197 | the register being reloaded. */ | |
eceef4c9 BS |
7198 | else if (rld[r].out_reg == 0 |
7199 | && rld[r].in != 0 | |
7200 | && ((GET_CODE (rld[r].in) == REG | |
7201 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER | |
7202 | && ! reg_has_output_reload[REGNO (rld[r].in)]) | |
7203 | || (GET_CODE (rld[r].in_reg) == REG | |
7204 | && ! reg_has_output_reload[REGNO (rld[r].in_reg)])) | |
7205 | && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn))) | |
51f0c3b7 | 7206 | { |
b3694847 | 7207 | int nregno; |
51f0c3b7 | 7208 | int nnr; |
d445b551 | 7209 | |
eceef4c9 BS |
7210 | if (GET_CODE (rld[r].in) == REG |
7211 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) | |
7212 | nregno = REGNO (rld[r].in); | |
7213 | else if (GET_CODE (rld[r].in_reg) == REG) | |
7214 | nregno = REGNO (rld[r].in_reg); | |
cb2afeb3 | 7215 | else |
eceef4c9 | 7216 | nregno = REGNO (XEXP (rld[r].in_reg, 0)); |
d08ea79f | 7217 | |
51f0c3b7 JW |
7218 | nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
7219 | : HARD_REGNO_NREGS (nregno, | |
eceef4c9 | 7220 | GET_MODE (rld[r].reg_rtx))); |
05d10675 | 7221 | |
eceef4c9 | 7222 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
7223 | |
7224 | if (nregno < FIRST_PSEUDO_REGISTER) | |
7225 | for (k = 1; k < nnr; k++) | |
7226 | reg_last_reload_reg[nregno + k] | |
7227 | = (nr == nnr | |
39d31de8 | 7228 | ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k] |
51f0c3b7 JW |
7229 | : 0); |
7230 | ||
7231 | /* Unless we inherited this reload, show we haven't | |
cb2afeb3 R |
7232 | recently done a store. |
7233 | Previous stores of inherited auto_inc expressions | |
7234 | also have to be discarded. */ | |
7235 | if (! reload_inherited[r] | |
eceef4c9 | 7236 | || (rld[r].out && ! rld[r].out_reg)) |
51f0c3b7 JW |
7237 | spill_reg_store[i] = 0; |
7238 | ||
7239 | for (k = 0; k < nr; k++) | |
7240 | { | |
e6e52be0 R |
7241 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7242 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
7243 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
7244 | ? nregno | |
7245 | : nregno + k); | |
e6e52be0 R |
7246 | reg_reloaded_insn[i + k] = insn; |
7247 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
51f0c3b7 JW |
7248 | } |
7249 | } | |
7250 | } | |
d445b551 | 7251 | |
51f0c3b7 JW |
7252 | /* However, if part of the reload reaches the end, then we must |
7253 | invalidate the old info for the part that survives to the end. */ | |
7254 | else if (part_reaches_end) | |
7255 | { | |
546b63fb | 7256 | for (k = 0; k < nr; k++) |
e6e52be0 | 7257 | if (reload_reg_reaches_end_p (i + k, |
eceef4c9 BS |
7258 | rld[r].opnum, |
7259 | rld[r].when_needed)) | |
e6e52be0 | 7260 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
32131a9c RK |
7261 | } |
7262 | } | |
7263 | ||
7264 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
7265 | It's reenabled in 1.35 because supposedly nothing else | |
7266 | deals with this problem. */ | |
7267 | ||
7268 | /* If a register gets output-reloaded from a non-spill register, | |
7269 | that invalidates any previous reloaded copy of it. | |
7270 | But forget_old_reloads_1 won't get to see it, because | |
7271 | it thinks only about the original insn. So invalidate it here. */ | |
eceef4c9 BS |
7272 | if (i < 0 && rld[r].out != 0 |
7273 | && (GET_CODE (rld[r].out) == REG | |
7274 | || (GET_CODE (rld[r].out) == MEM | |
7275 | && GET_CODE (rld[r].out_reg) == REG))) | |
32131a9c | 7276 | { |
eceef4c9 BS |
7277 | rtx out = (GET_CODE (rld[r].out) == REG |
7278 | ? rld[r].out : rld[r].out_reg); | |
b3694847 | 7279 | int nregno = REGNO (out); |
c7093272 | 7280 | if (nregno >= FIRST_PSEUDO_REGISTER) |
cb2afeb3 | 7281 | { |
6a651371 | 7282 | rtx src_reg, store_insn = NULL_RTX; |
cb2afeb3 R |
7283 | |
7284 | reg_last_reload_reg[nregno] = 0; | |
7285 | ||
7286 | /* If we can find a hard register that is stored, record | |
7287 | the storing insn so that we may delete this insn with | |
7288 | delete_output_reload. */ | |
eceef4c9 | 7289 | src_reg = rld[r].reg_rtx; |
cb2afeb3 R |
7290 | |
7291 | /* If this is an optional reload, try to find the source reg | |
7292 | from an input reload. */ | |
7293 | if (! src_reg) | |
7294 | { | |
7295 | rtx set = single_set (insn); | |
eceef4c9 | 7296 | if (set && SET_DEST (set) == rld[r].out) |
cb2afeb3 R |
7297 | { |
7298 | int k; | |
7299 | ||
7300 | src_reg = SET_SRC (set); | |
7301 | store_insn = insn; | |
7302 | for (k = 0; k < n_reloads; k++) | |
7303 | { | |
eceef4c9 | 7304 | if (rld[k].in == src_reg) |
cb2afeb3 | 7305 | { |
eceef4c9 | 7306 | src_reg = rld[k].reg_rtx; |
cb2afeb3 R |
7307 | break; |
7308 | } | |
7309 | } | |
7310 | } | |
7311 | } | |
7312 | else | |
7313 | store_insn = new_spill_reg_store[REGNO (src_reg)]; | |
7314 | if (src_reg && GET_CODE (src_reg) == REG | |
7315 | && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) | |
7316 | { | |
7317 | int src_regno = REGNO (src_reg); | |
8ec450a4 | 7318 | int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode); |
cb2afeb3 R |
7319 | /* The place where to find a death note varies with |
7320 | PRESERVE_DEATH_INFO_REGNO_P . The condition is not | |
7321 | necessarily checked exactly in the code that moves | |
7322 | notes, so just check both locations. */ | |
7323 | rtx note = find_regno_note (insn, REG_DEAD, src_regno); | |
1558b970 | 7324 | if (! note && store_insn) |
cb2afeb3 R |
7325 | note = find_regno_note (store_insn, REG_DEAD, src_regno); |
7326 | while (nr-- > 0) | |
7327 | { | |
7328 | spill_reg_store[src_regno + nr] = store_insn; | |
7329 | spill_reg_stored_to[src_regno + nr] = out; | |
7330 | reg_reloaded_contents[src_regno + nr] = nregno; | |
7331 | reg_reloaded_insn[src_regno + nr] = store_insn; | |
00f9f1bc | 7332 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr); |
cb2afeb3 R |
7333 | SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr); |
7334 | SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr); | |
7335 | if (note) | |
7336 | SET_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7337 | else | |
7338 | CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7339 | } | |
7340 | reg_last_reload_reg[nregno] = src_reg; | |
7341 | } | |
7342 | } | |
c7093272 RK |
7343 | else |
7344 | { | |
1d7254c5 | 7345 | int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out)); |
36281332 | 7346 | |
c7093272 RK |
7347 | while (num_regs-- > 0) |
7348 | reg_last_reload_reg[nregno + num_regs] = 0; | |
7349 | } | |
32131a9c RK |
7350 | } |
7351 | } | |
e6e52be0 | 7352 | IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); |
32131a9c RK |
7353 | } |
7354 | \f | |
5e03c156 RK |
7355 | /* Emit code to perform a reload from IN (which may be a reload register) to |
7356 | OUT (which may also be a reload register). IN or OUT is from operand | |
05d10675 | 7357 | OPNUM with reload type TYPE. |
546b63fb | 7358 | |
3c3eeea6 | 7359 | Returns first insn emitted. */ |
32131a9c RK |
7360 | |
7361 | rtx | |
5e03c156 RK |
7362 | gen_reload (out, in, opnum, type) |
7363 | rtx out; | |
32131a9c | 7364 | rtx in; |
546b63fb RK |
7365 | int opnum; |
7366 | enum reload_type type; | |
32131a9c | 7367 | { |
546b63fb | 7368 | rtx last = get_last_insn (); |
7a5b18b0 RK |
7369 | rtx tem; |
7370 | ||
7371 | /* If IN is a paradoxical SUBREG, remove it and try to put the | |
7372 | opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ | |
7373 | if (GET_CODE (in) == SUBREG | |
7374 | && (GET_MODE_SIZE (GET_MODE (in)) | |
7375 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
7376 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) | |
7377 | in = SUBREG_REG (in), out = tem; | |
7378 | else if (GET_CODE (out) == SUBREG | |
eceef4c9 BS |
7379 | && (GET_MODE_SIZE (GET_MODE (out)) |
7380 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
7381 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) | |
7a5b18b0 | 7382 | out = SUBREG_REG (out), in = tem; |
32131a9c | 7383 | |
a8fdc208 | 7384 | /* How to do this reload can get quite tricky. Normally, we are being |
32131a9c RK |
7385 | asked to reload a simple operand, such as a MEM, a constant, or a pseudo |
7386 | register that didn't get a hard register. In that case we can just | |
7387 | call emit_move_insn. | |
7388 | ||
a7fd196c JW |
7389 | We can also be asked to reload a PLUS that adds a register or a MEM to |
7390 | another register, constant or MEM. This can occur during frame pointer | |
7391 | elimination and while reloading addresses. This case is handled by | |
7392 | trying to emit a single insn to perform the add. If it is not valid, | |
7393 | we use a two insn sequence. | |
32131a9c RK |
7394 | |
7395 | Finally, we could be called to handle an 'o' constraint by putting | |
7396 | an address into a register. In that case, we first try to do this | |
7397 | with a named pattern of "reload_load_address". If no such pattern | |
7398 | exists, we just emit a SET insn and hope for the best (it will normally | |
7399 | be valid on machines that use 'o'). | |
7400 | ||
7401 | This entire process is made complex because reload will never | |
7402 | process the insns we generate here and so we must ensure that | |
7403 | they will fit their constraints and also by the fact that parts of | |
7404 | IN might be being reloaded separately and replaced with spill registers. | |
7405 | Because of this, we are, in some sense, just guessing the right approach | |
7406 | here. The one listed above seems to work. | |
7407 | ||
7408 | ??? At some point, this whole thing needs to be rethought. */ | |
7409 | ||
7410 | if (GET_CODE (in) == PLUS | |
a7fd196c | 7411 | && (GET_CODE (XEXP (in, 0)) == REG |
5c6b1bd2 | 7412 | || GET_CODE (XEXP (in, 0)) == SUBREG |
a7fd196c JW |
7413 | || GET_CODE (XEXP (in, 0)) == MEM) |
7414 | && (GET_CODE (XEXP (in, 1)) == REG | |
5c6b1bd2 | 7415 | || GET_CODE (XEXP (in, 1)) == SUBREG |
a7fd196c JW |
7416 | || CONSTANT_P (XEXP (in, 1)) |
7417 | || GET_CODE (XEXP (in, 1)) == MEM)) | |
32131a9c | 7418 | { |
a7fd196c JW |
7419 | /* We need to compute the sum of a register or a MEM and another |
7420 | register, constant, or MEM, and put it into the reload | |
3002e160 JW |
7421 | register. The best possible way of doing this is if the machine |
7422 | has a three-operand ADD insn that accepts the required operands. | |
32131a9c RK |
7423 | |
7424 | The simplest approach is to try to generate such an insn and see if it | |
7425 | is recognized and matches its constraints. If so, it can be used. | |
7426 | ||
7427 | It might be better not to actually emit the insn unless it is valid, | |
0009eff2 | 7428 | but we need to pass the insn as an operand to `recog' and |
0eadeb15 | 7429 | `extract_insn' and it is simpler to emit and then delete the insn if |
0009eff2 | 7430 | not valid than to dummy things up. */ |
a8fdc208 | 7431 | |
af929c62 | 7432 | rtx op0, op1, tem, insn; |
32131a9c | 7433 | int code; |
a8fdc208 | 7434 | |
af929c62 RK |
7435 | op0 = find_replacement (&XEXP (in, 0)); |
7436 | op1 = find_replacement (&XEXP (in, 1)); | |
7437 | ||
32131a9c RK |
7438 | /* Since constraint checking is strict, commutativity won't be |
7439 | checked, so we need to do that here to avoid spurious failure | |
7440 | if the add instruction is two-address and the second operand | |
7441 | of the add is the same as the reload reg, which is frequently | |
7442 | the case. If the insn would be A = B + A, rearrange it so | |
0f41302f | 7443 | it will be A = A + B as constrain_operands expects. */ |
a8fdc208 | 7444 | |
32131a9c | 7445 | if (GET_CODE (XEXP (in, 1)) == REG |
5e03c156 | 7446 | && REGNO (out) == REGNO (XEXP (in, 1))) |
af929c62 RK |
7447 | tem = op0, op0 = op1, op1 = tem; |
7448 | ||
7449 | if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) | |
38a448ca | 7450 | in = gen_rtx_PLUS (GET_MODE (in), op0, op1); |
32131a9c | 7451 | |
38a448ca | 7452 | insn = emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7453 | code = recog_memoized (insn); |
7454 | ||
7455 | if (code >= 0) | |
7456 | { | |
0eadeb15 | 7457 | extract_insn (insn); |
32131a9c RK |
7458 | /* We want constrain operands to treat this insn strictly in |
7459 | its validity determination, i.e., the way it would after reload | |
7460 | has completed. */ | |
0eadeb15 | 7461 | if (constrain_operands (1)) |
32131a9c RK |
7462 | return insn; |
7463 | } | |
7464 | ||
546b63fb | 7465 | delete_insns_since (last); |
32131a9c RK |
7466 | |
7467 | /* If that failed, we must use a conservative two-insn sequence. | |
09522f21 FS |
7468 | |
7469 | Use a move to copy one operand into the reload register. Prefer | |
7470 | to reload a constant, MEM or pseudo since the move patterns can | |
7471 | handle an arbitrary operand. If OP1 is not a constant, MEM or | |
7472 | pseudo and OP1 is not a valid operand for an add instruction, then | |
7473 | reload OP1. | |
7474 | ||
7475 | After reloading one of the operands into the reload register, add | |
7476 | the reload register to the output register. | |
32131a9c RK |
7477 | |
7478 | If there is another way to do this for a specific machine, a | |
7479 | DEFINE_PEEPHOLE should be specified that recognizes the sequence | |
7480 | we emit below. */ | |
7481 | ||
09522f21 FS |
7482 | code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code; |
7483 | ||
5c6b1bd2 | 7484 | if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG |
af929c62 | 7485 | || (GET_CODE (op1) == REG |
09522f21 FS |
7486 | && REGNO (op1) >= FIRST_PSEUDO_REGISTER) |
7487 | || (code != CODE_FOR_nothing | |
a995e389 RH |
7488 | && ! ((*insn_data[code].operand[2].predicate) |
7489 | (op1, insn_data[code].operand[2].mode)))) | |
af929c62 | 7490 | tem = op0, op0 = op1, op1 = tem; |
32131a9c | 7491 | |
5c6b1bd2 | 7492 | gen_reload (out, op0, opnum, type); |
39b56c2a | 7493 | |
5e03c156 | 7494 | /* If OP0 and OP1 are the same, we can use OUT for OP1. |
39b56c2a RK |
7495 | This fixes a problem on the 32K where the stack pointer cannot |
7496 | be used as an operand of an add insn. */ | |
7497 | ||
7498 | if (rtx_equal_p (op0, op1)) | |
5e03c156 | 7499 | op1 = out; |
39b56c2a | 7500 | |
5e03c156 | 7501 | insn = emit_insn (gen_add2_insn (out, op1)); |
c77c9766 RK |
7502 | |
7503 | /* If that failed, copy the address register to the reload register. | |
0f41302f | 7504 | Then add the constant to the reload register. */ |
c77c9766 RK |
7505 | |
7506 | code = recog_memoized (insn); | |
7507 | ||
7508 | if (code >= 0) | |
7509 | { | |
0eadeb15 | 7510 | extract_insn (insn); |
c77c9766 RK |
7511 | /* We want constrain operands to treat this insn strictly in |
7512 | its validity determination, i.e., the way it would after reload | |
7513 | has completed. */ | |
0eadeb15 | 7514 | if (constrain_operands (1)) |
4117a96b R |
7515 | { |
7516 | /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ | |
7517 | REG_NOTES (insn) | |
9e6a5703 | 7518 | = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
4117a96b R |
7519 | return insn; |
7520 | } | |
c77c9766 RK |
7521 | } |
7522 | ||
7523 | delete_insns_since (last); | |
7524 | ||
5c6b1bd2 | 7525 | gen_reload (out, op1, opnum, type); |
4117a96b | 7526 | insn = emit_insn (gen_add2_insn (out, op0)); |
9e6a5703 | 7527 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
32131a9c RK |
7528 | } |
7529 | ||
0dadecf6 RK |
7530 | #ifdef SECONDARY_MEMORY_NEEDED |
7531 | /* If we need a memory location to do the move, do it that way. */ | |
7532 | else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER | |
5e03c156 | 7533 | && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER |
0dadecf6 | 7534 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), |
5e03c156 RK |
7535 | REGNO_REG_CLASS (REGNO (out)), |
7536 | GET_MODE (out))) | |
0dadecf6 RK |
7537 | { |
7538 | /* Get the memory to use and rewrite both registers to its mode. */ | |
5e03c156 | 7539 | rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); |
0dadecf6 | 7540 | |
5e03c156 | 7541 | if (GET_MODE (loc) != GET_MODE (out)) |
38a448ca | 7542 | out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); |
0dadecf6 RK |
7543 | |
7544 | if (GET_MODE (loc) != GET_MODE (in)) | |
38a448ca | 7545 | in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); |
0dadecf6 | 7546 | |
5c6b1bd2 RK |
7547 | gen_reload (loc, in, opnum, type); |
7548 | gen_reload (out, loc, opnum, type); | |
0dadecf6 RK |
7549 | } |
7550 | #endif | |
7551 | ||
32131a9c RK |
7552 | /* If IN is a simple operand, use gen_move_insn. */ |
7553 | else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG) | |
5e03c156 | 7554 | emit_insn (gen_move_insn (out, in)); |
32131a9c RK |
7555 | |
7556 | #ifdef HAVE_reload_load_address | |
7557 | else if (HAVE_reload_load_address) | |
5e03c156 | 7558 | emit_insn (gen_reload_load_address (out, in)); |
32131a9c RK |
7559 | #endif |
7560 | ||
5e03c156 | 7561 | /* Otherwise, just write (set OUT IN) and hope for the best. */ |
32131a9c | 7562 | else |
38a448ca | 7563 | emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7564 | |
7565 | /* Return the first insn emitted. | |
546b63fb | 7566 | We can not just return get_last_insn, because there may have |
32131a9c RK |
7567 | been multiple instructions emitted. Also note that gen_move_insn may |
7568 | emit more than one insn itself, so we can not assume that there is one | |
7569 | insn emitted per emit_insn_before call. */ | |
7570 | ||
546b63fb | 7571 | return last ? NEXT_INSN (last) : get_insns (); |
32131a9c RK |
7572 | } |
7573 | \f | |
cda94cbb RH |
7574 | /* Delete a previously made output-reload whose result we now believe |
7575 | is not needed. First we double-check. | |
32131a9c RK |
7576 | |
7577 | INSN is the insn now being processed. | |
cb2afeb3 R |
7578 | LAST_RELOAD_REG is the hard register number for which we want to delete |
7579 | the last output reload. | |
7580 | J is the reload-number that originally used REG. The caller has made | |
7581 | certain that reload J doesn't use REG any longer for input. */ | |
32131a9c RK |
7582 | |
7583 | static void | |
cb2afeb3 | 7584 | delete_output_reload (insn, j, last_reload_reg) |
32131a9c RK |
7585 | rtx insn; |
7586 | int j; | |
cb2afeb3 | 7587 | int last_reload_reg; |
32131a9c | 7588 | { |
cb2afeb3 R |
7589 | rtx output_reload_insn = spill_reg_store[last_reload_reg]; |
7590 | rtx reg = spill_reg_stored_to[last_reload_reg]; | |
7591 | int k; | |
7592 | int n_occurrences; | |
7593 | int n_inherited = 0; | |
b3694847 | 7594 | rtx i1; |
cb2afeb3 | 7595 | rtx substed; |
05d10675 | 7596 | |
32131a9c RK |
7597 | /* Get the raw pseudo-register referred to. */ |
7598 | ||
32131a9c RK |
7599 | while (GET_CODE (reg) == SUBREG) |
7600 | reg = SUBREG_REG (reg); | |
cb2afeb3 R |
7601 | substed = reg_equiv_memory_loc[REGNO (reg)]; |
7602 | ||
7603 | /* This is unsafe if the operand occurs more often in the current | |
7604 | insn than it is inherited. */ | |
7605 | for (k = n_reloads - 1; k >= 0; k--) | |
7606 | { | |
eceef4c9 | 7607 | rtx reg2 = rld[k].in; |
cb2afeb3 R |
7608 | if (! reg2) |
7609 | continue; | |
7610 | if (GET_CODE (reg2) == MEM || reload_override_in[k]) | |
eceef4c9 | 7611 | reg2 = rld[k].in_reg; |
cb2afeb3 | 7612 | #ifdef AUTO_INC_DEC |
eceef4c9 BS |
7613 | if (rld[k].out && ! rld[k].out_reg) |
7614 | reg2 = XEXP (rld[k].in_reg, 0); | |
cb2afeb3 R |
7615 | #endif |
7616 | while (GET_CODE (reg2) == SUBREG) | |
7617 | reg2 = SUBREG_REG (reg2); | |
7618 | if (rtx_equal_p (reg2, reg)) | |
2eb6dac7 AS |
7619 | { |
7620 | if (reload_inherited[k] || reload_override_in[k] || k == j) | |
7621 | { | |
cb2afeb3 | 7622 | n_inherited++; |
eceef4c9 | 7623 | reg2 = rld[k].out_reg; |
2eb6dac7 AS |
7624 | if (! reg2) |
7625 | continue; | |
7626 | while (GET_CODE (reg2) == SUBREG) | |
7627 | reg2 = XEXP (reg2, 0); | |
7628 | if (rtx_equal_p (reg2, reg)) | |
7629 | n_inherited++; | |
7630 | } | |
7631 | else | |
7632 | return; | |
7633 | } | |
cb2afeb3 | 7634 | } |
4b983fdc | 7635 | n_occurrences = count_occurrences (PATTERN (insn), reg, 0); |
cb2afeb3 | 7636 | if (substed) |
5d7ef82a BS |
7637 | n_occurrences += count_occurrences (PATTERN (insn), |
7638 | eliminate_regs (substed, 0, | |
7639 | NULL_RTX), 0); | |
cb2afeb3 R |
7640 | if (n_occurrences > n_inherited) |
7641 | return; | |
32131a9c RK |
7642 | |
7643 | /* If the pseudo-reg we are reloading is no longer referenced | |
7644 | anywhere between the store into it and here, | |
7645 | and no jumps or labels intervene, then the value can get | |
7646 | here through the reload reg alone. | |
7647 | Otherwise, give up--return. */ | |
7648 | for (i1 = NEXT_INSN (output_reload_insn); | |
7649 | i1 != insn; i1 = NEXT_INSN (i1)) | |
7650 | { | |
7651 | if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) | |
7652 | return; | |
7653 | if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) | |
7654 | && reg_mentioned_p (reg, PATTERN (i1))) | |
aa6498c2 | 7655 | { |
cb2afeb3 R |
7656 | /* If this is USE in front of INSN, we only have to check that |
7657 | there are no more references than accounted for by inheritance. */ | |
7658 | while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE) | |
aa6498c2 | 7659 | { |
cb2afeb3 | 7660 | n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; |
aa6498c2 R |
7661 | i1 = NEXT_INSN (i1); |
7662 | } | |
cb2afeb3 | 7663 | if (n_occurrences <= n_inherited && i1 == insn) |
aa6498c2 R |
7664 | break; |
7665 | return; | |
7666 | } | |
32131a9c RK |
7667 | } |
7668 | ||
cda94cbb RH |
7669 | /* We will be deleting the insn. Remove the spill reg information. */ |
7670 | for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; ) | |
7671 | { | |
7672 | spill_reg_store[last_reload_reg + k] = 0; | |
7673 | spill_reg_stored_to[last_reload_reg + k] = 0; | |
7674 | } | |
7675 | ||
aa6498c2 | 7676 | /* The caller has already checked that REG dies or is set in INSN. |
cda94cbb RH |
7677 | It has also checked that we are optimizing, and thus some |
7678 | inaccurancies in the debugging information are acceptable. | |
7679 | So we could just delete output_reload_insn. But in some cases | |
7680 | we can improve the debugging information without sacrificing | |
7681 | optimization - maybe even improving the code: See if the pseudo | |
7682 | reg has been completely replaced with reload regs. If so, delete | |
7683 | the store insn and forget we had a stack slot for the pseudo. */ | |
eceef4c9 | 7684 | if (rld[j].out != rld[j].in |
aa6498c2 | 7685 | && REG_N_DEATHS (REGNO (reg)) == 1 |
a3a24aa6 | 7686 | && REG_N_SETS (REGNO (reg)) == 1 |
aa6498c2 R |
7687 | && REG_BASIC_BLOCK (REGNO (reg)) >= 0 |
7688 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) | |
32131a9c RK |
7689 | { |
7690 | rtx i2; | |
7691 | ||
cda94cbb RH |
7692 | /* We know that it was used only between here and the beginning of |
7693 | the current basic block. (We also know that the last use before | |
7694 | INSN was the output reload we are thinking of deleting, but never | |
7695 | mind that.) Search that range; see if any ref remains. */ | |
32131a9c RK |
7696 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) |
7697 | { | |
d445b551 RK |
7698 | rtx set = single_set (i2); |
7699 | ||
32131a9c RK |
7700 | /* Uses which just store in the pseudo don't count, |
7701 | since if they are the only uses, they are dead. */ | |
d445b551 | 7702 | if (set != 0 && SET_DEST (set) == reg) |
32131a9c RK |
7703 | continue; |
7704 | if (GET_CODE (i2) == CODE_LABEL | |
7705 | || GET_CODE (i2) == JUMP_INSN) | |
7706 | break; | |
7707 | if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) | |
7708 | && reg_mentioned_p (reg, PATTERN (i2))) | |
aa6498c2 R |
7709 | { |
7710 | /* Some other ref remains; just delete the output reload we | |
7711 | know to be dead. */ | |
cb2afeb3 | 7712 | delete_address_reloads (output_reload_insn, insn); |
ca6c03ca | 7713 | delete_insn (output_reload_insn); |
aa6498c2 R |
7714 | return; |
7715 | } | |
32131a9c RK |
7716 | } |
7717 | ||
cda94cbb RH |
7718 | /* Delete the now-dead stores into this pseudo. Note that this |
7719 | loop also takes care of deleting output_reload_insn. */ | |
32131a9c RK |
7720 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) |
7721 | { | |
d445b551 RK |
7722 | rtx set = single_set (i2); |
7723 | ||
7724 | if (set != 0 && SET_DEST (set) == reg) | |
5507b94b | 7725 | { |
cb2afeb3 | 7726 | delete_address_reloads (i2, insn); |
ca6c03ca | 7727 | delete_insn (i2); |
5507b94b | 7728 | } |
32131a9c RK |
7729 | if (GET_CODE (i2) == CODE_LABEL |
7730 | || GET_CODE (i2) == JUMP_INSN) | |
7731 | break; | |
7732 | } | |
7733 | ||
cda94cbb | 7734 | /* For the debugging info, say the pseudo lives in this reload reg. */ |
eceef4c9 | 7735 | reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx); |
32131a9c RK |
7736 | alter_reg (REGNO (reg), -1); |
7737 | } | |
cda94cbb RH |
7738 | else |
7739 | { | |
7740 | delete_address_reloads (output_reload_insn, insn); | |
7741 | delete_insn (output_reload_insn); | |
7742 | } | |
cb2afeb3 R |
7743 | } |
7744 | ||
7745 | /* We are going to delete DEAD_INSN. Recursively delete loads of | |
7746 | reload registers used in DEAD_INSN that are not used till CURRENT_INSN. | |
7747 | CURRENT_INSN is being reloaded, so we have to check its reloads too. */ | |
7748 | static void | |
7749 | delete_address_reloads (dead_insn, current_insn) | |
7750 | rtx dead_insn, current_insn; | |
7751 | { | |
7752 | rtx set = single_set (dead_insn); | |
7753 | rtx set2, dst, prev, next; | |
7754 | if (set) | |
7755 | { | |
7756 | rtx dst = SET_DEST (set); | |
7757 | if (GET_CODE (dst) == MEM) | |
7758 | delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); | |
7759 | } | |
7760 | /* If we deleted the store from a reloaded post_{in,de}c expression, | |
7761 | we can delete the matching adds. */ | |
7762 | prev = PREV_INSN (dead_insn); | |
7763 | next = NEXT_INSN (dead_insn); | |
7764 | if (! prev || ! next) | |
7765 | return; | |
7766 | set = single_set (next); | |
7767 | set2 = single_set (prev); | |
7768 | if (! set || ! set2 | |
7769 | || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS | |
7770 | || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT | |
7771 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT) | |
7772 | return; | |
7773 | dst = SET_DEST (set); | |
7774 | if (! rtx_equal_p (dst, SET_DEST (set2)) | |
7775 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) | |
7776 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) | |
7777 | || (INTVAL (XEXP (SET_SRC (set), 1)) | |
1d7254c5 | 7778 | != -INTVAL (XEXP (SET_SRC (set2), 1)))) |
cb2afeb3 | 7779 | return; |
53c17031 JH |
7780 | delete_related_insns (prev); |
7781 | delete_related_insns (next); | |
cb2afeb3 R |
7782 | } |
7783 | ||
7784 | /* Subfunction of delete_address_reloads: process registers found in X. */ | |
7785 | static void | |
7786 | delete_address_reloads_1 (dead_insn, x, current_insn) | |
7787 | rtx dead_insn, x, current_insn; | |
7788 | { | |
7789 | rtx prev, set, dst, i2; | |
7790 | int i, j; | |
7791 | enum rtx_code code = GET_CODE (x); | |
7792 | ||
7793 | if (code != REG) | |
7794 | { | |
1d7254c5 | 7795 | const char *fmt = GET_RTX_FORMAT (code); |
cb2afeb3 R |
7796 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
7797 | { | |
7798 | if (fmt[i] == 'e') | |
7799 | delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); | |
7800 | else if (fmt[i] == 'E') | |
7801 | { | |
1d7254c5 | 7802 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
cb2afeb3 R |
7803 | delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), |
7804 | current_insn); | |
7805 | } | |
7806 | } | |
7807 | return; | |
7808 | } | |
7809 | ||
7810 | if (spill_reg_order[REGNO (x)] < 0) | |
7811 | return; | |
aa6498c2 | 7812 | |
cb2afeb3 R |
7813 | /* Scan backwards for the insn that sets x. This might be a way back due |
7814 | to inheritance. */ | |
7815 | for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) | |
7816 | { | |
7817 | code = GET_CODE (prev); | |
7818 | if (code == CODE_LABEL || code == JUMP_INSN) | |
7819 | return; | |
7820 | if (GET_RTX_CLASS (code) != 'i') | |
7821 | continue; | |
7822 | if (reg_set_p (x, PATTERN (prev))) | |
7823 | break; | |
7824 | if (reg_referenced_p (x, PATTERN (prev))) | |
7825 | return; | |
7826 | } | |
7827 | if (! prev || INSN_UID (prev) < reload_first_uid) | |
7828 | return; | |
7829 | /* Check that PREV only sets the reload register. */ | |
7830 | set = single_set (prev); | |
7831 | if (! set) | |
7832 | return; | |
7833 | dst = SET_DEST (set); | |
7834 | if (GET_CODE (dst) != REG | |
7835 | || ! rtx_equal_p (dst, x)) | |
7836 | return; | |
7837 | if (! reg_set_p (dst, PATTERN (dead_insn))) | |
7838 | { | |
7839 | /* Check if DST was used in a later insn - | |
7840 | it might have been inherited. */ | |
7841 | for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) | |
7842 | { | |
7843 | if (GET_CODE (i2) == CODE_LABEL) | |
7844 | break; | |
2c3c49de | 7845 | if (! INSN_P (i2)) |
cb2afeb3 R |
7846 | continue; |
7847 | if (reg_referenced_p (dst, PATTERN (i2))) | |
7848 | { | |
7849 | /* If there is a reference to the register in the current insn, | |
7850 | it might be loaded in a non-inherited reload. If no other | |
7851 | reload uses it, that means the register is set before | |
7852 | referenced. */ | |
7853 | if (i2 == current_insn) | |
7854 | { | |
7855 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7856 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7857 | || reload_override_in[j] == dst) |
7858 | return; | |
7859 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7860 | if (rld[j].in && rld[j].reg_rtx == dst) |
cb2afeb3 R |
7861 | break; |
7862 | if (j >= 0) | |
7863 | break; | |
7864 | } | |
7865 | return; | |
7866 | } | |
7867 | if (GET_CODE (i2) == JUMP_INSN) | |
7868 | break; | |
cb2afeb3 | 7869 | /* If DST is still live at CURRENT_INSN, check if it is used for |
3900dc09 R |
7870 | any reload. Note that even if CURRENT_INSN sets DST, we still |
7871 | have to check the reloads. */ | |
cb2afeb3 R |
7872 | if (i2 == current_insn) |
7873 | { | |
7874 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7875 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7876 | || reload_override_in[j] == dst) |
7877 | return; | |
7878 | /* ??? We can't finish the loop here, because dst might be | |
7879 | allocated to a pseudo in this block if no reload in this | |
7880 | block needs any of the clsses containing DST - see | |
7881 | spill_hard_reg. There is no easy way to tell this, so we | |
7882 | have to scan till the end of the basic block. */ | |
7883 | } | |
3900dc09 R |
7884 | if (reg_set_p (dst, PATTERN (i2))) |
7885 | break; | |
cb2afeb3 R |
7886 | } |
7887 | } | |
7888 | delete_address_reloads_1 (prev, SET_SRC (set), current_insn); | |
7889 | reg_reloaded_contents[REGNO (dst)] = -1; | |
ca6c03ca | 7890 | delete_insn (prev); |
32131a9c | 7891 | } |
32131a9c | 7892 | \f |
a8fdc208 | 7893 | /* Output reload-insns to reload VALUE into RELOADREG. |
858a47b1 | 7894 | VALUE is an autoincrement or autodecrement RTX whose operand |
32131a9c RK |
7895 | is a register or memory location; |
7896 | so reloading involves incrementing that location. | |
cb2afeb3 | 7897 | IN is either identical to VALUE, or some cheaper place to reload from. |
32131a9c RK |
7898 | |
7899 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
cb2afeb3 | 7900 | This cannot be deduced from VALUE. |
32131a9c | 7901 | |
cb2afeb3 R |
7902 | Return the instruction that stores into RELOADREG. */ |
7903 | ||
7904 | static rtx | |
7905 | inc_for_reload (reloadreg, in, value, inc_amount) | |
32131a9c | 7906 | rtx reloadreg; |
cb2afeb3 | 7907 | rtx in, value; |
32131a9c | 7908 | int inc_amount; |
32131a9c RK |
7909 | { |
7910 | /* REG or MEM to be copied and incremented. */ | |
7911 | rtx incloc = XEXP (value, 0); | |
7912 | /* Nonzero if increment after copying. */ | |
7913 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); | |
546b63fb | 7914 | rtx last; |
0009eff2 RK |
7915 | rtx inc; |
7916 | rtx add_insn; | |
7917 | int code; | |
cb2afeb3 R |
7918 | rtx store; |
7919 | rtx real_in = in == value ? XEXP (in, 0) : in; | |
32131a9c RK |
7920 | |
7921 | /* No hard register is equivalent to this register after | |
7922 | inc/dec operation. If REG_LAST_RELOAD_REG were non-zero, | |
7923 | we could inc/dec that register as well (maybe even using it for | |
7924 | the source), but I'm not sure it's worth worrying about. */ | |
7925 | if (GET_CODE (incloc) == REG) | |
7926 | reg_last_reload_reg[REGNO (incloc)] = 0; | |
7927 | ||
7928 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
1d7254c5 | 7929 | inc_amount = -inc_amount; |
32131a9c | 7930 | |
fb3821f7 | 7931 | inc = GEN_INT (inc_amount); |
0009eff2 RK |
7932 | |
7933 | /* If this is post-increment, first copy the location to the reload reg. */ | |
cb2afeb3 R |
7934 | if (post && real_in != reloadreg) |
7935 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
0009eff2 | 7936 | |
cb2afeb3 R |
7937 | if (in == value) |
7938 | { | |
7939 | /* See if we can directly increment INCLOC. Use a method similar to | |
7940 | that in gen_reload. */ | |
0009eff2 | 7941 | |
cb2afeb3 R |
7942 | last = get_last_insn (); |
7943 | add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, | |
7944 | gen_rtx_PLUS (GET_MODE (incloc), | |
7945 | incloc, inc))); | |
05d10675 | 7946 | |
cb2afeb3 R |
7947 | code = recog_memoized (add_insn); |
7948 | if (code >= 0) | |
32131a9c | 7949 | { |
0eadeb15 BS |
7950 | extract_insn (add_insn); |
7951 | if (constrain_operands (1)) | |
cb2afeb3 R |
7952 | { |
7953 | /* If this is a pre-increment and we have incremented the value | |
7954 | where it lives, copy the incremented value to RELOADREG to | |
7955 | be used as an address. */ | |
0009eff2 | 7956 | |
cb2afeb3 R |
7957 | if (! post) |
7958 | emit_insn (gen_move_insn (reloadreg, incloc)); | |
546b63fb | 7959 | |
cb2afeb3 R |
7960 | return add_insn; |
7961 | } | |
32131a9c | 7962 | } |
cb2afeb3 | 7963 | delete_insns_since (last); |
32131a9c | 7964 | } |
0009eff2 | 7965 | |
0009eff2 RK |
7966 | /* If couldn't do the increment directly, must increment in RELOADREG. |
7967 | The way we do this depends on whether this is pre- or post-increment. | |
7968 | For pre-increment, copy INCLOC to the reload register, increment it | |
7969 | there, then save back. */ | |
7970 | ||
7971 | if (! post) | |
7972 | { | |
cb2afeb3 R |
7973 | if (in != reloadreg) |
7974 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
546b63fb | 7975 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7976 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
0009eff2 | 7977 | } |
32131a9c RK |
7978 | else |
7979 | { | |
0009eff2 RK |
7980 | /* Postincrement. |
7981 | Because this might be a jump insn or a compare, and because RELOADREG | |
7982 | may not be available after the insn in an input reload, we must do | |
7983 | the incrementation before the insn being reloaded for. | |
7984 | ||
cb2afeb3 | 7985 | We have already copied IN to RELOADREG. Increment the copy in |
0009eff2 RK |
7986 | RELOADREG, save that back, then decrement RELOADREG so it has |
7987 | the original value. */ | |
7988 | ||
546b63fb | 7989 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7990 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
546b63fb | 7991 | emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount))); |
32131a9c | 7992 | } |
0009eff2 | 7993 | |
cb2afeb3 | 7994 | return store; |
32131a9c RK |
7995 | } |
7996 | \f | |
2a9fb548 | 7997 | |
eab5c70a | 7998 | /* See whether a single set SET is a noop. */ |
2a9fb548 | 7999 | static int |
eab5c70a BS |
8000 | reload_cse_noop_set_p (set) |
8001 | rtx set; | |
2a9fb548 | 8002 | { |
eab5c70a BS |
8003 | return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); |
8004 | } | |
2a9fb548 | 8005 | |
eab5c70a BS |
8006 | /* Try to simplify INSN. */ |
8007 | static void | |
bf1660a6 | 8008 | reload_cse_simplify (insn, testreg) |
eab5c70a | 8009 | rtx insn; |
bf1660a6 | 8010 | rtx testreg; |
eab5c70a BS |
8011 | { |
8012 | rtx body = PATTERN (insn); | |
2a9fb548 | 8013 | |
eab5c70a | 8014 | if (GET_CODE (body) == SET) |
2a9fb548 | 8015 | { |
eab5c70a | 8016 | int count = 0; |
d5ae21aa AH |
8017 | |
8018 | /* Simplify even if we may think it is a no-op. | |
8019 | We may think a memory load of a value smaller than WORD_SIZE | |
8020 | is redundant because we haven't taken into account possible | |
8021 | implicit extension. reload_cse_simplify_set() will bring | |
8022 | this out, so it's safer to simplify before we delete. */ | |
8023 | count += reload_cse_simplify_set (body, insn); | |
8024 | ||
8025 | if (!count && reload_cse_noop_set_p (body)) | |
2a9fb548 | 8026 | { |
eab5c70a | 8027 | rtx value = SET_DEST (body); |
e0a09fda KW |
8028 | if (REG_P (value) |
8029 | && ! REG_FUNCTION_VALUE_P (value)) | |
eab5c70a | 8030 | value = 0; |
10d1bb36 | 8031 | delete_insn_and_edges (insn); |
eab5c70a | 8032 | return; |
2a9fb548 | 8033 | } |
2a9fb548 | 8034 | |
eab5c70a BS |
8035 | if (count > 0) |
8036 | apply_change_group (); | |
8037 | else | |
bf1660a6 | 8038 | reload_cse_simplify_operands (insn, testreg); |
eab5c70a BS |
8039 | } |
8040 | else if (GET_CODE (body) == PARALLEL) | |
2a9fb548 | 8041 | { |
eab5c70a BS |
8042 | int i; |
8043 | int count = 0; | |
8044 | rtx value = NULL_RTX; | |
2a9fb548 | 8045 | |
eab5c70a BS |
8046 | /* If every action in a PARALLEL is a noop, we can delete |
8047 | the entire PARALLEL. */ | |
8048 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
2a9fb548 | 8049 | { |
eab5c70a BS |
8050 | rtx part = XVECEXP (body, 0, i); |
8051 | if (GET_CODE (part) == SET) | |
2a9fb548 | 8052 | { |
eab5c70a BS |
8053 | if (! reload_cse_noop_set_p (part)) |
8054 | break; | |
cf87d551 HPN |
8055 | if (REG_P (SET_DEST (part)) |
8056 | && REG_FUNCTION_VALUE_P (SET_DEST (part))) | |
2a9fb548 | 8057 | { |
eab5c70a BS |
8058 | if (value) |
8059 | break; | |
8060 | value = SET_DEST (part); | |
2a9fb548 | 8061 | } |
2a9fb548 | 8062 | } |
eab5c70a BS |
8063 | else if (GET_CODE (part) != CLOBBER) |
8064 | break; | |
2a9fb548 | 8065 | } |
2a9fb548 | 8066 | |
eab5c70a BS |
8067 | if (i < 0) |
8068 | { | |
10d1bb36 | 8069 | delete_insn_and_edges (insn); |
eab5c70a BS |
8070 | /* We're done with this insn. */ |
8071 | return; | |
8072 | } | |
2a9fb548 | 8073 | |
eab5c70a BS |
8074 | /* It's not a no-op, but we can try to simplify it. */ |
8075 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
8076 | if (GET_CODE (XVECEXP (body, 0, i)) == SET) | |
8077 | count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); | |
8078 | ||
8079 | if (count > 0) | |
8080 | apply_change_group (); | |
8081 | else | |
bf1660a6 | 8082 | reload_cse_simplify_operands (insn, testreg); |
eab5c70a | 8083 | } |
2a9fb548 ILT |
8084 | } |
8085 | ||
8086 | /* Do a very simple CSE pass over the hard registers. | |
8087 | ||
8088 | This function detects no-op moves where we happened to assign two | |
8089 | different pseudo-registers to the same hard register, and then | |
8090 | copied one to the other. Reload will generate a useless | |
8091 | instruction copying a register to itself. | |
8092 | ||
8093 | This function also detects cases where we load a value from memory | |
8094 | into two different registers, and (if memory is more expensive than | |
8095 | registers) changes it to simply copy the first register into the | |
05d10675 | 8096 | second register. |
e9a25f70 JL |
8097 | |
8098 | Another optimization is performed that scans the operands of each | |
8099 | instruction to see whether the value is already available in a | |
8100 | hard register. It then replaces the operand with the hard register | |
8101 | if possible, much like an optional reload would. */ | |
2a9fb548 | 8102 | |
5adf6da0 R |
8103 | static void |
8104 | reload_cse_regs_1 (first) | |
2a9fb548 ILT |
8105 | rtx first; |
8106 | { | |
2a9fb548 | 8107 | rtx insn; |
bf1660a6 | 8108 | rtx testreg = gen_rtx_REG (VOIDmode, -1); |
2a9fb548 | 8109 | |
1d7254c5 | 8110 | cselib_init (); |
cbfc3ad3 RK |
8111 | init_alias_analysis (); |
8112 | ||
2a9fb548 ILT |
8113 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
8114 | { | |
2c3c49de | 8115 | if (INSN_P (insn)) |
bf1660a6 | 8116 | reload_cse_simplify (insn, testreg); |
2a9fb548 | 8117 | |
eab5c70a | 8118 | cselib_process_insn (insn); |
2a9fb548 ILT |
8119 | } |
8120 | ||
e05e2395 MM |
8121 | /* Clean up. */ |
8122 | end_alias_analysis (); | |
eab5c70a | 8123 | cselib_finish (); |
2a9fb548 ILT |
8124 | } |
8125 | ||
5adf6da0 R |
8126 | /* Call cse / combine like post-reload optimization phases. |
8127 | FIRST is the first instruction. */ | |
8128 | void | |
8129 | reload_cse_regs (first) | |
8130 | rtx first; | |
8131 | { | |
8132 | reload_cse_regs_1 (first); | |
8133 | reload_combine (); | |
8134 | reload_cse_move2add (first); | |
8135 | if (flag_expensive_optimizations) | |
8136 | reload_cse_regs_1 (first); | |
8137 | } | |
8138 | ||
2a9fb548 | 8139 | /* Try to simplify a single SET instruction. SET is the set pattern. |
e9a25f70 JL |
8140 | INSN is the instruction it came from. |
8141 | This function only handles one case: if we set a register to a value | |
8142 | which is not a register, we try to find that value in some other register | |
8143 | and change the set into a register copy. */ | |
2a9fb548 | 8144 | |
e9a25f70 | 8145 | static int |
2a9fb548 ILT |
8146 | reload_cse_simplify_set (set, insn) |
8147 | rtx set; | |
8148 | rtx insn; | |
8149 | { | |
eab5c70a | 8150 | int did_change = 0; |
2a9fb548 ILT |
8151 | int dreg; |
8152 | rtx src; | |
2a9fb548 | 8153 | enum reg_class dclass; |
eab5c70a BS |
8154 | int old_cost; |
8155 | cselib_val *val; | |
8156 | struct elt_loc_list *l; | |
78adc5a0 RH |
8157 | #ifdef LOAD_EXTEND_OP |
8158 | enum rtx_code extend_op = NIL; | |
8159 | #endif | |
2a9fb548 | 8160 | |
2a9fb548 ILT |
8161 | dreg = true_regnum (SET_DEST (set)); |
8162 | if (dreg < 0) | |
e9a25f70 | 8163 | return 0; |
2a9fb548 ILT |
8164 | |
8165 | src = SET_SRC (set); | |
8166 | if (side_effects_p (src) || true_regnum (src) >= 0) | |
e9a25f70 | 8167 | return 0; |
2a9fb548 | 8168 | |
cbd5b9a2 KR |
8169 | dclass = REGNO_REG_CLASS (dreg); |
8170 | ||
78adc5a0 RH |
8171 | #ifdef LOAD_EXTEND_OP |
8172 | /* When replacing a memory with a register, we need to honor assumptions | |
8173 | that combine made wrt the contents of sign bits. We'll do this by | |
a6a2274a | 8174 | generating an extend instruction instead of a reg->reg copy. Thus |
78adc5a0 RH |
8175 | the destination must be a register that we can widen. */ |
8176 | if (GET_CODE (src) == MEM | |
8177 | && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD | |
8178 | && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL | |
8179 | && GET_CODE (SET_DEST (set)) != REG) | |
8180 | return 0; | |
8181 | #endif | |
8182 | ||
33ab8de0 | 8183 | /* If memory loads are cheaper than register copies, don't change them. */ |
eab5c70a BS |
8184 | if (GET_CODE (src) == MEM) |
8185 | old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1); | |
8186 | else if (CONSTANT_P (src)) | |
8187 | old_cost = rtx_cost (src, SET); | |
8188 | else if (GET_CODE (src) == REG) | |
e56b4594 AO |
8189 | old_cost = REGISTER_MOVE_COST (GET_MODE (src), |
8190 | REGNO_REG_CLASS (REGNO (src)), dclass); | |
eab5c70a BS |
8191 | else |
8192 | /* ??? */ | |
8193 | old_cost = rtx_cost (src, SET); | |
2a9fb548 | 8194 | |
70bbeb8b | 8195 | val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0); |
eab5c70a | 8196 | if (! val) |
0254c561 | 8197 | return 0; |
eab5c70a | 8198 | for (l = val->locs; l; l = l->next) |
2a9fb548 | 8199 | { |
78adc5a0 | 8200 | rtx this_rtx = l->loc; |
eab5c70a | 8201 | int this_cost; |
78adc5a0 RH |
8202 | |
8203 | if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0)) | |
8204 | { | |
8205 | #ifdef LOAD_EXTEND_OP | |
8206 | if (extend_op != NIL) | |
8207 | { | |
8208 | HOST_WIDE_INT this_val; | |
8209 | ||
8210 | /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other | |
8211 | constants, such as SYMBOL_REF, cannot be extended. */ | |
8212 | if (GET_CODE (this_rtx) != CONST_INT) | |
8213 | continue; | |
8214 | ||
8215 | this_val = INTVAL (this_rtx); | |
8216 | switch (extend_op) | |
8217 | { | |
8218 | case ZERO_EXTEND: | |
8219 | this_val &= GET_MODE_MASK (GET_MODE (src)); | |
8220 | break; | |
8221 | case SIGN_EXTEND: | |
8222 | /* ??? In theory we're already extended. */ | |
8223 | if (this_val == trunc_int_for_mode (this_val, GET_MODE (src))) | |
8224 | break; | |
8225 | default: | |
8226 | abort (); | |
8227 | } | |
5cada064 | 8228 | this_rtx = GEN_INT (this_val); |
78adc5a0 RH |
8229 | } |
8230 | #endif | |
8231 | this_cost = rtx_cost (this_rtx, SET); | |
8232 | } | |
8233 | else if (GET_CODE (this_rtx) == REG) | |
8234 | { | |
8235 | #ifdef LOAD_EXTEND_OP | |
8236 | if (extend_op != NIL) | |
8237 | { | |
8238 | this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx); | |
8239 | this_cost = rtx_cost (this_rtx, SET); | |
8240 | } | |
8241 | else | |
8242 | #endif | |
8243 | this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx), | |
8244 | REGNO_REG_CLASS (REGNO (this_rtx)), | |
8245 | dclass); | |
8246 | } | |
eab5c70a BS |
8247 | else |
8248 | continue; | |
78adc5a0 RH |
8249 | |
8250 | /* If equal costs, prefer registers over anything else. That | |
8251 | tends to lead to smaller instructions on some machines. */ | |
8252 | if (this_cost < old_cost | |
8253 | || (this_cost == old_cost | |
8254 | && GET_CODE (this_rtx) == REG | |
8255 | && GET_CODE (SET_SRC (set)) != REG)) | |
8256 | { | |
8257 | #ifdef LOAD_EXTEND_OP | |
b216e516 JL |
8258 | if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD |
8259 | && extend_op != NIL) | |
8260 | { | |
8261 | rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))); | |
8262 | ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set)); | |
8263 | validate_change (insn, &SET_DEST (set), wide_dest, 1); | |
8264 | } | |
78adc5a0 RH |
8265 | #endif |
8266 | ||
8267 | validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1); | |
8268 | old_cost = this_cost, did_change = 1; | |
8269 | } | |
e9a25f70 | 8270 | } |
eab5c70a BS |
8271 | |
8272 | return did_change; | |
e9a25f70 JL |
8273 | } |
8274 | ||
8275 | /* Try to replace operands in INSN with equivalent values that are already | |
05d10675 BS |
8276 | in registers. This can be viewed as optional reloading. |
8277 | ||
e9a25f70 JL |
8278 | For each non-register operand in the insn, see if any hard regs are |
8279 | known to be equivalent to that operand. Record the alternatives which | |
8280 | can accept these hard registers. Among all alternatives, select the | |
8281 | ones which are better or equal to the one currently matching, where | |
8282 | "better" is in terms of '?' and '!' constraints. Among the remaining | |
8283 | alternatives, select the one which replaces most operands with | |
8284 | hard registers. */ | |
8285 | ||
8286 | static int | |
bf1660a6 | 8287 | reload_cse_simplify_operands (insn, testreg) |
e9a25f70 | 8288 | rtx insn; |
bf1660a6 | 8289 | rtx testreg; |
e9a25f70 | 8290 | { |
1d7254c5 | 8291 | int i, j; |
e9a25f70 | 8292 | |
eab5c70a BS |
8293 | /* For each operand, all registers that are equivalent to it. */ |
8294 | HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; | |
8295 | ||
9b3142b3 | 8296 | const char *constraints[MAX_RECOG_OPERANDS]; |
05d10675 | 8297 | |
e9a25f70 JL |
8298 | /* Vector recording how bad an alternative is. */ |
8299 | int *alternative_reject; | |
8300 | /* Vector recording how many registers can be introduced by choosing | |
8301 | this alternative. */ | |
8302 | int *alternative_nregs; | |
8303 | /* Array of vectors recording, for each operand and each alternative, | |
8304 | which hard register to substitute, or -1 if the operand should be | |
8305 | left as it is. */ | |
8306 | int *op_alt_regno[MAX_RECOG_OPERANDS]; | |
8307 | /* Array of alternatives, sorted in order of decreasing desirability. */ | |
8308 | int *alternative_order; | |
05d10675 | 8309 | |
0eadeb15 | 8310 | extract_insn (insn); |
e9a25f70 | 8311 | |
1ccbefce | 8312 | if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) |
1d300e19 | 8313 | return 0; |
e9a25f70 JL |
8314 | |
8315 | /* Figure out which alternative currently matches. */ | |
0eadeb15 | 8316 | if (! constrain_operands (1)) |
b8705408 | 8317 | fatal_insn_not_found (insn); |
1d7254c5 | 8318 | |
1ccbefce RH |
8319 | alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int)); |
8320 | alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int)); | |
8321 | alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int)); | |
8e2e89f7 KH |
8322 | memset ((char *) alternative_reject, 0, recog_data.n_alternatives * sizeof (int)); |
8323 | memset ((char *) alternative_nregs, 0, recog_data.n_alternatives * sizeof (int)); | |
e9a25f70 | 8324 | |
eab5c70a BS |
8325 | /* For each operand, find out which regs are equivalent. */ |
8326 | for (i = 0; i < recog_data.n_operands; i++) | |
8327 | { | |
8328 | cselib_val *v; | |
8329 | struct elt_loc_list *l; | |
8330 | ||
8331 | CLEAR_HARD_REG_SET (equiv_regs[i]); | |
8332 | ||
8333 | /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem | |
70bbeb8b BS |
8334 | right, so avoid the problem here. Likewise if we have a constant |
8335 | and the insn pattern doesn't tell us the mode we need. */ | |
8336 | if (GET_CODE (recog_data.operand[i]) == CODE_LABEL | |
8337 | || (CONSTANT_P (recog_data.operand[i]) | |
8338 | && recog_data.operand_mode[i] == VOIDmode)) | |
eab5c70a BS |
8339 | continue; |
8340 | ||
8341 | v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0); | |
8342 | if (! v) | |
8343 | continue; | |
8344 | ||
8345 | for (l = v->locs; l; l = l->next) | |
8346 | if (GET_CODE (l->loc) == REG) | |
8347 | SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); | |
8348 | } | |
8349 | ||
1ccbefce | 8350 | for (i = 0; i < recog_data.n_operands; i++) |
e9a25f70 JL |
8351 | { |
8352 | enum machine_mode mode; | |
8353 | int regno; | |
9b3142b3 | 8354 | const char *p; |
e9a25f70 | 8355 | |
1ccbefce RH |
8356 | op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int)); |
8357 | for (j = 0; j < recog_data.n_alternatives; j++) | |
e9a25f70 JL |
8358 | op_alt_regno[i][j] = -1; |
8359 | ||
1ccbefce RH |
8360 | p = constraints[i] = recog_data.constraints[i]; |
8361 | mode = recog_data.operand_mode[i]; | |
e9a25f70 JL |
8362 | |
8363 | /* Add the reject values for each alternative given by the constraints | |
8364 | for this operand. */ | |
8365 | j = 0; | |
8366 | while (*p != '\0') | |
8367 | { | |
8368 | char c = *p++; | |
8369 | if (c == ',') | |
8370 | j++; | |
8371 | else if (c == '?') | |
8372 | alternative_reject[j] += 3; | |
8373 | else if (c == '!') | |
8374 | alternative_reject[j] += 300; | |
8375 | } | |
8376 | ||
8377 | /* We won't change operands which are already registers. We | |
8378 | also don't want to modify output operands. */ | |
1ccbefce | 8379 | regno = true_regnum (recog_data.operand[i]); |
e9a25f70 JL |
8380 | if (regno >= 0 |
8381 | || constraints[i][0] == '=' | |
8382 | || constraints[i][0] == '+') | |
8383 | continue; | |
8384 | ||
8385 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
8386 | { | |
8387 | int class = (int) NO_REGS; | |
8388 | ||
eab5c70a | 8389 | if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) |
e9a25f70 JL |
8390 | continue; |
8391 | ||
bf1660a6 JL |
8392 | REGNO (testreg) = regno; |
8393 | PUT_MODE (testreg, mode); | |
0254c561 | 8394 | |
e9a25f70 JL |
8395 | /* We found a register equal to this operand. Now look for all |
8396 | alternatives that can accept this register and have not been | |
8397 | assigned a register they can use yet. */ | |
8398 | j = 0; | |
8399 | p = constraints[i]; | |
8400 | for (;;) | |
31418d35 | 8401 | { |
e9a25f70 | 8402 | char c = *p++; |
05d10675 | 8403 | |
e9a25f70 | 8404 | switch (c) |
31418d35 | 8405 | { |
e9a25f70 JL |
8406 | case '=': case '+': case '?': |
8407 | case '#': case '&': case '!': | |
05d10675 | 8408 | case '*': case '%': |
e9a25f70 | 8409 | case '0': case '1': case '2': case '3': case '4': |
c5c76735 | 8410 | case '5': case '6': case '7': case '8': case '9': |
e9a25f70 JL |
8411 | case 'm': case '<': case '>': case 'V': case 'o': |
8412 | case 'E': case 'F': case 'G': case 'H': | |
8413 | case 's': case 'i': case 'n': | |
8414 | case 'I': case 'J': case 'K': case 'L': | |
8415 | case 'M': case 'N': case 'O': case 'P': | |
e9a25f70 JL |
8416 | case 'p': case 'X': |
8417 | /* These don't say anything we care about. */ | |
8418 | break; | |
8419 | ||
8420 | case 'g': case 'r': | |
8421 | class = reg_class_subunion[(int) class][(int) GENERAL_REGS]; | |
8422 | break; | |
8423 | ||
8424 | default: | |
8425 | class | |
8e2e89f7 | 8426 | = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char) c)]; |
e9a25f70 | 8427 | break; |
31418d35 | 8428 | |
e9a25f70 JL |
8429 | case ',': case '\0': |
8430 | /* See if REGNO fits this alternative, and set it up as the | |
8431 | replacement register if we don't have one for this | |
0254c561 | 8432 | alternative yet and the operand being replaced is not |
1d7254c5 | 8433 | a cheap CONST_INT. */ |
e9a25f70 | 8434 | if (op_alt_regno[i][j] == -1 |
bf1660a6 | 8435 | && reg_fits_class_p (testreg, class, 0, mode) |
1ccbefce RH |
8436 | && (GET_CODE (recog_data.operand[i]) != CONST_INT |
8437 | || (rtx_cost (recog_data.operand[i], SET) | |
bf1660a6 | 8438 | > rtx_cost (testreg, SET)))) |
31418d35 | 8439 | { |
e9a25f70 JL |
8440 | alternative_nregs[j]++; |
8441 | op_alt_regno[i][j] = regno; | |
31418d35 | 8442 | } |
e9a25f70 JL |
8443 | j++; |
8444 | break; | |
31418d35 ILT |
8445 | } |
8446 | ||
e9a25f70 JL |
8447 | if (c == '\0') |
8448 | break; | |
8449 | } | |
8450 | } | |
8451 | } | |
8452 | ||
8453 | /* Record all alternatives which are better or equal to the currently | |
8454 | matching one in the alternative_order array. */ | |
1ccbefce | 8455 | for (i = j = 0; i < recog_data.n_alternatives; i++) |
e9a25f70 JL |
8456 | if (alternative_reject[i] <= alternative_reject[which_alternative]) |
8457 | alternative_order[j++] = i; | |
1ccbefce | 8458 | recog_data.n_alternatives = j; |
e9a25f70 JL |
8459 | |
8460 | /* Sort it. Given a small number of alternatives, a dumb algorithm | |
8461 | won't hurt too much. */ | |
1ccbefce | 8462 | for (i = 0; i < recog_data.n_alternatives - 1; i++) |
e9a25f70 JL |
8463 | { |
8464 | int best = i; | |
8465 | int best_reject = alternative_reject[alternative_order[i]]; | |
8466 | int best_nregs = alternative_nregs[alternative_order[i]]; | |
8467 | int tmp; | |
8468 | ||
1ccbefce | 8469 | for (j = i + 1; j < recog_data.n_alternatives; j++) |
e9a25f70 JL |
8470 | { |
8471 | int this_reject = alternative_reject[alternative_order[j]]; | |
8472 | int this_nregs = alternative_nregs[alternative_order[j]]; | |
8473 | ||
8474 | if (this_reject < best_reject | |
8475 | || (this_reject == best_reject && this_nregs < best_nregs)) | |
8476 | { | |
8477 | best = j; | |
8478 | best_reject = this_reject; | |
8479 | best_nregs = this_nregs; | |
31418d35 | 8480 | } |
2a9fb548 | 8481 | } |
05d10675 | 8482 | |
e9a25f70 JL |
8483 | tmp = alternative_order[best]; |
8484 | alternative_order[best] = alternative_order[i]; | |
8485 | alternative_order[i] = tmp; | |
8486 | } | |
05d10675 | 8487 | |
e9a25f70 JL |
8488 | /* Substitute the operands as determined by op_alt_regno for the best |
8489 | alternative. */ | |
8490 | j = alternative_order[0]; | |
e9a25f70 | 8491 | |
1ccbefce | 8492 | for (i = 0; i < recog_data.n_operands; i++) |
e9a25f70 | 8493 | { |
1ccbefce | 8494 | enum machine_mode mode = recog_data.operand_mode[i]; |
e9a25f70 JL |
8495 | if (op_alt_regno[i][j] == -1) |
8496 | continue; | |
8497 | ||
1ccbefce | 8498 | validate_change (insn, recog_data.operand_loc[i], |
38a448ca | 8499 | gen_rtx_REG (mode, op_alt_regno[i][j]), 1); |
e9a25f70 JL |
8500 | } |
8501 | ||
1ccbefce | 8502 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
e9a25f70 | 8503 | { |
1ccbefce RH |
8504 | int op = recog_data.dup_num[i]; |
8505 | enum machine_mode mode = recog_data.operand_mode[op]; | |
e9a25f70 JL |
8506 | |
8507 | if (op_alt_regno[op][j] == -1) | |
8508 | continue; | |
8509 | ||
1ccbefce | 8510 | validate_change (insn, recog_data.dup_loc[i], |
38a448ca | 8511 | gen_rtx_REG (mode, op_alt_regno[op][j]), 1); |
2a9fb548 | 8512 | } |
e9a25f70 | 8513 | |
e9a25f70 | 8514 | return apply_change_group (); |
2a9fb548 | 8515 | } |
5adf6da0 R |
8516 | \f |
8517 | /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg | |
8518 | addressing now. | |
8519 | This code might also be useful when reload gave up on reg+reg addresssing | |
8520 | because of clashes between the return register and INDEX_REG_CLASS. */ | |
8521 | ||
8522 | /* The maximum number of uses of a register we can keep track of to | |
8523 | replace them with reg+reg addressing. */ | |
8524 | #define RELOAD_COMBINE_MAX_USES 6 | |
8525 | ||
8526 | /* INSN is the insn where a register has ben used, and USEP points to the | |
8527 | location of the register within the rtl. */ | |
8528 | struct reg_use { rtx insn, *usep; }; | |
8529 | ||
8530 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | |
8531 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | |
8532 | indicates where it becomes live again. | |
8533 | Otherwise, USE_INDEX is the index of the last encountered use of the | |
8534 | register (which is first among these we have seen since we scan backwards), | |
8535 | OFFSET contains the constant offset that is added to the register in | |
8536 | all encountered uses, and USE_RUID indicates the first encountered, i.e. | |
ed937a19 R |
8537 | last, of these uses. |
8538 | STORE_RUID is always meaningful if we only want to use a value in a | |
8539 | register in a different place: it denotes the next insn in the insn | |
8540 | stream (i.e. the last ecountered) that sets or clobbers the register. */ | |
5adf6da0 R |
8541 | static struct |
8542 | { | |
8543 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | |
8544 | int use_index; | |
8545 | rtx offset; | |
8546 | int store_ruid; | |
8547 | int use_ruid; | |
8548 | } reg_state[FIRST_PSEUDO_REGISTER]; | |
8549 | ||
8550 | /* Reverse linear uid. This is increased in reload_combine while scanning | |
8551 | the instructions from last to first. It is used to set last_label_ruid | |
8552 | and the store_ruid / use_ruid fields in reg_state. */ | |
8553 | static int reload_combine_ruid; | |
8554 | ||
b0634509 R |
8555 | #define LABEL_LIVE(LABEL) \ |
8556 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | |
8557 | ||
5adf6da0 R |
8558 | static void |
8559 | reload_combine () | |
8560 | { | |
8561 | rtx insn, set; | |
ae0ed63a JM |
8562 | int first_index_reg = -1; |
8563 | int last_index_reg = 0; | |
5adf6da0 | 8564 | int i; |
e0082a72 | 8565 | basic_block bb; |
f8cd4126 | 8566 | unsigned int r; |
5adf6da0 | 8567 | int last_label_ruid; |
b0634509 R |
8568 | int min_labelno, n_labels; |
8569 | HARD_REG_SET ever_live_at_start, *label_live; | |
5adf6da0 | 8570 | |
f63d1bf7 | 8571 | /* If reg+reg can be used in offsetable memory addresses, the main chunk of |
5adf6da0 R |
8572 | reload has already used it where appropriate, so there is no use in |
8573 | trying to generate it now. */ | |
03acd8f8 | 8574 | if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS) |
5adf6da0 R |
8575 | return; |
8576 | ||
8577 | /* To avoid wasting too much time later searching for an index register, | |
8578 | determine the minimum and maximum index register numbers. */ | |
f8cd4126 RK |
8579 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
8580 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | |
8581 | { | |
881a8969 | 8582 | if (first_index_reg == -1) |
4c3f1588 RK |
8583 | first_index_reg = r; |
8584 | ||
8585 | last_index_reg = r; | |
f8cd4126 RK |
8586 | } |
8587 | ||
5adf6da0 | 8588 | /* If no index register is available, we can quit now. */ |
881a8969 | 8589 | if (first_index_reg == -1) |
5adf6da0 R |
8590 | return; |
8591 | ||
b0634509 R |
8592 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime |
8593 | information is a bit fuzzy immediately after reload, but it's | |
8594 | still good enough to determine which registers are live at a jump | |
8595 | destination. */ | |
8596 | min_labelno = get_first_label_num (); | |
8597 | n_labels = max_label_num () - min_labelno; | |
8598 | label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET)); | |
8599 | CLEAR_HARD_REG_SET (ever_live_at_start); | |
f8cd4126 | 8600 | |
e0082a72 | 8601 | FOR_EACH_BB_REVERSE (bb) |
b0634509 | 8602 | { |
e0082a72 | 8603 | insn = bb->head; |
b0634509 R |
8604 | if (GET_CODE (insn) == CODE_LABEL) |
8605 | { | |
8606 | HARD_REG_SET live; | |
8607 | ||
f8cd4126 | 8608 | REG_SET_TO_HARD_REG_SET (live, |
e0082a72 | 8609 | bb->global_live_at_start); |
f8cd4126 | 8610 | compute_use_by_pseudos (&live, |
e0082a72 | 8611 | bb->global_live_at_start); |
b0634509 R |
8612 | COPY_HARD_REG_SET (LABEL_LIVE (insn), live); |
8613 | IOR_HARD_REG_SET (ever_live_at_start, live); | |
8614 | } | |
8615 | } | |
8616 | ||
5adf6da0 R |
8617 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ |
8618 | last_label_ruid = reload_combine_ruid = 0; | |
f8cd4126 | 8619 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
5adf6da0 | 8620 | { |
f8cd4126 RK |
8621 | reg_state[r].store_ruid = reload_combine_ruid; |
8622 | if (fixed_regs[r]) | |
8623 | reg_state[r].use_index = -1; | |
5adf6da0 | 8624 | else |
f8cd4126 | 8625 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; |
5adf6da0 R |
8626 | } |
8627 | ||
8628 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
8629 | { | |
8630 | rtx note; | |
8631 | ||
8632 | /* We cannot do our optimization across labels. Invalidating all the use | |
8633 | information we have would be costly, so we just note where the label | |
05d10675 | 8634 | is and then later disable any optimization that would cross it. */ |
5adf6da0 R |
8635 | if (GET_CODE (insn) == CODE_LABEL) |
8636 | last_label_ruid = reload_combine_ruid; | |
f8cd4126 RK |
8637 | else if (GET_CODE (insn) == BARRIER) |
8638 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
8639 | if (! fixed_regs[r]) | |
8640 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
8641 | ||
2c3c49de | 8642 | if (! INSN_P (insn)) |
5adf6da0 | 8643 | continue; |
f8cd4126 | 8644 | |
5adf6da0 R |
8645 | reload_combine_ruid++; |
8646 | ||
8647 | /* Look for (set (REGX) (CONST_INT)) | |
eceef4c9 BS |
8648 | (set (REGX) (PLUS (REGX) (REGY))) |
8649 | ... | |
8650 | ... (MEM (REGX)) ... | |
5adf6da0 | 8651 | and convert it to |
eceef4c9 BS |
8652 | (set (REGZ) (CONST_INT)) |
8653 | ... | |
8654 | ... (MEM (PLUS (REGZ) (REGY)))... . | |
5adf6da0 R |
8655 | |
8656 | First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | |
8657 | and that we know all uses of REGX before it dies. */ | |
2abbc1bd R |
8658 | set = single_set (insn); |
8659 | if (set != NULL_RTX | |
5adf6da0 R |
8660 | && GET_CODE (SET_DEST (set)) == REG |
8661 | && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)), | |
8662 | GET_MODE (SET_DEST (set))) | |
8663 | == 1) | |
8664 | && GET_CODE (SET_SRC (set)) == PLUS | |
8665 | && GET_CODE (XEXP (SET_SRC (set), 1)) == REG | |
8666 | && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set)) | |
8667 | && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid) | |
8668 | { | |
8669 | rtx reg = SET_DEST (set); | |
8670 | rtx plus = SET_SRC (set); | |
8671 | rtx base = XEXP (plus, 1); | |
8672 | rtx prev = prev_nonnote_insn (insn); | |
8673 | rtx prev_set = prev ? single_set (prev) : NULL_RTX; | |
f8cd4126 | 8674 | unsigned int regno = REGNO (reg); |
6a651371 | 8675 | rtx const_reg = NULL_RTX; |
5adf6da0 R |
8676 | rtx reg_sum = NULL_RTX; |
8677 | ||
8678 | /* Now, we need an index register. | |
8679 | We'll set index_reg to this index register, const_reg to the | |
8680 | register that is to be loaded with the constant | |
8681 | (denoted as REGZ in the substitution illustration above), | |
8682 | and reg_sum to the register-register that we want to use to | |
8683 | substitute uses of REG (typically in MEMs) with. | |
8684 | First check REG and BASE for being index registers; | |
8685 | we can use them even if they are not dead. */ | |
8686 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | |
8687 | || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | |
8688 | REGNO (base))) | |
8689 | { | |
8690 | const_reg = reg; | |
8691 | reg_sum = plus; | |
8692 | } | |
8693 | else | |
8694 | { | |
05d10675 BS |
8695 | /* Otherwise, look for a free index register. Since we have |
8696 | checked above that neiter REG nor BASE are index registers, | |
8697 | if we find anything at all, it will be different from these | |
8698 | two registers. */ | |
8699 | for (i = first_index_reg; i <= last_index_reg; i++) | |
5adf6da0 | 8700 | { |
f8cd4126 RK |
8701 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], |
8702 | i) | |
5adf6da0 R |
8703 | && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES |
8704 | && reg_state[i].store_ruid <= reg_state[regno].use_ruid | |
8705 | && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1) | |
8706 | { | |
8707 | rtx index_reg = gen_rtx_REG (GET_MODE (reg), i); | |
f8cd4126 | 8708 | |
5adf6da0 R |
8709 | const_reg = index_reg; |
8710 | reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | |
8711 | break; | |
8712 | } | |
8713 | } | |
8714 | } | |
f8cd4126 | 8715 | |
ed937a19 R |
8716 | /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that |
8717 | (REGY), i.e. BASE, is not clobbered before the last use we'll | |
8718 | create. */ | |
f8cd4126 | 8719 | if (prev_set != 0 |
5adf6da0 R |
8720 | && GET_CODE (SET_SRC (prev_set)) == CONST_INT |
8721 | && rtx_equal_p (SET_DEST (prev_set), reg) | |
8722 | && reg_state[regno].use_index >= 0 | |
f8cd4126 RK |
8723 | && (reg_state[REGNO (base)].store_ruid |
8724 | <= reg_state[regno].use_ruid) | |
8725 | && reg_sum != 0) | |
5adf6da0 R |
8726 | { |
8727 | int i; | |
8728 | ||
f8cd4126 | 8729 | /* Change destination register and, if necessary, the |
5adf6da0 R |
8730 | constant value in PREV, the constant loading instruction. */ |
8731 | validate_change (prev, &SET_DEST (prev_set), const_reg, 1); | |
8732 | if (reg_state[regno].offset != const0_rtx) | |
8733 | validate_change (prev, | |
8734 | &SET_SRC (prev_set), | |
8735 | GEN_INT (INTVAL (SET_SRC (prev_set)) | |
8736 | + INTVAL (reg_state[regno].offset)), | |
8737 | 1); | |
f8cd4126 | 8738 | |
5adf6da0 R |
8739 | /* Now for every use of REG that we have recorded, replace REG |
8740 | with REG_SUM. */ | |
8741 | for (i = reg_state[regno].use_index; | |
8742 | i < RELOAD_COMBINE_MAX_USES; i++) | |
8743 | validate_change (reg_state[regno].reg_use[i].insn, | |
8744 | reg_state[regno].reg_use[i].usep, | |
d300f51f HPN |
8745 | /* Each change must have its own |
8746 | replacement. */ | |
8747 | copy_rtx (reg_sum), 1); | |
5adf6da0 R |
8748 | |
8749 | if (apply_change_group ()) | |
8750 | { | |
8751 | rtx *np; | |
8752 | ||
8753 | /* Delete the reg-reg addition. */ | |
ca6c03ca | 8754 | delete_insn (insn); |
5adf6da0 R |
8755 | |
8756 | if (reg_state[regno].offset != const0_rtx) | |
f8cd4126 RK |
8757 | /* Previous REG_EQUIV / REG_EQUAL notes for PREV |
8758 | are now invalid. */ | |
1d7254c5 | 8759 | for (np = ®_NOTES (prev); *np;) |
f8cd4126 RK |
8760 | { |
8761 | if (REG_NOTE_KIND (*np) == REG_EQUAL | |
8762 | || REG_NOTE_KIND (*np) == REG_EQUIV) | |
8763 | *np = XEXP (*np, 1); | |
8764 | else | |
8765 | np = &XEXP (*np, 1); | |
8766 | } | |
8767 | ||
5adf6da0 | 8768 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; |
f8cd4126 RK |
8769 | reg_state[REGNO (const_reg)].store_ruid |
8770 | = reload_combine_ruid; | |
5adf6da0 R |
8771 | continue; |
8772 | } | |
8773 | } | |
8774 | } | |
f8cd4126 | 8775 | |
1d7254c5 | 8776 | note_stores (PATTERN (insn), reload_combine_note_store, NULL); |
f8cd4126 | 8777 | |
5adf6da0 R |
8778 | if (GET_CODE (insn) == CALL_INSN) |
8779 | { | |
8780 | rtx link; | |
8781 | ||
f8cd4126 RK |
8782 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
8783 | if (call_used_regs[r]) | |
8784 | { | |
8785 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
8786 | reg_state[r].store_ruid = reload_combine_ruid; | |
8787 | } | |
8788 | ||
5adf6da0 R |
8789 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; |
8790 | link = XEXP (link, 1)) | |
6a69653a CM |
8791 | { |
8792 | rtx usage_rtx = XEXP (XEXP (link, 0), 0); | |
8793 | if (GET_CODE (usage_rtx) == REG) | |
8794 | { | |
ae0ed63a | 8795 | unsigned int i; |
6a69653a CM |
8796 | unsigned int start_reg = REGNO (usage_rtx); |
8797 | unsigned int num_regs = | |
8798 | HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx)); | |
8799 | unsigned int end_reg = start_reg + num_regs - 1; | |
8800 | for (i = start_reg; i <= end_reg; i++) | |
8801 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
8802 | { | |
8803 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
8804 | reg_state[i].store_ruid = reload_combine_ruid; | |
8805 | } | |
8806 | else | |
8807 | reg_state[i].use_index = -1; | |
8808 | } | |
8809 | } | |
f8cd4126 | 8810 | |
5adf6da0 | 8811 | } |
f8cd4126 RK |
8812 | else if (GET_CODE (insn) == JUMP_INSN |
8813 | && GET_CODE (PATTERN (insn)) != RETURN) | |
5adf6da0 R |
8814 | { |
8815 | /* Non-spill registers might be used at the call destination in | |
8816 | some unknown fashion, so we have to mark the unknown use. */ | |
b0634509 | 8817 | HARD_REG_SET *live; |
f8cd4126 | 8818 | |
b0634509 R |
8819 | if ((condjump_p (insn) || condjump_in_parallel_p (insn)) |
8820 | && JUMP_LABEL (insn)) | |
8821 | live = &LABEL_LIVE (JUMP_LABEL (insn)); | |
8822 | else | |
8823 | live = &ever_live_at_start; | |
f8cd4126 | 8824 | |
5adf6da0 | 8825 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) |
f8cd4126 RK |
8826 | if (TEST_HARD_REG_BIT (*live, i)) |
8827 | reg_state[i].use_index = -1; | |
5adf6da0 | 8828 | } |
f8cd4126 | 8829 | |
5adf6da0 R |
8830 | reload_combine_note_use (&PATTERN (insn), insn); |
8831 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
8832 | { | |
8833 | if (REG_NOTE_KIND (note) == REG_INC | |
8834 | && GET_CODE (XEXP (note, 0)) == REG) | |
ed937a19 R |
8835 | { |
8836 | int regno = REGNO (XEXP (note, 0)); | |
8837 | ||
8838 | reg_state[regno].store_ruid = reload_combine_ruid; | |
8839 | reg_state[regno].use_index = -1; | |
8840 | } | |
5adf6da0 R |
8841 | } |
8842 | } | |
f8cd4126 | 8843 | |
b0634509 | 8844 | free (label_live); |
5adf6da0 R |
8845 | } |
8846 | ||
8847 | /* Check if DST is a register or a subreg of a register; if it is, | |
8848 | update reg_state[regno].store_ruid and reg_state[regno].use_index | |
f93233bb | 8849 | accordingly. Called via note_stores from reload_combine. */ |
f8cd4126 | 8850 | |
5adf6da0 | 8851 | static void |
84832317 | 8852 | reload_combine_note_store (dst, set, data) |
f93233bb | 8853 | rtx dst, set; |
84832317 | 8854 | void *data ATTRIBUTE_UNUSED; |
5adf6da0 R |
8855 | { |
8856 | int regno = 0; | |
8857 | int i; | |
54ed0905 | 8858 | enum machine_mode mode = GET_MODE (dst); |
5adf6da0 R |
8859 | |
8860 | if (GET_CODE (dst) == SUBREG) | |
8861 | { | |
ddef6bc7 JJ |
8862 | regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), |
8863 | GET_MODE (SUBREG_REG (dst)), | |
8864 | SUBREG_BYTE (dst), | |
8865 | GET_MODE (dst)); | |
5adf6da0 R |
8866 | dst = SUBREG_REG (dst); |
8867 | } | |
8868 | if (GET_CODE (dst) != REG) | |
8869 | return; | |
8870 | regno += REGNO (dst); | |
54ca6ffa | 8871 | |
5adf6da0 | 8872 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be |
05d10675 | 8873 | careful with registers / register parts that are not full words. |
54ca6ffa JL |
8874 | |
8875 | Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */ | |
8876 | if (GET_CODE (set) != SET | |
8877 | || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT | |
8878 | || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT | |
8879 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) | |
ed937a19 | 8880 | { |
54ed0905 | 8881 | for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--) |
f93233bb JL |
8882 | { |
8883 | reg_state[i].use_index = -1; | |
8884 | reg_state[i].store_ruid = reload_combine_ruid; | |
8885 | } | |
ed937a19 | 8886 | } |
5adf6da0 R |
8887 | else |
8888 | { | |
54ed0905 | 8889 | for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--) |
5adf6da0 R |
8890 | { |
8891 | reg_state[i].store_ruid = reload_combine_ruid; | |
8892 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
8893 | } | |
8894 | } | |
8895 | } | |
8896 | ||
8897 | /* XP points to a piece of rtl that has to be checked for any uses of | |
8898 | registers. | |
8899 | *XP is the pattern of INSN, or a part of it. | |
8900 | Called from reload_combine, and recursively by itself. */ | |
8901 | static void | |
8902 | reload_combine_note_use (xp, insn) | |
8903 | rtx *xp, insn; | |
8904 | { | |
8905 | rtx x = *xp; | |
8906 | enum rtx_code code = x->code; | |
6f7d635c | 8907 | const char *fmt; |
5adf6da0 R |
8908 | int i, j; |
8909 | rtx offset = const0_rtx; /* For the REG case below. */ | |
8910 | ||
8911 | switch (code) | |
8912 | { | |
8913 | case SET: | |
8914 | if (GET_CODE (SET_DEST (x)) == REG) | |
8915 | { | |
8916 | reload_combine_note_use (&SET_SRC (x), insn); | |
8917 | return; | |
8918 | } | |
8919 | break; | |
8920 | ||
6ce7e0f9 R |
8921 | case USE: |
8922 | /* If this is the USE of a return value, we can't change it. */ | |
8923 | if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0))) | |
8924 | { | |
8925 | /* Mark the return register as used in an unknown fashion. */ | |
8926 | rtx reg = XEXP (x, 0); | |
8927 | int regno = REGNO (reg); | |
8928 | int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
8929 | ||
8930 | while (--nregs >= 0) | |
8931 | reg_state[regno + nregs].use_index = -1; | |
8932 | return; | |
8933 | } | |
8934 | break; | |
8935 | ||
5adf6da0 R |
8936 | case CLOBBER: |
8937 | if (GET_CODE (SET_DEST (x)) == REG) | |
3d17d93d AO |
8938 | { |
8939 | /* No spurious CLOBBERs of pseudo registers may remain. */ | |
8940 | if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER) | |
8941 | abort (); | |
8942 | return; | |
8943 | } | |
5adf6da0 R |
8944 | break; |
8945 | ||
8946 | case PLUS: | |
8947 | /* We are interested in (plus (reg) (const_int)) . */ | |
1d7254c5 KH |
8948 | if (GET_CODE (XEXP (x, 0)) != REG |
8949 | || GET_CODE (XEXP (x, 1)) != CONST_INT) | |
5adf6da0 R |
8950 | break; |
8951 | offset = XEXP (x, 1); | |
8952 | x = XEXP (x, 0); | |
05d10675 | 8953 | /* Fall through. */ |
5adf6da0 R |
8954 | case REG: |
8955 | { | |
8956 | int regno = REGNO (x); | |
8957 | int use_index; | |
6ce7e0f9 | 8958 | int nregs; |
5adf6da0 | 8959 | |
3d17d93d | 8960 | /* No spurious USEs of pseudo registers may remain. */ |
5adf6da0 | 8961 | if (regno >= FIRST_PSEUDO_REGISTER) |
3d17d93d | 8962 | abort (); |
5adf6da0 | 8963 | |
6ce7e0f9 R |
8964 | nregs = HARD_REGNO_NREGS (regno, GET_MODE (x)); |
8965 | ||
8966 | /* We can't substitute into multi-hard-reg uses. */ | |
8967 | if (nregs > 1) | |
8968 | { | |
8969 | while (--nregs >= 0) | |
8970 | reg_state[regno + nregs].use_index = -1; | |
8971 | return; | |
8972 | } | |
8973 | ||
5adf6da0 R |
8974 | /* If this register is already used in some unknown fashion, we |
8975 | can't do anything. | |
8976 | If we decrement the index from zero to -1, we can't store more | |
8977 | uses, so this register becomes used in an unknown fashion. */ | |
8978 | use_index = --reg_state[regno].use_index; | |
8979 | if (use_index < 0) | |
8980 | return; | |
8981 | ||
8982 | if (use_index != RELOAD_COMBINE_MAX_USES - 1) | |
8983 | { | |
8984 | /* We have found another use for a register that is already | |
8985 | used later. Check if the offsets match; if not, mark the | |
8986 | register as used in an unknown fashion. */ | |
8987 | if (! rtx_equal_p (offset, reg_state[regno].offset)) | |
8988 | { | |
8989 | reg_state[regno].use_index = -1; | |
8990 | return; | |
8991 | } | |
8992 | } | |
8993 | else | |
8994 | { | |
8995 | /* This is the first use of this register we have seen since we | |
8996 | marked it as dead. */ | |
8997 | reg_state[regno].offset = offset; | |
8998 | reg_state[regno].use_ruid = reload_combine_ruid; | |
8999 | } | |
9000 | reg_state[regno].reg_use[use_index].insn = insn; | |
9001 | reg_state[regno].reg_use[use_index].usep = xp; | |
9002 | return; | |
9003 | } | |
9004 | ||
9005 | default: | |
9006 | break; | |
9007 | } | |
9008 | ||
9009 | /* Recursively process the components of X. */ | |
9010 | fmt = GET_RTX_FORMAT (code); | |
9011 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
9012 | { | |
9013 | if (fmt[i] == 'e') | |
9014 | reload_combine_note_use (&XEXP (x, i), insn); | |
9015 | else if (fmt[i] == 'E') | |
9016 | { | |
9017 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9018 | reload_combine_note_use (&XVECEXP (x, i, j), insn); | |
9019 | } | |
9020 | } | |
9021 | } | |
9022 | \f | |
61f5625b AO |
9023 | /* See if we can reduce the cost of a constant by replacing a move |
9024 | with an add. We track situations in which a register is set to a | |
9025 | constant or to a register plus a constant. */ | |
5adf6da0 R |
9026 | /* We cannot do our optimization across labels. Invalidating all the |
9027 | information about register contents we have would be costly, so we | |
61f5625b AO |
9028 | use move2add_last_label_luid to note where the label is and then |
9029 | later disable any optimization that would cross it. | |
5adf6da0 | 9030 | reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if |
61f5625b | 9031 | reg_set_luid[n] is greater than last_label_luid[n] . */ |
5adf6da0 | 9032 | static int reg_set_luid[FIRST_PSEUDO_REGISTER]; |
770ae6cc | 9033 | |
61f5625b AO |
9034 | /* If reg_base_reg[n] is negative, register n has been set to |
9035 | reg_offset[n] in mode reg_mode[n] . | |
9036 | If reg_base_reg[n] is non-negative, register n has been set to the | |
9037 | sum of reg_offset[n] and the value of register reg_base_reg[n] | |
dc297297 | 9038 | before reg_set_luid[n], calculated in mode reg_mode[n] . */ |
61f5625b | 9039 | static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; |
5adf6da0 R |
9040 | static int reg_base_reg[FIRST_PSEUDO_REGISTER]; |
9041 | static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; | |
770ae6cc | 9042 | |
5adf6da0 R |
9043 | /* move2add_luid is linearily increased while scanning the instructions |
9044 | from first to last. It is used to set reg_set_luid in | |
6764d250 | 9045 | reload_cse_move2add and move2add_note_store. */ |
5adf6da0 R |
9046 | static int move2add_luid; |
9047 | ||
61f5625b AO |
9048 | /* move2add_last_label_luid is set whenever a label is found. Labels |
9049 | invalidate all previously collected reg_offset data. */ | |
9050 | static int move2add_last_label_luid; | |
9051 | ||
ccc4ae07 | 9052 | /* Generate a CONST_INT and force it in the range of MODE. */ |
770ae6cc | 9053 | |
61f5625b AO |
9054 | static HOST_WIDE_INT |
9055 | sext_for_mode (mode, value) | |
ccc4ae07 AS |
9056 | enum machine_mode mode; |
9057 | HOST_WIDE_INT value; | |
9058 | { | |
9059 | HOST_WIDE_INT cval = value & GET_MODE_MASK (mode); | |
9060 | int width = GET_MODE_BITSIZE (mode); | |
9061 | ||
9062 | /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number, | |
9063 | sign extend it. */ | |
9064 | if (width > 0 && width < HOST_BITS_PER_WIDE_INT | |
9065 | && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
9066 | cval |= (HOST_WIDE_INT) -1 << width; | |
9067 | ||
61f5625b | 9068 | return cval; |
ccc4ae07 AS |
9069 | } |
9070 | ||
61f5625b AO |
9071 | /* ??? We don't know how zero / sign extension is handled, hence we |
9072 | can't go from a narrower to a wider mode. */ | |
9073 | #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \ | |
9074 | (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \ | |
9075 | || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \ | |
9076 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \ | |
9077 | GET_MODE_BITSIZE (INMODE)))) | |
9078 | ||
5adf6da0 R |
9079 | static void |
9080 | reload_cse_move2add (first) | |
9081 | rtx first; | |
9082 | { | |
9083 | int i; | |
9084 | rtx insn; | |
5adf6da0 | 9085 | |
1d7254c5 | 9086 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) |
6764d250 BS |
9087 | reg_set_luid[i] = 0; |
9088 | ||
61f5625b AO |
9089 | move2add_last_label_luid = 0; |
9090 | move2add_luid = 2; | |
5adf6da0 R |
9091 | for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) |
9092 | { | |
9093 | rtx pat, note; | |
9094 | ||
9095 | if (GET_CODE (insn) == CODE_LABEL) | |
61f5625b AO |
9096 | { |
9097 | move2add_last_label_luid = move2add_luid; | |
9098 | /* We're going to increment move2add_luid twice after a | |
9099 | label, so that we can use move2add_last_label_luid + 1 as | |
9100 | the luid for constants. */ | |
9101 | move2add_luid++; | |
9102 | continue; | |
9103 | } | |
2c3c49de | 9104 | if (! INSN_P (insn)) |
5adf6da0 R |
9105 | continue; |
9106 | pat = PATTERN (insn); | |
9107 | /* For simplicity, we only perform this optimization on | |
9108 | straightforward SETs. */ | |
9109 | if (GET_CODE (pat) == SET | |
9110 | && GET_CODE (SET_DEST (pat)) == REG) | |
9111 | { | |
9112 | rtx reg = SET_DEST (pat); | |
9113 | int regno = REGNO (reg); | |
9114 | rtx src = SET_SRC (pat); | |
9115 | ||
9116 | /* Check if we have valid information on the contents of this | |
9117 | register in the mode of REG. */ | |
61f5625b AO |
9118 | if (reg_set_luid[regno] > move2add_last_label_luid |
9119 | && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])) | |
5adf6da0 R |
9120 | { |
9121 | /* Try to transform (set (REGX) (CONST_INT A)) | |
9122 | ... | |
9123 | (set (REGX) (CONST_INT B)) | |
9124 | to | |
9125 | (set (REGX) (CONST_INT A)) | |
9126 | ... | |
9127 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
9128 | ||
9129 | if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0) | |
9130 | { | |
9131 | int success = 0; | |
61f5625b AO |
9132 | rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg), |
9133 | INTVAL (src) | |
9134 | - reg_offset[regno])); | |
5adf6da0 R |
9135 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; |
9136 | use (set (reg) (reg)) instead. | |
9137 | We don't delete this insn, nor do we convert it into a | |
9138 | note, to avoid losing register notes or the return | |
9139 | value flag. jump2 already knowns how to get rid of | |
9140 | no-op moves. */ | |
9141 | if (new_src == const0_rtx) | |
9142 | success = validate_change (insn, &SET_SRC (pat), reg, 0); | |
9143 | else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET) | |
fb7e77d7 | 9144 | && have_add2_insn (reg, new_src)) |
5adf6da0 R |
9145 | success = validate_change (insn, &PATTERN (insn), |
9146 | gen_add2_insn (reg, new_src), 0); | |
5adf6da0 R |
9147 | reg_set_luid[regno] = move2add_luid; |
9148 | reg_mode[regno] = GET_MODE (reg); | |
61f5625b | 9149 | reg_offset[regno] = INTVAL (src); |
5adf6da0 R |
9150 | continue; |
9151 | } | |
9152 | ||
9153 | /* Try to transform (set (REGX) (REGY)) | |
9154 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
9155 | ... | |
9156 | (set (REGX) (REGY)) | |
9157 | (set (REGX) (PLUS (REGX) (CONST_INT B))) | |
9158 | to | |
9159 | (REGX) (REGY)) | |
9160 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
9161 | ... | |
9162 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
9163 | else if (GET_CODE (src) == REG | |
61f5625b AO |
9164 | && reg_set_luid[regno] == reg_set_luid[REGNO (src)] |
9165 | && reg_base_reg[regno] == reg_base_reg[REGNO (src)] | |
9166 | && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), | |
9167 | reg_mode[REGNO (src)])) | |
5adf6da0 R |
9168 | { |
9169 | rtx next = next_nonnote_insn (insn); | |
6a651371 | 9170 | rtx set = NULL_RTX; |
5adf6da0 R |
9171 | if (next) |
9172 | set = single_set (next); | |
61f5625b | 9173 | if (set |
5adf6da0 R |
9174 | && SET_DEST (set) == reg |
9175 | && GET_CODE (SET_SRC (set)) == PLUS | |
9176 | && XEXP (SET_SRC (set), 0) == reg | |
9177 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) | |
9178 | { | |
5adf6da0 | 9179 | rtx src3 = XEXP (SET_SRC (set), 1); |
61f5625b AO |
9180 | HOST_WIDE_INT added_offset = INTVAL (src3); |
9181 | HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; | |
9182 | HOST_WIDE_INT regno_offset = reg_offset[regno]; | |
9183 | rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg), | |
9184 | added_offset | |
9185 | + base_offset | |
9186 | - regno_offset)); | |
5adf6da0 R |
9187 | int success = 0; |
9188 | ||
9189 | if (new_src == const0_rtx) | |
9190 | /* See above why we create (set (reg) (reg)) here. */ | |
9191 | success | |
9192 | = validate_change (next, &SET_SRC (set), reg, 0); | |
9193 | else if ((rtx_cost (new_src, PLUS) | |
b437f1a7 | 9194 | < COSTS_N_INSNS (1) + rtx_cost (src3, SET)) |
fb7e77d7 | 9195 | && have_add2_insn (reg, new_src)) |
5adf6da0 R |
9196 | success |
9197 | = validate_change (next, &PATTERN (next), | |
9198 | gen_add2_insn (reg, new_src), 0); | |
9199 | if (success) | |
ca6c03ca | 9200 | delete_insn (insn); |
5adf6da0 | 9201 | insn = next; |
5adf6da0 | 9202 | reg_mode[regno] = GET_MODE (reg); |
61f5625b AO |
9203 | reg_offset[regno] = sext_for_mode (GET_MODE (reg), |
9204 | added_offset | |
9205 | + base_offset); | |
5adf6da0 R |
9206 | continue; |
9207 | } | |
9208 | } | |
9209 | } | |
9210 | } | |
9211 | ||
9212 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
9213 | { | |
9214 | if (REG_NOTE_KIND (note) == REG_INC | |
9215 | && GET_CODE (XEXP (note, 0)) == REG) | |
9216 | { | |
61f5625b | 9217 | /* Reset the information about this register. */ |
5adf6da0 R |
9218 | int regno = REGNO (XEXP (note, 0)); |
9219 | if (regno < FIRST_PSEUDO_REGISTER) | |
61f5625b | 9220 | reg_set_luid[regno] = 0; |
5adf6da0 | 9221 | } |
5adf6da0 | 9222 | } |
84832317 | 9223 | note_stores (PATTERN (insn), move2add_note_store, NULL); |
5adf6da0 R |
9224 | /* If this is a CALL_INSN, all call used registers are stored with |
9225 | unknown values. */ | |
9226 | if (GET_CODE (insn) == CALL_INSN) | |
9227 | { | |
1d7254c5 | 9228 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) |
5adf6da0 R |
9229 | { |
9230 | if (call_used_regs[i]) | |
61f5625b AO |
9231 | /* Reset the information about this register. */ |
9232 | reg_set_luid[i] = 0; | |
5adf6da0 R |
9233 | } |
9234 | } | |
9235 | } | |
9236 | } | |
9237 | ||
9238 | /* SET is a SET or CLOBBER that sets DST. | |
9239 | Update reg_set_luid, reg_offset and reg_base_reg accordingly. | |
9240 | Called from reload_cse_move2add via note_stores. */ | |
770ae6cc | 9241 | |
5adf6da0 | 9242 | static void |
84832317 | 9243 | move2add_note_store (dst, set, data) |
5adf6da0 | 9244 | rtx dst, set; |
84832317 | 9245 | void *data ATTRIBUTE_UNUSED; |
5adf6da0 | 9246 | { |
770ae6cc RK |
9247 | unsigned int regno = 0; |
9248 | unsigned int i; | |
5adf6da0 | 9249 | enum machine_mode mode = GET_MODE (dst); |
770ae6cc | 9250 | |
5adf6da0 R |
9251 | if (GET_CODE (dst) == SUBREG) |
9252 | { | |
ddef6bc7 JJ |
9253 | regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), |
9254 | GET_MODE (SUBREG_REG (dst)), | |
9255 | SUBREG_BYTE (dst), | |
9256 | GET_MODE (dst)); | |
5adf6da0 R |
9257 | dst = SUBREG_REG (dst); |
9258 | } | |
770ae6cc | 9259 | |
19ca869b JR |
9260 | /* Some targets do argument pushes without adding REG_INC notes. */ |
9261 | ||
9262 | if (GET_CODE (dst) == MEM) | |
9263 | { | |
9264 | dst = XEXP (dst, 0); | |
52fdbf26 | 9265 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC |
19ca869b | 9266 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC) |
61f5625b | 9267 | reg_set_luid[REGNO (XEXP (dst, 0))] = 0; |
19ca869b | 9268 | return; |
174fa2c4 | 9269 | } |
5adf6da0 R |
9270 | if (GET_CODE (dst) != REG) |
9271 | return; | |
9272 | ||
9273 | regno += REGNO (dst); | |
9274 | ||
f93233bb JL |
9275 | if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET |
9276 | && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT | |
9277 | && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT | |
9278 | && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) | |
5adf6da0 R |
9279 | { |
9280 | rtx src = SET_SRC (set); | |
61f5625b AO |
9281 | rtx base_reg; |
9282 | HOST_WIDE_INT offset; | |
9283 | int base_regno; | |
9284 | /* This may be different from mode, if SET_DEST (set) is a | |
9285 | SUBREG. */ | |
9286 | enum machine_mode dst_mode = GET_MODE (dst); | |
5adf6da0 | 9287 | |
5adf6da0 R |
9288 | switch (GET_CODE (src)) |
9289 | { | |
9290 | case PLUS: | |
61f5625b AO |
9291 | if (GET_CODE (XEXP (src, 0)) == REG) |
9292 | { | |
9293 | base_reg = XEXP (src, 0); | |
9294 | ||
9295 | if (GET_CODE (XEXP (src, 1)) == CONST_INT) | |
9296 | offset = INTVAL (XEXP (src, 1)); | |
9297 | else if (GET_CODE (XEXP (src, 1)) == REG | |
9298 | && (reg_set_luid[REGNO (XEXP (src, 1))] | |
9299 | > move2add_last_label_luid) | |
9300 | && (MODES_OK_FOR_MOVE2ADD | |
9301 | (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))) | |
9302 | { | |
9303 | if (reg_base_reg[REGNO (XEXP (src, 1))] < 0) | |
9304 | offset = reg_offset[REGNO (XEXP (src, 1))]; | |
9305 | /* Maybe the first register is known to be a | |
9306 | constant. */ | |
9307 | else if (reg_set_luid[REGNO (base_reg)] | |
9308 | > move2add_last_label_luid | |
9309 | && (MODES_OK_FOR_MOVE2ADD | |
9310 | (dst_mode, reg_mode[REGNO (XEXP (src, 1))])) | |
9311 | && reg_base_reg[REGNO (base_reg)] < 0) | |
9312 | { | |
9313 | offset = reg_offset[REGNO (base_reg)]; | |
9314 | base_reg = XEXP (src, 1); | |
9315 | } | |
9316 | else | |
9317 | goto invalidate; | |
9318 | } | |
9319 | else | |
9320 | goto invalidate; | |
770ae6cc | 9321 | |
61f5625b AO |
9322 | break; |
9323 | } | |
770ae6cc | 9324 | |
61f5625b | 9325 | goto invalidate; |
5adf6da0 R |
9326 | |
9327 | case REG: | |
61f5625b AO |
9328 | base_reg = src; |
9329 | offset = 0; | |
5adf6da0 R |
9330 | break; |
9331 | ||
61f5625b AO |
9332 | case CONST_INT: |
9333 | /* Start tracking the register as a constant. */ | |
5adf6da0 | 9334 | reg_base_reg[regno] = -1; |
61f5625b AO |
9335 | reg_offset[regno] = INTVAL (SET_SRC (set)); |
9336 | /* We assign the same luid to all registers set to constants. */ | |
9337 | reg_set_luid[regno] = move2add_last_label_luid + 1; | |
9338 | reg_mode[regno] = mode; | |
9339 | return; | |
a6a2274a | 9340 | |
61f5625b AO |
9341 | default: |
9342 | invalidate: | |
9343 | /* Invalidate the contents of the register. */ | |
9344 | reg_set_luid[regno] = 0; | |
9345 | return; | |
5adf6da0 | 9346 | } |
61f5625b AO |
9347 | |
9348 | base_regno = REGNO (base_reg); | |
9349 | /* If information about the base register is not valid, set it | |
9350 | up as a new base register, pretending its value is known | |
9351 | starting from the current insn. */ | |
9352 | if (reg_set_luid[base_regno] <= move2add_last_label_luid) | |
9353 | { | |
9354 | reg_base_reg[base_regno] = base_regno; | |
9355 | reg_offset[base_regno] = 0; | |
9356 | reg_set_luid[base_regno] = move2add_luid; | |
9357 | reg_mode[base_regno] = mode; | |
9358 | } | |
9359 | else if (! MODES_OK_FOR_MOVE2ADD (dst_mode, | |
9360 | reg_mode[base_regno])) | |
9361 | goto invalidate; | |
9362 | ||
9363 | reg_mode[regno] = mode; | |
9364 | ||
9365 | /* Copy base information from our base register. */ | |
9366 | reg_set_luid[regno] = reg_set_luid[base_regno]; | |
9367 | reg_base_reg[regno] = reg_base_reg[base_regno]; | |
9368 | ||
9369 | /* Compute the sum of the offsets or constants. */ | |
9370 | reg_offset[regno] = sext_for_mode (dst_mode, | |
9371 | offset | |
9372 | + reg_offset[base_regno]); | |
5adf6da0 R |
9373 | } |
9374 | else | |
9375 | { | |
770ae6cc RK |
9376 | unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode); |
9377 | ||
9378 | for (i = regno; i < endregno; i++) | |
61f5625b AO |
9379 | /* Reset the information about this register. */ |
9380 | reg_set_luid[i] = 0; | |
5adf6da0 R |
9381 | } |
9382 | } | |
2dfa9a87 MH |
9383 | |
9384 | #ifdef AUTO_INC_DEC | |
9385 | static void | |
9386 | add_auto_inc_notes (insn, x) | |
9387 | rtx insn; | |
9388 | rtx x; | |
9389 | { | |
9390 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 9391 | const char *fmt; |
2dfa9a87 MH |
9392 | int i, j; |
9393 | ||
9394 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
9395 | { | |
9396 | REG_NOTES (insn) | |
9397 | = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn)); | |
9398 | return; | |
9399 | } | |
9400 | ||
9401 | /* Scan all the operand sub-expressions. */ | |
9402 | fmt = GET_RTX_FORMAT (code); | |
9403 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
9404 | { | |
9405 | if (fmt[i] == 'e') | |
9406 | add_auto_inc_notes (insn, XEXP (x, i)); | |
9407 | else if (fmt[i] == 'E') | |
9408 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9409 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
9410 | } | |
9411 | } | |
9412 | #endif | |
94bd63e5 AH |
9413 | |
9414 | /* Copy EH notes from an insn to its reloads. */ | |
9415 | static void | |
9416 | copy_eh_notes (insn, x) | |
9417 | rtx insn; | |
9418 | rtx x; | |
9419 | { | |
9420 | rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
9421 | if (eh_note) | |
9422 | { | |
9423 | for (; x != 0; x = NEXT_INSN (x)) | |
9424 | { | |
9425 | if (may_trap_p (PATTERN (x))) | |
a6a2274a | 9426 | REG_NOTES (x) |
94bd63e5 AH |
9427 | = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0), |
9428 | REG_NOTES (x)); | |
9429 | } | |
9430 | } | |
9431 | } | |
9432 | ||
f1330226 JH |
9433 | /* This is used by reload pass, that does emit some instructions after |
9434 | abnormal calls moving basic block end, but in fact it wants to emit | |
9435 | them on the edge. Looks for abnormal call edges, find backward the | |
9436 | proper call and fix the damage. | |
a6a2274a | 9437 | |
f1330226 | 9438 | Similar handle instructions throwing exceptions internally. */ |
068473ec | 9439 | void |
f1330226 JH |
9440 | fixup_abnormal_edges () |
9441 | { | |
f1330226 | 9442 | bool inserted = false; |
e0082a72 | 9443 | basic_block bb; |
f1330226 | 9444 | |
e0082a72 | 9445 | FOR_EACH_BB (bb) |
f1330226 | 9446 | { |
f1330226 JH |
9447 | edge e; |
9448 | ||
9449 | /* Look for cases we are interested in - an calls or instructions causing | |
9450 | exceptions. */ | |
9451 | for (e = bb->succ; e; e = e->succ_next) | |
9452 | { | |
9453 | if (e->flags & EDGE_ABNORMAL_CALL) | |
9454 | break; | |
9455 | if ((e->flags & (EDGE_ABNORMAL | EDGE_EH)) | |
9456 | == (EDGE_ABNORMAL | EDGE_EH)) | |
9457 | break; | |
9458 | } | |
9459 | if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end)) | |
9460 | { | |
0c4992b0 | 9461 | rtx insn = bb->end, stop = NEXT_INSN (bb->end); |
f1330226 JH |
9462 | rtx next; |
9463 | for (e = bb->succ; e; e = e->succ_next) | |
9464 | if (e->flags & EDGE_FALLTHRU) | |
9465 | break; | |
39f95a2c JH |
9466 | /* Get past the new insns generated. Allow notes, as the insns may |
9467 | be already deleted. */ | |
9468 | while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE) | |
9469 | && !can_throw_internal (insn) | |
9470 | && insn != bb->head) | |
f1330226 JH |
9471 | insn = PREV_INSN (insn); |
9472 | if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn)) | |
9473 | abort (); | |
9474 | bb->end = insn; | |
9475 | inserted = true; | |
9476 | insn = NEXT_INSN (insn); | |
0c4992b0 | 9477 | while (insn && insn != stop) |
f1330226 JH |
9478 | { |
9479 | next = NEXT_INSN (insn); | |
0c4992b0 JH |
9480 | if (INSN_P (insn)) |
9481 | { | |
53c17031 | 9482 | delete_insn (insn); |
f8ed1958 | 9483 | |
ed8d2920 MM |
9484 | /* Sometimes there's still the return value USE. |
9485 | If it's placed after a trapping call (i.e. that | |
9486 | call is the last insn anyway), we have no fallthru | |
9487 | edge. Simply delete this use and don't try to insert | |
9488 | on the non-existant edge. */ | |
9489 | if (GET_CODE (PATTERN (insn)) != USE) | |
9490 | { | |
ed8d2920 MM |
9491 | /* We're not deleting it, we're moving it. */ |
9492 | INSN_DELETED_P (insn) = 0; | |
9493 | PREV_INSN (insn) = NULL_RTX; | |
9494 | NEXT_INSN (insn) = NULL_RTX; | |
f8ed1958 | 9495 | |
ed8d2920 MM |
9496 | insert_insn_on_edge (insn, e); |
9497 | } | |
0c4992b0 | 9498 | } |
f1330226 JH |
9499 | insn = next; |
9500 | } | |
9501 | } | |
9502 | } | |
9503 | if (inserted) | |
9504 | commit_edge_insertions (); | |
9505 | } |