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08a9dd06 | 1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
9daf6266 | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
81ef6b6a | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
4 | Free Software Foundation, Inc. | |
08a9dd06 | 5 | |
f12b58b3 | 6 | This file is part of GCC. |
08a9dd06 | 7 | |
f12b58b3 | 8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 2, or (at your option) any later | |
11 | version. | |
08a9dd06 | 12 | |
f12b58b3 | 13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
08a9dd06 | 17 | |
18 | You should have received a copy of the GNU General Public License | |
f12b58b3 | 19 | along with GCC; see the file COPYING. If not, write to the Free |
67ce556b | 20 | Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
08a9dd06 | 22 | |
08a9dd06 | 23 | #include "config.h" |
405711de | 24 | #include "system.h" |
805e22b2 | 25 | #include "coretypes.h" |
26 | #include "tm.h" | |
a986b5e0 | 27 | |
28 | #include "machmode.h" | |
29 | #include "hard-reg-set.h" | |
08a9dd06 | 30 | #include "rtl.h" |
7953c610 | 31 | #include "tm_p.h" |
08a9dd06 | 32 | #include "obstack.h" |
33 | #include "insn-config.h" | |
08a9dd06 | 34 | #include "flags.h" |
0a893c29 | 35 | #include "function.h" |
08a9dd06 | 36 | #include "expr.h" |
d8fc4d0b | 37 | #include "optabs.h" |
08a9dd06 | 38 | #include "regs.h" |
00cb30dc | 39 | #include "addresses.h" |
e94a59c6 | 40 | #include "basic-block.h" |
08a9dd06 | 41 | #include "reload.h" |
42 | #include "recog.h" | |
08a9dd06 | 43 | #include "output.h" |
2a9ed571 | 44 | #include "real.h" |
12874aaf | 45 | #include "toplev.h" |
7a577715 | 46 | #include "except.h" |
c99e85d9 | 47 | #include "tree.h" |
3072d30e | 48 | #include "df.h" |
4d58fa46 | 49 | #include "target.h" |
3072d30e | 50 | #include "dse.h" |
08a9dd06 | 51 | |
52 | /* This file contains the reload pass of the compiler, which is | |
53 | run after register allocation has been done. It checks that | |
54 | each insn is valid (operands required to be in registers really | |
55 | are in registers of the proper class) and fixes up invalid ones | |
56 | by copying values temporarily into registers for the insns | |
57 | that need them. | |
58 | ||
59 | The results of register allocation are described by the vector | |
60 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
61 | can be used to find which hard reg, if any, a pseudo reg is in. | |
62 | ||
63 | The technique we always use is to free up a few hard regs that are | |
64 | called ``reload regs'', and for each place where a pseudo reg | |
65 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
66 | ||
dab171c5 | 67 | Reload regs are allocated locally for every instruction that needs |
68 | reloads. When there are pseudos which are allocated to a register that | |
69 | has been chosen as a reload reg, such pseudos must be ``spilled''. | |
70 | This means that they go to other hard regs, or to stack slots if no other | |
08a9dd06 | 71 | available hard regs can be found. Spilling can invalidate more |
72 | insns, requiring additional need for reloads, so we must keep checking | |
73 | until the process stabilizes. | |
74 | ||
75 | For machines with different classes of registers, we must keep track | |
76 | of the register class needed for each reload, and make sure that | |
77 | we allocate enough reload registers of each class. | |
78 | ||
79 | The file reload.c contains the code that checks one insn for | |
80 | validity and reports the reloads that it needs. This file | |
81 | is in charge of scanning the entire rtl code, accumulating the | |
82 | reload needs, spilling, assigning reload registers to use for | |
83 | fixing up each insn, and generating the new insns to copy values | |
84 | into the reload registers. */ | |
85 | \f | |
86 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
a92771b8 | 87 | into which reg N has been reloaded (perhaps for a previous insn). */ |
08a9dd06 | 88 | static rtx *reg_last_reload_reg; |
89 | ||
90 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
91 | for an output reload that stores into reg N. */ | |
7d742877 | 92 | static regset_head reg_has_output_reload; |
08a9dd06 | 93 | |
94 | /* Indicates which hard regs are reload-registers for an output reload | |
95 | in the current insn. */ | |
96 | static HARD_REG_SET reg_is_output_reload; | |
97 | ||
98 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
99 | or zero if pseudo reg N is not equivalent to a constant. | |
100 | find_reloads looks at this in order to replace pseudo reg N | |
101 | with the constant it stands for. */ | |
102 | rtx *reg_equiv_constant; | |
103 | ||
2e4905ea | 104 | /* Element N is an invariant value to which pseudo reg N is equivalent. |
105 | eliminate_regs_in_insn uses this to replace pseudos in particular | |
106 | contexts. */ | |
107 | rtx *reg_equiv_invariant; | |
108 | ||
08a9dd06 | 109 | /* Element N is a memory location to which pseudo reg N is equivalent, |
110 | prior to any register elimination (such as frame pointer to stack | |
111 | pointer). Depending on whether or not it is a valid address, this value | |
112 | is transferred to either reg_equiv_address or reg_equiv_mem. */ | |
c548e550 | 113 | rtx *reg_equiv_memory_loc; |
08a9dd06 | 114 | |
2bc9fc53 | 115 | /* We allocate reg_equiv_memory_loc inside a varray so that the garbage |
116 | collector can keep track of what is inside. */ | |
28b69ba9 | 117 | VEC(rtx,gc) *reg_equiv_memory_loc_vec; |
2bc9fc53 | 118 | |
08a9dd06 | 119 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. |
120 | This is used when the address is not valid as a memory address | |
121 | (because its displacement is too big for the machine.) */ | |
122 | rtx *reg_equiv_address; | |
123 | ||
124 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
125 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
126 | rtx *reg_equiv_mem; | |
127 | ||
d51b37c2 | 128 | /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with |
129 | alternate representations of the location of pseudo reg N. */ | |
130 | rtx *reg_equiv_alt_mem_list; | |
131 | ||
08a9dd06 | 132 | /* Widest width in which each pseudo reg is referred to (via subreg). */ |
02e7a332 | 133 | static unsigned int *reg_max_ref_width; |
08a9dd06 | 134 | |
537e8d9c | 135 | /* Element N is the list of insns that initialized reg N from its equivalent |
08a9dd06 | 136 | constant or memory slot. */ |
d5058a95 | 137 | rtx *reg_equiv_init; |
138 | int reg_equiv_init_size; | |
08a9dd06 | 139 | |
dab171c5 | 140 | /* Vector to remember old contents of reg_renumber before spilling. */ |
141 | static short *reg_old_renumber; | |
142 | ||
a5e95c30 | 143 | /* During reload_as_needed, element N contains the last pseudo regno reloaded |
dab171c5 | 144 | into hard register N. If that pseudo reg occupied more than one register, |
08a9dd06 | 145 | reg_reloaded_contents points to that pseudo for each spill register in |
146 | use; all of these must remain set for an inheritance to occur. */ | |
147 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
148 | ||
149 | /* During reload_as_needed, element N contains the insn for which | |
a5e95c30 | 150 | hard register N was last used. Its contents are significant only |
151 | when reg_reloaded_valid is set for this register. */ | |
08a9dd06 | 152 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; |
153 | ||
45498ea1 | 154 | /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */ |
a5e95c30 | 155 | static HARD_REG_SET reg_reloaded_valid; |
156 | /* Indicate if the register was dead at the end of the reload. | |
157 | This is only valid if reg_reloaded_contents is set and valid. */ | |
158 | static HARD_REG_SET reg_reloaded_dead; | |
159 | ||
e467c16e | 160 | /* Indicate whether the register's current value is one that is not |
161 | safe to retain across a call, even for registers that are normally | |
162 | call-saved. */ | |
163 | static HARD_REG_SET reg_reloaded_call_part_clobbered; | |
164 | ||
08a9dd06 | 165 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ |
166 | static int n_spills; | |
167 | ||
168 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
169 | Holds the last rtx used for any given reg, or 0 if it has never | |
170 | been used for spilling yet. This rtx is reused, provided it has | |
171 | the proper mode. */ | |
172 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
173 | ||
174 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
175 | that was stored after the last time it was used. | |
176 | The precise value is the insn generated to do the store. */ | |
177 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
178 | ||
93c7b06e | 179 | /* This is the register that was stored with spill_reg_store. This is a |
180 | copy of reload_out / reload_out_reg when the value was stored; if | |
181 | reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ | |
182 | static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; | |
183 | ||
08a9dd06 | 184 | /* This table is the inverse mapping of spill_regs: |
185 | indexed by hard reg number, | |
186 | it contains the position of that reg in spill_regs, | |
5bb2f919 | 187 | or -1 for something that is not in spill_regs. |
e55026a1 | 188 | |
189 | ?!? This is no longer accurate. */ | |
08a9dd06 | 190 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; |
191 | ||
dab171c5 | 192 | /* This reg set indicates registers that can't be used as spill registers for |
193 | the currently processed insn. These are the hard registers which are live | |
194 | during the insn, but not allocated to pseudos, as well as fixed | |
195 | registers. */ | |
08a9dd06 | 196 | static HARD_REG_SET bad_spill_regs; |
197 | ||
dab171c5 | 198 | /* These are the hard registers that can't be used as spill register for any |
199 | insn. This includes registers used for user variables and registers that | |
200 | we can't eliminate. A register that appears in this set also can't be used | |
201 | to retry register allocation. */ | |
202 | static HARD_REG_SET bad_spill_regs_global; | |
203 | ||
08a9dd06 | 204 | /* Describes order of use of registers for reloading |
dab171c5 | 205 | of spilled pseudo-registers. `n_spills' is the number of |
206 | elements that are actually valid; new ones are added at the end. | |
207 | ||
208 | Both spill_regs and spill_reg_order are used on two occasions: | |
209 | once during find_reload_regs, where they keep track of the spill registers | |
210 | for a single insn, but also during reload_as_needed where they show all | |
211 | the registers ever used by reload. For the latter case, the information | |
212 | is calculated during finish_spills. */ | |
08a9dd06 | 213 | static short spill_regs[FIRST_PSEUDO_REGISTER]; |
214 | ||
dab171c5 | 215 | /* This vector of reg sets indicates, for each pseudo, which hard registers |
216 | may not be used for retrying global allocation because the register was | |
217 | formerly spilled from one of them. If we allowed reallocating a pseudo to | |
218 | a register that it was already allocated to, reload might not | |
219 | terminate. */ | |
220 | static HARD_REG_SET *pseudo_previous_regs; | |
221 | ||
222 | /* This vector of reg sets indicates, for each pseudo, which hard | |
223 | registers may not be used for retrying global allocation because they | |
224 | are used as spill registers during one of the insns in which the | |
225 | pseudo is live. */ | |
226 | static HARD_REG_SET *pseudo_forbidden_regs; | |
227 | ||
228 | /* All hard regs that have been used as spill registers for any insn are | |
229 | marked in this set. */ | |
230 | static HARD_REG_SET used_spill_regs; | |
ed69f33f | 231 | |
de261207 | 232 | /* Index of last register assigned as a spill register. We allocate in |
233 | a round-robin fashion. */ | |
de261207 | 234 | static int last_spill_reg; |
235 | ||
08a9dd06 | 236 | /* Nonzero if indirect addressing is supported on the machine; this means |
237 | that spilling (REG n) does not require reloading it into a register in | |
238 | order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The | |
239 | value indicates the level of indirect addressing supported, e.g., two | |
240 | means that (MEM (MEM (REG n))) is also valid if (REG n) does not get | |
241 | a hard register. */ | |
08a9dd06 | 242 | static char spill_indirect_levels; |
243 | ||
244 | /* Nonzero if indirect addressing is supported when the innermost MEM is | |
245 | of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to | |
1e625a2e | 246 | which these are valid is the same as spill_indirect_levels, above. */ |
12be4bb2 | 247 | char indirect_symref_ok; |
08a9dd06 | 248 | |
249 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
08a9dd06 | 250 | char double_reg_address_ok; |
251 | ||
252 | /* Record the stack slot for each spilled hard register. */ | |
08a9dd06 | 253 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; |
254 | ||
255 | /* Width allocated so far for that stack slot. */ | |
02e7a332 | 256 | static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; |
08a9dd06 | 257 | |
590ec786 | 258 | /* Record which pseudos needed to be spilled. */ |
fbf51e51 | 259 | static regset_head spilled_pseudos; |
260 | ||
261 | /* Used for communication between order_regs_for_reload and count_pseudo. | |
262 | Used to avoid counting one pseudo twice. */ | |
263 | static regset_head pseudos_counted; | |
590ec786 | 264 | |
08a9dd06 | 265 | /* First uid used by insns created by reload in this function. |
266 | Used in find_equiv_reg. */ | |
267 | int reload_first_uid; | |
268 | ||
269 | /* Flag set by local-alloc or global-alloc if anything is live in | |
270 | a call-clobbered reg across calls. */ | |
08a9dd06 | 271 | int caller_save_needed; |
272 | ||
273 | /* Set to 1 while reload_as_needed is operating. | |
274 | Required by some machines to handle any generated moves differently. */ | |
08a9dd06 | 275 | int reload_in_progress = 0; |
276 | ||
277 | /* These arrays record the insn_code of insns that may be needed to | |
278 | perform input and output reloads of special objects. They provide a | |
279 | place to pass a scratch register. */ | |
08a9dd06 | 280 | enum insn_code reload_in_optab[NUM_MACHINE_MODES]; |
281 | enum insn_code reload_out_optab[NUM_MACHINE_MODES]; | |
282 | ||
f9e15121 | 283 | /* This obstack is used for allocation of rtl during register elimination. |
08a9dd06 | 284 | The allocated storage can be freed once find_reloads has processed the |
285 | insn. */ | |
19e3c8bf | 286 | static struct obstack reload_obstack; |
e94a59c6 | 287 | |
288 | /* Points to the beginning of the reload_obstack. All insn_chain structures | |
289 | are allocated first. */ | |
56d727be | 290 | static char *reload_startobj; |
e94a59c6 | 291 | |
292 | /* The point after all insn_chain structures. Used to quickly deallocate | |
fbf51e51 | 293 | memory allocated in copy_reloads during calculate_needs_all_insns. */ |
56d727be | 294 | static char *reload_firstobj; |
08a9dd06 | 295 | |
fbf51e51 | 296 | /* This points before all local rtl generated by register elimination. |
297 | Used to quickly free all memory after processing one insn. */ | |
298 | static char *reload_insn_firstobj; | |
299 | ||
e94a59c6 | 300 | /* List of insn_chain instructions, one for every insn that reload needs to |
301 | examine. */ | |
302 | struct insn_chain *reload_insn_chain; | |
590ec786 | 303 | |
dab171c5 | 304 | /* List of all insns needing reloads. */ |
590ec786 | 305 | static struct insn_chain *insns_need_reload; |
08a9dd06 | 306 | \f |
307 | /* This structure is used to record information about register eliminations. | |
308 | Each array entry describes one possible way of eliminating a register | |
309 | in favor of another. If there is more than one way of eliminating a | |
310 | particular register, the most preferred should be specified first. */ | |
311 | ||
911d0ac2 | 312 | struct elim_table |
08a9dd06 | 313 | { |
a92771b8 | 314 | int from; /* Register number to be eliminated. */ |
315 | int to; /* Register number used as replacement. */ | |
ec96de93 | 316 | HOST_WIDE_INT initial_offset; /* Initial difference between values. */ |
a8b24921 | 317 | int can_eliminate; /* Nonzero if this elimination can be done. */ |
08a9dd06 | 318 | int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over |
a92771b8 | 319 | insns made by reload. */ |
ec96de93 | 320 | HOST_WIDE_INT offset; /* Current offset between the two regs. */ |
321 | HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */ | |
a92771b8 | 322 | int ref_outside_mem; /* "to" has been referenced outside a MEM. */ |
08a9dd06 | 323 | rtx from_rtx; /* REG rtx for the register to be eliminated. |
324 | We cannot simply compare the number since | |
325 | we might then spuriously replace a hard | |
326 | register corresponding to a pseudo | |
a92771b8 | 327 | assigned to the reg to be eliminated. */ |
328 | rtx to_rtx; /* REG rtx for the replacement. */ | |
911d0ac2 | 329 | }; |
330 | ||
aedd3e94 | 331 | static struct elim_table *reg_eliminate = 0; |
911d0ac2 | 332 | |
333 | /* This is an intermediate structure to initialize the table. It has | |
aedd3e94 | 334 | exactly the members provided by ELIMINABLE_REGS. */ |
e7c691ac | 335 | static const struct elim_table_1 |
911d0ac2 | 336 | { |
e7c691ac | 337 | const int from; |
338 | const int to; | |
911d0ac2 | 339 | } reg_eliminate_1[] = |
08a9dd06 | 340 | |
341 | /* If a set of eliminable registers was specified, define the table from it. | |
342 | Otherwise, default to the normal case of the frame pointer being | |
343 | replaced by the stack pointer. */ | |
344 | ||
345 | #ifdef ELIMINABLE_REGS | |
346 | ELIMINABLE_REGS; | |
347 | #else | |
348 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
349 | #endif | |
350 | ||
3098b2d3 | 351 | #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) |
08a9dd06 | 352 | |
353 | /* Record the number of pending eliminations that have an offset not equal | |
7fd957fe | 354 | to their initial offset. If nonzero, we use a new copy of each |
08a9dd06 | 355 | replacement result in any insns encountered. */ |
93c7b06e | 356 | int num_not_at_initial_offset; |
08a9dd06 | 357 | |
358 | /* Count the number of registers that we may be able to eliminate. */ | |
359 | static int num_eliminable; | |
aa8d28af | 360 | /* And the number of registers that are equivalent to a constant that |
361 | can be eliminated to frame_pointer / arg_pointer + constant. */ | |
362 | static int num_eliminable_invariants; | |
08a9dd06 | 363 | |
364 | /* For each label, we record the offset of each elimination. If we reach | |
365 | a label by more than one path and an offset differs, we cannot do the | |
2ff147ce | 366 | elimination. This information is indexed by the difference of the |
367 | number of the label and the first label number. We can't offset the | |
368 | pointer itself as this can cause problems on machines with segmented | |
369 | memory. The first table is an array of flags that records whether we | |
370 | have yet encountered a label and the second table is an array of arrays, | |
371 | one entry in the latter array for each elimination. */ | |
372 | ||
373 | static int first_label_num; | |
08a9dd06 | 374 | static char *offsets_known_at; |
ec96de93 | 375 | static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS]; |
08a9dd06 | 376 | |
377 | /* Number of labels in the current function. */ | |
378 | ||
379 | static int num_labels; | |
380 | \f | |
3ad4992f | 381 | static void replace_pseudos_in (rtx *, enum machine_mode, rtx); |
382 | static void maybe_fix_stack_asms (void); | |
383 | static void copy_reloads (struct insn_chain *); | |
384 | static void calculate_needs_all_insns (int); | |
385 | static int find_reg (struct insn_chain *, int); | |
386 | static void find_reload_regs (struct insn_chain *); | |
387 | static void select_reload_regs (void); | |
388 | static void delete_caller_save_insns (void); | |
389 | ||
390 | static void spill_failure (rtx, enum reg_class); | |
391 | static void count_spilled_pseudo (int, int, int); | |
392 | static void delete_dead_insn (rtx); | |
393 | static void alter_reg (int, int); | |
394 | static void set_label_offsets (rtx, rtx, int); | |
395 | static void check_eliminable_occurrences (rtx); | |
396 | static void elimination_effects (rtx, enum machine_mode); | |
397 | static int eliminate_regs_in_insn (rtx, int); | |
398 | static void update_eliminable_offsets (void); | |
399 | static void mark_not_eliminable (rtx, rtx, void *); | |
400 | static void set_initial_elim_offsets (void); | |
ba0fef14 | 401 | static bool verify_initial_elim_offsets (void); |
3ad4992f | 402 | static void set_initial_label_offsets (void); |
403 | static void set_offsets_for_label (rtx); | |
404 | static void init_elim_table (void); | |
405 | static void update_eliminables (HARD_REG_SET *); | |
406 | static void spill_hard_reg (unsigned int, int); | |
407 | static int finish_spills (int); | |
3ad4992f | 408 | static void scan_paradoxical_subregs (rtx); |
409 | static void count_pseudo (int); | |
410 | static void order_regs_for_reload (struct insn_chain *); | |
411 | static void reload_as_needed (int); | |
412 | static void forget_old_reloads_1 (rtx, rtx, void *); | |
94aa2a3c | 413 | static void forget_marked_reloads (regset); |
3ad4992f | 414 | static int reload_reg_class_lower (const void *, const void *); |
415 | static void mark_reload_reg_in_use (unsigned int, int, enum reload_type, | |
416 | enum machine_mode); | |
417 | static void clear_reload_reg_in_use (unsigned int, int, enum reload_type, | |
418 | enum machine_mode); | |
419 | static int reload_reg_free_p (unsigned int, int, enum reload_type); | |
420 | static int reload_reg_free_for_value_p (int, int, int, enum reload_type, | |
421 | rtx, rtx, int, int); | |
422 | static int free_for_value_p (int, enum machine_mode, int, enum reload_type, | |
423 | rtx, rtx, int, int); | |
424 | static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type); | |
425 | static int allocate_reload_reg (struct insn_chain *, int, int); | |
426 | static int conflicts_with_override (rtx); | |
427 | static void failed_reload (rtx, int); | |
428 | static int set_reload_reg (int, int); | |
429 | static void choose_reload_regs_init (struct insn_chain *, rtx *); | |
430 | static void choose_reload_regs (struct insn_chain *); | |
431 | static void merge_assigned_reloads (rtx); | |
432 | static void emit_input_reload_insns (struct insn_chain *, struct reload *, | |
433 | rtx, int); | |
434 | static void emit_output_reload_insns (struct insn_chain *, struct reload *, | |
435 | int); | |
436 | static void do_input_reload (struct insn_chain *, struct reload *, int); | |
437 | static void do_output_reload (struct insn_chain *, struct reload *, int); | |
9318b368 | 438 | static bool inherit_piecemeal_p (int, int); |
3ad4992f | 439 | static void emit_reload_insns (struct insn_chain *); |
440 | static void delete_output_reload (rtx, int, int); | |
441 | static void delete_address_reloads (rtx, rtx); | |
442 | static void delete_address_reloads_1 (rtx, rtx, rtx); | |
443 | static rtx inc_for_reload (rtx, rtx, rtx, int); | |
c4f0a530 | 444 | #ifdef AUTO_INC_DEC |
3ad4992f | 445 | static void add_auto_inc_notes (rtx, rtx); |
c4f0a530 | 446 | #endif |
3ad4992f | 447 | static void copy_eh_notes (rtx, rtx); |
3c01fc19 | 448 | static int reloads_conflict (int, int); |
449 | static rtx gen_reload (rtx, rtx, int, enum reload_type); | |
6af46e97 | 450 | static rtx emit_insn_if_valid_for_reload (rtx); |
08a9dd06 | 451 | \f |
81d0fbb3 | 452 | /* Initialize the reload pass once per compilation. */ |
453 | ||
08a9dd06 | 454 | void |
3ad4992f | 455 | init_reload (void) |
08a9dd06 | 456 | { |
19cb6b50 | 457 | int i; |
08a9dd06 | 458 | |
459 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
460 | Set spill_indirect_levels to the number of levels such addressing is | |
461 | permitted, zero if it is not permitted at all. */ | |
462 | ||
19cb6b50 | 463 | rtx tem |
941522d6 | 464 | = gen_rtx_MEM (Pmode, |
465 | gen_rtx_PLUS (Pmode, | |
7014838c | 466 | gen_rtx_REG (Pmode, |
467 | LAST_VIRTUAL_REGISTER + 1), | |
941522d6 | 468 | GEN_INT (4))); |
08a9dd06 | 469 | spill_indirect_levels = 0; |
470 | ||
471 | while (memory_address_p (QImode, tem)) | |
472 | { | |
473 | spill_indirect_levels++; | |
941522d6 | 474 | tem = gen_rtx_MEM (Pmode, tem); |
08a9dd06 | 475 | } |
476 | ||
477 | /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ | |
478 | ||
941522d6 | 479 | tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); |
08a9dd06 | 480 | indirect_symref_ok = memory_address_p (QImode, tem); |
481 | ||
482 | /* See if reg+reg is a valid (and offsettable) address. */ | |
483 | ||
b19bcbd6 | 484 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
26717e42 | 485 | { |
941522d6 | 486 | tem = gen_rtx_PLUS (Pmode, |
487 | gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), | |
488 | gen_rtx_REG (Pmode, i)); | |
7014838c | 489 | |
26717e42 | 490 | /* This way, we make sure that reg+reg is an offsettable address. */ |
491 | tem = plus_constant (tem, 4); | |
492 | ||
493 | if (memory_address_p (QImode, tem)) | |
494 | { | |
495 | double_reg_address_ok = 1; | |
496 | break; | |
497 | } | |
498 | } | |
08a9dd06 | 499 | |
a92771b8 | 500 | /* Initialize obstack for our rtl allocation. */ |
08a9dd06 | 501 | gcc_obstack_init (&reload_obstack); |
f0af5a88 | 502 | reload_startobj = obstack_alloc (&reload_obstack, 0); |
fbf51e51 | 503 | |
504 | INIT_REG_SET (&spilled_pseudos); | |
505 | INIT_REG_SET (&pseudos_counted); | |
08a9dd06 | 506 | } |
507 | ||
e94a59c6 | 508 | /* List of insn chains that are currently unused. */ |
509 | static struct insn_chain *unused_insn_chains = 0; | |
510 | ||
511 | /* Allocate an empty insn_chain structure. */ | |
512 | struct insn_chain * | |
3ad4992f | 513 | new_insn_chain (void) |
e94a59c6 | 514 | { |
515 | struct insn_chain *c; | |
516 | ||
517 | if (unused_insn_chains == 0) | |
518 | { | |
f0af5a88 | 519 | c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain)); |
f62c22a7 | 520 | INIT_REG_SET (&c->live_throughout); |
521 | INIT_REG_SET (&c->dead_or_set); | |
e94a59c6 | 522 | } |
523 | else | |
524 | { | |
525 | c = unused_insn_chains; | |
526 | unused_insn_chains = c->next; | |
527 | } | |
528 | c->is_caller_save_insn = 0; | |
dab171c5 | 529 | c->need_operand_change = 0; |
e94a59c6 | 530 | c->need_reload = 0; |
531 | c->need_elim = 0; | |
532 | return c; | |
533 | } | |
534 | ||
590ec786 | 535 | /* Small utility function to set all regs in hard reg set TO which are |
536 | allocated to pseudos in regset FROM. */ | |
02e7a332 | 537 | |
590ec786 | 538 | void |
3ad4992f | 539 | compute_use_by_pseudos (HARD_REG_SET *to, regset from) |
590ec786 | 540 | { |
02e7a332 | 541 | unsigned int regno; |
8c97cf13 | 542 | reg_set_iterator rsi; |
02e7a332 | 543 | |
8c97cf13 | 544 | EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi) |
545 | { | |
546 | int r = reg_renumber[regno]; | |
8c97cf13 | 547 | |
548 | if (r < 0) | |
549 | { | |
550 | /* reload_combine uses the information from | |
3072d30e | 551 | DF_RA_LIVE_IN (BASIC_BLOCK), which might still |
8c97cf13 | 552 | contain registers that have not actually been allocated |
553 | since they have an equivalence. */ | |
554 | gcc_assert (reload_completed); | |
555 | } | |
556 | else | |
a2c6f0b7 | 557 | add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r); |
8c97cf13 | 558 | } |
590ec786 | 559 | } |
ddaf7ad3 | 560 | |
561 | /* Replace all pseudos found in LOC with their corresponding | |
562 | equivalences. */ | |
563 | ||
564 | static void | |
3ad4992f | 565 | replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage) |
ddaf7ad3 | 566 | { |
567 | rtx x = *loc; | |
568 | enum rtx_code code; | |
569 | const char *fmt; | |
570 | int i, j; | |
571 | ||
572 | if (! x) | |
573 | return; | |
4f271297 | 574 | |
ddaf7ad3 | 575 | code = GET_CODE (x); |
576 | if (code == REG) | |
577 | { | |
97b330ca | 578 | unsigned int regno = REGNO (x); |
aada3aa9 | 579 | |
580 | if (regno < FIRST_PSEUDO_REGISTER) | |
ddaf7ad3 | 581 | return; |
582 | ||
583 | x = eliminate_regs (x, mem_mode, usage); | |
584 | if (x != *loc) | |
585 | { | |
586 | *loc = x; | |
d5f9786f | 587 | replace_pseudos_in (loc, mem_mode, usage); |
ddaf7ad3 | 588 | return; |
589 | } | |
590 | ||
aada3aa9 | 591 | if (reg_equiv_constant[regno]) |
592 | *loc = reg_equiv_constant[regno]; | |
593 | else if (reg_equiv_mem[regno]) | |
594 | *loc = reg_equiv_mem[regno]; | |
595 | else if (reg_equiv_address[regno]) | |
596 | *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]); | |
ddaf7ad3 | 597 | else |
04e579b6 | 598 | { |
599 | gcc_assert (!REG_P (regno_reg_rtx[regno]) | |
600 | || REGNO (regno_reg_rtx[regno]) != regno); | |
601 | *loc = regno_reg_rtx[regno]; | |
602 | } | |
ddaf7ad3 | 603 | |
604 | return; | |
605 | } | |
606 | else if (code == MEM) | |
607 | { | |
d5f9786f | 608 | replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage); |
ddaf7ad3 | 609 | return; |
610 | } | |
4f271297 | 611 | |
ddaf7ad3 | 612 | /* Process each of our operands recursively. */ |
613 | fmt = GET_RTX_FORMAT (code); | |
614 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
615 | if (*fmt == 'e') | |
d5f9786f | 616 | replace_pseudos_in (&XEXP (x, i), mem_mode, usage); |
ddaf7ad3 | 617 | else if (*fmt == 'E') |
618 | for (j = 0; j < XVECLEN (x, i); j++) | |
d5f9786f | 619 | replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage); |
ddaf7ad3 | 620 | } |
621 | ||
29f09705 | 622 | /* Determine if the current function has an exception receiver block |
623 | that reaches the exit block via non-exceptional edges */ | |
624 | ||
625 | static bool | |
626 | has_nonexceptional_receiver (void) | |
627 | { | |
628 | edge e; | |
629 | edge_iterator ei; | |
630 | basic_block *tos, *worklist, bb; | |
631 | ||
632 | /* If we're not optimizing, then just err on the safe side. */ | |
633 | if (!optimize) | |
634 | return true; | |
635 | ||
636 | /* First determine which blocks can reach exit via normal paths. */ | |
637 | tos = worklist = xmalloc (sizeof (basic_block) * (n_basic_blocks + 1)); | |
638 | ||
639 | FOR_EACH_BB (bb) | |
640 | bb->flags &= ~BB_REACHABLE; | |
641 | ||
642 | /* Place the exit block on our worklist. */ | |
643 | EXIT_BLOCK_PTR->flags |= BB_REACHABLE; | |
644 | *tos++ = EXIT_BLOCK_PTR; | |
645 | ||
646 | /* Iterate: find everything reachable from what we've already seen. */ | |
647 | while (tos != worklist) | |
648 | { | |
649 | bb = *--tos; | |
650 | ||
651 | FOR_EACH_EDGE (e, ei, bb->preds) | |
652 | if (!(e->flags & EDGE_ABNORMAL)) | |
653 | { | |
654 | basic_block src = e->src; | |
655 | ||
656 | if (!(src->flags & BB_REACHABLE)) | |
657 | { | |
658 | src->flags |= BB_REACHABLE; | |
659 | *tos++ = src; | |
660 | } | |
661 | } | |
662 | } | |
663 | free (worklist); | |
664 | ||
665 | /* Now see if there's a reachable block with an exceptional incoming | |
666 | edge. */ | |
667 | FOR_EACH_BB (bb) | |
668 | if (bb->flags & BB_REACHABLE) | |
669 | FOR_EACH_EDGE (e, ei, bb->preds) | |
670 | if (e->flags & EDGE_ABNORMAL) | |
671 | return true; | |
672 | ||
673 | /* No exceptional block reached exit unexceptionally. */ | |
674 | return false; | |
675 | } | |
676 | ||
dab171c5 | 677 | \f |
1aacee06 | 678 | /* Global variables used by reload and its subroutines. */ |
679 | ||
1aacee06 | 680 | /* Set during calculate_needs if an insn needs register elimination. */ |
681 | static int something_needs_elimination; | |
93c7b06e | 682 | /* Set during calculate_needs if an insn needs an operand changed. */ |
56d727be | 683 | static int something_needs_operands_changed; |
1aacee06 | 684 | |
1aacee06 | 685 | /* Nonzero means we couldn't get enough spill regs. */ |
686 | static int failure; | |
687 | ||
81d0fbb3 | 688 | /* Main entry point for the reload pass. |
08a9dd06 | 689 | |
690 | FIRST is the first insn of the function being compiled. | |
691 | ||
692 | GLOBAL nonzero means we were called from global_alloc | |
693 | and should attempt to reallocate any pseudoregs that we | |
694 | displace from hard regs we will use for reloads. | |
695 | If GLOBAL is zero, we do not have enough information to do that, | |
696 | so any pseudo reg that is spilled must go to the stack. | |
697 | ||
2e756f7d | 698 | Return value is nonzero if reload failed |
699 | and we must not do any more for this function. */ | |
700 | ||
701 | int | |
3ad4992f | 702 | reload (rtx first, int global) |
08a9dd06 | 703 | { |
19cb6b50 | 704 | int i; |
705 | rtx insn; | |
706 | struct elim_table *ep; | |
4c26117a | 707 | basic_block bb; |
08a9dd06 | 708 | |
08a9dd06 | 709 | /* Make sure even insns with volatile mem refs are recognizable. */ |
710 | init_recog (); | |
711 | ||
1aacee06 | 712 | failure = 0; |
713 | ||
f0af5a88 | 714 | reload_firstobj = obstack_alloc (&reload_obstack, 0); |
e94a59c6 | 715 | |
e546118a | 716 | /* Make sure that the last insn in the chain |
717 | is not something that needs reloading. */ | |
31b97e8f | 718 | emit_note (NOTE_INSN_DELETED); |
e546118a | 719 | |
08a9dd06 | 720 | /* Enable find_equiv_reg to distinguish insns made by reload. */ |
721 | reload_first_uid = get_max_uid (); | |
722 | ||
c538053c | 723 | #ifdef SECONDARY_MEMORY_NEEDED |
724 | /* Initialize the secondary memory table. */ | |
725 | clear_secondary_mem (); | |
726 | #endif | |
727 | ||
08a9dd06 | 728 | /* We don't have a stack slot for any spill reg yet. */ |
f0af5a88 | 729 | memset (spill_stack_slot, 0, sizeof spill_stack_slot); |
730 | memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width); | |
08a9dd06 | 731 | |
ca9902fc | 732 | /* Initialize the save area information for caller-save, in case some |
733 | are needed. */ | |
734 | init_save_areas (); | |
c8ad158d | 735 | |
08a9dd06 | 736 | /* Compute which hard registers are now in use |
737 | as homes for pseudo registers. | |
738 | This is done here rather than (eg) in global_alloc | |
739 | because this point is reached even if not optimizing. */ | |
08a9dd06 | 740 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
741 | mark_home_live (i); | |
742 | ||
29f09705 | 743 | /* A function that has a nonlocal label that can reach the exit |
744 | block via non-exceptional paths must save all call-saved | |
f668952a | 745 | registers. */ |
29f09705 | 746 | if (current_function_calls_unwind_init |
747 | || (current_function_has_nonlocal_label | |
748 | && has_nonexceptional_receiver ())) | |
f668952a | 749 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
5490c1ec | 750 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) |
3072d30e | 751 | df_set_regs_ever_live (i, true); |
f668952a | 752 | |
08a9dd06 | 753 | /* Find all the pseudo registers that didn't get hard regs |
754 | but do have known equivalent constants or memory slots. | |
755 | These include parameters (known equivalent to parameter slots) | |
756 | and cse'd or loop-moved constant memory addresses. | |
757 | ||
758 | Record constant equivalents in reg_equiv_constant | |
759 | so they will be substituted by find_reloads. | |
760 | Record memory equivalents in reg_mem_equiv so they can | |
761 | be substituted eventually by altering the REG-rtx's. */ | |
762 | ||
4c36ffe6 | 763 | reg_equiv_constant = XCNEWVEC (rtx, max_regno); |
764 | reg_equiv_invariant = XCNEWVEC (rtx, max_regno); | |
765 | reg_equiv_mem = XCNEWVEC (rtx, max_regno); | |
d51b37c2 | 766 | reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno); |
4c36ffe6 | 767 | reg_equiv_address = XCNEWVEC (rtx, max_regno); |
768 | reg_max_ref_width = XCNEWVEC (unsigned int, max_regno); | |
769 | reg_old_renumber = XCNEWVEC (short, max_regno); | |
b1b63592 | 770 | memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); |
4c36ffe6 | 771 | pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno); |
772 | pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno); | |
08a9dd06 | 773 | |
dab171c5 | 774 | CLEAR_HARD_REG_SET (bad_spill_regs_global); |
e715e2a3 | 775 | |
d40bf399 | 776 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent |
777 | to. Also find all paradoxical subregs and find largest such for | |
778 | each pseudo. */ | |
08a9dd06 | 779 | |
aa8d28af | 780 | num_eliminable_invariants = 0; |
08a9dd06 | 781 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
782 | { | |
783 | rtx set = single_set (insn); | |
784 | ||
b2920130 | 785 | /* We may introduce USEs that we want to remove at the end, so |
786 | we'll mark them with QImode. Make sure there are no | |
787 | previously-marked insns left by say regmove. */ | |
788 | if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE | |
789 | && GET_MODE (insn) != VOIDmode) | |
790 | PUT_MODE (insn, VOIDmode); | |
791 | ||
d5058a95 | 792 | if (INSN_P (insn)) |
793 | scan_paradoxical_subregs (PATTERN (insn)); | |
794 | ||
8ad4c111 | 795 | if (set != 0 && REG_P (SET_DEST (set))) |
08a9dd06 | 796 | { |
e5fdd564 | 797 | rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
d5058a95 | 798 | rtx x; |
799 | ||
800 | if (! note) | |
801 | continue; | |
802 | ||
803 | i = REGNO (SET_DEST (set)); | |
804 | x = XEXP (note, 0); | |
805 | ||
806 | if (i <= LAST_VIRTUAL_REGISTER) | |
807 | continue; | |
808 | ||
809 | if (! function_invariant_p (x) | |
810 | || ! flag_pic | |
811 | /* A function invariant is often CONSTANT_P but may | |
812 | include a register. We promise to only pass | |
813 | CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ | |
814 | || (CONSTANT_P (x) | |
815 | && LEGITIMATE_PIC_OPERAND_P (x))) | |
08a9dd06 | 816 | { |
d5058a95 | 817 | /* It can happen that a REG_EQUIV note contains a MEM |
818 | that is not a legitimate memory operand. As later | |
819 | stages of reload assume that all addresses found | |
820 | in the reg_equiv_* arrays were originally legitimate, | |
821 | we ignore such REG_EQUIV notes. */ | |
822 | if (memory_operand (x, VOIDmode)) | |
08a9dd06 | 823 | { |
d5058a95 | 824 | /* Always unshare the equivalence, so we can |
825 | substitute into this insn without touching the | |
826 | equivalence. */ | |
827 | reg_equiv_memory_loc[i] = copy_rtx (x); | |
828 | } | |
829 | else if (function_invariant_p (x)) | |
830 | { | |
831 | if (GET_CODE (x) == PLUS) | |
ad87de1e | 832 | { |
d5058a95 | 833 | /* This is PLUS of frame pointer and a constant, |
834 | and might be shared. Unshare it. */ | |
2e4905ea | 835 | reg_equiv_invariant[i] = copy_rtx (x); |
d5058a95 | 836 | num_eliminable_invariants++; |
ad87de1e | 837 | } |
2e4905ea | 838 | else if (x == frame_pointer_rtx || x == arg_pointer_rtx) |
08a9dd06 | 839 | { |
2e4905ea | 840 | reg_equiv_invariant[i] = x; |
d5058a95 | 841 | num_eliminable_invariants++; |
08a9dd06 | 842 | } |
d5058a95 | 843 | else if (LEGITIMATE_CONSTANT_P (x)) |
844 | reg_equiv_constant[i] = x; | |
08a9dd06 | 845 | else |
d5058a95 | 846 | { |
847 | reg_equiv_memory_loc[i] | |
848 | = force_const_mem (GET_MODE (SET_DEST (set)), x); | |
849 | if (! reg_equiv_memory_loc[i]) | |
850 | reg_equiv_init[i] = NULL_RTX; | |
851 | } | |
852 | } | |
853 | else | |
854 | { | |
855 | reg_equiv_init[i] = NULL_RTX; | |
856 | continue; | |
08a9dd06 | 857 | } |
858 | } | |
d5058a95 | 859 | else |
860 | reg_equiv_init[i] = NULL_RTX; | |
08a9dd06 | 861 | } |
08a9dd06 | 862 | } |
863 | ||
d5058a95 | 864 | if (dump_file) |
865 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
866 | if (reg_equiv_init[i]) | |
867 | { | |
868 | fprintf (dump_file, "init_insns for %u: ", i); | |
869 | print_inline_rtx (dump_file, reg_equiv_init[i], 20); | |
870 | fprintf (dump_file, "\n"); | |
871 | } | |
872 | ||
9d24e570 | 873 | init_elim_table (); |
08a9dd06 | 874 | |
2ff147ce | 875 | first_label_num = get_first_label_num (); |
876 | num_labels = max_label_num () - first_label_num; | |
08a9dd06 | 877 | |
878 | /* Allocate the tables used to store offset information at labels. */ | |
6dd870f4 | 879 | /* We used to use alloca here, but the size of what it would try to |
880 | allocate would occasionally cause it to exceed the stack limit and | |
881 | cause a core dump. */ | |
4c36ffe6 | 882 | offsets_known_at = XNEWVEC (char, num_labels); |
883 | offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT)); | |
08a9dd06 | 884 | |
08a9dd06 | 885 | /* Alter each pseudo-reg rtx to contain its hard reg number. |
886 | Assign stack slots to the pseudos that lack hard regs or equivalents. | |
887 | Do not touch virtual registers. */ | |
888 | ||
889 | for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) | |
890 | alter_reg (i, -1); | |
891 | ||
08a9dd06 | 892 | /* If we have some registers we think can be eliminated, scan all insns to |
893 | see if there is an insn that sets one of these registers to something | |
894 | other than itself plus a constant. If so, the register cannot be | |
895 | eliminated. Doing this scan here eliminates an extra pass through the | |
896 | main reload loop in the most common case where register elimination | |
897 | cannot be done. */ | |
898 | for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) | |
6d7dc5b9 | 899 | if (INSN_P (insn)) |
ec8895d7 | 900 | note_stores (PATTERN (insn), mark_not_eliminable, NULL); |
08a9dd06 | 901 | |
faf8dbee | 902 | maybe_fix_stack_asms (); |
903 | ||
dab171c5 | 904 | insns_need_reload = 0; |
905 | something_needs_elimination = 0; | |
5bb2f919 | 906 | |
de261207 | 907 | /* Initialize to -1, which means take the first spill register. */ |
908 | last_spill_reg = -1; | |
909 | ||
08a9dd06 | 910 | /* Spill any hard regs that we know we can't eliminate. */ |
dab171c5 | 911 | CLEAR_HARD_REG_SET (used_spill_regs); |
fd11b602 | 912 | /* There can be multiple ways to eliminate a register; |
913 | they should be listed adjacently. | |
914 | Elimination for any register fails only if all possible ways fail. */ | |
915 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ) | |
916 | { | |
917 | int from = ep->from; | |
918 | int can_eliminate = 0; | |
919 | do | |
920 | { | |
921 | can_eliminate |= ep->can_eliminate; | |
922 | ep++; | |
923 | } | |
924 | while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from); | |
925 | if (! can_eliminate) | |
926 | spill_hard_reg (from, 1); | |
927 | } | |
0394c2e6 | 928 | |
929 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
930 | if (frame_pointer_needed) | |
bfd0ee98 | 931 | spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1); |
0394c2e6 | 932 | #endif |
bfd0ee98 | 933 | finish_spills (global); |
590ec786 | 934 | |
9e519b97 | 935 | /* From now on, we may need to generate moves differently. We may also |
936 | allow modifications of insns which cause them to not be recognized. | |
937 | Any such modifications will be cleaned up during reload itself. */ | |
c1668c09 | 938 | reload_in_progress = 1; |
939 | ||
08a9dd06 | 940 | /* This loop scans the entire function each go-round |
941 | and repeats until one repetition spills no additional hard regs. */ | |
dab171c5 | 942 | for (;;) |
08a9dd06 | 943 | { |
dab171c5 | 944 | int something_changed; |
945 | int did_spill; | |
dab171c5 | 946 | HOST_WIDE_INT starting_frame_size; |
08a9dd06 | 947 | |
2debb316 | 948 | starting_frame_size = get_frame_size (); |
949 | ||
9d24e570 | 950 | set_initial_elim_offsets (); |
f87f6d5d | 951 | set_initial_label_offsets (); |
dab171c5 | 952 | |
08a9dd06 | 953 | /* For each pseudo register that has an equivalent location defined, |
954 | try to eliminate any eliminable registers (such as the frame pointer) | |
955 | assuming initial offsets for the replacement register, which | |
956 | is the normal case. | |
957 | ||
958 | If the resulting location is directly addressable, substitute | |
959 | the MEM we just got directly for the old REG. | |
960 | ||
961 | If it is not addressable but is a constant or the sum of a hard reg | |
962 | and constant, it is probably not addressable because the constant is | |
963 | out of range, in that case record the address; we will generate | |
964 | hairy code to compute the address in a register each time it is | |
37690010 | 965 | needed. Similarly if it is a hard register, but one that is not |
966 | valid as an address register. | |
08a9dd06 | 967 | |
968 | If the location is not addressable, but does not have one of the | |
969 | above forms, assign a stack slot. We have to do this to avoid the | |
970 | potential of producing lots of reloads if, e.g., a location involves | |
971 | a pseudo that didn't get a hard register and has an equivalent memory | |
972 | location that also involves a pseudo that didn't get a hard register. | |
973 | ||
974 | Perhaps at some point we will improve reload_when_needed handling | |
975 | so this problem goes away. But that's very hairy. */ | |
976 | ||
977 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
978 | if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) | |
979 | { | |
6182a80f | 980 | rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); |
08a9dd06 | 981 | |
982 | if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), | |
983 | XEXP (x, 0))) | |
984 | reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; | |
695ea1b4 | 985 | else if (CONSTANT_P (XEXP (x, 0)) |
8ad4c111 | 986 | || (REG_P (XEXP (x, 0)) |
37690010 | 987 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) |
08a9dd06 | 988 | || (GET_CODE (XEXP (x, 0)) == PLUS |
8ad4c111 | 989 | && REG_P (XEXP (XEXP (x, 0), 0)) |
08a9dd06 | 990 | && (REGNO (XEXP (XEXP (x, 0), 0)) |
991 | < FIRST_PSEUDO_REGISTER) | |
695ea1b4 | 992 | && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) |
08a9dd06 | 993 | reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; |
994 | else | |
995 | { | |
996 | /* Make a new stack slot. Then indicate that something | |
c8ad158d | 997 | changed so we go back and recompute offsets for |
08a9dd06 | 998 | eliminable registers because the allocation of memory |
999 | below might change some offset. reg_equiv_{mem,address} | |
1000 | will be set up for this pseudo on the next pass around | |
1001 | the loop. */ | |
1002 | reg_equiv_memory_loc[i] = 0; | |
1003 | reg_equiv_init[i] = 0; | |
1004 | alter_reg (i, -1); | |
08a9dd06 | 1005 | } |
1006 | } | |
c8ad158d | 1007 | |
e546118a | 1008 | if (caller_save_needed) |
1009 | setup_save_areas (); | |
1010 | ||
dab171c5 | 1011 | /* If we allocated another stack slot, redo elimination bookkeeping. */ |
e546118a | 1012 | if (starting_frame_size != get_frame_size ()) |
08a9dd06 | 1013 | continue; |
65e83e60 | 1014 | if (starting_frame_size && cfun->stack_alignment_needed) |
1015 | { | |
1016 | /* If we have a stack frame, we must align it now. The | |
1017 | stack size may be a part of the offset computation for | |
1018 | register elimination. So if this changes the stack size, | |
1019 | then repeat the elimination bookkeeping. We don't | |
1020 | realign when there is no stack, as that will cause a | |
1021 | stack frame when none is needed should | |
1022 | STARTING_FRAME_OFFSET not be already aligned to | |
1023 | STACK_BOUNDARY. */ | |
1024 | assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed); | |
1025 | if (starting_frame_size != get_frame_size ()) | |
1026 | continue; | |
1027 | } | |
08a9dd06 | 1028 | |
e546118a | 1029 | if (caller_save_needed) |
ca9902fc | 1030 | { |
e546118a | 1031 | save_call_clobbered_regs (); |
1032 | /* That might have allocated new insn_chain structures. */ | |
f0af5a88 | 1033 | reload_firstobj = obstack_alloc (&reload_obstack, 0); |
ca9902fc | 1034 | } |
1035 | ||
dab171c5 | 1036 | calculate_needs_all_insns (global); |
1037 | ||
fbf51e51 | 1038 | CLEAR_REG_SET (&spilled_pseudos); |
dab171c5 | 1039 | did_spill = 0; |
1040 | ||
1041 | something_changed = 0; | |
08a9dd06 | 1042 | |
c538053c | 1043 | /* If we allocated any new memory locations, make another pass |
1044 | since it might have changed elimination offsets. */ | |
1045 | if (starting_frame_size != get_frame_size ()) | |
1046 | something_changed = 1; | |
1047 | ||
ba0fef14 | 1048 | /* Even if the frame size remained the same, we might still have |
1049 | changed elimination offsets, e.g. if find_reloads called | |
1050 | force_const_mem requiring the back end to allocate a constant | |
1051 | pool base register that needs to be saved on the stack. */ | |
1052 | else if (!verify_initial_elim_offsets ()) | |
1053 | something_changed = 1; | |
1054 | ||
9d24e570 | 1055 | { |
1056 | HARD_REG_SET to_spill; | |
1057 | CLEAR_HARD_REG_SET (to_spill); | |
1058 | update_eliminables (&to_spill); | |
7e806a89 | 1059 | AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill); |
0aacf12c | 1060 | |
9d24e570 | 1061 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1062 | if (TEST_HARD_REG_BIT (to_spill, i)) | |
08a9dd06 | 1063 | { |
bfd0ee98 | 1064 | spill_hard_reg (i, 1); |
dab171c5 | 1065 | did_spill = 1; |
60e28df3 | 1066 | |
1067 | /* Regardless of the state of spills, if we previously had | |
8c2e6a91 | 1068 | a register that we thought we could eliminate, but now can |
60e28df3 | 1069 | not eliminate, we must run another pass. |
1070 | ||
1071 | Consider pseudos which have an entry in reg_equiv_* which | |
1072 | reference an eliminable register. We must make another pass | |
1073 | to update reg_equiv_* so that we do not substitute in the | |
1074 | old value from when we thought the elimination could be | |
1075 | performed. */ | |
1076 | something_changed = 1; | |
08a9dd06 | 1077 | } |
9d24e570 | 1078 | } |
0394c2e6 | 1079 | |
bfd0ee98 | 1080 | select_reload_regs (); |
497a7b01 | 1081 | if (failure) |
1082 | goto failed; | |
e546118a | 1083 | |
497a7b01 | 1084 | if (insns_need_reload != 0 || did_spill) |
bfd0ee98 | 1085 | something_changed |= finish_spills (global); |
590ec786 | 1086 | |
dab171c5 | 1087 | if (! something_changed) |
1088 | break; | |
1089 | ||
1090 | if (caller_save_needed) | |
590ec786 | 1091 | delete_caller_save_insns (); |
fbf51e51 | 1092 | |
1093 | obstack_free (&reload_obstack, reload_firstobj); | |
08a9dd06 | 1094 | } |
1095 | ||
1096 | /* If global-alloc was run, notify it of any register eliminations we have | |
1097 | done. */ | |
1098 | if (global) | |
1099 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1100 | if (ep->can_eliminate) | |
1101 | mark_elimination (ep->from, ep->to); | |
1102 | ||
08a9dd06 | 1103 | /* If a pseudo has no hard reg, delete the insns that made the equivalence. |
1104 | If that insn didn't set the register (i.e., it copied the register to | |
1105 | memory), just delete that insn instead of the equivalencing insn plus | |
1106 | anything now dead. If we call delete_dead_insn on that insn, we may | |
537e8d9c | 1107 | delete the insn that actually sets the register if the register dies |
08a9dd06 | 1108 | there and that is incorrect. */ |
1109 | ||
1110 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
537e8d9c | 1111 | { |
1112 | if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) | |
1113 | { | |
1114 | rtx list; | |
1115 | for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) | |
1116 | { | |
1117 | rtx equiv_insn = XEXP (list, 0); | |
77f78a8f | 1118 | |
1119 | /* If we already deleted the insn or if it may trap, we can't | |
1120 | delete it. The latter case shouldn't happen, but can | |
1121 | if an insn has a variable address, gets a REG_EH_REGION | |
77aa6362 | 1122 | note added to it, and then gets converted into a load |
77f78a8f | 1123 | from a constant address. */ |
6d7dc5b9 | 1124 | if (NOTE_P (equiv_insn) |
77f78a8f | 1125 | || can_throw_internal (equiv_insn)) |
1126 | ; | |
1127 | else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) | |
537e8d9c | 1128 | delete_dead_insn (equiv_insn); |
1129 | else | |
7bd3dcc4 | 1130 | SET_INSN_DELETED (equiv_insn); |
537e8d9c | 1131 | } |
1132 | } | |
1133 | } | |
08a9dd06 | 1134 | |
1135 | /* Use the reload registers where necessary | |
1136 | by generating move instructions to move the must-be-register | |
1137 | values into or out of the reload registers. */ | |
1138 | ||
dab171c5 | 1139 | if (insns_need_reload != 0 || something_needs_elimination |
1140 | || something_needs_operands_changed) | |
8ad9ded8 | 1141 | { |
4728a88d | 1142 | HOST_WIDE_INT old_frame_size = get_frame_size (); |
8ad9ded8 | 1143 | |
bfd0ee98 | 1144 | reload_as_needed (global); |
8ad9ded8 | 1145 | |
04e579b6 | 1146 | gcc_assert (old_frame_size == get_frame_size ()); |
8ad9ded8 | 1147 | |
ba0fef14 | 1148 | gcc_assert (verify_initial_elim_offsets ()); |
8ad9ded8 | 1149 | } |
08a9dd06 | 1150 | |
6631552e | 1151 | /* If we were able to eliminate the frame pointer, show that it is no |
81d0fbb3 | 1152 | longer live at the start of any basic block. If it ls live by |
6631552e | 1153 | virtue of being in a pseudo, that pseudo will be marked live |
1154 | and hence the frame pointer will be known to be live via that | |
1155 | pseudo. */ | |
1156 | ||
1157 | if (! frame_pointer_needed) | |
4c26117a | 1158 | FOR_EACH_BB (bb) |
3072d30e | 1159 | { |
1160 | bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM); | |
1161 | bitmap_clear_bit (df_get_live_top (bb), HARD_FRAME_POINTER_REGNUM); | |
1162 | } | |
1163 | ||
1fa3a8f6 | 1164 | /* Come here (with failure set nonzero) if we can't get enough spill |
1165 | regs. */ | |
2e756f7d | 1166 | failed: |
1167 | ||
fbf51e51 | 1168 | CLEAR_REG_SET (&spilled_pseudos); |
f905c47c | 1169 | reload_in_progress = 0; |
1170 | ||
08a9dd06 | 1171 | /* Now eliminate all pseudo regs by modifying them into |
1172 | their equivalent memory references. | |
1173 | The REG-rtx's for the pseudos are modified in place, | |
1174 | so all insns that used to refer to them now refer to memory. | |
1175 | ||
1176 | For a reg that has a reg_equiv_address, all those insns | |
1177 | were changed by reloading so that no insns refer to it any longer; | |
1178 | but the DECL_RTL of a variable decl may refer to it, | |
1179 | and if so this causes the debugging info to mention the variable. */ | |
1180 | ||
1181 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1182 | { | |
1183 | rtx addr = 0; | |
9e042f31 | 1184 | |
1185 | if (reg_equiv_mem[i]) | |
1186 | addr = XEXP (reg_equiv_mem[i], 0); | |
1187 | ||
08a9dd06 | 1188 | if (reg_equiv_address[i]) |
1189 | addr = reg_equiv_address[i]; | |
9e042f31 | 1190 | |
08a9dd06 | 1191 | if (addr) |
1192 | { | |
1193 | if (reg_renumber[i] < 0) | |
1194 | { | |
1195 | rtx reg = regno_reg_rtx[i]; | |
c6259b83 | 1196 | |
e7f75e15 | 1197 | REG_USERVAR_P (reg) = 0; |
25999090 | 1198 | PUT_CODE (reg, MEM); |
08a9dd06 | 1199 | XEXP (reg, 0) = addr; |
c6259b83 | 1200 | if (reg_equiv_memory_loc[i]) |
1201 | MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]); | |
1202 | else | |
1203 | { | |
b04fab2a | 1204 | MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0; |
c6259b83 | 1205 | MEM_ATTRS (reg) = 0; |
1206 | } | |
43283c91 | 1207 | MEM_NOTRAP_P (reg) = 1; |
08a9dd06 | 1208 | } |
1209 | else if (reg_equiv_mem[i]) | |
1210 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1211 | } | |
1212 | } | |
1213 | ||
8648fb5b | 1214 | /* We must set reload_completed now since the cleanup_subreg_operands call |
1215 | below will re-recognize each insn and reload may have generated insns | |
1216 | which are only valid during and after reload. */ | |
1217 | reload_completed = 1; | |
1218 | ||
631ef7ce | 1219 | /* Make a pass over all the insns and delete all USEs which we inserted |
1220 | only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED | |
8516f6b0 | 1221 | notes. Delete all CLOBBER insns, except those that refer to the return |
1222 | value and the special mem:BLK CLOBBERs added to prevent the scheduler | |
1223 | from misarranging variable-array code, and simplify (subreg (reg)) | |
62ede483 | 1224 | operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they |
1225 | are no longer useful or accurate. Strip and regenerate REG_INC notes | |
1226 | that may have been moved around. */ | |
08a9dd06 | 1227 | |
1228 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
9204e736 | 1229 | if (INSN_P (insn)) |
08a9dd06 | 1230 | { |
3f4d644c | 1231 | rtx *pnote; |
08a9dd06 | 1232 | |
6d7dc5b9 | 1233 | if (CALL_P (insn)) |
d5f9786f | 1234 | replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn), |
1235 | VOIDmode, CALL_INSN_FUNCTION_USAGE (insn)); | |
ddaf7ad3 | 1236 | |
d740a1dd | 1237 | if ((GET_CODE (PATTERN (insn)) == USE |
b2920130 | 1238 | /* We mark with QImode USEs introduced by reload itself. */ |
1239 | && (GET_MODE (insn) == QImode | |
1240 | || find_reg_note (insn, REG_EQUAL, NULL_RTX))) | |
631ef7ce | 1241 | || (GET_CODE (PATTERN (insn)) == CLOBBER |
e16ceb8e | 1242 | && (!MEM_P (XEXP (PATTERN (insn), 0)) |
8516f6b0 | 1243 | || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode |
1244 | || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH | |
3ad4992f | 1245 | && XEXP (XEXP (PATTERN (insn), 0), 0) |
8516f6b0 | 1246 | != stack_pointer_rtx)) |
8ad4c111 | 1247 | && (!REG_P (XEXP (PATTERN (insn), 0)) |
631ef7ce | 1248 | || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) |
6aed5e78 | 1249 | { |
7b15bb79 | 1250 | delete_insn (insn); |
6aed5e78 | 1251 | continue; |
1252 | } | |
3f4d644c | 1253 | |
d5f9786f | 1254 | /* Some CLOBBERs may survive until here and still reference unassigned |
1255 | pseudos with const equivalent, which may in turn cause ICE in later | |
1256 | passes if the reference remains in place. */ | |
1257 | if (GET_CODE (PATTERN (insn)) == CLOBBER) | |
1258 | replace_pseudos_in (& XEXP (PATTERN (insn), 0), | |
1259 | VOIDmode, PATTERN (insn)); | |
1260 | ||
eafdc6c2 | 1261 | /* Discard obvious no-ops, even without -O. This optimization |
1262 | is fast and doesn't interfere with debugging. */ | |
1263 | if (NONJUMP_INSN_P (insn) | |
1264 | && GET_CODE (PATTERN (insn)) == SET | |
1265 | && REG_P (SET_SRC (PATTERN (insn))) | |
1266 | && REG_P (SET_DEST (PATTERN (insn))) | |
1267 | && (REGNO (SET_SRC (PATTERN (insn))) | |
1268 | == REGNO (SET_DEST (PATTERN (insn))))) | |
1269 | { | |
1270 | delete_insn (insn); | |
1271 | continue; | |
1272 | } | |
1273 | ||
3f4d644c | 1274 | pnote = ®_NOTES (insn); |
1275 | while (*pnote != 0) | |
08a9dd06 | 1276 | { |
3f4d644c | 1277 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
881c3cf0 | 1278 | || REG_NOTE_KIND (*pnote) == REG_UNUSED |
c4f0a530 | 1279 | || REG_NOTE_KIND (*pnote) == REG_INC |
881c3cf0 | 1280 | || REG_NOTE_KIND (*pnote) == REG_RETVAL |
3072d30e | 1281 | || REG_NOTE_KIND (*pnote) == REG_LIBCALL_ID |
881c3cf0 | 1282 | || REG_NOTE_KIND (*pnote) == REG_LIBCALL) |
3f4d644c | 1283 | *pnote = XEXP (*pnote, 1); |
1284 | else | |
1285 | pnote = &XEXP (*pnote, 1); | |
08a9dd06 | 1286 | } |
d740a1dd | 1287 | |
c4f0a530 | 1288 | #ifdef AUTO_INC_DEC |
1289 | add_auto_inc_notes (insn, PATTERN (insn)); | |
1290 | #endif | |
1291 | ||
3d8785bc | 1292 | /* Simplify (subreg (reg)) if it appears as an operand. */ |
d740a1dd | 1293 | cleanup_subreg_operands (insn); |
3d8785bc | 1294 | |
1295 | /* Clean up invalid ASMs so that they don't confuse later passes. | |
1296 | See PR 21299. */ | |
1297 | if (asm_noperands (PATTERN (insn)) >= 0) | |
1298 | { | |
1299 | extract_insn (insn); | |
1300 | if (!constrain_operands (1)) | |
1301 | { | |
1302 | error_for_asm (insn, | |
1303 | "%<asm%> operand has impossible constraints"); | |
1304 | delete_insn (insn); | |
1305 | continue; | |
1306 | } | |
1307 | } | |
6aed5e78 | 1308 | } |
08a9dd06 | 1309 | |
be2828ce | 1310 | /* If we are doing stack checking, give a warning if this function's |
1311 | frame size is larger than we expect. */ | |
1312 | if (flag_stack_check && ! STACK_CHECK_BUILTIN) | |
1313 | { | |
1314 | HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; | |
5bb2f919 | 1315 | static int verbose_warned = 0; |
1316 | ||
be2828ce | 1317 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
3072d30e | 1318 | if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i]) |
be2828ce | 1319 | size += UNITS_PER_WORD; |
1320 | ||
1321 | if (size > STACK_CHECK_MAX_FRAME_SIZE) | |
5bb2f919 | 1322 | { |
c3ceba8e | 1323 | warning (0, "frame size too large for reliable stack checking"); |
be2828ce | 1324 | if (! verbose_warned) |
1325 | { | |
c3ceba8e | 1326 | warning (0, "try reducing the number of local variables"); |
be2828ce | 1327 | verbose_warned = 1; |
1328 | } | |
1329 | } | |
1330 | } | |
1331 | ||
08a9dd06 | 1332 | /* Indicate that we no longer have known memory locations or constants. */ |
77210fa2 | 1333 | if (reg_equiv_constant) |
1334 | free (reg_equiv_constant); | |
2e4905ea | 1335 | if (reg_equiv_invariant) |
1336 | free (reg_equiv_invariant); | |
08a9dd06 | 1337 | reg_equiv_constant = 0; |
2e4905ea | 1338 | reg_equiv_invariant = 0; |
28b69ba9 | 1339 | VEC_free (rtx, gc, reg_equiv_memory_loc_vec); |
08a9dd06 | 1340 | reg_equiv_memory_loc = 0; |
2e756f7d | 1341 | |
2ff147ce | 1342 | if (offsets_known_at) |
1343 | free (offsets_known_at); | |
1344 | if (offsets_at) | |
1345 | free (offsets_at); | |
6dd870f4 | 1346 | |
d51b37c2 | 1347 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1348 | if (reg_equiv_alt_mem_list[i]) | |
1349 | free_EXPR_LIST_list (®_equiv_alt_mem_list[i]); | |
1350 | free (reg_equiv_alt_mem_list); | |
1351 | ||
829c0ce9 | 1352 | free (reg_equiv_mem); |
d5058a95 | 1353 | reg_equiv_init = 0; |
829c0ce9 | 1354 | free (reg_equiv_address); |
1355 | free (reg_max_ref_width); | |
dab171c5 | 1356 | free (reg_old_renumber); |
1357 | free (pseudo_previous_regs); | |
1358 | free (pseudo_forbidden_regs); | |
829c0ce9 | 1359 | |
ed69f33f | 1360 | CLEAR_HARD_REG_SET (used_spill_regs); |
1361 | for (i = 0; i < n_spills; i++) | |
1362 | SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); | |
1363 | ||
590ec786 | 1364 | /* Free all the insn_chain structures at once. */ |
1365 | obstack_free (&reload_obstack, reload_startobj); | |
1366 | unused_insn_chains = 0; | |
2f0bfe72 | 1367 | fixup_abnormal_edges (); |
590ec786 | 1368 | |
907bb1cf | 1369 | /* Replacing pseudos with their memory equivalents might have |
1370 | created shared rtx. Subsequent passes would get confused | |
1371 | by this, so unshare everything here. */ | |
1372 | unshare_all_rtl_again (first); | |
1373 | ||
23d75d32 | 1374 | #ifdef STACK_BOUNDARY |
1375 | /* init_emit has set the alignment of the hard frame pointer | |
1376 | to STACK_BOUNDARY. It is very likely no longer valid if | |
1377 | the hard frame pointer was used for register allocation. */ | |
1378 | if (!frame_pointer_needed) | |
1379 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; | |
1380 | #endif | |
1381 | ||
2e756f7d | 1382 | return failure; |
08a9dd06 | 1383 | } |
1aacee06 | 1384 | |
faf8dbee | 1385 | /* Yet another special case. Unfortunately, reg-stack forces people to |
1386 | write incorrect clobbers in asm statements. These clobbers must not | |
1387 | cause the register to appear in bad_spill_regs, otherwise we'll call | |
1388 | fatal_insn later. We clear the corresponding regnos in the live | |
1389 | register sets to avoid this. | |
1390 | The whole thing is rather sick, I'm afraid. */ | |
d6cb6164 | 1391 | |
faf8dbee | 1392 | static void |
3ad4992f | 1393 | maybe_fix_stack_asms (void) |
faf8dbee | 1394 | { |
1395 | #ifdef STACK_REGS | |
6c645607 | 1396 | const char *constraints[MAX_RECOG_OPERANDS]; |
faf8dbee | 1397 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
1398 | struct insn_chain *chain; | |
1399 | ||
1400 | for (chain = reload_insn_chain; chain != 0; chain = chain->next) | |
1401 | { | |
1402 | int i, noperands; | |
1403 | HARD_REG_SET clobbered, allowed; | |
1404 | rtx pat; | |
1405 | ||
9204e736 | 1406 | if (! INSN_P (chain->insn) |
faf8dbee | 1407 | || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) |
1408 | continue; | |
1409 | pat = PATTERN (chain->insn); | |
1410 | if (GET_CODE (pat) != PARALLEL) | |
1411 | continue; | |
1412 | ||
1413 | CLEAR_HARD_REG_SET (clobbered); | |
1414 | CLEAR_HARD_REG_SET (allowed); | |
1415 | ||
1416 | /* First, make a mask of all stack regs that are clobbered. */ | |
1417 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
1418 | { | |
1419 | rtx t = XVECEXP (pat, 0, i); | |
1420 | if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) | |
1421 | SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); | |
1422 | } | |
1423 | ||
1424 | /* Get the operand values and constraints out of the insn. */ | |
ed420a25 | 1425 | decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, |
09fb10e8 | 1426 | constraints, operand_mode, NULL); |
faf8dbee | 1427 | |
1428 | /* For every operand, see what registers are allowed. */ | |
1429 | for (i = 0; i < noperands; i++) | |
1430 | { | |
9d161652 | 1431 | const char *p = constraints[i]; |
faf8dbee | 1432 | /* For every alternative, we compute the class of registers allowed |
1433 | for reloading in CLS, and merge its contents into the reg set | |
1434 | ALLOWED. */ | |
1435 | int cls = (int) NO_REGS; | |
1436 | ||
1437 | for (;;) | |
1438 | { | |
48ea5577 | 1439 | char c = *p; |
faf8dbee | 1440 | |
1441 | if (c == '\0' || c == ',' || c == '#') | |
1442 | { | |
1443 | /* End of one alternative - mark the regs in the current | |
1444 | class, and reset the class. */ | |
1445 | IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); | |
1446 | cls = NO_REGS; | |
48ea5577 | 1447 | p++; |
faf8dbee | 1448 | if (c == '#') |
1449 | do { | |
1450 | c = *p++; | |
1451 | } while (c != '\0' && c != ','); | |
1452 | if (c == '\0') | |
1453 | break; | |
1454 | continue; | |
1455 | } | |
1456 | ||
1457 | switch (c) | |
1458 | { | |
1459 | case '=': case '+': case '*': case '%': case '?': case '!': | |
1460 | case '0': case '1': case '2': case '3': case '4': case 'm': | |
1461 | case '<': case '>': case 'V': case 'o': case '&': case 'E': | |
1462 | case 'F': case 's': case 'i': case 'n': case 'X': case 'I': | |
1463 | case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': | |
1464 | case 'P': | |
faf8dbee | 1465 | break; |
1466 | ||
1467 | case 'p': | |
2e6d14e8 | 1468 | cls = (int) reg_class_subunion[cls] |
00cb30dc | 1469 | [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; |
faf8dbee | 1470 | break; |
1471 | ||
1472 | case 'g': | |
1473 | case 'r': | |
1474 | cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; | |
1475 | break; | |
1476 | ||
1477 | default: | |
48ea5577 | 1478 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) |
a5004c3d | 1479 | cls = (int) reg_class_subunion[cls] |
00cb30dc | 1480 | [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; |
a5004c3d | 1481 | else |
1482 | cls = (int) reg_class_subunion[cls] | |
48ea5577 | 1483 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; |
faf8dbee | 1484 | } |
48ea5577 | 1485 | p += CONSTRAINT_LEN (c, p); |
faf8dbee | 1486 | } |
1487 | } | |
1488 | /* Those of the registers which are clobbered, but allowed by the | |
1489 | constraints, must be usable as reload registers. So clear them | |
1490 | out of the life information. */ | |
1491 | AND_HARD_REG_SET (allowed, clobbered); | |
1492 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1493 | if (TEST_HARD_REG_BIT (allowed, i)) | |
1494 | { | |
f62c22a7 | 1495 | CLEAR_REGNO_REG_SET (&chain->live_throughout, i); |
1496 | CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); | |
faf8dbee | 1497 | } |
1498 | } | |
1499 | ||
1500 | #endif | |
1501 | } | |
dab171c5 | 1502 | \f |
fbf51e51 | 1503 | /* Copy the global variables n_reloads and rld into the corresponding elts |
1504 | of CHAIN. */ | |
1505 | static void | |
3ad4992f | 1506 | copy_reloads (struct insn_chain *chain) |
fbf51e51 | 1507 | { |
1508 | chain->n_reloads = n_reloads; | |
f0af5a88 | 1509 | chain->rld = obstack_alloc (&reload_obstack, |
1510 | n_reloads * sizeof (struct reload)); | |
fbf51e51 | 1511 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
f0af5a88 | 1512 | reload_insn_firstobj = obstack_alloc (&reload_obstack, 0); |
fbf51e51 | 1513 | } |
1514 | ||
dab171c5 | 1515 | /* Walk the chain of insns, and determine for each whether it needs reloads |
1516 | and/or eliminations. Build the corresponding insns_need_reload list, and | |
1517 | set something_needs_elimination as appropriate. */ | |
1518 | static void | |
3ad4992f | 1519 | calculate_needs_all_insns (int global) |
1aacee06 | 1520 | { |
590ec786 | 1521 | struct insn_chain **pprev_reload = &insns_need_reload; |
7a45336a | 1522 | struct insn_chain *chain, *next = 0; |
1aacee06 | 1523 | |
dab171c5 | 1524 | something_needs_elimination = 0; |
1525 | ||
f0af5a88 | 1526 | reload_insn_firstobj = obstack_alloc (&reload_obstack, 0); |
7a45336a | 1527 | for (chain = reload_insn_chain; chain != 0; chain = next) |
1aacee06 | 1528 | { |
456b6b44 | 1529 | rtx insn = chain->insn; |
dab171c5 | 1530 | |
7a45336a | 1531 | next = chain->next; |
1532 | ||
fbf51e51 | 1533 | /* Clear out the shortcuts. */ |
1534 | chain->n_reloads = 0; | |
456b6b44 | 1535 | chain->need_elim = 0; |
1536 | chain->need_reload = 0; | |
1537 | chain->need_operand_change = 0; | |
1aacee06 | 1538 | |
dab171c5 | 1539 | /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might |
1540 | include REG_LABEL), we need to see what effects this has on the | |
1541 | known offsets at labels. */ | |
1aacee06 | 1542 | |
6d7dc5b9 | 1543 | if (LABEL_P (insn) || JUMP_P (insn) |
9204e736 | 1544 | || (INSN_P (insn) && REG_NOTES (insn) != 0)) |
1aacee06 | 1545 | set_label_offsets (insn, insn, 0); |
1546 | ||
9204e736 | 1547 | if (INSN_P (insn)) |
1aacee06 | 1548 | { |
1549 | rtx old_body = PATTERN (insn); | |
1550 | int old_code = INSN_CODE (insn); | |
1551 | rtx old_notes = REG_NOTES (insn); | |
1552 | int did_elimination = 0; | |
93c7b06e | 1553 | int operands_changed = 0; |
aa8d28af | 1554 | rtx set = single_set (insn); |
1555 | ||
1556 | /* Skip insns that only set an equivalence. */ | |
8ad4c111 | 1557 | if (set && REG_P (SET_DEST (set)) |
aa8d28af | 1558 | && reg_renumber[REGNO (SET_DEST (set))] < 0 |
2e4905ea | 1559 | && (reg_equiv_constant[REGNO (SET_DEST (set))] |
1560 | || (reg_equiv_invariant[REGNO (SET_DEST (set))])) | |
1561 | && reg_equiv_init[REGNO (SET_DEST (set))]) | |
456b6b44 | 1562 | continue; |
1aacee06 | 1563 | |
1aacee06 | 1564 | /* If needed, eliminate any eliminable registers. */ |
aa8d28af | 1565 | if (num_eliminable || num_eliminable_invariants) |
1aacee06 | 1566 | did_elimination = eliminate_regs_in_insn (insn, 0); |
1567 | ||
1568 | /* Analyze the instruction. */ | |
93c7b06e | 1569 | operands_changed = find_reloads (insn, 0, spill_indirect_levels, |
1570 | global, spill_reg_order); | |
1571 | ||
1572 | /* If a no-op set needs more than one reload, this is likely | |
1573 | to be something that needs input address reloads. We | |
1574 | can't get rid of this cleanly later, and it is of no use | |
1575 | anyway, so discard it now. | |
1576 | We only do this when expensive_optimizations is enabled, | |
1577 | since this complements reload inheritance / output | |
1578 | reload deletion, and it can make debugging harder. */ | |
1579 | if (flag_expensive_optimizations && n_reloads > 1) | |
1580 | { | |
1581 | rtx set = single_set (insn); | |
1582 | if (set | |
1583 | && SET_SRC (set) == SET_DEST (set) | |
8ad4c111 | 1584 | && REG_P (SET_SRC (set)) |
93c7b06e | 1585 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) |
1586 | { | |
b36d64df | 1587 | delete_insn (insn); |
45498ea1 | 1588 | /* Delete it from the reload chain. */ |
7a45336a | 1589 | if (chain->prev) |
1590 | chain->prev->next = next; | |
1591 | else | |
1592 | reload_insn_chain = next; | |
1593 | if (next) | |
1594 | next->prev = chain->prev; | |
1595 | chain->next = unused_insn_chains; | |
1596 | unused_insn_chains = chain; | |
93c7b06e | 1597 | continue; |
1598 | } | |
1599 | } | |
1600 | if (num_eliminable) | |
1601 | update_eliminable_offsets (); | |
1aacee06 | 1602 | |
1603 | /* Remember for later shortcuts which insns had any reloads or | |
590ec786 | 1604 | register eliminations. */ |
1605 | chain->need_elim = did_elimination; | |
dab171c5 | 1606 | chain->need_reload = n_reloads > 0; |
1607 | chain->need_operand_change = operands_changed; | |
1aacee06 | 1608 | |
1609 | /* Discard any register replacements done. */ | |
1610 | if (did_elimination) | |
1611 | { | |
fbf51e51 | 1612 | obstack_free (&reload_obstack, reload_insn_firstobj); |
1aacee06 | 1613 | PATTERN (insn) = old_body; |
1614 | INSN_CODE (insn) = old_code; | |
1615 | REG_NOTES (insn) = old_notes; | |
1616 | something_needs_elimination = 1; | |
1617 | } | |
1618 | ||
93c7b06e | 1619 | something_needs_operands_changed |= operands_changed; |
1620 | ||
e546118a | 1621 | if (n_reloads != 0) |
590ec786 | 1622 | { |
fbf51e51 | 1623 | copy_reloads (chain); |
590ec786 | 1624 | *pprev_reload = chain; |
1625 | pprev_reload = &chain->next_need_reload; | |
590ec786 | 1626 | } |
1aacee06 | 1627 | } |
1aacee06 | 1628 | } |
590ec786 | 1629 | *pprev_reload = 0; |
1aacee06 | 1630 | } |
fbf51e51 | 1631 | \f |
1632 | /* Comparison function for qsort to decide which of two reloads | |
1633 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
1aacee06 | 1634 | |
fbf51e51 | 1635 | static int |
3ad4992f | 1636 | reload_reg_class_lower (const void *r1p, const void *r2p) |
1aacee06 | 1637 | { |
19cb6b50 | 1638 | int r1 = *(const short *) r1p, r2 = *(const short *) r2p; |
1639 | int t; | |
1aacee06 | 1640 | |
fbf51e51 | 1641 | /* Consider required reloads before optional ones. */ |
1642 | t = rld[r1].optional - rld[r2].optional; | |
1643 | if (t != 0) | |
1644 | return t; | |
1aacee06 | 1645 | |
fbf51e51 | 1646 | /* Count all solitary classes before non-solitary ones. */ |
1647 | t = ((reg_class_size[(int) rld[r2].class] == 1) | |
1648 | - (reg_class_size[(int) rld[r1].class] == 1)); | |
1649 | if (t != 0) | |
1650 | return t; | |
1aacee06 | 1651 | |
fbf51e51 | 1652 | /* Aside from solitaires, consider all multi-reg groups first. */ |
1653 | t = rld[r2].nregs - rld[r1].nregs; | |
1654 | if (t != 0) | |
1655 | return t; | |
1aacee06 | 1656 | |
fbf51e51 | 1657 | /* Consider reloads in order of increasing reg-class number. */ |
1658 | t = (int) rld[r1].class - (int) rld[r2].class; | |
1659 | if (t != 0) | |
1660 | return t; | |
1aacee06 | 1661 | |
fbf51e51 | 1662 | /* If reloads are equally urgent, sort by reload number, |
1663 | so that the results of qsort leave nothing to chance. */ | |
1664 | return r1 - r2; | |
1665 | } | |
1666 | \f | |
1667 | /* The cost of spilling each hard reg. */ | |
1668 | static int spill_cost[FIRST_PSEUDO_REGISTER]; | |
1aacee06 | 1669 | |
fbf51e51 | 1670 | /* When spilling multiple hard registers, we use SPILL_COST for the first |
1671 | spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST | |
1672 | only the first hard reg for a multi-reg pseudo. */ | |
1673 | static int spill_add_cost[FIRST_PSEUDO_REGISTER]; | |
1aacee06 | 1674 | |
fbf51e51 | 1675 | /* Update the spill cost arrays, considering that pseudo REG is live. */ |
02e7a332 | 1676 | |
fbf51e51 | 1677 | static void |
3ad4992f | 1678 | count_pseudo (int reg) |
fbf51e51 | 1679 | { |
63f23608 | 1680 | int freq = REG_FREQ (reg); |
fbf51e51 | 1681 | int r = reg_renumber[reg]; |
1682 | int nregs; | |
1aacee06 | 1683 | |
fbf51e51 | 1684 | if (REGNO_REG_SET_P (&pseudos_counted, reg) |
1685 | || REGNO_REG_SET_P (&spilled_pseudos, reg)) | |
1686 | return; | |
1aacee06 | 1687 | |
fbf51e51 | 1688 | SET_REGNO_REG_SET (&pseudos_counted, reg); |
1aacee06 | 1689 | |
04e579b6 | 1690 | gcc_assert (r >= 0); |
aedd3e94 | 1691 | |
63f23608 | 1692 | spill_add_cost[r] += freq; |
1aacee06 | 1693 | |
67d6c12b | 1694 | nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)]; |
fbf51e51 | 1695 | while (nregs-- > 0) |
63f23608 | 1696 | spill_cost[r + nregs] += freq; |
fbf51e51 | 1697 | } |
1aacee06 | 1698 | |
fbf51e51 | 1699 | /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the |
1700 | contents of BAD_SPILL_REGS for the insn described by CHAIN. */ | |
d6cb6164 | 1701 | |
fbf51e51 | 1702 | static void |
3ad4992f | 1703 | order_regs_for_reload (struct insn_chain *chain) |
fbf51e51 | 1704 | { |
4f917ffe | 1705 | unsigned i; |
d6cb6164 | 1706 | HARD_REG_SET used_by_pseudos; |
1707 | HARD_REG_SET used_by_pseudos2; | |
8c97cf13 | 1708 | reg_set_iterator rsi; |
1aacee06 | 1709 | |
d6cb6164 | 1710 | COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set); |
1aacee06 | 1711 | |
fbf51e51 | 1712 | memset (spill_cost, 0, sizeof spill_cost); |
1713 | memset (spill_add_cost, 0, sizeof spill_add_cost); | |
1aacee06 | 1714 | |
fbf51e51 | 1715 | /* Count number of uses of each hard reg by pseudo regs allocated to it |
d6cb6164 | 1716 | and then order them by decreasing use. First exclude hard registers |
1717 | that are live in or across this insn. */ | |
1718 | ||
1719 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); | |
1720 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
1721 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos); | |
1722 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2); | |
1aacee06 | 1723 | |
fbf51e51 | 1724 | /* Now find out which pseudos are allocated to it, and update |
1725 | hard_reg_n_uses. */ | |
1726 | CLEAR_REG_SET (&pseudos_counted); | |
1aacee06 | 1727 | |
fbf51e51 | 1728 | EXECUTE_IF_SET_IN_REG_SET |
8c97cf13 | 1729 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi) |
1730 | { | |
1731 | count_pseudo (i); | |
1732 | } | |
fbf51e51 | 1733 | EXECUTE_IF_SET_IN_REG_SET |
8c97cf13 | 1734 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi) |
1735 | { | |
1736 | count_pseudo (i); | |
1737 | } | |
fbf51e51 | 1738 | CLEAR_REG_SET (&pseudos_counted); |
1aacee06 | 1739 | } |
dab171c5 | 1740 | \f |
fbf51e51 | 1741 | /* Vector of reload-numbers showing the order in which the reloads should |
1742 | be processed. */ | |
1743 | static short reload_order[MAX_RELOADS]; | |
1aacee06 | 1744 | |
fbf51e51 | 1745 | /* This is used to keep track of the spill regs used in one insn. */ |
1746 | static HARD_REG_SET used_spill_regs_local; | |
dab171c5 | 1747 | |
fbf51e51 | 1748 | /* We decided to spill hard register SPILLED, which has a size of |
1749 | SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, | |
1750 | is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will | |
1751 | update SPILL_COST/SPILL_ADD_COST. */ | |
02e7a332 | 1752 | |
dab171c5 | 1753 | static void |
3ad4992f | 1754 | count_spilled_pseudo (int spilled, int spilled_nregs, int reg) |
1aacee06 | 1755 | { |
fbf51e51 | 1756 | int r = reg_renumber[reg]; |
67d6c12b | 1757 | int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)]; |
1aacee06 | 1758 | |
fbf51e51 | 1759 | if (REGNO_REG_SET_P (&spilled_pseudos, reg) |
1760 | || spilled + spilled_nregs <= r || r + nregs <= spilled) | |
1761 | return; | |
1aacee06 | 1762 | |
fbf51e51 | 1763 | SET_REGNO_REG_SET (&spilled_pseudos, reg); |
1aacee06 | 1764 | |
63f23608 | 1765 | spill_add_cost[r] -= REG_FREQ (reg); |
fbf51e51 | 1766 | while (nregs-- > 0) |
63f23608 | 1767 | spill_cost[r + nregs] -= REG_FREQ (reg); |
1aacee06 | 1768 | } |
1769 | ||
fbf51e51 | 1770 | /* Find reload register to use for reload number ORDER. */ |
dab171c5 | 1771 | |
fbf51e51 | 1772 | static int |
3ad4992f | 1773 | find_reg (struct insn_chain *chain, int order) |
1aacee06 | 1774 | { |
fbf51e51 | 1775 | int rnum = reload_order[order]; |
1776 | struct reload *rl = rld + rnum; | |
1777 | int best_cost = INT_MAX; | |
1778 | int best_reg = -1; | |
02e7a332 | 1779 | unsigned int i, j; |
1780 | int k; | |
fbf51e51 | 1781 | HARD_REG_SET not_usable; |
1782 | HARD_REG_SET used_by_other_reload; | |
8c97cf13 | 1783 | reg_set_iterator rsi; |
1aacee06 | 1784 | |
fbf51e51 | 1785 | COPY_HARD_REG_SET (not_usable, bad_spill_regs); |
1786 | IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); | |
1787 | IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]); | |
1788 | ||
1789 | CLEAR_HARD_REG_SET (used_by_other_reload); | |
02e7a332 | 1790 | for (k = 0; k < order; k++) |
1aacee06 | 1791 | { |
02e7a332 | 1792 | int other = reload_order[k]; |
1793 | ||
fbf51e51 | 1794 | if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) |
1795 | for (j = 0; j < rld[other].nregs; j++) | |
1796 | SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); | |
1797 | } | |
1aacee06 | 1798 | |
fbf51e51 | 1799 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1800 | { | |
02e7a332 | 1801 | unsigned int regno = i; |
1802 | ||
fbf51e51 | 1803 | if (! TEST_HARD_REG_BIT (not_usable, regno) |
1804 | && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) | |
1805 | && HARD_REGNO_MODE_OK (regno, rl->mode)) | |
1aacee06 | 1806 | { |
fbf51e51 | 1807 | int this_cost = spill_cost[regno]; |
1808 | int ok = 1; | |
67d6c12b | 1809 | unsigned int this_nregs = hard_regno_nregs[regno][rl->mode]; |
1aacee06 | 1810 | |
fbf51e51 | 1811 | for (j = 1; j < this_nregs; j++) |
1812 | { | |
1813 | this_cost += spill_add_cost[regno + j]; | |
1814 | if ((TEST_HARD_REG_BIT (not_usable, regno + j)) | |
1815 | || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) | |
1816 | ok = 0; | |
1817 | } | |
1818 | if (! ok) | |
1819 | continue; | |
8ad4c111 | 1820 | if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno) |
fbf51e51 | 1821 | this_cost--; |
8ad4c111 | 1822 | if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno) |
fbf51e51 | 1823 | this_cost--; |
1824 | if (this_cost < best_cost | |
1825 | /* Among registers with equal cost, prefer caller-saved ones, or | |
1826 | use REG_ALLOC_ORDER if it is defined. */ | |
1827 | || (this_cost == best_cost | |
1828 | #ifdef REG_ALLOC_ORDER | |
1829 | && (inv_reg_alloc_order[regno] | |
1830 | < inv_reg_alloc_order[best_reg]) | |
1831 | #else | |
1832 | && call_used_regs[regno] | |
1833 | && ! call_used_regs[best_reg] | |
1834 | #endif | |
1835 | )) | |
1836 | { | |
1837 | best_reg = regno; | |
1838 | best_cost = this_cost; | |
1aacee06 | 1839 | } |
1840 | } | |
1841 | } | |
fbf51e51 | 1842 | if (best_reg == -1) |
1843 | return 0; | |
02e7a332 | 1844 | |
450d042a | 1845 | if (dump_file) |
1846 | fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum); | |
02e7a332 | 1847 | |
67d6c12b | 1848 | rl->nregs = hard_regno_nregs[best_reg][rl->mode]; |
fbf51e51 | 1849 | rl->regno = best_reg; |
1aacee06 | 1850 | |
fbf51e51 | 1851 | EXECUTE_IF_SET_IN_REG_SET |
8c97cf13 | 1852 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi) |
1853 | { | |
1854 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1855 | } | |
02e7a332 | 1856 | |
fbf51e51 | 1857 | EXECUTE_IF_SET_IN_REG_SET |
8c97cf13 | 1858 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi) |
1859 | { | |
1860 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1861 | } | |
dab171c5 | 1862 | |
fbf51e51 | 1863 | for (i = 0; i < rl->nregs; i++) |
1864 | { | |
04e579b6 | 1865 | gcc_assert (spill_cost[best_reg + i] == 0); |
1866 | gcc_assert (spill_add_cost[best_reg + i] == 0); | |
fbf51e51 | 1867 | SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); |
1868 | } | |
1869 | return 1; | |
dab171c5 | 1870 | } |
1871 | ||
1872 | /* Find more reload regs to satisfy the remaining need of an insn, which | |
1873 | is given by CHAIN. | |
1aacee06 | 1874 | Do it by ascending class number, since otherwise a reg |
1875 | might be spilled for a big class and might fail to count | |
fbf51e51 | 1876 | for a smaller class even though it belongs to that class. */ |
1aacee06 | 1877 | |
dab171c5 | 1878 | static void |
3ad4992f | 1879 | find_reload_regs (struct insn_chain *chain) |
1aacee06 | 1880 | { |
fbf51e51 | 1881 | int i; |
1aacee06 | 1882 | |
fbf51e51 | 1883 | /* In order to be certain of getting the registers we need, |
1884 | we must sort the reloads into order of increasing register class. | |
1885 | Then our grabbing of reload registers will parallel the process | |
1886 | that provided the reload registers. */ | |
1887 | for (i = 0; i < chain->n_reloads; i++) | |
1aacee06 | 1888 | { |
fbf51e51 | 1889 | /* Show whether this reload already has a hard reg. */ |
1890 | if (chain->rld[i].reg_rtx) | |
1aacee06 | 1891 | { |
fbf51e51 | 1892 | int regno = REGNO (chain->rld[i].reg_rtx); |
1893 | chain->rld[i].regno = regno; | |
02e7a332 | 1894 | chain->rld[i].nregs |
67d6c12b | 1895 | = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)]; |
1aacee06 | 1896 | } |
fbf51e51 | 1897 | else |
1898 | chain->rld[i].regno = -1; | |
1899 | reload_order[i] = i; | |
1900 | } | |
1aacee06 | 1901 | |
fbf51e51 | 1902 | n_reloads = chain->n_reloads; |
1903 | memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); | |
1aacee06 | 1904 | |
fbf51e51 | 1905 | CLEAR_HARD_REG_SET (used_spill_regs_local); |
dab171c5 | 1906 | |
450d042a | 1907 | if (dump_file) |
1908 | fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn)); | |
1aacee06 | 1909 | |
fbf51e51 | 1910 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); |
1aacee06 | 1911 | |
fbf51e51 | 1912 | /* Compute the order of preference for hard registers to spill. */ |
1aacee06 | 1913 | |
fbf51e51 | 1914 | order_regs_for_reload (chain); |
1aacee06 | 1915 | |
fbf51e51 | 1916 | for (i = 0; i < n_reloads; i++) |
1917 | { | |
1918 | int r = reload_order[i]; | |
1aacee06 | 1919 | |
fbf51e51 | 1920 | /* Ignore reloads that got marked inoperative. */ |
1921 | if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) | |
1922 | && ! rld[r].optional | |
1923 | && rld[r].regno == -1) | |
bfd0ee98 | 1924 | if (! find_reg (chain, i)) |
fbf51e51 | 1925 | { |
36326827 | 1926 | if (dump_file) |
7e806a89 | 1927 | fprintf (dump_file, "reload failure for reload %d\n", r); |
92b80308 | 1928 | spill_failure (chain->insn, rld[r].class); |
fbf51e51 | 1929 | failure = 1; |
dab171c5 | 1930 | return; |
fbf51e51 | 1931 | } |
1aacee06 | 1932 | } |
5bb2f919 | 1933 | |
fbf51e51 | 1934 | COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local); |
1935 | IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local); | |
dab171c5 | 1936 | |
fbf51e51 | 1937 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
1aacee06 | 1938 | } |
1939 | ||
fbf51e51 | 1940 | static void |
3ad4992f | 1941 | select_reload_regs (void) |
9d24e570 | 1942 | { |
fbf51e51 | 1943 | struct insn_chain *chain; |
9d24e570 | 1944 | |
fbf51e51 | 1945 | /* Try to satisfy the needs for each insn. */ |
1946 | for (chain = insns_need_reload; chain != 0; | |
1947 | chain = chain->next_need_reload) | |
bfd0ee98 | 1948 | find_reload_regs (chain); |
9d24e570 | 1949 | } |
08a9dd06 | 1950 | \f |
e546118a | 1951 | /* Delete all insns that were inserted by emit_caller_save_insns during |
1952 | this iteration. */ | |
1953 | static void | |
3ad4992f | 1954 | delete_caller_save_insns (void) |
e546118a | 1955 | { |
590ec786 | 1956 | struct insn_chain *c = reload_insn_chain; |
e546118a | 1957 | |
590ec786 | 1958 | while (c != 0) |
e546118a | 1959 | { |
590ec786 | 1960 | while (c != 0 && c->is_caller_save_insn) |
e546118a | 1961 | { |
590ec786 | 1962 | struct insn_chain *next = c->next; |
1963 | rtx insn = c->insn; | |
1964 | ||
590ec786 | 1965 | if (c == reload_insn_chain) |
1966 | reload_insn_chain = next; | |
b36d64df | 1967 | delete_insn (insn); |
590ec786 | 1968 | |
1969 | if (next) | |
1970 | next->prev = c->prev; | |
1971 | if (c->prev) | |
1972 | c->prev->next = next; | |
1973 | c->next = unused_insn_chains; | |
1974 | unused_insn_chains = c; | |
1975 | c = next; | |
e546118a | 1976 | } |
590ec786 | 1977 | if (c != 0) |
1978 | c = c->next; | |
e546118a | 1979 | } |
1980 | } | |
1981 | \f | |
2e756f7d | 1982 | /* Handle the failure to find a register to spill. |
1983 | INSN should be one of the insns which needed this particular spill reg. */ | |
1984 | ||
1985 | static void | |
3ad4992f | 1986 | spill_failure (rtx insn, enum reg_class class) |
2e756f7d | 1987 | { |
1988 | if (asm_noperands (PATTERN (insn)) >= 0) | |
eb586f2c | 1989 | error_for_asm (insn, "can't find a register in class %qs while " |
1990 | "reloading %<asm%>", | |
92b80308 | 1991 | reg_class_names[class]); |
2e756f7d | 1992 | else |
92b80308 | 1993 | { |
eb586f2c | 1994 | error ("unable to find a register to spill in class %qs", |
92b80308 | 1995 | reg_class_names[class]); |
36326827 | 1996 | |
1997 | if (dump_file) | |
1998 | { | |
1999 | fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); | |
2000 | debug_reload_to_stream (dump_file); | |
2001 | } | |
cb8bacb6 | 2002 | fatal_insn ("this is the insn:", insn); |
92b80308 | 2003 | } |
2e756f7d | 2004 | } |
08a9dd06 | 2005 | \f |
2006 | /* Delete an unneeded INSN and any previous insns who sole purpose is loading | |
2007 | data that is dead in INSN. */ | |
2008 | ||
2009 | static void | |
3ad4992f | 2010 | delete_dead_insn (rtx insn) |
08a9dd06 | 2011 | { |
2012 | rtx prev = prev_real_insn (insn); | |
2013 | rtx prev_dest; | |
2014 | ||
2015 | /* If the previous insn sets a register that dies in our insn, delete it | |
2016 | too. */ | |
2017 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
8ad4c111 | 2018 | && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest)) |
08a9dd06 | 2019 | && reg_mentioned_p (prev_dest, PATTERN (insn)) |
5d4a682a | 2020 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) |
2021 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
08a9dd06 | 2022 | delete_dead_insn (prev); |
2023 | ||
7bd3dcc4 | 2024 | SET_INSN_DELETED (insn); |
08a9dd06 | 2025 | } |
2026 | ||
2027 | /* Modify the home of pseudo-reg I. | |
2028 | The new home is present in reg_renumber[I]. | |
2029 | ||
2030 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
2031 | or it may be -1, meaning there is none or it is not relevant. | |
2032 | This is used so that all pseudos spilled from a given hard reg | |
2033 | can share one stack slot. */ | |
2034 | ||
2035 | static void | |
3ad4992f | 2036 | alter_reg (int i, int from_reg) |
08a9dd06 | 2037 | { |
2038 | /* When outputting an inline function, this can happen | |
2039 | for a reg that isn't actually used. */ | |
2040 | if (regno_reg_rtx[i] == 0) | |
2041 | return; | |
2042 | ||
2043 | /* If the reg got changed to a MEM at rtl-generation time, | |
2044 | ignore it. */ | |
8ad4c111 | 2045 | if (!REG_P (regno_reg_rtx[i])) |
08a9dd06 | 2046 | return; |
2047 | ||
2048 | /* Modify the reg-rtx to contain the new hard reg | |
2049 | number or else to contain its pseudo reg number. */ | |
3072d30e | 2050 | SET_REGNO (regno_reg_rtx[i], |
2051 | reg_renumber[i] >= 0 ? reg_renumber[i] : i); | |
08a9dd06 | 2052 | |
2053 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
2054 | allocate a stack slot for it. */ | |
2055 | ||
2056 | if (reg_renumber[i] < 0 | |
394685a4 | 2057 | && REG_N_REFS (i) > 0 |
08a9dd06 | 2058 | && reg_equiv_constant[i] == 0 |
2e4905ea | 2059 | && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0) |
08a9dd06 | 2060 | && reg_equiv_memory_loc[i] == 0) |
2061 | { | |
19cb6b50 | 2062 | rtx x; |
595d62e9 | 2063 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); |
02e7a332 | 2064 | unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); |
595d62e9 | 2065 | unsigned int inherent_align = GET_MODE_ALIGNMENT (mode); |
02e7a332 | 2066 | unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]); |
595d62e9 | 2067 | unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT; |
08a9dd06 | 2068 | int adjust = 0; |
2069 | ||
2070 | /* Each pseudo reg has an inherent size which comes from its own mode, | |
2071 | and a total size which provides room for paradoxical subregs | |
2072 | which refer to the pseudo reg in wider modes. | |
2073 | ||
2074 | We can use a slot already allocated if it provides both | |
2075 | enough inherent space and enough total space. | |
2076 | Otherwise, we allocate a new slot, making sure that it has no less | |
2077 | inherent space, and no less total space, then the previous slot. */ | |
2078 | if (from_reg == -1) | |
2079 | { | |
3072d30e | 2080 | HOST_WIDE_INT alias_set = new_alias_set (); |
2081 | ||
08a9dd06 | 2082 | /* No known place to spill from => no slot to reuse. */ |
595d62e9 | 2083 | x = assign_stack_local (mode, total_size, |
2084 | min_align > inherent_align | |
2085 | || total_size > inherent_size ? -1 : 0); | |
51356f86 | 2086 | if (BYTES_BIG_ENDIAN) |
04188a85 | 2087 | /* Cancel the big-endian correction done in assign_stack_local. |
2088 | Get the address of the beginning of the slot. | |
2089 | This is so we can do a big-endian correction unconditionally | |
2090 | below. */ | |
2091 | adjust = inherent_size - total_size; | |
2092 | ||
f7c44134 | 2093 | /* Nothing can alias this slot except this pseudo. */ |
3072d30e | 2094 | set_mem_alias_set (x, alias_set); |
2095 | dse_record_singleton_alias_set (alias_set, mode); | |
08a9dd06 | 2096 | } |
f7c44134 | 2097 | |
08a9dd06 | 2098 | /* Reuse a stack slot if possible. */ |
2099 | else if (spill_stack_slot[from_reg] != 0 | |
2100 | && spill_stack_slot_width[from_reg] >= total_size | |
2101 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
595d62e9 | 2102 | >= inherent_size) |
2103 | && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align) | |
08a9dd06 | 2104 | x = spill_stack_slot[from_reg]; |
2105 | /* Allocate a bigger slot. */ | |
2106 | else | |
2107 | { | |
2108 | /* Compute maximum size needed, both for inherent size | |
2109 | and for total size. */ | |
56351df3 | 2110 | rtx stack_slot; |
f7c44134 | 2111 | |
08a9dd06 | 2112 | if (spill_stack_slot[from_reg]) |
2113 | { | |
2114 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
2115 | > inherent_size) | |
2116 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
2117 | if (spill_stack_slot_width[from_reg] > total_size) | |
2118 | total_size = spill_stack_slot_width[from_reg]; | |
595d62e9 | 2119 | if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align) |
2120 | min_align = MEM_ALIGN (spill_stack_slot[from_reg]); | |
08a9dd06 | 2121 | } |
f7c44134 | 2122 | |
08a9dd06 | 2123 | /* Make a slot with that size. */ |
a0516f44 | 2124 | x = assign_stack_local (mode, total_size, |
595d62e9 | 2125 | min_align > inherent_align |
2126 | || total_size > inherent_size ? -1 : 0); | |
56351df3 | 2127 | stack_slot = x; |
f7c44134 | 2128 | |
2129 | /* All pseudos mapped to this slot can alias each other. */ | |
2130 | if (spill_stack_slot[from_reg]) | |
3072d30e | 2131 | { |
2132 | HOST_WIDE_INT alias_set | |
2133 | = MEM_ALIAS_SET (spill_stack_slot[from_reg]); | |
2134 | set_mem_alias_set (x, alias_set); | |
2135 | dse_invalidate_singleton_alias_set (alias_set); | |
2136 | } | |
f7c44134 | 2137 | else |
3072d30e | 2138 | { |
2139 | HOST_WIDE_INT alias_set = new_alias_set (); | |
2140 | set_mem_alias_set (x, alias_set); | |
2141 | dse_record_singleton_alias_set (alias_set, mode); | |
2142 | } | |
f7c44134 | 2143 | |
51356f86 | 2144 | if (BYTES_BIG_ENDIAN) |
2145 | { | |
2146 | /* Cancel the big-endian correction done in assign_stack_local. | |
2147 | Get the address of the beginning of the slot. | |
2148 | This is so we can do a big-endian correction unconditionally | |
2149 | below. */ | |
2150 | adjust = GET_MODE_SIZE (mode) - total_size; | |
56351df3 | 2151 | if (adjust) |
2a631e19 | 2152 | stack_slot |
2153 | = adjust_address_nv (x, mode_for_size (total_size | |
941522d6 | 2154 | * BITS_PER_UNIT, |
2155 | MODE_INT, 1), | |
2a631e19 | 2156 | adjust); |
51356f86 | 2157 | } |
f7c44134 | 2158 | |
56351df3 | 2159 | spill_stack_slot[from_reg] = stack_slot; |
08a9dd06 | 2160 | spill_stack_slot_width[from_reg] = total_size; |
2161 | } | |
2162 | ||
08a9dd06 | 2163 | /* On a big endian machine, the "address" of the slot |
2164 | is the address of the low part that fits its inherent mode. */ | |
51356f86 | 2165 | if (BYTES_BIG_ENDIAN && inherent_size < total_size) |
08a9dd06 | 2166 | adjust += (total_size - inherent_size); |
08a9dd06 | 2167 | |
2168 | /* If we have any adjustment to make, or if the stack slot is the | |
2169 | wrong mode, make a new stack slot. */ | |
278fe152 | 2170 | x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); |
2171 | ||
2172 | /* If we have a decl for the original register, set it for the | |
2173 | memory. If this is a shared MEM, make a copy. */ | |
ca74b940 | 2174 | if (REG_EXPR (regno_reg_rtx[i]) |
ce45a448 | 2175 | && DECL_P (REG_EXPR (regno_reg_rtx[i]))) |
278fe152 | 2176 | { |
ca74b940 | 2177 | rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i])); |
278fe152 | 2178 | |
c99e85d9 | 2179 | /* We can do this only for the DECLs home pseudo, not for |
2180 | any copies of it, since otherwise when the stack slot | |
2181 | is reused, nonoverlapping_memrefs_p might think they | |
2182 | cannot overlap. */ | |
8ad4c111 | 2183 | if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i) |
c99e85d9 | 2184 | { |
2185 | if (from_reg != -1 && spill_stack_slot[from_reg] == x) | |
2186 | x = copy_rtx (x); | |
2187 | ||
ca74b940 | 2188 | set_mem_attrs_from_reg (x, regno_reg_rtx[i]); |
c99e85d9 | 2189 | } |
278fe152 | 2190 | } |
08a9dd06 | 2191 | |
1e625a2e | 2192 | /* Save the stack slot for later. */ |
08a9dd06 | 2193 | reg_equiv_memory_loc[i] = x; |
2194 | } | |
2195 | } | |
2196 | ||
3072d30e | 2197 | /* Mark the slots in regs_ever_live for the hard regs used by |
2198 | pseudo-reg number REGNO, accessed in MODE. */ | |
08a9dd06 | 2199 | |
3072d30e | 2200 | static void |
2201 | mark_home_live_1 (int regno, enum machine_mode mode) | |
08a9dd06 | 2202 | { |
19cb6b50 | 2203 | int i, lim; |
02e7a332 | 2204 | |
08a9dd06 | 2205 | i = reg_renumber[regno]; |
2206 | if (i < 0) | |
2207 | return; | |
a2c6f0b7 | 2208 | lim = end_hard_regno (PSEUDO_REGNO_MODE (regno), i); |
08a9dd06 | 2209 | while (i < lim) |
3072d30e | 2210 | df_set_regs_ever_live(i++, true); |
2211 | } | |
2212 | ||
2213 | /* Mark the slots in regs_ever_live for the hard regs | |
2214 | used by pseudo-reg number REGNO. */ | |
2215 | ||
2216 | void | |
2217 | mark_home_live (int regno) | |
2218 | { | |
2219 | if (reg_renumber[regno] >= 0) | |
2220 | mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno)); | |
08a9dd06 | 2221 | } |
2222 | \f | |
2223 | /* This function handles the tracking of elimination offsets around branches. | |
2224 | ||
2225 | X is a piece of RTL being scanned. | |
2226 | ||
2227 | INSN is the insn that it came from, if any. | |
2228 | ||
7fd957fe | 2229 | INITIAL_P is nonzero if we are to set the offset to be the initial |
08a9dd06 | 2230 | offset and zero if we are setting the offset of the label to be the |
2231 | current offset. */ | |
2232 | ||
2233 | static void | |
3ad4992f | 2234 | set_label_offsets (rtx x, rtx insn, int initial_p) |
08a9dd06 | 2235 | { |
2236 | enum rtx_code code = GET_CODE (x); | |
2237 | rtx tem; | |
274c11d8 | 2238 | unsigned int i; |
08a9dd06 | 2239 | struct elim_table *p; |
2240 | ||
2241 | switch (code) | |
2242 | { | |
2243 | case LABEL_REF: | |
3add3b31 | 2244 | if (LABEL_REF_NONLOCAL_P (x)) |
2245 | return; | |
2246 | ||
08a9dd06 | 2247 | x = XEXP (x, 0); |
2248 | ||
a92771b8 | 2249 | /* ... fall through ... */ |
08a9dd06 | 2250 | |
2251 | case CODE_LABEL: | |
2252 | /* If we know nothing about this label, set the desired offsets. Note | |
2253 | that this sets the offset at a label to be the offset before a label | |
2254 | if we don't know anything about the label. This is not correct for | |
2255 | the label after a BARRIER, but is the best guess we can make. If | |
2256 | we guessed wrong, we will suppress an elimination that might have | |
2257 | been possible had we been able to guess correctly. */ | |
2258 | ||
2ff147ce | 2259 | if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num]) |
08a9dd06 | 2260 | { |
2261 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
2ff147ce | 2262 | offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] |
08a9dd06 | 2263 | = (initial_p ? reg_eliminate[i].initial_offset |
2264 | : reg_eliminate[i].offset); | |
2ff147ce | 2265 | offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1; |
08a9dd06 | 2266 | } |
2267 | ||
2268 | /* Otherwise, if this is the definition of a label and it is | |
f9e15121 | 2269 | preceded by a BARRIER, set our offsets to the known offset of |
08a9dd06 | 2270 | that label. */ |
2271 | ||
2272 | else if (x == insn | |
2273 | && (tem = prev_nonnote_insn (insn)) != 0 | |
6d7dc5b9 | 2274 | && BARRIER_P (tem)) |
f87f6d5d | 2275 | set_offsets_for_label (insn); |
08a9dd06 | 2276 | else |
2277 | /* If neither of the above cases is true, compare each offset | |
2278 | with those previously recorded and suppress any eliminations | |
2279 | where the offsets disagree. */ | |
c8ad158d | 2280 | |
08a9dd06 | 2281 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) |
2ff147ce | 2282 | if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] |
08a9dd06 | 2283 | != (initial_p ? reg_eliminate[i].initial_offset |
2284 | : reg_eliminate[i].offset)) | |
2285 | reg_eliminate[i].can_eliminate = 0; | |
2286 | ||
2287 | return; | |
2288 | ||
2289 | case JUMP_INSN: | |
2290 | set_label_offsets (PATTERN (insn), insn, initial_p); | |
2291 | ||
a92771b8 | 2292 | /* ... fall through ... */ |
08a9dd06 | 2293 | |
2294 | case INSN: | |
2295 | case CALL_INSN: | |
2296 | /* Any labels mentioned in REG_LABEL notes can be branched to indirectly | |
2297 | and hence must have all eliminations at their initial offsets. */ | |
2298 | for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) | |
2299 | if (REG_NOTE_KIND (tem) == REG_LABEL) | |
2300 | set_label_offsets (XEXP (tem, 0), insn, 1); | |
2301 | return; | |
2302 | ||
e4d20541 | 2303 | case PARALLEL: |
08a9dd06 | 2304 | case ADDR_VEC: |
2305 | case ADDR_DIFF_VEC: | |
e4d20541 | 2306 | /* Each of the labels in the parallel or address vector must be |
2307 | at their initial offsets. We want the first field for PARALLEL | |
2308 | and ADDR_VEC and the second field for ADDR_DIFF_VEC. */ | |
08a9dd06 | 2309 | |
274c11d8 | 2310 | for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) |
08a9dd06 | 2311 | set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), |
2312 | insn, initial_p); | |
2313 | return; | |
2314 | ||
2315 | case SET: | |
2316 | /* We only care about setting PC. If the source is not RETURN, | |
2317 | IF_THEN_ELSE, or a label, disable any eliminations not at | |
2318 | their initial offsets. Similarly if any arm of the IF_THEN_ELSE | |
2319 | isn't one of those possibilities. For branches to a label, | |
2320 | call ourselves recursively. | |
2321 | ||
2322 | Note that this can disable elimination unnecessarily when we have | |
2323 | a non-local goto since it will look like a non-constant jump to | |
2324 | someplace in the current function. This isn't a significant | |
2325 | problem since such jumps will normally be when all elimination | |
2326 | pairs are back to their initial offsets. */ | |
2327 | ||
2328 | if (SET_DEST (x) != pc_rtx) | |
2329 | return; | |
2330 | ||
2331 | switch (GET_CODE (SET_SRC (x))) | |
2332 | { | |
2333 | case PC: | |
2334 | case RETURN: | |
2335 | return; | |
2336 | ||
2337 | case LABEL_REF: | |
9d95b2b0 | 2338 | set_label_offsets (SET_SRC (x), insn, initial_p); |
08a9dd06 | 2339 | return; |
2340 | ||
2341 | case IF_THEN_ELSE: | |
2342 | tem = XEXP (SET_SRC (x), 1); | |
2343 | if (GET_CODE (tem) == LABEL_REF) | |
2344 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2345 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2346 | break; | |
2347 | ||
2348 | tem = XEXP (SET_SRC (x), 2); | |
2349 | if (GET_CODE (tem) == LABEL_REF) | |
2350 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2351 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2352 | break; | |
2353 | return; | |
0dbd1c74 | 2354 | |
2355 | default: | |
2356 | break; | |
08a9dd06 | 2357 | } |
2358 | ||
2359 | /* If we reach here, all eliminations must be at their initial | |
2360 | offset because we are doing a jump to a variable address. */ | |
2361 | for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) | |
2362 | if (p->offset != p->initial_offset) | |
2363 | p->can_eliminate = 0; | |
0dbd1c74 | 2364 | break; |
5bb2f919 | 2365 | |
0dbd1c74 | 2366 | default: |
2367 | break; | |
08a9dd06 | 2368 | } |
2369 | } | |
2370 | \f | |
c8ad158d | 2371 | /* Scan X and replace any eliminable registers (such as fp) with a |
08a9dd06 | 2372 | replacement (such as sp), plus an offset. |
2373 | ||
2374 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
2375 | much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a | |
2376 | MEM, we are allowed to replace a sum of a register and the constant zero | |
2377 | with the register, which we cannot do outside a MEM. In addition, we need | |
2378 | to record the fact that a register is referenced outside a MEM. | |
2379 | ||
b8b76680 | 2380 | If INSN is an insn, it is the insn containing X. If we replace a REG |
7fd957fe | 2381 | in a SET_DEST with an equivalent MEM and INSN is nonzero, write a |
08a9dd06 | 2382 | CLOBBER of the pseudo after INSN so find_equiv_regs will know that |
3398e91d | 2383 | the REG is being modified. |
08a9dd06 | 2384 | |
b8b76680 | 2385 | Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). |
2386 | That's used when we eliminate in expressions stored in notes. | |
2387 | This means, do not set ref_outside_mem even if the reference | |
2388 | is outside of MEMs. | |
2389 | ||
08a9dd06 | 2390 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had |
2391 | replacements done assuming all offsets are at their initial values. If | |
2392 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | |
2393 | encounter, return the actual location so that find_reloads will do | |
2394 | the proper thing. */ | |
2395 | ||
2e4905ea | 2396 | static rtx |
2397 | eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn, | |
2398 | bool may_use_invariant) | |
08a9dd06 | 2399 | { |
2400 | enum rtx_code code = GET_CODE (x); | |
2401 | struct elim_table *ep; | |
2402 | int regno; | |
2403 | rtx new; | |
2404 | int i, j; | |
d2ca078f | 2405 | const char *fmt; |
08a9dd06 | 2406 | int copied = 0; |
2407 | ||
e965e340 | 2408 | if (! current_function_decl) |
2409 | return x; | |
cc9c157e | 2410 | |
08a9dd06 | 2411 | switch (code) |
2412 | { | |
2413 | case CONST_INT: | |
2414 | case CONST_DOUBLE: | |
886cfd4f | 2415 | case CONST_VECTOR: |
08a9dd06 | 2416 | case CONST: |
2417 | case SYMBOL_REF: | |
2418 | case CODE_LABEL: | |
2419 | case PC: | |
2420 | case CC0: | |
2421 | case ASM_INPUT: | |
2422 | case ADDR_VEC: | |
2423 | case ADDR_DIFF_VEC: | |
2424 | case RETURN: | |
2425 | return x; | |
2426 | ||
2427 | case REG: | |
2428 | regno = REGNO (x); | |
2429 | ||
2430 | /* First handle the case where we encounter a bare register that | |
2431 | is eliminable. Replace it with a PLUS. */ | |
2432 | if (regno < FIRST_PSEUDO_REGISTER) | |
2433 | { | |
2434 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2435 | ep++) | |
2436 | if (ep->from_rtx == x && ep->can_eliminate) | |
6b21946f | 2437 | return plus_constant (ep->to_rtx, ep->previous_offset); |
08a9dd06 | 2438 | |
2439 | } | |
d864b719 | 2440 | else if (reg_renumber && reg_renumber[regno] < 0 |
2e4905ea | 2441 | && reg_equiv_invariant && reg_equiv_invariant[regno]) |
2442 | { | |
2443 | if (may_use_invariant) | |
2444 | return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]), | |
2445 | mem_mode, insn, true); | |
2446 | /* There exists at least one use of REGNO that cannot be | |
2447 | eliminated. Prevent the defining insn from being deleted. */ | |
2448 | reg_equiv_init[regno] = NULL_RTX; | |
2449 | alter_reg (regno, -1); | |
2450 | } | |
08a9dd06 | 2451 | return x; |
2452 | ||
7014838c | 2453 | /* You might think handling MINUS in a manner similar to PLUS is a |
2454 | good idea. It is not. It has been tried multiple times and every | |
2455 | time the change has had to have been reverted. | |
2456 | ||
2457 | Other parts of reload know a PLUS is special (gen_reload for example) | |
2458 | and require special code to handle code a reloaded PLUS operand. | |
2459 | ||
2460 | Also consider backends where the flags register is clobbered by a | |
3f7df443 | 2461 | MINUS, but we can emit a PLUS that does not clobber flags (IA-32, |
7014838c | 2462 | lea instruction comes to mind). If we try to reload a MINUS, we |
2463 | may kill the flags register that was holding a useful value. | |
2464 | ||
2465 | So, please before trying to handle MINUS, consider reload as a | |
2466 | whole instead of this little section as well as the backend issues. */ | |
08a9dd06 | 2467 | case PLUS: |
2468 | /* If this is the sum of an eliminable register and a constant, rework | |
1e625a2e | 2469 | the sum. */ |
8ad4c111 | 2470 | if (REG_P (XEXP (x, 0)) |
08a9dd06 | 2471 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER |
2472 | && CONSTANT_P (XEXP (x, 1))) | |
2473 | { | |
2474 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2475 | ep++) | |
2476 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2477 | { | |
08a9dd06 | 2478 | /* The only time we want to replace a PLUS with a REG (this |
2479 | occurs when the constant operand of the PLUS is the negative | |
2480 | of the offset) is when we are inside a MEM. We won't want | |
2481 | to do so at other times because that would change the | |
2482 | structure of the insn in a way that reload can't handle. | |
2483 | We special-case the commonest situation in | |
2484 | eliminate_regs_in_insn, so just replace a PLUS with a | |
2485 | PLUS here, unless inside a MEM. */ | |
e77a9f50 | 2486 | if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT |
08a9dd06 | 2487 | && INTVAL (XEXP (x, 1)) == - ep->previous_offset) |
2488 | return ep->to_rtx; | |
2489 | else | |
941522d6 | 2490 | return gen_rtx_PLUS (Pmode, ep->to_rtx, |
2491 | plus_constant (XEXP (x, 1), | |
2492 | ep->previous_offset)); | |
08a9dd06 | 2493 | } |
2494 | ||
2495 | /* If the register is not eliminable, we are done since the other | |
2496 | operand is a constant. */ | |
2497 | return x; | |
2498 | } | |
2499 | ||
2500 | /* If this is part of an address, we want to bring any constant to the | |
2501 | outermost PLUS. We will do this by doing register replacement in | |
2502 | our operands and seeing if a constant shows up in one of them. | |
2503 | ||
6b21946f | 2504 | Note that there is no risk of modifying the structure of the insn, |
2505 | since we only get called for its operands, thus we are either | |
2506 | modifying the address inside a MEM, or something like an address | |
2507 | operand of a load-address insn. */ | |
08a9dd06 | 2508 | |
2509 | { | |
2e4905ea | 2510 | rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); |
2511 | rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); | |
08a9dd06 | 2512 | |
d864b719 | 2513 | if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))) |
08a9dd06 | 2514 | { |
2515 | /* If one side is a PLUS and the other side is a pseudo that | |
c8ad158d | 2516 | didn't get a hard register but has a reg_equiv_constant, |
08a9dd06 | 2517 | we must replace the constant here since it may no longer |
2518 | be in the position of any operand. */ | |
8ad4c111 | 2519 | if (GET_CODE (new0) == PLUS && REG_P (new1) |
08a9dd06 | 2520 | && REGNO (new1) >= FIRST_PSEUDO_REGISTER |
2521 | && reg_renumber[REGNO (new1)] < 0 | |
2522 | && reg_equiv_constant != 0 | |
2523 | && reg_equiv_constant[REGNO (new1)] != 0) | |
2524 | new1 = reg_equiv_constant[REGNO (new1)]; | |
8ad4c111 | 2525 | else if (GET_CODE (new1) == PLUS && REG_P (new0) |
08a9dd06 | 2526 | && REGNO (new0) >= FIRST_PSEUDO_REGISTER |
2527 | && reg_renumber[REGNO (new0)] < 0 | |
2528 | && reg_equiv_constant[REGNO (new0)] != 0) | |
2529 | new0 = reg_equiv_constant[REGNO (new0)]; | |
2530 | ||
2531 | new = form_sum (new0, new1); | |
2532 | ||
2533 | /* As above, if we are not inside a MEM we do not want to | |
2534 | turn a PLUS into something else. We might try to do so here | |
2535 | for an addition of 0 if we aren't optimizing. */ | |
2536 | if (! mem_mode && GET_CODE (new) != PLUS) | |
941522d6 | 2537 | return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx); |
08a9dd06 | 2538 | else |
2539 | return new; | |
2540 | } | |
2541 | } | |
2542 | return x; | |
2543 | ||
7f24d2b8 | 2544 | case MULT: |
5bb2f919 | 2545 | /* If this is the product of an eliminable register and a |
7f24d2b8 | 2546 | constant, apply the distribute law and move the constant out |
2547 | so that we have (plus (mult ..) ..). This is needed in order | |
c3418f42 | 2548 | to keep load-address insns valid. This case is pathological. |
7f24d2b8 | 2549 | We ignore the possibility of overflow here. */ |
8ad4c111 | 2550 | if (REG_P (XEXP (x, 0)) |
7f24d2b8 | 2551 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER |
2552 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2553 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2554 | ep++) | |
2555 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2556 | { | |
2557 | if (! mem_mode | |
2558 | /* Refs inside notes don't count for this purpose. */ | |
2559 | && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST | |
2560 | || GET_CODE (insn) == INSN_LIST))) | |
2561 | ep->ref_outside_mem = 1; | |
2562 | ||
2563 | return | |
941522d6 | 2564 | plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), |
7f24d2b8 | 2565 | ep->previous_offset * INTVAL (XEXP (x, 1))); |
2566 | } | |
08a9dd06 | 2567 | |
a92771b8 | 2568 | /* ... fall through ... */ |
08a9dd06 | 2569 | |
08a9dd06 | 2570 | case CALL: |
2571 | case COMPARE: | |
7014838c | 2572 | /* See comments before PLUS about handling MINUS. */ |
049f26da | 2573 | case MINUS: |
08a9dd06 | 2574 | case DIV: case UDIV: |
2575 | case MOD: case UMOD: | |
2576 | case AND: case IOR: case XOR: | |
6503f782 | 2577 | case ROTATERT: case ROTATE: |
2578 | case ASHIFTRT: case LSHIFTRT: case ASHIFT: | |
08a9dd06 | 2579 | case NE: case EQ: |
2580 | case GE: case GT: case GEU: case GTU: | |
2581 | case LE: case LT: case LEU: case LTU: | |
2582 | { | |
2e4905ea | 2583 | rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); |
2584 | rtx new1 = XEXP (x, 1) | |
2585 | ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0; | |
08a9dd06 | 2586 | |
2587 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
941522d6 | 2588 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); |
08a9dd06 | 2589 | } |
2590 | return x; | |
2591 | ||
7f24d2b8 | 2592 | case EXPR_LIST: |
2593 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | |
2594 | if (XEXP (x, 0)) | |
2595 | { | |
2e4905ea | 2596 | new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); |
7f24d2b8 | 2597 | if (new != XEXP (x, 0)) |
6d454b95 | 2598 | { |
2599 | /* If this is a REG_DEAD note, it is not valid anymore. | |
2600 | Using the eliminated version could result in creating a | |
2601 | REG_DEAD note for the stack or frame pointer. */ | |
2602 | if (GET_MODE (x) == REG_DEAD) | |
2603 | return (XEXP (x, 1) | |
2e4905ea | 2604 | ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true) |
6d454b95 | 2605 | : NULL_RTX); |
2606 | ||
2607 | x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1)); | |
2608 | } | |
7f24d2b8 | 2609 | } |
2610 | ||
a92771b8 | 2611 | /* ... fall through ... */ |
7f24d2b8 | 2612 | |
2613 | case INSN_LIST: | |
2614 | /* Now do eliminations in the rest of the chain. If this was | |
2615 | an EXPR_LIST, this might result in allocating more memory than is | |
2616 | strictly needed, but it simplifies the code. */ | |
2617 | if (XEXP (x, 1)) | |
2618 | { | |
2e4905ea | 2619 | new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); |
7f24d2b8 | 2620 | if (new != XEXP (x, 1)) |
d864b719 | 2621 | return |
2622 | gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new); | |
7f24d2b8 | 2623 | } |
2624 | return x; | |
2625 | ||
08a9dd06 | 2626 | case PRE_INC: |
2627 | case POST_INC: | |
2628 | case PRE_DEC: | |
2629 | case POST_DEC: | |
cc6757ec | 2630 | /* We do not support elimination of a register that is modified. |
2631 | elimination_effects has already make sure that this does not | |
2632 | happen. */ | |
2633 | return x; | |
2634 | ||
2635 | case PRE_MODIFY: | |
2636 | case POST_MODIFY: | |
2637 | /* We do not support elimination of a register that is modified. | |
2638 | elimination_effects has already make sure that this does not | |
2639 | happen. The only remaining case we need to consider here is | |
2640 | that the increment value may be an eliminable register. */ | |
2641 | if (GET_CODE (XEXP (x, 1)) == PLUS | |
2642 | && XEXP (XEXP (x, 1), 0) == XEXP (x, 0)) | |
2643 | { | |
2644 | rtx new = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode, | |
2645 | insn, true); | |
2646 | ||
2647 | if (new != XEXP (XEXP (x, 1), 1)) | |
2648 | return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0), | |
2649 | gen_rtx_PLUS (GET_MODE (x), | |
2650 | XEXP (x, 0), new)); | |
2651 | } | |
2652 | return x; | |
2653 | ||
08a9dd06 | 2654 | case STRICT_LOW_PART: |
2655 | case NEG: case NOT: | |
2656 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2657 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2658 | case FLOAT: case FIX: | |
2659 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2660 | case ABS: | |
2661 | case SQRT: | |
2662 | case FFS: | |
6a08d0ab | 2663 | case CLZ: |
2664 | case CTZ: | |
2665 | case POPCOUNT: | |
2666 | case PARITY: | |
42791117 | 2667 | case BSWAP: |
2e4905ea | 2668 | new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); |
08a9dd06 | 2669 | if (new != XEXP (x, 0)) |
941522d6 | 2670 | return gen_rtx_fmt_e (code, GET_MODE (x), new); |
08a9dd06 | 2671 | return x; |
2672 | ||
2673 | case SUBREG: | |
701e46d0 | 2674 | /* Similar to above processing, but preserve SUBREG_BYTE. |
08a9dd06 | 2675 | Convert (subreg (mem)) to (mem) if not paradoxical. |
2676 | Also, if we have a non-paradoxical (subreg (pseudo)) and the | |
2677 | pseudo didn't get a hard reg, we must replace this with the | |
5cd86fd9 | 2678 | eliminated version of the memory location because push_reload |
08a9dd06 | 2679 | may do the replacement in certain circumstances. */ |
8ad4c111 | 2680 | if (REG_P (SUBREG_REG (x)) |
08a9dd06 | 2681 | && (GET_MODE_SIZE (GET_MODE (x)) |
2682 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2683 | && reg_equiv_memory_loc != 0 | |
2684 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2685 | { | |
93c7b06e | 2686 | new = SUBREG_REG (x); |
08a9dd06 | 2687 | } |
2688 | else | |
2e4905ea | 2689 | new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false); |
08a9dd06 | 2690 | |
701e46d0 | 2691 | if (new != SUBREG_REG (x)) |
08a9dd06 | 2692 | { |
e87a9401 | 2693 | int x_size = GET_MODE_SIZE (GET_MODE (x)); |
2694 | int new_size = GET_MODE_SIZE (GET_MODE (new)); | |
2695 | ||
e16ceb8e | 2696 | if (MEM_P (new) |
ebbb4987 | 2697 | && ((x_size < new_size |
6182a80f | 2698 | #ifdef WORD_REGISTER_OPERATIONS |
ebbb4987 | 2699 | /* On these machines, combine can create rtl of the form |
2700 | (set (subreg:m1 (reg:m2 R) 0) ...) | |
5bb2f919 | 2701 | where m1 < m2, and expects something interesting to |
ebbb4987 | 2702 | happen to the entire word. Moreover, it will use the |
2703 | (reg:m2 R) later, expecting all bits to be preserved. | |
5bb2f919 | 2704 | So if the number of words is the same, preserve the |
5cd86fd9 | 2705 | subreg so that push_reload can see it. */ |
ee866761 | 2706 | && ! ((x_size - 1) / UNITS_PER_WORD |
2707 | == (new_size -1 ) / UNITS_PER_WORD) | |
6182a80f | 2708 | #endif |
ebbb4987 | 2709 | ) |
ee866761 | 2710 | || x_size == new_size) |
6182a80f | 2711 | ) |
69562d20 | 2712 | return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x)); |
08a9dd06 | 2713 | else |
701e46d0 | 2714 | return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x)); |
08a9dd06 | 2715 | } |
2716 | ||
2717 | return x; | |
2718 | ||
08a9dd06 | 2719 | case MEM: |
2720 | /* Our only special processing is to pass the mode of the MEM to our | |
2721 | recursive call and copy the flags. While we are here, handle this | |
2722 | case more efficiently. */ | |
e4e86ec5 | 2723 | return |
2724 | replace_equiv_address_nv (x, | |
2e4905ea | 2725 | eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), |
2726 | insn, true)); | |
5bb2f919 | 2727 | |
6b21946f | 2728 | case USE: |
51e97650 | 2729 | /* Handle insn_list USE that a call to a pure function may generate. */ |
2e4905ea | 2730 | new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false); |
51e97650 | 2731 | if (new != XEXP (x, 0)) |
2732 | return gen_rtx_USE (GET_MODE (x), new); | |
2733 | return x; | |
2734 | ||
6b21946f | 2735 | case CLOBBER: |
2736 | case ASM_OPERANDS: | |
2737 | case SET: | |
04e579b6 | 2738 | gcc_unreachable (); |
6b21946f | 2739 | |
0dbd1c74 | 2740 | default: |
2741 | break; | |
08a9dd06 | 2742 | } |
2743 | ||
2744 | /* Process each of our operands recursively. If any have changed, make a | |
2745 | copy of the rtx. */ | |
2746 | fmt = GET_RTX_FORMAT (code); | |
2747 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2748 | { | |
2749 | if (*fmt == 'e') | |
2750 | { | |
2e4905ea | 2751 | new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false); |
08a9dd06 | 2752 | if (new != XEXP (x, i) && ! copied) |
2753 | { | |
f2d0e9f1 | 2754 | x = shallow_copy_rtx (x); |
08a9dd06 | 2755 | copied = 1; |
2756 | } | |
2757 | XEXP (x, i) = new; | |
2758 | } | |
2759 | else if (*fmt == 'E') | |
2760 | { | |
2761 | int copied_vec = 0; | |
2762 | for (j = 0; j < XVECLEN (x, i); j++) | |
2763 | { | |
2e4905ea | 2764 | new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false); |
08a9dd06 | 2765 | if (new != XVECEXP (x, i, j) && ! copied_vec) |
2766 | { | |
a4070a91 | 2767 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), |
2768 | XVEC (x, i)->elem); | |
08a9dd06 | 2769 | if (! copied) |
2770 | { | |
f2d0e9f1 | 2771 | x = shallow_copy_rtx (x); |
08a9dd06 | 2772 | copied = 1; |
2773 | } | |
2774 | XVEC (x, i) = new_v; | |
2775 | copied_vec = 1; | |
2776 | } | |
2777 | XVECEXP (x, i, j) = new; | |
2778 | } | |
2779 | } | |
2780 | } | |
2781 | ||
2782 | return x; | |
2783 | } | |
6b21946f | 2784 | |
2e4905ea | 2785 | rtx |
2786 | eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn) | |
2787 | { | |
2788 | return eliminate_regs_1 (x, mem_mode, insn, false); | |
2789 | } | |
2790 | ||
6b21946f | 2791 | /* Scan rtx X for modifications of elimination target registers. Update |
2792 | the table of eliminables to reflect the changed state. MEM_MODE is | |
2793 | the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ | |
2794 | ||
2795 | static void | |
3ad4992f | 2796 | elimination_effects (rtx x, enum machine_mode mem_mode) |
6b21946f | 2797 | { |
2798 | enum rtx_code code = GET_CODE (x); | |
2799 | struct elim_table *ep; | |
2800 | int regno; | |
2801 | int i, j; | |
2802 | const char *fmt; | |
2803 | ||
2804 | switch (code) | |
2805 | { | |
2806 | case CONST_INT: | |
2807 | case CONST_DOUBLE: | |
886cfd4f | 2808 | case CONST_VECTOR: |
6b21946f | 2809 | case CONST: |
2810 | case SYMBOL_REF: | |
2811 | case CODE_LABEL: | |
2812 | case PC: | |
2813 | case CC0: | |
2814 | case ASM_INPUT: | |
2815 | case ADDR_VEC: | |
2816 | case ADDR_DIFF_VEC: | |
2817 | case RETURN: | |
2818 | return; | |
2819 | ||
6b21946f | 2820 | case REG: |
2821 | regno = REGNO (x); | |
2822 | ||
2823 | /* First handle the case where we encounter a bare register that | |
2824 | is eliminable. Replace it with a PLUS. */ | |
2825 | if (regno < FIRST_PSEUDO_REGISTER) | |
2826 | { | |
2827 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2828 | ep++) | |
2829 | if (ep->from_rtx == x && ep->can_eliminate) | |
2830 | { | |
2831 | if (! mem_mode) | |
2832 | ep->ref_outside_mem = 1; | |
2833 | return; | |
2834 | } | |
2835 | ||
2836 | } | |
2837 | else if (reg_renumber[regno] < 0 && reg_equiv_constant | |
2838 | && reg_equiv_constant[regno] | |
5e60d9d6 | 2839 | && ! function_invariant_p (reg_equiv_constant[regno])) |
6b21946f | 2840 | elimination_effects (reg_equiv_constant[regno], mem_mode); |
2841 | return; | |
2842 | ||
2843 | case PRE_INC: | |
2844 | case POST_INC: | |
2845 | case PRE_DEC: | |
2846 | case POST_DEC: | |
40988080 | 2847 | case POST_MODIFY: |
2848 | case PRE_MODIFY: | |
cc6757ec | 2849 | /* If we modify the source of an elimination rule, disable it. */ |
2850 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2851 | if (ep->from_rtx == XEXP (x, 0)) | |
2852 | ep->can_eliminate = 0; | |
2853 | ||
2854 | /* If we modify the target of an elimination rule by adding a constant, | |
2855 | update its offset. If we modify the target in any other way, we'll | |
2856 | have to disable the rule as well. */ | |
6b21946f | 2857 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
2858 | if (ep->to_rtx == XEXP (x, 0)) | |
2859 | { | |
2860 | int size = GET_MODE_SIZE (mem_mode); | |
2861 | ||
2862 | /* If more bytes than MEM_MODE are pushed, account for them. */ | |
2863 | #ifdef PUSH_ROUNDING | |
2864 | if (ep->to_rtx == stack_pointer_rtx) | |
2865 | size = PUSH_ROUNDING (size); | |
2866 | #endif | |
2867 | if (code == PRE_DEC || code == POST_DEC) | |
2868 | ep->offset += size; | |
40988080 | 2869 | else if (code == PRE_INC || code == POST_INC) |
6b21946f | 2870 | ep->offset -= size; |
cc6757ec | 2871 | else if (code == PRE_MODIFY || code == POST_MODIFY) |
2872 | { | |
2873 | if (GET_CODE (XEXP (x, 1)) == PLUS | |
2874 | && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) | |
2875 | && CONST_INT_P (XEXP (XEXP (x, 1), 1))) | |
2876 | ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1)); | |
2877 | else | |
2878 | ep->can_eliminate = 0; | |
2879 | } | |
6b21946f | 2880 | } |
2881 | ||
40988080 | 2882 | /* These two aren't unary operators. */ |
2883 | if (code == POST_MODIFY || code == PRE_MODIFY) | |
2884 | break; | |
2885 | ||
6b21946f | 2886 | /* Fall through to generic unary operation case. */ |
2887 | case STRICT_LOW_PART: | |
2888 | case NEG: case NOT: | |
2889 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2890 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2891 | case FLOAT: case FIX: | |
2892 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2893 | case ABS: | |
2894 | case SQRT: | |
2895 | case FFS: | |
6a08d0ab | 2896 | case CLZ: |
2897 | case CTZ: | |
2898 | case POPCOUNT: | |
2899 | case PARITY: | |
42791117 | 2900 | case BSWAP: |
6b21946f | 2901 | elimination_effects (XEXP (x, 0), mem_mode); |
2902 | return; | |
2903 | ||
2904 | case SUBREG: | |
8ad4c111 | 2905 | if (REG_P (SUBREG_REG (x)) |
6b21946f | 2906 | && (GET_MODE_SIZE (GET_MODE (x)) |
2907 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2908 | && reg_equiv_memory_loc != 0 | |
2909 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2910 | return; | |
2911 | ||
2912 | elimination_effects (SUBREG_REG (x), mem_mode); | |
2913 | return; | |
2914 | ||
2915 | case USE: | |
2916 | /* If using a register that is the source of an eliminate we still | |
2917 | think can be performed, note it cannot be performed since we don't | |
2918 | know how this register is used. */ | |
2919 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2920 | if (ep->from_rtx == XEXP (x, 0)) | |
2921 | ep->can_eliminate = 0; | |
2922 | ||
2923 | elimination_effects (XEXP (x, 0), mem_mode); | |
2924 | return; | |
2925 | ||
2926 | case CLOBBER: | |
2927 | /* If clobbering a register that is the replacement register for an | |
2928 | elimination we still think can be performed, note that it cannot | |
2929 | be performed. Otherwise, we need not be concerned about it. */ | |
2930 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2931 | if (ep->to_rtx == XEXP (x, 0)) | |
2932 | ep->can_eliminate = 0; | |
2933 | ||
2934 | elimination_effects (XEXP (x, 0), mem_mode); | |
2935 | return; | |
2936 | ||
2937 | case SET: | |
2938 | /* Check for setting a register that we know about. */ | |
8ad4c111 | 2939 | if (REG_P (SET_DEST (x))) |
6b21946f | 2940 | { |
2941 | /* See if this is setting the replacement register for an | |
2942 | elimination. | |
2943 | ||
2944 | If DEST is the hard frame pointer, we do nothing because we | |
2945 | assume that all assignments to the frame pointer are for | |
2946 | non-local gotos and are being done at a time when they are valid | |
2947 | and do not disturb anything else. Some machines want to | |
2948 | eliminate a fake argument pointer (or even a fake frame pointer) | |
2949 | with either the real frame or the stack pointer. Assignments to | |
2950 | the hard frame pointer must not prevent this elimination. */ | |
2951 | ||
2952 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2953 | ep++) | |
2954 | if (ep->to_rtx == SET_DEST (x) | |
2955 | && SET_DEST (x) != hard_frame_pointer_rtx) | |
2956 | { | |
2957 | /* If it is being incremented, adjust the offset. Otherwise, | |
2958 | this elimination can't be done. */ | |
2959 | rtx src = SET_SRC (x); | |
2960 | ||
2961 | if (GET_CODE (src) == PLUS | |
2962 | && XEXP (src, 0) == SET_DEST (x) | |
2963 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2964 | ep->offset -= INTVAL (XEXP (src, 1)); | |
2965 | else | |
2966 | ep->can_eliminate = 0; | |
2967 | } | |
2968 | } | |
2969 | ||
2970 | elimination_effects (SET_DEST (x), 0); | |
2971 | elimination_effects (SET_SRC (x), 0); | |
2972 | return; | |
2973 | ||
2974 | case MEM: | |
6b21946f | 2975 | /* Our only special processing is to pass the mode of the MEM to our |
2976 | recursive call. */ | |
2977 | elimination_effects (XEXP (x, 0), GET_MODE (x)); | |
2978 | return; | |
2979 | ||
2980 | default: | |
2981 | break; | |
2982 | } | |
2983 | ||
2984 | fmt = GET_RTX_FORMAT (code); | |
2985 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2986 | { | |
2987 | if (*fmt == 'e') | |
2988 | elimination_effects (XEXP (x, i), mem_mode); | |
2989 | else if (*fmt == 'E') | |
2990 | for (j = 0; j < XVECLEN (x, i); j++) | |
2991 | elimination_effects (XVECEXP (x, i, j), mem_mode); | |
2992 | } | |
2993 | } | |
2994 | ||
2995 | /* Descend through rtx X and verify that no references to eliminable registers | |
2996 | remain. If any do remain, mark the involved register as not | |
2997 | eliminable. */ | |
dccf4eb3 | 2998 | |
6b21946f | 2999 | static void |
3ad4992f | 3000 | check_eliminable_occurrences (rtx x) |
6b21946f | 3001 | { |
3002 | const char *fmt; | |
3003 | int i; | |
3004 | enum rtx_code code; | |
3005 | ||
3006 | if (x == 0) | |
3007 | return; | |
aedd3e94 | 3008 | |
6b21946f | 3009 | code = GET_CODE (x); |
3010 | ||
3011 | if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
3012 | { | |
3013 | struct elim_table *ep; | |
3014 | ||
3015 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
aa150c9f | 3016 | if (ep->from_rtx == x) |
6b21946f | 3017 | ep->can_eliminate = 0; |
3018 | return; | |
3019 | } | |
aedd3e94 | 3020 | |
6b21946f | 3021 | fmt = GET_RTX_FORMAT (code); |
3022 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
3023 | { | |
3024 | if (*fmt == 'e') | |
3025 | check_eliminable_occurrences (XEXP (x, i)); | |
3026 | else if (*fmt == 'E') | |
3027 | { | |
3028 | int j; | |
3029 | for (j = 0; j < XVECLEN (x, i); j++) | |
3030 | check_eliminable_occurrences (XVECEXP (x, i, j)); | |
3031 | } | |
3032 | } | |
3033 | } | |
08a9dd06 | 3034 | \f |
3035 | /* Scan INSN and eliminate all eliminable registers in it. | |
3036 | ||
3037 | If REPLACE is nonzero, do the replacement destructively. Also | |
3038 | delete the insn as dead it if it is setting an eliminable register. | |
3039 | ||
3040 | If REPLACE is zero, do all our allocations in reload_obstack. | |
3041 | ||
3042 | If no eliminations were done and this insn doesn't require any elimination | |
3043 | processing (these are not identical conditions: it might be updating sp, | |
3044 | but not referencing fp; this needs to be seen during reload_as_needed so | |
3045 | that the offset between fp and sp can be taken into consideration), zero | |
3046 | is returned. Otherwise, 1 is returned. */ | |
3047 | ||
3048 | static int | |
3ad4992f | 3049 | eliminate_regs_in_insn (rtx insn, int replace) |
08a9dd06 | 3050 | { |
6b21946f | 3051 | int icode = recog_memoized (insn); |
08a9dd06 | 3052 | rtx old_body = PATTERN (insn); |
6b21946f | 3053 | int insn_is_asm = asm_noperands (old_body) >= 0; |
d92d1db8 | 3054 | rtx old_set = single_set (insn); |
08a9dd06 | 3055 | rtx new_body; |
3056 | int val = 0; | |
805e22b2 | 3057 | int i; |
6b21946f | 3058 | rtx substed_operand[MAX_RECOG_OPERANDS]; |
3059 | rtx orig_operand[MAX_RECOG_OPERANDS]; | |
08a9dd06 | 3060 | struct elim_table *ep; |
2e4905ea | 3061 | rtx plus_src, plus_cst_src; |
08a9dd06 | 3062 | |
6b21946f | 3063 | if (! insn_is_asm && icode < 0) |
3064 | { | |
04e579b6 | 3065 | gcc_assert (GET_CODE (PATTERN (insn)) == USE |
3066 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
3067 | || GET_CODE (PATTERN (insn)) == ADDR_VEC | |
3068 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
3069 | || GET_CODE (PATTERN (insn)) == ASM_INPUT); | |
3070 | return 0; | |
6b21946f | 3071 | } |
3072 | ||
8ad4c111 | 3073 | if (old_set != 0 && REG_P (SET_DEST (old_set)) |
d92d1db8 | 3074 | && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) |
08a9dd06 | 3075 | { |
3076 | /* Check for setting an eliminable register. */ | |
3077 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
d92d1db8 | 3078 | if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) |
08a9dd06 | 3079 | { |
14d6e77b | 3080 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
3081 | /* If this is setting the frame pointer register to the | |
3082 | hardware frame pointer register and this is an elimination | |
3083 | that will be done (tested above), this insn is really | |
3084 | adjusting the frame pointer downward to compensate for | |
3085 | the adjustment done before a nonlocal goto. */ | |
3086 | if (ep->from == FRAME_POINTER_REGNUM | |
3087 | && ep->to == HARD_FRAME_POINTER_REGNUM) | |
3088 | { | |
79ed0259 | 3089 | rtx base = SET_SRC (old_set); |
3090 | rtx base_insn = insn; | |
ec96de93 | 3091 | HOST_WIDE_INT offset = 0; |
79ed0259 | 3092 | |
3093 | while (base != ep->to_rtx) | |
ec6d6e82 | 3094 | { |
79ed0259 | 3095 | rtx prev_insn, prev_set; |
3096 | ||
3097 | if (GET_CODE (base) == PLUS | |
3098 | && GET_CODE (XEXP (base, 1)) == CONST_INT) | |
3099 | { | |
3100 | offset += INTVAL (XEXP (base, 1)); | |
3101 | base = XEXP (base, 0); | |
3102 | } | |
3103 | else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0 | |
3104 | && (prev_set = single_set (prev_insn)) != 0 | |
3105 | && rtx_equal_p (SET_DEST (prev_set), base)) | |
3106 | { | |
3107 | base = SET_SRC (prev_set); | |
3108 | base_insn = prev_insn; | |
3109 | } | |
3110 | else | |
3111 | break; | |
ec6d6e82 | 3112 | } |
14d6e77b | 3113 | |
79ed0259 | 3114 | if (base == ep->to_rtx) |
14d6e77b | 3115 | { |
d3e97cac | 3116 | rtx src |
3117 | = plus_constant (ep->to_rtx, offset - ep->offset); | |
3118 | ||
3119 | new_body = old_body; | |
3120 | if (! replace) | |
3121 | { | |
3122 | new_body = copy_insn (old_body); | |
3123 | if (REG_NOTES (insn)) | |
3124 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3125 | } | |
3126 | PATTERN (insn) = new_body; | |
3127 | old_set = single_set (insn); | |
3128 | ||
3129 | /* First see if this insn remains valid when we | |
3130 | make the change. If not, keep the INSN_CODE | |
3131 | the same and let reload fit it up. */ | |
3132 | validate_change (insn, &SET_SRC (old_set), src, 1); | |
3133 | validate_change (insn, &SET_DEST (old_set), | |
3134 | ep->to_rtx, 1); | |
3135 | if (! apply_change_group ()) | |
14d6e77b | 3136 | { |
d3e97cac | 3137 | SET_SRC (old_set) = src; |
3138 | SET_DEST (old_set) = ep->to_rtx; | |
14d6e77b | 3139 | } |
3140 | ||
3141 | val = 1; | |
3142 | goto done; | |
3143 | } | |
3144 | } | |
3145 | #endif | |
3146 | ||
08a9dd06 | 3147 | /* In this case this insn isn't serving a useful purpose. We |
3148 | will delete it in reload_as_needed once we know that this | |
3149 | elimination is, in fact, being done. | |
3150 | ||
b090827b | 3151 | If REPLACE isn't set, we can't delete this insn, but needn't |
08a9dd06 | 3152 | process it since it won't be used unless something changes. */ |
3153 | if (replace) | |
e784c52f | 3154 | { |
aedd3e94 | 3155 | delete_dead_insn (insn); |
e784c52f | 3156 | return 1; |
3157 | } | |
08a9dd06 | 3158 | val = 1; |
3159 | goto done; | |
3160 | } | |
a92fb03b | 3161 | } |
08a9dd06 | 3162 | |
a92fb03b | 3163 | /* We allow one special case which happens to work on all machines we |
9feec5c7 | 3164 | currently support: a single set with the source or a REG_EQUAL |
3165 | note being a PLUS of an eliminable register and a constant. */ | |
2e4905ea | 3166 | plus_src = plus_cst_src = 0; |
8ad4c111 | 3167 | if (old_set && REG_P (SET_DEST (old_set))) |
a92fb03b | 3168 | { |
2e4905ea | 3169 | if (GET_CODE (SET_SRC (old_set)) == PLUS) |
9feec5c7 | 3170 | plus_src = SET_SRC (old_set); |
ca42e34a | 3171 | /* First see if the source is of the form (plus (...) CST). */ |
2e4905ea | 3172 | if (plus_src |
ca42e34a | 3173 | && GET_CODE (XEXP (plus_src, 1)) == CONST_INT) |
2e4905ea | 3174 | plus_cst_src = plus_src; |
3175 | else if (REG_P (SET_SRC (old_set)) | |
3176 | || plus_src) | |
9feec5c7 | 3177 | { |
3178 | /* Otherwise, see if we have a REG_EQUAL note of the form | |
ca42e34a | 3179 | (plus (...) CST). */ |
9feec5c7 | 3180 | rtx links; |
3181 | for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) | |
3182 | { | |
ea4c8f87 | 3183 | if ((REG_NOTE_KIND (links) == REG_EQUAL |
3184 | || REG_NOTE_KIND (links) == REG_EQUIV) | |
9feec5c7 | 3185 | && GET_CODE (XEXP (links, 0)) == PLUS |
ca42e34a | 3186 | && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT) |
9feec5c7 | 3187 | { |
2e4905ea | 3188 | plus_cst_src = XEXP (links, 0); |
9feec5c7 | 3189 | break; |
3190 | } | |
3191 | } | |
3192 | } | |
ca42e34a | 3193 | |
3194 | /* Check that the first operand of the PLUS is a hard reg or | |
3195 | the lowpart subreg of one. */ | |
3196 | if (plus_cst_src) | |
3197 | { | |
3198 | rtx reg = XEXP (plus_cst_src, 0); | |
3199 | if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg)) | |
3200 | reg = SUBREG_REG (reg); | |
3201 | ||
3202 | if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) | |
3203 | plus_cst_src = 0; | |
3204 | } | |
9feec5c7 | 3205 | } |
2e4905ea | 3206 | if (plus_cst_src) |
9feec5c7 | 3207 | { |
2e4905ea | 3208 | rtx reg = XEXP (plus_cst_src, 0); |
3209 | HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1)); | |
08a9dd06 | 3210 | |
ca42e34a | 3211 | if (GET_CODE (reg) == SUBREG) |
3212 | reg = SUBREG_REG (reg); | |
3213 | ||
a92fb03b | 3214 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3215 | if (ep->from_rtx == reg && ep->can_eliminate) | |
3216 | { | |
ca42e34a | 3217 | rtx to_rtx = ep->to_rtx; |
a92fb03b | 3218 | offset += ep->offset; |
81ef6b6a | 3219 | offset = trunc_int_for_mode (offset, GET_MODE (reg)); |
08a9dd06 | 3220 | |
ca42e34a | 3221 | if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG) |
3222 | to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)), | |
3223 | to_rtx); | |
bf822070 | 3224 | /* If we have a nonzero offset, and the source is already |
3225 | a simple REG, the following transformation would | |
3226 | increase the cost of the insn by replacing a simple REG | |
3227 | with (plus (reg sp) CST). So try only when we already | |
3228 | had a PLUS before. */ | |
403ac203 | 3229 | if (offset == 0 || plus_src) |
bf822070 | 3230 | { |
403ac203 | 3231 | rtx new_src = plus_constant (to_rtx, offset); |
3232 | ||
bf822070 | 3233 | new_body = old_body; |
3234 | if (! replace) | |
3235 | { | |
3236 | new_body = copy_insn (old_body); | |
3237 | if (REG_NOTES (insn)) | |
3238 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3239 | } | |
3240 | PATTERN (insn) = new_body; | |
3241 | old_set = single_set (insn); | |
3242 | ||
403ac203 | 3243 | /* First see if this insn remains valid when we make the |
3244 | change. If not, try to replace the whole pattern with | |
3245 | a simple set (this may help if the original insn was a | |
3246 | PARALLEL that was only recognized as single_set due to | |
3247 | REG_UNUSED notes). If this isn't valid either, keep | |
3248 | the INSN_CODE the same and let reload fix it up. */ | |
3249 | if (!validate_change (insn, &SET_SRC (old_set), new_src, 0)) | |
3250 | { | |
3251 | rtx new_pat = gen_rtx_SET (VOIDmode, | |
3252 | SET_DEST (old_set), new_src); | |
3253 | ||
3254 | if (!validate_change (insn, &PATTERN (insn), new_pat, 0)) | |
3255 | SET_SRC (old_set) = new_src; | |
3256 | } | |
bf822070 | 3257 | } |
9feec5c7 | 3258 | else |
3259 | break; | |
3260 | ||
a92fb03b | 3261 | val = 1; |
3262 | /* This can't have an effect on elimination offsets, so skip right | |
3263 | to the end. */ | |
3264 | goto done; | |
3265 | } | |
08a9dd06 | 3266 | } |
3267 | ||
6b21946f | 3268 | /* Determine the effects of this insn on elimination offsets. */ |
3269 | elimination_effects (old_body, 0); | |
3270 | ||
3271 | /* Eliminate all eliminable registers occurring in operands that | |
3272 | can be handled by reload. */ | |
3273 | extract_insn (insn); | |
6b21946f | 3274 | for (i = 0; i < recog_data.n_operands; i++) |
3275 | { | |
3276 | orig_operand[i] = recog_data.operand[i]; | |
3277 | substed_operand[i] = recog_data.operand[i]; | |
3278 | ||
3279 | /* For an asm statement, every operand is eliminable. */ | |
3280 | if (insn_is_asm || insn_data[icode].operand[i].eliminable) | |
3281 | { | |
2e4905ea | 3282 | bool is_set_src, in_plus; |
3283 | ||
6b21946f | 3284 | /* Check for setting a register that we know about. */ |
3285 | if (recog_data.operand_type[i] != OP_IN | |
8ad4c111 | 3286 | && REG_P (orig_operand[i])) |
6b21946f | 3287 | { |
3288 | /* If we are assigning to a register that can be eliminated, it | |
3289 | must be as part of a PARALLEL, since the code above handles | |
3290 | single SETs. We must indicate that we can no longer | |
3291 | eliminate this reg. */ | |
3292 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
3293 | ep++) | |
aa150c9f | 3294 | if (ep->from_rtx == orig_operand[i]) |
6b21946f | 3295 | ep->can_eliminate = 0; |
3296 | } | |
3297 | ||
2e4905ea | 3298 | /* Companion to the above plus substitution, we can allow |
3299 | invariants as the source of a plain move. */ | |
3300 | is_set_src = false; | |
3301 | if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set)) | |
3302 | is_set_src = true; | |
3303 | in_plus = false; | |
3304 | if (plus_src | |
3305 | && (recog_data.operand_loc[i] == &XEXP (plus_src, 0) | |
3306 | || recog_data.operand_loc[i] == &XEXP (plus_src, 1))) | |
3307 | in_plus = true; | |
3308 | ||
3309 | substed_operand[i] | |
3310 | = eliminate_regs_1 (recog_data.operand[i], 0, | |
3311 | replace ? insn : NULL_RTX, | |
3312 | is_set_src || in_plus); | |
6b21946f | 3313 | if (substed_operand[i] != orig_operand[i]) |
805e22b2 | 3314 | val = 1; |
6b21946f | 3315 | /* Terminate the search in check_eliminable_occurrences at |
3316 | this point. */ | |
3317 | *recog_data.operand_loc[i] = 0; | |
3318 | ||
3319 | /* If an output operand changed from a REG to a MEM and INSN is an | |
3320 | insn, write a CLOBBER insn. */ | |
3321 | if (recog_data.operand_type[i] != OP_IN | |
8ad4c111 | 3322 | && REG_P (orig_operand[i]) |
e16ceb8e | 3323 | && MEM_P (substed_operand[i]) |
6b21946f | 3324 | && replace) |
3325 | emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]), | |
3326 | insn); | |
3327 | } | |
3328 | } | |
3329 | ||
3330 | for (i = 0; i < recog_data.n_dups; i++) | |
3331 | *recog_data.dup_loc[i] | |
aedd3e94 | 3332 | = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; |
6b21946f | 3333 | |
3334 | /* If any eliminable remain, they aren't eliminable anymore. */ | |
3335 | check_eliminable_occurrences (old_body); | |
08a9dd06 | 3336 | |
6b21946f | 3337 | /* Substitute the operands; the new values are in the substed_operand |
3338 | array. */ | |
3339 | for (i = 0; i < recog_data.n_operands; i++) | |
3340 | *recog_data.operand_loc[i] = substed_operand[i]; | |
3341 | for (i = 0; i < recog_data.n_dups; i++) | |
aedd3e94 | 3342 | *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]]; |
08a9dd06 | 3343 | |
6b21946f | 3344 | /* If we are replacing a body that was a (set X (plus Y Z)), try to |
08a9dd06 | 3345 | re-recognize the insn. We do this in case we had a simple addition |
3346 | but now can do this as a load-address. This saves an insn in this | |
6b21946f | 3347 | common case. |
3348 | If re-recognition fails, the old insn code number will still be used, | |
3349 | and some register operands may have changed into PLUS expressions. | |
3350 | These will be handled by find_reloads by loading them into a register | |
aedd3e94 | 3351 | again. */ |
08a9dd06 | 3352 | |
6b21946f | 3353 | if (val) |
08a9dd06 | 3354 | { |
721e78c7 | 3355 | /* If we aren't replacing things permanently and we changed something, |
3356 | make another copy to ensure that all the RTL is new. Otherwise | |
3357 | things can go wrong if find_reload swaps commutative operands | |
a92771b8 | 3358 | and one is inside RTL that has been copied while the other is not. */ |
6b21946f | 3359 | new_body = old_body; |
3360 | if (! replace) | |
af518e28 | 3361 | { |
3362 | new_body = copy_insn (old_body); | |
3363 | if (REG_NOTES (insn)) | |
3364 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3365 | } | |
6b21946f | 3366 | PATTERN (insn) = new_body; |
721e78c7 | 3367 | |
d92d1db8 | 3368 | /* If we had a move insn but now we don't, rerecognize it. This will |
3369 | cause spurious re-recognition if the old move had a PARALLEL since | |
3370 | the new one still will, but we can't call single_set without | |
3371 | having put NEW_BODY into the insn and the re-recognition won't | |
3372 | hurt in this rare case. */ | |
6b21946f | 3373 | /* ??? Why this huge if statement - why don't we just rerecognize the |
3374 | thing always? */ | |
3375 | if (! insn_is_asm | |
3376 | && old_set != 0 | |
8ad4c111 | 3377 | && ((REG_P (SET_SRC (old_set)) |
d92d1db8 | 3378 | && (GET_CODE (new_body) != SET |
8ad4c111 | 3379 | || !REG_P (SET_SRC (new_body)))) |
d92d1db8 | 3380 | /* If this was a load from or store to memory, compare |
ed420a25 | 3381 | the MEM in recog_data.operand to the one in the insn. |
3382 | If they are not equal, then rerecognize the insn. */ | |
d92d1db8 | 3383 | || (old_set != 0 |
e16ceb8e | 3384 | && ((MEM_P (SET_SRC (old_set)) |
ed420a25 | 3385 | && SET_SRC (old_set) != recog_data.operand[1]) |
e16ceb8e | 3386 | || (MEM_P (SET_DEST (old_set)) |
ed420a25 | 3387 | && SET_DEST (old_set) != recog_data.operand[0]))) |
d92d1db8 | 3388 | /* If this was an add insn before, rerecognize. */ |
3389 | || GET_CODE (SET_SRC (old_set)) == PLUS)) | |
eb77fc03 | 3390 | { |
6b21946f | 3391 | int new_icode = recog (PATTERN (insn), insn, 0); |
0919df43 | 3392 | if (new_icode >= 0) |
3393 | INSN_CODE (insn) = new_icode; | |
eb77fc03 | 3394 | } |
6b21946f | 3395 | } |
08a9dd06 | 3396 | |
6b21946f | 3397 | /* Restore the old body. If there were any changes to it, we made a copy |
3398 | of it while the changes were still in place, so we'll correctly return | |
3399 | a modified insn below. */ | |
3400 | if (! replace) | |
3401 | { | |
3402 | /* Restore the old body. */ | |
3403 | for (i = 0; i < recog_data.n_operands; i++) | |
3404 | *recog_data.operand_loc[i] = orig_operand[i]; | |
3405 | for (i = 0; i < recog_data.n_dups; i++) | |
aedd3e94 | 3406 | *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; |
08a9dd06 | 3407 | } |
c8ad158d | 3408 | |
6b21946f | 3409 | /* Update all elimination pairs to reflect the status after the current |
3410 | insn. The changes we make were determined by the earlier call to | |
3411 | elimination_effects. | |
ca9902fc | 3412 | |
e61c498c | 3413 | We also detect cases where register elimination cannot be done, |
08a9dd06 | 3414 | namely, if a register would be both changed and referenced outside a MEM |
3415 | in the resulting insn since such an insn is often undefined and, even if | |
3416 | not, we cannot know what meaning will be given to it. Note that it is | |
3417 | valid to have a register used in an address in an insn that changes it | |
3418 | (presumably with a pre- or post-increment or decrement). | |
3419 | ||
3420 | If anything changes, return nonzero. */ | |
3421 | ||
08a9dd06 | 3422 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3423 | { | |
3424 | if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | |
3425 | ep->can_eliminate = 0; | |
3426 | ||
3427 | ep->ref_outside_mem = 0; | |
3428 | ||
3429 | if (ep->previous_offset != ep->offset) | |
3430 | val = 1; | |
08a9dd06 | 3431 | } |
3432 | ||
3433 | done: | |
c3418f42 | 3434 | /* If we changed something, perform elimination in REG_NOTES. This is |
afca26e1 | 3435 | needed even when REPLACE is zero because a REG_DEAD note might refer |
3436 | to a register that we eliminate and could cause a different number | |
3437 | of spill registers to be needed in the final reload pass than in | |
3438 | the pre-passes. */ | |
1d5f8a5b | 3439 | if (val && REG_NOTES (insn) != 0) |
2e4905ea | 3440 | REG_NOTES (insn) |
3441 | = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true); | |
afca26e1 | 3442 | |
08a9dd06 | 3443 | return val; |
3444 | } | |
3445 | ||
93c7b06e | 3446 | /* Loop through all elimination pairs. |
3447 | Recalculate the number not at initial offset. | |
3448 | ||
3449 | Compute the maximum offset (minimum offset if the stack does not | |
3450 | grow downward) for each elimination pair. */ | |
3451 | ||
3452 | static void | |
3ad4992f | 3453 | update_eliminable_offsets (void) |
93c7b06e | 3454 | { |
3455 | struct elim_table *ep; | |
3456 | ||
3457 | num_not_at_initial_offset = 0; | |
3458 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3459 | { | |
3460 | ep->previous_offset = ep->offset; | |
3461 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3462 | num_not_at_initial_offset++; | |
93c7b06e | 3463 | } |
3464 | } | |
3465 | ||
08a9dd06 | 3466 | /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register |
3467 | replacement we currently believe is valid, mark it as not eliminable if X | |
3468 | modifies DEST in any way other than by adding a constant integer to it. | |
3469 | ||
3470 | If DEST is the frame pointer, we do nothing because we assume that | |
ecbd56da | 3471 | all assignments to the hard frame pointer are nonlocal gotos and are being |
3472 | done at a time when they are valid and do not disturb anything else. | |
08a9dd06 | 3473 | Some machines want to eliminate a fake argument pointer with either the |
ecbd56da | 3474 | frame or stack pointer. Assignments to the hard frame pointer must not |
3475 | prevent this elimination. | |
08a9dd06 | 3476 | |
3477 | Called via note_stores from reload before starting its passes to scan | |
3478 | the insns of the function. */ | |
3479 | ||
3480 | static void | |
3ad4992f | 3481 | mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED) |
08a9dd06 | 3482 | { |
19cb6b50 | 3483 | unsigned int i; |
08a9dd06 | 3484 | |
3485 | /* A SUBREG of a hard register here is just changing its mode. We should | |
3486 | not see a SUBREG of an eliminable hard register, but check just in | |
3487 | case. */ | |
3488 | if (GET_CODE (dest) == SUBREG) | |
3489 | dest = SUBREG_REG (dest); | |
3490 | ||
ecbd56da | 3491 | if (dest == hard_frame_pointer_rtx) |
08a9dd06 | 3492 | return; |
3493 | ||
3494 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3495 | if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx | |
3496 | && (GET_CODE (x) != SET | |
3497 | || GET_CODE (SET_SRC (x)) != PLUS | |
3498 | || XEXP (SET_SRC (x), 0) != dest | |
3499 | || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) | |
3500 | { | |
3501 | reg_eliminate[i].can_eliminate_previous | |
3502 | = reg_eliminate[i].can_eliminate = 0; | |
3503 | num_eliminable--; | |
3504 | } | |
3505 | } | |
9d24e570 | 3506 | |
8ad9ded8 | 3507 | /* Verify that the initial elimination offsets did not change since the |
3508 | last call to set_initial_elim_offsets. This is used to catch cases | |
3509 | where something illegal happened during reload_as_needed that could | |
3510 | cause incorrect code to be generated if we did not check for it. */ | |
29768226 | 3511 | |
ba0fef14 | 3512 | static bool |
3ad4992f | 3513 | verify_initial_elim_offsets (void) |
8ad9ded8 | 3514 | { |
ec96de93 | 3515 | HOST_WIDE_INT t; |
8ad9ded8 | 3516 | |
ba0fef14 | 3517 | if (!num_eliminable) |
3518 | return true; | |
3519 | ||
8ad9ded8 | 3520 | #ifdef ELIMINABLE_REGS |
65dbb427 | 3521 | { |
3522 | struct elim_table *ep; | |
3523 | ||
3524 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3525 | { | |
3526 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); | |
3527 | if (t != ep->initial_offset) | |
3528 | return false; | |
3529 | } | |
3530 | } | |
8ad9ded8 | 3531 | #else |
3532 | INITIAL_FRAME_POINTER_OFFSET (t); | |
ba0fef14 | 3533 | if (t != reg_eliminate[0].initial_offset) |
3534 | return false; | |
5bb2f919 | 3535 | #endif |
ba0fef14 | 3536 | |
3537 | return true; | |
8ad9ded8 | 3538 | } |
3539 | ||
9d24e570 | 3540 | /* Reset all offsets on eliminable registers to their initial values. */ |
dccf4eb3 | 3541 | |
9d24e570 | 3542 | static void |
3ad4992f | 3543 | set_initial_elim_offsets (void) |
9d24e570 | 3544 | { |
f87f6d5d | 3545 | struct elim_table *ep = reg_eliminate; |
9d24e570 | 3546 | |
3547 | #ifdef ELIMINABLE_REGS | |
f87f6d5d | 3548 | for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
9d24e570 | 3549 | { |
3550 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); | |
f87f6d5d | 3551 | ep->previous_offset = ep->offset = ep->initial_offset; |
9d24e570 | 3552 | } |
3553 | #else | |
f87f6d5d | 3554 | INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); |
3555 | ep->previous_offset = ep->offset = ep->initial_offset; | |
9d24e570 | 3556 | #endif |
3557 | ||
3558 | num_not_at_initial_offset = 0; | |
f87f6d5d | 3559 | } |
9d24e570 | 3560 | |
b471f4db | 3561 | /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */ |
3562 | ||
3563 | static void | |
3564 | set_initial_eh_label_offset (rtx label) | |
3565 | { | |
3566 | set_label_offsets (label, NULL_RTX, 1); | |
3567 | } | |
3568 | ||
f87f6d5d | 3569 | /* Initialize the known label offsets. |
3570 | Set a known offset for each forced label to be at the initial offset | |
3571 | of each elimination. We do this because we assume that all | |
3572 | computed jumps occur from a location where each elimination is | |
3573 | at its initial offset. | |
3574 | For all other labels, show that we don't know the offsets. */ | |
9d24e570 | 3575 | |
f87f6d5d | 3576 | static void |
3ad4992f | 3577 | set_initial_label_offsets (void) |
f87f6d5d | 3578 | { |
3579 | rtx x; | |
2ff147ce | 3580 | memset (offsets_known_at, 0, num_labels); |
9d24e570 | 3581 | |
3582 | for (x = forced_labels; x; x = XEXP (x, 1)) | |
3583 | if (XEXP (x, 0)) | |
3584 | set_label_offsets (XEXP (x, 0), NULL_RTX, 1); | |
b471f4db | 3585 | |
3586 | for_each_eh_label (set_initial_eh_label_offset); | |
9d24e570 | 3587 | } |
3588 | ||
f87f6d5d | 3589 | /* Set all elimination offsets to the known values for the code label given |
3590 | by INSN. */ | |
dccf4eb3 | 3591 | |
f87f6d5d | 3592 | static void |
3ad4992f | 3593 | set_offsets_for_label (rtx insn) |
f87f6d5d | 3594 | { |
3c1d7436 | 3595 | unsigned int i; |
f87f6d5d | 3596 | int label_nr = CODE_LABEL_NUMBER (insn); |
3597 | struct elim_table *ep; | |
3598 | ||
3599 | num_not_at_initial_offset = 0; | |
3600 | for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) | |
3601 | { | |
2ff147ce | 3602 | ep->offset = ep->previous_offset |
3603 | = offsets_at[label_nr - first_label_num][i]; | |
f87f6d5d | 3604 | if (ep->can_eliminate && ep->offset != ep->initial_offset) |
3605 | num_not_at_initial_offset++; | |
3606 | } | |
3607 | } | |
3608 | ||
9d24e570 | 3609 | /* See if anything that happened changes which eliminations are valid. |
7800959d | 3610 | For example, on the SPARC, whether or not the frame pointer can |
9d24e570 | 3611 | be eliminated can depend on what registers have been used. We need |
3612 | not check some conditions again (such as flag_omit_frame_pointer) | |
3613 | since they can't have changed. */ | |
3614 | ||
3615 | static void | |
3ad4992f | 3616 | update_eliminables (HARD_REG_SET *pset) |
9d24e570 | 3617 | { |
9d24e570 | 3618 | int previous_frame_pointer_needed = frame_pointer_needed; |
9d24e570 | 3619 | struct elim_table *ep; |
3620 | ||
3621 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3622 | if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) | |
3623 | #ifdef ELIMINABLE_REGS | |
3624 | || ! CAN_ELIMINATE (ep->from, ep->to) | |
3625 | #endif | |
3626 | ) | |
3627 | ep->can_eliminate = 0; | |
3628 | ||
3629 | /* Look for the case where we have discovered that we can't replace | |
3630 | register A with register B and that means that we will now be | |
3631 | trying to replace register A with register C. This means we can | |
3632 | no longer replace register C with register B and we need to disable | |
3633 | such an elimination, if it exists. This occurs often with A == ap, | |
3634 | B == sp, and C == fp. */ | |
3635 | ||
3636 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3637 | { | |
3638 | struct elim_table *op; | |
19cb6b50 | 3639 | int new_to = -1; |
9d24e570 | 3640 | |
3641 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3642 | { | |
3643 | /* Find the current elimination for ep->from, if there is a | |
3644 | new one. */ | |
3645 | for (op = reg_eliminate; | |
3646 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3647 | if (op->from == ep->from && op->can_eliminate) | |
3648 | { | |
3649 | new_to = op->to; | |
3650 | break; | |
3651 | } | |
3652 | ||
3653 | /* See if there is an elimination of NEW_TO -> EP->TO. If so, | |
3654 | disable it. */ | |
3655 | for (op = reg_eliminate; | |
3656 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3657 | if (op->from == new_to && op->to == ep->to) | |
3658 | op->can_eliminate = 0; | |
3659 | } | |
3660 | } | |
3661 | ||
3662 | /* See if any registers that we thought we could eliminate the previous | |
3663 | time are no longer eliminable. If so, something has changed and we | |
3664 | must spill the register. Also, recompute the number of eliminable | |
3665 | registers and see if the frame pointer is needed; it is if there is | |
3666 | no elimination of the frame pointer that we can perform. */ | |
3667 | ||
3668 | frame_pointer_needed = 1; | |
3669 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3670 | { | |
3671 | if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM | |
3672 | && ep->to != HARD_FRAME_POINTER_REGNUM) | |
3673 | frame_pointer_needed = 0; | |
3674 | ||
3675 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3676 | { | |
3677 | ep->can_eliminate_previous = 0; | |
3678 | SET_HARD_REG_BIT (*pset, ep->from); | |
3679 | num_eliminable--; | |
3680 | } | |
3681 | } | |
3682 | ||
9d24e570 | 3683 | /* If we didn't need a frame pointer last time, but we do now, spill |
3684 | the hard frame pointer. */ | |
3685 | if (frame_pointer_needed && ! previous_frame_pointer_needed) | |
3686 | SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); | |
9d24e570 | 3687 | } |
3688 | ||
eca883d1 | 3689 | /* Return true if X is used as the target register of an elimination. */ |
3690 | ||
3691 | bool | |
3692 | elimination_target_reg_p (rtx x) | |
3693 | { | |
3694 | struct elim_table *ep; | |
3695 | ||
3696 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3697 | if (ep->to_rtx == x && ep->can_eliminate) | |
3698 | return true; | |
3699 | ||
3700 | return false; | |
3701 | } | |
3702 | ||
9d24e570 | 3703 | /* Initialize the table of registers to eliminate. */ |
dccf4eb3 | 3704 | |
9d24e570 | 3705 | static void |
3ad4992f | 3706 | init_elim_table (void) |
9d24e570 | 3707 | { |
3708 | struct elim_table *ep; | |
911d0ac2 | 3709 | #ifdef ELIMINABLE_REGS |
e7c691ac | 3710 | const struct elim_table_1 *ep1; |
911d0ac2 | 3711 | #endif |
9d24e570 | 3712 | |
911d0ac2 | 3713 | if (!reg_eliminate) |
f0af5a88 | 3714 | reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS); |
5bb2f919 | 3715 | |
9d24e570 | 3716 | /* Does this function require a frame pointer? */ |
3717 | ||
3718 | frame_pointer_needed = (! flag_omit_frame_pointer | |
9d24e570 | 3719 | /* ?? If EXIT_IGNORE_STACK is set, we will not save |
3720 | and restore sp for alloca. So we can't eliminate | |
3721 | the frame pointer in that case. At some point, | |
3722 | we should improve this by emitting the | |
3723 | sp-adjusting insns for this case. */ | |
3724 | || (current_function_calls_alloca | |
3725 | && EXIT_IGNORE_STACK) | |
e3e15c50 | 3726 | || current_function_accesses_prior_frames |
9d24e570 | 3727 | || FRAME_POINTER_REQUIRED); |
3728 | ||
3729 | num_eliminable = 0; | |
3730 | ||
3731 | #ifdef ELIMINABLE_REGS | |
911d0ac2 | 3732 | for (ep = reg_eliminate, ep1 = reg_eliminate_1; |
3733 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) | |
9d24e570 | 3734 | { |
911d0ac2 | 3735 | ep->from = ep1->from; |
3736 | ep->to = ep1->to; | |
9d24e570 | 3737 | ep->can_eliminate = ep->can_eliminate_previous |
3738 | = (CAN_ELIMINATE (ep->from, ep->to) | |
3739 | && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed)); | |
3740 | } | |
3741 | #else | |
911d0ac2 | 3742 | reg_eliminate[0].from = reg_eliminate_1[0].from; |
3743 | reg_eliminate[0].to = reg_eliminate_1[0].to; | |
9d24e570 | 3744 | reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous |
3745 | = ! frame_pointer_needed; | |
3746 | #endif | |
3747 | ||
3748 | /* Count the number of eliminable registers and build the FROM and TO | |
27a9551b | 3749 | REG rtx's. Note that code in gen_rtx_REG will cause, e.g., |
943d05fc | 3750 | gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. |
9d24e570 | 3751 | We depend on this. */ |
3752 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3753 | { | |
3754 | num_eliminable += ep->can_eliminate; | |
3755 | ep->from_rtx = gen_rtx_REG (Pmode, ep->from); | |
3756 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | |
3757 | } | |
3758 | } | |
08a9dd06 | 3759 | \f |
3760 | /* Kick all pseudos out of hard register REGNO. | |
08a9dd06 | 3761 | |
3762 | If CANT_ELIMINATE is nonzero, it means that we are doing this spill | |
3763 | because we found we can't eliminate some register. In the case, no pseudos | |
3764 | are allowed to be in the register, even if they are only in a block that | |
3765 | doesn't require spill registers, unlike the case when we are spilling this | |
3766 | hard reg to produce another spill register. | |
3767 | ||
3768 | Return nonzero if any pseudos needed to be kicked out. */ | |
3769 | ||
dab171c5 | 3770 | static void |
3ad4992f | 3771 | spill_hard_reg (unsigned int regno, int cant_eliminate) |
08a9dd06 | 3772 | { |
19cb6b50 | 3773 | int i; |
08a9dd06 | 3774 | |
0394c2e6 | 3775 | if (cant_eliminate) |
dab171c5 | 3776 | { |
3777 | SET_HARD_REG_BIT (bad_spill_regs_global, regno); | |
3072d30e | 3778 | df_set_regs_ever_live (regno, true); |
dab171c5 | 3779 | } |
0394c2e6 | 3780 | |
08a9dd06 | 3781 | /* Spill every pseudo reg that was allocated to this reg |
3782 | or to something that overlaps this reg. */ | |
3783 | ||
3784 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3785 | if (reg_renumber[i] >= 0 | |
02e7a332 | 3786 | && (unsigned int) reg_renumber[i] <= regno |
a2c6f0b7 | 3787 | && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno) |
fbf51e51 | 3788 | SET_REGNO_REG_SET (&spilled_pseudos, i); |
dab171c5 | 3789 | } |
08a9dd06 | 3790 | |
dab171c5 | 3791 | /* After find_reload_regs has been run for all insn that need reloads, |
3792 | and/or spill_hard_regs was called, this function is used to actually | |
3793 | spill pseudo registers and try to reallocate them. It also sets up the | |
3794 | spill_regs array for use by choose_reload_regs. */ | |
c8ad158d | 3795 | |
dab171c5 | 3796 | static int |
3ad4992f | 3797 | finish_spills (int global) |
dab171c5 | 3798 | { |
3799 | struct insn_chain *chain; | |
3800 | int something_changed = 0; | |
4f917ffe | 3801 | unsigned i; |
8c97cf13 | 3802 | reg_set_iterator rsi; |
dab171c5 | 3803 | |
3804 | /* Build the spill_regs array for the function. */ | |
3805 | /* If there are some registers still to eliminate and one of the spill regs | |
3806 | wasn't ever used before, additional stack space may have to be | |
3807 | allocated to store this register. Thus, we may have changed the offset | |
3808 | between the stack and frame pointers, so mark that something has changed. | |
08a9dd06 | 3809 | |
dab171c5 | 3810 | One might think that we need only set VAL to 1 if this is a call-used |
3811 | register. However, the set of registers that must be saved by the | |
3812 | prologue is not identical to the call-used set. For example, the | |
3813 | register used by the call insn for the return PC is a call-used register, | |
3814 | but must be saved by the prologue. */ | |
3815 | ||
3816 | n_spills = 0; | |
3817 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3818 | if (TEST_HARD_REG_BIT (used_spill_regs, i)) | |
3819 | { | |
3820 | spill_reg_order[i] = n_spills; | |
3821 | spill_regs[n_spills++] = i; | |
3072d30e | 3822 | if (num_eliminable && ! df_regs_ever_live_p (i)) |
dab171c5 | 3823 | something_changed = 1; |
3072d30e | 3824 | df_set_regs_ever_live (i, true); |
dab171c5 | 3825 | } |
3826 | else | |
3827 | spill_reg_order[i] = -1; | |
3828 | ||
8c97cf13 | 3829 | EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi) |
3830 | { | |
3831 | /* Record the current hard register the pseudo is allocated to in | |
3832 | pseudo_previous_regs so we avoid reallocating it to the same | |
3833 | hard reg in a later pass. */ | |
3834 | gcc_assert (reg_renumber[i] >= 0); | |
3835 | ||
3836 | SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); | |
3837 | /* Mark it as no longer having a hard register home. */ | |
3838 | reg_renumber[i] = -1; | |
3839 | /* We will need to scan everything again. */ | |
3840 | something_changed = 1; | |
3841 | } | |
590ec786 | 3842 | |
dab171c5 | 3843 | /* Retry global register allocation if possible. */ |
3844 | if (global) | |
3845 | { | |
f0af5a88 | 3846 | memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET)); |
dab171c5 | 3847 | /* For every insn that needs reloads, set the registers used as spill |
3848 | regs in pseudo_forbidden_regs for every pseudo live across the | |
3849 | insn. */ | |
3850 | for (chain = insns_need_reload; chain; chain = chain->next_need_reload) | |
3851 | { | |
3852 | EXECUTE_IF_SET_IN_REG_SET | |
8c97cf13 | 3853 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi) |
3854 | { | |
40290b32 | 3855 | IOR_HARD_REG_SET (pseudo_forbidden_regs[i], |
3856 | chain->used_spill_regs); | |
8c97cf13 | 3857 | } |
dab171c5 | 3858 | EXECUTE_IF_SET_IN_REG_SET |
8c97cf13 | 3859 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi) |
3860 | { | |
40290b32 | 3861 | IOR_HARD_REG_SET (pseudo_forbidden_regs[i], |
3862 | chain->used_spill_regs); | |
8c97cf13 | 3863 | } |
dab171c5 | 3864 | } |
590ec786 | 3865 | |
dab171c5 | 3866 | /* Retry allocating the spilled pseudos. For each reg, merge the |
3867 | various reg sets that indicate which hard regs can't be used, | |
3868 | and call retry_global_alloc. | |
5bb2f919 | 3869 | We change spill_pseudos here to only contain pseudos that did not |
dab171c5 | 3870 | get a new hard register. */ |
4f917ffe | 3871 | for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++) |
dab171c5 | 3872 | if (reg_old_renumber[i] != reg_renumber[i]) |
08a9dd06 | 3873 | { |
dab171c5 | 3874 | HARD_REG_SET forbidden; |
3875 | COPY_HARD_REG_SET (forbidden, bad_spill_regs_global); | |
3876 | IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]); | |
3877 | IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]); | |
3878 | retry_global_alloc (i, forbidden); | |
3879 | if (reg_renumber[i] >= 0) | |
fbf51e51 | 3880 | CLEAR_REGNO_REG_SET (&spilled_pseudos, i); |
08a9dd06 | 3881 | } |
dab171c5 | 3882 | } |
590ec786 | 3883 | |
dab171c5 | 3884 | /* Fix up the register information in the insn chain. |
3885 | This involves deleting those of the spilled pseudos which did not get | |
3886 | a new hard register home from the live_{before,after} sets. */ | |
590ec786 | 3887 | for (chain = reload_insn_chain; chain; chain = chain->next) |
3888 | { | |
dab171c5 | 3889 | HARD_REG_SET used_by_pseudos; |
3890 | HARD_REG_SET used_by_pseudos2; | |
3891 | ||
f62c22a7 | 3892 | AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); |
3893 | AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); | |
dab171c5 | 3894 | |
3895 | /* Mark any unallocated hard regs as available for spills. That | |
3896 | makes inheritance work somewhat better. */ | |
3897 | if (chain->need_reload) | |
3898 | { | |
f62c22a7 | 3899 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); |
3900 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
dab171c5 | 3901 | IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); |
3902 | ||
3903 | /* Save the old value for the sanity test below. */ | |
3904 | COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs); | |
3905 | ||
f62c22a7 | 3906 | compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); |
3907 | compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); | |
dab171c5 | 3908 | COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); |
3909 | AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); | |
3910 | ||
3911 | /* Make sure we only enlarge the set. */ | |
ddc556d1 | 3912 | gcc_assert (hard_reg_set_subset_p (used_by_pseudos2, |
3913 | chain->used_spill_regs)); | |
dab171c5 | 3914 | } |
590ec786 | 3915 | } |
dab171c5 | 3916 | |
3917 | /* Let alter_reg modify the reg rtx's for the modified pseudos. */ | |
4f917ffe | 3918 | for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++) |
dab171c5 | 3919 | { |
3920 | int regno = reg_renumber[i]; | |
3921 | if (reg_old_renumber[i] == regno) | |
3922 | continue; | |
5bb2f919 | 3923 | |
dab171c5 | 3924 | alter_reg (i, reg_old_renumber[i]); |
3925 | reg_old_renumber[i] = regno; | |
450d042a | 3926 | if (dump_file) |
dab171c5 | 3927 | { |
3928 | if (regno == -1) | |
450d042a | 3929 | fprintf (dump_file, " Register %d now on stack.\n\n", i); |
dab171c5 | 3930 | else |
450d042a | 3931 | fprintf (dump_file, " Register %d now in %d.\n\n", |
dab171c5 | 3932 | i, reg_renumber[i]); |
3933 | } | |
3934 | } | |
3935 | ||
3936 | return something_changed; | |
590ec786 | 3937 | } |
08a9dd06 | 3938 | \f |
d40bf399 | 3939 | /* Find all paradoxical subregs within X and update reg_max_ref_width. */ |
08a9dd06 | 3940 | |
3941 | static void | |
3ad4992f | 3942 | scan_paradoxical_subregs (rtx x) |
08a9dd06 | 3943 | { |
19cb6b50 | 3944 | int i; |
3945 | const char *fmt; | |
3946 | enum rtx_code code = GET_CODE (x); | |
08a9dd06 | 3947 | |
3948 | switch (code) | |
3949 | { | |
e715e2a3 | 3950 | case REG: |
08a9dd06 | 3951 | case CONST_INT: |
3952 | case CONST: | |
3953 | case SYMBOL_REF: | |
3954 | case LABEL_REF: | |
3955 | case CONST_DOUBLE: | |
886cfd4f | 3956 | case CONST_VECTOR: /* shouldn't happen, but just in case. */ |
08a9dd06 | 3957 | case CC0: |
3958 | case PC: | |
08a9dd06 | 3959 | case USE: |
3960 | case CLOBBER: | |
3961 | return; | |
3962 | ||
3963 | case SUBREG: | |
8ad4c111 | 3964 | if (REG_P (SUBREG_REG (x)) |
595d62e9 | 3965 | && (GET_MODE_SIZE (GET_MODE (x)) |
3966 | > reg_max_ref_width[REGNO (SUBREG_REG (x))])) | |
3072d30e | 3967 | { |
3968 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
3969 | = GET_MODE_SIZE (GET_MODE (x)); | |
3970 | mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x)); | |
3971 | } | |
08a9dd06 | 3972 | return; |
5bb2f919 | 3973 | |
0dbd1c74 | 3974 | default: |
3975 | break; | |
08a9dd06 | 3976 | } |
3977 | ||
3978 | fmt = GET_RTX_FORMAT (code); | |
3979 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3980 | { | |
3981 | if (fmt[i] == 'e') | |
3982 | scan_paradoxical_subregs (XEXP (x, i)); | |
3983 | else if (fmt[i] == 'E') | |
3984 | { | |
19cb6b50 | 3985 | int j; |
aedd3e94 | 3986 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
08a9dd06 | 3987 | scan_paradoxical_subregs (XVECEXP (x, i, j)); |
3988 | } | |
3989 | } | |
3990 | } | |
3991 | \f | |
43283c91 | 3992 | /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note, |
3993 | examine all of the reload insns between PREV and NEXT exclusive, and | |
3994 | annotate all that may trap. */ | |
3995 | ||
3996 | static void | |
3997 | fixup_eh_region_note (rtx insn, rtx prev, rtx next) | |
3998 | { | |
3999 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
4000 | unsigned int trap_count; | |
4001 | rtx i; | |
4002 | ||
4003 | if (note == NULL) | |
4004 | return; | |
4005 | ||
4006 | if (may_trap_p (PATTERN (insn))) | |
4007 | trap_count = 1; | |
4008 | else | |
4009 | { | |
4010 | remove_note (insn, note); | |
4011 | trap_count = 0; | |
4012 | } | |
4013 | ||
4014 | for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i)) | |
4015 | if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i))) | |
4016 | { | |
4017 | trap_count++; | |
4018 | REG_NOTES (i) | |
4019 | = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i)); | |
4020 | } | |
43283c91 | 4021 | } |
4022 | ||
08a9dd06 | 4023 | /* Reload pseudo-registers into hard regs around each insn as needed. |
4024 | Additional register load insns are output before the insn that needs it | |
4025 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
4026 | ||
4027 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
a6f0d869 | 4028 | which registers are already available in reload registers. |
08a9dd06 | 4029 | We update these for the reloads that we perform, |
4030 | as the insns are scanned. */ | |
4031 | ||
4032 | static void | |
3ad4992f | 4033 | reload_as_needed (int live_known) |
08a9dd06 | 4034 | { |
590ec786 | 4035 | struct insn_chain *chain; |
349858d4 | 4036 | #if defined (AUTO_INC_DEC) |
19cb6b50 | 4037 | int i; |
3c1d7436 | 4038 | #endif |
08a9dd06 | 4039 | rtx x; |
08a9dd06 | 4040 | |
f0af5a88 | 4041 | memset (spill_reg_rtx, 0, sizeof spill_reg_rtx); |
4042 | memset (spill_reg_store, 0, sizeof spill_reg_store); | |
4c36ffe6 | 4043 | reg_last_reload_reg = XCNEWVEC (rtx, max_regno); |
7d742877 | 4044 | INIT_REG_SET (®_has_output_reload); |
a5e95c30 | 4045 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
e467c16e | 4046 | CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered); |
08a9dd06 | 4047 | |
f87f6d5d | 4048 | set_initial_elim_offsets (); |
08a9dd06 | 4049 | |
590ec786 | 4050 | for (chain = reload_insn_chain; chain; chain = chain->next) |
08a9dd06 | 4051 | { |
aec26802 | 4052 | rtx prev = 0; |
590ec786 | 4053 | rtx insn = chain->insn; |
4054 | rtx old_next = NEXT_INSN (insn); | |
08a9dd06 | 4055 | |
4056 | /* If we pass a label, copy the offsets from the label information | |
4057 | into the current offsets of each elimination. */ | |
6d7dc5b9 | 4058 | if (LABEL_P (insn)) |
f87f6d5d | 4059 | set_offsets_for_label (insn); |
08a9dd06 | 4060 | |
9204e736 | 4061 | else if (INSN_P (insn)) |
08a9dd06 | 4062 | { |
94aa2a3c | 4063 | regset_head regs_to_forget; |
4064 | INIT_REG_SET (®s_to_forget); | |
4065 | note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget); | |
9ef537cb | 4066 | |
a22e7476 | 4067 | /* If this is a USE and CLOBBER of a MEM, ensure that any |
4068 | references to eliminable registers have been removed. */ | |
4069 | ||
4070 | if ((GET_CODE (PATTERN (insn)) == USE | |
4071 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
e16ceb8e | 4072 | && MEM_P (XEXP (PATTERN (insn), 0))) |
a22e7476 | 4073 | XEXP (XEXP (PATTERN (insn), 0), 0) |
4074 | = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), | |
e87a9401 | 4075 | GET_MODE (XEXP (PATTERN (insn), 0)), |
6182a80f | 4076 | NULL_RTX); |
a22e7476 | 4077 | |
08a9dd06 | 4078 | /* If we need to do register elimination processing, do so. |
4079 | This might delete the insn, in which case we are done. */ | |
aa8d28af | 4080 | if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) |
08a9dd06 | 4081 | { |
4082 | eliminate_regs_in_insn (insn, 1); | |
6d7dc5b9 | 4083 | if (NOTE_P (insn)) |
93c7b06e | 4084 | { |
4085 | update_eliminable_offsets (); | |
94aa2a3c | 4086 | CLEAR_REG_SET (®s_to_forget); |
93c7b06e | 4087 | continue; |
4088 | } | |
08a9dd06 | 4089 | } |
4090 | ||
590ec786 | 4091 | /* If need_elim is nonzero but need_reload is zero, one might think |
4092 | that we could simply set n_reloads to 0. However, find_reloads | |
4093 | could have done some manipulation of the insn (such as swapping | |
4094 | commutative operands), and these manipulations are lost during | |
4095 | the first pass for every insn that needs register elimination. | |
4096 | So the actions of find_reloads must be redone here. */ | |
4097 | ||
dab171c5 | 4098 | if (! chain->need_elim && ! chain->need_reload |
4099 | && ! chain->need_operand_change) | |
08a9dd06 | 4100 | n_reloads = 0; |
4101 | /* First find the pseudo regs that must be reloaded for this insn. | |
4102 | This info is returned in the tables reload_... (see reload.h). | |
4103 | Also modify the body of INSN by substituting RELOAD | |
4104 | rtx's for those pseudo regs. */ | |
4105 | else | |
4106 | { | |
7d742877 | 4107 | CLEAR_REG_SET (®_has_output_reload); |
08a9dd06 | 4108 | CLEAR_HARD_REG_SET (reg_is_output_reload); |
4109 | ||
4110 | find_reloads (insn, 1, spill_indirect_levels, live_known, | |
4111 | spill_reg_order); | |
4112 | } | |
4113 | ||
4114 | if (n_reloads > 0) | |
4115 | { | |
93c7b06e | 4116 | rtx next = NEXT_INSN (insn); |
bb552490 | 4117 | rtx p; |
08a9dd06 | 4118 | |
93c7b06e | 4119 | prev = PREV_INSN (insn); |
4120 | ||
08a9dd06 | 4121 | /* Now compute which reload regs to reload them into. Perhaps |
4122 | reusing reload regs from previous insns, or else output | |
4123 | load insns to reload them. Maybe output store insns too. | |
4124 | Record the choices of reload reg in reload_reg_rtx. */ | |
dab171c5 | 4125 | choose_reload_regs (chain); |
08a9dd06 | 4126 | |
5bb2f919 | 4127 | /* Merge any reloads that we didn't combine for fear of |
81d0fbb3 | 4128 | increasing the number of spill registers needed but now |
4129 | discover can be safely merged. */ | |
2fcd559a | 4130 | if (SMALL_REGISTER_CLASSES) |
4131 | merge_assigned_reloads (insn); | |
81d0fbb3 | 4132 | |
08a9dd06 | 4133 | /* Generate the insns to reload operands into or out of |
4134 | their reload regs. */ | |
bfd0ee98 | 4135 | emit_reload_insns (chain); |
08a9dd06 | 4136 | |
4137 | /* Substitute the chosen reload regs from reload_reg_rtx | |
4138 | into the insn's body (or perhaps into the bodies of other | |
4139 | load and store insn that we just made for reloading | |
4140 | and that we moved the structure into). */ | |
d3ff0f75 | 4141 | subst_reloads (insn); |
bb552490 | 4142 | |
43283c91 | 4143 | /* Adjust the exception region notes for loads and stores. */ |
f0fbc1cd | 4144 | if (flag_non_call_exceptions && !CALL_P (insn)) |
43283c91 | 4145 | fixup_eh_region_note (insn, prev, next); |
4146 | ||
bb552490 | 4147 | /* If this was an ASM, make sure that all the reload insns |
4148 | we have generated are valid. If not, give an error | |
4149 | and delete them. */ | |
bb552490 | 4150 | if (asm_noperands (PATTERN (insn)) >= 0) |
4151 | for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) | |
9204e736 | 4152 | if (p != insn && INSN_P (p) |
4d9dcced | 4153 | && GET_CODE (PATTERN (p)) != USE |
bb552490 | 4154 | && (recog_memoized (p) < 0 |
7f82be90 | 4155 | || (extract_insn (p), ! constrain_operands (1)))) |
bb552490 | 4156 | { |
4157 | error_for_asm (insn, | |
eb586f2c | 4158 | "%<asm%> operand requires " |
4159 | "impossible reload"); | |
b36d64df | 4160 | delete_insn (p); |
bb552490 | 4161 | } |
08a9dd06 | 4162 | } |
226e9ef3 | 4163 | |
4164 | if (num_eliminable && chain->need_elim) | |
4165 | update_eliminable_offsets (); | |
4166 | ||
08a9dd06 | 4167 | /* Any previously reloaded spilled pseudo reg, stored in this insn, |
4168 | is no longer validly lying around to save a future reload. | |
4169 | Note that this does not detect pseudos that were reloaded | |
4170 | for this insn in order to be stored in | |
4171 | (obeying register constraints). That is correct; such reload | |
4172 | registers ARE still valid. */ | |
94aa2a3c | 4173 | forget_marked_reloads (®s_to_forget); |
4174 | CLEAR_REG_SET (®s_to_forget); | |
08a9dd06 | 4175 | |
4176 | /* There may have been CLOBBER insns placed after INSN. So scan | |
4177 | between INSN and NEXT and use them to forget old reloads. */ | |
590ec786 | 4178 | for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) |
6d7dc5b9 | 4179 | if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER) |
ec8895d7 | 4180 | note_stores (PATTERN (x), forget_old_reloads_1, NULL); |
08a9dd06 | 4181 | |
4182 | #ifdef AUTO_INC_DEC | |
93c7b06e | 4183 | /* Likewise for regs altered by auto-increment in this insn. |
4184 | REG_INC notes have been changed by reloading: | |
4185 | find_reloads_address_1 records substitutions for them, | |
4186 | which have been performed by subst_reloads above. */ | |
4187 | for (i = n_reloads - 1; i >= 0; i--) | |
4188 | { | |
48666d2c | 4189 | rtx in_reg = rld[i].in_reg; |
93c7b06e | 4190 | if (in_reg) |
4191 | { | |
4192 | enum rtx_code code = GET_CODE (in_reg); | |
4193 | /* PRE_INC / PRE_DEC will have the reload register ending up | |
4194 | with the same value as the stack slot, but that doesn't | |
4195 | hold true for POST_INC / POST_DEC. Either we have to | |
4196 | convert the memory access to a true POST_INC / POST_DEC, | |
4197 | or we can't use the reload register for inheritance. */ | |
4198 | if ((code == POST_INC || code == POST_DEC) | |
4199 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
48666d2c | 4200 | REGNO (rld[i].reg_rtx)) |
c13446db | 4201 | /* Make sure it is the inc/dec pseudo, and not |
4202 | some other (e.g. output operand) pseudo. */ | |
3473aefe | 4203 | && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
c13446db | 4204 | == REGNO (XEXP (in_reg, 0)))) |
5bb2f919 | 4205 | |
93c7b06e | 4206 | { |
48666d2c | 4207 | rtx reload_reg = rld[i].reg_rtx; |
93c7b06e | 4208 | enum machine_mode mode = GET_MODE (reload_reg); |
4209 | int n = 0; | |
4210 | rtx p; | |
4211 | ||
4212 | for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) | |
4213 | { | |
4214 | /* We really want to ignore REG_INC notes here, so | |
4215 | use PATTERN (p) as argument to reg_set_p . */ | |
4216 | if (reg_set_p (reload_reg, PATTERN (p))) | |
4217 | break; | |
40988080 | 4218 | n = count_occurrences (PATTERN (p), reload_reg, 0); |
93c7b06e | 4219 | if (! n) |
4220 | continue; | |
4221 | if (n == 1) | |
420d3340 | 4222 | { |
4223 | n = validate_replace_rtx (reload_reg, | |
27a9551b | 4224 | gen_rtx_fmt_e (code, |
4225 | mode, | |
4226 | reload_reg), | |
420d3340 | 4227 | p); |
4228 | ||
4229 | /* We must also verify that the constraints | |
4230 | are met after the replacement. */ | |
4231 | extract_insn (p); | |
4232 | if (n) | |
4233 | n = constrain_operands (1); | |
4234 | else | |
4235 | break; | |
4236 | ||
4237 | /* If the constraints were not met, then | |
4238 | undo the replacement. */ | |
4239 | if (!n) | |
4240 | { | |
27a9551b | 4241 | validate_replace_rtx (gen_rtx_fmt_e (code, |
4242 | mode, | |
4243 | reload_reg), | |
420d3340 | 4244 | reload_reg, p); |
4245 | break; | |
4246 | } | |
5bb2f919 | 4247 | |
420d3340 | 4248 | } |
93c7b06e | 4249 | break; |
4250 | } | |
4251 | if (n == 1) | |
4059e6ae | 4252 | { |
4253 | REG_NOTES (p) | |
4254 | = gen_rtx_EXPR_LIST (REG_INC, reload_reg, | |
4255 | REG_NOTES (p)); | |
4256 | /* Mark this as having an output reload so that the | |
4257 | REG_INC processing code below won't invalidate | |
4258 | the reload for inheritance. */ | |
4259 | SET_HARD_REG_BIT (reg_is_output_reload, | |
4260 | REGNO (reload_reg)); | |
7d742877 | 4261 | SET_REGNO_REG_SET (®_has_output_reload, |
4262 | REGNO (XEXP (in_reg, 0))); | |
4059e6ae | 4263 | } |
93c7b06e | 4264 | else |
aedd3e94 | 4265 | forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, |
ec8895d7 | 4266 | NULL); |
93c7b06e | 4267 | } |
4059e6ae | 4268 | else if ((code == PRE_INC || code == PRE_DEC) |
4269 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
48666d2c | 4270 | REGNO (rld[i].reg_rtx)) |
4059e6ae | 4271 | /* Make sure it is the inc/dec pseudo, and not |
4272 | some other (e.g. output operand) pseudo. */ | |
3473aefe | 4273 | && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
4059e6ae | 4274 | == REGNO (XEXP (in_reg, 0)))) |
4275 | { | |
4276 | SET_HARD_REG_BIT (reg_is_output_reload, | |
48666d2c | 4277 | REGNO (rld[i].reg_rtx)); |
7d742877 | 4278 | SET_REGNO_REG_SET (®_has_output_reload, |
4279 | REGNO (XEXP (in_reg, 0))); | |
4059e6ae | 4280 | } |
93c7b06e | 4281 | } |
4282 | } | |
4059e6ae | 4283 | /* If a pseudo that got a hard register is auto-incremented, |
4284 | we must purge records of copying it into pseudos without | |
4285 | hard registers. */ | |
08a9dd06 | 4286 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) |
4287 | if (REG_NOTE_KIND (x) == REG_INC) | |
4288 | { | |
4289 | /* See if this pseudo reg was reloaded in this insn. | |
4290 | If so, its last-reload info is still valid | |
4291 | because it is based on this insn's reload. */ | |
4292 | for (i = 0; i < n_reloads; i++) | |
48666d2c | 4293 | if (rld[i].out == XEXP (x, 0)) |
08a9dd06 | 4294 | break; |
4295 | ||
ff25496d | 4296 | if (i == n_reloads) |
ec8895d7 | 4297 | forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); |
08a9dd06 | 4298 | } |
4299 | #endif | |
4300 | } | |
4301 | /* A reload reg's contents are unknown after a label. */ | |
6d7dc5b9 | 4302 | if (LABEL_P (insn)) |
a5e95c30 | 4303 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
08a9dd06 | 4304 | |
4305 | /* Don't assume a reload reg is still good after a call insn | |
e467c16e | 4306 | if it is a call-used reg, or if it contains a value that will |
4307 | be partially clobbered by the call. */ | |
6d7dc5b9 | 4308 | else if (CALL_P (insn)) |
e467c16e | 4309 | { |
337d789b | 4310 | AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set); |
e467c16e | 4311 | AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered); |
4312 | } | |
08a9dd06 | 4313 | } |
bfcb79b1 | 4314 | |
4315 | /* Clean up. */ | |
4316 | free (reg_last_reload_reg); | |
7d742877 | 4317 | CLEAR_REG_SET (®_has_output_reload); |
08a9dd06 | 4318 | } |
4319 | ||
4320 | /* Discard all record of any value reloaded from X, | |
4321 | or reloaded in X from someplace else; | |
4322 | unless X is an output reload reg of the current insn. | |
4323 | ||
4324 | X may be a hard reg (the reload reg) | |
94aa2a3c | 4325 | or it may be a pseudo reg that was reloaded from. |
4326 | ||
4327 | When DATA is non-NULL just mark the registers in regset | |
4328 | to be forgotten later. */ | |
08a9dd06 | 4329 | |
4330 | static void | |
3ad4992f | 4331 | forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED, |
94aa2a3c | 4332 | void *data) |
08a9dd06 | 4333 | { |
02e7a332 | 4334 | unsigned int regno; |
4335 | unsigned int nr; | |
94aa2a3c | 4336 | regset regs = (regset) data; |
9cc47c53 | 4337 | |
701e46d0 | 4338 | /* note_stores does give us subregs of hard regs, |
1fa3a8f6 | 4339 | subreg_regno_offset requires a hard reg. */ |
9cc47c53 | 4340 | while (GET_CODE (x) == SUBREG) |
4341 | { | |
bb018d90 | 4342 | /* We ignore the subreg offset when calculating the regno, |
4343 | because we are using the entire underlying hard register | |
4344 | below. */ | |
9cc47c53 | 4345 | x = SUBREG_REG (x); |
4346 | } | |
08a9dd06 | 4347 | |
8ad4c111 | 4348 | if (!REG_P (x)) |
08a9dd06 | 4349 | return; |
4350 | ||
bb018d90 | 4351 | regno = REGNO (x); |
08a9dd06 | 4352 | |
4353 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4354 | nr = 1; | |
4355 | else | |
4356 | { | |
02e7a332 | 4357 | unsigned int i; |
4358 | ||
67d6c12b | 4359 | nr = hard_regno_nregs[regno][GET_MODE (x)]; |
08a9dd06 | 4360 | /* Storing into a spilled-reg invalidates its contents. |
4361 | This can happen if a block-local pseudo is allocated to that reg | |
4362 | and it wasn't spilled because this block's total need is 0. | |
4363 | Then some insn might have an optional reload and use this reg. */ | |
94aa2a3c | 4364 | if (!regs) |
4365 | for (i = 0; i < nr; i++) | |
4366 | /* But don't do this if the reg actually serves as an output | |
4367 | reload reg in the current instruction. */ | |
4368 | if (n_reloads == 0 | |
4369 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) | |
4370 | { | |
4371 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); | |
4372 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i); | |
4373 | spill_reg_store[regno + i] = 0; | |
4374 | } | |
08a9dd06 | 4375 | } |
4376 | ||
94aa2a3c | 4377 | if (regs) |
4378 | while (nr-- > 0) | |
4379 | SET_REGNO_REG_SET (regs, regno + nr); | |
4380 | else | |
4381 | { | |
4382 | /* Since value of X has changed, | |
4383 | forget any value previously copied from it. */ | |
4384 | ||
4385 | while (nr-- > 0) | |
4386 | /* But don't forget a copy if this is the output reload | |
4387 | that establishes the copy's validity. */ | |
7d742877 | 4388 | if (n_reloads == 0 |
4389 | || !REGNO_REG_SET_P (®_has_output_reload, regno + nr)) | |
94aa2a3c | 4390 | reg_last_reload_reg[regno + nr] = 0; |
4391 | } | |
4392 | } | |
08a9dd06 | 4393 | |
94aa2a3c | 4394 | /* Forget the reloads marked in regset by previous function. */ |
4395 | static void | |
4396 | forget_marked_reloads (regset regs) | |
4397 | { | |
4398 | unsigned int reg; | |
4399 | reg_set_iterator rsi; | |
4400 | EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi) | |
4401 | { | |
4402 | if (reg < FIRST_PSEUDO_REGISTER | |
4403 | /* But don't do this if the reg actually serves as an output | |
4404 | reload reg in the current instruction. */ | |
4405 | && (n_reloads == 0 | |
4406 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg))) | |
4407 | { | |
4408 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg); | |
4409 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg); | |
4410 | spill_reg_store[reg] = 0; | |
4411 | } | |
7d742877 | 4412 | if (n_reloads == 0 |
4413 | || !REGNO_REG_SET_P (®_has_output_reload, reg)) | |
94aa2a3c | 4414 | reg_last_reload_reg[reg] = 0; |
4415 | } | |
08a9dd06 | 4416 | } |
4417 | \f | |
08a9dd06 | 4418 | /* The following HARD_REG_SETs indicate when each hard register is |
4419 | used for a reload of various parts of the current insn. */ | |
4420 | ||
cab048af | 4421 | /* If reg is unavailable for all reloads. */ |
4422 | static HARD_REG_SET reload_reg_unavailable; | |
08a9dd06 | 4423 | /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ |
4424 | static HARD_REG_SET reload_reg_used; | |
81d0fbb3 | 4425 | /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ |
4426 | static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; | |
9e53d777 | 4427 | /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ |
4428 | static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; | |
81d0fbb3 | 4429 | /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ |
4430 | static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; | |
9e53d777 | 4431 | /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ |
4432 | static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; | |
81d0fbb3 | 4433 | /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ |
4434 | static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; | |
4435 | /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ | |
4436 | static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; | |
08a9dd06 | 4437 | /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ |
4438 | static HARD_REG_SET reload_reg_used_in_op_addr; | |
58866c2c | 4439 | /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ |
4440 | static HARD_REG_SET reload_reg_used_in_op_addr_reload; | |
81d0fbb3 | 4441 | /* If reg is in use for a RELOAD_FOR_INSN reload. */ |
4442 | static HARD_REG_SET reload_reg_used_in_insn; | |
4443 | /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ | |
4444 | static HARD_REG_SET reload_reg_used_in_other_addr; | |
08a9dd06 | 4445 | |
4446 | /* If reg is in use as a reload reg for any sort of reload. */ | |
4447 | static HARD_REG_SET reload_reg_used_at_all; | |
4448 | ||
7ac01373 | 4449 | /* If reg is use as an inherited reload. We just mark the first register |
4450 | in the group. */ | |
4451 | static HARD_REG_SET reload_reg_used_for_inherit; | |
4452 | ||
9e519b97 | 4453 | /* Records which hard regs are used in any way, either as explicit use or |
4454 | by being allocated to a pseudo during any point of the current insn. */ | |
4455 | static HARD_REG_SET reg_used_in_insn; | |
88ce984a | 4456 | |
81d0fbb3 | 4457 | /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and |
4458 | TYPE. MODE is used to indicate how many consecutive regs are | |
4459 | actually used. */ | |
08a9dd06 | 4460 | |
4461 | static void | |
3ad4992f | 4462 | mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type, |
4463 | enum machine_mode mode) | |
08a9dd06 | 4464 | { |
67d6c12b | 4465 | unsigned int nregs = hard_regno_nregs[regno][mode]; |
02e7a332 | 4466 | unsigned int i; |
08a9dd06 | 4467 | |
4468 | for (i = regno; i < nregs + regno; i++) | |
4469 | { | |
81d0fbb3 | 4470 | switch (type) |
08a9dd06 | 4471 | { |
4472 | case RELOAD_OTHER: | |
4473 | SET_HARD_REG_BIT (reload_reg_used, i); | |
4474 | break; | |
4475 | ||
81d0fbb3 | 4476 | case RELOAD_FOR_INPUT_ADDRESS: |
4477 | SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); | |
08a9dd06 | 4478 | break; |
4479 | ||
9e53d777 | 4480 | case RELOAD_FOR_INPADDR_ADDRESS: |
4481 | SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); | |
4482 | break; | |
4483 | ||
81d0fbb3 | 4484 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4485 | SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); | |
08a9dd06 | 4486 | break; |
4487 | ||
9e53d777 | 4488 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4489 | SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); | |
4490 | break; | |
4491 | ||
08a9dd06 | 4492 | case RELOAD_FOR_OPERAND_ADDRESS: |
4493 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
4494 | break; | |
4495 | ||
58866c2c | 4496 | case RELOAD_FOR_OPADDR_ADDR: |
4497 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); | |
4498 | break; | |
4499 | ||
81d0fbb3 | 4500 | case RELOAD_FOR_OTHER_ADDRESS: |
4501 | SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); | |
4502 | break; | |
4503 | ||
08a9dd06 | 4504 | case RELOAD_FOR_INPUT: |
81d0fbb3 | 4505 | SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); |
08a9dd06 | 4506 | break; |
4507 | ||
4508 | case RELOAD_FOR_OUTPUT: | |
81d0fbb3 | 4509 | SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); |
4510 | break; | |
4511 | ||
4512 | case RELOAD_FOR_INSN: | |
4513 | SET_HARD_REG_BIT (reload_reg_used_in_insn, i); | |
08a9dd06 | 4514 | break; |
4515 | } | |
4516 | ||
4517 | SET_HARD_REG_BIT (reload_reg_used_at_all, i); | |
4518 | } | |
4519 | } | |
4520 | ||
7ac01373 | 4521 | /* Similarly, but show REGNO is no longer in use for a reload. */ |
4522 | ||
4523 | static void | |
3ad4992f | 4524 | clear_reload_reg_in_use (unsigned int regno, int opnum, |
4525 | enum reload_type type, enum machine_mode mode) | |
7ac01373 | 4526 | { |
67d6c12b | 4527 | unsigned int nregs = hard_regno_nregs[regno][mode]; |
02e7a332 | 4528 | unsigned int start_regno, end_regno, r; |
7ac01373 | 4529 | int i; |
93c7b06e | 4530 | /* A complication is that for some reload types, inheritance might |
4531 | allow multiple reloads of the same types to share a reload register. | |
4532 | We set check_opnum if we have to check only reloads with the same | |
4533 | operand number, and check_any if we have to check all reloads. */ | |
4534 | int check_opnum = 0; | |
4535 | int check_any = 0; | |
4536 | HARD_REG_SET *used_in_set; | |
7ac01373 | 4537 | |
93c7b06e | 4538 | switch (type) |
7ac01373 | 4539 | { |
93c7b06e | 4540 | case RELOAD_OTHER: |
4541 | used_in_set = &reload_reg_used; | |
4542 | break; | |
7ac01373 | 4543 | |
93c7b06e | 4544 | case RELOAD_FOR_INPUT_ADDRESS: |
4545 | used_in_set = &reload_reg_used_in_input_addr[opnum]; | |
4546 | break; | |
7ac01373 | 4547 | |
93c7b06e | 4548 | case RELOAD_FOR_INPADDR_ADDRESS: |
4549 | check_opnum = 1; | |
4550 | used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; | |
4551 | break; | |
9e53d777 | 4552 | |
93c7b06e | 4553 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4554 | used_in_set = &reload_reg_used_in_output_addr[opnum]; | |
4555 | break; | |
7ac01373 | 4556 | |
93c7b06e | 4557 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4558 | check_opnum = 1; | |
4559 | used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; | |
4560 | break; | |
9e53d777 | 4561 | |
93c7b06e | 4562 | case RELOAD_FOR_OPERAND_ADDRESS: |
4563 | used_in_set = &reload_reg_used_in_op_addr; | |
4564 | break; | |
7ac01373 | 4565 | |
93c7b06e | 4566 | case RELOAD_FOR_OPADDR_ADDR: |
4567 | check_any = 1; | |
4568 | used_in_set = &reload_reg_used_in_op_addr_reload; | |
4569 | break; | |
58866c2c | 4570 | |
93c7b06e | 4571 | case RELOAD_FOR_OTHER_ADDRESS: |
4572 | used_in_set = &reload_reg_used_in_other_addr; | |
4573 | check_any = 1; | |
4574 | break; | |
7ac01373 | 4575 | |
93c7b06e | 4576 | case RELOAD_FOR_INPUT: |
4577 | used_in_set = &reload_reg_used_in_input[opnum]; | |
4578 | break; | |
7ac01373 | 4579 | |
93c7b06e | 4580 | case RELOAD_FOR_OUTPUT: |
4581 | used_in_set = &reload_reg_used_in_output[opnum]; | |
4582 | break; | |
7ac01373 | 4583 | |
93c7b06e | 4584 | case RELOAD_FOR_INSN: |
4585 | used_in_set = &reload_reg_used_in_insn; | |
4586 | break; | |
4587 | default: | |
04e579b6 | 4588 | gcc_unreachable (); |
93c7b06e | 4589 | } |
4590 | /* We resolve conflicts with remaining reloads of the same type by | |
95cc2547 | 4591 | excluding the intervals of reload registers by them from the |
93c7b06e | 4592 | interval of freed reload registers. Since we only keep track of |
4593 | one set of interval bounds, we might have to exclude somewhat | |
78eda270 | 4594 | more than what would be necessary if we used a HARD_REG_SET here. |
93c7b06e | 4595 | But this should only happen very infrequently, so there should |
4596 | be no reason to worry about it. */ | |
5bb2f919 | 4597 | |
93c7b06e | 4598 | start_regno = regno; |
4599 | end_regno = regno + nregs; | |
4600 | if (check_opnum || check_any) | |
4601 | { | |
4602 | for (i = n_reloads - 1; i >= 0; i--) | |
4603 | { | |
48666d2c | 4604 | if (rld[i].when_needed == type |
4605 | && (check_any || rld[i].opnum == opnum) | |
4606 | && rld[i].reg_rtx) | |
93c7b06e | 4607 | { |
02e7a332 | 4608 | unsigned int conflict_start = true_regnum (rld[i].reg_rtx); |
4609 | unsigned int conflict_end | |
a2c6f0b7 | 4610 | = end_hard_regno (rld[i].mode, conflict_start); |
93c7b06e | 4611 | |
4612 | /* If there is an overlap with the first to-be-freed register, | |
4613 | adjust the interval start. */ | |
4614 | if (conflict_start <= start_regno && conflict_end > start_regno) | |
4615 | start_regno = conflict_end; | |
4616 | /* Otherwise, if there is a conflict with one of the other | |
4617 | to-be-freed registers, adjust the interval end. */ | |
4618 | if (conflict_start > start_regno && conflict_start < end_regno) | |
4619 | end_regno = conflict_start; | |
4620 | } | |
7ac01373 | 4621 | } |
4622 | } | |
02e7a332 | 4623 | |
4624 | for (r = start_regno; r < end_regno; r++) | |
4625 | CLEAR_HARD_REG_BIT (*used_in_set, r); | |
7ac01373 | 4626 | } |
4627 | ||
08a9dd06 | 4628 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort |
81d0fbb3 | 4629 | specified by OPNUM and TYPE. */ |
08a9dd06 | 4630 | |
4631 | static int | |
3ad4992f | 4632 | reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type) |
08a9dd06 | 4633 | { |
81d0fbb3 | 4634 | int i; |
4635 | ||
8fa27ffb | 4636 | /* In use for a RELOAD_OTHER means it's not available for anything. */ |
cab048af | 4637 | if (TEST_HARD_REG_BIT (reload_reg_used, regno) |
4638 | || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) | |
08a9dd06 | 4639 | return 0; |
81d0fbb3 | 4640 | |
4641 | switch (type) | |
08a9dd06 | 4642 | { |
4643 | case RELOAD_OTHER: | |
8fa27ffb | 4644 | /* In use for anything means we can't use it for RELOAD_OTHER. */ |
4645 | if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) | |
563fb44c | 4646 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
5482e0c7 | 4647 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) |
563fb44c | 4648 | || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) |
4649 | return 0; | |
4650 | ||
4651 | for (i = 0; i < reload_n_operands; i++) | |
4652 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
9e53d777 | 4653 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
563fb44c | 4654 | || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
9e53d777 | 4655 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
563fb44c | 4656 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) |
4657 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4658 | return 0; | |
4659 | ||
4660 | return 1; | |
08a9dd06 | 4661 | |
08a9dd06 | 4662 | case RELOAD_FOR_INPUT: |
81d0fbb3 | 4663 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4664 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
4665 | return 0; | |
4666 | ||
58866c2c | 4667 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4668 | return 0; | |
4669 | ||
81d0fbb3 | 4670 | /* If it is used for some other input, can't use it. */ |
4671 | for (i = 0; i < reload_n_operands; i++) | |
4672 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4673 | return 0; | |
4674 | ||
4675 | /* If it is used in a later operand's address, can't use it. */ | |
4676 | for (i = opnum + 1; i < reload_n_operands; i++) | |
9e53d777 | 4677 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4678 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
81d0fbb3 | 4679 | return 0; |
4680 | ||
4681 | return 1; | |
4682 | ||
4683 | case RELOAD_FOR_INPUT_ADDRESS: | |
4684 | /* Can't use a register if it is used for an input address for this | |
4685 | operand or used as an input in an earlier one. */ | |
9e53d777 | 4686 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) |
4687 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) | |
4688 | return 0; | |
4689 | ||
4690 | for (i = 0; i < opnum; i++) | |
4691 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4692 | return 0; | |
4693 | ||
4694 | return 1; | |
4695 | ||
4696 | case RELOAD_FOR_INPADDR_ADDRESS: | |
4697 | /* Can't use a register if it is used for an input address | |
5bb2f919 | 4698 | for this operand or used as an input in an earlier |
4699 | one. */ | |
9e53d777 | 4700 | if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) |
81d0fbb3 | 4701 | return 0; |
4702 | ||
4703 | for (i = 0; i < opnum; i++) | |
4704 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4705 | return 0; | |
4706 | ||
4707 | return 1; | |
4708 | ||
4709 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
4710 | /* Can't use a register if it is used for an output address for this | |
3bd67e9c | 4711 | operand or used as an output in this or a later operand. Note |
4712 | that multiple output operands are emitted in reverse order, so | |
4713 | the conflicting ones are those with lower indices. */ | |
81d0fbb3 | 4714 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) |
4715 | return 0; | |
4716 | ||
3bd67e9c | 4717 | for (i = 0; i <= opnum; i++) |
81d0fbb3 | 4718 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4719 | return 0; | |
4720 | ||
4721 | return 1; | |
4722 | ||
9e53d777 | 4723 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4724 | /* Can't use a register if it is used for an output address | |
5bb2f919 | 4725 | for this operand or used as an output in this or a |
3bd67e9c | 4726 | later operand. Note that multiple output operands are |
4727 | emitted in reverse order, so the conflicting ones are | |
4728 | those with lower indices. */ | |
9e53d777 | 4729 | if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) |
4730 | return 0; | |
4731 | ||
3bd67e9c | 4732 | for (i = 0; i <= opnum; i++) |
9e53d777 | 4733 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4734 | return 0; | |
4735 | ||
4736 | return 1; | |
4737 | ||
08a9dd06 | 4738 | case RELOAD_FOR_OPERAND_ADDRESS: |
81d0fbb3 | 4739 | for (i = 0; i < reload_n_operands; i++) |
4740 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4741 | return 0; | |
4742 | ||
4743 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4744 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4745 | ||
58866c2c | 4746 | case RELOAD_FOR_OPADDR_ADDR: |
4747 | for (i = 0; i < reload_n_operands; i++) | |
5bb2f919 | 4748 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4749 | return 0; | |
58866c2c | 4750 | |
4429ee8b | 4751 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); |
58866c2c | 4752 | |
08a9dd06 | 4753 | case RELOAD_FOR_OUTPUT: |
81d0fbb3 | 4754 | /* This cannot share a register with RELOAD_FOR_INSN reloads, other |
3bd67e9c | 4755 | outputs, or an operand address for this or an earlier output. |
4756 | Note that multiple output operands are emitted in reverse order, | |
4757 | so the conflicting ones are those with higher indices. */ | |
81d0fbb3 | 4758 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) |
4759 | return 0; | |
4760 | ||
4761 | for (i = 0; i < reload_n_operands; i++) | |
4762 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4763 | return 0; | |
4764 | ||
3bd67e9c | 4765 | for (i = opnum; i < reload_n_operands; i++) |
9e53d777 | 4766 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4767 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
81d0fbb3 | 4768 | return 0; |
4769 | ||
4770 | return 1; | |
4771 | ||
4772 | case RELOAD_FOR_INSN: | |
4773 | for (i = 0; i < reload_n_operands; i++) | |
4774 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) | |
4775 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4776 | return 0; | |
4777 | ||
4778 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4779 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4780 | ||
4781 | case RELOAD_FOR_OTHER_ADDRESS: | |
4782 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
04e579b6 | 4783 | |
4784 | default: | |
4785 | gcc_unreachable (); | |
08a9dd06 | 4786 | } |
08a9dd06 | 4787 | } |
4788 | ||
08a9dd06 | 4789 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
81d0fbb3 | 4790 | needed for the part of the insn specified by OPNUM and TYPE, |
08a9dd06 | 4791 | is still available in REGNO at the end of the insn. |
4792 | ||
4793 | We can assume that the reload reg was already tested for availability | |
4794 | at the time it is needed, and we should not check this again, | |
4795 | in case the reg has already been marked in use. */ | |
4796 | ||
4797 | static int | |
3ad4992f | 4798 | reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type) |
08a9dd06 | 4799 | { |
81d0fbb3 | 4800 | int i; |
4801 | ||
4802 | switch (type) | |
08a9dd06 | 4803 | { |
4804 | case RELOAD_OTHER: | |
4805 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
4806 | its value must reach the end. */ | |
4807 | return 1; | |
4808 | ||
4809 | /* If this use is for part of the insn, | |
5bb2f919 | 4810 | its value reaches if no subsequent part uses the same register. |
81d0fbb3 | 4811 | Just like the above function, don't try to do this with lots |
4812 | of fallthroughs. */ | |
4813 | ||
4814 | case RELOAD_FOR_OTHER_ADDRESS: | |
4815 | /* Here we check for everything else, since these don't conflict | |
4816 | with anything else and everything comes later. */ | |
4817 | ||
4818 | for (i = 0; i < reload_n_operands; i++) | |
4819 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
9e53d777 | 4820 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
81d0fbb3 | 4821 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) |
4822 | || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
9e53d777 | 4823 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
81d0fbb3 | 4824 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4825 | return 0; | |
4826 | ||
4827 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
5482e0c7 | 4828 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) |
81d0fbb3 | 4829 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4830 | && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
4831 | ||
4832 | case RELOAD_FOR_INPUT_ADDRESS: | |
9e53d777 | 4833 | case RELOAD_FOR_INPADDR_ADDRESS: |
81d0fbb3 | 4834 | /* Similar, except that we check only for this and subsequent inputs |
4835 | and the address of only subsequent inputs and we do not need | |
4836 | to check for RELOAD_OTHER objects since they are known not to | |
4837 | conflict. */ | |
4838 | ||
4839 | for (i = opnum; i < reload_n_operands; i++) | |
4840 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4841 | return 0; | |
4842 | ||
4843 | for (i = opnum + 1; i < reload_n_operands; i++) | |
9e53d777 | 4844 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4845 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
81d0fbb3 | 4846 | return 0; |
4847 | ||
4848 | for (i = 0; i < reload_n_operands; i++) | |
4849 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
9e53d777 | 4850 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
81d0fbb3 | 4851 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4852 | return 0; | |
4853 | ||
58866c2c | 4854 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4855 | return 0; | |
4856 | ||
4284e477 | 4857 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4858 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4859 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
81d0fbb3 | 4860 | |
08a9dd06 | 4861 | case RELOAD_FOR_INPUT: |
81d0fbb3 | 4862 | /* Similar to input address, except we start at the next operand for |
5bb2f919 | 4863 | both input and input address and we do not check for |
81d0fbb3 | 4864 | RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these |
4865 | would conflict. */ | |
4866 | ||
4867 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4868 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
9e53d777 | 4869 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
81d0fbb3 | 4870 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4871 | return 0; | |
4872 | ||
a92771b8 | 4873 | /* ... fall through ... */ |
81d0fbb3 | 4874 | |
08a9dd06 | 4875 | case RELOAD_FOR_OPERAND_ADDRESS: |
81d0fbb3 | 4876 | /* Check outputs and their addresses. */ |
4877 | ||
4878 | for (i = 0; i < reload_n_operands; i++) | |
4879 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
9e53d777 | 4880 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
81d0fbb3 | 4881 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4882 | return 0; | |
4883 | ||
4284e477 | 4884 | return (!TEST_HARD_REG_BIT (reload_reg_used, regno)); |
81d0fbb3 | 4885 | |
58866c2c | 4886 | case RELOAD_FOR_OPADDR_ADDR: |
4887 | for (i = 0; i < reload_n_operands; i++) | |
4888 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
9e53d777 | 4889 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
58866c2c | 4890 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4891 | return 0; | |
4892 | ||
4284e477 | 4893 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4894 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4895 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
58866c2c | 4896 | |
81d0fbb3 | 4897 | case RELOAD_FOR_INSN: |
58866c2c | 4898 | /* These conflict with other outputs with RELOAD_OTHER. So |
81d0fbb3 | 4899 | we need only check for output addresses. */ |
4900 | ||
3bd67e9c | 4901 | opnum = reload_n_operands; |
81d0fbb3 | 4902 | |
a92771b8 | 4903 | /* ... fall through ... */ |
81d0fbb3 | 4904 | |
08a9dd06 | 4905 | case RELOAD_FOR_OUTPUT: |
81d0fbb3 | 4906 | case RELOAD_FOR_OUTPUT_ADDRESS: |
9e53d777 | 4907 | case RELOAD_FOR_OUTADDR_ADDRESS: |
81d0fbb3 | 4908 | /* We already know these can't conflict with a later output. So the |
3bd67e9c | 4909 | only thing to check are later output addresses. |
4910 | Note that multiple output operands are emitted in reverse order, | |
4911 | so the conflicting ones are those with lower indices. */ | |
4912 | for (i = 0; i < opnum; i++) | |
9e53d777 | 4913 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4914 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
81d0fbb3 | 4915 | return 0; |
4916 | ||
08a9dd06 | 4917 | return 1; |
81d0fbb3 | 4918 | |
04e579b6 | 4919 | default: |
4920 | gcc_unreachable (); | |
4921 | } | |
08a9dd06 | 4922 | } |
4923 | \f | |
a7f41594 | 4924 | |
4925 | /* Returns whether R1 and R2 are uniquely chained: the value of one | |
4926 | is used by the other, and that value is not used by any other | |
4927 | reload for this insn. This is used to partially undo the decision | |
4928 | made in find_reloads when in the case of multiple | |
4929 | RELOAD_FOR_OPERAND_ADDRESS reloads it converts all | |
4930 | RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS | |
4931 | reloads. This code tries to avoid the conflict created by that | |
4932 | change. It might be cleaner to explicitly keep track of which | |
4933 | RELOAD_FOR_OPADDR_ADDR reload is associated with which | |
4934 | RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect | |
4935 | this after the fact. */ | |
4936 | static bool | |
4937 | reloads_unique_chain_p (int r1, int r2) | |
4938 | { | |
4939 | int i; | |
4940 | ||
4941 | /* We only check input reloads. */ | |
4942 | if (! rld[r1].in || ! rld[r2].in) | |
4943 | return false; | |
4944 | ||
4945 | /* Avoid anything with output reloads. */ | |
4946 | if (rld[r1].out || rld[r2].out) | |
4947 | return false; | |
4948 | ||
4949 | /* "chained" means one reload is a component of the other reload, | |
4950 | not the same as the other reload. */ | |
4951 | if (rld[r1].opnum != rld[r2].opnum | |
4952 | || rtx_equal_p (rld[r1].in, rld[r2].in) | |
4953 | || rld[r1].optional || rld[r2].optional | |
4954 | || ! (reg_mentioned_p (rld[r1].in, rld[r2].in) | |
4955 | || reg_mentioned_p (rld[r2].in, rld[r1].in))) | |
4956 | return false; | |
4957 | ||
4958 | for (i = 0; i < n_reloads; i ++) | |
4959 | /* Look for input reloads that aren't our two */ | |
4960 | if (i != r1 && i != r2 && rld[i].in) | |
4961 | { | |
4962 | /* If our reload is mentioned at all, it isn't a simple chain. */ | |
4963 | if (reg_mentioned_p (rld[r1].in, rld[i].in)) | |
4964 | return false; | |
4965 | } | |
4966 | return true; | |
4967 | } | |
4968 | ||
fff4060f | 4969 | /* Return 1 if the reloads denoted by R1 and R2 cannot share a register. |
4970 | Return 0 otherwise. | |
4971 | ||
4972 | This function uses the same algorithm as reload_reg_free_p above. */ | |
4973 | ||
3c01fc19 | 4974 | static int |
3ad4992f | 4975 | reloads_conflict (int r1, int r2) |
fff4060f | 4976 | { |
48666d2c | 4977 | enum reload_type r1_type = rld[r1].when_needed; |
4978 | enum reload_type r2_type = rld[r2].when_needed; | |
4979 | int r1_opnum = rld[r1].opnum; | |
4980 | int r2_opnum = rld[r2].opnum; | |
fff4060f | 4981 | |
8fa27ffb | 4982 | /* RELOAD_OTHER conflicts with everything. */ |
4983 | if (r2_type == RELOAD_OTHER) | |
fff4060f | 4984 | return 1; |
4985 | ||
4986 | /* Otherwise, check conflicts differently for each type. */ | |
4987 | ||
4988 | switch (r1_type) | |
4989 | { | |
4990 | case RELOAD_FOR_INPUT: | |
5bb2f919 | 4991 | return (r2_type == RELOAD_FOR_INSN |
fff4060f | 4992 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS |
58866c2c | 4993 | || r2_type == RELOAD_FOR_OPADDR_ADDR |
fff4060f | 4994 | || r2_type == RELOAD_FOR_INPUT |
9e53d777 | 4995 | || ((r2_type == RELOAD_FOR_INPUT_ADDRESS |
4996 | || r2_type == RELOAD_FOR_INPADDR_ADDRESS) | |
4997 | && r2_opnum > r1_opnum)); | |
fff4060f | 4998 | |
4999 | case RELOAD_FOR_INPUT_ADDRESS: | |
5000 | return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) | |
5001 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
5002 | ||
9e53d777 | 5003 | case RELOAD_FOR_INPADDR_ADDRESS: |
5004 | return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) | |
5005 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
5006 | ||
fff4060f | 5007 | case RELOAD_FOR_OUTPUT_ADDRESS: |
5008 | return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) | |
3bd67e9c | 5009 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
fff4060f | 5010 | |
9e53d777 | 5011 | case RELOAD_FOR_OUTADDR_ADDRESS: |
5012 | return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) | |
3bd67e9c | 5013 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
9e53d777 | 5014 | |
fff4060f | 5015 | case RELOAD_FOR_OPERAND_ADDRESS: |
5016 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN | |
a7f41594 | 5017 | || (r2_type == RELOAD_FOR_OPERAND_ADDRESS |
5018 | && !reloads_unique_chain_p (r1, r2))); | |
fff4060f | 5019 | |
58866c2c | 5020 | case RELOAD_FOR_OPADDR_ADDR: |
5bb2f919 | 5021 | return (r2_type == RELOAD_FOR_INPUT |
4429ee8b | 5022 | || r2_type == RELOAD_FOR_OPADDR_ADDR); |
58866c2c | 5023 | |
fff4060f | 5024 | case RELOAD_FOR_OUTPUT: |
5025 | return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT | |
9e53d777 | 5026 | || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS |
5027 | || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) | |
3bd67e9c | 5028 | && r2_opnum >= r1_opnum)); |
fff4060f | 5029 | |
5030 | case RELOAD_FOR_INSN: | |
5031 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT | |
5032 | || r2_type == RELOAD_FOR_INSN | |
5033 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); | |
5034 | ||
5035 | case RELOAD_FOR_OTHER_ADDRESS: | |
5036 | return r2_type == RELOAD_FOR_OTHER_ADDRESS; | |
5037 | ||
bd0217a9 | 5038 | case RELOAD_OTHER: |
8fa27ffb | 5039 | return 1; |
bd0217a9 | 5040 | |
fff4060f | 5041 | default: |
04e579b6 | 5042 | gcc_unreachable (); |
fff4060f | 5043 | } |
5044 | } | |
5045 | \f | |
08a9dd06 | 5046 | /* Indexed by reload number, 1 if incoming value |
5047 | inherited from previous insns. */ | |
56d727be | 5048 | static char reload_inherited[MAX_RELOADS]; |
08a9dd06 | 5049 | |
5050 | /* For an inherited reload, this is the insn the reload was inherited from, | |
5051 | if we know it. Otherwise, this is 0. */ | |
56d727be | 5052 | static rtx reload_inheritance_insn[MAX_RELOADS]; |
08a9dd06 | 5053 | |
7fd957fe | 5054 | /* If nonzero, this is a place to get the value of the reload, |
08a9dd06 | 5055 | rather than using reload_in. */ |
56d727be | 5056 | static rtx reload_override_in[MAX_RELOADS]; |
08a9dd06 | 5057 | |
a5e95c30 | 5058 | /* For each reload, the hard register number of the register used, |
5059 | or -1 if we did not need a register for this reload. */ | |
56d727be | 5060 | static int reload_spill_index[MAX_RELOADS]; |
08a9dd06 | 5061 | |
a971a41c | 5062 | /* Subroutine of free_for_value_p, used to check a single register. |
5063 | START_REGNO is the starting regno of the full reload register | |
5064 | (possibly comprising multiple hard registers) that we are considering. */ | |
2f013d29 | 5065 | |
88148277 | 5066 | static int |
3ad4992f | 5067 | reload_reg_free_for_value_p (int start_regno, int regno, int opnum, |
5068 | enum reload_type type, rtx value, rtx out, | |
5069 | int reloadnum, int ignore_address_reloads) | |
88148277 | 5070 | { |
5071 | int time1; | |
92c7a85c | 5072 | /* Set if we see an input reload that must not share its reload register |
5073 | with any new earlyclobber, but might otherwise share the reload | |
5074 | register with an output or input-output reload. */ | |
5075 | int check_earlyclobber = 0; | |
88148277 | 5076 | int i; |
c6bdbe11 | 5077 | int copy = 0; |
5078 | ||
cab048af | 5079 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) |
24b200cb | 5080 | return 0; |
5081 | ||
c6bdbe11 | 5082 | if (out == const0_rtx) |
5083 | { | |
5084 | copy = 1; | |
5085 | out = NULL_RTX; | |
5086 | } | |
88148277 | 5087 | |
5088 | /* We use some pseudo 'time' value to check if the lifetimes of the | |
5089 | new register use would overlap with the one of a previous reload | |
5090 | that is not read-only or uses a different value. | |
5091 | The 'time' used doesn't have to be linear in any shape or form, just | |
5092 | monotonic. | |
5093 | Some reload types use different 'buckets' for each operand. | |
5094 | So there are MAX_RECOG_OPERANDS different time values for each | |
cfaa75fa | 5095 | such reload type. |
5096 | We compute TIME1 as the time when the register for the prospective | |
5097 | new reload ceases to be live, and TIME2 for each existing | |
5098 | reload as the time when that the reload register of that reload | |
5099 | becomes live. | |
5100 | Where there is little to be gained by exact lifetime calculations, | |
5101 | we just make conservative assumptions, i.e. a longer lifetime; | |
5102 | this is done in the 'default:' cases. */ | |
88148277 | 5103 | switch (type) |
5104 | { | |
5105 | case RELOAD_FOR_OTHER_ADDRESS: | |
fa5a8144 | 5106 | /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ |
98d56795 | 5107 | time1 = copy ? 0 : 1; |
88148277 | 5108 | break; |
c6bdbe11 | 5109 | case RELOAD_OTHER: |
5110 | time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; | |
5111 | break; | |
5bb2f919 | 5112 | /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, |
5113 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , | |
5114 | respectively, to the time values for these, we get distinct time | |
5115 | values. To get distinct time values for each operand, we have to | |
5116 | multiply opnum by at least three. We round that up to four because | |
5117 | multiply by four is often cheaper. */ | |
88148277 | 5118 | case RELOAD_FOR_INPADDR_ADDRESS: |
c6bdbe11 | 5119 | time1 = opnum * 4 + 2; |
88148277 | 5120 | break; |
5121 | case RELOAD_FOR_INPUT_ADDRESS: | |
c6bdbe11 | 5122 | time1 = opnum * 4 + 3; |
5123 | break; | |
5124 | case RELOAD_FOR_INPUT: | |
5125 | /* All RELOAD_FOR_INPUT reloads remain live till the instruction | |
5126 | executes (inclusive). */ | |
5127 | time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; | |
88148277 | 5128 | break; |
93c7b06e | 5129 | case RELOAD_FOR_OPADDR_ADDR: |
5bb2f919 | 5130 | /* opnum * 4 + 4 |
5131 | <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ | |
93c7b06e | 5132 | time1 = MAX_RECOG_OPERANDS * 4 + 1; |
5133 | break; | |
5134 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5135 | /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn | |
5136 | is executed. */ | |
c6bdbe11 | 5137 | time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; |
5138 | break; | |
5139 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
5140 | time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; | |
88148277 | 5141 | break; |
88148277 | 5142 | case RELOAD_FOR_OUTPUT_ADDRESS: |
c6bdbe11 | 5143 | time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; |
88148277 | 5144 | break; |
5145 | default: | |
c6bdbe11 | 5146 | time1 = MAX_RECOG_OPERANDS * 5 + 5; |
88148277 | 5147 | } |
5148 | ||
5149 | for (i = 0; i < n_reloads; i++) | |
5150 | { | |
48666d2c | 5151 | rtx reg = rld[i].reg_rtx; |
8ad4c111 | 5152 | if (reg && REG_P (reg) |
88148277 | 5153 | && ((unsigned) regno - true_regnum (reg) |
67d6c12b | 5154 | <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1) |
2f013d29 | 5155 | && i != reloadnum) |
88148277 | 5156 | { |
a971a41c | 5157 | rtx other_input = rld[i].in; |
5158 | ||
5159 | /* If the other reload loads the same input value, that | |
5160 | will not cause a conflict only if it's loading it into | |
5161 | the same register. */ | |
5162 | if (true_regnum (reg) != start_regno) | |
5163 | other_input = NULL_RTX; | |
5164 | if (! other_input || ! rtx_equal_p (other_input, value) | |
48666d2c | 5165 | || rld[i].out || out) |
88148277 | 5166 | { |
92c7a85c | 5167 | int time2; |
48666d2c | 5168 | switch (rld[i].when_needed) |
2f013d29 | 5169 | { |
5170 | case RELOAD_FOR_OTHER_ADDRESS: | |
5171 | time2 = 0; | |
5172 | break; | |
5173 | case RELOAD_FOR_INPADDR_ADDRESS: | |
93c7b06e | 5174 | /* find_reloads makes sure that a |
5175 | RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used | |
5176 | by at most one - the first - | |
5177 | RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the | |
5178 | address reload is inherited, the address address reload | |
5179 | goes away, so we can ignore this conflict. */ | |
c6bdbe11 | 5180 | if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 |
5181 | && ignore_address_reloads | |
5182 | /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. | |
5183 | Then the address address is still needed to store | |
5184 | back the new address. */ | |
48666d2c | 5185 | && ! rld[reloadnum].out) |
93c7b06e | 5186 | continue; |
c6bdbe11 | 5187 | /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its |
5188 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS | |
5189 | reloads go away. */ | |
48666d2c | 5190 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
c6bdbe11 | 5191 | && ignore_address_reloads |
5192 | /* Unless we are reloading an auto_inc expression. */ | |
48666d2c | 5193 | && ! rld[reloadnum].out) |
c6bdbe11 | 5194 | continue; |
48666d2c | 5195 | time2 = rld[i].opnum * 4 + 2; |
2f013d29 | 5196 | break; |
5197 | case RELOAD_FOR_INPUT_ADDRESS: | |
48666d2c | 5198 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
c6bdbe11 | 5199 | && ignore_address_reloads |
48666d2c | 5200 | && ! rld[reloadnum].out) |
c6bdbe11 | 5201 | continue; |
48666d2c | 5202 | time2 = rld[i].opnum * 4 + 3; |
2f013d29 | 5203 | break; |
5204 | case RELOAD_FOR_INPUT: | |
48666d2c | 5205 | time2 = rld[i].opnum * 4 + 4; |
92c7a85c | 5206 | check_earlyclobber = 1; |
2f013d29 | 5207 | break; |
48666d2c | 5208 | /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 |
5bb2f919 | 5209 | == MAX_RECOG_OPERAND * 4 */ |
93c7b06e | 5210 | case RELOAD_FOR_OPADDR_ADDR: |
c6bdbe11 | 5211 | if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 |
5212 | && ignore_address_reloads | |
48666d2c | 5213 | && ! rld[reloadnum].out) |
93c7b06e | 5214 | continue; |
c6bdbe11 | 5215 | time2 = MAX_RECOG_OPERANDS * 4 + 1; |
93c7b06e | 5216 | break; |
5217 | case RELOAD_FOR_OPERAND_ADDRESS: | |
c6bdbe11 | 5218 | time2 = MAX_RECOG_OPERANDS * 4 + 2; |
92c7a85c | 5219 | check_earlyclobber = 1; |
c6bdbe11 | 5220 | break; |
5221 | case RELOAD_FOR_INSN: | |
5222 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
93c7b06e | 5223 | break; |
2f013d29 | 5224 | case RELOAD_FOR_OUTPUT: |
5bb2f919 | 5225 | /* All RELOAD_FOR_OUTPUT reloads become live just after the |
5226 | instruction is executed. */ | |
c6bdbe11 | 5227 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
2f013d29 | 5228 | break; |
5bb2f919 | 5229 | /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with |
5230 | the RELOAD_FOR_OUTPUT reloads, so assign it the same time | |
5231 | value. */ | |
93c7b06e | 5232 | case RELOAD_FOR_OUTADDR_ADDRESS: |
c6bdbe11 | 5233 | if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 |
5234 | && ignore_address_reloads | |
48666d2c | 5235 | && ! rld[reloadnum].out) |
93c7b06e | 5236 | continue; |
48666d2c | 5237 | time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; |
c6bdbe11 | 5238 | break; |
2f013d29 | 5239 | case RELOAD_FOR_OUTPUT_ADDRESS: |
48666d2c | 5240 | time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; |
2f013d29 | 5241 | break; |
5242 | case RELOAD_OTHER: | |
c6bdbe11 | 5243 | /* If there is no conflict in the input part, handle this |
5244 | like an output reload. */ | |
a971a41c | 5245 | if (! rld[i].in || rtx_equal_p (other_input, value)) |
2f013d29 | 5246 | { |
c6bdbe11 | 5247 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
4399a7a8 | 5248 | /* Earlyclobbered outputs must conflict with inputs. */ |
92c7a85c | 5249 | if (earlyclobber_operand_p (rld[i].out)) |
5250 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
aedd3e94 | 5251 | |
2f013d29 | 5252 | break; |
5253 | } | |
c6bdbe11 | 5254 | time2 = 1; |
5255 | /* RELOAD_OTHER might be live beyond instruction execution, | |
5256 | but this is not obvious when we set time2 = 1. So check | |
5257 | here if there might be a problem with the new reload | |
5258 | clobbering the register used by the RELOAD_OTHER. */ | |
5259 | if (out) | |
5260 | return 0; | |
5261 | break; | |
2f013d29 | 5262 | default: |
c6bdbe11 | 5263 | return 0; |
2f013d29 | 5264 | } |
daed075e | 5265 | if ((time1 >= time2 |
48666d2c | 5266 | && (! rld[i].in || rld[i].out |
a971a41c | 5267 | || ! rtx_equal_p (other_input, value))) |
48666d2c | 5268 | || (out && rld[reloadnum].out_reg |
23ccd46e | 5269 | && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) |
2f013d29 | 5270 | return 0; |
88148277 | 5271 | } |
88148277 | 5272 | } |
5273 | } | |
92c7a85c | 5274 | |
5275 | /* Earlyclobbered outputs must conflict with inputs. */ | |
5276 | if (check_earlyclobber && out && earlyclobber_operand_p (out)) | |
5277 | return 0; | |
5278 | ||
88148277 | 5279 | return 1; |
5280 | } | |
5281 | ||
34b8be6b | 5282 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
5283 | needed for the part of the insn specified by OPNUM and TYPE, | |
5284 | may be used to load VALUE into it. | |
5285 | ||
5286 | MODE is the mode in which the register is used, this is needed to | |
5287 | determine how many hard regs to test. | |
5288 | ||
5289 | Other read-only reloads with the same value do not conflict | |
7fd957fe | 5290 | unless OUT is nonzero and these other reloads have to live while |
34b8be6b | 5291 | output reloads live. |
5292 | If OUT is CONST0_RTX, this is a special case: it means that the | |
5293 | test should not be for using register REGNO as reload register, but | |
5294 | for copying from register REGNO into the reload register. | |
5295 | ||
5296 | RELOADNUM is the number of the reload we want to load this value for; | |
5297 | a reload does not conflict with itself. | |
5298 | ||
5299 | When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with | |
5300 | reloads that load an address for the very reload we are considering. | |
5301 | ||
5302 | The caller has to make sure that there is no conflict with the return | |
5303 | register. */ | |
5304 | ||
5305 | static int | |
3ad4992f | 5306 | free_for_value_p (int regno, enum machine_mode mode, int opnum, |
5307 | enum reload_type type, rtx value, rtx out, int reloadnum, | |
5308 | int ignore_address_reloads) | |
34b8be6b | 5309 | { |
67d6c12b | 5310 | int nregs = hard_regno_nregs[regno][mode]; |
34b8be6b | 5311 | while (nregs-- > 0) |
a971a41c | 5312 | if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type, |
5313 | value, out, reloadnum, | |
5314 | ignore_address_reloads)) | |
34b8be6b | 5315 | return 0; |
5316 | return 1; | |
5317 | } | |
5318 | ||
d5790af8 | 5319 | /* Return nonzero if the rtx X is invariant over the current function. */ |
1fa3a8f6 | 5320 | /* ??? Actually, the places where we use this expect exactly what is |
5321 | tested here, and not everything that is function invariant. In | |
5322 | particular, the frame pointer and arg pointer are special cased; | |
5323 | pic_offset_table_rtx is not, and we must not spill these things to | |
5324 | memory. */ | |
d5790af8 | 5325 | |
dfc4de0a | 5326 | int |
d5790af8 | 5327 | function_invariant_p (rtx x) |
5328 | { | |
5329 | if (CONSTANT_P (x)) | |
5330 | return 1; | |
5331 | if (x == frame_pointer_rtx || x == arg_pointer_rtx) | |
5332 | return 1; | |
5333 | if (GET_CODE (x) == PLUS | |
5334 | && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx) | |
5335 | && CONSTANT_P (XEXP (x, 1))) | |
5336 | return 1; | |
5337 | return 0; | |
5338 | } | |
5339 | ||
b5083cca | 5340 | /* Determine whether the reload reg X overlaps any rtx'es used for |
5341 | overriding inheritance. Return nonzero if so. */ | |
5342 | ||
5343 | static int | |
3ad4992f | 5344 | conflicts_with_override (rtx x) |
b5083cca | 5345 | { |
5346 | int i; | |
5347 | for (i = 0; i < n_reloads; i++) | |
5348 | if (reload_override_in[i] | |
5349 | && reg_overlap_mentioned_p (x, reload_override_in[i])) | |
5350 | return 1; | |
5351 | return 0; | |
5352 | } | |
5353 | \f | |
456b6b44 | 5354 | /* Give an error message saying we failed to find a reload for INSN, |
5355 | and clear out reload R. */ | |
5356 | static void | |
3ad4992f | 5357 | failed_reload (rtx insn, int r) |
456b6b44 | 5358 | { |
5359 | if (asm_noperands (PATTERN (insn)) < 0) | |
5360 | /* It's the compiler's fault. */ | |
cb8bacb6 | 5361 | fatal_insn ("could not find a spill register", insn); |
456b6b44 | 5362 | |
5363 | /* It's the user's fault; the operand's mode and constraint | |
5364 | don't match. Disable this reload so we don't crash in final. */ | |
5365 | error_for_asm (insn, | |
eb586f2c | 5366 | "%<asm%> operand constraint incompatible with operand size"); |
456b6b44 | 5367 | rld[r].in = 0; |
5368 | rld[r].out = 0; | |
5369 | rld[r].reg_rtx = 0; | |
5370 | rld[r].optional = 1; | |
5371 | rld[r].secondary_p = 1; | |
5372 | } | |
5373 | ||
5374 | /* I is the index in SPILL_REG_RTX of the reload register we are to allocate | |
5375 | for reload R. If it's valid, get an rtx for it. Return nonzero if | |
5376 | successful. */ | |
5377 | static int | |
3ad4992f | 5378 | set_reload_reg (int i, int r) |
456b6b44 | 5379 | { |
5380 | int regno; | |
5381 | rtx reg = spill_reg_rtx[i]; | |
5382 | ||
5383 | if (reg == 0 || GET_MODE (reg) != rld[r].mode) | |
5384 | spill_reg_rtx[i] = reg | |
5385 | = gen_rtx_REG (rld[r].mode, spill_regs[i]); | |
5386 | ||
5387 | regno = true_regnum (reg); | |
5388 | ||
5389 | /* Detect when the reload reg can't hold the reload mode. | |
5390 | This used to be one `if', but Sequent compiler can't handle that. */ | |
5391 | if (HARD_REGNO_MODE_OK (regno, rld[r].mode)) | |
5392 | { | |
5393 | enum machine_mode test_mode = VOIDmode; | |
5394 | if (rld[r].in) | |
5395 | test_mode = GET_MODE (rld[r].in); | |
5396 | /* If rld[r].in has VOIDmode, it means we will load it | |
5397 | in whatever mode the reload reg has: to wit, rld[r].mode. | |
5398 | We have already tested that for validity. */ | |
5399 | /* Aside from that, we need to test that the expressions | |
5400 | to reload from or into have modes which are valid for this | |
5401 | reload register. Otherwise the reload insns would be invalid. */ | |
5402 | if (! (rld[r].in != 0 && test_mode != VOIDmode | |
5403 | && ! HARD_REGNO_MODE_OK (regno, test_mode))) | |
5404 | if (! (rld[r].out != 0 | |
5405 | && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out)))) | |
5406 | { | |
5407 | /* The reg is OK. */ | |
5408 | last_spill_reg = i; | |
5409 | ||
5410 | /* Mark as in use for this insn the reload regs we use | |
5411 | for this. */ | |
5412 | mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, | |
5413 | rld[r].when_needed, rld[r].mode); | |
5414 | ||
5415 | rld[r].reg_rtx = reg; | |
5416 | reload_spill_index[r] = spill_regs[i]; | |
5417 | return 1; | |
5418 | } | |
5419 | } | |
5420 | return 0; | |
5421 | } | |
5422 | ||
08a9dd06 | 5423 | /* Find a spill register to use as a reload register for reload R. |
7fd957fe | 5424 | LAST_RELOAD is nonzero if this is the last reload for the insn being |
08a9dd06 | 5425 | processed. |
5426 | ||
48666d2c | 5427 | Set rld[R].reg_rtx to the register allocated. |
08a9dd06 | 5428 | |
fbf51e51 | 5429 | We return 1 if successful, or 0 if we couldn't find a spill reg and |
5430 | we didn't change anything. */ | |
08a9dd06 | 5431 | |
5432 | static int | |
3ad4992f | 5433 | allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r, |
5434 | int last_reload) | |
08a9dd06 | 5435 | { |
456b6b44 | 5436 | int i, pass, count; |
08a9dd06 | 5437 | |
5438 | /* If we put this reload ahead, thinking it is a group, | |
5439 | then insist on finding a group. Otherwise we can grab a | |
c8ad158d | 5440 | reg that some other reload needs. |
08a9dd06 | 5441 | (That can happen when we have a 68000 DATA_OR_FP_REG |
5442 | which is a group of data regs or one fp reg.) | |
5443 | We need not be so restrictive if there are no more reloads | |
5444 | for this insn. | |
5445 | ||
5446 | ??? Really it would be nicer to have smarter handling | |
5447 | for that kind of reg class, where a problem like this is normal. | |
5448 | Perhaps those classes should be avoided for reloading | |
5449 | by use of more alternatives. */ | |
5450 | ||
13592517 | 5451 | int force_group = rld[r].nregs > 1 && ! last_reload; |
08a9dd06 | 5452 | |
5453 | /* If we want a single register and haven't yet found one, | |
5454 | take any reg in the right class and not in use. | |
5455 | If we want a consecutive group, here is where we look for it. | |
5456 | ||
5457 | We use two passes so we can first look for reload regs to | |
5458 | reuse, which are already in use for other reloads in this insn, | |
5459 | and only then use additional registers. | |
5460 | I think that maximizing reuse is needed to make sure we don't | |
5461 | run out of reload regs. Suppose we have three reloads, and | |
5462 | reloads A and B can share regs. These need two regs. | |
5463 | Suppose A and B are given different regs. | |
5464 | That leaves none for C. */ | |
5465 | for (pass = 0; pass < 2; pass++) | |
5466 | { | |
5467 | /* I is the index in spill_regs. | |
5468 | We advance it round-robin between insns to use all spill regs | |
5469 | equally, so that inherited reloads have a chance | |
fbf51e51 | 5470 | of leapfrogging each other. */ |
5471 | ||
5472 | i = last_spill_reg; | |
5bb2f919 | 5473 | |
28e0535a | 5474 | for (count = 0; count < n_spills; count++) |
08a9dd06 | 5475 | { |
48666d2c | 5476 | int class = (int) rld[r].class; |
dab171c5 | 5477 | int regnum; |
08a9dd06 | 5478 | |
dab171c5 | 5479 | i++; |
5480 | if (i >= n_spills) | |
5481 | i -= n_spills; | |
5482 | regnum = spill_regs[i]; | |
08a9dd06 | 5483 | |
48666d2c | 5484 | if ((reload_reg_free_p (regnum, rld[r].opnum, |
5485 | rld[r].when_needed) | |
5486 | || (rld[r].in | |
5bb2f919 | 5487 | /* We check reload_reg_used to make sure we |
5488 | don't clobber the return register. */ | |
dab171c5 | 5489 | && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) |
34b8be6b | 5490 | && free_for_value_p (regnum, rld[r].mode, rld[r].opnum, |
5491 | rld[r].when_needed, rld[r].in, | |
5492 | rld[r].out, r, 1))) | |
dab171c5 | 5493 | && TEST_HARD_REG_BIT (reg_class_contents[class], regnum) |
13592517 | 5494 | && HARD_REGNO_MODE_OK (regnum, rld[r].mode) |
7ac01373 | 5495 | /* Look first for regs to share, then for unshared. But |
5496 | don't share regs used for inherited reloads; they are | |
5497 | the ones we want to preserve. */ | |
5498 | && (pass | |
5499 | || (TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
dab171c5 | 5500 | regnum) |
7ac01373 | 5501 | && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, |
dab171c5 | 5502 | regnum)))) |
08a9dd06 | 5503 | { |
67d6c12b | 5504 | int nr = hard_regno_nregs[regnum][rld[r].mode]; |
08a9dd06 | 5505 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG |
5506 | (on 68000) got us two FP regs. If NR is 1, | |
5507 | we would reject both of them. */ | |
5508 | if (force_group) | |
456b6b44 | 5509 | nr = rld[r].nregs; |
08a9dd06 | 5510 | /* If we need only one reg, we have already won. */ |
5511 | if (nr == 1) | |
5512 | { | |
5513 | /* But reject a single reg if we demand a group. */ | |
5514 | if (force_group) | |
5515 | continue; | |
5516 | break; | |
5517 | } | |
5518 | /* Otherwise check that as many consecutive regs as we need | |
fbf51e51 | 5519 | are available here. */ |
5520 | while (nr > 1) | |
5521 | { | |
5522 | int regno = regnum + nr - 1; | |
5523 | if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
5524 | && spill_reg_order[regno] >= 0 | |
5525 | && reload_reg_free_p (regno, rld[r].opnum, | |
5526 | rld[r].when_needed))) | |
5527 | break; | |
5528 | nr--; | |
5529 | } | |
08a9dd06 | 5530 | if (nr == 1) |
5531 | break; | |
5532 | } | |
5533 | } | |
5534 | ||
5535 | /* If we found something on pass 1, omit pass 2. */ | |
5536 | if (count < n_spills) | |
5537 | break; | |
5538 | } | |
aedd3e94 | 5539 | |
08a9dd06 | 5540 | /* We should have found a spill register by now. */ |
fbf51e51 | 5541 | if (count >= n_spills) |
08a9dd06 | 5542 | return 0; |
5543 | ||
fbf51e51 | 5544 | /* I is the index in SPILL_REG_RTX of the reload register we are to |
5545 | allocate. Get an rtx for it and find its register number. */ | |
08a9dd06 | 5546 | |
fbf51e51 | 5547 | return set_reload_reg (i, r); |
08a9dd06 | 5548 | } |
5549 | \f | |
456b6b44 | 5550 | /* Initialize all the tables needed to allocate reload registers. |
5551 | CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX | |
5552 | is the array we use to restore the reg_rtx field for every reload. */ | |
d6cb6164 | 5553 | |
08a9dd06 | 5554 | static void |
3ad4992f | 5555 | choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx) |
08a9dd06 | 5556 | { |
456b6b44 | 5557 | int i; |
08a9dd06 | 5558 | |
456b6b44 | 5559 | for (i = 0; i < n_reloads; i++) |
5560 | rld[i].reg_rtx = save_reload_reg_rtx[i]; | |
08a9dd06 | 5561 | |
93d3b7de | 5562 | memset (reload_inherited, 0, MAX_RELOADS); |
f0af5a88 | 5563 | memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx)); |
5564 | memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx)); | |
08a9dd06 | 5565 | |
5566 | CLEAR_HARD_REG_SET (reload_reg_used); | |
5567 | CLEAR_HARD_REG_SET (reload_reg_used_at_all); | |
08a9dd06 | 5568 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); |
58866c2c | 5569 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); |
81d0fbb3 | 5570 | CLEAR_HARD_REG_SET (reload_reg_used_in_insn); |
5571 | CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); | |
08a9dd06 | 5572 | |
9e519b97 | 5573 | CLEAR_HARD_REG_SET (reg_used_in_insn); |
5574 | { | |
5575 | HARD_REG_SET tmp; | |
f62c22a7 | 5576 | REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); |
9e519b97 | 5577 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
f62c22a7 | 5578 | REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); |
9e519b97 | 5579 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
f62c22a7 | 5580 | compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); |
5581 | compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); | |
9e519b97 | 5582 | } |
d6cb6164 | 5583 | |
81d0fbb3 | 5584 | for (i = 0; i < reload_n_operands; i++) |
5585 | { | |
5586 | CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); | |
5587 | CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); | |
5588 | CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); | |
9e53d777 | 5589 | CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); |
81d0fbb3 | 5590 | CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); |
9e53d777 | 5591 | CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); |
81d0fbb3 | 5592 | } |
08a9dd06 | 5593 | |
cab048af | 5594 | COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs); |
5bb2f919 | 5595 | |
456b6b44 | 5596 | CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); |
08a9dd06 | 5597 | |
456b6b44 | 5598 | for (i = 0; i < n_reloads; i++) |
5599 | /* If we have already decided to use a certain register, | |
5600 | don't use it in another way. */ | |
5601 | if (rld[i].reg_rtx) | |
5602 | mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, | |
5603 | rld[i].when_needed, rld[i].mode); | |
5604 | } | |
08a9dd06 | 5605 | |
456b6b44 | 5606 | /* Assign hard reg targets for the pseudo-registers we must reload |
5607 | into hard regs for this insn. | |
5608 | Also output the instructions to copy them in and out of the hard regs. | |
5609 | ||
5610 | For machines with register classes, we are responsible for | |
5611 | finding a reload reg in the proper class. */ | |
5612 | ||
5613 | static void | |
3ad4992f | 5614 | choose_reload_regs (struct insn_chain *chain) |
456b6b44 | 5615 | { |
5616 | rtx insn = chain->insn; | |
19cb6b50 | 5617 | int i, j; |
02e7a332 | 5618 | unsigned int max_group_size = 1; |
456b6b44 | 5619 | enum reg_class group_class = NO_REGS; |
fbf51e51 | 5620 | int pass, win, inheritance; |
456b6b44 | 5621 | |
5622 | rtx save_reload_reg_rtx[MAX_RELOADS]; | |
08a9dd06 | 5623 | |
08a9dd06 | 5624 | /* In order to be certain of getting the registers we need, |
5625 | we must sort the reloads into order of increasing register class. | |
5626 | Then our grabbing of reload registers will parallel the process | |
c8ad158d | 5627 | that provided the reload registers. |
08a9dd06 | 5628 | |
5629 | Also note whether any of the reloads wants a consecutive group of regs. | |
5630 | If so, record the maximum size of the group desired and what | |
5631 | register class contains all the groups needed by this insn. */ | |
5632 | ||
5633 | for (j = 0; j < n_reloads; j++) | |
5634 | { | |
5635 | reload_order[j] = j; | |
5636 | reload_spill_index[j] = -1; | |
5637 | ||
13592517 | 5638 | if (rld[j].nregs > 1) |
08a9dd06 | 5639 | { |
13592517 | 5640 | max_group_size = MAX (rld[j].nregs, max_group_size); |
02e7a332 | 5641 | group_class |
337d789b | 5642 | = reg_class_superunion[(int) rld[j].class][(int) group_class]; |
08a9dd06 | 5643 | } |
5644 | ||
48666d2c | 5645 | save_reload_reg_rtx[j] = rld[j].reg_rtx; |
08a9dd06 | 5646 | } |
5647 | ||
5648 | if (n_reloads > 1) | |
5649 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
5650 | ||
5ef88ef5 | 5651 | /* If -O, try first with inheritance, then turning it off. |
5652 | If not -O, don't do inheritance. | |
5653 | Using inheritance when not optimizing leads to paradoxes | |
5654 | with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves | |
5655 | because one side of the comparison might be inherited. */ | |
fbf51e51 | 5656 | win = 0; |
5ef88ef5 | 5657 | for (inheritance = optimize > 0; inheritance >= 0; inheritance--) |
08a9dd06 | 5658 | { |
456b6b44 | 5659 | choose_reload_regs_init (chain, save_reload_reg_rtx); |
5660 | ||
08a9dd06 | 5661 | /* Process the reloads in order of preference just found. |
5662 | Beyond this point, subregs can be found in reload_reg_rtx. | |
5663 | ||
02e7a332 | 5664 | This used to look for an existing reloaded home for all of the |
5665 | reloads, and only then perform any new reloads. But that could lose | |
5666 | if the reloads were done out of reg-class order because a later | |
5667 | reload with a looser constraint might have an old home in a register | |
5668 | needed by an earlier reload with a tighter constraint. | |
08a9dd06 | 5669 | |
5670 | To solve this, we make two passes over the reloads, in the order | |
5671 | described above. In the first pass we try to inherit a reload | |
5672 | from a previous insn. If there is a later reload that needs a | |
5673 | class that is a proper subset of the class being processed, we must | |
5674 | also allocate a spill register during the first pass. | |
5675 | ||
5676 | Then make a second pass over the reloads to allocate any reloads | |
5677 | that haven't been given registers yet. */ | |
5678 | ||
5679 | for (j = 0; j < n_reloads; j++) | |
5680 | { | |
19cb6b50 | 5681 | int r = reload_order[j]; |
e42003bb | 5682 | rtx search_equiv = NULL_RTX; |
08a9dd06 | 5683 | |
5684 | /* Ignore reloads that got marked inoperative. */ | |
48666d2c | 5685 | if (rld[r].out == 0 && rld[r].in == 0 |
5686 | && ! rld[r].secondary_p) | |
08a9dd06 | 5687 | continue; |
5688 | ||
c8ff929f | 5689 | /* If find_reloads chose to use reload_in or reload_out as a reload |
f2a79eb6 | 5690 | register, we don't need to chose one. Otherwise, try even if it |
5691 | found one since we might save an insn if we find the value lying | |
c8ff929f | 5692 | around. |
5693 | Try also when reload_in is a pseudo without a hard reg. */ | |
48666d2c | 5694 | if (rld[r].in != 0 && rld[r].reg_rtx != 0 |
5695 | && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) | |
5696 | || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) | |
e16ceb8e | 5697 | && !MEM_P (rld[r].in) |
48666d2c | 5698 | && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) |
08a9dd06 | 5699 | continue; |
5700 | ||
5701 | #if 0 /* No longer needed for correct operation. | |
5702 | It might give better code, or might not; worth an experiment? */ | |
5703 | /* If this is an optional reload, we can't inherit from earlier insns | |
5704 | until we are sure that any non-optional reloads have been allocated. | |
5705 | The following code takes advantage of the fact that optional reloads | |
5706 | are at the end of reload_order. */ | |
48666d2c | 5707 | if (rld[r].optional != 0) |
08a9dd06 | 5708 | for (i = 0; i < j; i++) |
48666d2c | 5709 | if ((rld[reload_order[i]].out != 0 |
5710 | || rld[reload_order[i]].in != 0 | |
5711 | || rld[reload_order[i]].secondary_p) | |
5712 | && ! rld[reload_order[i]].optional | |
5713 | && rld[reload_order[i]].reg_rtx == 0) | |
fbf51e51 | 5714 | allocate_reload_reg (chain, reload_order[i], 0); |
08a9dd06 | 5715 | #endif |
5716 | ||
5717 | /* First see if this pseudo is already available as reloaded | |
5718 | for a previous insn. We cannot try to inherit for reloads | |
5719 | that are smaller than the maximum number of registers needed | |
5720 | for groups unless the register we would allocate cannot be used | |
5721 | for the groups. | |
5722 | ||
5723 | We could check here to see if this is a secondary reload for | |
5724 | an object that is already in a register of the desired class. | |
5725 | This would avoid the need for the secondary reload register. | |
5726 | But this is complex because we can't easily determine what | |
f2a79eb6 | 5727 | objects might want to be loaded via this reload. So let a |
5728 | register be allocated here. In `emit_reload_insns' we suppress | |
5729 | one of the loads in the case described above. */ | |
08a9dd06 | 5730 | |
5731 | if (inheritance) | |
5732 | { | |
701e46d0 | 5733 | int byte = 0; |
19cb6b50 | 5734 | int regno = -1; |
df9f2bb6 | 5735 | enum machine_mode mode = VOIDmode; |
08a9dd06 | 5736 | |
48666d2c | 5737 | if (rld[r].in == 0) |
08a9dd06 | 5738 | ; |
8ad4c111 | 5739 | else if (REG_P (rld[r].in)) |
bab79d5d | 5740 | { |
48666d2c | 5741 | regno = REGNO (rld[r].in); |
5742 | mode = GET_MODE (rld[r].in); | |
bab79d5d | 5743 | } |
8ad4c111 | 5744 | else if (REG_P (rld[r].in_reg)) |
bab79d5d | 5745 | { |
48666d2c | 5746 | regno = REGNO (rld[r].in_reg); |
5747 | mode = GET_MODE (rld[r].in_reg); | |
bab79d5d | 5748 | } |
48666d2c | 5749 | else if (GET_CODE (rld[r].in_reg) == SUBREG |
8ad4c111 | 5750 | && REG_P (SUBREG_REG (rld[r].in_reg))) |
6aed5e78 | 5751 | { |
48666d2c | 5752 | regno = REGNO (SUBREG_REG (rld[r].in_reg)); |
93c7b06e | 5753 | if (regno < FIRST_PSEUDO_REGISTER) |
701e46d0 | 5754 | regno = subreg_regno (rld[r].in_reg); |
0fe7e658 | 5755 | else |
5756 | byte = SUBREG_BYTE (rld[r].in_reg); | |
48666d2c | 5757 | mode = GET_MODE (rld[r].in_reg); |
93c7b06e | 5758 | } |
5759 | #ifdef AUTO_INC_DEC | |
f5bccbd1 | 5760 | else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC |
8ad4c111 | 5761 | && REG_P (XEXP (rld[r].in_reg, 0))) |
93c7b06e | 5762 | { |
48666d2c | 5763 | regno = REGNO (XEXP (rld[r].in_reg, 0)); |
5764 | mode = GET_MODE (XEXP (rld[r].in_reg, 0)); | |
5765 | rld[r].out = rld[r].in; | |
6aed5e78 | 5766 | } |
93c7b06e | 5767 | #endif |
08a9dd06 | 5768 | #if 0 |
5769 | /* This won't work, since REGNO can be a pseudo reg number. | |
5770 | Also, it takes much more hair to keep track of all the things | |
5771 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
48666d2c | 5772 | else if (GET_CODE (rld[r].in) == SUBREG |
8ad4c111 | 5773 | && REG_P (SUBREG_REG (rld[r].in))) |
701e46d0 | 5774 | regno = subreg_regno (rld[r].in); |
08a9dd06 | 5775 | #endif |
5776 | ||
f82c9309 | 5777 | if (regno >= 0 |
5778 | && reg_last_reload_reg[regno] != 0 | |
5779 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
5780 | /* Verify that the register it's in can be used in | |
5781 | mode MODE. */ | |
5782 | && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]), | |
5783 | GET_MODE (reg_last_reload_reg[regno]), | |
5784 | mode) | |
5785 | #endif | |
5786 | ) | |
08a9dd06 | 5787 | { |
48666d2c | 5788 | enum reg_class class = rld[r].class, last_class; |
93c7b06e | 5789 | rtx last_reg = reg_last_reload_reg[regno]; |
c5af420e | 5790 | enum machine_mode need_mode; |
5bb2f919 | 5791 | |
701e46d0 | 5792 | i = REGNO (last_reg); |
5793 | i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode); | |
93c7b06e | 5794 | last_class = REGNO_REG_CLASS (i); |
c5af420e | 5795 | |
701e46d0 | 5796 | if (byte == 0) |
e699a0ac | 5797 | need_mode = mode; |
5798 | else | |
5799 | need_mode | |
941b4534 | 5800 | = smallest_mode_for_size (GET_MODE_BITSIZE (mode) |
5801 | + byte * BITS_PER_UNIT, | |
e699a0ac | 5802 | GET_MODE_CLASS (mode)); |
c5af420e | 5803 | |
941b4534 | 5804 | if ((GET_MODE_SIZE (GET_MODE (last_reg)) |
c5af420e | 5805 | >= GET_MODE_SIZE (need_mode)) |
93c7b06e | 5806 | && reg_reloaded_contents[i] == regno |
a5e95c30 | 5807 | && TEST_HARD_REG_BIT (reg_reloaded_valid, i) |
13592517 | 5808 | && HARD_REGNO_MODE_OK (i, rld[r].mode) |
93c7b06e | 5809 | && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i) |
5810 | /* Even if we can't use this register as a reload | |
5811 | register, we might use it for reload_override_in, | |
5812 | if copying it to the desired class is cheap | |
5813 | enough. */ | |
0ac516dc | 5814 | || ((REGISTER_MOVE_COST (mode, last_class, class) |
93c7b06e | 5815 | < MEMORY_MOVE_COST (mode, class, 1)) |
4d58fa46 | 5816 | && (secondary_reload_class (1, class, mode, |
5817 | last_reg) | |
93c7b06e | 5818 | == NO_REGS) |
93c7b06e | 5819 | #ifdef SECONDARY_MEMORY_NEEDED |
5820 | && ! SECONDARY_MEMORY_NEEDED (last_class, class, | |
5821 | mode) | |
5822 | #endif | |
5823 | )) | |
5824 | ||
13592517 | 5825 | && (rld[r].nregs == max_group_size |
08a9dd06 | 5826 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], |
a5e95c30 | 5827 | i)) |
34b8be6b | 5828 | && free_for_value_p (i, rld[r].mode, rld[r].opnum, |
5829 | rld[r].when_needed, rld[r].in, | |
5830 | const0_rtx, r, 1)) | |
08a9dd06 | 5831 | { |
5832 | /* If a group is needed, verify that all the subsequent | |
a92771b8 | 5833 | registers still have their values intact. */ |
67d6c12b | 5834 | int nr = hard_regno_nregs[i][rld[r].mode]; |
08a9dd06 | 5835 | int k; |
5836 | ||
5837 | for (k = 1; k < nr; k++) | |
a5e95c30 | 5838 | if (reg_reloaded_contents[i + k] != regno |
5839 | || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) | |
08a9dd06 | 5840 | break; |
5841 | ||
5842 | if (k == nr) | |
5843 | { | |
99a8d31a | 5844 | int i1; |
1af37dfe | 5845 | int bad_for_class; |
99a8d31a | 5846 | |
93c7b06e | 5847 | last_reg = (GET_MODE (last_reg) == mode |
5848 | ? last_reg : gen_rtx_REG (mode, i)); | |
5849 | ||
1af37dfe | 5850 | bad_for_class = 0; |
5851 | for (k = 0; k < nr; k++) | |
5852 | bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], | |
5853 | i+k); | |
5854 | ||
99a8d31a | 5855 | /* We found a register that contains the |
5856 | value we need. If this register is the | |
5857 | same as an `earlyclobber' operand of the | |
5858 | current insn, just mark it as a place to | |
5859 | reload from since we can't use it as the | |
5860 | reload register itself. */ | |
5861 | ||
5862 | for (i1 = 0; i1 < n_earlyclobbers; i1++) | |
5863 | if (reg_overlap_mentioned_for_reload_p | |
5864 | (reg_last_reload_reg[regno], | |
5865 | reload_earlyclobbers[i1])) | |
5866 | break; | |
5867 | ||
c06cbe22 | 5868 | if (i1 != n_earlyclobbers |
34b8be6b | 5869 | || ! (free_for_value_p (i, rld[r].mode, |
5870 | rld[r].opnum, | |
5871 | rld[r].when_needed, rld[r].in, | |
5872 | rld[r].out, r, 1)) | |
a5e95c30 | 5873 | /* Don't use it if we'd clobber a pseudo reg. */ |
9e519b97 | 5874 | || (TEST_HARD_REG_BIT (reg_used_in_insn, i) |
48666d2c | 5875 | && rld[r].out |
a5e95c30 | 5876 | && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) |
a138e13e | 5877 | /* Don't clobber the frame pointer. */ |
aedd3e94 | 5878 | || (i == HARD_FRAME_POINTER_REGNUM |
6f813137 | 5879 | && frame_pointer_needed |
aedd3e94 | 5880 | && rld[r].out) |
c06cbe22 | 5881 | /* Don't really use the inherited spill reg |
5882 | if we need it wider than we've got it. */ | |
13592517 | 5883 | || (GET_MODE_SIZE (rld[r].mode) |
c8ff929f | 5884 | > GET_MODE_SIZE (mode)) |
1af37dfe | 5885 | || bad_for_class |
93c7b06e | 5886 | |
c8ff929f | 5887 | /* If find_reloads chose reload_out as reload |
5888 | register, stay with it - that leaves the | |
5889 | inherited register for subsequent reloads. */ | |
48666d2c | 5890 | || (rld[r].out && rld[r].reg_rtx |
456b6b44 | 5891 | && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) |
93c7b06e | 5892 | { |
0e460feb | 5893 | if (! rld[r].optional) |
5894 | { | |
5895 | reload_override_in[r] = last_reg; | |
5896 | reload_inheritance_insn[r] | |
5897 | = reg_reloaded_insn[i]; | |
5898 | } | |
93c7b06e | 5899 | } |
99a8d31a | 5900 | else |
5901 | { | |
a24e1dd2 | 5902 | int k; |
99a8d31a | 5903 | /* We can use this as a reload reg. */ |
5904 | /* Mark the register as in use for this part of | |
5905 | the insn. */ | |
a5e95c30 | 5906 | mark_reload_reg_in_use (i, |
48666d2c | 5907 | rld[r].opnum, |
5908 | rld[r].when_needed, | |
13592517 | 5909 | rld[r].mode); |
48666d2c | 5910 | rld[r].reg_rtx = last_reg; |
99a8d31a | 5911 | reload_inherited[r] = 1; |
5912 | reload_inheritance_insn[r] | |
5913 | = reg_reloaded_insn[i]; | |
5914 | reload_spill_index[r] = i; | |
a24e1dd2 | 5915 | for (k = 0; k < nr; k++) |
5916 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, | |
a5e95c30 | 5917 | i + k); |
99a8d31a | 5918 | } |
08a9dd06 | 5919 | } |
5920 | } | |
5921 | } | |
5922 | } | |
5923 | ||
5924 | /* Here's another way to see if the value is already lying around. */ | |
5925 | if (inheritance | |
48666d2c | 5926 | && rld[r].in != 0 |
08a9dd06 | 5927 | && ! reload_inherited[r] |
48666d2c | 5928 | && rld[r].out == 0 |
5929 | && (CONSTANT_P (rld[r].in) | |
5930 | || GET_CODE (rld[r].in) == PLUS | |
8ad4c111 | 5931 | || REG_P (rld[r].in) |
e16ceb8e | 5932 | || MEM_P (rld[r].in)) |
13592517 | 5933 | && (rld[r].nregs == max_group_size |
48666d2c | 5934 | || ! reg_classes_intersect_p (rld[r].class, group_class))) |
5935 | search_equiv = rld[r].in; | |
e42003bb | 5936 | /* If this is an output reload from a simple move insn, look |
5937 | if an equivalence for the input is available. */ | |
48666d2c | 5938 | else if (inheritance && rld[r].in == 0 && rld[r].out != 0) |
e42003bb | 5939 | { |
5940 | rtx set = single_set (insn); | |
5941 | ||
5942 | if (set | |
48666d2c | 5943 | && rtx_equal_p (rld[r].out, SET_DEST (set)) |
e42003bb | 5944 | && CONSTANT_P (SET_SRC (set))) |
5945 | search_equiv = SET_SRC (set); | |
5946 | } | |
5947 | ||
5948 | if (search_equiv) | |
08a9dd06 | 5949 | { |
19cb6b50 | 5950 | rtx equiv |
48666d2c | 5951 | = find_equiv_reg (search_equiv, insn, rld[r].class, |
4679ade3 | 5952 | -1, NULL, 0, rld[r].mode); |
d844aacc | 5953 | int regno = 0; |
08a9dd06 | 5954 | |
5955 | if (equiv != 0) | |
5956 | { | |
8ad4c111 | 5957 | if (REG_P (equiv)) |
08a9dd06 | 5958 | regno = REGNO (equiv); |
04e579b6 | 5959 | else |
08a9dd06 | 5960 | { |
ef5b5374 | 5961 | /* This must be a SUBREG of a hard register. |
5962 | Make a new REG since this might be used in an | |
5963 | address and not all machines support SUBREGs | |
5964 | there. */ | |
04e579b6 | 5965 | gcc_assert (GET_CODE (equiv) == SUBREG); |
701e46d0 | 5966 | regno = subreg_regno (equiv); |
13592517 | 5967 | equiv = gen_rtx_REG (rld[r].mode, regno); |
fc0cc704 | 5968 | /* If we choose EQUIV as the reload register, but the |
5969 | loop below decides to cancel the inheritance, we'll | |
5970 | end up reloading EQUIV in rld[r].mode, not the mode | |
5971 | it had originally. That isn't safe when EQUIV isn't | |
5972 | available as a spill register since its value might | |
5973 | still be live at this point. */ | |
5974 | for (i = regno; i < regno + (int) rld[r].nregs; i++) | |
5975 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, i)) | |
5976 | equiv = 0; | |
08a9dd06 | 5977 | } |
08a9dd06 | 5978 | } |
5979 | ||
5980 | /* If we found a spill reg, reject it unless it is free | |
5981 | and of the desired class. */ | |
7e6128ca | 5982 | if (equiv != 0) |
5983 | { | |
5984 | int regs_used = 0; | |
5985 | int bad_for_class = 0; | |
5986 | int max_regno = regno + rld[r].nregs; | |
5987 | ||
5988 | for (i = regno; i < max_regno; i++) | |
5989 | { | |
5990 | regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
5991 | i); | |
3ad4992f | 5992 | bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], |
7e6128ca | 5993 | i); |
5994 | } | |
5995 | ||
5996 | if ((regs_used | |
34b8be6b | 5997 | && ! free_for_value_p (regno, rld[r].mode, |
5998 | rld[r].opnum, rld[r].when_needed, | |
5999 | rld[r].in, rld[r].out, r, 1)) | |
7e6128ca | 6000 | || bad_for_class) |
6001 | equiv = 0; | |
6002 | } | |
08a9dd06 | 6003 | |
13592517 | 6004 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) |
08a9dd06 | 6005 | equiv = 0; |
6006 | ||
6007 | /* We found a register that contains the value we need. | |
6008 | If this register is the same as an `earlyclobber' operand | |
6009 | of the current insn, just mark it as a place to reload from | |
6010 | since we can't use it as the reload register itself. */ | |
6011 | ||
6012 | if (equiv != 0) | |
6013 | for (i = 0; i < n_earlyclobbers; i++) | |
d3862ba2 | 6014 | if (reg_overlap_mentioned_for_reload_p (equiv, |
6015 | reload_earlyclobbers[i])) | |
08a9dd06 | 6016 | { |
0e460feb | 6017 | if (! rld[r].optional) |
6018 | reload_override_in[r] = equiv; | |
08a9dd06 | 6019 | equiv = 0; |
6020 | break; | |
6021 | } | |
6022 | ||
ec89129f | 6023 | /* If the equiv register we have found is explicitly clobbered |
6024 | in the current insn, it depends on the reload type if we | |
6025 | can use it, use it for reload_override_in, or not at all. | |
6026 | In particular, we then can't use EQUIV for a | |
6027 | RELOAD_FOR_OUTPUT_ADDRESS reload. */ | |
08a9dd06 | 6028 | |
ab7883ae | 6029 | if (equiv != 0) |
4f271297 | 6030 | { |
a80cd853 | 6031 | if (regno_clobbered_p (regno, insn, rld[r].mode, 2)) |
ab7883ae | 6032 | switch (rld[r].when_needed) |
6033 | { | |
6034 | case RELOAD_FOR_OTHER_ADDRESS: | |
6035 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6036 | case RELOAD_FOR_INPUT_ADDRESS: | |
6037 | case RELOAD_FOR_OPADDR_ADDR: | |
6038 | break; | |
6039 | case RELOAD_OTHER: | |
6040 | case RELOAD_FOR_INPUT: | |
6041 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6042 | if (! rld[r].optional) | |
6043 | reload_override_in[r] = equiv; | |
6044 | /* Fall through. */ | |
6045 | default: | |
6046 | equiv = 0; | |
6047 | break; | |
6048 | } | |
6049 | else if (regno_clobbered_p (regno, insn, rld[r].mode, 1)) | |
6050 | switch (rld[r].when_needed) | |
6051 | { | |
6052 | case RELOAD_FOR_OTHER_ADDRESS: | |
6053 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6054 | case RELOAD_FOR_INPUT_ADDRESS: | |
6055 | case RELOAD_FOR_OPADDR_ADDR: | |
6056 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6057 | case RELOAD_FOR_INPUT: | |
6058 | break; | |
6059 | case RELOAD_OTHER: | |
6060 | if (! rld[r].optional) | |
6061 | reload_override_in[r] = equiv; | |
6062 | /* Fall through. */ | |
6063 | default: | |
6064 | equiv = 0; | |
6065 | break; | |
6066 | } | |
08a9dd06 | 6067 | } |
6068 | ||
6069 | /* If we found an equivalent reg, say no code need be generated | |
6070 | to load it, and use it as our reload reg. */ | |
2617fe26 | 6071 | if (equiv != 0 |
6072 | && (regno != HARD_FRAME_POINTER_REGNUM | |
6f813137 | 6073 | || !frame_pointer_needed)) |
08a9dd06 | 6074 | { |
67d6c12b | 6075 | int nr = hard_regno_nregs[regno][rld[r].mode]; |
7786d760 | 6076 | int k; |
48666d2c | 6077 | rld[r].reg_rtx = equiv; |
08a9dd06 | 6078 | reload_inherited[r] = 1; |
7786d760 | 6079 | |
bd24587d | 6080 | /* If reg_reloaded_valid is not set for this register, |
6081 | there might be a stale spill_reg_store lying around. | |
6082 | We must clear it, since otherwise emit_reload_insns | |
6083 | might delete the store. */ | |
6084 | if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) | |
6085 | spill_reg_store[regno] = NULL_RTX; | |
7786d760 | 6086 | /* If any of the hard registers in EQUIV are spill |
6087 | registers, mark them as in use for this insn. */ | |
6088 | for (k = 0; k < nr; k++) | |
7ac01373 | 6089 | { |
7786d760 | 6090 | i = spill_reg_order[regno + k]; |
6091 | if (i >= 0) | |
6092 | { | |
48666d2c | 6093 | mark_reload_reg_in_use (regno, rld[r].opnum, |
6094 | rld[r].when_needed, | |
13592517 | 6095 | rld[r].mode); |
7786d760 | 6096 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, |
6097 | regno + k); | |
6098 | } | |
7ac01373 | 6099 | } |
08a9dd06 | 6100 | } |
6101 | } | |
6102 | ||
6103 | /* If we found a register to use already, or if this is an optional | |
6104 | reload, we are done. */ | |
48666d2c | 6105 | if (rld[r].reg_rtx != 0 || rld[r].optional != 0) |
08a9dd06 | 6106 | continue; |
6107 | ||
aedd3e94 | 6108 | #if 0 |
6109 | /* No longer needed for correct operation. Might or might | |
6110 | not give better code on the average. Want to experiment? */ | |
08a9dd06 | 6111 | |
6112 | /* See if there is a later reload that has a class different from our | |
6113 | class that intersects our class or that requires less register | |
6114 | than our reload. If so, we must allocate a register to this | |
6115 | reload now, since that reload might inherit a previous reload | |
6116 | and take the only available register in our class. Don't do this | |
6117 | for optional reloads since they will force all previous reloads | |
6118 | to be allocated. Also don't do this for reloads that have been | |
6119 | turned off. */ | |
6120 | ||
6121 | for (i = j + 1; i < n_reloads; i++) | |
6122 | { | |
6123 | int s = reload_order[i]; | |
6124 | ||
48666d2c | 6125 | if ((rld[s].in == 0 && rld[s].out == 0 |
6126 | && ! rld[s].secondary_p) | |
6127 | || rld[s].optional) | |
08a9dd06 | 6128 | continue; |
6129 | ||
48666d2c | 6130 | if ((rld[s].class != rld[r].class |
6131 | && reg_classes_intersect_p (rld[r].class, | |
6132 | rld[s].class)) | |
13592517 | 6133 | || rld[s].nregs < rld[r].nregs) |
5bb2f919 | 6134 | break; |
08a9dd06 | 6135 | } |
6136 | ||
6137 | if (i == n_reloads) | |
6138 | continue; | |
6139 | ||
fbf51e51 | 6140 | allocate_reload_reg (chain, r, j == n_reloads - 1); |
08a9dd06 | 6141 | #endif |
6142 | } | |
6143 | ||
6144 | /* Now allocate reload registers for anything non-optional that | |
6145 | didn't get one yet. */ | |
6146 | for (j = 0; j < n_reloads; j++) | |
6147 | { | |
19cb6b50 | 6148 | int r = reload_order[j]; |
08a9dd06 | 6149 | |
6150 | /* Ignore reloads that got marked inoperative. */ | |
48666d2c | 6151 | if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) |
08a9dd06 | 6152 | continue; |
6153 | ||
6154 | /* Skip reloads that already have a register allocated or are | |
a92771b8 | 6155 | optional. */ |
48666d2c | 6156 | if (rld[r].reg_rtx != 0 || rld[r].optional) |
08a9dd06 | 6157 | continue; |
6158 | ||
fbf51e51 | 6159 | if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) |
08a9dd06 | 6160 | break; |
6161 | } | |
6162 | ||
6163 | /* If that loop got all the way, we have won. */ | |
6164 | if (j == n_reloads) | |
fbf51e51 | 6165 | { |
6166 | win = 1; | |
6167 | break; | |
6168 | } | |
08a9dd06 | 6169 | |
08a9dd06 | 6170 | /* Loop around and try without any inheritance. */ |
08a9dd06 | 6171 | } |
6172 | ||
fbf51e51 | 6173 | if (! win) |
6174 | { | |
6175 | /* First undo everything done by the failed attempt | |
6176 | to allocate with inheritance. */ | |
6177 | choose_reload_regs_init (chain, save_reload_reg_rtx); | |
6178 | ||
6179 | /* Some sanity tests to verify that the reloads found in the first | |
6180 | pass are identical to the ones we have now. */ | |
04e579b6 | 6181 | gcc_assert (chain->n_reloads == n_reloads); |
fbf51e51 | 6182 | |
6183 | for (i = 0; i < n_reloads; i++) | |
6184 | { | |
6185 | if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) | |
6186 | continue; | |
04e579b6 | 6187 | gcc_assert (chain->rld[i].when_needed == rld[i].when_needed); |
fbf51e51 | 6188 | for (j = 0; j < n_spills; j++) |
6189 | if (spill_regs[j] == chain->rld[i].regno) | |
6190 | if (! set_reload_reg (j, i)) | |
6191 | failed_reload (chain->insn, i); | |
6192 | } | |
6193 | } | |
6194 | ||
08a9dd06 | 6195 | /* If we thought we could inherit a reload, because it seemed that |
6196 | nothing else wanted the same reload register earlier in the insn, | |
93c7b06e | 6197 | verify that assumption, now that all reloads have been assigned. |
6198 | Likewise for reloads where reload_override_in has been set. */ | |
08a9dd06 | 6199 | |
93c7b06e | 6200 | /* If doing expensive optimizations, do one preliminary pass that doesn't |
6201 | cancel any inheritance, but removes reloads that have been needed only | |
6202 | for reloads that we know can be inherited. */ | |
6203 | for (pass = flag_expensive_optimizations; pass >= 0; pass--) | |
08a9dd06 | 6204 | { |
93c7b06e | 6205 | for (j = 0; j < n_reloads; j++) |
524613c6 | 6206 | { |
19cb6b50 | 6207 | int r = reload_order[j]; |
93c7b06e | 6208 | rtx check_reg; |
48666d2c | 6209 | if (reload_inherited[r] && rld[r].reg_rtx) |
6210 | check_reg = rld[r].reg_rtx; | |
93c7b06e | 6211 | else if (reload_override_in[r] |
8ad4c111 | 6212 | && (REG_P (reload_override_in[r]) |
5bb2f919 | 6213 | || GET_CODE (reload_override_in[r]) == SUBREG)) |
93c7b06e | 6214 | check_reg = reload_override_in[r]; |
6215 | else | |
6216 | continue; | |
34b8be6b | 6217 | if (! free_for_value_p (true_regnum (check_reg), rld[r].mode, |
6218 | rld[r].opnum, rld[r].when_needed, rld[r].in, | |
6219 | (reload_inherited[r] | |
6220 | ? rld[r].out : const0_rtx), | |
6221 | r, 1)) | |
524613c6 | 6222 | { |
93c7b06e | 6223 | if (pass) |
6224 | continue; | |
6225 | reload_inherited[r] = 0; | |
6226 | reload_override_in[r] = 0; | |
524613c6 | 6227 | } |
93c7b06e | 6228 | /* If we can inherit a RELOAD_FOR_INPUT, or can use a |
6229 | reload_override_in, then we do not need its related | |
6230 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; | |
6231 | likewise for other reload types. | |
6232 | We handle this by removing a reload when its only replacement | |
6233 | is mentioned in reload_in of the reload we are going to inherit. | |
6234 | A special case are auto_inc expressions; even if the input is | |
6235 | inherited, we still need the address for the output. We can | |
39ba54b9 | 6236 | recognize them because they have RELOAD_OUT set to RELOAD_IN. |
4a82352a | 6237 | If we succeeded removing some reload and we are doing a preliminary |
93c7b06e | 6238 | pass just to remove such reloads, make another pass, since the |
6239 | removal of one reload might allow us to inherit another one. */ | |
48666d2c | 6240 | else if (rld[r].in |
6241 | && rld[r].out != rld[r].in | |
6242 | && remove_address_replacements (rld[r].in) && pass) | |
93c7b06e | 6243 | pass = 2; |
08a9dd06 | 6244 | } |
6245 | } | |
6246 | ||
6247 | /* Now that reload_override_in is known valid, | |
6248 | actually override reload_in. */ | |
6249 | for (j = 0; j < n_reloads; j++) | |
6250 | if (reload_override_in[j]) | |
48666d2c | 6251 | rld[j].in = reload_override_in[j]; |
08a9dd06 | 6252 | |
a8b24921 | 6253 | /* If this reload won't be done because it has been canceled or is |
08a9dd06 | 6254 | optional and not inherited, clear reload_reg_rtx so other |
6255 | routines (such as subst_reloads) don't get confused. */ | |
6256 | for (j = 0; j < n_reloads; j++) | |
48666d2c | 6257 | if (rld[j].reg_rtx != 0 |
6258 | && ((rld[j].optional && ! reload_inherited[j]) | |
6259 | || (rld[j].in == 0 && rld[j].out == 0 | |
6260 | && ! rld[j].secondary_p))) | |
7ac01373 | 6261 | { |
48666d2c | 6262 | int regno = true_regnum (rld[j].reg_rtx); |
7ac01373 | 6263 | |
6264 | if (spill_reg_order[regno] >= 0) | |
48666d2c | 6265 | clear_reload_reg_in_use (regno, rld[j].opnum, |
13592517 | 6266 | rld[j].when_needed, rld[j].mode); |
48666d2c | 6267 | rld[j].reg_rtx = 0; |
931d05cc | 6268 | reload_spill_index[j] = -1; |
7ac01373 | 6269 | } |
08a9dd06 | 6270 | |
6271 | /* Record which pseudos and which spill regs have output reloads. */ | |
6272 | for (j = 0; j < n_reloads; j++) | |
6273 | { | |
19cb6b50 | 6274 | int r = reload_order[j]; |
08a9dd06 | 6275 | |
6276 | i = reload_spill_index[r]; | |
6277 | ||
a5e95c30 | 6278 | /* I is nonneg if this reload uses a register. |
48666d2c | 6279 | If rld[r].reg_rtx is 0, this is an optional reload |
08a9dd06 | 6280 | that we opted to ignore. */ |
8ad4c111 | 6281 | if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg) |
48666d2c | 6282 | && rld[r].reg_rtx != 0) |
08a9dd06 | 6283 | { |
19cb6b50 | 6284 | int nregno = REGNO (rld[r].out_reg); |
4ddbcdd2 | 6285 | int nr = 1; |
6286 | ||
6287 | if (nregno < FIRST_PSEUDO_REGISTER) | |
67d6c12b | 6288 | nr = hard_regno_nregs[nregno][rld[r].mode]; |
08a9dd06 | 6289 | |
6290 | while (--nr >= 0) | |
7d742877 | 6291 | SET_REGNO_REG_SET (®_has_output_reload, |
6292 | nregno + nr); | |
4ddbcdd2 | 6293 | |
6294 | if (i >= 0) | |
08a9dd06 | 6295 | { |
67d6c12b | 6296 | nr = hard_regno_nregs[i][rld[r].mode]; |
4ddbcdd2 | 6297 | while (--nr >= 0) |
a5e95c30 | 6298 | SET_HARD_REG_BIT (reg_is_output_reload, i + nr); |
08a9dd06 | 6299 | } |
6300 | ||
04e579b6 | 6301 | gcc_assert (rld[r].when_needed == RELOAD_OTHER |
6302 | || rld[r].when_needed == RELOAD_FOR_OUTPUT | |
6303 | || rld[r].when_needed == RELOAD_FOR_INSN); | |
08a9dd06 | 6304 | } |
6305 | } | |
6306 | } | |
93c7b06e | 6307 | |
6308 | /* Deallocate the reload register for reload R. This is called from | |
6309 | remove_address_replacements. */ | |
dccf4eb3 | 6310 | |
93c7b06e | 6311 | void |
3ad4992f | 6312 | deallocate_reload_reg (int r) |
93c7b06e | 6313 | { |
6314 | int regno; | |
6315 | ||
48666d2c | 6316 | if (! rld[r].reg_rtx) |
93c7b06e | 6317 | return; |
48666d2c | 6318 | regno = true_regnum (rld[r].reg_rtx); |
6319 | rld[r].reg_rtx = 0; | |
93c7b06e | 6320 | if (spill_reg_order[regno] >= 0) |
48666d2c | 6321 | clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, |
13592517 | 6322 | rld[r].mode); |
93c7b06e | 6323 | reload_spill_index[r] = -1; |
6324 | } | |
08a9dd06 | 6325 | \f |
7fd957fe | 6326 | /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two |
81d0fbb3 | 6327 | reloads of the same item for fear that we might not have enough reload |
6328 | registers. However, normally they will get the same reload register | |
5bb2f919 | 6329 | and hence actually need not be loaded twice. |
81d0fbb3 | 6330 | |
6331 | Here we check for the most common case of this phenomenon: when we have | |
6332 | a number of reloads for the same object, each of which were allocated | |
6333 | the same reload_reg_rtx, that reload_reg_rtx is not used for any other | |
6334 | reload, and is not modified in the insn itself. If we find such, | |
6335 | merge all the reloads and set the resulting reload to RELOAD_OTHER. | |
6336 | This will not increase the number of spill registers needed and will | |
6337 | prevent redundant code. */ | |
6338 | ||
81d0fbb3 | 6339 | static void |
3ad4992f | 6340 | merge_assigned_reloads (rtx insn) |
81d0fbb3 | 6341 | { |
6342 | int i, j; | |
6343 | ||
6344 | /* Scan all the reloads looking for ones that only load values and | |
6345 | are not already RELOAD_OTHER and ones whose reload_reg_rtx are | |
6346 | assigned and not modified by INSN. */ | |
6347 | ||
6348 | for (i = 0; i < n_reloads; i++) | |
6349 | { | |
bb89c1cf | 6350 | int conflicting_input = 0; |
6351 | int max_input_address_opnum = -1; | |
6352 | int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; | |
6353 | ||
48666d2c | 6354 | if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER |
6355 | || rld[i].out != 0 || rld[i].reg_rtx == 0 | |
6356 | || reg_set_p (rld[i].reg_rtx, insn)) | |
81d0fbb3 | 6357 | continue; |
6358 | ||
6359 | /* Look at all other reloads. Ensure that the only use of this | |
6360 | reload_reg_rtx is in a reload that just loads the same value | |
6361 | as we do. Note that any secondary reloads must be of the identical | |
6362 | class since the values, modes, and result registers are the | |
6363 | same, so we need not do anything with any secondary reloads. */ | |
6364 | ||
6365 | for (j = 0; j < n_reloads; j++) | |
6366 | { | |
48666d2c | 6367 | if (i == j || rld[j].reg_rtx == 0 |
6368 | || ! reg_overlap_mentioned_p (rld[j].reg_rtx, | |
6369 | rld[i].reg_rtx)) | |
81d0fbb3 | 6370 | continue; |
6371 | ||
48666d2c | 6372 | if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6373 | && rld[j].opnum > max_input_address_opnum) | |
6374 | max_input_address_opnum = rld[j].opnum; | |
bb89c1cf | 6375 | |
81d0fbb3 | 6376 | /* If the reload regs aren't exactly the same (e.g, different modes) |
bb89c1cf | 6377 | or if the values are different, we can't merge this reload. |
6378 | But if it is an input reload, we might still merge | |
6379 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ | |
81d0fbb3 | 6380 | |
48666d2c | 6381 | if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) |
6382 | || rld[j].out != 0 || rld[j].in == 0 | |
6383 | || ! rtx_equal_p (rld[i].in, rld[j].in)) | |
bb89c1cf | 6384 | { |
48666d2c | 6385 | if (rld[j].when_needed != RELOAD_FOR_INPUT |
6386 | || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS | |
6387 | || rld[i].opnum > rld[j].opnum) | |
6388 | && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS)) | |
bb89c1cf | 6389 | break; |
6390 | conflicting_input = 1; | |
48666d2c | 6391 | if (min_conflicting_input_opnum > rld[j].opnum) |
6392 | min_conflicting_input_opnum = rld[j].opnum; | |
bb89c1cf | 6393 | } |
81d0fbb3 | 6394 | } |
6395 | ||
6396 | /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if | |
6397 | we, in fact, found any matching reloads. */ | |
6398 | ||
bb89c1cf | 6399 | if (j == n_reloads |
6400 | && max_input_address_opnum <= min_conflicting_input_opnum) | |
81d0fbb3 | 6401 | { |
535e833b | 6402 | gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT); |
6403 | ||
81d0fbb3 | 6404 | for (j = 0; j < n_reloads; j++) |
48666d2c | 6405 | if (i != j && rld[j].reg_rtx != 0 |
6406 | && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) | |
bb89c1cf | 6407 | && (! conflicting_input |
48666d2c | 6408 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6409 | || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
81d0fbb3 | 6410 | { |
48666d2c | 6411 | rld[i].when_needed = RELOAD_OTHER; |
6412 | rld[j].in = 0; | |
d70eda17 | 6413 | reload_spill_index[j] = -1; |
81d0fbb3 | 6414 | transfer_replacements (i, j); |
6415 | } | |
6416 | ||
d9f9327b | 6417 | /* If this is now RELOAD_OTHER, look for any reloads that |
6418 | load parts of this operand and set them to | |
6419 | RELOAD_FOR_OTHER_ADDRESS if they were for inputs, | |
6420 | RELOAD_OTHER for outputs. Note that this test is | |
6421 | equivalent to looking for reloads for this operand | |
6422 | number. | |
6423 | ||
6424 | We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; | |
6425 | it may share registers with a RELOAD_FOR_INPUT, so we can | |
6426 | not change it to RELOAD_FOR_OTHER_ADDRESS. We should | |
6427 | never need to, since we do not modify RELOAD_FOR_OUTPUT. | |
6428 | ||
6429 | It is possible that the RELOAD_FOR_OPERAND_ADDRESS | |
6430 | instruction is assigned the same register as the earlier | |
6431 | RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two | |
6432 | instructions will cause the RELOAD_FOR_OTHER_ADDRESS | |
6433 | instruction to be deleted later on. */ | |
81d0fbb3 | 6434 | |
48666d2c | 6435 | if (rld[i].when_needed == RELOAD_OTHER) |
81d0fbb3 | 6436 | for (j = 0; j < n_reloads; j++) |
48666d2c | 6437 | if (rld[j].in != 0 |
b59528b6 | 6438 | && rld[j].when_needed != RELOAD_OTHER |
a128fe75 | 6439 | && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS |
535e833b | 6440 | && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS |
d9f9327b | 6441 | && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS |
a128fe75 | 6442 | && (! conflicting_input |
6443 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
6444 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
48666d2c | 6445 | && reg_overlap_mentioned_for_reload_p (rld[j].in, |
6446 | rld[i].in)) | |
f5dd30a8 | 6447 | { |
6448 | int k; | |
6449 | ||
6450 | rld[j].when_needed | |
6451 | = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
6452 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
6453 | ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); | |
6454 | ||
1fa3a8f6 | 6455 | /* Check to see if we accidentally converted two |
6456 | reloads that use the same reload register with | |
6457 | different inputs to the same type. If so, the | |
6458 | resulting code won't work. */ | |
f5dd30a8 | 6459 | if (rld[j].reg_rtx) |
6460 | for (k = 0; k < j; k++) | |
04e579b6 | 6461 | gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0 |
6462 | || rld[k].when_needed != rld[j].when_needed | |
6463 | || !rtx_equal_p (rld[k].reg_rtx, | |
6464 | rld[j].reg_rtx) | |
6465 | || rtx_equal_p (rld[k].in, | |
6466 | rld[j].in)); | |
f5dd30a8 | 6467 | } |
81d0fbb3 | 6468 | } |
6469 | } | |
5bb2f919 | 6470 | } |
81d0fbb3 | 6471 | \f |
41c1545c | 6472 | /* These arrays are filled by emit_reload_insns and its subroutines. */ |
6473 | static rtx input_reload_insns[MAX_RECOG_OPERANDS]; | |
6474 | static rtx other_input_address_reload_insns = 0; | |
6475 | static rtx other_input_reload_insns = 0; | |
6476 | static rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6477 | static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6478 | static rtx output_reload_insns[MAX_RECOG_OPERANDS]; | |
6479 | static rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6480 | static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6481 | static rtx operand_reload_insns = 0; | |
6482 | static rtx other_operand_reload_insns = 0; | |
6483 | static rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; | |
6484 | ||
6485 | /* Values to be put in spill_reg_store are put here first. */ | |
6486 | static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
6487 | static HARD_REG_SET reg_reloaded_died; | |
6488 | ||
4d58fa46 | 6489 | /* Check if *RELOAD_REG is suitable as an intermediate or scratch register |
6490 | of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg | |
6491 | is nonzero, if that is suitable. On success, change *RELOAD_REG to the | |
6492 | adjusted register, and return true. Otherwise, return false. */ | |
6493 | static bool | |
6494 | reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg, | |
6495 | enum reg_class new_class, | |
6496 | enum machine_mode new_mode) | |
6497 | ||
6498 | { | |
6499 | rtx reg; | |
6500 | ||
6501 | for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0) | |
6502 | { | |
6503 | unsigned regno = REGNO (reg); | |
6504 | ||
6505 | if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno)) | |
6506 | continue; | |
6507 | if (GET_MODE (reg) != new_mode) | |
6508 | { | |
6509 | if (!HARD_REGNO_MODE_OK (regno, new_mode)) | |
6510 | continue; | |
6511 | if (hard_regno_nregs[regno][new_mode] | |
6512 | > hard_regno_nregs[regno][GET_MODE (reg)]) | |
6513 | continue; | |
6514 | reg = reload_adjust_reg_for_mode (reg, new_mode); | |
6515 | } | |
6516 | *reload_reg = reg; | |
6517 | return true; | |
6518 | } | |
6519 | return false; | |
6520 | } | |
6521 | ||
6522 | /* Check if *RELOAD_REG is suitable as a scratch register for the reload | |
6523 | pattern with insn_code ICODE, or alternatively, if alt_reload_reg is | |
6524 | nonzero, if that is suitable. On success, change *RELOAD_REG to the | |
6525 | adjusted register, and return true. Otherwise, return false. */ | |
6526 | static bool | |
6527 | reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg, | |
6528 | enum insn_code icode) | |
6529 | ||
6530 | { | |
6531 | enum reg_class new_class = scratch_reload_class (icode); | |
6532 | enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode; | |
6533 | ||
6534 | return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg, | |
6535 | new_class, new_mode); | |
6536 | } | |
6537 | ||
41c1545c | 6538 | /* Generate insns to perform reload RL, which is for the insn in CHAIN and |
6539 | has the number J. OLD contains the value to be used as input. */ | |
02e7a332 | 6540 | |
08a9dd06 | 6541 | static void |
3ad4992f | 6542 | emit_input_reload_insns (struct insn_chain *chain, struct reload *rl, |
6543 | rtx old, int j) | |
08a9dd06 | 6544 | { |
590ec786 | 6545 | rtx insn = chain->insn; |
19cb6b50 | 6546 | rtx reloadreg = rl->reg_rtx; |
41c1545c | 6547 | rtx oldequiv_reg = 0; |
6548 | rtx oldequiv = 0; | |
6549 | int special = 0; | |
6550 | enum machine_mode mode; | |
6551 | rtx *where; | |
6552 | ||
6553 | /* Determine the mode to reload in. | |
6554 | This is very tricky because we have three to choose from. | |
6555 | There is the mode the insn operand wants (rl->inmode). | |
6556 | There is the mode of the reload register RELOADREG. | |
6557 | There is the intrinsic mode of the operand, which we could find | |
6558 | by stripping some SUBREGs. | |
6559 | It turns out that RELOADREG's mode is irrelevant: | |
6560 | we can change that arbitrarily. | |
6561 | ||
6562 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
6563 | then the reload reg may not support QImode moves, so use SImode. | |
6564 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
6565 | because the QImode value is in the least significant part of a | |
6566 | slot big enough for a SImode. If foo is some other sort of | |
6567 | memory reference, then it is impossible to reload this case, | |
6568 | so previous passes had better make sure this never happens. | |
6569 | ||
6570 | Then consider a one-word union which has SImode and one of its | |
6571 | members is a float, being fetched as (SUBREG:SF union:SI). | |
6572 | We must fetch that as SFmode because we could be loading into | |
6573 | a float-only register. In this case OLD's mode is correct. | |
6574 | ||
6575 | Consider an immediate integer: it has VOIDmode. Here we need | |
6576 | to get a mode from something else. | |
6577 | ||
6578 | In some cases, there is a fourth mode, the operand's | |
6579 | containing mode. If the insn specifies a containing mode for | |
6580 | this operand, it overrides all others. | |
6581 | ||
6582 | I am not sure whether the algorithm here is always right, | |
6583 | but it does the right things in those cases. */ | |
6584 | ||
6585 | mode = GET_MODE (old); | |
6586 | if (mode == VOIDmode) | |
6587 | mode = rl->inmode; | |
590ec786 | 6588 | |
41c1545c | 6589 | /* delete_output_reload is only invoked properly if old contains |
6590 | the original pseudo register. Since this is replaced with a | |
6591 | hard reg when RELOAD_OVERRIDE_IN is set, see if we can | |
6592 | find the pseudo in RELOAD_IN_REG. */ | |
997a5633 | 6593 | if (reload_override_in[j] |
8ad4c111 | 6594 | && REG_P (rl->in_reg)) |
41c1545c | 6595 | { |
6596 | oldequiv = old; | |
6597 | old = rl->in_reg; | |
6598 | } | |
6599 | if (oldequiv == 0) | |
6600 | oldequiv = old; | |
8ad4c111 | 6601 | else if (REG_P (oldequiv)) |
41c1545c | 6602 | oldequiv_reg = oldequiv; |
6603 | else if (GET_CODE (oldequiv) == SUBREG) | |
6604 | oldequiv_reg = SUBREG_REG (oldequiv); | |
6605 | ||
6606 | /* If we are reloading from a register that was recently stored in | |
6607 | with an output-reload, see if we can prove there was | |
6608 | actually no need to store the old value in it. */ | |
6609 | ||
8ad4c111 | 6610 | if (optimize && REG_P (oldequiv) |
41c1545c | 6611 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER |
6612 | && spill_reg_store[REGNO (oldequiv)] | |
8ad4c111 | 6613 | && REG_P (old) |
41c1545c | 6614 | && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) |
6615 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6616 | rl->out_reg))) | |
6617 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6618 | ||
6619 | /* Encapsulate both RELOADREG and OLDEQUIV into that mode, | |
6620 | then load RELOADREG from OLDEQUIV. Note that we cannot use | |
6621 | gen_lowpart_common since it can do the wrong thing when | |
6622 | RELOADREG has a multi-word mode. Note that RELOADREG | |
6623 | must always be a REG here. */ | |
6624 | ||
6625 | if (GET_MODE (reloadreg) != mode) | |
fd3ac62f | 6626 | reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); |
41c1545c | 6627 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) |
6628 | oldequiv = SUBREG_REG (oldequiv); | |
6629 | if (GET_MODE (oldequiv) != VOIDmode | |
6630 | && mode != GET_MODE (oldequiv)) | |
701e46d0 | 6631 | oldequiv = gen_lowpart_SUBREG (mode, oldequiv); |
41c1545c | 6632 | |
6633 | /* Switch to the right place to emit the reload insns. */ | |
6634 | switch (rl->when_needed) | |
6635 | { | |
6636 | case RELOAD_OTHER: | |
6637 | where = &other_input_reload_insns; | |
6638 | break; | |
6639 | case RELOAD_FOR_INPUT: | |
6640 | where = &input_reload_insns[rl->opnum]; | |
6641 | break; | |
6642 | case RELOAD_FOR_INPUT_ADDRESS: | |
6643 | where = &input_address_reload_insns[rl->opnum]; | |
6644 | break; | |
6645 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6646 | where = &inpaddr_address_reload_insns[rl->opnum]; | |
6647 | break; | |
6648 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
6649 | where = &output_address_reload_insns[rl->opnum]; | |
6650 | break; | |
6651 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
6652 | where = &outaddr_address_reload_insns[rl->opnum]; | |
6653 | break; | |
6654 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6655 | where = &operand_reload_insns; | |
6656 | break; | |
6657 | case RELOAD_FOR_OPADDR_ADDR: | |
6658 | where = &other_operand_reload_insns; | |
6659 | break; | |
6660 | case RELOAD_FOR_OTHER_ADDRESS: | |
6661 | where = &other_input_address_reload_insns; | |
6662 | break; | |
6663 | default: | |
04e579b6 | 6664 | gcc_unreachable (); |
41c1545c | 6665 | } |
81d0fbb3 | 6666 | |
41c1545c | 6667 | push_to_sequence (*where); |
08a9dd06 | 6668 | |
41c1545c | 6669 | /* Auto-increment addresses must be reloaded in a special way. */ |
6670 | if (rl->out && ! rl->out_reg) | |
08a9dd06 | 6671 | { |
41c1545c | 6672 | /* We are not going to bother supporting the case where a |
6673 | incremented register can't be copied directly from | |
6674 | OLDEQUIV since this seems highly unlikely. */ | |
04e579b6 | 6675 | gcc_assert (rl->secondary_in_reload < 0); |
08a9dd06 | 6676 | |
41c1545c | 6677 | if (reload_inherited[j]) |
6678 | oldequiv = reloadreg; | |
93c7b06e | 6679 | |
41c1545c | 6680 | old = XEXP (rl->in_reg, 0); |
08a9dd06 | 6681 | |
8ad4c111 | 6682 | if (optimize && REG_P (oldequiv) |
41c1545c | 6683 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER |
6684 | && spill_reg_store[REGNO (oldequiv)] | |
8ad4c111 | 6685 | && REG_P (old) |
41c1545c | 6686 | && (dead_or_set_p (insn, |
6687 | spill_reg_stored_to[REGNO (oldequiv)]) | |
6688 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6689 | old))) | |
6690 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6691 | ||
6692 | /* Prevent normal processing of this reload. */ | |
6693 | special = 1; | |
6694 | /* Output a special code sequence for this case. */ | |
6695 | new_spill_reg_store[REGNO (reloadreg)] | |
6696 | = inc_for_reload (reloadreg, oldequiv, rl->out, | |
6697 | rl->inc); | |
6698 | } | |
08a9dd06 | 6699 | |
41c1545c | 6700 | /* If we are reloading a pseudo-register that was set by the previous |
6701 | insn, see if we can get rid of that pseudo-register entirely | |
6702 | by redirecting the previous insn into our reload register. */ | |
6703 | ||
8ad4c111 | 6704 | else if (optimize && REG_P (old) |
41c1545c | 6705 | && REGNO (old) >= FIRST_PSEUDO_REGISTER |
6706 | && dead_or_set_p (insn, old) | |
6707 | /* This is unsafe if some other reload | |
6708 | uses the same reg first. */ | |
b5083cca | 6709 | && ! conflicts_with_override (reloadreg) |
34b8be6b | 6710 | && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum, |
6711 | rl->when_needed, old, rl->out, j, 0)) | |
41c1545c | 6712 | { |
6713 | rtx temp = PREV_INSN (insn); | |
6d7dc5b9 | 6714 | while (temp && NOTE_P (temp)) |
41c1545c | 6715 | temp = PREV_INSN (temp); |
6716 | if (temp | |
6d7dc5b9 | 6717 | && NONJUMP_INSN_P (temp) |
41c1545c | 6718 | && GET_CODE (PATTERN (temp)) == SET |
6719 | && SET_DEST (PATTERN (temp)) == old | |
6720 | /* Make sure we can access insn_operand_constraint. */ | |
6721 | && asm_noperands (PATTERN (temp)) < 0 | |
41c1545c | 6722 | /* This is unsafe if operand occurs more than once in current |
6723 | insn. Perhaps some occurrences aren't reloaded. */ | |
51f6e244 | 6724 | && count_occurrences (PATTERN (insn), old, 0) == 1) |
41c1545c | 6725 | { |
51f6e244 | 6726 | rtx old = SET_DEST (PATTERN (temp)); |
41c1545c | 6727 | /* Store into the reload register instead of the pseudo. */ |
6728 | SET_DEST (PATTERN (temp)) = reloadreg; | |
6729 | ||
51f6e244 | 6730 | /* Verify that resulting insn is valid. */ |
6731 | extract_insn (temp); | |
6732 | if (constrain_operands (1)) | |
08a9dd06 | 6733 | { |
51f6e244 | 6734 | /* If the previous insn is an output reload, the source is |
6735 | a reload register, and its spill_reg_store entry will | |
6736 | contain the previous destination. This is now | |
6737 | invalid. */ | |
8ad4c111 | 6738 | if (REG_P (SET_SRC (PATTERN (temp))) |
51f6e244 | 6739 | && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) |
6740 | { | |
6741 | spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
6742 | spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
6743 | } | |
08a9dd06 | 6744 | |
51f6e244 | 6745 | /* If these are the only uses of the pseudo reg, |
6746 | pretend for GDB it lives in the reload reg we used. */ | |
6747 | if (REG_N_DEATHS (REGNO (old)) == 1 | |
6748 | && REG_N_SETS (REGNO (old)) == 1) | |
6749 | { | |
6750 | reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx); | |
6751 | alter_reg (REGNO (old), -1); | |
6752 | } | |
6753 | special = 1; | |
6754 | } | |
6755 | else | |
93c7b06e | 6756 | { |
51f6e244 | 6757 | SET_DEST (PATTERN (temp)) = old; |
08a9dd06 | 6758 | } |
41c1545c | 6759 | } |
6760 | } | |
08a9dd06 | 6761 | |
41c1545c | 6762 | /* We can't do that, so output an insn to load RELOADREG. */ |
08a9dd06 | 6763 | |
41c1545c | 6764 | /* If we have a secondary reload, pick up the secondary register |
6765 | and icode, if any. If OLDEQUIV and OLD are different or | |
6766 | if this is an in-out reload, recompute whether or not we | |
6767 | still need a secondary register and what the icode should | |
6768 | be. If we still need a secondary register and the class or | |
6769 | icode is different, go back to reloading from OLD if using | |
6770 | OLDEQUIV means that we got the wrong type of register. We | |
6771 | cannot have different class or icode due to an in-out reload | |
6772 | because we don't make such reloads when both the input and | |
6773 | output need secondary reload registers. */ | |
6774 | ||
f192c4ac | 6775 | if (! special && rl->secondary_in_reload >= 0) |
41c1545c | 6776 | { |
6777 | rtx second_reload_reg = 0; | |
4d58fa46 | 6778 | rtx third_reload_reg = 0; |
41c1545c | 6779 | int secondary_reload = rl->secondary_in_reload; |
6780 | rtx real_oldequiv = oldequiv; | |
6781 | rtx real_old = old; | |
6782 | rtx tmp; | |
6783 | enum insn_code icode; | |
4d58fa46 | 6784 | enum insn_code tertiary_icode = CODE_FOR_nothing; |
41c1545c | 6785 | |
6786 | /* If OLDEQUIV is a pseudo with a MEM, get the real MEM | |
6787 | and similarly for OLD. | |
6788 | See comments in get_secondary_reload in reload.c. */ | |
6789 | /* If it is a pseudo that cannot be replaced with its | |
6790 | equivalent MEM, we must fall back to reload_in, which | |
6791 | will have all the necessary substitutions registered. | |
6792 | Likewise for a pseudo that can't be replaced with its | |
6793 | equivalent constant. | |
6794 | ||
6795 | Take extra care for subregs of such pseudos. Note that | |
6796 | we cannot use reg_equiv_mem in this case because it is | |
6797 | not in the right mode. */ | |
6798 | ||
6799 | tmp = oldequiv; | |
6800 | if (GET_CODE (tmp) == SUBREG) | |
6801 | tmp = SUBREG_REG (tmp); | |
8ad4c111 | 6802 | if (REG_P (tmp) |
41c1545c | 6803 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER |
6804 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6805 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6806 | { | |
6807 | if (! reg_equiv_mem[REGNO (tmp)] | |
6808 | || num_not_at_initial_offset | |
6809 | || GET_CODE (oldequiv) == SUBREG) | |
6810 | real_oldequiv = rl->in; | |
6811 | else | |
6812 | real_oldequiv = reg_equiv_mem[REGNO (tmp)]; | |
6813 | } | |
08a9dd06 | 6814 | |
41c1545c | 6815 | tmp = old; |
6816 | if (GET_CODE (tmp) == SUBREG) | |
6817 | tmp = SUBREG_REG (tmp); | |
8ad4c111 | 6818 | if (REG_P (tmp) |
41c1545c | 6819 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER |
6820 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6821 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6822 | { | |
6823 | if (! reg_equiv_mem[REGNO (tmp)] | |
6824 | || num_not_at_initial_offset | |
6825 | || GET_CODE (old) == SUBREG) | |
6826 | real_old = rl->in; | |
6827 | else | |
6828 | real_old = reg_equiv_mem[REGNO (tmp)]; | |
6829 | } | |
6830 | ||
6831 | second_reload_reg = rld[secondary_reload].reg_rtx; | |
4d58fa46 | 6832 | if (rld[secondary_reload].secondary_in_reload >= 0) |
6833 | { | |
6834 | int tertiary_reload = rld[secondary_reload].secondary_in_reload; | |
6835 | ||
6836 | third_reload_reg = rld[tertiary_reload].reg_rtx; | |
6837 | tertiary_icode = rld[secondary_reload].secondary_in_icode; | |
6838 | /* We'd have to add more code for quartary reloads. */ | |
6839 | gcc_assert (rld[tertiary_reload].secondary_in_reload < 0); | |
6840 | } | |
41c1545c | 6841 | icode = rl->secondary_in_icode; |
6842 | ||
6843 | if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) | |
6844 | || (rl->in != 0 && rl->out != 0)) | |
6845 | { | |
4d58fa46 | 6846 | secondary_reload_info sri, sri2; |
6847 | enum reg_class new_class, new_t_class; | |
41c1545c | 6848 | |
4d58fa46 | 6849 | sri.icode = CODE_FOR_nothing; |
6850 | sri.prev_sri = NULL; | |
6851 | new_class = targetm.secondary_reload (1, real_oldequiv, rl->class, | |
6852 | mode, &sri); | |
6853 | ||
6854 | if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
41c1545c | 6855 | second_reload_reg = 0; |
4d58fa46 | 6856 | else if (new_class == NO_REGS) |
08a9dd06 | 6857 | { |
4d58fa46 | 6858 | if (reload_adjust_reg_for_icode (&second_reload_reg, |
6859 | third_reload_reg, sri.icode)) | |
6860 | icode = sri.icode, third_reload_reg = 0; | |
41c1545c | 6861 | else |
4d58fa46 | 6862 | oldequiv = old, real_oldequiv = real_old; |
6863 | } | |
6864 | else if (sri.icode != CODE_FOR_nothing) | |
6865 | /* We currently lack a way to express this in reloads. */ | |
6866 | gcc_unreachable (); | |
6867 | else | |
6868 | { | |
6869 | sri2.icode = CODE_FOR_nothing; | |
6870 | sri2.prev_sri = &sri; | |
6871 | new_t_class = targetm.secondary_reload (1, real_oldequiv, | |
6872 | new_class, mode, &sri); | |
6873 | if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing) | |
08a9dd06 | 6874 | { |
4d58fa46 | 6875 | if (reload_adjust_reg_for_temp (&second_reload_reg, |
6876 | third_reload_reg, | |
6877 | new_class, mode)) | |
6878 | third_reload_reg = 0, tertiary_icode = sri2.icode; | |
41c1545c | 6879 | else |
4d58fa46 | 6880 | oldequiv = old, real_oldequiv = real_old; |
6881 | } | |
6882 | else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing) | |
6883 | { | |
6884 | rtx intermediate = second_reload_reg; | |
68fe1709 | 6885 | |
4d58fa46 | 6886 | if (reload_adjust_reg_for_temp (&intermediate, NULL, |
6887 | new_class, mode) | |
6888 | && reload_adjust_reg_for_icode (&third_reload_reg, NULL, | |
6889 | sri2.icode)) | |
08a9dd06 | 6890 | { |
4d58fa46 | 6891 | second_reload_reg = intermediate; |
6892 | tertiary_icode = sri2.icode; | |
6893 | } | |
6894 | else | |
6895 | oldequiv = old, real_oldequiv = real_old; | |
6896 | } | |
6897 | else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing) | |
6898 | { | |
6899 | rtx intermediate = second_reload_reg; | |
6900 | ||
6901 | if (reload_adjust_reg_for_temp (&intermediate, NULL, | |
6902 | new_class, mode) | |
6903 | && reload_adjust_reg_for_temp (&third_reload_reg, NULL, | |
6904 | new_t_class, mode)) | |
6905 | { | |
6906 | second_reload_reg = intermediate; | |
6907 | tertiary_icode = sri2.icode; | |
08a9dd06 | 6908 | } |
4d58fa46 | 6909 | else |
6910 | oldequiv = old, real_oldequiv = real_old; | |
08a9dd06 | 6911 | } |
4d58fa46 | 6912 | else |
6913 | /* This could be handled more intelligently too. */ | |
6914 | oldequiv = old, real_oldequiv = real_old; | |
08a9dd06 | 6915 | } |
41c1545c | 6916 | } |
08a9dd06 | 6917 | |
41c1545c | 6918 | /* If we still need a secondary reload register, check |
6919 | to see if it is being used as a scratch or intermediate | |
6920 | register and generate code appropriately. If we need | |
6921 | a scratch register, use REAL_OLDEQUIV since the form of | |
6922 | the insn may depend on the actual address if it is | |
6923 | a MEM. */ | |
81d0fbb3 | 6924 | |
41c1545c | 6925 | if (second_reload_reg) |
6926 | { | |
6927 | if (icode != CODE_FOR_nothing) | |
08a9dd06 | 6928 | { |
4d58fa46 | 6929 | /* We'd have to add extra code to handle this case. */ |
6930 | gcc_assert (!third_reload_reg); | |
6931 | ||
41c1545c | 6932 | emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, |
6933 | second_reload_reg)); | |
f192c4ac | 6934 | special = 1; |
41c1545c | 6935 | } |
6936 | else | |
6937 | { | |
6938 | /* See if we need a scratch register to load the | |
6939 | intermediate register (a tertiary reload). */ | |
41c1545c | 6940 | if (tertiary_icode != CODE_FOR_nothing) |
6941 | { | |
41c1545c | 6942 | emit_insn ((GEN_FCN (tertiary_icode) |
6943 | (second_reload_reg, real_oldequiv, | |
6944 | third_reload_reg))); | |
6945 | } | |
4d58fa46 | 6946 | else if (third_reload_reg) |
6947 | { | |
6948 | gen_reload (third_reload_reg, real_oldequiv, | |
6949 | rl->opnum, | |
6950 | rl->when_needed); | |
6951 | gen_reload (second_reload_reg, third_reload_reg, | |
6952 | rl->opnum, | |
6953 | rl->when_needed); | |
6954 | } | |
41c1545c | 6955 | else |
6956 | gen_reload (second_reload_reg, real_oldequiv, | |
6957 | rl->opnum, | |
6958 | rl->when_needed); | |
08a9dd06 | 6959 | |
41c1545c | 6960 | oldequiv = second_reload_reg; |
6961 | } | |
6962 | } | |
6963 | } | |
08a9dd06 | 6964 | |
f192c4ac | 6965 | if (! special && ! rtx_equal_p (reloadreg, oldequiv)) |
41c1545c | 6966 | { |
6967 | rtx real_oldequiv = oldequiv; | |
6968 | ||
8ad4c111 | 6969 | if ((REG_P (oldequiv) |
41c1545c | 6970 | && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER |
6971 | && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 | |
6972 | || reg_equiv_constant[REGNO (oldequiv)] != 0)) | |
6973 | || (GET_CODE (oldequiv) == SUBREG | |
8ad4c111 | 6974 | && REG_P (SUBREG_REG (oldequiv)) |
41c1545c | 6975 | && (REGNO (SUBREG_REG (oldequiv)) |
6976 | >= FIRST_PSEUDO_REGISTER) | |
6977 | && ((reg_equiv_memory_loc | |
6978 | [REGNO (SUBREG_REG (oldequiv))] != 0) | |
6979 | || (reg_equiv_constant | |
af9687ec | 6980 | [REGNO (SUBREG_REG (oldequiv))] != 0))) |
6981 | || (CONSTANT_P (oldequiv) | |
d63f5e12 | 6982 | && (PREFERRED_RELOAD_CLASS (oldequiv, |
6983 | REGNO_REG_CLASS (REGNO (reloadreg))) | |
6984 | == NO_REGS))) | |
41c1545c | 6985 | real_oldequiv = rl->in; |
6986 | gen_reload (reloadreg, real_oldequiv, rl->opnum, | |
6987 | rl->when_needed); | |
6988 | } | |
08a9dd06 | 6989 | |
d8c23d3f | 6990 | if (flag_non_call_exceptions) |
6991 | copy_eh_notes (insn, get_insns ()); | |
6992 | ||
41c1545c | 6993 | /* End this sequence. */ |
6994 | *where = get_insns (); | |
6995 | end_sequence (); | |
2617fe26 | 6996 | |
41c1545c | 6997 | /* Update reload_override_in so that delete_address_reloads_1 |
6998 | can see the actual register usage. */ | |
6999 | if (oldequiv_reg) | |
7000 | reload_override_in[j] = oldequiv; | |
7001 | } | |
08a9dd06 | 7002 | |
41c1545c | 7003 | /* Generate insns to for the output reload RL, which is for the insn described |
7004 | by CHAIN and has the number J. */ | |
7005 | static void | |
3ad4992f | 7006 | emit_output_reload_insns (struct insn_chain *chain, struct reload *rl, |
7007 | int j) | |
41c1545c | 7008 | { |
7009 | rtx reloadreg = rl->reg_rtx; | |
7010 | rtx insn = chain->insn; | |
7011 | int special = 0; | |
7012 | rtx old = rl->out; | |
7013 | enum machine_mode mode = GET_MODE (old); | |
7014 | rtx p; | |
08a9dd06 | 7015 | |
41c1545c | 7016 | if (rl->when_needed == RELOAD_OTHER) |
7017 | start_sequence (); | |
7018 | else | |
7019 | push_to_sequence (output_reload_insns[rl->opnum]); | |
08a9dd06 | 7020 | |
41c1545c | 7021 | /* Determine the mode to reload in. |
7022 | See comments above (for input reloading). */ | |
08a9dd06 | 7023 | |
41c1545c | 7024 | if (mode == VOIDmode) |
7025 | { | |
7026 | /* VOIDmode should never happen for an output. */ | |
7027 | if (asm_noperands (PATTERN (insn)) < 0) | |
7028 | /* It's the compiler's fault. */ | |
7029 | fatal_insn ("VOIDmode on an output", insn); | |
eb586f2c | 7030 | error_for_asm (insn, "output operand is constant in %<asm%>"); |
41c1545c | 7031 | /* Prevent crash--use something we know is valid. */ |
7032 | mode = word_mode; | |
7033 | old = gen_rtx_REG (mode, REGNO (reloadreg)); | |
7034 | } | |
81d0fbb3 | 7035 | |
41c1545c | 7036 | if (GET_MODE (reloadreg) != mode) |
fd3ac62f | 7037 | reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); |
08a9dd06 | 7038 | |
41c1545c | 7039 | /* If we need two reload regs, set RELOADREG to the intermediate |
7040 | one, since it will be stored into OLD. We might need a secondary | |
7041 | register only for an input reload, so check again here. */ | |
08a9dd06 | 7042 | |
41c1545c | 7043 | if (rl->secondary_out_reload >= 0) |
7044 | { | |
7045 | rtx real_old = old; | |
4d58fa46 | 7046 | int secondary_reload = rl->secondary_out_reload; |
7047 | int tertiary_reload = rld[secondary_reload].secondary_out_reload; | |
93c7b06e | 7048 | |
8ad4c111 | 7049 | if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER |
41c1545c | 7050 | && reg_equiv_mem[REGNO (old)] != 0) |
7051 | real_old = reg_equiv_mem[REGNO (old)]; | |
08a9dd06 | 7052 | |
4d58fa46 | 7053 | if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS) |
6aed5e78 | 7054 | { |
41c1545c | 7055 | rtx second_reloadreg = reloadreg; |
4d58fa46 | 7056 | reloadreg = rld[secondary_reload].reg_rtx; |
08a9dd06 | 7057 | |
41c1545c | 7058 | /* See if RELOADREG is to be used as a scratch register |
7059 | or as an intermediate register. */ | |
7060 | if (rl->secondary_out_icode != CODE_FOR_nothing) | |
7061 | { | |
4d58fa46 | 7062 | /* We'd have to add extra code to handle this case. */ |
7063 | gcc_assert (tertiary_reload < 0); | |
7064 | ||
41c1545c | 7065 | emit_insn ((GEN_FCN (rl->secondary_out_icode) |
7066 | (real_old, second_reloadreg, reloadreg))); | |
7067 | special = 1; | |
7068 | } | |
7069 | else | |
7070 | { | |
7071 | /* See if we need both a scratch and intermediate reload | |
7072 | register. */ | |
08a9dd06 | 7073 | |
41c1545c | 7074 | enum insn_code tertiary_icode |
7075 | = rld[secondary_reload].secondary_out_icode; | |
08a9dd06 | 7076 | |
4d58fa46 | 7077 | /* We'd have to add more code for quartary reloads. */ |
7078 | gcc_assert (tertiary_reload < 0 | |
7079 | || rld[tertiary_reload].secondary_out_reload < 0); | |
7080 | ||
41c1545c | 7081 | if (GET_MODE (reloadreg) != mode) |
fd3ac62f | 7082 | reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); |
93c7b06e | 7083 | |
41c1545c | 7084 | if (tertiary_icode != CODE_FOR_nothing) |
7085 | { | |
4d58fa46 | 7086 | rtx third_reloadreg = rld[tertiary_reload].reg_rtx; |
41c1545c | 7087 | rtx tem; |
7088 | ||
7089 | /* Copy primary reload reg to secondary reload reg. | |
7090 | (Note that these have been swapped above, then | |
d8d6496b | 7091 | secondary reload reg to OLD using our insn.) */ |
41c1545c | 7092 | |
7093 | /* If REAL_OLD is a paradoxical SUBREG, remove it | |
7094 | and try to put the opposite SUBREG on | |
7095 | RELOADREG. */ | |
7096 | if (GET_CODE (real_old) == SUBREG | |
7097 | && (GET_MODE_SIZE (GET_MODE (real_old)) | |
7098 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) | |
7099 | && 0 != (tem = gen_lowpart_common | |
7100 | (GET_MODE (SUBREG_REG (real_old)), | |
7101 | reloadreg))) | |
7102 | real_old = SUBREG_REG (real_old), reloadreg = tem; | |
7103 | ||
7104 | gen_reload (reloadreg, second_reloadreg, | |
7105 | rl->opnum, rl->when_needed); | |
7106 | emit_insn ((GEN_FCN (tertiary_icode) | |
7107 | (real_old, reloadreg, third_reloadreg))); | |
7108 | special = 1; | |
7109 | } | |
5bb2f919 | 7110 | |
41c1545c | 7111 | else |
4d58fa46 | 7112 | { |
7113 | /* Copy between the reload regs here and then to | |
7114 | OUT later. */ | |
7115 | ||
7116 | gen_reload (reloadreg, second_reloadreg, | |
7117 | rl->opnum, rl->when_needed); | |
7118 | if (tertiary_reload >= 0) | |
7119 | { | |
7120 | rtx third_reloadreg = rld[tertiary_reload].reg_rtx; | |
93c7b06e | 7121 | |
4d58fa46 | 7122 | gen_reload (third_reloadreg, reloadreg, |
7123 | rl->opnum, rl->when_needed); | |
7124 | reloadreg = third_reloadreg; | |
7125 | } | |
7126 | } | |
fa9351ee | 7127 | } |
41c1545c | 7128 | } |
7129 | } | |
08a9dd06 | 7130 | |
41c1545c | 7131 | /* Output the last reload insn. */ |
7132 | if (! special) | |
7133 | { | |
7134 | rtx set; | |
7135 | ||
7136 | /* Don't output the last reload if OLD is not the dest of | |
aedd3e94 | 7137 | INSN and is in the src and is clobbered by INSN. */ |
41c1545c | 7138 | if (! flag_expensive_optimizations |
8ad4c111 | 7139 | || !REG_P (old) |
41c1545c | 7140 | || !(set = single_set (insn)) |
7141 | || rtx_equal_p (old, SET_DEST (set)) | |
7142 | || !reg_mentioned_p (old, SET_SRC (set)) | |
2f59f8b2 | 7143 | || !((REGNO (old) < FIRST_PSEUDO_REGISTER) |
7144 | && regno_clobbered_p (REGNO (old), insn, rl->mode, 0))) | |
41c1545c | 7145 | gen_reload (old, reloadreg, rl->opnum, |
7146 | rl->when_needed); | |
7147 | } | |
08a9dd06 | 7148 | |
41c1545c | 7149 | /* Look at all insns we emitted, just to be safe. */ |
7150 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
9204e736 | 7151 | if (INSN_P (p)) |
41c1545c | 7152 | { |
7153 | rtx pat = PATTERN (p); | |
81d0fbb3 | 7154 | |
41c1545c | 7155 | /* If this output reload doesn't come from a spill reg, |
7156 | clear any memory of reloaded copies of the pseudo reg. | |
7157 | If this output reload comes from a spill reg, | |
7158 | reg_has_output_reload will make this do nothing. */ | |
7159 | note_stores (pat, forget_old_reloads_1, NULL); | |
93c7b06e | 7160 | |
41c1545c | 7161 | if (reg_mentioned_p (rl->reg_rtx, pat)) |
7162 | { | |
7163 | rtx set = single_set (insn); | |
7164 | if (reload_spill_index[j] < 0 | |
7165 | && set | |
7166 | && SET_SRC (set) == rl->reg_rtx) | |
7167 | { | |
7168 | int src = REGNO (SET_SRC (set)); | |
08a9dd06 | 7169 | |
41c1545c | 7170 | reload_spill_index[j] = src; |
7171 | SET_HARD_REG_BIT (reg_is_output_reload, src); | |
7172 | if (find_regno_note (insn, REG_DEAD, src)) | |
7173 | SET_HARD_REG_BIT (reg_reloaded_died, src); | |
7174 | } | |
7175 | if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER) | |
7176 | { | |
7177 | int s = rl->secondary_out_reload; | |
7178 | set = single_set (p); | |
7179 | /* If this reload copies only to the secondary reload | |
7180 | register, the secondary reload does the actual | |
7181 | store. */ | |
7182 | if (s >= 0 && set == NULL_RTX) | |
aedd3e94 | 7183 | /* We can't tell what function the secondary reload |
7184 | has and where the actual store to the pseudo is | |
7185 | made; leave new_spill_reg_store alone. */ | |
7186 | ; | |
41c1545c | 7187 | else if (s >= 0 |
7188 | && SET_SRC (set) == rl->reg_rtx | |
7189 | && SET_DEST (set) == rld[s].reg_rtx) | |
7190 | { | |
7191 | /* Usually the next instruction will be the | |
7192 | secondary reload insn; if we can confirm | |
7193 | that it is, setting new_spill_reg_store to | |
7194 | that insn will allow an extra optimization. */ | |
7195 | rtx s_reg = rld[s].reg_rtx; | |
7196 | rtx next = NEXT_INSN (p); | |
7197 | rld[s].out = rl->out; | |
7198 | rld[s].out_reg = rl->out_reg; | |
7199 | set = single_set (next); | |
7200 | if (set && SET_SRC (set) == s_reg | |
7201 | && ! new_spill_reg_store[REGNO (s_reg)]) | |
7202 | { | |
7203 | SET_HARD_REG_BIT (reg_is_output_reload, | |
7204 | REGNO (s_reg)); | |
7205 | new_spill_reg_store[REGNO (s_reg)] = next; | |
7206 | } | |
7207 | } | |
7208 | else | |
7209 | new_spill_reg_store[REGNO (rl->reg_rtx)] = p; | |
7210 | } | |
7211 | } | |
7212 | } | |
08a9dd06 | 7213 | |
41c1545c | 7214 | if (rl->when_needed == RELOAD_OTHER) |
7215 | { | |
31d3e01c | 7216 | emit_insn (other_output_reload_insns[rl->opnum]); |
41c1545c | 7217 | other_output_reload_insns[rl->opnum] = get_insns (); |
7218 | } | |
7219 | else | |
7220 | output_reload_insns[rl->opnum] = get_insns (); | |
08a9dd06 | 7221 | |
d8c23d3f | 7222 | if (flag_non_call_exceptions) |
7223 | copy_eh_notes (insn, get_insns ()); | |
7224 | ||
aedd3e94 | 7225 | end_sequence (); |
41c1545c | 7226 | } |
08a9dd06 | 7227 | |
41c1545c | 7228 | /* Do input reloading for reload RL, which is for the insn described by CHAIN |
7229 | and has the number J. */ | |
7230 | static void | |
3ad4992f | 7231 | do_input_reload (struct insn_chain *chain, struct reload *rl, int j) |
41c1545c | 7232 | { |
41c1545c | 7233 | rtx insn = chain->insn; |
e16ceb8e | 7234 | rtx old = (rl->in && MEM_P (rl->in) |
41c1545c | 7235 | ? rl->in_reg : rl->in); |
7236 | ||
7237 | if (old != 0 | |
7238 | /* AUTO_INC reloads need to be handled even if inherited. We got an | |
7239 | AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ | |
7240 | && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) | |
7241 | && ! rtx_equal_p (rl->reg_rtx, old) | |
7242 | && rl->reg_rtx != 0) | |
dccf4eb3 | 7243 | emit_input_reload_insns (chain, rld + j, old, j); |
08a9dd06 | 7244 | |
41c1545c | 7245 | /* When inheriting a wider reload, we have a MEM in rl->in, |
7246 | e.g. inheriting a SImode output reload for | |
7247 | (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ | |
7248 | if (optimize && reload_inherited[j] && rl->in | |
e16ceb8e | 7249 | && MEM_P (rl->in) |
7250 | && MEM_P (rl->in_reg) | |
41c1545c | 7251 | && reload_spill_index[j] >= 0 |
7252 | && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) | |
805e22b2 | 7253 | rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; |
08a9dd06 | 7254 | |
41c1545c | 7255 | /* If we are reloading a register that was recently stored in with an |
7256 | output-reload, see if we can prove there was | |
7257 | actually no need to store the old value in it. */ | |
08a9dd06 | 7258 | |
41c1545c | 7259 | if (optimize |
7260 | && (reload_inherited[j] || reload_override_in[j]) | |
7261 | && rl->reg_rtx | |
8ad4c111 | 7262 | && REG_P (rl->reg_rtx) |
41c1545c | 7263 | && spill_reg_store[REGNO (rl->reg_rtx)] != 0 |
7264 | #if 0 | |
7265 | /* There doesn't seem to be any reason to restrict this to pseudos | |
7266 | and doing so loses in the case where we are copying from a | |
7267 | register of the wrong class. */ | |
7268 | && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
7269 | >= FIRST_PSEUDO_REGISTER) | |
7270 | #endif | |
7271 | /* The insn might have already some references to stackslots | |
7272 | replaced by MEMs, while reload_out_reg still names the | |
7273 | original pseudo. */ | |
7274 | && (dead_or_set_p (insn, | |
7275 | spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
7276 | || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], | |
7277 | rl->out_reg))) | |
7278 | delete_output_reload (insn, j, REGNO (rl->reg_rtx)); | |
7279 | } | |
08a9dd06 | 7280 | |
41c1545c | 7281 | /* Do output reloading for reload RL, which is for the insn described by |
7282 | CHAIN and has the number J. | |
7283 | ??? At some point we need to support handling output reloads of | |
7284 | JUMP_INSNs or insns that set cc0. */ | |
7285 | static void | |
3ad4992f | 7286 | do_output_reload (struct insn_chain *chain, struct reload *rl, int j) |
41c1545c | 7287 | { |
7288 | rtx note, old; | |
7289 | rtx insn = chain->insn; | |
7290 | /* If this is an output reload that stores something that is | |
7291 | not loaded in this same reload, see if we can eliminate a previous | |
7292 | store. */ | |
7293 | rtx pseudo = rl->out_reg; | |
7294 | ||
7295 | if (pseudo | |
752fbe10 | 7296 | && optimize |
8ad4c111 | 7297 | && REG_P (pseudo) |
41c1545c | 7298 | && ! rtx_equal_p (rl->in_reg, pseudo) |
7299 | && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER | |
7300 | && reg_last_reload_reg[REGNO (pseudo)]) | |
7301 | { | |
7302 | int pseudo_no = REGNO (pseudo); | |
7303 | int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); | |
7304 | ||
7305 | /* We don't need to test full validity of last_regno for | |
7306 | inherit here; we only want to know if the store actually | |
7307 | matches the pseudo. */ | |
e46bd117 | 7308 | if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno) |
7309 | && reg_reloaded_contents[last_regno] == pseudo_no | |
41c1545c | 7310 | && spill_reg_store[last_regno] |
7311 | && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) | |
7312 | delete_output_reload (insn, j, last_regno); | |
7313 | } | |
b6fdd226 | 7314 | |
41c1545c | 7315 | old = rl->out_reg; |
7316 | if (old == 0 | |
7317 | || rl->reg_rtx == old | |
7318 | || rl->reg_rtx == 0) | |
7319 | return; | |
08a9dd06 | 7320 | |
41c1545c | 7321 | /* An output operand that dies right away does need a reload, |
7322 | but need not be copied from it. Show the new location in the | |
7323 | REG_UNUSED note. */ | |
8ad4c111 | 7324 | if ((REG_P (old) || GET_CODE (old) == SCRATCH) |
41c1545c | 7325 | && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) |
7326 | { | |
7327 | XEXP (note, 0) = rl->reg_rtx; | |
7328 | return; | |
7329 | } | |
7330 | /* Likewise for a SUBREG of an operand that dies. */ | |
7331 | else if (GET_CODE (old) == SUBREG | |
8ad4c111 | 7332 | && REG_P (SUBREG_REG (old)) |
41c1545c | 7333 | && 0 != (note = find_reg_note (insn, REG_UNUSED, |
7334 | SUBREG_REG (old)))) | |
7335 | { | |
7336 | XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), | |
7337 | rl->reg_rtx); | |
7338 | return; | |
7339 | } | |
7340 | else if (GET_CODE (old) == SCRATCH) | |
7341 | /* If we aren't optimizing, there won't be a REG_UNUSED note, | |
7342 | but we don't want to make an output reload. */ | |
7343 | return; | |
3a875c6b | 7344 | |
41c1545c | 7345 | /* If is a JUMP_INSN, we can't support output reloads yet. */ |
caeb1224 | 7346 | gcc_assert (NONJUMP_INSN_P (insn)); |
b6fdd226 | 7347 | |
41c1545c | 7348 | emit_output_reload_insns (chain, rld + j, j); |
7349 | } | |
3a875c6b | 7350 | |
9318b368 | 7351 | /* Reload number R reloads from or to a group of hard registers starting at |
7352 | register REGNO. Return true if it can be treated for inheritance purposes | |
7353 | like a group of reloads, each one reloading a single hard register. | |
7354 | The caller has already checked that the spill register and REGNO use | |
7355 | the same number of registers to store the reload value. */ | |
7356 | ||
7357 | static bool | |
b7f56370 | 7358 | inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED) |
9318b368 | 7359 | { |
7360 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
7361 | return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r], | |
7362 | GET_MODE (rld[r].reg_rtx), | |
7363 | reg_raw_mode[reload_spill_index[r]]) | |
7364 | && !REG_CANNOT_CHANGE_MODE_P (regno, | |
7365 | GET_MODE (rld[r].reg_rtx), | |
7366 | reg_raw_mode[regno])); | |
7367 | #else | |
7368 | return true; | |
7369 | #endif | |
7370 | } | |
7371 | ||
41c1545c | 7372 | /* Output insns to reload values in and out of the chosen reload regs. */ |
08a9dd06 | 7373 | |
41c1545c | 7374 | static void |
3ad4992f | 7375 | emit_reload_insns (struct insn_chain *chain) |
41c1545c | 7376 | { |
7377 | rtx insn = chain->insn; | |
08a9dd06 | 7378 | |
19cb6b50 | 7379 | int j; |
a5e95c30 | 7380 | |
41c1545c | 7381 | CLEAR_HARD_REG_SET (reg_reloaded_died); |
a5e95c30 | 7382 | |
41c1545c | 7383 | for (j = 0; j < reload_n_operands; j++) |
7384 | input_reload_insns[j] = input_address_reload_insns[j] | |
7385 | = inpaddr_address_reload_insns[j] | |
7386 | = output_reload_insns[j] = output_address_reload_insns[j] | |
7387 | = outaddr_address_reload_insns[j] | |
7388 | = other_output_reload_insns[j] = 0; | |
7389 | other_input_address_reload_insns = 0; | |
7390 | other_input_reload_insns = 0; | |
7391 | operand_reload_insns = 0; | |
7392 | other_operand_reload_insns = 0; | |
08a9dd06 | 7393 | |
f0d643fd | 7394 | /* Dump reloads into the dump file. */ |
450d042a | 7395 | if (dump_file) |
f0d643fd | 7396 | { |
450d042a | 7397 | fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); |
7398 | debug_reload_to_stream (dump_file); | |
f0d643fd | 7399 | } |
7400 | ||
41c1545c | 7401 | /* Now output the instructions to copy the data into and out of the |
7402 | reload registers. Do these in the order that the reloads were reported, | |
7403 | since reloads of base and index registers precede reloads of operands | |
7404 | and the operands may need the base and index registers reloaded. */ | |
08a9dd06 | 7405 | |
41c1545c | 7406 | for (j = 0; j < n_reloads; j++) |
7407 | { | |
7408 | if (rld[j].reg_rtx | |
7409 | && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER) | |
7410 | new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0; | |
a43b19e2 | 7411 | |
41c1545c | 7412 | do_input_reload (chain, rld + j, j); |
7413 | do_output_reload (chain, rld + j, j); | |
08a9dd06 | 7414 | } |
7415 | ||
81d0fbb3 | 7416 | /* Now write all the insns we made for reloads in the order expected by |
7417 | the allocation functions. Prior to the insn being reloaded, we write | |
7418 | the following reloads: | |
7419 | ||
7420 | RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. | |
7421 | ||
8fa27ffb | 7422 | RELOAD_OTHER reloads. |
81d0fbb3 | 7423 | |
9e53d777 | 7424 | For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed |
7425 | by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the | |
7426 | RELOAD_FOR_INPUT reload for the operand. | |
81d0fbb3 | 7427 | |
58866c2c | 7428 | RELOAD_FOR_OPADDR_ADDRS reloads. |
7429 | ||
81d0fbb3 | 7430 | RELOAD_FOR_OPERAND_ADDRESS reloads. |
7431 | ||
7432 | After the insn being reloaded, we write the following: | |
7433 | ||
9e53d777 | 7434 | For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed |
7435 | by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the | |
7436 | RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output | |
7437 | reloads for the operand. The RELOAD_OTHER output reloads are | |
7438 | output in descending order by reload number. */ | |
81d0fbb3 | 7439 | |
0891f67c | 7440 | emit_insn_before (other_input_address_reload_insns, insn); |
7441 | emit_insn_before (other_input_reload_insns, insn); | |
81d0fbb3 | 7442 | |
7443 | for (j = 0; j < reload_n_operands; j++) | |
7444 | { | |
0891f67c | 7445 | emit_insn_before (inpaddr_address_reload_insns[j], insn); |
7446 | emit_insn_before (input_address_reload_insns[j], insn); | |
7447 | emit_insn_before (input_reload_insns[j], insn); | |
81d0fbb3 | 7448 | } |
7449 | ||
0891f67c | 7450 | emit_insn_before (other_operand_reload_insns, insn); |
7451 | emit_insn_before (operand_reload_insns, insn); | |
81d0fbb3 | 7452 | |
7453 | for (j = 0; j < reload_n_operands; j++) | |
7454 | { | |
0891f67c | 7455 | rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn); |
7456 | x = emit_insn_after (output_address_reload_insns[j], x); | |
7457 | x = emit_insn_after (output_reload_insns[j], x); | |
7458 | emit_insn_after (other_output_reload_insns[j], x); | |
81d0fbb3 | 7459 | } |
7460 | ||
08a9dd06 | 7461 | /* For all the spill regs newly reloaded in this instruction, |
7462 | record what they were reloaded from, so subsequent instructions | |
497de2d4 | 7463 | can inherit the reloads. |
7464 | ||
7465 | Update spill_reg_store for the reloads of this insn. | |
d9999eba | 7466 | Copy the elements that were updated in the loop above. */ |
08a9dd06 | 7467 | |
7468 | for (j = 0; j < n_reloads; j++) | |
7469 | { | |
19cb6b50 | 7470 | int r = reload_order[j]; |
7471 | int i = reload_spill_index[r]; | |
08a9dd06 | 7472 | |
324b84e2 | 7473 | /* If this is a non-inherited input reload from a pseudo, we must |
5bb2f919 | 7474 | clear any memory of a previous store to the same pseudo. Only do |
7475 | something if there will not be an output reload for the pseudo | |
7476 | being reloaded. */ | |
48666d2c | 7477 | if (rld[r].in_reg != 0 |
5bb2f919 | 7478 | && ! (reload_inherited[r] || reload_override_in[r])) |
7479 | { | |
48666d2c | 7480 | rtx reg = rld[r].in_reg; |
324b84e2 | 7481 | |
5bb2f919 | 7482 | if (GET_CODE (reg) == SUBREG) |
324b84e2 | 7483 | reg = SUBREG_REG (reg); |
5bb2f919 | 7484 | |
8ad4c111 | 7485 | if (REG_P (reg) |
324b84e2 | 7486 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER |
7d742877 | 7487 | && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg))) |
324b84e2 | 7488 | { |
7489 | int nregno = REGNO (reg); | |
7490 | ||
7491 | if (reg_last_reload_reg[nregno]) | |
5bb2f919 | 7492 | { |
7493 | int last_regno = REGNO (reg_last_reload_reg[nregno]); | |
324b84e2 | 7494 | |
5bb2f919 | 7495 | if (reg_reloaded_contents[last_regno] == nregno) |
324b84e2 | 7496 | spill_reg_store[last_regno] = 0; |
5bb2f919 | 7497 | } |
324b84e2 | 7498 | } |
7499 | } | |
5bb2f919 | 7500 | |
a5e95c30 | 7501 | /* I is nonneg if this reload used a register. |
48666d2c | 7502 | If rld[r].reg_rtx is 0, this is an optional reload |
1d23c719 | 7503 | that we opted to ignore. */ |
497de2d4 | 7504 | |
48666d2c | 7505 | if (i >= 0 && rld[r].reg_rtx != 0) |
08a9dd06 | 7506 | { |
67d6c12b | 7507 | int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)]; |
08a9dd06 | 7508 | int k; |
1d23c719 | 7509 | int part_reaches_end = 0; |
7510 | int all_reaches_end = 1; | |
08a9dd06 | 7511 | |
1d23c719 | 7512 | /* For a multi register reload, we need to check if all or part |
7513 | of the value lives to the end. */ | |
08a9dd06 | 7514 | for (k = 0; k < nr; k++) |
7515 | { | |
48666d2c | 7516 | if (reload_reg_reaches_end_p (i + k, rld[r].opnum, |
7517 | rld[r].when_needed)) | |
1d23c719 | 7518 | part_reaches_end = 1; |
7519 | else | |
7520 | all_reaches_end = 0; | |
08a9dd06 | 7521 | } |
7522 | ||
1d23c719 | 7523 | /* Ignore reloads that don't reach the end of the insn in |
7524 | entirety. */ | |
7525 | if (all_reaches_end) | |
08a9dd06 | 7526 | { |
1d23c719 | 7527 | /* First, clear out memory of what used to be in this spill reg. |
7528 | If consecutive registers are used, clear them all. */ | |
a6f0d869 | 7529 | |
08a9dd06 | 7530 | for (k = 0; k < nr; k++) |
e467c16e | 7531 | { |
a5e95c30 | 7532 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
e467c16e | 7533 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k); |
7534 | } | |
a6f0d869 | 7535 | |
1d23c719 | 7536 | /* Maybe the spill reg contains a copy of reload_out. */ |
48666d2c | 7537 | if (rld[r].out != 0 |
8ad4c111 | 7538 | && (REG_P (rld[r].out) |
93c7b06e | 7539 | #ifdef AUTO_INC_DEC |
48666d2c | 7540 | || ! rld[r].out_reg |
93c7b06e | 7541 | #endif |
8ad4c111 | 7542 | || REG_P (rld[r].out_reg))) |
1d23c719 | 7543 | { |
8ad4c111 | 7544 | rtx out = (REG_P (rld[r].out) |
48666d2c | 7545 | ? rld[r].out |
7546 | : rld[r].out_reg | |
7547 | ? rld[r].out_reg | |
7548 | /* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); | |
19cb6b50 | 7549 | int nregno = REGNO (out); |
1d23c719 | 7550 | int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
67d6c12b | 7551 | : hard_regno_nregs[nregno] |
7552 | [GET_MODE (rld[r].reg_rtx)]); | |
9318b368 | 7553 | bool piecemeal; |
1d23c719 | 7554 | |
7555 | spill_reg_store[i] = new_spill_reg_store[i]; | |
93c7b06e | 7556 | spill_reg_stored_to[i] = out; |
48666d2c | 7557 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
1d23c719 | 7558 | |
9318b368 | 7559 | piecemeal = (nregno < FIRST_PSEUDO_REGISTER |
7560 | && nr == nnr | |
7561 | && inherit_piecemeal_p (r, nregno)); | |
7562 | ||
1d23c719 | 7563 | /* If NREGNO is a hard register, it may occupy more than |
5bb2f919 | 7564 | one register. If it does, say what is in the |
1d23c719 | 7565 | rest of the registers assuming that both registers |
7566 | agree on how many words the object takes. If not, | |
7567 | invalidate the subsequent registers. */ | |
7568 | ||
7569 | if (nregno < FIRST_PSEUDO_REGISTER) | |
7570 | for (k = 1; k < nnr; k++) | |
7571 | reg_last_reload_reg[nregno + k] | |
9318b368 | 7572 | = (piecemeal |
8a0b950c | 7573 | ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k] |
1d23c719 | 7574 | : 0); |
7575 | ||
7576 | /* Now do the inverse operation. */ | |
7577 | for (k = 0; k < nr; k++) | |
7578 | { | |
a5e95c30 | 7579 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7580 | reg_reloaded_contents[i + k] | |
9318b368 | 7581 | = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal |
1d23c719 | 7582 | ? nregno |
7583 | : nregno + k); | |
a5e95c30 | 7584 | reg_reloaded_insn[i + k] = insn; |
7585 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
e467c16e | 7586 | if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out))) |
7587 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k); | |
1d23c719 | 7588 | } |
7589 | } | |
a6f0d869 | 7590 | |
1d23c719 | 7591 | /* Maybe the spill reg contains a copy of reload_in. Only do |
7592 | something if there will not be an output reload for | |
7593 | the register being reloaded. */ | |
48666d2c | 7594 | else if (rld[r].out_reg == 0 |
7595 | && rld[r].in != 0 | |
8ad4c111 | 7596 | && ((REG_P (rld[r].in) |
48666d2c | 7597 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER |
7d742877 | 7598 | && !REGNO_REG_SET_P (®_has_output_reload, |
47df8084 | 7599 | REGNO (rld[r].in))) |
8ad4c111 | 7600 | || (REG_P (rld[r].in_reg) |
7d742877 | 7601 | && !REGNO_REG_SET_P (®_has_output_reload, |
f9b7f54d | 7602 | REGNO (rld[r].in_reg)))) |
48666d2c | 7603 | && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn))) |
1d23c719 | 7604 | { |
19cb6b50 | 7605 | int nregno; |
1d23c719 | 7606 | int nnr; |
e467c16e | 7607 | rtx in; |
9318b368 | 7608 | bool piecemeal; |
497de2d4 | 7609 | |
8ad4c111 | 7610 | if (REG_P (rld[r].in) |
48666d2c | 7611 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) |
e467c16e | 7612 | in = rld[r].in; |
8ad4c111 | 7613 | else if (REG_P (rld[r].in_reg)) |
e467c16e | 7614 | in = rld[r].in_reg; |
93c7b06e | 7615 | else |
e467c16e | 7616 | in = XEXP (rld[r].in_reg, 0); |
7617 | nregno = REGNO (in); | |
a6f0d869 | 7618 | |
1d23c719 | 7619 | nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
67d6c12b | 7620 | : hard_regno_nregs[nregno] |
7621 | [GET_MODE (rld[r].reg_rtx)]); | |
5bb2f919 | 7622 | |
48666d2c | 7623 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
1d23c719 | 7624 | |
9318b368 | 7625 | piecemeal = (nregno < FIRST_PSEUDO_REGISTER |
7626 | && nr == nnr | |
7627 | && inherit_piecemeal_p (r, nregno)); | |
7628 | ||
1d23c719 | 7629 | if (nregno < FIRST_PSEUDO_REGISTER) |
7630 | for (k = 1; k < nnr; k++) | |
7631 | reg_last_reload_reg[nregno + k] | |
9318b368 | 7632 | = (piecemeal |
8a0b950c | 7633 | ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k] |
1d23c719 | 7634 | : 0); |
7635 | ||
7636 | /* Unless we inherited this reload, show we haven't | |
93c7b06e | 7637 | recently done a store. |
7638 | Previous stores of inherited auto_inc expressions | |
7639 | also have to be discarded. */ | |
7640 | if (! reload_inherited[r] | |
48666d2c | 7641 | || (rld[r].out && ! rld[r].out_reg)) |
1d23c719 | 7642 | spill_reg_store[i] = 0; |
7643 | ||
7644 | for (k = 0; k < nr; k++) | |
7645 | { | |
a5e95c30 | 7646 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7647 | reg_reloaded_contents[i + k] | |
9318b368 | 7648 | = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal |
1d23c719 | 7649 | ? nregno |
7650 | : nregno + k); | |
a5e95c30 | 7651 | reg_reloaded_insn[i + k] = insn; |
7652 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
e467c16e | 7653 | if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in))) |
7654 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k); | |
1d23c719 | 7655 | } |
7656 | } | |
7657 | } | |
497de2d4 | 7658 | |
1d23c719 | 7659 | /* However, if part of the reload reaches the end, then we must |
7660 | invalidate the old info for the part that survives to the end. */ | |
7661 | else if (part_reaches_end) | |
7662 | { | |
81d0fbb3 | 7663 | for (k = 0; k < nr; k++) |
a5e95c30 | 7664 | if (reload_reg_reaches_end_p (i + k, |
48666d2c | 7665 | rld[r].opnum, |
7666 | rld[r].when_needed)) | |
a5e95c30 | 7667 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
08a9dd06 | 7668 | } |
7669 | } | |
7670 | ||
7671 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
7672 | It's reenabled in 1.35 because supposedly nothing else | |
7673 | deals with this problem. */ | |
7674 | ||
7675 | /* If a register gets output-reloaded from a non-spill register, | |
7676 | that invalidates any previous reloaded copy of it. | |
7677 | But forget_old_reloads_1 won't get to see it, because | |
95468ea2 | 7678 | it thinks only about the original insn. So invalidate it here. |
7679 | Also do the same thing for RELOAD_OTHER constraints where the | |
7680 | output is discarded. */ | |
7681 | if (i < 0 | |
7682 | && ((rld[r].out != 0 | |
7683 | && (REG_P (rld[r].out) | |
7684 | || (MEM_P (rld[r].out) | |
7685 | && REG_P (rld[r].out_reg)))) | |
7686 | || (rld[r].out == 0 && rld[r].out_reg | |
8ad4c111 | 7687 | && REG_P (rld[r].out_reg)))) |
08a9dd06 | 7688 | { |
95468ea2 | 7689 | rtx out = ((rld[r].out && REG_P (rld[r].out)) |
48666d2c | 7690 | ? rld[r].out : rld[r].out_reg); |
19cb6b50 | 7691 | int nregno = REGNO (out); |
7b1ee155 | 7692 | |
7693 | /* REG_RTX is now set or clobbered by the main instruction. | |
7694 | As the comment above explains, forget_old_reloads_1 only | |
7695 | sees the original instruction, and there is no guarantee | |
7696 | that the original instruction also clobbered REG_RTX. | |
7697 | For example, if find_reloads sees that the input side of | |
7698 | a matched operand pair dies in this instruction, it may | |
7699 | use the input register as the reload register. | |
7700 | ||
7701 | Calling forget_old_reloads_1 is a waste of effort if | |
7702 | REG_RTX is also the output register. | |
7703 | ||
7704 | If we know that REG_RTX holds the value of a pseudo | |
7705 | register, the code after the call will record that fact. */ | |
7706 | if (rld[r].reg_rtx && rld[r].reg_rtx != out) | |
7707 | forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL); | |
7708 | ||
9a2d5fa0 | 7709 | if (nregno >= FIRST_PSEUDO_REGISTER) |
93c7b06e | 7710 | { |
df9f2bb6 | 7711 | rtx src_reg, store_insn = NULL_RTX; |
93c7b06e | 7712 | |
7713 | reg_last_reload_reg[nregno] = 0; | |
7714 | ||
7715 | /* If we can find a hard register that is stored, record | |
7716 | the storing insn so that we may delete this insn with | |
7717 | delete_output_reload. */ | |
48666d2c | 7718 | src_reg = rld[r].reg_rtx; |
93c7b06e | 7719 | |
7720 | /* If this is an optional reload, try to find the source reg | |
7721 | from an input reload. */ | |
7722 | if (! src_reg) | |
7723 | { | |
7724 | rtx set = single_set (insn); | |
48666d2c | 7725 | if (set && SET_DEST (set) == rld[r].out) |
93c7b06e | 7726 | { |
7727 | int k; | |
7728 | ||
7729 | src_reg = SET_SRC (set); | |
7730 | store_insn = insn; | |
7731 | for (k = 0; k < n_reloads; k++) | |
7732 | { | |
48666d2c | 7733 | if (rld[k].in == src_reg) |
93c7b06e | 7734 | { |
48666d2c | 7735 | src_reg = rld[k].reg_rtx; |
93c7b06e | 7736 | break; |
7737 | } | |
7738 | } | |
7739 | } | |
7740 | } | |
7741 | else | |
7742 | store_insn = new_spill_reg_store[REGNO (src_reg)]; | |
8ad4c111 | 7743 | if (src_reg && REG_P (src_reg) |
93c7b06e | 7744 | && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) |
7745 | { | |
7746 | int src_regno = REGNO (src_reg); | |
67d6c12b | 7747 | int nr = hard_regno_nregs[src_regno][rld[r].mode]; |
93c7b06e | 7748 | /* The place where to find a death note varies with |
7749 | PRESERVE_DEATH_INFO_REGNO_P . The condition is not | |
7750 | necessarily checked exactly in the code that moves | |
7751 | notes, so just check both locations. */ | |
7752 | rtx note = find_regno_note (insn, REG_DEAD, src_regno); | |
1d9f44ba | 7753 | if (! note && store_insn) |
93c7b06e | 7754 | note = find_regno_note (store_insn, REG_DEAD, src_regno); |
7755 | while (nr-- > 0) | |
7756 | { | |
7757 | spill_reg_store[src_regno + nr] = store_insn; | |
7758 | spill_reg_stored_to[src_regno + nr] = out; | |
7759 | reg_reloaded_contents[src_regno + nr] = nregno; | |
7760 | reg_reloaded_insn[src_regno + nr] = store_insn; | |
207fccde | 7761 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr); |
93c7b06e | 7762 | SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr); |
e467c16e | 7763 | if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr, |
7764 | GET_MODE (src_reg))) | |
7765 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, | |
7766 | src_regno + nr); | |
93c7b06e | 7767 | SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr); |
7768 | if (note) | |
7769 | SET_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7770 | else | |
7771 | CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7772 | } | |
7773 | reg_last_reload_reg[nregno] = src_reg; | |
ac8edb96 | 7774 | /* We have to set reg_has_output_reload here, or else |
7775 | forget_old_reloads_1 will clear reg_last_reload_reg | |
7776 | right away. */ | |
7d742877 | 7777 | SET_REGNO_REG_SET (®_has_output_reload, |
7778 | nregno); | |
93c7b06e | 7779 | } |
7780 | } | |
9a2d5fa0 | 7781 | else |
7782 | { | |
95468ea2 | 7783 | int num_regs = hard_regno_nregs[nregno][GET_MODE (out)]; |
f16fc94d | 7784 | |
9a2d5fa0 | 7785 | while (num_regs-- > 0) |
7786 | reg_last_reload_reg[nregno + num_regs] = 0; | |
7787 | } | |
08a9dd06 | 7788 | } |
7789 | } | |
a5e95c30 | 7790 | IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); |
08a9dd06 | 7791 | } |
7792 | \f | |
6af46e97 | 7793 | /* Go through the motions to emit INSN and test if it is strictly valid. |
7794 | Return the emitted insn if valid, else return NULL. */ | |
7795 | ||
7796 | static rtx | |
7797 | emit_insn_if_valid_for_reload (rtx insn) | |
7798 | { | |
7799 | rtx last = get_last_insn (); | |
7800 | int code; | |
7801 | ||
7802 | insn = emit_insn (insn); | |
7803 | code = recog_memoized (insn); | |
7804 | ||
7805 | if (code >= 0) | |
7806 | { | |
7807 | extract_insn (insn); | |
7808 | /* We want constrain operands to treat this insn strictly in its | |
7809 | validity determination, i.e., the way it would after reload has | |
7810 | completed. */ | |
7811 | if (constrain_operands (1)) | |
7812 | return insn; | |
7813 | } | |
7814 | ||
7815 | delete_insns_since (last); | |
7816 | return NULL; | |
7817 | } | |
7818 | ||
b6fdd226 | 7819 | /* Emit code to perform a reload from IN (which may be a reload register) to |
7820 | OUT (which may also be a reload register). IN or OUT is from operand | |
5bb2f919 | 7821 | OPNUM with reload type TYPE. |
81d0fbb3 | 7822 | |
bb552490 | 7823 | Returns first insn emitted. */ |
08a9dd06 | 7824 | |
3c01fc19 | 7825 | static rtx |
3ad4992f | 7826 | gen_reload (rtx out, rtx in, int opnum, enum reload_type type) |
08a9dd06 | 7827 | { |
81d0fbb3 | 7828 | rtx last = get_last_insn (); |
9fc7ac1a | 7829 | rtx tem; |
7830 | ||
7831 | /* If IN is a paradoxical SUBREG, remove it and try to put the | |
7832 | opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ | |
7833 | if (GET_CODE (in) == SUBREG | |
7834 | && (GET_MODE_SIZE (GET_MODE (in)) | |
7835 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
7836 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) | |
7837 | in = SUBREG_REG (in), out = tem; | |
7838 | else if (GET_CODE (out) == SUBREG | |
48666d2c | 7839 | && (GET_MODE_SIZE (GET_MODE (out)) |
7840 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
7841 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) | |
9fc7ac1a | 7842 | out = SUBREG_REG (out), in = tem; |
08a9dd06 | 7843 | |
c8ad158d | 7844 | /* How to do this reload can get quite tricky. Normally, we are being |
08a9dd06 | 7845 | asked to reload a simple operand, such as a MEM, a constant, or a pseudo |
7846 | register that didn't get a hard register. In that case we can just | |
7847 | call emit_move_insn. | |
7848 | ||
82f1ce58 | 7849 | We can also be asked to reload a PLUS that adds a register or a MEM to |
7850 | another register, constant or MEM. This can occur during frame pointer | |
7851 | elimination and while reloading addresses. This case is handled by | |
7852 | trying to emit a single insn to perform the add. If it is not valid, | |
7853 | we use a two insn sequence. | |
08a9dd06 | 7854 | |
6af46e97 | 7855 | Or we can be asked to reload an unary operand that was a fragment of |
7856 | an addressing mode, into a register. If it isn't recognized as-is, | |
7857 | we try making the unop operand and the reload-register the same: | |
7858 | (set reg:X (unop:X expr:Y)) | |
7859 | -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)). | |
7860 | ||
08a9dd06 | 7861 | Finally, we could be called to handle an 'o' constraint by putting |
7862 | an address into a register. In that case, we first try to do this | |
7863 | with a named pattern of "reload_load_address". If no such pattern | |
7864 | exists, we just emit a SET insn and hope for the best (it will normally | |
7865 | be valid on machines that use 'o'). | |
7866 | ||
7867 | This entire process is made complex because reload will never | |
7868 | process the insns we generate here and so we must ensure that | |
7869 | they will fit their constraints and also by the fact that parts of | |
7870 | IN might be being reloaded separately and replaced with spill registers. | |
7871 | Because of this, we are, in some sense, just guessing the right approach | |
7872 | here. The one listed above seems to work. | |
7873 | ||
7874 | ??? At some point, this whole thing needs to be rethought. */ | |
7875 | ||
7876 | if (GET_CODE (in) == PLUS | |
8ad4c111 | 7877 | && (REG_P (XEXP (in, 0)) |
e54018d3 | 7878 | || GET_CODE (XEXP (in, 0)) == SUBREG |
e16ceb8e | 7879 | || MEM_P (XEXP (in, 0))) |
8ad4c111 | 7880 | && (REG_P (XEXP (in, 1)) |
e54018d3 | 7881 | || GET_CODE (XEXP (in, 1)) == SUBREG |
82f1ce58 | 7882 | || CONSTANT_P (XEXP (in, 1)) |
e16ceb8e | 7883 | || MEM_P (XEXP (in, 1)))) |
08a9dd06 | 7884 | { |
82f1ce58 | 7885 | /* We need to compute the sum of a register or a MEM and another |
7886 | register, constant, or MEM, and put it into the reload | |
2147669e | 7887 | register. The best possible way of doing this is if the machine |
7888 | has a three-operand ADD insn that accepts the required operands. | |
08a9dd06 | 7889 | |
7890 | The simplest approach is to try to generate such an insn and see if it | |
7891 | is recognized and matches its constraints. If so, it can be used. | |
7892 | ||
7893 | It might be better not to actually emit the insn unless it is valid, | |
45b79593 | 7894 | but we need to pass the insn as an operand to `recog' and |
7f82be90 | 7895 | `extract_insn' and it is simpler to emit and then delete the insn if |
45b79593 | 7896 | not valid than to dummy things up. */ |
c8ad158d | 7897 | |
8a7a0a5a | 7898 | rtx op0, op1, tem, insn; |
08a9dd06 | 7899 | int code; |
c8ad158d | 7900 | |
8a7a0a5a | 7901 | op0 = find_replacement (&XEXP (in, 0)); |
7902 | op1 = find_replacement (&XEXP (in, 1)); | |
7903 | ||
08a9dd06 | 7904 | /* Since constraint checking is strict, commutativity won't be |
7905 | checked, so we need to do that here to avoid spurious failure | |
7906 | if the add instruction is two-address and the second operand | |
7907 | of the add is the same as the reload reg, which is frequently | |
7908 | the case. If the insn would be A = B + A, rearrange it so | |
a92771b8 | 7909 | it will be A = A + B as constrain_operands expects. */ |
c8ad158d | 7910 | |
8ad4c111 | 7911 | if (REG_P (XEXP (in, 1)) |
b6fdd226 | 7912 | && REGNO (out) == REGNO (XEXP (in, 1))) |
8a7a0a5a | 7913 | tem = op0, op0 = op1, op1 = tem; |
7914 | ||
7915 | if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) | |
941522d6 | 7916 | in = gen_rtx_PLUS (GET_MODE (in), op0, op1); |
08a9dd06 | 7917 | |
6af46e97 | 7918 | insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in)); |
7919 | if (insn) | |
7920 | return insn; | |
08a9dd06 | 7921 | |
7922 | /* If that failed, we must use a conservative two-insn sequence. | |
866ec3ba | 7923 | |
7924 | Use a move to copy one operand into the reload register. Prefer | |
7925 | to reload a constant, MEM or pseudo since the move patterns can | |
7926 | handle an arbitrary operand. If OP1 is not a constant, MEM or | |
7927 | pseudo and OP1 is not a valid operand for an add instruction, then | |
7928 | reload OP1. | |
7929 | ||
7930 | After reloading one of the operands into the reload register, add | |
7931 | the reload register to the output register. | |
08a9dd06 | 7932 | |
7933 | If there is another way to do this for a specific machine, a | |
7934 | DEFINE_PEEPHOLE should be specified that recognizes the sequence | |
7935 | we emit below. */ | |
7936 | ||
866ec3ba | 7937 | code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code; |
7938 | ||
e16ceb8e | 7939 | if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG |
8ad4c111 | 7940 | || (REG_P (op1) |
866ec3ba | 7941 | && REGNO (op1) >= FIRST_PSEUDO_REGISTER) |
7942 | || (code != CODE_FOR_nothing | |
6357eaae | 7943 | && ! ((*insn_data[code].operand[2].predicate) |
7944 | (op1, insn_data[code].operand[2].mode)))) | |
8a7a0a5a | 7945 | tem = op0, op0 = op1, op1 = tem; |
08a9dd06 | 7946 | |
e54018d3 | 7947 | gen_reload (out, op0, opnum, type); |
9fd8c471 | 7948 | |
b6fdd226 | 7949 | /* If OP0 and OP1 are the same, we can use OUT for OP1. |
9fd8c471 | 7950 | This fixes a problem on the 32K where the stack pointer cannot |
7951 | be used as an operand of an add insn. */ | |
7952 | ||
7953 | if (rtx_equal_p (op0, op1)) | |
b6fdd226 | 7954 | op1 = out; |
9fd8c471 | 7955 | |
6af46e97 | 7956 | insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1)); |
7957 | if (insn) | |
b2b06b7e | 7958 | { |
6af46e97 | 7959 | /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ |
750a330e | 7960 | set_unique_reg_note (insn, REG_EQUIV, in); |
6af46e97 | 7961 | return insn; |
b2b06b7e | 7962 | } |
7963 | ||
6af46e97 | 7964 | /* If that failed, copy the address register to the reload register. |
7965 | Then add the constant to the reload register. */ | |
b2b06b7e | 7966 | |
eca883d1 | 7967 | gcc_assert (!reg_overlap_mentioned_p (out, op0)); |
e54018d3 | 7968 | gen_reload (out, op1, opnum, type); |
7f060acf | 7969 | insn = emit_insn (gen_add2_insn (out, op0)); |
750a330e | 7970 | set_unique_reg_note (insn, REG_EQUIV, in); |
08a9dd06 | 7971 | } |
7972 | ||
c538053c | 7973 | #ifdef SECONDARY_MEMORY_NEEDED |
7974 | /* If we need a memory location to do the move, do it that way. */ | |
8ad4c111 | 7975 | else if ((REG_P (in) || GET_CODE (in) == SUBREG) |
b627bae7 | 7976 | && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER |
8ad4c111 | 7977 | && (REG_P (out) || GET_CODE (out) == SUBREG) |
b627bae7 | 7978 | && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER |
7979 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)), | |
7980 | REGNO_REG_CLASS (reg_or_subregno (out)), | |
b6fdd226 | 7981 | GET_MODE (out))) |
c538053c | 7982 | { |
7983 | /* Get the memory to use and rewrite both registers to its mode. */ | |
b6fdd226 | 7984 | rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); |
c538053c | 7985 | |
b6fdd226 | 7986 | if (GET_MODE (loc) != GET_MODE (out)) |
941522d6 | 7987 | out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); |
c538053c | 7988 | |
7989 | if (GET_MODE (loc) != GET_MODE (in)) | |
941522d6 | 7990 | in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); |
c538053c | 7991 | |
e54018d3 | 7992 | gen_reload (loc, in, opnum, type); |
7993 | gen_reload (out, loc, opnum, type); | |
c538053c | 7994 | } |
7995 | #endif | |
6af46e97 | 7996 | else if (REG_P (out) && UNARY_P (in)) |
7997 | { | |
7998 | rtx insn; | |
7999 | rtx op1; | |
8000 | rtx out_moded; | |
8001 | rtx set; | |
c538053c | 8002 | |
8641bc19 | 8003 | op1 = find_replacement (&XEXP (in, 0)); |
8004 | if (op1 != XEXP (in, 0)) | |
8005 | in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1); | |
8006 | ||
6af46e97 | 8007 | /* First, try a plain SET. */ |
8008 | set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in)); | |
8009 | if (set) | |
8010 | return set; | |
8011 | ||
8012 | /* If that failed, move the inner operand to the reload | |
8013 | register, and try the same unop with the inner expression | |
8014 | replaced with the reload register. */ | |
6af46e97 | 8015 | |
8016 | if (GET_MODE (op1) != GET_MODE (out)) | |
8017 | out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out)); | |
8018 | else | |
8019 | out_moded = out; | |
8020 | ||
8021 | gen_reload (out_moded, op1, opnum, type); | |
8022 | ||
8023 | insn | |
8024 | = gen_rtx_SET (VOIDmode, out, | |
8025 | gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), | |
8026 | out_moded)); | |
8027 | insn = emit_insn_if_valid_for_reload (insn); | |
8028 | if (insn) | |
8029 | { | |
750a330e | 8030 | set_unique_reg_note (insn, REG_EQUIV, in); |
6af46e97 | 8031 | return insn; |
8032 | } | |
8033 | ||
8034 | fatal_insn ("Failure trying to reload:", set); | |
8035 | } | |
08a9dd06 | 8036 | /* If IN is a simple operand, use gen_move_insn. */ |
6720e96c | 8037 | else if (OBJECT_P (in) || GET_CODE (in) == SUBREG) |
493488c1 | 8038 | { |
8039 | tem = emit_insn (gen_move_insn (out, in)); | |
8040 | /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */ | |
8041 | mark_jump_label (in, tem, 0); | |
8042 | } | |
08a9dd06 | 8043 | |
8044 | #ifdef HAVE_reload_load_address | |
8045 | else if (HAVE_reload_load_address) | |
b6fdd226 | 8046 | emit_insn (gen_reload_load_address (out, in)); |
08a9dd06 | 8047 | #endif |
8048 | ||
b6fdd226 | 8049 | /* Otherwise, just write (set OUT IN) and hope for the best. */ |
08a9dd06 | 8050 | else |
941522d6 | 8051 | emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
08a9dd06 | 8052 | |
8053 | /* Return the first insn emitted. | |
81d0fbb3 | 8054 | We can not just return get_last_insn, because there may have |
08a9dd06 | 8055 | been multiple instructions emitted. Also note that gen_move_insn may |
8056 | emit more than one insn itself, so we can not assume that there is one | |
8057 | insn emitted per emit_insn_before call. */ | |
8058 | ||
81d0fbb3 | 8059 | return last ? NEXT_INSN (last) : get_insns (); |
08a9dd06 | 8060 | } |
8061 | \f | |
e172357f | 8062 | /* Delete a previously made output-reload whose result we now believe |
8063 | is not needed. First we double-check. | |
08a9dd06 | 8064 | |
8065 | INSN is the insn now being processed. | |
93c7b06e | 8066 | LAST_RELOAD_REG is the hard register number for which we want to delete |
8067 | the last output reload. | |
8068 | J is the reload-number that originally used REG. The caller has made | |
8069 | certain that reload J doesn't use REG any longer for input. */ | |
08a9dd06 | 8070 | |
8071 | static void | |
3ad4992f | 8072 | delete_output_reload (rtx insn, int j, int last_reload_reg) |
08a9dd06 | 8073 | { |
93c7b06e | 8074 | rtx output_reload_insn = spill_reg_store[last_reload_reg]; |
8075 | rtx reg = spill_reg_stored_to[last_reload_reg]; | |
8076 | int k; | |
8077 | int n_occurrences; | |
8078 | int n_inherited = 0; | |
19cb6b50 | 8079 | rtx i1; |
93c7b06e | 8080 | rtx substed; |
5bb2f919 | 8081 | |
d3da2ad8 | 8082 | /* It is possible that this reload has been only used to set another reload |
8083 | we eliminated earlier and thus deleted this instruction too. */ | |
8084 | if (INSN_DELETED_P (output_reload_insn)) | |
8085 | return; | |
8086 | ||
08a9dd06 | 8087 | /* Get the raw pseudo-register referred to. */ |
8088 | ||
08a9dd06 | 8089 | while (GET_CODE (reg) == SUBREG) |
8090 | reg = SUBREG_REG (reg); | |
93c7b06e | 8091 | substed = reg_equiv_memory_loc[REGNO (reg)]; |
8092 | ||
8093 | /* This is unsafe if the operand occurs more often in the current | |
8094 | insn than it is inherited. */ | |
8095 | for (k = n_reloads - 1; k >= 0; k--) | |
8096 | { | |
48666d2c | 8097 | rtx reg2 = rld[k].in; |
93c7b06e | 8098 | if (! reg2) |
8099 | continue; | |
e16ceb8e | 8100 | if (MEM_P (reg2) || reload_override_in[k]) |
48666d2c | 8101 | reg2 = rld[k].in_reg; |
93c7b06e | 8102 | #ifdef AUTO_INC_DEC |
48666d2c | 8103 | if (rld[k].out && ! rld[k].out_reg) |
8104 | reg2 = XEXP (rld[k].in_reg, 0); | |
93c7b06e | 8105 | #endif |
8106 | while (GET_CODE (reg2) == SUBREG) | |
8107 | reg2 = SUBREG_REG (reg2); | |
8108 | if (rtx_equal_p (reg2, reg)) | |
a1e5a0e1 | 8109 | { |
8110 | if (reload_inherited[k] || reload_override_in[k] || k == j) | |
759d3f80 | 8111 | n_inherited++; |
a1e5a0e1 | 8112 | else |
8113 | return; | |
8114 | } | |
93c7b06e | 8115 | } |
40988080 | 8116 | n_occurrences = count_occurrences (PATTERN (insn), reg, 0); |
ac6a6c76 | 8117 | if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn)) |
8118 | n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn), | |
8119 | reg, 0); | |
93c7b06e | 8120 | if (substed) |
226e9ef3 | 8121 | n_occurrences += count_occurrences (PATTERN (insn), |
8122 | eliminate_regs (substed, 0, | |
8123 | NULL_RTX), 0); | |
d51b37c2 | 8124 | for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1)) |
8125 | { | |
8126 | gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed)); | |
8127 | n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0); | |
8128 | } | |
93c7b06e | 8129 | if (n_occurrences > n_inherited) |
8130 | return; | |
08a9dd06 | 8131 | |
8132 | /* If the pseudo-reg we are reloading is no longer referenced | |
8133 | anywhere between the store into it and here, | |
dfa6b79b | 8134 | and we're within the same basic block, then the value can only |
8135 | pass through the reload reg and end up here. | |
08a9dd06 | 8136 | Otherwise, give up--return. */ |
8137 | for (i1 = NEXT_INSN (output_reload_insn); | |
8138 | i1 != insn; i1 = NEXT_INSN (i1)) | |
8139 | { | |
dfa6b79b | 8140 | if (NOTE_INSN_BASIC_BLOCK_P (i1)) |
08a9dd06 | 8141 | return; |
6d7dc5b9 | 8142 | if ((NONJUMP_INSN_P (i1) || CALL_P (i1)) |
08a9dd06 | 8143 | && reg_mentioned_p (reg, PATTERN (i1))) |
fb4ed7f4 | 8144 | { |
93c7b06e | 8145 | /* If this is USE in front of INSN, we only have to check that |
8146 | there are no more references than accounted for by inheritance. */ | |
6d7dc5b9 | 8147 | while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE) |
fb4ed7f4 | 8148 | { |
93c7b06e | 8149 | n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; |
fb4ed7f4 | 8150 | i1 = NEXT_INSN (i1); |
8151 | } | |
93c7b06e | 8152 | if (n_occurrences <= n_inherited && i1 == insn) |
fb4ed7f4 | 8153 | break; |
8154 | return; | |
8155 | } | |
08a9dd06 | 8156 | } |
8157 | ||
e172357f | 8158 | /* We will be deleting the insn. Remove the spill reg information. */ |
67d6c12b | 8159 | for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; ) |
e172357f | 8160 | { |
8161 | spill_reg_store[last_reload_reg + k] = 0; | |
8162 | spill_reg_stored_to[last_reload_reg + k] = 0; | |
8163 | } | |
8164 | ||
fb4ed7f4 | 8165 | /* The caller has already checked that REG dies or is set in INSN. |
e172357f | 8166 | It has also checked that we are optimizing, and thus some |
de132707 | 8167 | inaccuracies in the debugging information are acceptable. |
e172357f | 8168 | So we could just delete output_reload_insn. But in some cases |
8169 | we can improve the debugging information without sacrificing | |
8170 | optimization - maybe even improving the code: See if the pseudo | |
8171 | reg has been completely replaced with reload regs. If so, delete | |
8172 | the store insn and forget we had a stack slot for the pseudo. */ | |
48666d2c | 8173 | if (rld[j].out != rld[j].in |
fb4ed7f4 | 8174 | && REG_N_DEATHS (REGNO (reg)) == 1 |
7304b676 | 8175 | && REG_N_SETS (REGNO (reg)) == 1 |
3072d30e | 8176 | && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS |
fb4ed7f4 | 8177 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) |
08a9dd06 | 8178 | { |
8179 | rtx i2; | |
8180 | ||
e172357f | 8181 | /* We know that it was used only between here and the beginning of |
8182 | the current basic block. (We also know that the last use before | |
8183 | INSN was the output reload we are thinking of deleting, but never | |
8184 | mind that.) Search that range; see if any ref remains. */ | |
08a9dd06 | 8185 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) |
8186 | { | |
497de2d4 | 8187 | rtx set = single_set (i2); |
8188 | ||
08a9dd06 | 8189 | /* Uses which just store in the pseudo don't count, |
8190 | since if they are the only uses, they are dead. */ | |
497de2d4 | 8191 | if (set != 0 && SET_DEST (set) == reg) |
08a9dd06 | 8192 | continue; |
6d7dc5b9 | 8193 | if (LABEL_P (i2) |
8194 | || JUMP_P (i2)) | |
08a9dd06 | 8195 | break; |
6d7dc5b9 | 8196 | if ((NONJUMP_INSN_P (i2) || CALL_P (i2)) |
08a9dd06 | 8197 | && reg_mentioned_p (reg, PATTERN (i2))) |
fb4ed7f4 | 8198 | { |
8199 | /* Some other ref remains; just delete the output reload we | |
8200 | know to be dead. */ | |
93c7b06e | 8201 | delete_address_reloads (output_reload_insn, insn); |
b36d64df | 8202 | delete_insn (output_reload_insn); |
fb4ed7f4 | 8203 | return; |
8204 | } | |
08a9dd06 | 8205 | } |
8206 | ||
e172357f | 8207 | /* Delete the now-dead stores into this pseudo. Note that this |
8208 | loop also takes care of deleting output_reload_insn. */ | |
08a9dd06 | 8209 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) |
8210 | { | |
497de2d4 | 8211 | rtx set = single_set (i2); |
8212 | ||
8213 | if (set != 0 && SET_DEST (set) == reg) | |
2b3f56be | 8214 | { |
93c7b06e | 8215 | delete_address_reloads (i2, insn); |
b36d64df | 8216 | delete_insn (i2); |
2b3f56be | 8217 | } |
6d7dc5b9 | 8218 | if (LABEL_P (i2) |
8219 | || JUMP_P (i2)) | |
08a9dd06 | 8220 | break; |
8221 | } | |
8222 | ||
e172357f | 8223 | /* For the debugging info, say the pseudo lives in this reload reg. */ |
48666d2c | 8224 | reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx); |
08a9dd06 | 8225 | alter_reg (REGNO (reg), -1); |
8226 | } | |
e172357f | 8227 | else |
8228 | { | |
8229 | delete_address_reloads (output_reload_insn, insn); | |
8230 | delete_insn (output_reload_insn); | |
8231 | } | |
93c7b06e | 8232 | } |
8233 | ||
8234 | /* We are going to delete DEAD_INSN. Recursively delete loads of | |
8235 | reload registers used in DEAD_INSN that are not used till CURRENT_INSN. | |
8236 | CURRENT_INSN is being reloaded, so we have to check its reloads too. */ | |
8237 | static void | |
3ad4992f | 8238 | delete_address_reloads (rtx dead_insn, rtx current_insn) |
93c7b06e | 8239 | { |
8240 | rtx set = single_set (dead_insn); | |
8241 | rtx set2, dst, prev, next; | |
8242 | if (set) | |
8243 | { | |
8244 | rtx dst = SET_DEST (set); | |
e16ceb8e | 8245 | if (MEM_P (dst)) |
93c7b06e | 8246 | delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); |
8247 | } | |
8248 | /* If we deleted the store from a reloaded post_{in,de}c expression, | |
8249 | we can delete the matching adds. */ | |
8250 | prev = PREV_INSN (dead_insn); | |
8251 | next = NEXT_INSN (dead_insn); | |
8252 | if (! prev || ! next) | |
8253 | return; | |
8254 | set = single_set (next); | |
8255 | set2 = single_set (prev); | |
8256 | if (! set || ! set2 | |
8257 | || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS | |
8258 | || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT | |
8259 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT) | |
8260 | return; | |
8261 | dst = SET_DEST (set); | |
8262 | if (! rtx_equal_p (dst, SET_DEST (set2)) | |
8263 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) | |
8264 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) | |
8265 | || (INTVAL (XEXP (SET_SRC (set), 1)) | |
aedd3e94 | 8266 | != -INTVAL (XEXP (SET_SRC (set2), 1)))) |
93c7b06e | 8267 | return; |
e4bf866d | 8268 | delete_related_insns (prev); |
8269 | delete_related_insns (next); | |
93c7b06e | 8270 | } |
8271 | ||
8272 | /* Subfunction of delete_address_reloads: process registers found in X. */ | |
8273 | static void | |
3ad4992f | 8274 | delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn) |
93c7b06e | 8275 | { |
8276 | rtx prev, set, dst, i2; | |
8277 | int i, j; | |
8278 | enum rtx_code code = GET_CODE (x); | |
8279 | ||
8280 | if (code != REG) | |
8281 | { | |
aedd3e94 | 8282 | const char *fmt = GET_RTX_FORMAT (code); |
93c7b06e | 8283 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
8284 | { | |
8285 | if (fmt[i] == 'e') | |
8286 | delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); | |
8287 | else if (fmt[i] == 'E') | |
8288 | { | |
aedd3e94 | 8289 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
93c7b06e | 8290 | delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), |
8291 | current_insn); | |
8292 | } | |
8293 | } | |
8294 | return; | |
8295 | } | |
8296 | ||
8297 | if (spill_reg_order[REGNO (x)] < 0) | |
8298 | return; | |
fb4ed7f4 | 8299 | |
93c7b06e | 8300 | /* Scan backwards for the insn that sets x. This might be a way back due |
8301 | to inheritance. */ | |
8302 | for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) | |
8303 | { | |
8304 | code = GET_CODE (prev); | |
8305 | if (code == CODE_LABEL || code == JUMP_INSN) | |
8306 | return; | |
6720e96c | 8307 | if (!INSN_P (prev)) |
93c7b06e | 8308 | continue; |
8309 | if (reg_set_p (x, PATTERN (prev))) | |
8310 | break; | |
8311 | if (reg_referenced_p (x, PATTERN (prev))) | |
8312 | return; | |
8313 | } | |
8314 | if (! prev || INSN_UID (prev) < reload_first_uid) | |
8315 | return; | |
8316 | /* Check that PREV only sets the reload register. */ | |
8317 | set = single_set (prev); | |
8318 | if (! set) | |
8319 | return; | |
8320 | dst = SET_DEST (set); | |
8ad4c111 | 8321 | if (!REG_P (dst) |
93c7b06e | 8322 | || ! rtx_equal_p (dst, x)) |
8323 | return; | |
8324 | if (! reg_set_p (dst, PATTERN (dead_insn))) | |
8325 | { | |
8326 | /* Check if DST was used in a later insn - | |
8327 | it might have been inherited. */ | |
8328 | for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) | |
8329 | { | |
6d7dc5b9 | 8330 | if (LABEL_P (i2)) |
93c7b06e | 8331 | break; |
9204e736 | 8332 | if (! INSN_P (i2)) |
93c7b06e | 8333 | continue; |
8334 | if (reg_referenced_p (dst, PATTERN (i2))) | |
8335 | { | |
8336 | /* If there is a reference to the register in the current insn, | |
8337 | it might be loaded in a non-inherited reload. If no other | |
8338 | reload uses it, that means the register is set before | |
8339 | referenced. */ | |
8340 | if (i2 == current_insn) | |
8341 | { | |
8342 | for (j = n_reloads - 1; j >= 0; j--) | |
48666d2c | 8343 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
93c7b06e | 8344 | || reload_override_in[j] == dst) |
8345 | return; | |
8346 | for (j = n_reloads - 1; j >= 0; j--) | |
48666d2c | 8347 | if (rld[j].in && rld[j].reg_rtx == dst) |
93c7b06e | 8348 | break; |
8349 | if (j >= 0) | |
8350 | break; | |
8351 | } | |
8352 | return; | |
8353 | } | |
6d7dc5b9 | 8354 | if (JUMP_P (i2)) |
93c7b06e | 8355 | break; |
93c7b06e | 8356 | /* If DST is still live at CURRENT_INSN, check if it is used for |
9a300548 | 8357 | any reload. Note that even if CURRENT_INSN sets DST, we still |
8358 | have to check the reloads. */ | |
93c7b06e | 8359 | if (i2 == current_insn) |
8360 | { | |
8361 | for (j = n_reloads - 1; j >= 0; j--) | |
48666d2c | 8362 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
93c7b06e | 8363 | || reload_override_in[j] == dst) |
8364 | return; | |
8365 | /* ??? We can't finish the loop here, because dst might be | |
8366 | allocated to a pseudo in this block if no reload in this | |
de132707 | 8367 | block needs any of the classes containing DST - see |
93c7b06e | 8368 | spill_hard_reg. There is no easy way to tell this, so we |
8369 | have to scan till the end of the basic block. */ | |
8370 | } | |
9a300548 | 8371 | if (reg_set_p (dst, PATTERN (i2))) |
8372 | break; | |
93c7b06e | 8373 | } |
8374 | } | |
8375 | delete_address_reloads_1 (prev, SET_SRC (set), current_insn); | |
8376 | reg_reloaded_contents[REGNO (dst)] = -1; | |
b36d64df | 8377 | delete_insn (prev); |
08a9dd06 | 8378 | } |
08a9dd06 | 8379 | \f |
c8ad158d | 8380 | /* Output reload-insns to reload VALUE into RELOADREG. |
df5e872e | 8381 | VALUE is an autoincrement or autodecrement RTX whose operand |
08a9dd06 | 8382 | is a register or memory location; |
8383 | so reloading involves incrementing that location. | |
93c7b06e | 8384 | IN is either identical to VALUE, or some cheaper place to reload from. |
08a9dd06 | 8385 | |
8386 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
93c7b06e | 8387 | This cannot be deduced from VALUE. |
08a9dd06 | 8388 | |
93c7b06e | 8389 | Return the instruction that stores into RELOADREG. */ |
8390 | ||
8391 | static rtx | |
3ad4992f | 8392 | inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount) |
08a9dd06 | 8393 | { |
8394 | /* REG or MEM to be copied and incremented. */ | |
23c79c0f | 8395 | rtx incloc = find_replacement (&XEXP (value, 0)); |
08a9dd06 | 8396 | /* Nonzero if increment after copying. */ |
f5bccbd1 | 8397 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC |
8398 | || GET_CODE (value) == POST_MODIFY); | |
81d0fbb3 | 8399 | rtx last; |
45b79593 | 8400 | rtx inc; |
8401 | rtx add_insn; | |
8402 | int code; | |
93c7b06e | 8403 | rtx store; |
23c79c0f | 8404 | rtx real_in = in == value ? incloc : in; |
08a9dd06 | 8405 | |
8406 | /* No hard register is equivalent to this register after | |
7fd957fe | 8407 | inc/dec operation. If REG_LAST_RELOAD_REG were nonzero, |
08a9dd06 | 8408 | we could inc/dec that register as well (maybe even using it for |
8409 | the source), but I'm not sure it's worth worrying about. */ | |
8ad4c111 | 8410 | if (REG_P (incloc)) |
08a9dd06 | 8411 | reg_last_reload_reg[REGNO (incloc)] = 0; |
8412 | ||
f5bccbd1 | 8413 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) |
8414 | { | |
8415 | gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS); | |
23c79c0f | 8416 | inc = find_replacement (&XEXP (XEXP (value, 1), 1)); |
f5bccbd1 | 8417 | } |
8418 | else | |
8419 | { | |
8420 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
8421 | inc_amount = -inc_amount; | |
08a9dd06 | 8422 | |
f5bccbd1 | 8423 | inc = GEN_INT (inc_amount); |
8424 | } | |
45b79593 | 8425 | |
8426 | /* If this is post-increment, first copy the location to the reload reg. */ | |
93c7b06e | 8427 | if (post && real_in != reloadreg) |
8428 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
45b79593 | 8429 | |
93c7b06e | 8430 | if (in == value) |
8431 | { | |
8432 | /* See if we can directly increment INCLOC. Use a method similar to | |
8433 | that in gen_reload. */ | |
45b79593 | 8434 | |
93c7b06e | 8435 | last = get_last_insn (); |
8436 | add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, | |
8437 | gen_rtx_PLUS (GET_MODE (incloc), | |
8438 | incloc, inc))); | |
5bb2f919 | 8439 | |
93c7b06e | 8440 | code = recog_memoized (add_insn); |
8441 | if (code >= 0) | |
08a9dd06 | 8442 | { |
7f82be90 | 8443 | extract_insn (add_insn); |
8444 | if (constrain_operands (1)) | |
93c7b06e | 8445 | { |
8446 | /* If this is a pre-increment and we have incremented the value | |
8447 | where it lives, copy the incremented value to RELOADREG to | |
8448 | be used as an address. */ | |
45b79593 | 8449 | |
93c7b06e | 8450 | if (! post) |
8451 | emit_insn (gen_move_insn (reloadreg, incloc)); | |
81d0fbb3 | 8452 | |
93c7b06e | 8453 | return add_insn; |
8454 | } | |
08a9dd06 | 8455 | } |
93c7b06e | 8456 | delete_insns_since (last); |
08a9dd06 | 8457 | } |
45b79593 | 8458 | |
45b79593 | 8459 | /* If couldn't do the increment directly, must increment in RELOADREG. |
8460 | The way we do this depends on whether this is pre- or post-increment. | |
8461 | For pre-increment, copy INCLOC to the reload register, increment it | |
8462 | there, then save back. */ | |
8463 | ||
8464 | if (! post) | |
8465 | { | |
93c7b06e | 8466 | if (in != reloadreg) |
8467 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
81d0fbb3 | 8468 | emit_insn (gen_add2_insn (reloadreg, inc)); |
93c7b06e | 8469 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
45b79593 | 8470 | } |
08a9dd06 | 8471 | else |
8472 | { | |
45b79593 | 8473 | /* Postincrement. |
8474 | Because this might be a jump insn or a compare, and because RELOADREG | |
8475 | may not be available after the insn in an input reload, we must do | |
8476 | the incrementation before the insn being reloaded for. | |
8477 | ||
93c7b06e | 8478 | We have already copied IN to RELOADREG. Increment the copy in |
45b79593 | 8479 | RELOADREG, save that back, then decrement RELOADREG so it has |
8480 | the original value. */ | |
8481 | ||
81d0fbb3 | 8482 | emit_insn (gen_add2_insn (reloadreg, inc)); |
93c7b06e | 8483 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
f5bccbd1 | 8484 | if (GET_CODE (inc) == CONST_INT) |
7e806a89 | 8485 | emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc)))); |
f5bccbd1 | 8486 | else |
8487 | emit_insn (gen_sub2_insn (reloadreg, inc)); | |
08a9dd06 | 8488 | } |
45b79593 | 8489 | |
93c7b06e | 8490 | return store; |
08a9dd06 | 8491 | } |
8492 | \f | |
c4f0a530 | 8493 | #ifdef AUTO_INC_DEC |
8494 | static void | |
3ad4992f | 8495 | add_auto_inc_notes (rtx insn, rtx x) |
c4f0a530 | 8496 | { |
8497 | enum rtx_code code = GET_CODE (x); | |
d2ca078f | 8498 | const char *fmt; |
c4f0a530 | 8499 | int i, j; |
8500 | ||
8501 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
8502 | { | |
8503 | REG_NOTES (insn) | |
8504 | = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn)); | |
8505 | return; | |
8506 | } | |
8507 | ||
8508 | /* Scan all the operand sub-expressions. */ | |
8509 | fmt = GET_RTX_FORMAT (code); | |
8510 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
8511 | { | |
8512 | if (fmt[i] == 'e') | |
8513 | add_auto_inc_notes (insn, XEXP (x, i)); | |
8514 | else if (fmt[i] == 'E') | |
8515 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
8516 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
8517 | } | |
8518 | } | |
8519 | #endif | |
d8c23d3f | 8520 | |
8521 | /* Copy EH notes from an insn to its reloads. */ | |
8522 | static void | |
3ad4992f | 8523 | copy_eh_notes (rtx insn, rtx x) |
d8c23d3f | 8524 | { |
8525 | rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
8526 | if (eh_note) | |
8527 | { | |
8528 | for (; x != 0; x = NEXT_INSN (x)) | |
8529 | { | |
8530 | if (may_trap_p (PATTERN (x))) | |
2617fe26 | 8531 | REG_NOTES (x) |
d8c23d3f | 8532 | = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0), |
8533 | REG_NOTES (x)); | |
8534 | } | |
8535 | } | |
8536 | } | |
8537 | ||
2f0bfe72 | 8538 | /* This is used by reload pass, that does emit some instructions after |
8539 | abnormal calls moving basic block end, but in fact it wants to emit | |
8540 | them on the edge. Looks for abnormal call edges, find backward the | |
8541 | proper call and fix the damage. | |
2617fe26 | 8542 | |
2f0bfe72 | 8543 | Similar handle instructions throwing exceptions internally. */ |
17a54dac | 8544 | void |
3ad4992f | 8545 | fixup_abnormal_edges (void) |
2f0bfe72 | 8546 | { |
2f0bfe72 | 8547 | bool inserted = false; |
4c26117a | 8548 | basic_block bb; |
2f0bfe72 | 8549 | |
4c26117a | 8550 | FOR_EACH_BB (bb) |
2f0bfe72 | 8551 | { |
2f0bfe72 | 8552 | edge e; |
cd665a06 | 8553 | edge_iterator ei; |
2f0bfe72 | 8554 | |
edc2a478 | 8555 | /* Look for cases we are interested in - calls or instructions causing |
2f0bfe72 | 8556 | exceptions. */ |
cd665a06 | 8557 | FOR_EACH_EDGE (e, ei, bb->succs) |
2f0bfe72 | 8558 | { |
8559 | if (e->flags & EDGE_ABNORMAL_CALL) | |
8560 | break; | |
8561 | if ((e->flags & (EDGE_ABNORMAL | EDGE_EH)) | |
8562 | == (EDGE_ABNORMAL | EDGE_EH)) | |
8563 | break; | |
8564 | } | |
6d7dc5b9 | 8565 | if (e && !CALL_P (BB_END (bb)) |
5496dbfc | 8566 | && !can_throw_internal (BB_END (bb))) |
2f0bfe72 | 8567 | { |
43283c91 | 8568 | rtx insn; |
8569 | ||
8570 | /* Get past the new insns generated. Allow notes, as the insns | |
8571 | may be already deleted. */ | |
8572 | insn = BB_END (bb); | |
6d7dc5b9 | 8573 | while ((NONJUMP_INSN_P (insn) || NOTE_P (insn)) |
7a577715 | 8574 | && !can_throw_internal (insn) |
5496dbfc | 8575 | && insn != BB_HEAD (bb)) |
2f0bfe72 | 8576 | insn = PREV_INSN (insn); |
43283c91 | 8577 | |
8578 | if (CALL_P (insn) || can_throw_internal (insn)) | |
2f0bfe72 | 8579 | { |
43283c91 | 8580 | rtx stop, next; |
8581 | ||
8582 | stop = NEXT_INSN (BB_END (bb)); | |
8583 | BB_END (bb) = insn; | |
8584 | insn = NEXT_INSN (insn); | |
8585 | ||
8586 | FOR_EACH_EDGE (e, ei, bb->succs) | |
8587 | if (e->flags & EDGE_FALLTHRU) | |
8588 | break; | |
8589 | ||
8590 | while (insn && insn != stop) | |
740dc6f2 | 8591 | { |
43283c91 | 8592 | next = NEXT_INSN (insn); |
8593 | if (INSN_P (insn)) | |
cb5c5698 | 8594 | { |
ab30576b | 8595 | delete_insn (insn); |
43283c91 | 8596 | |
8597 | /* Sometimes there's still the return value USE. | |
8598 | If it's placed after a trapping call (i.e. that | |
8599 | call is the last insn anyway), we have no fallthru | |
8600 | edge. Simply delete this use and don't try to insert | |
8601 | on the non-existent edge. */ | |
8602 | if (GET_CODE (PATTERN (insn)) != USE) | |
8603 | { | |
8604 | /* We're not deleting it, we're moving it. */ | |
8605 | INSN_DELETED_P (insn) = 0; | |
8606 | PREV_INSN (insn) = NULL_RTX; | |
8607 | NEXT_INSN (insn) = NULL_RTX; | |
5fad51c9 | 8608 | |
43283c91 | 8609 | insert_insn_on_edge (insn, e); |
8610 | inserted = true; | |
8611 | } | |
cb5c5698 | 8612 | } |
ab30576b | 8613 | else if (!BARRIER_P (insn)) |
8614 | set_block_for_insn (insn, NULL); | |
43283c91 | 8615 | insn = next; |
740dc6f2 | 8616 | } |
2f0bfe72 | 8617 | } |
43283c91 | 8618 | |
8619 | /* It may be that we don't find any such trapping insn. In this | |
8620 | case we discovered quite late that the insn that had been | |
8621 | marked as can_throw_internal in fact couldn't trap at all. | |
8622 | So we should in fact delete the EH edges out of the block. */ | |
8623 | else | |
8624 | purge_dead_edges (bb); | |
2f0bfe72 | 8625 | } |
8626 | } | |
43283c91 | 8627 | |
16f40b30 | 8628 | /* We've possibly turned single trapping insn into multiple ones. */ |
8629 | if (flag_non_call_exceptions) | |
8630 | { | |
8631 | sbitmap blocks; | |
8632 | blocks = sbitmap_alloc (last_basic_block); | |
8633 | sbitmap_ones (blocks); | |
8634 | find_many_sub_basic_blocks (blocks); | |
8635 | } | |
8636 | ||
2f0bfe72 | 8637 | if (inserted) |
8638 | commit_edge_insertions (); | |
43283c91 | 8639 | |
8640 | #ifdef ENABLE_CHECKING | |
8641 | /* Verify that we didn't turn one trapping insn into many, and that | |
8642 | we found and corrected all of the problems wrt fixups on the | |
8643 | fallthru edge. */ | |
8644 | verify_flow_info (); | |
8645 | #endif | |
2f0bfe72 | 8646 | } |