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32131a9c | 1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
af841dbd | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
4c9034c5 KK |
3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
4 | Free Software Foundation, Inc. | |
32131a9c | 5 | |
1322177d | 6 | This file is part of GCC. |
32131a9c | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
32131a9c | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
32131a9c RK |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
32131a9c | 21 | |
32131a9c | 22 | #include "config.h" |
670ee920 | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
cab634f2 KG |
26 | |
27 | #include "machmode.h" | |
28 | #include "hard-reg-set.h" | |
32131a9c | 29 | #include "rtl.h" |
6baf1cc8 | 30 | #include "tm_p.h" |
32131a9c RK |
31 | #include "obstack.h" |
32 | #include "insn-config.h" | |
32131a9c | 33 | #include "flags.h" |
49ad7cfa | 34 | #include "function.h" |
32131a9c | 35 | #include "expr.h" |
e78d8e51 | 36 | #include "optabs.h" |
32131a9c | 37 | #include "regs.h" |
c4963a0a | 38 | #include "addresses.h" |
cad6f7d0 | 39 | #include "basic-block.h" |
32131a9c RK |
40 | #include "reload.h" |
41 | #include "recog.h" | |
32131a9c | 42 | #include "output.h" |
a9c366bf | 43 | #include "real.h" |
10f0ad3d | 44 | #include "toplev.h" |
39f95a2c | 45 | #include "except.h" |
a20fd5ac | 46 | #include "tree.h" |
6fb5fa3c | 47 | #include "df.h" |
8a99f6f9 | 48 | #include "target.h" |
6fb5fa3c | 49 | #include "dse.h" |
32131a9c RK |
50 | |
51 | /* This file contains the reload pass of the compiler, which is | |
52 | run after register allocation has been done. It checks that | |
53 | each insn is valid (operands required to be in registers really | |
54 | are in registers of the proper class) and fixes up invalid ones | |
55 | by copying values temporarily into registers for the insns | |
56 | that need them. | |
57 | ||
58 | The results of register allocation are described by the vector | |
59 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
60 | can be used to find which hard reg, if any, a pseudo reg is in. | |
61 | ||
62 | The technique we always use is to free up a few hard regs that are | |
63 | called ``reload regs'', and for each place where a pseudo reg | |
64 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
65 | ||
03acd8f8 BS |
66 | Reload regs are allocated locally for every instruction that needs |
67 | reloads. When there are pseudos which are allocated to a register that | |
68 | has been chosen as a reload reg, such pseudos must be ``spilled''. | |
69 | This means that they go to other hard regs, or to stack slots if no other | |
32131a9c RK |
70 | available hard regs can be found. Spilling can invalidate more |
71 | insns, requiring additional need for reloads, so we must keep checking | |
72 | until the process stabilizes. | |
73 | ||
74 | For machines with different classes of registers, we must keep track | |
75 | of the register class needed for each reload, and make sure that | |
76 | we allocate enough reload registers of each class. | |
77 | ||
78 | The file reload.c contains the code that checks one insn for | |
79 | validity and reports the reloads that it needs. This file | |
80 | is in charge of scanning the entire rtl code, accumulating the | |
81 | reload needs, spilling, assigning reload registers to use for | |
82 | fixing up each insn, and generating the new insns to copy values | |
83 | into the reload registers. */ | |
84 | \f | |
85 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
0f41302f | 86 | into which reg N has been reloaded (perhaps for a previous insn). */ |
32131a9c RK |
87 | static rtx *reg_last_reload_reg; |
88 | ||
89 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
90 | for an output reload that stores into reg N. */ | |
2c61f5f1 | 91 | static regset_head reg_has_output_reload; |
32131a9c RK |
92 | |
93 | /* Indicates which hard regs are reload-registers for an output reload | |
94 | in the current insn. */ | |
95 | static HARD_REG_SET reg_is_output_reload; | |
96 | ||
97 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
98 | or zero if pseudo reg N is not equivalent to a constant. | |
99 | find_reloads looks at this in order to replace pseudo reg N | |
100 | with the constant it stands for. */ | |
101 | rtx *reg_equiv_constant; | |
102 | ||
ab156144 RH |
103 | /* Element N is an invariant value to which pseudo reg N is equivalent. |
104 | eliminate_regs_in_insn uses this to replace pseudos in particular | |
105 | contexts. */ | |
106 | rtx *reg_equiv_invariant; | |
107 | ||
32131a9c RK |
108 | /* Element N is a memory location to which pseudo reg N is equivalent, |
109 | prior to any register elimination (such as frame pointer to stack | |
110 | pointer). Depending on whether or not it is a valid address, this value | |
111 | is transferred to either reg_equiv_address or reg_equiv_mem. */ | |
4803a34a | 112 | rtx *reg_equiv_memory_loc; |
32131a9c | 113 | |
965ccc5a R |
114 | /* We allocate reg_equiv_memory_loc inside a varray so that the garbage |
115 | collector can keep track of what is inside. */ | |
43b373a2 | 116 | VEC(rtx,gc) *reg_equiv_memory_loc_vec; |
965ccc5a | 117 | |
32131a9c RK |
118 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. |
119 | This is used when the address is not valid as a memory address | |
120 | (because its displacement is too big for the machine.) */ | |
121 | rtx *reg_equiv_address; | |
122 | ||
123 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
124 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
125 | rtx *reg_equiv_mem; | |
126 | ||
3f1e3e70 AO |
127 | /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with |
128 | alternate representations of the location of pseudo reg N. */ | |
129 | rtx *reg_equiv_alt_mem_list; | |
130 | ||
32131a9c | 131 | /* Widest width in which each pseudo reg is referred to (via subreg). */ |
770ae6cc | 132 | static unsigned int *reg_max_ref_width; |
32131a9c | 133 | |
135eb61c | 134 | /* Element N is the list of insns that initialized reg N from its equivalent |
32131a9c | 135 | constant or memory slot. */ |
d7f88d86 BS |
136 | rtx *reg_equiv_init; |
137 | int reg_equiv_init_size; | |
32131a9c | 138 | |
03acd8f8 BS |
139 | /* Vector to remember old contents of reg_renumber before spilling. */ |
140 | static short *reg_old_renumber; | |
141 | ||
e6e52be0 | 142 | /* During reload_as_needed, element N contains the last pseudo regno reloaded |
03acd8f8 | 143 | into hard register N. If that pseudo reg occupied more than one register, |
32131a9c RK |
144 | reg_reloaded_contents points to that pseudo for each spill register in |
145 | use; all of these must remain set for an inheritance to occur. */ | |
146 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
147 | ||
148 | /* During reload_as_needed, element N contains the insn for which | |
e6e52be0 R |
149 | hard register N was last used. Its contents are significant only |
150 | when reg_reloaded_valid is set for this register. */ | |
32131a9c RK |
151 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; |
152 | ||
3eae4643 | 153 | /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */ |
e6e52be0 R |
154 | static HARD_REG_SET reg_reloaded_valid; |
155 | /* Indicate if the register was dead at the end of the reload. | |
156 | This is only valid if reg_reloaded_contents is set and valid. */ | |
157 | static HARD_REG_SET reg_reloaded_dead; | |
158 | ||
e3e9336f DJ |
159 | /* Indicate whether the register's current value is one that is not |
160 | safe to retain across a call, even for registers that are normally | |
161 | call-saved. */ | |
162 | static HARD_REG_SET reg_reloaded_call_part_clobbered; | |
163 | ||
32131a9c RK |
164 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ |
165 | static int n_spills; | |
166 | ||
167 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
168 | Holds the last rtx used for any given reg, or 0 if it has never | |
169 | been used for spilling yet. This rtx is reused, provided it has | |
170 | the proper mode. */ | |
171 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
172 | ||
173 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
174 | that was stored after the last time it was used. | |
175 | The precise value is the insn generated to do the store. */ | |
176 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
177 | ||
cb2afeb3 R |
178 | /* This is the register that was stored with spill_reg_store. This is a |
179 | copy of reload_out / reload_out_reg when the value was stored; if | |
180 | reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ | |
181 | static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; | |
182 | ||
32131a9c RK |
183 | /* This table is the inverse mapping of spill_regs: |
184 | indexed by hard reg number, | |
185 | it contains the position of that reg in spill_regs, | |
05d10675 | 186 | or -1 for something that is not in spill_regs. |
13c8e8e3 JL |
187 | |
188 | ?!? This is no longer accurate. */ | |
32131a9c RK |
189 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; |
190 | ||
03acd8f8 BS |
191 | /* This reg set indicates registers that can't be used as spill registers for |
192 | the currently processed insn. These are the hard registers which are live | |
193 | during the insn, but not allocated to pseudos, as well as fixed | |
194 | registers. */ | |
32131a9c RK |
195 | static HARD_REG_SET bad_spill_regs; |
196 | ||
03acd8f8 BS |
197 | /* These are the hard registers that can't be used as spill register for any |
198 | insn. This includes registers used for user variables and registers that | |
199 | we can't eliminate. A register that appears in this set also can't be used | |
200 | to retry register allocation. */ | |
201 | static HARD_REG_SET bad_spill_regs_global; | |
202 | ||
32131a9c | 203 | /* Describes order of use of registers for reloading |
03acd8f8 BS |
204 | of spilled pseudo-registers. `n_spills' is the number of |
205 | elements that are actually valid; new ones are added at the end. | |
206 | ||
207 | Both spill_regs and spill_reg_order are used on two occasions: | |
208 | once during find_reload_regs, where they keep track of the spill registers | |
209 | for a single insn, but also during reload_as_needed where they show all | |
210 | the registers ever used by reload. For the latter case, the information | |
211 | is calculated during finish_spills. */ | |
32131a9c RK |
212 | static short spill_regs[FIRST_PSEUDO_REGISTER]; |
213 | ||
03acd8f8 BS |
214 | /* This vector of reg sets indicates, for each pseudo, which hard registers |
215 | may not be used for retrying global allocation because the register was | |
216 | formerly spilled from one of them. If we allowed reallocating a pseudo to | |
217 | a register that it was already allocated to, reload might not | |
218 | terminate. */ | |
219 | static HARD_REG_SET *pseudo_previous_regs; | |
220 | ||
221 | /* This vector of reg sets indicates, for each pseudo, which hard | |
222 | registers may not be used for retrying global allocation because they | |
223 | are used as spill registers during one of the insns in which the | |
224 | pseudo is live. */ | |
225 | static HARD_REG_SET *pseudo_forbidden_regs; | |
226 | ||
227 | /* All hard regs that have been used as spill registers for any insn are | |
228 | marked in this set. */ | |
229 | static HARD_REG_SET used_spill_regs; | |
8b4f9969 | 230 | |
4079cd63 JW |
231 | /* Index of last register assigned as a spill register. We allocate in |
232 | a round-robin fashion. */ | |
4079cd63 JW |
233 | static int last_spill_reg; |
234 | ||
32131a9c RK |
235 | /* Nonzero if indirect addressing is supported on the machine; this means |
236 | that spilling (REG n) does not require reloading it into a register in | |
237 | order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The | |
238 | value indicates the level of indirect addressing supported, e.g., two | |
239 | means that (MEM (MEM (REG n))) is also valid if (REG n) does not get | |
240 | a hard register. */ | |
32131a9c RK |
241 | static char spill_indirect_levels; |
242 | ||
243 | /* Nonzero if indirect addressing is supported when the innermost MEM is | |
244 | of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to | |
6d2f8887 | 245 | which these are valid is the same as spill_indirect_levels, above. */ |
98af7219 | 246 | char indirect_symref_ok; |
32131a9c RK |
247 | |
248 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
32131a9c RK |
249 | char double_reg_address_ok; |
250 | ||
251 | /* Record the stack slot for each spilled hard register. */ | |
32131a9c RK |
252 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; |
253 | ||
254 | /* Width allocated so far for that stack slot. */ | |
770ae6cc | 255 | static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; |
32131a9c | 256 | |
7609e720 | 257 | /* Record which pseudos needed to be spilled. */ |
f5d8c9f4 BS |
258 | static regset_head spilled_pseudos; |
259 | ||
260 | /* Used for communication between order_regs_for_reload and count_pseudo. | |
261 | Used to avoid counting one pseudo twice. */ | |
262 | static regset_head pseudos_counted; | |
7609e720 | 263 | |
32131a9c RK |
264 | /* First uid used by insns created by reload in this function. |
265 | Used in find_equiv_reg. */ | |
266 | int reload_first_uid; | |
267 | ||
268 | /* Flag set by local-alloc or global-alloc if anything is live in | |
269 | a call-clobbered reg across calls. */ | |
32131a9c RK |
270 | int caller_save_needed; |
271 | ||
272 | /* Set to 1 while reload_as_needed is operating. | |
273 | Required by some machines to handle any generated moves differently. */ | |
32131a9c RK |
274 | int reload_in_progress = 0; |
275 | ||
276 | /* These arrays record the insn_code of insns that may be needed to | |
277 | perform input and output reloads of special objects. They provide a | |
278 | place to pass a scratch register. */ | |
32131a9c RK |
279 | enum insn_code reload_in_optab[NUM_MACHINE_MODES]; |
280 | enum insn_code reload_out_optab[NUM_MACHINE_MODES]; | |
281 | ||
d45cf215 | 282 | /* This obstack is used for allocation of rtl during register elimination. |
32131a9c RK |
283 | The allocated storage can be freed once find_reloads has processed the |
284 | insn. */ | |
5983a90e | 285 | static struct obstack reload_obstack; |
cad6f7d0 BS |
286 | |
287 | /* Points to the beginning of the reload_obstack. All insn_chain structures | |
288 | are allocated first. */ | |
cf0fa607 | 289 | static char *reload_startobj; |
cad6f7d0 BS |
290 | |
291 | /* The point after all insn_chain structures. Used to quickly deallocate | |
f5d8c9f4 | 292 | memory allocated in copy_reloads during calculate_needs_all_insns. */ |
cf0fa607 | 293 | static char *reload_firstobj; |
32131a9c | 294 | |
f5d8c9f4 BS |
295 | /* This points before all local rtl generated by register elimination. |
296 | Used to quickly free all memory after processing one insn. */ | |
297 | static char *reload_insn_firstobj; | |
298 | ||
cad6f7d0 BS |
299 | /* List of insn_chain instructions, one for every insn that reload needs to |
300 | examine. */ | |
301 | struct insn_chain *reload_insn_chain; | |
7609e720 | 302 | |
03acd8f8 | 303 | /* List of all insns needing reloads. */ |
7609e720 | 304 | static struct insn_chain *insns_need_reload; |
32131a9c RK |
305 | \f |
306 | /* This structure is used to record information about register eliminations. | |
307 | Each array entry describes one possible way of eliminating a register | |
308 | in favor of another. If there is more than one way of eliminating a | |
309 | particular register, the most preferred should be specified first. */ | |
310 | ||
590cf94d | 311 | struct elim_table |
32131a9c | 312 | { |
0f41302f MS |
313 | int from; /* Register number to be eliminated. */ |
314 | int to; /* Register number used as replacement. */ | |
b19ee4bd | 315 | HOST_WIDE_INT initial_offset; /* Initial difference between values. */ |
272d0bee | 316 | int can_eliminate; /* Nonzero if this elimination can be done. */ |
32131a9c | 317 | int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over |
0f41302f | 318 | insns made by reload. */ |
b19ee4bd JJ |
319 | HOST_WIDE_INT offset; /* Current offset between the two regs. */ |
320 | HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */ | |
0f41302f | 321 | int ref_outside_mem; /* "to" has been referenced outside a MEM. */ |
32131a9c RK |
322 | rtx from_rtx; /* REG rtx for the register to be eliminated. |
323 | We cannot simply compare the number since | |
324 | we might then spuriously replace a hard | |
325 | register corresponding to a pseudo | |
0f41302f MS |
326 | assigned to the reg to be eliminated. */ |
327 | rtx to_rtx; /* REG rtx for the replacement. */ | |
590cf94d KG |
328 | }; |
329 | ||
1d7254c5 | 330 | static struct elim_table *reg_eliminate = 0; |
590cf94d KG |
331 | |
332 | /* This is an intermediate structure to initialize the table. It has | |
1d7254c5 | 333 | exactly the members provided by ELIMINABLE_REGS. */ |
0b5826ac | 334 | static const struct elim_table_1 |
590cf94d | 335 | { |
0b5826ac KG |
336 | const int from; |
337 | const int to; | |
590cf94d | 338 | } reg_eliminate_1[] = |
32131a9c RK |
339 | |
340 | /* If a set of eliminable registers was specified, define the table from it. | |
341 | Otherwise, default to the normal case of the frame pointer being | |
342 | replaced by the stack pointer. */ | |
343 | ||
344 | #ifdef ELIMINABLE_REGS | |
345 | ELIMINABLE_REGS; | |
346 | #else | |
347 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
348 | #endif | |
349 | ||
b6a1cbae | 350 | #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) |
32131a9c RK |
351 | |
352 | /* Record the number of pending eliminations that have an offset not equal | |
40f03658 | 353 | to their initial offset. If nonzero, we use a new copy of each |
32131a9c | 354 | replacement result in any insns encountered. */ |
cb2afeb3 | 355 | int num_not_at_initial_offset; |
32131a9c RK |
356 | |
357 | /* Count the number of registers that we may be able to eliminate. */ | |
358 | static int num_eliminable; | |
2b49ee39 R |
359 | /* And the number of registers that are equivalent to a constant that |
360 | can be eliminated to frame_pointer / arg_pointer + constant. */ | |
361 | static int num_eliminable_invariants; | |
32131a9c RK |
362 | |
363 | /* For each label, we record the offset of each elimination. If we reach | |
364 | a label by more than one path and an offset differs, we cannot do the | |
4cc0fdd2 JDA |
365 | elimination. This information is indexed by the difference of the |
366 | number of the label and the first label number. We can't offset the | |
367 | pointer itself as this can cause problems on machines with segmented | |
368 | memory. The first table is an array of flags that records whether we | |
369 | have yet encountered a label and the second table is an array of arrays, | |
370 | one entry in the latter array for each elimination. */ | |
371 | ||
372 | static int first_label_num; | |
32131a9c | 373 | static char *offsets_known_at; |
b19ee4bd | 374 | static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS]; |
32131a9c RK |
375 | |
376 | /* Number of labels in the current function. */ | |
377 | ||
378 | static int num_labels; | |
379 | \f | |
0c20a65f AJ |
380 | static void replace_pseudos_in (rtx *, enum machine_mode, rtx); |
381 | static void maybe_fix_stack_asms (void); | |
382 | static void copy_reloads (struct insn_chain *); | |
383 | static void calculate_needs_all_insns (int); | |
384 | static int find_reg (struct insn_chain *, int); | |
385 | static void find_reload_regs (struct insn_chain *); | |
386 | static void select_reload_regs (void); | |
387 | static void delete_caller_save_insns (void); | |
388 | ||
389 | static void spill_failure (rtx, enum reg_class); | |
390 | static void count_spilled_pseudo (int, int, int); | |
391 | static void delete_dead_insn (rtx); | |
392 | static void alter_reg (int, int); | |
393 | static void set_label_offsets (rtx, rtx, int); | |
394 | static void check_eliminable_occurrences (rtx); | |
395 | static void elimination_effects (rtx, enum machine_mode); | |
396 | static int eliminate_regs_in_insn (rtx, int); | |
397 | static void update_eliminable_offsets (void); | |
7bc980e1 | 398 | static void mark_not_eliminable (rtx, const_rtx, void *); |
0c20a65f | 399 | static void set_initial_elim_offsets (void); |
9f938de1 | 400 | static bool verify_initial_elim_offsets (void); |
0c20a65f AJ |
401 | static void set_initial_label_offsets (void); |
402 | static void set_offsets_for_label (rtx); | |
403 | static void init_elim_table (void); | |
404 | static void update_eliminables (HARD_REG_SET *); | |
405 | static void spill_hard_reg (unsigned int, int); | |
406 | static int finish_spills (int); | |
0c20a65f AJ |
407 | static void scan_paradoxical_subregs (rtx); |
408 | static void count_pseudo (int); | |
409 | static void order_regs_for_reload (struct insn_chain *); | |
410 | static void reload_as_needed (int); | |
7bc980e1 | 411 | static void forget_old_reloads_1 (rtx, const_rtx, void *); |
db4c7386 | 412 | static void forget_marked_reloads (regset); |
0c20a65f AJ |
413 | static int reload_reg_class_lower (const void *, const void *); |
414 | static void mark_reload_reg_in_use (unsigned int, int, enum reload_type, | |
415 | enum machine_mode); | |
416 | static void clear_reload_reg_in_use (unsigned int, int, enum reload_type, | |
417 | enum machine_mode); | |
418 | static int reload_reg_free_p (unsigned int, int, enum reload_type); | |
419 | static int reload_reg_free_for_value_p (int, int, int, enum reload_type, | |
420 | rtx, rtx, int, int); | |
421 | static int free_for_value_p (int, enum machine_mode, int, enum reload_type, | |
422 | rtx, rtx, int, int); | |
423 | static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type); | |
424 | static int allocate_reload_reg (struct insn_chain *, int, int); | |
425 | static int conflicts_with_override (rtx); | |
426 | static void failed_reload (rtx, int); | |
427 | static int set_reload_reg (int, int); | |
428 | static void choose_reload_regs_init (struct insn_chain *, rtx *); | |
429 | static void choose_reload_regs (struct insn_chain *); | |
430 | static void merge_assigned_reloads (rtx); | |
431 | static void emit_input_reload_insns (struct insn_chain *, struct reload *, | |
432 | rtx, int); | |
433 | static void emit_output_reload_insns (struct insn_chain *, struct reload *, | |
434 | int); | |
435 | static void do_input_reload (struct insn_chain *, struct reload *, int); | |
436 | static void do_output_reload (struct insn_chain *, struct reload *, int); | |
b5ba341f | 437 | static bool inherit_piecemeal_p (int, int); |
0c20a65f AJ |
438 | static void emit_reload_insns (struct insn_chain *); |
439 | static void delete_output_reload (rtx, int, int); | |
440 | static void delete_address_reloads (rtx, rtx); | |
441 | static void delete_address_reloads_1 (rtx, rtx, rtx); | |
442 | static rtx inc_for_reload (rtx, rtx, rtx, int); | |
2dfa9a87 | 443 | #ifdef AUTO_INC_DEC |
0c20a65f | 444 | static void add_auto_inc_notes (rtx, rtx); |
2dfa9a87 | 445 | #endif |
0c20a65f | 446 | static void copy_eh_notes (rtx, rtx); |
bf9a0db3 KH |
447 | static int reloads_conflict (int, int); |
448 | static rtx gen_reload (rtx, rtx, int, enum reload_type); | |
ff0d9879 | 449 | static rtx emit_insn_if_valid_for_reload (rtx); |
32131a9c | 450 | \f |
546b63fb RK |
451 | /* Initialize the reload pass once per compilation. */ |
452 | ||
32131a9c | 453 | void |
0c20a65f | 454 | init_reload (void) |
32131a9c | 455 | { |
b3694847 | 456 | int i; |
32131a9c RK |
457 | |
458 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
459 | Set spill_indirect_levels to the number of levels such addressing is | |
460 | permitted, zero if it is not permitted at all. */ | |
461 | ||
b3694847 | 462 | rtx tem |
38a448ca RH |
463 | = gen_rtx_MEM (Pmode, |
464 | gen_rtx_PLUS (Pmode, | |
c5c76735 JL |
465 | gen_rtx_REG (Pmode, |
466 | LAST_VIRTUAL_REGISTER + 1), | |
38a448ca | 467 | GEN_INT (4))); |
32131a9c RK |
468 | spill_indirect_levels = 0; |
469 | ||
470 | while (memory_address_p (QImode, tem)) | |
471 | { | |
472 | spill_indirect_levels++; | |
38a448ca | 473 | tem = gen_rtx_MEM (Pmode, tem); |
32131a9c RK |
474 | } |
475 | ||
476 | /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ | |
477 | ||
38a448ca | 478 | tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); |
32131a9c RK |
479 | indirect_symref_ok = memory_address_p (QImode, tem); |
480 | ||
481 | /* See if reg+reg is a valid (and offsettable) address. */ | |
482 | ||
65701fd2 | 483 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
57caa638 | 484 | { |
38a448ca RH |
485 | tem = gen_rtx_PLUS (Pmode, |
486 | gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), | |
487 | gen_rtx_REG (Pmode, i)); | |
c5c76735 | 488 | |
57caa638 RS |
489 | /* This way, we make sure that reg+reg is an offsettable address. */ |
490 | tem = plus_constant (tem, 4); | |
491 | ||
492 | if (memory_address_p (QImode, tem)) | |
493 | { | |
494 | double_reg_address_ok = 1; | |
495 | break; | |
496 | } | |
497 | } | |
32131a9c | 498 | |
0f41302f | 499 | /* Initialize obstack for our rtl allocation. */ |
32131a9c | 500 | gcc_obstack_init (&reload_obstack); |
703ad42b | 501 | reload_startobj = obstack_alloc (&reload_obstack, 0); |
f5d8c9f4 BS |
502 | |
503 | INIT_REG_SET (&spilled_pseudos); | |
504 | INIT_REG_SET (&pseudos_counted); | |
32131a9c RK |
505 | } |
506 | ||
cad6f7d0 BS |
507 | /* List of insn chains that are currently unused. */ |
508 | static struct insn_chain *unused_insn_chains = 0; | |
509 | ||
510 | /* Allocate an empty insn_chain structure. */ | |
511 | struct insn_chain * | |
0c20a65f | 512 | new_insn_chain (void) |
cad6f7d0 BS |
513 | { |
514 | struct insn_chain *c; | |
515 | ||
516 | if (unused_insn_chains == 0) | |
517 | { | |
703ad42b | 518 | c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain)); |
239a0f5b BS |
519 | INIT_REG_SET (&c->live_throughout); |
520 | INIT_REG_SET (&c->dead_or_set); | |
cad6f7d0 BS |
521 | } |
522 | else | |
523 | { | |
524 | c = unused_insn_chains; | |
525 | unused_insn_chains = c->next; | |
526 | } | |
527 | c->is_caller_save_insn = 0; | |
03acd8f8 | 528 | c->need_operand_change = 0; |
cad6f7d0 BS |
529 | c->need_reload = 0; |
530 | c->need_elim = 0; | |
531 | return c; | |
532 | } | |
533 | ||
7609e720 BS |
534 | /* Small utility function to set all regs in hard reg set TO which are |
535 | allocated to pseudos in regset FROM. */ | |
770ae6cc | 536 | |
7609e720 | 537 | void |
0c20a65f | 538 | compute_use_by_pseudos (HARD_REG_SET *to, regset from) |
7609e720 | 539 | { |
770ae6cc | 540 | unsigned int regno; |
a2041967 | 541 | reg_set_iterator rsi; |
770ae6cc | 542 | |
a2041967 KH |
543 | EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi) |
544 | { | |
545 | int r = reg_renumber[regno]; | |
a2041967 KH |
546 | |
547 | if (r < 0) | |
548 | { | |
549 | /* reload_combine uses the information from | |
6fb5fa3c | 550 | DF_RA_LIVE_IN (BASIC_BLOCK), which might still |
a2041967 KH |
551 | contain registers that have not actually been allocated |
552 | since they have an equivalence. */ | |
553 | gcc_assert (reload_completed); | |
554 | } | |
555 | else | |
09e18274 | 556 | add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r); |
a2041967 | 557 | } |
7609e720 | 558 | } |
f474c6f8 AO |
559 | |
560 | /* Replace all pseudos found in LOC with their corresponding | |
561 | equivalences. */ | |
562 | ||
563 | static void | |
0c20a65f | 564 | replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage) |
f474c6f8 AO |
565 | { |
566 | rtx x = *loc; | |
567 | enum rtx_code code; | |
568 | const char *fmt; | |
569 | int i, j; | |
570 | ||
571 | if (! x) | |
572 | return; | |
174fa2c4 | 573 | |
f474c6f8 AO |
574 | code = GET_CODE (x); |
575 | if (code == REG) | |
576 | { | |
ae0ed63a | 577 | unsigned int regno = REGNO (x); |
086fef9e AO |
578 | |
579 | if (regno < FIRST_PSEUDO_REGISTER) | |
f474c6f8 AO |
580 | return; |
581 | ||
582 | x = eliminate_regs (x, mem_mode, usage); | |
583 | if (x != *loc) | |
584 | { | |
585 | *loc = x; | |
ee960939 | 586 | replace_pseudos_in (loc, mem_mode, usage); |
f474c6f8 AO |
587 | return; |
588 | } | |
589 | ||
086fef9e AO |
590 | if (reg_equiv_constant[regno]) |
591 | *loc = reg_equiv_constant[regno]; | |
592 | else if (reg_equiv_mem[regno]) | |
593 | *loc = reg_equiv_mem[regno]; | |
594 | else if (reg_equiv_address[regno]) | |
595 | *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]); | |
f474c6f8 | 596 | else |
41374e13 NS |
597 | { |
598 | gcc_assert (!REG_P (regno_reg_rtx[regno]) | |
599 | || REGNO (regno_reg_rtx[regno]) != regno); | |
600 | *loc = regno_reg_rtx[regno]; | |
601 | } | |
f474c6f8 AO |
602 | |
603 | return; | |
604 | } | |
605 | else if (code == MEM) | |
606 | { | |
ee960939 | 607 | replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage); |
f474c6f8 AO |
608 | return; |
609 | } | |
174fa2c4 | 610 | |
f474c6f8 AO |
611 | /* Process each of our operands recursively. */ |
612 | fmt = GET_RTX_FORMAT (code); | |
613 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
614 | if (*fmt == 'e') | |
ee960939 | 615 | replace_pseudos_in (&XEXP (x, i), mem_mode, usage); |
f474c6f8 AO |
616 | else if (*fmt == 'E') |
617 | for (j = 0; j < XVECLEN (x, i); j++) | |
ee960939 | 618 | replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage); |
f474c6f8 AO |
619 | } |
620 | ||
ecaebb9e NS |
621 | /* Determine if the current function has an exception receiver block |
622 | that reaches the exit block via non-exceptional edges */ | |
623 | ||
624 | static bool | |
625 | has_nonexceptional_receiver (void) | |
626 | { | |
627 | edge e; | |
628 | edge_iterator ei; | |
629 | basic_block *tos, *worklist, bb; | |
630 | ||
631 | /* If we're not optimizing, then just err on the safe side. */ | |
632 | if (!optimize) | |
633 | return true; | |
634 | ||
635 | /* First determine which blocks can reach exit via normal paths. */ | |
636 | tos = worklist = xmalloc (sizeof (basic_block) * (n_basic_blocks + 1)); | |
637 | ||
638 | FOR_EACH_BB (bb) | |
639 | bb->flags &= ~BB_REACHABLE; | |
640 | ||
641 | /* Place the exit block on our worklist. */ | |
642 | EXIT_BLOCK_PTR->flags |= BB_REACHABLE; | |
643 | *tos++ = EXIT_BLOCK_PTR; | |
644 | ||
645 | /* Iterate: find everything reachable from what we've already seen. */ | |
646 | while (tos != worklist) | |
647 | { | |
648 | bb = *--tos; | |
649 | ||
650 | FOR_EACH_EDGE (e, ei, bb->preds) | |
651 | if (!(e->flags & EDGE_ABNORMAL)) | |
652 | { | |
653 | basic_block src = e->src; | |
654 | ||
655 | if (!(src->flags & BB_REACHABLE)) | |
656 | { | |
657 | src->flags |= BB_REACHABLE; | |
658 | *tos++ = src; | |
659 | } | |
660 | } | |
661 | } | |
662 | free (worklist); | |
663 | ||
664 | /* Now see if there's a reachable block with an exceptional incoming | |
665 | edge. */ | |
666 | FOR_EACH_BB (bb) | |
667 | if (bb->flags & BB_REACHABLE) | |
668 | FOR_EACH_EDGE (e, ei, bb->preds) | |
669 | if (e->flags & EDGE_ABNORMAL) | |
670 | return true; | |
671 | ||
672 | /* No exceptional block reached exit unexceptionally. */ | |
673 | return false; | |
674 | } | |
675 | ||
03acd8f8 | 676 | \f |
1e5bd841 BS |
677 | /* Global variables used by reload and its subroutines. */ |
678 | ||
1e5bd841 BS |
679 | /* Set during calculate_needs if an insn needs register elimination. */ |
680 | static int something_needs_elimination; | |
cb2afeb3 | 681 | /* Set during calculate_needs if an insn needs an operand changed. */ |
cf0fa607 | 682 | static int something_needs_operands_changed; |
1e5bd841 | 683 | |
1e5bd841 BS |
684 | /* Nonzero means we couldn't get enough spill regs. */ |
685 | static int failure; | |
686 | ||
546b63fb | 687 | /* Main entry point for the reload pass. |
32131a9c RK |
688 | |
689 | FIRST is the first insn of the function being compiled. | |
690 | ||
691 | GLOBAL nonzero means we were called from global_alloc | |
692 | and should attempt to reallocate any pseudoregs that we | |
693 | displace from hard regs we will use for reloads. | |
694 | If GLOBAL is zero, we do not have enough information to do that, | |
695 | so any pseudo reg that is spilled must go to the stack. | |
696 | ||
5352b11a RS |
697 | Return value is nonzero if reload failed |
698 | and we must not do any more for this function. */ | |
699 | ||
700 | int | |
0c20a65f | 701 | reload (rtx first, int global) |
32131a9c | 702 | { |
b3694847 SS |
703 | int i; |
704 | rtx insn; | |
705 | struct elim_table *ep; | |
e0082a72 | 706 | basic_block bb; |
32131a9c | 707 | |
32131a9c RK |
708 | /* Make sure even insns with volatile mem refs are recognizable. */ |
709 | init_recog (); | |
710 | ||
1e5bd841 BS |
711 | failure = 0; |
712 | ||
703ad42b | 713 | reload_firstobj = obstack_alloc (&reload_obstack, 0); |
cad6f7d0 | 714 | |
437a710d BS |
715 | /* Make sure that the last insn in the chain |
716 | is not something that needs reloading. */ | |
2e040219 | 717 | emit_note (NOTE_INSN_DELETED); |
437a710d | 718 | |
32131a9c RK |
719 | /* Enable find_equiv_reg to distinguish insns made by reload. */ |
720 | reload_first_uid = get_max_uid (); | |
721 | ||
0dadecf6 RK |
722 | #ifdef SECONDARY_MEMORY_NEEDED |
723 | /* Initialize the secondary memory table. */ | |
724 | clear_secondary_mem (); | |
725 | #endif | |
726 | ||
32131a9c | 727 | /* We don't have a stack slot for any spill reg yet. */ |
703ad42b KG |
728 | memset (spill_stack_slot, 0, sizeof spill_stack_slot); |
729 | memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width); | |
32131a9c | 730 | |
a8efe40d RK |
731 | /* Initialize the save area information for caller-save, in case some |
732 | are needed. */ | |
733 | init_save_areas (); | |
a8fdc208 | 734 | |
32131a9c RK |
735 | /* Compute which hard registers are now in use |
736 | as homes for pseudo registers. | |
737 | This is done here rather than (eg) in global_alloc | |
738 | because this point is reached even if not optimizing. */ | |
32131a9c RK |
739 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
740 | mark_home_live (i); | |
741 | ||
ecaebb9e NS |
742 | /* A function that has a nonlocal label that can reach the exit |
743 | block via non-exceptional paths must save all call-saved | |
8dddd002 | 744 | registers. */ |
ecaebb9e NS |
745 | if (current_function_calls_unwind_init |
746 | || (current_function_has_nonlocal_label | |
747 | && has_nonexceptional_receiver ())) | |
8dddd002 | 748 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
2a3e384f | 749 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) |
6fb5fa3c | 750 | df_set_regs_ever_live (i, true); |
8dddd002 | 751 | |
32131a9c RK |
752 | /* Find all the pseudo registers that didn't get hard regs |
753 | but do have known equivalent constants or memory slots. | |
754 | These include parameters (known equivalent to parameter slots) | |
755 | and cse'd or loop-moved constant memory addresses. | |
756 | ||
757 | Record constant equivalents in reg_equiv_constant | |
758 | so they will be substituted by find_reloads. | |
759 | Record memory equivalents in reg_mem_equiv so they can | |
760 | be substituted eventually by altering the REG-rtx's. */ | |
761 | ||
5ed6ace5 MD |
762 | reg_equiv_constant = XCNEWVEC (rtx, max_regno); |
763 | reg_equiv_invariant = XCNEWVEC (rtx, max_regno); | |
764 | reg_equiv_mem = XCNEWVEC (rtx, max_regno); | |
3f1e3e70 | 765 | reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno); |
5ed6ace5 MD |
766 | reg_equiv_address = XCNEWVEC (rtx, max_regno); |
767 | reg_max_ref_width = XCNEWVEC (unsigned int, max_regno); | |
768 | reg_old_renumber = XCNEWVEC (short, max_regno); | |
4e135bdd | 769 | memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); |
5ed6ace5 MD |
770 | pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno); |
771 | pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno); | |
32131a9c | 772 | |
03acd8f8 | 773 | CLEAR_HARD_REG_SET (bad_spill_regs_global); |
56f58d3a | 774 | |
d754127f ILT |
775 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent |
776 | to. Also find all paradoxical subregs and find largest such for | |
777 | each pseudo. */ | |
32131a9c | 778 | |
2b49ee39 | 779 | num_eliminable_invariants = 0; |
32131a9c RK |
780 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
781 | { | |
782 | rtx set = single_set (insn); | |
783 | ||
3d17d93d AO |
784 | /* We may introduce USEs that we want to remove at the end, so |
785 | we'll mark them with QImode. Make sure there are no | |
786 | previously-marked insns left by say regmove. */ | |
787 | if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE | |
788 | && GET_MODE (insn) != VOIDmode) | |
789 | PUT_MODE (insn, VOIDmode); | |
790 | ||
d7f88d86 BS |
791 | if (INSN_P (insn)) |
792 | scan_paradoxical_subregs (PATTERN (insn)); | |
793 | ||
f8cfc6aa | 794 | if (set != 0 && REG_P (SET_DEST (set))) |
32131a9c | 795 | { |
fb3821f7 | 796 | rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
d7f88d86 BS |
797 | rtx x; |
798 | ||
799 | if (! note) | |
800 | continue; | |
801 | ||
802 | i = REGNO (SET_DEST (set)); | |
803 | x = XEXP (note, 0); | |
804 | ||
805 | if (i <= LAST_VIRTUAL_REGISTER) | |
806 | continue; | |
807 | ||
808 | if (! function_invariant_p (x) | |
809 | || ! flag_pic | |
810 | /* A function invariant is often CONSTANT_P but may | |
811 | include a register. We promise to only pass | |
812 | CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ | |
813 | || (CONSTANT_P (x) | |
814 | && LEGITIMATE_PIC_OPERAND_P (x))) | |
32131a9c | 815 | { |
d7f88d86 BS |
816 | /* It can happen that a REG_EQUIV note contains a MEM |
817 | that is not a legitimate memory operand. As later | |
818 | stages of reload assume that all addresses found | |
819 | in the reg_equiv_* arrays were originally legitimate, | |
820 | we ignore such REG_EQUIV notes. */ | |
821 | if (memory_operand (x, VOIDmode)) | |
32131a9c | 822 | { |
d7f88d86 BS |
823 | /* Always unshare the equivalence, so we can |
824 | substitute into this insn without touching the | |
825 | equivalence. */ | |
826 | reg_equiv_memory_loc[i] = copy_rtx (x); | |
827 | } | |
828 | else if (function_invariant_p (x)) | |
829 | { | |
830 | if (GET_CODE (x) == PLUS) | |
956d6950 | 831 | { |
d7f88d86 BS |
832 | /* This is PLUS of frame pointer and a constant, |
833 | and might be shared. Unshare it. */ | |
ab156144 | 834 | reg_equiv_invariant[i] = copy_rtx (x); |
d7f88d86 | 835 | num_eliminable_invariants++; |
956d6950 | 836 | } |
ab156144 | 837 | else if (x == frame_pointer_rtx || x == arg_pointer_rtx) |
32131a9c | 838 | { |
ab156144 | 839 | reg_equiv_invariant[i] = x; |
d7f88d86 | 840 | num_eliminable_invariants++; |
32131a9c | 841 | } |
d7f88d86 BS |
842 | else if (LEGITIMATE_CONSTANT_P (x)) |
843 | reg_equiv_constant[i] = x; | |
32131a9c | 844 | else |
d7f88d86 BS |
845 | { |
846 | reg_equiv_memory_loc[i] | |
847 | = force_const_mem (GET_MODE (SET_DEST (set)), x); | |
848 | if (! reg_equiv_memory_loc[i]) | |
849 | reg_equiv_init[i] = NULL_RTX; | |
850 | } | |
851 | } | |
852 | else | |
853 | { | |
854 | reg_equiv_init[i] = NULL_RTX; | |
855 | continue; | |
32131a9c RK |
856 | } |
857 | } | |
d7f88d86 BS |
858 | else |
859 | reg_equiv_init[i] = NULL_RTX; | |
32131a9c | 860 | } |
32131a9c RK |
861 | } |
862 | ||
d7f88d86 BS |
863 | if (dump_file) |
864 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
865 | if (reg_equiv_init[i]) | |
866 | { | |
867 | fprintf (dump_file, "init_insns for %u: ", i); | |
868 | print_inline_rtx (dump_file, reg_equiv_init[i], 20); | |
869 | fprintf (dump_file, "\n"); | |
870 | } | |
871 | ||
09dd1133 | 872 | init_elim_table (); |
32131a9c | 873 | |
4cc0fdd2 JDA |
874 | first_label_num = get_first_label_num (); |
875 | num_labels = max_label_num () - first_label_num; | |
32131a9c RK |
876 | |
877 | /* Allocate the tables used to store offset information at labels. */ | |
a68d4b75 BK |
878 | /* We used to use alloca here, but the size of what it would try to |
879 | allocate would occasionally cause it to exceed the stack limit and | |
880 | cause a core dump. */ | |
5ed6ace5 MD |
881 | offsets_known_at = XNEWVEC (char, num_labels); |
882 | offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT)); | |
32131a9c | 883 | |
32131a9c RK |
884 | /* Alter each pseudo-reg rtx to contain its hard reg number. |
885 | Assign stack slots to the pseudos that lack hard regs or equivalents. | |
886 | Do not touch virtual registers. */ | |
887 | ||
888 | for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) | |
889 | alter_reg (i, -1); | |
890 | ||
32131a9c RK |
891 | /* If we have some registers we think can be eliminated, scan all insns to |
892 | see if there is an insn that sets one of these registers to something | |
893 | other than itself plus a constant. If so, the register cannot be | |
894 | eliminated. Doing this scan here eliminates an extra pass through the | |
895 | main reload loop in the most common case where register elimination | |
896 | cannot be done. */ | |
897 | for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) | |
4b4bf941 | 898 | if (INSN_P (insn)) |
84832317 | 899 | note_stores (PATTERN (insn), mark_not_eliminable, NULL); |
32131a9c | 900 | |
18a90182 BS |
901 | maybe_fix_stack_asms (); |
902 | ||
03acd8f8 BS |
903 | insns_need_reload = 0; |
904 | something_needs_elimination = 0; | |
05d10675 | 905 | |
4079cd63 JW |
906 | /* Initialize to -1, which means take the first spill register. */ |
907 | last_spill_reg = -1; | |
908 | ||
32131a9c | 909 | /* Spill any hard regs that we know we can't eliminate. */ |
03acd8f8 | 910 | CLEAR_HARD_REG_SET (used_spill_regs); |
4ab51fb5 R |
911 | /* There can be multiple ways to eliminate a register; |
912 | they should be listed adjacently. | |
913 | Elimination for any register fails only if all possible ways fail. */ | |
914 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ) | |
915 | { | |
916 | int from = ep->from; | |
917 | int can_eliminate = 0; | |
918 | do | |
919 | { | |
920 | can_eliminate |= ep->can_eliminate; | |
921 | ep++; | |
922 | } | |
923 | while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from); | |
924 | if (! can_eliminate) | |
925 | spill_hard_reg (from, 1); | |
926 | } | |
9ff3516a RK |
927 | |
928 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
929 | if (frame_pointer_needed) | |
e04ca094 | 930 | spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1); |
9ff3516a | 931 | #endif |
e04ca094 | 932 | finish_spills (global); |
7609e720 | 933 | |
f1db3576 JL |
934 | /* From now on, we may need to generate moves differently. We may also |
935 | allow modifications of insns which cause them to not be recognized. | |
936 | Any such modifications will be cleaned up during reload itself. */ | |
b2f15f94 RK |
937 | reload_in_progress = 1; |
938 | ||
32131a9c RK |
939 | /* This loop scans the entire function each go-round |
940 | and repeats until one repetition spills no additional hard regs. */ | |
03acd8f8 | 941 | for (;;) |
32131a9c | 942 | { |
03acd8f8 BS |
943 | int something_changed; |
944 | int did_spill; | |
03acd8f8 | 945 | HOST_WIDE_INT starting_frame_size; |
32131a9c | 946 | |
7657bf2f JW |
947 | starting_frame_size = get_frame_size (); |
948 | ||
09dd1133 | 949 | set_initial_elim_offsets (); |
1f3b1e1a | 950 | set_initial_label_offsets (); |
03acd8f8 | 951 | |
32131a9c RK |
952 | /* For each pseudo register that has an equivalent location defined, |
953 | try to eliminate any eliminable registers (such as the frame pointer) | |
954 | assuming initial offsets for the replacement register, which | |
955 | is the normal case. | |
956 | ||
957 | If the resulting location is directly addressable, substitute | |
958 | the MEM we just got directly for the old REG. | |
959 | ||
960 | If it is not addressable but is a constant or the sum of a hard reg | |
961 | and constant, it is probably not addressable because the constant is | |
962 | out of range, in that case record the address; we will generate | |
963 | hairy code to compute the address in a register each time it is | |
6491dbbb RK |
964 | needed. Similarly if it is a hard register, but one that is not |
965 | valid as an address register. | |
32131a9c RK |
966 | |
967 | If the location is not addressable, but does not have one of the | |
968 | above forms, assign a stack slot. We have to do this to avoid the | |
969 | potential of producing lots of reloads if, e.g., a location involves | |
970 | a pseudo that didn't get a hard register and has an equivalent memory | |
971 | location that also involves a pseudo that didn't get a hard register. | |
972 | ||
973 | Perhaps at some point we will improve reload_when_needed handling | |
974 | so this problem goes away. But that's very hairy. */ | |
975 | ||
976 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
977 | if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) | |
978 | { | |
1914f5da | 979 | rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); |
32131a9c RK |
980 | |
981 | if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), | |
982 | XEXP (x, 0))) | |
983 | reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; | |
1f663989 | 984 | else if (CONSTANT_P (XEXP (x, 0)) |
f8cfc6aa | 985 | || (REG_P (XEXP (x, 0)) |
6491dbbb | 986 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) |
32131a9c | 987 | || (GET_CODE (XEXP (x, 0)) == PLUS |
f8cfc6aa | 988 | && REG_P (XEXP (XEXP (x, 0), 0)) |
32131a9c RK |
989 | && (REGNO (XEXP (XEXP (x, 0), 0)) |
990 | < FIRST_PSEUDO_REGISTER) | |
1f663989 | 991 | && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) |
32131a9c RK |
992 | reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; |
993 | else | |
994 | { | |
995 | /* Make a new stack slot. Then indicate that something | |
a8fdc208 | 996 | changed so we go back and recompute offsets for |
32131a9c RK |
997 | eliminable registers because the allocation of memory |
998 | below might change some offset. reg_equiv_{mem,address} | |
999 | will be set up for this pseudo on the next pass around | |
1000 | the loop. */ | |
1001 | reg_equiv_memory_loc[i] = 0; | |
1002 | reg_equiv_init[i] = 0; | |
1003 | alter_reg (i, -1); | |
32131a9c RK |
1004 | } |
1005 | } | |
a8fdc208 | 1006 | |
437a710d BS |
1007 | if (caller_save_needed) |
1008 | setup_save_areas (); | |
1009 | ||
03acd8f8 | 1010 | /* If we allocated another stack slot, redo elimination bookkeeping. */ |
437a710d | 1011 | if (starting_frame_size != get_frame_size ()) |
32131a9c | 1012 | continue; |
970af867 NS |
1013 | if (starting_frame_size && cfun->stack_alignment_needed) |
1014 | { | |
1015 | /* If we have a stack frame, we must align it now. The | |
1016 | stack size may be a part of the offset computation for | |
1017 | register elimination. So if this changes the stack size, | |
1018 | then repeat the elimination bookkeeping. We don't | |
1019 | realign when there is no stack, as that will cause a | |
1020 | stack frame when none is needed should | |
1021 | STARTING_FRAME_OFFSET not be already aligned to | |
1022 | STACK_BOUNDARY. */ | |
1023 | assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed); | |
1024 | if (starting_frame_size != get_frame_size ()) | |
1025 | continue; | |
1026 | } | |
32131a9c | 1027 | |
437a710d | 1028 | if (caller_save_needed) |
a8efe40d | 1029 | { |
437a710d BS |
1030 | save_call_clobbered_regs (); |
1031 | /* That might have allocated new insn_chain structures. */ | |
703ad42b | 1032 | reload_firstobj = obstack_alloc (&reload_obstack, 0); |
a8efe40d RK |
1033 | } |
1034 | ||
03acd8f8 BS |
1035 | calculate_needs_all_insns (global); |
1036 | ||
f5d8c9f4 | 1037 | CLEAR_REG_SET (&spilled_pseudos); |
03acd8f8 BS |
1038 | did_spill = 0; |
1039 | ||
1040 | something_changed = 0; | |
32131a9c | 1041 | |
0dadecf6 RK |
1042 | /* If we allocated any new memory locations, make another pass |
1043 | since it might have changed elimination offsets. */ | |
1044 | if (starting_frame_size != get_frame_size ()) | |
1045 | something_changed = 1; | |
1046 | ||
9f938de1 UW |
1047 | /* Even if the frame size remained the same, we might still have |
1048 | changed elimination offsets, e.g. if find_reloads called | |
1049 | force_const_mem requiring the back end to allocate a constant | |
1050 | pool base register that needs to be saved on the stack. */ | |
1051 | else if (!verify_initial_elim_offsets ()) | |
1052 | something_changed = 1; | |
1053 | ||
09dd1133 BS |
1054 | { |
1055 | HARD_REG_SET to_spill; | |
1056 | CLEAR_HARD_REG_SET (to_spill); | |
1057 | update_eliminables (&to_spill); | |
247140ea | 1058 | AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill); |
184f4c56 | 1059 | |
09dd1133 BS |
1060 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1061 | if (TEST_HARD_REG_BIT (to_spill, i)) | |
32131a9c | 1062 | { |
e04ca094 | 1063 | spill_hard_reg (i, 1); |
03acd8f8 | 1064 | did_spill = 1; |
8f5db3c1 JL |
1065 | |
1066 | /* Regardless of the state of spills, if we previously had | |
e591c83d | 1067 | a register that we thought we could eliminate, but now can |
8f5db3c1 JL |
1068 | not eliminate, we must run another pass. |
1069 | ||
1070 | Consider pseudos which have an entry in reg_equiv_* which | |
1071 | reference an eliminable register. We must make another pass | |
1072 | to update reg_equiv_* so that we do not substitute in the | |
1073 | old value from when we thought the elimination could be | |
1074 | performed. */ | |
1075 | something_changed = 1; | |
32131a9c | 1076 | } |
09dd1133 | 1077 | } |
9ff3516a | 1078 | |
e04ca094 | 1079 | select_reload_regs (); |
e483bf9c BS |
1080 | if (failure) |
1081 | goto failed; | |
437a710d | 1082 | |
e483bf9c | 1083 | if (insns_need_reload != 0 || did_spill) |
e04ca094 | 1084 | something_changed |= finish_spills (global); |
7609e720 | 1085 | |
03acd8f8 BS |
1086 | if (! something_changed) |
1087 | break; | |
1088 | ||
1089 | if (caller_save_needed) | |
7609e720 | 1090 | delete_caller_save_insns (); |
f5d8c9f4 BS |
1091 | |
1092 | obstack_free (&reload_obstack, reload_firstobj); | |
32131a9c RK |
1093 | } |
1094 | ||
1095 | /* If global-alloc was run, notify it of any register eliminations we have | |
1096 | done. */ | |
1097 | if (global) | |
1098 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1099 | if (ep->can_eliminate) | |
1100 | mark_elimination (ep->from, ep->to); | |
1101 | ||
32131a9c RK |
1102 | /* If a pseudo has no hard reg, delete the insns that made the equivalence. |
1103 | If that insn didn't set the register (i.e., it copied the register to | |
1104 | memory), just delete that insn instead of the equivalencing insn plus | |
1105 | anything now dead. If we call delete_dead_insn on that insn, we may | |
135eb61c | 1106 | delete the insn that actually sets the register if the register dies |
32131a9c RK |
1107 | there and that is incorrect. */ |
1108 | ||
1109 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
135eb61c R |
1110 | { |
1111 | if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) | |
1112 | { | |
1113 | rtx list; | |
1114 | for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) | |
1115 | { | |
1116 | rtx equiv_insn = XEXP (list, 0); | |
78571511 RK |
1117 | |
1118 | /* If we already deleted the insn or if it may trap, we can't | |
1119 | delete it. The latter case shouldn't happen, but can | |
1120 | if an insn has a variable address, gets a REG_EH_REGION | |
569b7f6a | 1121 | note added to it, and then gets converted into a load |
78571511 | 1122 | from a constant address. */ |
4b4bf941 | 1123 | if (NOTE_P (equiv_insn) |
78571511 RK |
1124 | || can_throw_internal (equiv_insn)) |
1125 | ; | |
1126 | else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) | |
135eb61c R |
1127 | delete_dead_insn (equiv_insn); |
1128 | else | |
6773e15f | 1129 | SET_INSN_DELETED (equiv_insn); |
135eb61c R |
1130 | } |
1131 | } | |
1132 | } | |
32131a9c RK |
1133 | |
1134 | /* Use the reload registers where necessary | |
1135 | by generating move instructions to move the must-be-register | |
1136 | values into or out of the reload registers. */ | |
1137 | ||
03acd8f8 BS |
1138 | if (insns_need_reload != 0 || something_needs_elimination |
1139 | || something_needs_operands_changed) | |
c47f5ea5 | 1140 | { |
102870fb | 1141 | HOST_WIDE_INT old_frame_size = get_frame_size (); |
c47f5ea5 | 1142 | |
e04ca094 | 1143 | reload_as_needed (global); |
c47f5ea5 | 1144 | |
41374e13 | 1145 | gcc_assert (old_frame_size == get_frame_size ()); |
c47f5ea5 | 1146 | |
9f938de1 | 1147 | gcc_assert (verify_initial_elim_offsets ()); |
c47f5ea5 | 1148 | } |
32131a9c | 1149 | |
2a1f8b6b | 1150 | /* If we were able to eliminate the frame pointer, show that it is no |
546b63fb | 1151 | longer live at the start of any basic block. If it ls live by |
2a1f8b6b RK |
1152 | virtue of being in a pseudo, that pseudo will be marked live |
1153 | and hence the frame pointer will be known to be live via that | |
1154 | pseudo. */ | |
1155 | ||
1156 | if (! frame_pointer_needed) | |
e0082a72 | 1157 | FOR_EACH_BB (bb) |
6fb5fa3c DB |
1158 | { |
1159 | bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM); | |
1160 | bitmap_clear_bit (df_get_live_top (bb), HARD_FRAME_POINTER_REGNUM); | |
1161 | } | |
1162 | ||
0e61db61 NS |
1163 | /* Come here (with failure set nonzero) if we can't get enough spill |
1164 | regs. */ | |
5352b11a RS |
1165 | failed: |
1166 | ||
f5d8c9f4 | 1167 | CLEAR_REG_SET (&spilled_pseudos); |
a3ec87a8 RS |
1168 | reload_in_progress = 0; |
1169 | ||
32131a9c RK |
1170 | /* Now eliminate all pseudo regs by modifying them into |
1171 | their equivalent memory references. | |
1172 | The REG-rtx's for the pseudos are modified in place, | |
1173 | so all insns that used to refer to them now refer to memory. | |
1174 | ||
1175 | For a reg that has a reg_equiv_address, all those insns | |
1176 | were changed by reloading so that no insns refer to it any longer; | |
1177 | but the DECL_RTL of a variable decl may refer to it, | |
1178 | and if so this causes the debugging info to mention the variable. */ | |
1179 | ||
1180 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1181 | { | |
1182 | rtx addr = 0; | |
9ec36da5 JL |
1183 | |
1184 | if (reg_equiv_mem[i]) | |
1185 | addr = XEXP (reg_equiv_mem[i], 0); | |
1186 | ||
32131a9c RK |
1187 | if (reg_equiv_address[i]) |
1188 | addr = reg_equiv_address[i]; | |
9ec36da5 | 1189 | |
32131a9c RK |
1190 | if (addr) |
1191 | { | |
1192 | if (reg_renumber[i] < 0) | |
1193 | { | |
1194 | rtx reg = regno_reg_rtx[i]; | |
173b24b9 | 1195 | |
5a63e069 | 1196 | REG_USERVAR_P (reg) = 0; |
ef178af3 | 1197 | PUT_CODE (reg, MEM); |
32131a9c | 1198 | XEXP (reg, 0) = addr; |
173b24b9 RK |
1199 | if (reg_equiv_memory_loc[i]) |
1200 | MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]); | |
1201 | else | |
1202 | { | |
389fdba0 | 1203 | MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0; |
173b24b9 RK |
1204 | MEM_ATTRS (reg) = 0; |
1205 | } | |
be0c514c | 1206 | MEM_NOTRAP_P (reg) = 1; |
32131a9c RK |
1207 | } |
1208 | else if (reg_equiv_mem[i]) | |
1209 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1210 | } | |
1211 | } | |
1212 | ||
2ae74651 JL |
1213 | /* We must set reload_completed now since the cleanup_subreg_operands call |
1214 | below will re-recognize each insn and reload may have generated insns | |
1215 | which are only valid during and after reload. */ | |
1216 | reload_completed = 1; | |
1217 | ||
bd695e1e RH |
1218 | /* Make a pass over all the insns and delete all USEs which we inserted |
1219 | only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED | |
41e34bab DJ |
1220 | notes. Delete all CLOBBER insns, except those that refer to the return |
1221 | value and the special mem:BLK CLOBBERs added to prevent the scheduler | |
1222 | from misarranging variable-array code, and simplify (subreg (reg)) | |
260f91c2 DJ |
1223 | operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they |
1224 | are no longer useful or accurate. Strip and regenerate REG_INC notes | |
1225 | that may have been moved around. */ | |
32131a9c RK |
1226 | |
1227 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 1228 | if (INSN_P (insn)) |
32131a9c | 1229 | { |
6764d250 | 1230 | rtx *pnote; |
32131a9c | 1231 | |
4b4bf941 | 1232 | if (CALL_P (insn)) |
ee960939 OH |
1233 | replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn), |
1234 | VOIDmode, CALL_INSN_FUNCTION_USAGE (insn)); | |
f474c6f8 | 1235 | |
0304f787 | 1236 | if ((GET_CODE (PATTERN (insn)) == USE |
3d17d93d AO |
1237 | /* We mark with QImode USEs introduced by reload itself. */ |
1238 | && (GET_MODE (insn) == QImode | |
1239 | || find_reg_note (insn, REG_EQUAL, NULL_RTX))) | |
bd695e1e | 1240 | || (GET_CODE (PATTERN (insn)) == CLOBBER |
3c0cb5de | 1241 | && (!MEM_P (XEXP (PATTERN (insn), 0)) |
41e34bab DJ |
1242 | || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode |
1243 | || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH | |
0c20a65f | 1244 | && XEXP (XEXP (PATTERN (insn), 0), 0) |
41e34bab | 1245 | != stack_pointer_rtx)) |
f8cfc6aa | 1246 | && (!REG_P (XEXP (PATTERN (insn), 0)) |
bd695e1e | 1247 | || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) |
b60a8416 | 1248 | { |
e5eac8ef | 1249 | delete_insn (insn); |
b60a8416 R |
1250 | continue; |
1251 | } | |
6764d250 | 1252 | |
ee960939 OH |
1253 | /* Some CLOBBERs may survive until here and still reference unassigned |
1254 | pseudos with const equivalent, which may in turn cause ICE in later | |
1255 | passes if the reference remains in place. */ | |
1256 | if (GET_CODE (PATTERN (insn)) == CLOBBER) | |
1257 | replace_pseudos_in (& XEXP (PATTERN (insn), 0), | |
1258 | VOIDmode, PATTERN (insn)); | |
1259 | ||
17ac08e2 ILT |
1260 | /* Discard obvious no-ops, even without -O. This optimization |
1261 | is fast and doesn't interfere with debugging. */ | |
1262 | if (NONJUMP_INSN_P (insn) | |
1263 | && GET_CODE (PATTERN (insn)) == SET | |
1264 | && REG_P (SET_SRC (PATTERN (insn))) | |
1265 | && REG_P (SET_DEST (PATTERN (insn))) | |
1266 | && (REGNO (SET_SRC (PATTERN (insn))) | |
1267 | == REGNO (SET_DEST (PATTERN (insn))))) | |
1268 | { | |
1269 | delete_insn (insn); | |
1270 | continue; | |
1271 | } | |
1272 | ||
6764d250 BS |
1273 | pnote = ®_NOTES (insn); |
1274 | while (*pnote != 0) | |
32131a9c | 1275 | { |
6764d250 | 1276 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
80599fd9 | 1277 | || REG_NOTE_KIND (*pnote) == REG_UNUSED |
2dfa9a87 | 1278 | || REG_NOTE_KIND (*pnote) == REG_INC |
80599fd9 | 1279 | || REG_NOTE_KIND (*pnote) == REG_RETVAL |
6fb5fa3c | 1280 | || REG_NOTE_KIND (*pnote) == REG_LIBCALL_ID |
80599fd9 | 1281 | || REG_NOTE_KIND (*pnote) == REG_LIBCALL) |
6764d250 BS |
1282 | *pnote = XEXP (*pnote, 1); |
1283 | else | |
1284 | pnote = &XEXP (*pnote, 1); | |
32131a9c | 1285 | } |
0304f787 | 1286 | |
2dfa9a87 MH |
1287 | #ifdef AUTO_INC_DEC |
1288 | add_auto_inc_notes (insn, PATTERN (insn)); | |
1289 | #endif | |
1290 | ||
5d8a5434 | 1291 | /* Simplify (subreg (reg)) if it appears as an operand. */ |
0304f787 | 1292 | cleanup_subreg_operands (insn); |
5d8a5434 JJ |
1293 | |
1294 | /* Clean up invalid ASMs so that they don't confuse later passes. | |
1295 | See PR 21299. */ | |
1296 | if (asm_noperands (PATTERN (insn)) >= 0) | |
1297 | { | |
1298 | extract_insn (insn); | |
1299 | if (!constrain_operands (1)) | |
1300 | { | |
1301 | error_for_asm (insn, | |
1302 | "%<asm%> operand has impossible constraints"); | |
1303 | delete_insn (insn); | |
1304 | continue; | |
1305 | } | |
1306 | } | |
b60a8416 | 1307 | } |
32131a9c | 1308 | |
ab87f8c8 JL |
1309 | /* If we are doing stack checking, give a warning if this function's |
1310 | frame size is larger than we expect. */ | |
1311 | if (flag_stack_check && ! STACK_CHECK_BUILTIN) | |
1312 | { | |
1313 | HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; | |
05d10675 BS |
1314 | static int verbose_warned = 0; |
1315 | ||
ab87f8c8 | 1316 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
6fb5fa3c | 1317 | if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i]) |
ab87f8c8 JL |
1318 | size += UNITS_PER_WORD; |
1319 | ||
1320 | if (size > STACK_CHECK_MAX_FRAME_SIZE) | |
05d10675 | 1321 | { |
d4ee4d25 | 1322 | warning (0, "frame size too large for reliable stack checking"); |
ab87f8c8 JL |
1323 | if (! verbose_warned) |
1324 | { | |
d4ee4d25 | 1325 | warning (0, "try reducing the number of local variables"); |
ab87f8c8 JL |
1326 | verbose_warned = 1; |
1327 | } | |
1328 | } | |
1329 | } | |
1330 | ||
32131a9c | 1331 | /* Indicate that we no longer have known memory locations or constants. */ |
58d9f9d9 JL |
1332 | if (reg_equiv_constant) |
1333 | free (reg_equiv_constant); | |
ab156144 RH |
1334 | if (reg_equiv_invariant) |
1335 | free (reg_equiv_invariant); | |
32131a9c | 1336 | reg_equiv_constant = 0; |
ab156144 | 1337 | reg_equiv_invariant = 0; |
43b373a2 | 1338 | VEC_free (rtx, gc, reg_equiv_memory_loc_vec); |
32131a9c | 1339 | reg_equiv_memory_loc = 0; |
5352b11a | 1340 | |
4cc0fdd2 JDA |
1341 | if (offsets_known_at) |
1342 | free (offsets_known_at); | |
1343 | if (offsets_at) | |
1344 | free (offsets_at); | |
a68d4b75 | 1345 | |
3f1e3e70 AO |
1346 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1347 | if (reg_equiv_alt_mem_list[i]) | |
1348 | free_EXPR_LIST_list (®_equiv_alt_mem_list[i]); | |
1349 | free (reg_equiv_alt_mem_list); | |
1350 | ||
56a65848 | 1351 | free (reg_equiv_mem); |
d7f88d86 | 1352 | reg_equiv_init = 0; |
56a65848 DB |
1353 | free (reg_equiv_address); |
1354 | free (reg_max_ref_width); | |
03acd8f8 BS |
1355 | free (reg_old_renumber); |
1356 | free (pseudo_previous_regs); | |
1357 | free (pseudo_forbidden_regs); | |
56a65848 | 1358 | |
8b4f9969 JW |
1359 | CLEAR_HARD_REG_SET (used_spill_regs); |
1360 | for (i = 0; i < n_spills; i++) | |
1361 | SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); | |
1362 | ||
7609e720 BS |
1363 | /* Free all the insn_chain structures at once. */ |
1364 | obstack_free (&reload_obstack, reload_startobj); | |
1365 | unused_insn_chains = 0; | |
f1330226 | 1366 | fixup_abnormal_edges (); |
7609e720 | 1367 | |
e16e3291 UW |
1368 | /* Replacing pseudos with their memory equivalents might have |
1369 | created shared rtx. Subsequent passes would get confused | |
1370 | by this, so unshare everything here. */ | |
1371 | unshare_all_rtl_again (first); | |
1372 | ||
b483cfb7 EB |
1373 | #ifdef STACK_BOUNDARY |
1374 | /* init_emit has set the alignment of the hard frame pointer | |
1375 | to STACK_BOUNDARY. It is very likely no longer valid if | |
1376 | the hard frame pointer was used for register allocation. */ | |
1377 | if (!frame_pointer_needed) | |
1378 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; | |
1379 | #endif | |
1380 | ||
5352b11a | 1381 | return failure; |
32131a9c | 1382 | } |
1e5bd841 | 1383 | |
18a90182 BS |
1384 | /* Yet another special case. Unfortunately, reg-stack forces people to |
1385 | write incorrect clobbers in asm statements. These clobbers must not | |
1386 | cause the register to appear in bad_spill_regs, otherwise we'll call | |
1387 | fatal_insn later. We clear the corresponding regnos in the live | |
1388 | register sets to avoid this. | |
1389 | The whole thing is rather sick, I'm afraid. */ | |
efc9bd41 | 1390 | |
18a90182 | 1391 | static void |
0c20a65f | 1392 | maybe_fix_stack_asms (void) |
18a90182 BS |
1393 | { |
1394 | #ifdef STACK_REGS | |
392dccb7 | 1395 | const char *constraints[MAX_RECOG_OPERANDS]; |
18a90182 BS |
1396 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
1397 | struct insn_chain *chain; | |
1398 | ||
1399 | for (chain = reload_insn_chain; chain != 0; chain = chain->next) | |
1400 | { | |
1401 | int i, noperands; | |
1402 | HARD_REG_SET clobbered, allowed; | |
1403 | rtx pat; | |
1404 | ||
2c3c49de | 1405 | if (! INSN_P (chain->insn) |
18a90182 BS |
1406 | || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) |
1407 | continue; | |
1408 | pat = PATTERN (chain->insn); | |
1409 | if (GET_CODE (pat) != PARALLEL) | |
1410 | continue; | |
1411 | ||
1412 | CLEAR_HARD_REG_SET (clobbered); | |
1413 | CLEAR_HARD_REG_SET (allowed); | |
1414 | ||
1415 | /* First, make a mask of all stack regs that are clobbered. */ | |
1416 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
1417 | { | |
1418 | rtx t = XVECEXP (pat, 0, i); | |
1419 | if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) | |
1420 | SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); | |
1421 | } | |
1422 | ||
1423 | /* Get the operand values and constraints out of the insn. */ | |
1ccbefce | 1424 | decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, |
bff4b63d | 1425 | constraints, operand_mode, NULL); |
18a90182 BS |
1426 | |
1427 | /* For every operand, see what registers are allowed. */ | |
1428 | for (i = 0; i < noperands; i++) | |
1429 | { | |
6b9c6f4f | 1430 | const char *p = constraints[i]; |
18a90182 BS |
1431 | /* For every alternative, we compute the class of registers allowed |
1432 | for reloading in CLS, and merge its contents into the reg set | |
1433 | ALLOWED. */ | |
1434 | int cls = (int) NO_REGS; | |
1435 | ||
1436 | for (;;) | |
1437 | { | |
97488870 | 1438 | char c = *p; |
18a90182 BS |
1439 | |
1440 | if (c == '\0' || c == ',' || c == '#') | |
1441 | { | |
1442 | /* End of one alternative - mark the regs in the current | |
1443 | class, and reset the class. */ | |
1444 | IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); | |
1445 | cls = NO_REGS; | |
97488870 | 1446 | p++; |
18a90182 BS |
1447 | if (c == '#') |
1448 | do { | |
1449 | c = *p++; | |
1450 | } while (c != '\0' && c != ','); | |
1451 | if (c == '\0') | |
1452 | break; | |
1453 | continue; | |
1454 | } | |
1455 | ||
1456 | switch (c) | |
1457 | { | |
1458 | case '=': case '+': case '*': case '%': case '?': case '!': | |
1459 | case '0': case '1': case '2': case '3': case '4': case 'm': | |
1460 | case '<': case '>': case 'V': case 'o': case '&': case 'E': | |
1461 | case 'F': case 's': case 'i': case 'n': case 'X': case 'I': | |
1462 | case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': | |
1463 | case 'P': | |
18a90182 BS |
1464 | break; |
1465 | ||
1466 | case 'p': | |
3dcc68a4 | 1467 | cls = (int) reg_class_subunion[cls] |
c4963a0a | 1468 | [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; |
18a90182 BS |
1469 | break; |
1470 | ||
1471 | case 'g': | |
1472 | case 'r': | |
1473 | cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; | |
1474 | break; | |
1475 | ||
1476 | default: | |
97488870 | 1477 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) |
ccfc6cc8 | 1478 | cls = (int) reg_class_subunion[cls] |
c4963a0a | 1479 | [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; |
ccfc6cc8 UW |
1480 | else |
1481 | cls = (int) reg_class_subunion[cls] | |
97488870 | 1482 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; |
18a90182 | 1483 | } |
97488870 | 1484 | p += CONSTRAINT_LEN (c, p); |
18a90182 BS |
1485 | } |
1486 | } | |
1487 | /* Those of the registers which are clobbered, but allowed by the | |
1488 | constraints, must be usable as reload registers. So clear them | |
1489 | out of the life information. */ | |
1490 | AND_HARD_REG_SET (allowed, clobbered); | |
1491 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1492 | if (TEST_HARD_REG_BIT (allowed, i)) | |
1493 | { | |
239a0f5b BS |
1494 | CLEAR_REGNO_REG_SET (&chain->live_throughout, i); |
1495 | CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); | |
18a90182 BS |
1496 | } |
1497 | } | |
1498 | ||
1499 | #endif | |
1500 | } | |
03acd8f8 | 1501 | \f |
f5d8c9f4 BS |
1502 | /* Copy the global variables n_reloads and rld into the corresponding elts |
1503 | of CHAIN. */ | |
1504 | static void | |
0c20a65f | 1505 | copy_reloads (struct insn_chain *chain) |
f5d8c9f4 BS |
1506 | { |
1507 | chain->n_reloads = n_reloads; | |
703ad42b KG |
1508 | chain->rld = obstack_alloc (&reload_obstack, |
1509 | n_reloads * sizeof (struct reload)); | |
f5d8c9f4 | 1510 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
703ad42b | 1511 | reload_insn_firstobj = obstack_alloc (&reload_obstack, 0); |
f5d8c9f4 BS |
1512 | } |
1513 | ||
03acd8f8 BS |
1514 | /* Walk the chain of insns, and determine for each whether it needs reloads |
1515 | and/or eliminations. Build the corresponding insns_need_reload list, and | |
1516 | set something_needs_elimination as appropriate. */ | |
1517 | static void | |
0c20a65f | 1518 | calculate_needs_all_insns (int global) |
1e5bd841 | 1519 | { |
7609e720 | 1520 | struct insn_chain **pprev_reload = &insns_need_reload; |
462561b7 | 1521 | struct insn_chain *chain, *next = 0; |
1e5bd841 | 1522 | |
03acd8f8 BS |
1523 | something_needs_elimination = 0; |
1524 | ||
703ad42b | 1525 | reload_insn_firstobj = obstack_alloc (&reload_obstack, 0); |
462561b7 | 1526 | for (chain = reload_insn_chain; chain != 0; chain = next) |
1e5bd841 | 1527 | { |
67e61fe7 | 1528 | rtx insn = chain->insn; |
03acd8f8 | 1529 | |
462561b7 JJ |
1530 | next = chain->next; |
1531 | ||
f5d8c9f4 BS |
1532 | /* Clear out the shortcuts. */ |
1533 | chain->n_reloads = 0; | |
67e61fe7 BS |
1534 | chain->need_elim = 0; |
1535 | chain->need_reload = 0; | |
1536 | chain->need_operand_change = 0; | |
1e5bd841 | 1537 | |
03acd8f8 BS |
1538 | /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might |
1539 | include REG_LABEL), we need to see what effects this has on the | |
1540 | known offsets at labels. */ | |
1e5bd841 | 1541 | |
4b4bf941 | 1542 | if (LABEL_P (insn) || JUMP_P (insn) |
2c3c49de | 1543 | || (INSN_P (insn) && REG_NOTES (insn) != 0)) |
1e5bd841 BS |
1544 | set_label_offsets (insn, insn, 0); |
1545 | ||
2c3c49de | 1546 | if (INSN_P (insn)) |
1e5bd841 BS |
1547 | { |
1548 | rtx old_body = PATTERN (insn); | |
1549 | int old_code = INSN_CODE (insn); | |
1550 | rtx old_notes = REG_NOTES (insn); | |
1551 | int did_elimination = 0; | |
cb2afeb3 | 1552 | int operands_changed = 0; |
2b49ee39 R |
1553 | rtx set = single_set (insn); |
1554 | ||
1555 | /* Skip insns that only set an equivalence. */ | |
f8cfc6aa | 1556 | if (set && REG_P (SET_DEST (set)) |
2b49ee39 | 1557 | && reg_renumber[REGNO (SET_DEST (set))] < 0 |
ab156144 RH |
1558 | && (reg_equiv_constant[REGNO (SET_DEST (set))] |
1559 | || (reg_equiv_invariant[REGNO (SET_DEST (set))])) | |
1560 | && reg_equiv_init[REGNO (SET_DEST (set))]) | |
67e61fe7 | 1561 | continue; |
1e5bd841 | 1562 | |
1e5bd841 | 1563 | /* If needed, eliminate any eliminable registers. */ |
2b49ee39 | 1564 | if (num_eliminable || num_eliminable_invariants) |
1e5bd841 BS |
1565 | did_elimination = eliminate_regs_in_insn (insn, 0); |
1566 | ||
1567 | /* Analyze the instruction. */ | |
cb2afeb3 R |
1568 | operands_changed = find_reloads (insn, 0, spill_indirect_levels, |
1569 | global, spill_reg_order); | |
1570 | ||
1571 | /* If a no-op set needs more than one reload, this is likely | |
1572 | to be something that needs input address reloads. We | |
1573 | can't get rid of this cleanly later, and it is of no use | |
1574 | anyway, so discard it now. | |
1575 | We only do this when expensive_optimizations is enabled, | |
1576 | since this complements reload inheritance / output | |
1577 | reload deletion, and it can make debugging harder. */ | |
1578 | if (flag_expensive_optimizations && n_reloads > 1) | |
1579 | { | |
1580 | rtx set = single_set (insn); | |
1581 | if (set | |
1582 | && SET_SRC (set) == SET_DEST (set) | |
f8cfc6aa | 1583 | && REG_P (SET_SRC (set)) |
cb2afeb3 R |
1584 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) |
1585 | { | |
ca6c03ca | 1586 | delete_insn (insn); |
3eae4643 | 1587 | /* Delete it from the reload chain. */ |
462561b7 JJ |
1588 | if (chain->prev) |
1589 | chain->prev->next = next; | |
1590 | else | |
1591 | reload_insn_chain = next; | |
1592 | if (next) | |
1593 | next->prev = chain->prev; | |
1594 | chain->next = unused_insn_chains; | |
1595 | unused_insn_chains = chain; | |
cb2afeb3 R |
1596 | continue; |
1597 | } | |
1598 | } | |
1599 | if (num_eliminable) | |
1600 | update_eliminable_offsets (); | |
1e5bd841 BS |
1601 | |
1602 | /* Remember for later shortcuts which insns had any reloads or | |
7609e720 BS |
1603 | register eliminations. */ |
1604 | chain->need_elim = did_elimination; | |
03acd8f8 BS |
1605 | chain->need_reload = n_reloads > 0; |
1606 | chain->need_operand_change = operands_changed; | |
1e5bd841 BS |
1607 | |
1608 | /* Discard any register replacements done. */ | |
1609 | if (did_elimination) | |
1610 | { | |
f5d8c9f4 | 1611 | obstack_free (&reload_obstack, reload_insn_firstobj); |
1e5bd841 BS |
1612 | PATTERN (insn) = old_body; |
1613 | INSN_CODE (insn) = old_code; | |
1614 | REG_NOTES (insn) = old_notes; | |
1615 | something_needs_elimination = 1; | |
1616 | } | |
1617 | ||
cb2afeb3 R |
1618 | something_needs_operands_changed |= operands_changed; |
1619 | ||
437a710d | 1620 | if (n_reloads != 0) |
7609e720 | 1621 | { |
f5d8c9f4 | 1622 | copy_reloads (chain); |
7609e720 BS |
1623 | *pprev_reload = chain; |
1624 | pprev_reload = &chain->next_need_reload; | |
7609e720 | 1625 | } |
1e5bd841 | 1626 | } |
1e5bd841 | 1627 | } |
7609e720 | 1628 | *pprev_reload = 0; |
1e5bd841 | 1629 | } |
f5d8c9f4 BS |
1630 | \f |
1631 | /* Comparison function for qsort to decide which of two reloads | |
1632 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
1e5bd841 | 1633 | |
f5d8c9f4 | 1634 | static int |
0c20a65f | 1635 | reload_reg_class_lower (const void *r1p, const void *r2p) |
1e5bd841 | 1636 | { |
b3694847 SS |
1637 | int r1 = *(const short *) r1p, r2 = *(const short *) r2p; |
1638 | int t; | |
1e5bd841 | 1639 | |
f5d8c9f4 BS |
1640 | /* Consider required reloads before optional ones. */ |
1641 | t = rld[r1].optional - rld[r2].optional; | |
1642 | if (t != 0) | |
1643 | return t; | |
1e5bd841 | 1644 | |
f5d8c9f4 BS |
1645 | /* Count all solitary classes before non-solitary ones. */ |
1646 | t = ((reg_class_size[(int) rld[r2].class] == 1) | |
1647 | - (reg_class_size[(int) rld[r1].class] == 1)); | |
1648 | if (t != 0) | |
1649 | return t; | |
1e5bd841 | 1650 | |
f5d8c9f4 BS |
1651 | /* Aside from solitaires, consider all multi-reg groups first. */ |
1652 | t = rld[r2].nregs - rld[r1].nregs; | |
1653 | if (t != 0) | |
1654 | return t; | |
1e5bd841 | 1655 | |
f5d8c9f4 BS |
1656 | /* Consider reloads in order of increasing reg-class number. */ |
1657 | t = (int) rld[r1].class - (int) rld[r2].class; | |
1658 | if (t != 0) | |
1659 | return t; | |
1e5bd841 | 1660 | |
f5d8c9f4 BS |
1661 | /* If reloads are equally urgent, sort by reload number, |
1662 | so that the results of qsort leave nothing to chance. */ | |
1663 | return r1 - r2; | |
1664 | } | |
1665 | \f | |
1666 | /* The cost of spilling each hard reg. */ | |
1667 | static int spill_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1668 | |
f5d8c9f4 BS |
1669 | /* When spilling multiple hard registers, we use SPILL_COST for the first |
1670 | spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST | |
1671 | only the first hard reg for a multi-reg pseudo. */ | |
1672 | static int spill_add_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1673 | |
f5d8c9f4 | 1674 | /* Update the spill cost arrays, considering that pseudo REG is live. */ |
770ae6cc | 1675 | |
f5d8c9f4 | 1676 | static void |
0c20a65f | 1677 | count_pseudo (int reg) |
f5d8c9f4 | 1678 | { |
b2aec5c0 | 1679 | int freq = REG_FREQ (reg); |
f5d8c9f4 BS |
1680 | int r = reg_renumber[reg]; |
1681 | int nregs; | |
1e5bd841 | 1682 | |
f5d8c9f4 BS |
1683 | if (REGNO_REG_SET_P (&pseudos_counted, reg) |
1684 | || REGNO_REG_SET_P (&spilled_pseudos, reg)) | |
1685 | return; | |
1e5bd841 | 1686 | |
f5d8c9f4 | 1687 | SET_REGNO_REG_SET (&pseudos_counted, reg); |
1e5bd841 | 1688 | |
41374e13 | 1689 | gcc_assert (r >= 0); |
1d7254c5 | 1690 | |
b2aec5c0 | 1691 | spill_add_cost[r] += freq; |
1e5bd841 | 1692 | |
66fd46b6 | 1693 | nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)]; |
f5d8c9f4 | 1694 | while (nregs-- > 0) |
b2aec5c0 | 1695 | spill_cost[r + nregs] += freq; |
f5d8c9f4 | 1696 | } |
1e5bd841 | 1697 | |
f5d8c9f4 BS |
1698 | /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the |
1699 | contents of BAD_SPILL_REGS for the insn described by CHAIN. */ | |
efc9bd41 | 1700 | |
f5d8c9f4 | 1701 | static void |
0c20a65f | 1702 | order_regs_for_reload (struct insn_chain *chain) |
f5d8c9f4 | 1703 | { |
3cd8c58a | 1704 | unsigned i; |
efc9bd41 RK |
1705 | HARD_REG_SET used_by_pseudos; |
1706 | HARD_REG_SET used_by_pseudos2; | |
a2041967 | 1707 | reg_set_iterator rsi; |
1e5bd841 | 1708 | |
efc9bd41 | 1709 | COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set); |
1e5bd841 | 1710 | |
f5d8c9f4 BS |
1711 | memset (spill_cost, 0, sizeof spill_cost); |
1712 | memset (spill_add_cost, 0, sizeof spill_add_cost); | |
1e5bd841 | 1713 | |
f5d8c9f4 | 1714 | /* Count number of uses of each hard reg by pseudo regs allocated to it |
efc9bd41 RK |
1715 | and then order them by decreasing use. First exclude hard registers |
1716 | that are live in or across this insn. */ | |
1717 | ||
1718 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); | |
1719 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
1720 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos); | |
1721 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2); | |
1e5bd841 | 1722 | |
f5d8c9f4 BS |
1723 | /* Now find out which pseudos are allocated to it, and update |
1724 | hard_reg_n_uses. */ | |
1725 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1726 | |
f5d8c9f4 | 1727 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
1728 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi) |
1729 | { | |
1730 | count_pseudo (i); | |
1731 | } | |
f5d8c9f4 | 1732 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
1733 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi) |
1734 | { | |
1735 | count_pseudo (i); | |
1736 | } | |
f5d8c9f4 | 1737 | CLEAR_REG_SET (&pseudos_counted); |
1e5bd841 | 1738 | } |
03acd8f8 | 1739 | \f |
f5d8c9f4 BS |
1740 | /* Vector of reload-numbers showing the order in which the reloads should |
1741 | be processed. */ | |
1742 | static short reload_order[MAX_RELOADS]; | |
1e5bd841 | 1743 | |
f5d8c9f4 BS |
1744 | /* This is used to keep track of the spill regs used in one insn. */ |
1745 | static HARD_REG_SET used_spill_regs_local; | |
03acd8f8 | 1746 | |
f5d8c9f4 BS |
1747 | /* We decided to spill hard register SPILLED, which has a size of |
1748 | SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, | |
1749 | is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will | |
1750 | update SPILL_COST/SPILL_ADD_COST. */ | |
770ae6cc | 1751 | |
03acd8f8 | 1752 | static void |
0c20a65f | 1753 | count_spilled_pseudo (int spilled, int spilled_nregs, int reg) |
1e5bd841 | 1754 | { |
f5d8c9f4 | 1755 | int r = reg_renumber[reg]; |
66fd46b6 | 1756 | int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)]; |
1e5bd841 | 1757 | |
f5d8c9f4 BS |
1758 | if (REGNO_REG_SET_P (&spilled_pseudos, reg) |
1759 | || spilled + spilled_nregs <= r || r + nregs <= spilled) | |
1760 | return; | |
1e5bd841 | 1761 | |
f5d8c9f4 | 1762 | SET_REGNO_REG_SET (&spilled_pseudos, reg); |
1e5bd841 | 1763 | |
b2aec5c0 | 1764 | spill_add_cost[r] -= REG_FREQ (reg); |
f5d8c9f4 | 1765 | while (nregs-- > 0) |
b2aec5c0 | 1766 | spill_cost[r + nregs] -= REG_FREQ (reg); |
1e5bd841 BS |
1767 | } |
1768 | ||
f5d8c9f4 | 1769 | /* Find reload register to use for reload number ORDER. */ |
03acd8f8 | 1770 | |
f5d8c9f4 | 1771 | static int |
0c20a65f | 1772 | find_reg (struct insn_chain *chain, int order) |
1e5bd841 | 1773 | { |
f5d8c9f4 BS |
1774 | int rnum = reload_order[order]; |
1775 | struct reload *rl = rld + rnum; | |
1776 | int best_cost = INT_MAX; | |
1777 | int best_reg = -1; | |
770ae6cc RK |
1778 | unsigned int i, j; |
1779 | int k; | |
f5d8c9f4 BS |
1780 | HARD_REG_SET not_usable; |
1781 | HARD_REG_SET used_by_other_reload; | |
a2041967 | 1782 | reg_set_iterator rsi; |
1e5bd841 | 1783 | |
f5d8c9f4 BS |
1784 | COPY_HARD_REG_SET (not_usable, bad_spill_regs); |
1785 | IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); | |
1786 | IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]); | |
1787 | ||
1788 | CLEAR_HARD_REG_SET (used_by_other_reload); | |
770ae6cc | 1789 | for (k = 0; k < order; k++) |
1e5bd841 | 1790 | { |
770ae6cc RK |
1791 | int other = reload_order[k]; |
1792 | ||
f5d8c9f4 BS |
1793 | if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) |
1794 | for (j = 0; j < rld[other].nregs; j++) | |
1795 | SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); | |
1796 | } | |
1e5bd841 | 1797 | |
f5d8c9f4 BS |
1798 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1799 | { | |
770ae6cc RK |
1800 | unsigned int regno = i; |
1801 | ||
f5d8c9f4 BS |
1802 | if (! TEST_HARD_REG_BIT (not_usable, regno) |
1803 | && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) | |
1804 | && HARD_REGNO_MODE_OK (regno, rl->mode)) | |
1e5bd841 | 1805 | { |
f5d8c9f4 BS |
1806 | int this_cost = spill_cost[regno]; |
1807 | int ok = 1; | |
66fd46b6 | 1808 | unsigned int this_nregs = hard_regno_nregs[regno][rl->mode]; |
1e5bd841 | 1809 | |
f5d8c9f4 BS |
1810 | for (j = 1; j < this_nregs; j++) |
1811 | { | |
1812 | this_cost += spill_add_cost[regno + j]; | |
1813 | if ((TEST_HARD_REG_BIT (not_usable, regno + j)) | |
1814 | || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) | |
1815 | ok = 0; | |
1816 | } | |
1817 | if (! ok) | |
1818 | continue; | |
f8cfc6aa | 1819 | if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno) |
f5d8c9f4 | 1820 | this_cost--; |
f8cfc6aa | 1821 | if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno) |
f5d8c9f4 BS |
1822 | this_cost--; |
1823 | if (this_cost < best_cost | |
1824 | /* Among registers with equal cost, prefer caller-saved ones, or | |
1825 | use REG_ALLOC_ORDER if it is defined. */ | |
1826 | || (this_cost == best_cost | |
1827 | #ifdef REG_ALLOC_ORDER | |
1828 | && (inv_reg_alloc_order[regno] | |
1829 | < inv_reg_alloc_order[best_reg]) | |
1830 | #else | |
1831 | && call_used_regs[regno] | |
1832 | && ! call_used_regs[best_reg] | |
1833 | #endif | |
1834 | )) | |
1835 | { | |
1836 | best_reg = regno; | |
1837 | best_cost = this_cost; | |
1e5bd841 BS |
1838 | } |
1839 | } | |
1840 | } | |
f5d8c9f4 BS |
1841 | if (best_reg == -1) |
1842 | return 0; | |
770ae6cc | 1843 | |
c263766c RH |
1844 | if (dump_file) |
1845 | fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum); | |
770ae6cc | 1846 | |
66fd46b6 | 1847 | rl->nregs = hard_regno_nregs[best_reg][rl->mode]; |
f5d8c9f4 | 1848 | rl->regno = best_reg; |
1e5bd841 | 1849 | |
f5d8c9f4 | 1850 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
1851 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi) |
1852 | { | |
1853 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1854 | } | |
770ae6cc | 1855 | |
f5d8c9f4 | 1856 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
1857 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi) |
1858 | { | |
1859 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1860 | } | |
03acd8f8 | 1861 | |
f5d8c9f4 BS |
1862 | for (i = 0; i < rl->nregs; i++) |
1863 | { | |
41374e13 NS |
1864 | gcc_assert (spill_cost[best_reg + i] == 0); |
1865 | gcc_assert (spill_add_cost[best_reg + i] == 0); | |
f5d8c9f4 BS |
1866 | SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); |
1867 | } | |
1868 | return 1; | |
03acd8f8 BS |
1869 | } |
1870 | ||
1871 | /* Find more reload regs to satisfy the remaining need of an insn, which | |
1872 | is given by CHAIN. | |
1e5bd841 BS |
1873 | Do it by ascending class number, since otherwise a reg |
1874 | might be spilled for a big class and might fail to count | |
f5d8c9f4 | 1875 | for a smaller class even though it belongs to that class. */ |
1e5bd841 | 1876 | |
03acd8f8 | 1877 | static void |
0c20a65f | 1878 | find_reload_regs (struct insn_chain *chain) |
1e5bd841 | 1879 | { |
f5d8c9f4 | 1880 | int i; |
1e5bd841 | 1881 | |
f5d8c9f4 BS |
1882 | /* In order to be certain of getting the registers we need, |
1883 | we must sort the reloads into order of increasing register class. | |
1884 | Then our grabbing of reload registers will parallel the process | |
1885 | that provided the reload registers. */ | |
1886 | for (i = 0; i < chain->n_reloads; i++) | |
1e5bd841 | 1887 | { |
f5d8c9f4 BS |
1888 | /* Show whether this reload already has a hard reg. */ |
1889 | if (chain->rld[i].reg_rtx) | |
1e5bd841 | 1890 | { |
f5d8c9f4 BS |
1891 | int regno = REGNO (chain->rld[i].reg_rtx); |
1892 | chain->rld[i].regno = regno; | |
770ae6cc | 1893 | chain->rld[i].nregs |
66fd46b6 | 1894 | = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)]; |
1e5bd841 | 1895 | } |
f5d8c9f4 BS |
1896 | else |
1897 | chain->rld[i].regno = -1; | |
1898 | reload_order[i] = i; | |
1899 | } | |
1e5bd841 | 1900 | |
f5d8c9f4 BS |
1901 | n_reloads = chain->n_reloads; |
1902 | memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); | |
1e5bd841 | 1903 | |
f5d8c9f4 | 1904 | CLEAR_HARD_REG_SET (used_spill_regs_local); |
03acd8f8 | 1905 | |
c263766c RH |
1906 | if (dump_file) |
1907 | fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn)); | |
1e5bd841 | 1908 | |
f5d8c9f4 | 1909 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); |
1e5bd841 | 1910 | |
f5d8c9f4 | 1911 | /* Compute the order of preference for hard registers to spill. */ |
1e5bd841 | 1912 | |
f5d8c9f4 | 1913 | order_regs_for_reload (chain); |
1e5bd841 | 1914 | |
f5d8c9f4 BS |
1915 | for (i = 0; i < n_reloads; i++) |
1916 | { | |
1917 | int r = reload_order[i]; | |
1e5bd841 | 1918 | |
f5d8c9f4 BS |
1919 | /* Ignore reloads that got marked inoperative. */ |
1920 | if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) | |
1921 | && ! rld[r].optional | |
1922 | && rld[r].regno == -1) | |
e04ca094 | 1923 | if (! find_reg (chain, i)) |
f5d8c9f4 | 1924 | { |
ff182b5c | 1925 | if (dump_file) |
247140ea | 1926 | fprintf (dump_file, "reload failure for reload %d\n", r); |
ecf3151a | 1927 | spill_failure (chain->insn, rld[r].class); |
f5d8c9f4 | 1928 | failure = 1; |
03acd8f8 | 1929 | return; |
f5d8c9f4 | 1930 | } |
1e5bd841 | 1931 | } |
05d10675 | 1932 | |
f5d8c9f4 BS |
1933 | COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local); |
1934 | IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local); | |
03acd8f8 | 1935 | |
f5d8c9f4 | 1936 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
1e5bd841 BS |
1937 | } |
1938 | ||
f5d8c9f4 | 1939 | static void |
0c20a65f | 1940 | select_reload_regs (void) |
09dd1133 | 1941 | { |
f5d8c9f4 | 1942 | struct insn_chain *chain; |
09dd1133 | 1943 | |
f5d8c9f4 BS |
1944 | /* Try to satisfy the needs for each insn. */ |
1945 | for (chain = insns_need_reload; chain != 0; | |
1946 | chain = chain->next_need_reload) | |
e04ca094 | 1947 | find_reload_regs (chain); |
09dd1133 | 1948 | } |
32131a9c | 1949 | \f |
437a710d BS |
1950 | /* Delete all insns that were inserted by emit_caller_save_insns during |
1951 | this iteration. */ | |
1952 | static void | |
0c20a65f | 1953 | delete_caller_save_insns (void) |
437a710d | 1954 | { |
7609e720 | 1955 | struct insn_chain *c = reload_insn_chain; |
437a710d | 1956 | |
7609e720 | 1957 | while (c != 0) |
437a710d | 1958 | { |
7609e720 | 1959 | while (c != 0 && c->is_caller_save_insn) |
437a710d | 1960 | { |
7609e720 BS |
1961 | struct insn_chain *next = c->next; |
1962 | rtx insn = c->insn; | |
1963 | ||
7609e720 BS |
1964 | if (c == reload_insn_chain) |
1965 | reload_insn_chain = next; | |
ca6c03ca | 1966 | delete_insn (insn); |
7609e720 BS |
1967 | |
1968 | if (next) | |
1969 | next->prev = c->prev; | |
1970 | if (c->prev) | |
1971 | c->prev->next = next; | |
1972 | c->next = unused_insn_chains; | |
1973 | unused_insn_chains = c; | |
1974 | c = next; | |
437a710d | 1975 | } |
7609e720 BS |
1976 | if (c != 0) |
1977 | c = c->next; | |
437a710d BS |
1978 | } |
1979 | } | |
1980 | \f | |
5352b11a RS |
1981 | /* Handle the failure to find a register to spill. |
1982 | INSN should be one of the insns which needed this particular spill reg. */ | |
1983 | ||
1984 | static void | |
0c20a65f | 1985 | spill_failure (rtx insn, enum reg_class class) |
5352b11a RS |
1986 | { |
1987 | if (asm_noperands (PATTERN (insn)) >= 0) | |
971801ff JM |
1988 | error_for_asm (insn, "can't find a register in class %qs while " |
1989 | "reloading %<asm%>", | |
ecf3151a | 1990 | reg_class_names[class]); |
5352b11a | 1991 | else |
ecf3151a | 1992 | { |
971801ff | 1993 | error ("unable to find a register to spill in class %qs", |
ecf3151a | 1994 | reg_class_names[class]); |
ff182b5c DD |
1995 | |
1996 | if (dump_file) | |
1997 | { | |
1998 | fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); | |
1999 | debug_reload_to_stream (dump_file); | |
2000 | } | |
1f978f5f | 2001 | fatal_insn ("this is the insn:", insn); |
ecf3151a | 2002 | } |
5352b11a | 2003 | } |
32131a9c RK |
2004 | \f |
2005 | /* Delete an unneeded INSN and any previous insns who sole purpose is loading | |
2006 | data that is dead in INSN. */ | |
2007 | ||
2008 | static void | |
0c20a65f | 2009 | delete_dead_insn (rtx insn) |
32131a9c RK |
2010 | { |
2011 | rtx prev = prev_real_insn (insn); | |
2012 | rtx prev_dest; | |
2013 | ||
2014 | /* If the previous insn sets a register that dies in our insn, delete it | |
2015 | too. */ | |
2016 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
f8cfc6aa | 2017 | && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest)) |
32131a9c | 2018 | && reg_mentioned_p (prev_dest, PATTERN (insn)) |
b294ca38 R |
2019 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) |
2020 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
32131a9c RK |
2021 | delete_dead_insn (prev); |
2022 | ||
6773e15f | 2023 | SET_INSN_DELETED (insn); |
32131a9c RK |
2024 | } |
2025 | ||
2026 | /* Modify the home of pseudo-reg I. | |
2027 | The new home is present in reg_renumber[I]. | |
2028 | ||
2029 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
2030 | or it may be -1, meaning there is none or it is not relevant. | |
2031 | This is used so that all pseudos spilled from a given hard reg | |
2032 | can share one stack slot. */ | |
2033 | ||
2034 | static void | |
0c20a65f | 2035 | alter_reg (int i, int from_reg) |
32131a9c RK |
2036 | { |
2037 | /* When outputting an inline function, this can happen | |
2038 | for a reg that isn't actually used. */ | |
2039 | if (regno_reg_rtx[i] == 0) | |
2040 | return; | |
2041 | ||
2042 | /* If the reg got changed to a MEM at rtl-generation time, | |
2043 | ignore it. */ | |
f8cfc6aa | 2044 | if (!REG_P (regno_reg_rtx[i])) |
32131a9c RK |
2045 | return; |
2046 | ||
2047 | /* Modify the reg-rtx to contain the new hard reg | |
2048 | number or else to contain its pseudo reg number. */ | |
6fb5fa3c DB |
2049 | SET_REGNO (regno_reg_rtx[i], |
2050 | reg_renumber[i] >= 0 ? reg_renumber[i] : i); | |
32131a9c RK |
2051 | |
2052 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
2053 | allocate a stack slot for it. */ | |
2054 | ||
2055 | if (reg_renumber[i] < 0 | |
b1f21e0a | 2056 | && REG_N_REFS (i) > 0 |
32131a9c | 2057 | && reg_equiv_constant[i] == 0 |
ab156144 | 2058 | && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0) |
32131a9c RK |
2059 | && reg_equiv_memory_loc[i] == 0) |
2060 | { | |
b3694847 | 2061 | rtx x; |
63a7a62b | 2062 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); |
770ae6cc | 2063 | unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); |
63a7a62b | 2064 | unsigned int inherent_align = GET_MODE_ALIGNMENT (mode); |
770ae6cc | 2065 | unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]); |
63a7a62b | 2066 | unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT; |
32131a9c RK |
2067 | int adjust = 0; |
2068 | ||
2069 | /* Each pseudo reg has an inherent size which comes from its own mode, | |
2070 | and a total size which provides room for paradoxical subregs | |
2071 | which refer to the pseudo reg in wider modes. | |
2072 | ||
2073 | We can use a slot already allocated if it provides both | |
2074 | enough inherent space and enough total space. | |
2075 | Otherwise, we allocate a new slot, making sure that it has no less | |
2076 | inherent space, and no less total space, then the previous slot. */ | |
2077 | if (from_reg == -1) | |
2078 | { | |
6fb5fa3c DB |
2079 | HOST_WIDE_INT alias_set = new_alias_set (); |
2080 | ||
32131a9c | 2081 | /* No known place to spill from => no slot to reuse. */ |
63a7a62b RS |
2082 | x = assign_stack_local (mode, total_size, |
2083 | min_align > inherent_align | |
2084 | || total_size > inherent_size ? -1 : 0); | |
f76b9db2 | 2085 | if (BYTES_BIG_ENDIAN) |
02db8dd0 RK |
2086 | /* Cancel the big-endian correction done in assign_stack_local. |
2087 | Get the address of the beginning of the slot. | |
2088 | This is so we can do a big-endian correction unconditionally | |
2089 | below. */ | |
2090 | adjust = inherent_size - total_size; | |
2091 | ||
3bdf5ad1 | 2092 | /* Nothing can alias this slot except this pseudo. */ |
6fb5fa3c DB |
2093 | set_mem_alias_set (x, alias_set); |
2094 | dse_record_singleton_alias_set (alias_set, mode); | |
32131a9c | 2095 | } |
3bdf5ad1 | 2096 | |
32131a9c RK |
2097 | /* Reuse a stack slot if possible. */ |
2098 | else if (spill_stack_slot[from_reg] != 0 | |
2099 | && spill_stack_slot_width[from_reg] >= total_size | |
2100 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
63a7a62b RS |
2101 | >= inherent_size) |
2102 | && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align) | |
32131a9c RK |
2103 | x = spill_stack_slot[from_reg]; |
2104 | /* Allocate a bigger slot. */ | |
2105 | else | |
2106 | { | |
2107 | /* Compute maximum size needed, both for inherent size | |
2108 | and for total size. */ | |
4f2d3674 | 2109 | rtx stack_slot; |
3bdf5ad1 | 2110 | |
32131a9c RK |
2111 | if (spill_stack_slot[from_reg]) |
2112 | { | |
2113 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
2114 | > inherent_size) | |
2115 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
2116 | if (spill_stack_slot_width[from_reg] > total_size) | |
2117 | total_size = spill_stack_slot_width[from_reg]; | |
63a7a62b RS |
2118 | if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align) |
2119 | min_align = MEM_ALIGN (spill_stack_slot[from_reg]); | |
32131a9c | 2120 | } |
3bdf5ad1 | 2121 | |
32131a9c | 2122 | /* Make a slot with that size. */ |
cabcf079 | 2123 | x = assign_stack_local (mode, total_size, |
63a7a62b RS |
2124 | min_align > inherent_align |
2125 | || total_size > inherent_size ? -1 : 0); | |
4f2d3674 | 2126 | stack_slot = x; |
3bdf5ad1 RK |
2127 | |
2128 | /* All pseudos mapped to this slot can alias each other. */ | |
2129 | if (spill_stack_slot[from_reg]) | |
6fb5fa3c DB |
2130 | { |
2131 | HOST_WIDE_INT alias_set | |
2132 | = MEM_ALIAS_SET (spill_stack_slot[from_reg]); | |
2133 | set_mem_alias_set (x, alias_set); | |
2134 | dse_invalidate_singleton_alias_set (alias_set); | |
2135 | } | |
3bdf5ad1 | 2136 | else |
6fb5fa3c DB |
2137 | { |
2138 | HOST_WIDE_INT alias_set = new_alias_set (); | |
2139 | set_mem_alias_set (x, alias_set); | |
2140 | dse_record_singleton_alias_set (alias_set, mode); | |
2141 | } | |
3bdf5ad1 | 2142 | |
f76b9db2 ILT |
2143 | if (BYTES_BIG_ENDIAN) |
2144 | { | |
2145 | /* Cancel the big-endian correction done in assign_stack_local. | |
2146 | Get the address of the beginning of the slot. | |
2147 | This is so we can do a big-endian correction unconditionally | |
2148 | below. */ | |
2149 | adjust = GET_MODE_SIZE (mode) - total_size; | |
4f2d3674 | 2150 | if (adjust) |
8ac61af7 RK |
2151 | stack_slot |
2152 | = adjust_address_nv (x, mode_for_size (total_size | |
38a448ca RH |
2153 | * BITS_PER_UNIT, |
2154 | MODE_INT, 1), | |
8ac61af7 | 2155 | adjust); |
f76b9db2 | 2156 | } |
3bdf5ad1 | 2157 | |
4f2d3674 | 2158 | spill_stack_slot[from_reg] = stack_slot; |
32131a9c RK |
2159 | spill_stack_slot_width[from_reg] = total_size; |
2160 | } | |
2161 | ||
32131a9c RK |
2162 | /* On a big endian machine, the "address" of the slot |
2163 | is the address of the low part that fits its inherent mode. */ | |
f76b9db2 | 2164 | if (BYTES_BIG_ENDIAN && inherent_size < total_size) |
32131a9c | 2165 | adjust += (total_size - inherent_size); |
32131a9c RK |
2166 | |
2167 | /* If we have any adjustment to make, or if the stack slot is the | |
2168 | wrong mode, make a new stack slot. */ | |
1285011e RK |
2169 | x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); |
2170 | ||
2171 | /* If we have a decl for the original register, set it for the | |
2172 | memory. If this is a shared MEM, make a copy. */ | |
a560d4d4 | 2173 | if (REG_EXPR (regno_reg_rtx[i]) |
6615c446 | 2174 | && DECL_P (REG_EXPR (regno_reg_rtx[i]))) |
1285011e | 2175 | { |
a560d4d4 | 2176 | rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i])); |
1285011e | 2177 | |
a20fd5ac JJ |
2178 | /* We can do this only for the DECLs home pseudo, not for |
2179 | any copies of it, since otherwise when the stack slot | |
2180 | is reused, nonoverlapping_memrefs_p might think they | |
2181 | cannot overlap. */ | |
f8cfc6aa | 2182 | if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i) |
a20fd5ac JJ |
2183 | { |
2184 | if (from_reg != -1 && spill_stack_slot[from_reg] == x) | |
2185 | x = copy_rtx (x); | |
2186 | ||
a560d4d4 | 2187 | set_mem_attrs_from_reg (x, regno_reg_rtx[i]); |
a20fd5ac | 2188 | } |
1285011e | 2189 | } |
32131a9c | 2190 | |
6d2f8887 | 2191 | /* Save the stack slot for later. */ |
32131a9c RK |
2192 | reg_equiv_memory_loc[i] = x; |
2193 | } | |
2194 | } | |
2195 | ||
6fb5fa3c DB |
2196 | /* Mark the slots in regs_ever_live for the hard regs used by |
2197 | pseudo-reg number REGNO, accessed in MODE. */ | |
32131a9c | 2198 | |
6fb5fa3c DB |
2199 | static void |
2200 | mark_home_live_1 (int regno, enum machine_mode mode) | |
32131a9c | 2201 | { |
b3694847 | 2202 | int i, lim; |
770ae6cc | 2203 | |
32131a9c RK |
2204 | i = reg_renumber[regno]; |
2205 | if (i < 0) | |
2206 | return; | |
b0384c54 | 2207 | lim = end_hard_regno (mode, i); |
32131a9c | 2208 | while (i < lim) |
6fb5fa3c DB |
2209 | df_set_regs_ever_live(i++, true); |
2210 | } | |
2211 | ||
2212 | /* Mark the slots in regs_ever_live for the hard regs | |
2213 | used by pseudo-reg number REGNO. */ | |
2214 | ||
2215 | void | |
2216 | mark_home_live (int regno) | |
2217 | { | |
2218 | if (reg_renumber[regno] >= 0) | |
2219 | mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno)); | |
32131a9c RK |
2220 | } |
2221 | \f | |
2222 | /* This function handles the tracking of elimination offsets around branches. | |
2223 | ||
2224 | X is a piece of RTL being scanned. | |
2225 | ||
2226 | INSN is the insn that it came from, if any. | |
2227 | ||
40f03658 | 2228 | INITIAL_P is nonzero if we are to set the offset to be the initial |
32131a9c RK |
2229 | offset and zero if we are setting the offset of the label to be the |
2230 | current offset. */ | |
2231 | ||
2232 | static void | |
0c20a65f | 2233 | set_label_offsets (rtx x, rtx insn, int initial_p) |
32131a9c RK |
2234 | { |
2235 | enum rtx_code code = GET_CODE (x); | |
2236 | rtx tem; | |
e51712db | 2237 | unsigned int i; |
32131a9c RK |
2238 | struct elim_table *p; |
2239 | ||
2240 | switch (code) | |
2241 | { | |
2242 | case LABEL_REF: | |
8be386d9 RS |
2243 | if (LABEL_REF_NONLOCAL_P (x)) |
2244 | return; | |
2245 | ||
32131a9c RK |
2246 | x = XEXP (x, 0); |
2247 | ||
0f41302f | 2248 | /* ... fall through ... */ |
32131a9c RK |
2249 | |
2250 | case CODE_LABEL: | |
2251 | /* If we know nothing about this label, set the desired offsets. Note | |
2252 | that this sets the offset at a label to be the offset before a label | |
2253 | if we don't know anything about the label. This is not correct for | |
2254 | the label after a BARRIER, but is the best guess we can make. If | |
2255 | we guessed wrong, we will suppress an elimination that might have | |
2256 | been possible had we been able to guess correctly. */ | |
2257 | ||
4cc0fdd2 | 2258 | if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num]) |
32131a9c RK |
2259 | { |
2260 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
4cc0fdd2 | 2261 | offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] |
32131a9c RK |
2262 | = (initial_p ? reg_eliminate[i].initial_offset |
2263 | : reg_eliminate[i].offset); | |
4cc0fdd2 | 2264 | offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1; |
32131a9c RK |
2265 | } |
2266 | ||
2267 | /* Otherwise, if this is the definition of a label and it is | |
d45cf215 | 2268 | preceded by a BARRIER, set our offsets to the known offset of |
32131a9c RK |
2269 | that label. */ |
2270 | ||
2271 | else if (x == insn | |
2272 | && (tem = prev_nonnote_insn (insn)) != 0 | |
4b4bf941 | 2273 | && BARRIER_P (tem)) |
1f3b1e1a | 2274 | set_offsets_for_label (insn); |
32131a9c RK |
2275 | else |
2276 | /* If neither of the above cases is true, compare each offset | |
2277 | with those previously recorded and suppress any eliminations | |
2278 | where the offsets disagree. */ | |
a8fdc208 | 2279 | |
32131a9c | 2280 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) |
4cc0fdd2 | 2281 | if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] |
32131a9c RK |
2282 | != (initial_p ? reg_eliminate[i].initial_offset |
2283 | : reg_eliminate[i].offset)) | |
2284 | reg_eliminate[i].can_eliminate = 0; | |
2285 | ||
2286 | return; | |
2287 | ||
2288 | case JUMP_INSN: | |
2289 | set_label_offsets (PATTERN (insn), insn, initial_p); | |
2290 | ||
0f41302f | 2291 | /* ... fall through ... */ |
32131a9c RK |
2292 | |
2293 | case INSN: | |
2294 | case CALL_INSN: | |
2295 | /* Any labels mentioned in REG_LABEL notes can be branched to indirectly | |
2296 | and hence must have all eliminations at their initial offsets. */ | |
2297 | for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) | |
2298 | if (REG_NOTE_KIND (tem) == REG_LABEL) | |
2299 | set_label_offsets (XEXP (tem, 0), insn, 1); | |
2300 | return; | |
2301 | ||
0c0ba09c | 2302 | case PARALLEL: |
32131a9c RK |
2303 | case ADDR_VEC: |
2304 | case ADDR_DIFF_VEC: | |
0c0ba09c JJ |
2305 | /* Each of the labels in the parallel or address vector must be |
2306 | at their initial offsets. We want the first field for PARALLEL | |
2307 | and ADDR_VEC and the second field for ADDR_DIFF_VEC. */ | |
32131a9c | 2308 | |
e51712db | 2309 | for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) |
32131a9c RK |
2310 | set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), |
2311 | insn, initial_p); | |
2312 | return; | |
2313 | ||
2314 | case SET: | |
2315 | /* We only care about setting PC. If the source is not RETURN, | |
2316 | IF_THEN_ELSE, or a label, disable any eliminations not at | |
2317 | their initial offsets. Similarly if any arm of the IF_THEN_ELSE | |
2318 | isn't one of those possibilities. For branches to a label, | |
2319 | call ourselves recursively. | |
2320 | ||
2321 | Note that this can disable elimination unnecessarily when we have | |
2322 | a non-local goto since it will look like a non-constant jump to | |
2323 | someplace in the current function. This isn't a significant | |
2324 | problem since such jumps will normally be when all elimination | |
2325 | pairs are back to their initial offsets. */ | |
2326 | ||
2327 | if (SET_DEST (x) != pc_rtx) | |
2328 | return; | |
2329 | ||
2330 | switch (GET_CODE (SET_SRC (x))) | |
2331 | { | |
2332 | case PC: | |
2333 | case RETURN: | |
2334 | return; | |
2335 | ||
2336 | case LABEL_REF: | |
8f235343 | 2337 | set_label_offsets (SET_SRC (x), insn, initial_p); |
32131a9c RK |
2338 | return; |
2339 | ||
2340 | case IF_THEN_ELSE: | |
2341 | tem = XEXP (SET_SRC (x), 1); | |
2342 | if (GET_CODE (tem) == LABEL_REF) | |
2343 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2344 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2345 | break; | |
2346 | ||
2347 | tem = XEXP (SET_SRC (x), 2); | |
2348 | if (GET_CODE (tem) == LABEL_REF) | |
2349 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2350 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2351 | break; | |
2352 | return; | |
e9a25f70 JL |
2353 | |
2354 | default: | |
2355 | break; | |
32131a9c RK |
2356 | } |
2357 | ||
2358 | /* If we reach here, all eliminations must be at their initial | |
2359 | offset because we are doing a jump to a variable address. */ | |
2360 | for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) | |
2361 | if (p->offset != p->initial_offset) | |
2362 | p->can_eliminate = 0; | |
e9a25f70 | 2363 | break; |
05d10675 | 2364 | |
e9a25f70 JL |
2365 | default: |
2366 | break; | |
32131a9c RK |
2367 | } |
2368 | } | |
2369 | \f | |
a8fdc208 | 2370 | /* Scan X and replace any eliminable registers (such as fp) with a |
32131a9c RK |
2371 | replacement (such as sp), plus an offset. |
2372 | ||
2373 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
2374 | much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a | |
2375 | MEM, we are allowed to replace a sum of a register and the constant zero | |
2376 | with the register, which we cannot do outside a MEM. In addition, we need | |
2377 | to record the fact that a register is referenced outside a MEM. | |
2378 | ||
ff32812a | 2379 | If INSN is an insn, it is the insn containing X. If we replace a REG |
40f03658 | 2380 | in a SET_DEST with an equivalent MEM and INSN is nonzero, write a |
32131a9c | 2381 | CLOBBER of the pseudo after INSN so find_equiv_regs will know that |
38e01259 | 2382 | the REG is being modified. |
32131a9c | 2383 | |
ff32812a RS |
2384 | Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). |
2385 | That's used when we eliminate in expressions stored in notes. | |
2386 | This means, do not set ref_outside_mem even if the reference | |
2387 | is outside of MEMs. | |
2388 | ||
32131a9c RK |
2389 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had |
2390 | replacements done assuming all offsets are at their initial values. If | |
2391 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | |
2392 | encounter, return the actual location so that find_reloads will do | |
2393 | the proper thing. */ | |
2394 | ||
ab156144 RH |
2395 | static rtx |
2396 | eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn, | |
2397 | bool may_use_invariant) | |
32131a9c RK |
2398 | { |
2399 | enum rtx_code code = GET_CODE (x); | |
2400 | struct elim_table *ep; | |
2401 | int regno; | |
2402 | rtx new; | |
2403 | int i, j; | |
6f7d635c | 2404 | const char *fmt; |
32131a9c RK |
2405 | int copied = 0; |
2406 | ||
d6633f01 NS |
2407 | if (! current_function_decl) |
2408 | return x; | |
9969bb2c | 2409 | |
32131a9c RK |
2410 | switch (code) |
2411 | { | |
2412 | case CONST_INT: | |
2413 | case CONST_DOUBLE: | |
69ef87e2 | 2414 | case CONST_VECTOR: |
32131a9c RK |
2415 | case CONST: |
2416 | case SYMBOL_REF: | |
2417 | case CODE_LABEL: | |
2418 | case PC: | |
2419 | case CC0: | |
2420 | case ASM_INPUT: | |
2421 | case ADDR_VEC: | |
2422 | case ADDR_DIFF_VEC: | |
2423 | case RETURN: | |
2424 | return x; | |
2425 | ||
2426 | case REG: | |
2427 | regno = REGNO (x); | |
2428 | ||
2429 | /* First handle the case where we encounter a bare register that | |
2430 | is eliminable. Replace it with a PLUS. */ | |
2431 | if (regno < FIRST_PSEUDO_REGISTER) | |
2432 | { | |
2433 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2434 | ep++) | |
2435 | if (ep->from_rtx == x && ep->can_eliminate) | |
dfac187e | 2436 | return plus_constant (ep->to_rtx, ep->previous_offset); |
32131a9c RK |
2437 | |
2438 | } | |
cd7c9015 | 2439 | else if (reg_renumber && reg_renumber[regno] < 0 |
ab156144 RH |
2440 | && reg_equiv_invariant && reg_equiv_invariant[regno]) |
2441 | { | |
2442 | if (may_use_invariant) | |
2443 | return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]), | |
2444 | mem_mode, insn, true); | |
2445 | /* There exists at least one use of REGNO that cannot be | |
2446 | eliminated. Prevent the defining insn from being deleted. */ | |
2447 | reg_equiv_init[regno] = NULL_RTX; | |
2448 | alter_reg (regno, -1); | |
2449 | } | |
32131a9c RK |
2450 | return x; |
2451 | ||
c5c76735 JL |
2452 | /* You might think handling MINUS in a manner similar to PLUS is a |
2453 | good idea. It is not. It has been tried multiple times and every | |
2454 | time the change has had to have been reverted. | |
2455 | ||
2456 | Other parts of reload know a PLUS is special (gen_reload for example) | |
2457 | and require special code to handle code a reloaded PLUS operand. | |
2458 | ||
2459 | Also consider backends where the flags register is clobbered by a | |
a457ee07 | 2460 | MINUS, but we can emit a PLUS that does not clobber flags (IA-32, |
c5c76735 JL |
2461 | lea instruction comes to mind). If we try to reload a MINUS, we |
2462 | may kill the flags register that was holding a useful value. | |
2463 | ||
2464 | So, please before trying to handle MINUS, consider reload as a | |
2465 | whole instead of this little section as well as the backend issues. */ | |
32131a9c RK |
2466 | case PLUS: |
2467 | /* If this is the sum of an eliminable register and a constant, rework | |
6d2f8887 | 2468 | the sum. */ |
f8cfc6aa | 2469 | if (REG_P (XEXP (x, 0)) |
32131a9c RK |
2470 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER |
2471 | && CONSTANT_P (XEXP (x, 1))) | |
2472 | { | |
2473 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2474 | ep++) | |
2475 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2476 | { | |
32131a9c RK |
2477 | /* The only time we want to replace a PLUS with a REG (this |
2478 | occurs when the constant operand of the PLUS is the negative | |
2479 | of the offset) is when we are inside a MEM. We won't want | |
2480 | to do so at other times because that would change the | |
2481 | structure of the insn in a way that reload can't handle. | |
2482 | We special-case the commonest situation in | |
2483 | eliminate_regs_in_insn, so just replace a PLUS with a | |
2484 | PLUS here, unless inside a MEM. */ | |
a23b64d5 | 2485 | if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT |
32131a9c RK |
2486 | && INTVAL (XEXP (x, 1)) == - ep->previous_offset) |
2487 | return ep->to_rtx; | |
2488 | else | |
38a448ca RH |
2489 | return gen_rtx_PLUS (Pmode, ep->to_rtx, |
2490 | plus_constant (XEXP (x, 1), | |
2491 | ep->previous_offset)); | |
32131a9c RK |
2492 | } |
2493 | ||
2494 | /* If the register is not eliminable, we are done since the other | |
2495 | operand is a constant. */ | |
2496 | return x; | |
2497 | } | |
2498 | ||
2499 | /* If this is part of an address, we want to bring any constant to the | |
2500 | outermost PLUS. We will do this by doing register replacement in | |
2501 | our operands and seeing if a constant shows up in one of them. | |
2502 | ||
dfac187e BS |
2503 | Note that there is no risk of modifying the structure of the insn, |
2504 | since we only get called for its operands, thus we are either | |
2505 | modifying the address inside a MEM, or something like an address | |
2506 | operand of a load-address insn. */ | |
32131a9c RK |
2507 | |
2508 | { | |
ab156144 RH |
2509 | rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); |
2510 | rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); | |
32131a9c | 2511 | |
cd7c9015 | 2512 | if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))) |
32131a9c RK |
2513 | { |
2514 | /* If one side is a PLUS and the other side is a pseudo that | |
a8fdc208 | 2515 | didn't get a hard register but has a reg_equiv_constant, |
32131a9c RK |
2516 | we must replace the constant here since it may no longer |
2517 | be in the position of any operand. */ | |
f8cfc6aa | 2518 | if (GET_CODE (new0) == PLUS && REG_P (new1) |
32131a9c RK |
2519 | && REGNO (new1) >= FIRST_PSEUDO_REGISTER |
2520 | && reg_renumber[REGNO (new1)] < 0 | |
2521 | && reg_equiv_constant != 0 | |
2522 | && reg_equiv_constant[REGNO (new1)] != 0) | |
2523 | new1 = reg_equiv_constant[REGNO (new1)]; | |
f8cfc6aa | 2524 | else if (GET_CODE (new1) == PLUS && REG_P (new0) |
32131a9c RK |
2525 | && REGNO (new0) >= FIRST_PSEUDO_REGISTER |
2526 | && reg_renumber[REGNO (new0)] < 0 | |
2527 | && reg_equiv_constant[REGNO (new0)] != 0) | |
2528 | new0 = reg_equiv_constant[REGNO (new0)]; | |
2529 | ||
2530 | new = form_sum (new0, new1); | |
2531 | ||
2532 | /* As above, if we are not inside a MEM we do not want to | |
2533 | turn a PLUS into something else. We might try to do so here | |
2534 | for an addition of 0 if we aren't optimizing. */ | |
2535 | if (! mem_mode && GET_CODE (new) != PLUS) | |
38a448ca | 2536 | return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx); |
32131a9c RK |
2537 | else |
2538 | return new; | |
2539 | } | |
2540 | } | |
2541 | return x; | |
2542 | ||
981c7390 | 2543 | case MULT: |
05d10675 | 2544 | /* If this is the product of an eliminable register and a |
981c7390 RK |
2545 | constant, apply the distribute law and move the constant out |
2546 | so that we have (plus (mult ..) ..). This is needed in order | |
9faa82d8 | 2547 | to keep load-address insns valid. This case is pathological. |
981c7390 | 2548 | We ignore the possibility of overflow here. */ |
f8cfc6aa | 2549 | if (REG_P (XEXP (x, 0)) |
981c7390 RK |
2550 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER |
2551 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2552 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2553 | ep++) | |
2554 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2555 | { | |
2556 | if (! mem_mode | |
2557 | /* Refs inside notes don't count for this purpose. */ | |
2558 | && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST | |
2559 | || GET_CODE (insn) == INSN_LIST))) | |
2560 | ep->ref_outside_mem = 1; | |
2561 | ||
2562 | return | |
38a448ca | 2563 | plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), |
981c7390 RK |
2564 | ep->previous_offset * INTVAL (XEXP (x, 1))); |
2565 | } | |
32131a9c | 2566 | |
0f41302f | 2567 | /* ... fall through ... */ |
32131a9c | 2568 | |
32131a9c RK |
2569 | case CALL: |
2570 | case COMPARE: | |
c5c76735 | 2571 | /* See comments before PLUS about handling MINUS. */ |
930aeef3 | 2572 | case MINUS: |
32131a9c RK |
2573 | case DIV: case UDIV: |
2574 | case MOD: case UMOD: | |
2575 | case AND: case IOR: case XOR: | |
45620ed4 RK |
2576 | case ROTATERT: case ROTATE: |
2577 | case ASHIFTRT: case LSHIFTRT: case ASHIFT: | |
32131a9c RK |
2578 | case NE: case EQ: |
2579 | case GE: case GT: case GEU: case GTU: | |
2580 | case LE: case LT: case LEU: case LTU: | |
2581 | { | |
ab156144 RH |
2582 | rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); |
2583 | rtx new1 = XEXP (x, 1) | |
2584 | ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0; | |
32131a9c RK |
2585 | |
2586 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
38a448ca | 2587 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); |
32131a9c RK |
2588 | } |
2589 | return x; | |
2590 | ||
981c7390 RK |
2591 | case EXPR_LIST: |
2592 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | |
2593 | if (XEXP (x, 0)) | |
2594 | { | |
ab156144 | 2595 | new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); |
981c7390 | 2596 | if (new != XEXP (x, 0)) |
13bb79d4 R |
2597 | { |
2598 | /* If this is a REG_DEAD note, it is not valid anymore. | |
2599 | Using the eliminated version could result in creating a | |
2600 | REG_DEAD note for the stack or frame pointer. */ | |
2601 | if (GET_MODE (x) == REG_DEAD) | |
2602 | return (XEXP (x, 1) | |
ab156144 | 2603 | ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true) |
13bb79d4 R |
2604 | : NULL_RTX); |
2605 | ||
2606 | x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1)); | |
2607 | } | |
981c7390 RK |
2608 | } |
2609 | ||
0f41302f | 2610 | /* ... fall through ... */ |
981c7390 RK |
2611 | |
2612 | case INSN_LIST: | |
2613 | /* Now do eliminations in the rest of the chain. If this was | |
2614 | an EXPR_LIST, this might result in allocating more memory than is | |
2615 | strictly needed, but it simplifies the code. */ | |
2616 | if (XEXP (x, 1)) | |
2617 | { | |
ab156144 | 2618 | new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); |
981c7390 | 2619 | if (new != XEXP (x, 1)) |
cd7c9015 RK |
2620 | return |
2621 | gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new); | |
981c7390 RK |
2622 | } |
2623 | return x; | |
2624 | ||
32131a9c RK |
2625 | case PRE_INC: |
2626 | case POST_INC: | |
2627 | case PRE_DEC: | |
2628 | case POST_DEC: | |
b098aaf2 UW |
2629 | /* We do not support elimination of a register that is modified. |
2630 | elimination_effects has already make sure that this does not | |
2631 | happen. */ | |
2632 | return x; | |
2633 | ||
2634 | case PRE_MODIFY: | |
2635 | case POST_MODIFY: | |
2636 | /* We do not support elimination of a register that is modified. | |
2637 | elimination_effects has already make sure that this does not | |
2638 | happen. The only remaining case we need to consider here is | |
2639 | that the increment value may be an eliminable register. */ | |
2640 | if (GET_CODE (XEXP (x, 1)) == PLUS | |
2641 | && XEXP (XEXP (x, 1), 0) == XEXP (x, 0)) | |
2642 | { | |
2643 | rtx new = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode, | |
2644 | insn, true); | |
2645 | ||
2646 | if (new != XEXP (XEXP (x, 1), 1)) | |
2647 | return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0), | |
2648 | gen_rtx_PLUS (GET_MODE (x), | |
2649 | XEXP (x, 0), new)); | |
2650 | } | |
2651 | return x; | |
2652 | ||
32131a9c RK |
2653 | case STRICT_LOW_PART: |
2654 | case NEG: case NOT: | |
2655 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2656 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2657 | case FLOAT: case FIX: | |
2658 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2659 | case ABS: | |
2660 | case SQRT: | |
2661 | case FFS: | |
2928cd7a RH |
2662 | case CLZ: |
2663 | case CTZ: | |
2664 | case POPCOUNT: | |
2665 | case PARITY: | |
167fa32c | 2666 | case BSWAP: |
ab156144 | 2667 | new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); |
32131a9c | 2668 | if (new != XEXP (x, 0)) |
38a448ca | 2669 | return gen_rtx_fmt_e (code, GET_MODE (x), new); |
32131a9c RK |
2670 | return x; |
2671 | ||
2672 | case SUBREG: | |
ddef6bc7 | 2673 | /* Similar to above processing, but preserve SUBREG_BYTE. |
32131a9c RK |
2674 | Convert (subreg (mem)) to (mem) if not paradoxical. |
2675 | Also, if we have a non-paradoxical (subreg (pseudo)) and the | |
2676 | pseudo didn't get a hard reg, we must replace this with the | |
bd235d86 | 2677 | eliminated version of the memory location because push_reload |
32131a9c | 2678 | may do the replacement in certain circumstances. */ |
f8cfc6aa | 2679 | if (REG_P (SUBREG_REG (x)) |
32131a9c RK |
2680 | && (GET_MODE_SIZE (GET_MODE (x)) |
2681 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2682 | && reg_equiv_memory_loc != 0 | |
2683 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2684 | { | |
cb2afeb3 | 2685 | new = SUBREG_REG (x); |
32131a9c RK |
2686 | } |
2687 | else | |
ab156144 | 2688 | new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false); |
32131a9c | 2689 | |
ddef6bc7 | 2690 | if (new != SUBREG_REG (x)) |
32131a9c | 2691 | { |
29ae5012 RK |
2692 | int x_size = GET_MODE_SIZE (GET_MODE (x)); |
2693 | int new_size = GET_MODE_SIZE (GET_MODE (new)); | |
2694 | ||
3c0cb5de | 2695 | if (MEM_P (new) |
6d49a073 | 2696 | && ((x_size < new_size |
1914f5da | 2697 | #ifdef WORD_REGISTER_OPERATIONS |
6d49a073 JW |
2698 | /* On these machines, combine can create rtl of the form |
2699 | (set (subreg:m1 (reg:m2 R) 0) ...) | |
05d10675 | 2700 | where m1 < m2, and expects something interesting to |
6d49a073 JW |
2701 | happen to the entire word. Moreover, it will use the |
2702 | (reg:m2 R) later, expecting all bits to be preserved. | |
05d10675 | 2703 | So if the number of words is the same, preserve the |
bd235d86 | 2704 | subreg so that push_reload can see it. */ |
5d9669fd RK |
2705 | && ! ((x_size - 1) / UNITS_PER_WORD |
2706 | == (new_size -1 ) / UNITS_PER_WORD) | |
1914f5da | 2707 | #endif |
6d49a073 | 2708 | ) |
5d9669fd | 2709 | || x_size == new_size) |
1914f5da | 2710 | ) |
a2ff290c | 2711 | return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x)); |
32131a9c | 2712 | else |
ddef6bc7 | 2713 | return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x)); |
32131a9c RK |
2714 | } |
2715 | ||
2716 | return x; | |
2717 | ||
32131a9c RK |
2718 | case MEM: |
2719 | /* Our only special processing is to pass the mode of the MEM to our | |
2720 | recursive call and copy the flags. While we are here, handle this | |
2721 | case more efficiently. */ | |
f1ec5147 RK |
2722 | return |
2723 | replace_equiv_address_nv (x, | |
ab156144 RH |
2724 | eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), |
2725 | insn, true)); | |
05d10675 | 2726 | |
dfac187e | 2727 | case USE: |
055c7759 | 2728 | /* Handle insn_list USE that a call to a pure function may generate. */ |
ab156144 | 2729 | new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false); |
055c7759 JDA |
2730 | if (new != XEXP (x, 0)) |
2731 | return gen_rtx_USE (GET_MODE (x), new); | |
2732 | return x; | |
2733 | ||
dfac187e BS |
2734 | case CLOBBER: |
2735 | case ASM_OPERANDS: | |
2736 | case SET: | |
41374e13 | 2737 | gcc_unreachable (); |
dfac187e | 2738 | |
e9a25f70 JL |
2739 | default: |
2740 | break; | |
32131a9c RK |
2741 | } |
2742 | ||
2743 | /* Process each of our operands recursively. If any have changed, make a | |
2744 | copy of the rtx. */ | |
2745 | fmt = GET_RTX_FORMAT (code); | |
2746 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2747 | { | |
2748 | if (*fmt == 'e') | |
2749 | { | |
ab156144 | 2750 | new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false); |
32131a9c RK |
2751 | if (new != XEXP (x, i) && ! copied) |
2752 | { | |
aacd3885 | 2753 | x = shallow_copy_rtx (x); |
32131a9c RK |
2754 | copied = 1; |
2755 | } | |
2756 | XEXP (x, i) = new; | |
2757 | } | |
2758 | else if (*fmt == 'E') | |
2759 | { | |
2760 | int copied_vec = 0; | |
2761 | for (j = 0; j < XVECLEN (x, i); j++) | |
2762 | { | |
ab156144 | 2763 | new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false); |
32131a9c RK |
2764 | if (new != XVECEXP (x, i, j) && ! copied_vec) |
2765 | { | |
8f985ec4 ZW |
2766 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), |
2767 | XVEC (x, i)->elem); | |
32131a9c RK |
2768 | if (! copied) |
2769 | { | |
aacd3885 | 2770 | x = shallow_copy_rtx (x); |
32131a9c RK |
2771 | copied = 1; |
2772 | } | |
2773 | XVEC (x, i) = new_v; | |
2774 | copied_vec = 1; | |
2775 | } | |
2776 | XVECEXP (x, i, j) = new; | |
2777 | } | |
2778 | } | |
2779 | } | |
2780 | ||
2781 | return x; | |
2782 | } | |
dfac187e | 2783 | |
ab156144 RH |
2784 | rtx |
2785 | eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn) | |
2786 | { | |
2787 | return eliminate_regs_1 (x, mem_mode, insn, false); | |
2788 | } | |
2789 | ||
dfac187e BS |
2790 | /* Scan rtx X for modifications of elimination target registers. Update |
2791 | the table of eliminables to reflect the changed state. MEM_MODE is | |
2792 | the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ | |
2793 | ||
2794 | static void | |
0c20a65f | 2795 | elimination_effects (rtx x, enum machine_mode mem_mode) |
dfac187e BS |
2796 | { |
2797 | enum rtx_code code = GET_CODE (x); | |
2798 | struct elim_table *ep; | |
2799 | int regno; | |
2800 | int i, j; | |
2801 | const char *fmt; | |
2802 | ||
2803 | switch (code) | |
2804 | { | |
2805 | case CONST_INT: | |
2806 | case CONST_DOUBLE: | |
69ef87e2 | 2807 | case CONST_VECTOR: |
dfac187e BS |
2808 | case CONST: |
2809 | case SYMBOL_REF: | |
2810 | case CODE_LABEL: | |
2811 | case PC: | |
2812 | case CC0: | |
2813 | case ASM_INPUT: | |
2814 | case ADDR_VEC: | |
2815 | case ADDR_DIFF_VEC: | |
2816 | case RETURN: | |
2817 | return; | |
2818 | ||
dfac187e BS |
2819 | case REG: |
2820 | regno = REGNO (x); | |
2821 | ||
2822 | /* First handle the case where we encounter a bare register that | |
2823 | is eliminable. Replace it with a PLUS. */ | |
2824 | if (regno < FIRST_PSEUDO_REGISTER) | |
2825 | { | |
2826 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2827 | ep++) | |
2828 | if (ep->from_rtx == x && ep->can_eliminate) | |
2829 | { | |
2830 | if (! mem_mode) | |
2831 | ep->ref_outside_mem = 1; | |
2832 | return; | |
2833 | } | |
2834 | ||
2835 | } | |
2836 | else if (reg_renumber[regno] < 0 && reg_equiv_constant | |
2837 | && reg_equiv_constant[regno] | |
92a21141 | 2838 | && ! function_invariant_p (reg_equiv_constant[regno])) |
dfac187e BS |
2839 | elimination_effects (reg_equiv_constant[regno], mem_mode); |
2840 | return; | |
2841 | ||
2842 | case PRE_INC: | |
2843 | case POST_INC: | |
2844 | case PRE_DEC: | |
2845 | case POST_DEC: | |
4b983fdc RH |
2846 | case POST_MODIFY: |
2847 | case PRE_MODIFY: | |
b098aaf2 UW |
2848 | /* If we modify the source of an elimination rule, disable it. */ |
2849 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2850 | if (ep->from_rtx == XEXP (x, 0)) | |
2851 | ep->can_eliminate = 0; | |
2852 | ||
2853 | /* If we modify the target of an elimination rule by adding a constant, | |
2854 | update its offset. If we modify the target in any other way, we'll | |
2855 | have to disable the rule as well. */ | |
dfac187e BS |
2856 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
2857 | if (ep->to_rtx == XEXP (x, 0)) | |
2858 | { | |
2859 | int size = GET_MODE_SIZE (mem_mode); | |
2860 | ||
2861 | /* If more bytes than MEM_MODE are pushed, account for them. */ | |
2862 | #ifdef PUSH_ROUNDING | |
2863 | if (ep->to_rtx == stack_pointer_rtx) | |
2864 | size = PUSH_ROUNDING (size); | |
2865 | #endif | |
2866 | if (code == PRE_DEC || code == POST_DEC) | |
2867 | ep->offset += size; | |
4b983fdc | 2868 | else if (code == PRE_INC || code == POST_INC) |
dfac187e | 2869 | ep->offset -= size; |
b098aaf2 UW |
2870 | else if (code == PRE_MODIFY || code == POST_MODIFY) |
2871 | { | |
2872 | if (GET_CODE (XEXP (x, 1)) == PLUS | |
2873 | && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) | |
2874 | && CONST_INT_P (XEXP (XEXP (x, 1), 1))) | |
2875 | ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1)); | |
2876 | else | |
2877 | ep->can_eliminate = 0; | |
2878 | } | |
dfac187e BS |
2879 | } |
2880 | ||
4b983fdc RH |
2881 | /* These two aren't unary operators. */ |
2882 | if (code == POST_MODIFY || code == PRE_MODIFY) | |
2883 | break; | |
2884 | ||
dfac187e BS |
2885 | /* Fall through to generic unary operation case. */ |
2886 | case STRICT_LOW_PART: | |
2887 | case NEG: case NOT: | |
2888 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2889 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2890 | case FLOAT: case FIX: | |
2891 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2892 | case ABS: | |
2893 | case SQRT: | |
2894 | case FFS: | |
2928cd7a RH |
2895 | case CLZ: |
2896 | case CTZ: | |
2897 | case POPCOUNT: | |
2898 | case PARITY: | |
167fa32c | 2899 | case BSWAP: |
dfac187e BS |
2900 | elimination_effects (XEXP (x, 0), mem_mode); |
2901 | return; | |
2902 | ||
2903 | case SUBREG: | |
f8cfc6aa | 2904 | if (REG_P (SUBREG_REG (x)) |
dfac187e BS |
2905 | && (GET_MODE_SIZE (GET_MODE (x)) |
2906 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2907 | && reg_equiv_memory_loc != 0 | |
2908 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2909 | return; | |
2910 | ||
2911 | elimination_effects (SUBREG_REG (x), mem_mode); | |
2912 | return; | |
2913 | ||
2914 | case USE: | |
2915 | /* If using a register that is the source of an eliminate we still | |
2916 | think can be performed, note it cannot be performed since we don't | |
2917 | know how this register is used. */ | |
2918 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2919 | if (ep->from_rtx == XEXP (x, 0)) | |
2920 | ep->can_eliminate = 0; | |
2921 | ||
2922 | elimination_effects (XEXP (x, 0), mem_mode); | |
2923 | return; | |
2924 | ||
2925 | case CLOBBER: | |
2926 | /* If clobbering a register that is the replacement register for an | |
2927 | elimination we still think can be performed, note that it cannot | |
2928 | be performed. Otherwise, we need not be concerned about it. */ | |
2929 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2930 | if (ep->to_rtx == XEXP (x, 0)) | |
2931 | ep->can_eliminate = 0; | |
2932 | ||
2933 | elimination_effects (XEXP (x, 0), mem_mode); | |
2934 | return; | |
2935 | ||
2936 | case SET: | |
2937 | /* Check for setting a register that we know about. */ | |
f8cfc6aa | 2938 | if (REG_P (SET_DEST (x))) |
dfac187e BS |
2939 | { |
2940 | /* See if this is setting the replacement register for an | |
2941 | elimination. | |
2942 | ||
2943 | If DEST is the hard frame pointer, we do nothing because we | |
2944 | assume that all assignments to the frame pointer are for | |
2945 | non-local gotos and are being done at a time when they are valid | |
2946 | and do not disturb anything else. Some machines want to | |
2947 | eliminate a fake argument pointer (or even a fake frame pointer) | |
2948 | with either the real frame or the stack pointer. Assignments to | |
2949 | the hard frame pointer must not prevent this elimination. */ | |
2950 | ||
2951 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2952 | ep++) | |
2953 | if (ep->to_rtx == SET_DEST (x) | |
2954 | && SET_DEST (x) != hard_frame_pointer_rtx) | |
2955 | { | |
2956 | /* If it is being incremented, adjust the offset. Otherwise, | |
2957 | this elimination can't be done. */ | |
2958 | rtx src = SET_SRC (x); | |
2959 | ||
2960 | if (GET_CODE (src) == PLUS | |
2961 | && XEXP (src, 0) == SET_DEST (x) | |
2962 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2963 | ep->offset -= INTVAL (XEXP (src, 1)); | |
2964 | else | |
2965 | ep->can_eliminate = 0; | |
2966 | } | |
2967 | } | |
2968 | ||
2969 | elimination_effects (SET_DEST (x), 0); | |
2970 | elimination_effects (SET_SRC (x), 0); | |
2971 | return; | |
2972 | ||
2973 | case MEM: | |
dfac187e BS |
2974 | /* Our only special processing is to pass the mode of the MEM to our |
2975 | recursive call. */ | |
2976 | elimination_effects (XEXP (x, 0), GET_MODE (x)); | |
2977 | return; | |
2978 | ||
2979 | default: | |
2980 | break; | |
2981 | } | |
2982 | ||
2983 | fmt = GET_RTX_FORMAT (code); | |
2984 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2985 | { | |
2986 | if (*fmt == 'e') | |
2987 | elimination_effects (XEXP (x, i), mem_mode); | |
2988 | else if (*fmt == 'E') | |
2989 | for (j = 0; j < XVECLEN (x, i); j++) | |
2990 | elimination_effects (XVECEXP (x, i, j), mem_mode); | |
2991 | } | |
2992 | } | |
2993 | ||
2994 | /* Descend through rtx X and verify that no references to eliminable registers | |
2995 | remain. If any do remain, mark the involved register as not | |
2996 | eliminable. */ | |
1d813780 | 2997 | |
dfac187e | 2998 | static void |
0c20a65f | 2999 | check_eliminable_occurrences (rtx x) |
dfac187e BS |
3000 | { |
3001 | const char *fmt; | |
3002 | int i; | |
3003 | enum rtx_code code; | |
3004 | ||
3005 | if (x == 0) | |
3006 | return; | |
1d7254c5 | 3007 | |
dfac187e BS |
3008 | code = GET_CODE (x); |
3009 | ||
3010 | if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
3011 | { | |
3012 | struct elim_table *ep; | |
3013 | ||
3014 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
761fa0f7 | 3015 | if (ep->from_rtx == x) |
dfac187e BS |
3016 | ep->can_eliminate = 0; |
3017 | return; | |
3018 | } | |
1d7254c5 | 3019 | |
dfac187e BS |
3020 | fmt = GET_RTX_FORMAT (code); |
3021 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
3022 | { | |
3023 | if (*fmt == 'e') | |
3024 | check_eliminable_occurrences (XEXP (x, i)); | |
3025 | else if (*fmt == 'E') | |
3026 | { | |
3027 | int j; | |
3028 | for (j = 0; j < XVECLEN (x, i); j++) | |
3029 | check_eliminable_occurrences (XVECEXP (x, i, j)); | |
3030 | } | |
3031 | } | |
3032 | } | |
32131a9c RK |
3033 | \f |
3034 | /* Scan INSN and eliminate all eliminable registers in it. | |
3035 | ||
3036 | If REPLACE is nonzero, do the replacement destructively. Also | |
3037 | delete the insn as dead it if it is setting an eliminable register. | |
3038 | ||
3039 | If REPLACE is zero, do all our allocations in reload_obstack. | |
3040 | ||
3041 | If no eliminations were done and this insn doesn't require any elimination | |
3042 | processing (these are not identical conditions: it might be updating sp, | |
3043 | but not referencing fp; this needs to be seen during reload_as_needed so | |
3044 | that the offset between fp and sp can be taken into consideration), zero | |
3045 | is returned. Otherwise, 1 is returned. */ | |
3046 | ||
3047 | static int | |
0c20a65f | 3048 | eliminate_regs_in_insn (rtx insn, int replace) |
32131a9c | 3049 | { |
dfac187e | 3050 | int icode = recog_memoized (insn); |
32131a9c | 3051 | rtx old_body = PATTERN (insn); |
dfac187e | 3052 | int insn_is_asm = asm_noperands (old_body) >= 0; |
774672d2 | 3053 | rtx old_set = single_set (insn); |
32131a9c RK |
3054 | rtx new_body; |
3055 | int val = 0; | |
4977bab6 | 3056 | int i; |
dfac187e BS |
3057 | rtx substed_operand[MAX_RECOG_OPERANDS]; |
3058 | rtx orig_operand[MAX_RECOG_OPERANDS]; | |
32131a9c | 3059 | struct elim_table *ep; |
ab156144 | 3060 | rtx plus_src, plus_cst_src; |
32131a9c | 3061 | |
dfac187e BS |
3062 | if (! insn_is_asm && icode < 0) |
3063 | { | |
41374e13 NS |
3064 | gcc_assert (GET_CODE (PATTERN (insn)) == USE |
3065 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
3066 | || GET_CODE (PATTERN (insn)) == ADDR_VEC | |
3067 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
3068 | || GET_CODE (PATTERN (insn)) == ASM_INPUT); | |
3069 | return 0; | |
dfac187e BS |
3070 | } |
3071 | ||
f8cfc6aa | 3072 | if (old_set != 0 && REG_P (SET_DEST (old_set)) |
774672d2 | 3073 | && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) |
32131a9c RK |
3074 | { |
3075 | /* Check for setting an eliminable register. */ | |
3076 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
774672d2 | 3077 | if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) |
32131a9c | 3078 | { |
dd1eab0a RK |
3079 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
3080 | /* If this is setting the frame pointer register to the | |
3081 | hardware frame pointer register and this is an elimination | |
3082 | that will be done (tested above), this insn is really | |
3083 | adjusting the frame pointer downward to compensate for | |
3084 | the adjustment done before a nonlocal goto. */ | |
3085 | if (ep->from == FRAME_POINTER_REGNUM | |
3086 | && ep->to == HARD_FRAME_POINTER_REGNUM) | |
3087 | { | |
75eefe3f UW |
3088 | rtx base = SET_SRC (old_set); |
3089 | rtx base_insn = insn; | |
b19ee4bd | 3090 | HOST_WIDE_INT offset = 0; |
75eefe3f UW |
3091 | |
3092 | while (base != ep->to_rtx) | |
8026ebba | 3093 | { |
75eefe3f UW |
3094 | rtx prev_insn, prev_set; |
3095 | ||
3096 | if (GET_CODE (base) == PLUS | |
3097 | && GET_CODE (XEXP (base, 1)) == CONST_INT) | |
3098 | { | |
3099 | offset += INTVAL (XEXP (base, 1)); | |
3100 | base = XEXP (base, 0); | |
3101 | } | |
3102 | else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0 | |
3103 | && (prev_set = single_set (prev_insn)) != 0 | |
3104 | && rtx_equal_p (SET_DEST (prev_set), base)) | |
3105 | { | |
3106 | base = SET_SRC (prev_set); | |
3107 | base_insn = prev_insn; | |
3108 | } | |
3109 | else | |
3110 | break; | |
8026ebba | 3111 | } |
dd1eab0a | 3112 | |
75eefe3f | 3113 | if (base == ep->to_rtx) |
dd1eab0a | 3114 | { |
c77fbfbe GK |
3115 | rtx src |
3116 | = plus_constant (ep->to_rtx, offset - ep->offset); | |
3117 | ||
3118 | new_body = old_body; | |
3119 | if (! replace) | |
3120 | { | |
3121 | new_body = copy_insn (old_body); | |
3122 | if (REG_NOTES (insn)) | |
3123 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3124 | } | |
3125 | PATTERN (insn) = new_body; | |
3126 | old_set = single_set (insn); | |
3127 | ||
3128 | /* First see if this insn remains valid when we | |
3129 | make the change. If not, keep the INSN_CODE | |
3130 | the same and let reload fit it up. */ | |
3131 | validate_change (insn, &SET_SRC (old_set), src, 1); | |
3132 | validate_change (insn, &SET_DEST (old_set), | |
3133 | ep->to_rtx, 1); | |
3134 | if (! apply_change_group ()) | |
dd1eab0a | 3135 | { |
c77fbfbe GK |
3136 | SET_SRC (old_set) = src; |
3137 | SET_DEST (old_set) = ep->to_rtx; | |
dd1eab0a RK |
3138 | } |
3139 | ||
3140 | val = 1; | |
3141 | goto done; | |
3142 | } | |
3143 | } | |
3144 | #endif | |
3145 | ||
32131a9c RK |
3146 | /* In this case this insn isn't serving a useful purpose. We |
3147 | will delete it in reload_as_needed once we know that this | |
3148 | elimination is, in fact, being done. | |
3149 | ||
abc95ed3 | 3150 | If REPLACE isn't set, we can't delete this insn, but needn't |
32131a9c RK |
3151 | process it since it won't be used unless something changes. */ |
3152 | if (replace) | |
8a34409d | 3153 | { |
1d7254c5 | 3154 | delete_dead_insn (insn); |
8a34409d RH |
3155 | return 1; |
3156 | } | |
32131a9c RK |
3157 | val = 1; |
3158 | goto done; | |
3159 | } | |
aa5524a9 | 3160 | } |
32131a9c | 3161 | |
aa5524a9 | 3162 | /* We allow one special case which happens to work on all machines we |
ace3ffcd KH |
3163 | currently support: a single set with the source or a REG_EQUAL |
3164 | note being a PLUS of an eliminable register and a constant. */ | |
ab156144 | 3165 | plus_src = plus_cst_src = 0; |
f8cfc6aa | 3166 | if (old_set && REG_P (SET_DEST (old_set))) |
aa5524a9 | 3167 | { |
ab156144 | 3168 | if (GET_CODE (SET_SRC (old_set)) == PLUS) |
ace3ffcd | 3169 | plus_src = SET_SRC (old_set); |
7efd40b5 | 3170 | /* First see if the source is of the form (plus (...) CST). */ |
ab156144 | 3171 | if (plus_src |
7efd40b5 | 3172 | && GET_CODE (XEXP (plus_src, 1)) == CONST_INT) |
ab156144 RH |
3173 | plus_cst_src = plus_src; |
3174 | else if (REG_P (SET_SRC (old_set)) | |
3175 | || plus_src) | |
ace3ffcd KH |
3176 | { |
3177 | /* Otherwise, see if we have a REG_EQUAL note of the form | |
7efd40b5 | 3178 | (plus (...) CST). */ |
ace3ffcd KH |
3179 | rtx links; |
3180 | for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) | |
3181 | { | |
7c11b28c BS |
3182 | if ((REG_NOTE_KIND (links) == REG_EQUAL |
3183 | || REG_NOTE_KIND (links) == REG_EQUIV) | |
ace3ffcd | 3184 | && GET_CODE (XEXP (links, 0)) == PLUS |
7efd40b5 | 3185 | && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT) |
ace3ffcd | 3186 | { |
ab156144 | 3187 | plus_cst_src = XEXP (links, 0); |
ace3ffcd KH |
3188 | break; |
3189 | } | |
3190 | } | |
3191 | } | |
7efd40b5 UW |
3192 | |
3193 | /* Check that the first operand of the PLUS is a hard reg or | |
3194 | the lowpart subreg of one. */ | |
3195 | if (plus_cst_src) | |
3196 | { | |
3197 | rtx reg = XEXP (plus_cst_src, 0); | |
3198 | if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg)) | |
3199 | reg = SUBREG_REG (reg); | |
3200 | ||
3201 | if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) | |
3202 | plus_cst_src = 0; | |
3203 | } | |
ace3ffcd | 3204 | } |
ab156144 | 3205 | if (plus_cst_src) |
ace3ffcd | 3206 | { |
ab156144 RH |
3207 | rtx reg = XEXP (plus_cst_src, 0); |
3208 | HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1)); | |
32131a9c | 3209 | |
7efd40b5 UW |
3210 | if (GET_CODE (reg) == SUBREG) |
3211 | reg = SUBREG_REG (reg); | |
3212 | ||
aa5524a9 BS |
3213 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3214 | if (ep->from_rtx == reg && ep->can_eliminate) | |
3215 | { | |
7efd40b5 | 3216 | rtx to_rtx = ep->to_rtx; |
aa5524a9 | 3217 | offset += ep->offset; |
4c9034c5 | 3218 | offset = trunc_int_for_mode (offset, GET_MODE (reg)); |
32131a9c | 3219 | |
7efd40b5 UW |
3220 | if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG) |
3221 | to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)), | |
3222 | to_rtx); | |
8c1249f9 PB |
3223 | /* If we have a nonzero offset, and the source is already |
3224 | a simple REG, the following transformation would | |
3225 | increase the cost of the insn by replacing a simple REG | |
3226 | with (plus (reg sp) CST). So try only when we already | |
3227 | had a PLUS before. */ | |
551d6929 | 3228 | if (offset == 0 || plus_src) |
8c1249f9 | 3229 | { |
551d6929 UW |
3230 | rtx new_src = plus_constant (to_rtx, offset); |
3231 | ||
8c1249f9 PB |
3232 | new_body = old_body; |
3233 | if (! replace) | |
3234 | { | |
3235 | new_body = copy_insn (old_body); | |
3236 | if (REG_NOTES (insn)) | |
3237 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3238 | } | |
3239 | PATTERN (insn) = new_body; | |
3240 | old_set = single_set (insn); | |
3241 | ||
551d6929 UW |
3242 | /* First see if this insn remains valid when we make the |
3243 | change. If not, try to replace the whole pattern with | |
3244 | a simple set (this may help if the original insn was a | |
3245 | PARALLEL that was only recognized as single_set due to | |
3246 | REG_UNUSED notes). If this isn't valid either, keep | |
3247 | the INSN_CODE the same and let reload fix it up. */ | |
3248 | if (!validate_change (insn, &SET_SRC (old_set), new_src, 0)) | |
3249 | { | |
3250 | rtx new_pat = gen_rtx_SET (VOIDmode, | |
3251 | SET_DEST (old_set), new_src); | |
3252 | ||
3253 | if (!validate_change (insn, &PATTERN (insn), new_pat, 0)) | |
3254 | SET_SRC (old_set) = new_src; | |
3255 | } | |
8c1249f9 | 3256 | } |
ace3ffcd KH |
3257 | else |
3258 | break; | |
3259 | ||
aa5524a9 BS |
3260 | val = 1; |
3261 | /* This can't have an effect on elimination offsets, so skip right | |
3262 | to the end. */ | |
3263 | goto done; | |
3264 | } | |
32131a9c RK |
3265 | } |
3266 | ||
dfac187e BS |
3267 | /* Determine the effects of this insn on elimination offsets. */ |
3268 | elimination_effects (old_body, 0); | |
3269 | ||
3270 | /* Eliminate all eliminable registers occurring in operands that | |
3271 | can be handled by reload. */ | |
3272 | extract_insn (insn); | |
dfac187e BS |
3273 | for (i = 0; i < recog_data.n_operands; i++) |
3274 | { | |
3275 | orig_operand[i] = recog_data.operand[i]; | |
3276 | substed_operand[i] = recog_data.operand[i]; | |
3277 | ||
3278 | /* For an asm statement, every operand is eliminable. */ | |
3279 | if (insn_is_asm || insn_data[icode].operand[i].eliminable) | |
3280 | { | |
ab156144 RH |
3281 | bool is_set_src, in_plus; |
3282 | ||
dfac187e BS |
3283 | /* Check for setting a register that we know about. */ |
3284 | if (recog_data.operand_type[i] != OP_IN | |
f8cfc6aa | 3285 | && REG_P (orig_operand[i])) |
dfac187e BS |
3286 | { |
3287 | /* If we are assigning to a register that can be eliminated, it | |
3288 | must be as part of a PARALLEL, since the code above handles | |
3289 | single SETs. We must indicate that we can no longer | |
3290 | eliminate this reg. */ | |
3291 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
3292 | ep++) | |
761fa0f7 | 3293 | if (ep->from_rtx == orig_operand[i]) |
dfac187e BS |
3294 | ep->can_eliminate = 0; |
3295 | } | |
3296 | ||
ab156144 RH |
3297 | /* Companion to the above plus substitution, we can allow |
3298 | invariants as the source of a plain move. */ | |
3299 | is_set_src = false; | |
3300 | if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set)) | |
3301 | is_set_src = true; | |
3302 | in_plus = false; | |
3303 | if (plus_src | |
3304 | && (recog_data.operand_loc[i] == &XEXP (plus_src, 0) | |
3305 | || recog_data.operand_loc[i] == &XEXP (plus_src, 1))) | |
3306 | in_plus = true; | |
3307 | ||
3308 | substed_operand[i] | |
3309 | = eliminate_regs_1 (recog_data.operand[i], 0, | |
3310 | replace ? insn : NULL_RTX, | |
3311 | is_set_src || in_plus); | |
dfac187e | 3312 | if (substed_operand[i] != orig_operand[i]) |
4977bab6 | 3313 | val = 1; |
dfac187e BS |
3314 | /* Terminate the search in check_eliminable_occurrences at |
3315 | this point. */ | |
3316 | *recog_data.operand_loc[i] = 0; | |
3317 | ||
3318 | /* If an output operand changed from a REG to a MEM and INSN is an | |
3319 | insn, write a CLOBBER insn. */ | |
3320 | if (recog_data.operand_type[i] != OP_IN | |
f8cfc6aa | 3321 | && REG_P (orig_operand[i]) |
3c0cb5de | 3322 | && MEM_P (substed_operand[i]) |
dfac187e BS |
3323 | && replace) |
3324 | emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]), | |
3325 | insn); | |
3326 | } | |
3327 | } | |
3328 | ||
3329 | for (i = 0; i < recog_data.n_dups; i++) | |
3330 | *recog_data.dup_loc[i] | |
1d7254c5 | 3331 | = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; |
dfac187e BS |
3332 | |
3333 | /* If any eliminable remain, they aren't eliminable anymore. */ | |
3334 | check_eliminable_occurrences (old_body); | |
32131a9c | 3335 | |
dfac187e BS |
3336 | /* Substitute the operands; the new values are in the substed_operand |
3337 | array. */ | |
3338 | for (i = 0; i < recog_data.n_operands; i++) | |
3339 | *recog_data.operand_loc[i] = substed_operand[i]; | |
3340 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3341 | *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3342 | |
dfac187e | 3343 | /* If we are replacing a body that was a (set X (plus Y Z)), try to |
32131a9c RK |
3344 | re-recognize the insn. We do this in case we had a simple addition |
3345 | but now can do this as a load-address. This saves an insn in this | |
dfac187e BS |
3346 | common case. |
3347 | If re-recognition fails, the old insn code number will still be used, | |
3348 | and some register operands may have changed into PLUS expressions. | |
3349 | These will be handled by find_reloads by loading them into a register | |
1d7254c5 | 3350 | again. */ |
32131a9c | 3351 | |
dfac187e | 3352 | if (val) |
32131a9c | 3353 | { |
7c791b13 RK |
3354 | /* If we aren't replacing things permanently and we changed something, |
3355 | make another copy to ensure that all the RTL is new. Otherwise | |
3356 | things can go wrong if find_reload swaps commutative operands | |
0f41302f | 3357 | and one is inside RTL that has been copied while the other is not. */ |
dfac187e BS |
3358 | new_body = old_body; |
3359 | if (! replace) | |
1b3b5765 BS |
3360 | { |
3361 | new_body = copy_insn (old_body); | |
3362 | if (REG_NOTES (insn)) | |
3363 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3364 | } | |
dfac187e | 3365 | PATTERN (insn) = new_body; |
7c791b13 | 3366 | |
774672d2 RK |
3367 | /* If we had a move insn but now we don't, rerecognize it. This will |
3368 | cause spurious re-recognition if the old move had a PARALLEL since | |
3369 | the new one still will, but we can't call single_set without | |
3370 | having put NEW_BODY into the insn and the re-recognition won't | |
3371 | hurt in this rare case. */ | |
dfac187e BS |
3372 | /* ??? Why this huge if statement - why don't we just rerecognize the |
3373 | thing always? */ | |
3374 | if (! insn_is_asm | |
3375 | && old_set != 0 | |
f8cfc6aa | 3376 | && ((REG_P (SET_SRC (old_set)) |
774672d2 | 3377 | && (GET_CODE (new_body) != SET |
f8cfc6aa | 3378 | || !REG_P (SET_SRC (new_body)))) |
774672d2 | 3379 | /* If this was a load from or store to memory, compare |
1ccbefce RH |
3380 | the MEM in recog_data.operand to the one in the insn. |
3381 | If they are not equal, then rerecognize the insn. */ | |
774672d2 | 3382 | || (old_set != 0 |
3c0cb5de | 3383 | && ((MEM_P (SET_SRC (old_set)) |
1ccbefce | 3384 | && SET_SRC (old_set) != recog_data.operand[1]) |
3c0cb5de | 3385 | || (MEM_P (SET_DEST (old_set)) |
1ccbefce | 3386 | && SET_DEST (old_set) != recog_data.operand[0]))) |
774672d2 RK |
3387 | /* If this was an add insn before, rerecognize. */ |
3388 | || GET_CODE (SET_SRC (old_set)) == PLUS)) | |
4a5d0fb5 | 3389 | { |
dfac187e | 3390 | int new_icode = recog (PATTERN (insn), insn, 0); |
a5ee7cba AM |
3391 | if (new_icode >= 0) |
3392 | INSN_CODE (insn) = new_icode; | |
4a5d0fb5 | 3393 | } |
dfac187e | 3394 | } |
32131a9c | 3395 | |
dfac187e BS |
3396 | /* Restore the old body. If there were any changes to it, we made a copy |
3397 | of it while the changes were still in place, so we'll correctly return | |
3398 | a modified insn below. */ | |
3399 | if (! replace) | |
3400 | { | |
3401 | /* Restore the old body. */ | |
3402 | for (i = 0; i < recog_data.n_operands; i++) | |
3403 | *recog_data.operand_loc[i] = orig_operand[i]; | |
3404 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3405 | *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3406 | } |
a8fdc208 | 3407 | |
dfac187e BS |
3408 | /* Update all elimination pairs to reflect the status after the current |
3409 | insn. The changes we make were determined by the earlier call to | |
3410 | elimination_effects. | |
a8efe40d | 3411 | |
423adbb9 | 3412 | We also detect cases where register elimination cannot be done, |
32131a9c RK |
3413 | namely, if a register would be both changed and referenced outside a MEM |
3414 | in the resulting insn since such an insn is often undefined and, even if | |
3415 | not, we cannot know what meaning will be given to it. Note that it is | |
3416 | valid to have a register used in an address in an insn that changes it | |
3417 | (presumably with a pre- or post-increment or decrement). | |
3418 | ||
3419 | If anything changes, return nonzero. */ | |
3420 | ||
32131a9c RK |
3421 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3422 | { | |
3423 | if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | |
3424 | ep->can_eliminate = 0; | |
3425 | ||
3426 | ep->ref_outside_mem = 0; | |
3427 | ||
3428 | if (ep->previous_offset != ep->offset) | |
3429 | val = 1; | |
32131a9c RK |
3430 | } |
3431 | ||
3432 | done: | |
9faa82d8 | 3433 | /* If we changed something, perform elimination in REG_NOTES. This is |
05b4c365 RK |
3434 | needed even when REPLACE is zero because a REG_DEAD note might refer |
3435 | to a register that we eliminate and could cause a different number | |
3436 | of spill registers to be needed in the final reload pass than in | |
3437 | the pre-passes. */ | |
20748cab | 3438 | if (val && REG_NOTES (insn) != 0) |
ab156144 RH |
3439 | REG_NOTES (insn) |
3440 | = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true); | |
05b4c365 | 3441 | |
32131a9c RK |
3442 | return val; |
3443 | } | |
3444 | ||
cb2afeb3 R |
3445 | /* Loop through all elimination pairs. |
3446 | Recalculate the number not at initial offset. | |
3447 | ||
3448 | Compute the maximum offset (minimum offset if the stack does not | |
3449 | grow downward) for each elimination pair. */ | |
3450 | ||
3451 | static void | |
0c20a65f | 3452 | update_eliminable_offsets (void) |
cb2afeb3 R |
3453 | { |
3454 | struct elim_table *ep; | |
3455 | ||
3456 | num_not_at_initial_offset = 0; | |
3457 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3458 | { | |
3459 | ep->previous_offset = ep->offset; | |
3460 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3461 | num_not_at_initial_offset++; | |
cb2afeb3 R |
3462 | } |
3463 | } | |
3464 | ||
32131a9c RK |
3465 | /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register |
3466 | replacement we currently believe is valid, mark it as not eliminable if X | |
3467 | modifies DEST in any way other than by adding a constant integer to it. | |
3468 | ||
3469 | If DEST is the frame pointer, we do nothing because we assume that | |
3ec2ea3e DE |
3470 | all assignments to the hard frame pointer are nonlocal gotos and are being |
3471 | done at a time when they are valid and do not disturb anything else. | |
32131a9c | 3472 | Some machines want to eliminate a fake argument pointer with either the |
3ec2ea3e DE |
3473 | frame or stack pointer. Assignments to the hard frame pointer must not |
3474 | prevent this elimination. | |
32131a9c RK |
3475 | |
3476 | Called via note_stores from reload before starting its passes to scan | |
3477 | the insns of the function. */ | |
3478 | ||
3479 | static void | |
7bc980e1 | 3480 | mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) |
32131a9c | 3481 | { |
b3694847 | 3482 | unsigned int i; |
32131a9c RK |
3483 | |
3484 | /* A SUBREG of a hard register here is just changing its mode. We should | |
3485 | not see a SUBREG of an eliminable hard register, but check just in | |
3486 | case. */ | |
3487 | if (GET_CODE (dest) == SUBREG) | |
3488 | dest = SUBREG_REG (dest); | |
3489 | ||
3ec2ea3e | 3490 | if (dest == hard_frame_pointer_rtx) |
32131a9c RK |
3491 | return; |
3492 | ||
3493 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3494 | if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx | |
3495 | && (GET_CODE (x) != SET | |
3496 | || GET_CODE (SET_SRC (x)) != PLUS | |
3497 | || XEXP (SET_SRC (x), 0) != dest | |
3498 | || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) | |
3499 | { | |
3500 | reg_eliminate[i].can_eliminate_previous | |
3501 | = reg_eliminate[i].can_eliminate = 0; | |
3502 | num_eliminable--; | |
3503 | } | |
3504 | } | |
09dd1133 | 3505 | |
c47f5ea5 BS |
3506 | /* Verify that the initial elimination offsets did not change since the |
3507 | last call to set_initial_elim_offsets. This is used to catch cases | |
3508 | where something illegal happened during reload_as_needed that could | |
3509 | cause incorrect code to be generated if we did not check for it. */ | |
c8d8ed65 | 3510 | |
9f938de1 | 3511 | static bool |
0c20a65f | 3512 | verify_initial_elim_offsets (void) |
c47f5ea5 | 3513 | { |
b19ee4bd | 3514 | HOST_WIDE_INT t; |
c47f5ea5 | 3515 | |
9f938de1 UW |
3516 | if (!num_eliminable) |
3517 | return true; | |
3518 | ||
c47f5ea5 | 3519 | #ifdef ELIMINABLE_REGS |
67730e23 ILT |
3520 | { |
3521 | struct elim_table *ep; | |
3522 | ||
3523 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3524 | { | |
3525 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); | |
3526 | if (t != ep->initial_offset) | |
3527 | return false; | |
3528 | } | |
3529 | } | |
c47f5ea5 BS |
3530 | #else |
3531 | INITIAL_FRAME_POINTER_OFFSET (t); | |
9f938de1 UW |
3532 | if (t != reg_eliminate[0].initial_offset) |
3533 | return false; | |
05d10675 | 3534 | #endif |
9f938de1 UW |
3535 | |
3536 | return true; | |
c47f5ea5 BS |
3537 | } |
3538 | ||
09dd1133 | 3539 | /* Reset all offsets on eliminable registers to their initial values. */ |
1d813780 | 3540 | |
09dd1133 | 3541 | static void |
0c20a65f | 3542 | set_initial_elim_offsets (void) |
09dd1133 | 3543 | { |
1f3b1e1a | 3544 | struct elim_table *ep = reg_eliminate; |
09dd1133 BS |
3545 | |
3546 | #ifdef ELIMINABLE_REGS | |
1f3b1e1a | 3547 | for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
09dd1133 BS |
3548 | { |
3549 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); | |
1f3b1e1a | 3550 | ep->previous_offset = ep->offset = ep->initial_offset; |
09dd1133 BS |
3551 | } |
3552 | #else | |
1f3b1e1a JL |
3553 | INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); |
3554 | ep->previous_offset = ep->offset = ep->initial_offset; | |
09dd1133 BS |
3555 | #endif |
3556 | ||
3557 | num_not_at_initial_offset = 0; | |
1f3b1e1a | 3558 | } |
09dd1133 | 3559 | |
58767f00 RH |
3560 | /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */ |
3561 | ||
3562 | static void | |
3563 | set_initial_eh_label_offset (rtx label) | |
3564 | { | |
3565 | set_label_offsets (label, NULL_RTX, 1); | |
3566 | } | |
3567 | ||
1f3b1e1a JL |
3568 | /* Initialize the known label offsets. |
3569 | Set a known offset for each forced label to be at the initial offset | |
3570 | of each elimination. We do this because we assume that all | |
3571 | computed jumps occur from a location where each elimination is | |
3572 | at its initial offset. | |
3573 | For all other labels, show that we don't know the offsets. */ | |
09dd1133 | 3574 | |
1f3b1e1a | 3575 | static void |
0c20a65f | 3576 | set_initial_label_offsets (void) |
1f3b1e1a JL |
3577 | { |
3578 | rtx x; | |
4cc0fdd2 | 3579 | memset (offsets_known_at, 0, num_labels); |
09dd1133 BS |
3580 | |
3581 | for (x = forced_labels; x; x = XEXP (x, 1)) | |
3582 | if (XEXP (x, 0)) | |
3583 | set_label_offsets (XEXP (x, 0), NULL_RTX, 1); | |
58767f00 RH |
3584 | |
3585 | for_each_eh_label (set_initial_eh_label_offset); | |
09dd1133 BS |
3586 | } |
3587 | ||
1f3b1e1a JL |
3588 | /* Set all elimination offsets to the known values for the code label given |
3589 | by INSN. */ | |
1d813780 | 3590 | |
1f3b1e1a | 3591 | static void |
0c20a65f | 3592 | set_offsets_for_label (rtx insn) |
1f3b1e1a | 3593 | { |
973838fd | 3594 | unsigned int i; |
1f3b1e1a JL |
3595 | int label_nr = CODE_LABEL_NUMBER (insn); |
3596 | struct elim_table *ep; | |
3597 | ||
3598 | num_not_at_initial_offset = 0; | |
3599 | for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) | |
3600 | { | |
4cc0fdd2 JDA |
3601 | ep->offset = ep->previous_offset |
3602 | = offsets_at[label_nr - first_label_num][i]; | |
1f3b1e1a JL |
3603 | if (ep->can_eliminate && ep->offset != ep->initial_offset) |
3604 | num_not_at_initial_offset++; | |
3605 | } | |
3606 | } | |
3607 | ||
09dd1133 | 3608 | /* See if anything that happened changes which eliminations are valid. |
981f6289 | 3609 | For example, on the SPARC, whether or not the frame pointer can |
09dd1133 BS |
3610 | be eliminated can depend on what registers have been used. We need |
3611 | not check some conditions again (such as flag_omit_frame_pointer) | |
3612 | since they can't have changed. */ | |
3613 | ||
3614 | static void | |
0c20a65f | 3615 | update_eliminables (HARD_REG_SET *pset) |
09dd1133 | 3616 | { |
09dd1133 | 3617 | int previous_frame_pointer_needed = frame_pointer_needed; |
09dd1133 BS |
3618 | struct elim_table *ep; |
3619 | ||
3620 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3621 | if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) | |
3622 | #ifdef ELIMINABLE_REGS | |
3623 | || ! CAN_ELIMINATE (ep->from, ep->to) | |
3624 | #endif | |
3625 | ) | |
3626 | ep->can_eliminate = 0; | |
3627 | ||
3628 | /* Look for the case where we have discovered that we can't replace | |
3629 | register A with register B and that means that we will now be | |
3630 | trying to replace register A with register C. This means we can | |
3631 | no longer replace register C with register B and we need to disable | |
3632 | such an elimination, if it exists. This occurs often with A == ap, | |
3633 | B == sp, and C == fp. */ | |
3634 | ||
3635 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3636 | { | |
3637 | struct elim_table *op; | |
b3694847 | 3638 | int new_to = -1; |
09dd1133 BS |
3639 | |
3640 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3641 | { | |
3642 | /* Find the current elimination for ep->from, if there is a | |
3643 | new one. */ | |
3644 | for (op = reg_eliminate; | |
3645 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3646 | if (op->from == ep->from && op->can_eliminate) | |
3647 | { | |
3648 | new_to = op->to; | |
3649 | break; | |
3650 | } | |
3651 | ||
3652 | /* See if there is an elimination of NEW_TO -> EP->TO. If so, | |
3653 | disable it. */ | |
3654 | for (op = reg_eliminate; | |
3655 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3656 | if (op->from == new_to && op->to == ep->to) | |
3657 | op->can_eliminate = 0; | |
3658 | } | |
3659 | } | |
3660 | ||
3661 | /* See if any registers that we thought we could eliminate the previous | |
3662 | time are no longer eliminable. If so, something has changed and we | |
3663 | must spill the register. Also, recompute the number of eliminable | |
3664 | registers and see if the frame pointer is needed; it is if there is | |
3665 | no elimination of the frame pointer that we can perform. */ | |
3666 | ||
3667 | frame_pointer_needed = 1; | |
3668 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3669 | { | |
3670 | if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM | |
3671 | && ep->to != HARD_FRAME_POINTER_REGNUM) | |
3672 | frame_pointer_needed = 0; | |
3673 | ||
3674 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3675 | { | |
3676 | ep->can_eliminate_previous = 0; | |
3677 | SET_HARD_REG_BIT (*pset, ep->from); | |
3678 | num_eliminable--; | |
3679 | } | |
3680 | } | |
3681 | ||
09dd1133 BS |
3682 | /* If we didn't need a frame pointer last time, but we do now, spill |
3683 | the hard frame pointer. */ | |
3684 | if (frame_pointer_needed && ! previous_frame_pointer_needed) | |
3685 | SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); | |
09dd1133 BS |
3686 | } |
3687 | ||
8c74fb06 RS |
3688 | /* Return true if X is used as the target register of an elimination. */ |
3689 | ||
3690 | bool | |
3691 | elimination_target_reg_p (rtx x) | |
3692 | { | |
3693 | struct elim_table *ep; | |
3694 | ||
3695 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3696 | if (ep->to_rtx == x && ep->can_eliminate) | |
3697 | return true; | |
3698 | ||
3699 | return false; | |
3700 | } | |
3701 | ||
09dd1133 | 3702 | /* Initialize the table of registers to eliminate. */ |
1d813780 | 3703 | |
09dd1133 | 3704 | static void |
0c20a65f | 3705 | init_elim_table (void) |
09dd1133 BS |
3706 | { |
3707 | struct elim_table *ep; | |
590cf94d | 3708 | #ifdef ELIMINABLE_REGS |
0b5826ac | 3709 | const struct elim_table_1 *ep1; |
590cf94d | 3710 | #endif |
09dd1133 | 3711 | |
590cf94d | 3712 | if (!reg_eliminate) |
703ad42b | 3713 | reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS); |
05d10675 | 3714 | |
09dd1133 BS |
3715 | /* Does this function require a frame pointer? */ |
3716 | ||
3717 | frame_pointer_needed = (! flag_omit_frame_pointer | |
09dd1133 BS |
3718 | /* ?? If EXIT_IGNORE_STACK is set, we will not save |
3719 | and restore sp for alloca. So we can't eliminate | |
3720 | the frame pointer in that case. At some point, | |
3721 | we should improve this by emitting the | |
3722 | sp-adjusting insns for this case. */ | |
3723 | || (current_function_calls_alloca | |
3724 | && EXIT_IGNORE_STACK) | |
c8f27794 | 3725 | || current_function_accesses_prior_frames |
09dd1133 BS |
3726 | || FRAME_POINTER_REQUIRED); |
3727 | ||
3728 | num_eliminable = 0; | |
3729 | ||
3730 | #ifdef ELIMINABLE_REGS | |
590cf94d KG |
3731 | for (ep = reg_eliminate, ep1 = reg_eliminate_1; |
3732 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) | |
09dd1133 | 3733 | { |
590cf94d KG |
3734 | ep->from = ep1->from; |
3735 | ep->to = ep1->to; | |
09dd1133 BS |
3736 | ep->can_eliminate = ep->can_eliminate_previous |
3737 | = (CAN_ELIMINATE (ep->from, ep->to) | |
3738 | && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed)); | |
3739 | } | |
3740 | #else | |
590cf94d KG |
3741 | reg_eliminate[0].from = reg_eliminate_1[0].from; |
3742 | reg_eliminate[0].to = reg_eliminate_1[0].to; | |
09dd1133 BS |
3743 | reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous |
3744 | = ! frame_pointer_needed; | |
3745 | #endif | |
3746 | ||
3747 | /* Count the number of eliminable registers and build the FROM and TO | |
2fb00d7f | 3748 | REG rtx's. Note that code in gen_rtx_REG will cause, e.g., |
f84d109f | 3749 | gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. |
09dd1133 BS |
3750 | We depend on this. */ |
3751 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3752 | { | |
3753 | num_eliminable += ep->can_eliminate; | |
3754 | ep->from_rtx = gen_rtx_REG (Pmode, ep->from); | |
3755 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | |
3756 | } | |
3757 | } | |
32131a9c RK |
3758 | \f |
3759 | /* Kick all pseudos out of hard register REGNO. | |
32131a9c RK |
3760 | |
3761 | If CANT_ELIMINATE is nonzero, it means that we are doing this spill | |
3762 | because we found we can't eliminate some register. In the case, no pseudos | |
3763 | are allowed to be in the register, even if they are only in a block that | |
3764 | doesn't require spill registers, unlike the case when we are spilling this | |
3765 | hard reg to produce another spill register. | |
3766 | ||
3767 | Return nonzero if any pseudos needed to be kicked out. */ | |
3768 | ||
03acd8f8 | 3769 | static void |
0c20a65f | 3770 | spill_hard_reg (unsigned int regno, int cant_eliminate) |
32131a9c | 3771 | { |
b3694847 | 3772 | int i; |
32131a9c | 3773 | |
9ff3516a | 3774 | if (cant_eliminate) |
03acd8f8 BS |
3775 | { |
3776 | SET_HARD_REG_BIT (bad_spill_regs_global, regno); | |
6fb5fa3c | 3777 | df_set_regs_ever_live (regno, true); |
03acd8f8 | 3778 | } |
9ff3516a | 3779 | |
32131a9c RK |
3780 | /* Spill every pseudo reg that was allocated to this reg |
3781 | or to something that overlaps this reg. */ | |
3782 | ||
3783 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3784 | if (reg_renumber[i] >= 0 | |
770ae6cc | 3785 | && (unsigned int) reg_renumber[i] <= regno |
09e18274 | 3786 | && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno) |
f5d8c9f4 | 3787 | SET_REGNO_REG_SET (&spilled_pseudos, i); |
03acd8f8 | 3788 | } |
32131a9c | 3789 | |
03acd8f8 BS |
3790 | /* After find_reload_regs has been run for all insn that need reloads, |
3791 | and/or spill_hard_regs was called, this function is used to actually | |
3792 | spill pseudo registers and try to reallocate them. It also sets up the | |
3793 | spill_regs array for use by choose_reload_regs. */ | |
a8fdc208 | 3794 | |
03acd8f8 | 3795 | static int |
0c20a65f | 3796 | finish_spills (int global) |
03acd8f8 BS |
3797 | { |
3798 | struct insn_chain *chain; | |
3799 | int something_changed = 0; | |
3cd8c58a | 3800 | unsigned i; |
a2041967 | 3801 | reg_set_iterator rsi; |
03acd8f8 BS |
3802 | |
3803 | /* Build the spill_regs array for the function. */ | |
3804 | /* If there are some registers still to eliminate and one of the spill regs | |
3805 | wasn't ever used before, additional stack space may have to be | |
3806 | allocated to store this register. Thus, we may have changed the offset | |
3807 | between the stack and frame pointers, so mark that something has changed. | |
32131a9c | 3808 | |
03acd8f8 BS |
3809 | One might think that we need only set VAL to 1 if this is a call-used |
3810 | register. However, the set of registers that must be saved by the | |
3811 | prologue is not identical to the call-used set. For example, the | |
3812 | register used by the call insn for the return PC is a call-used register, | |
3813 | but must be saved by the prologue. */ | |
3814 | ||
3815 | n_spills = 0; | |
3816 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3817 | if (TEST_HARD_REG_BIT (used_spill_regs, i)) | |
3818 | { | |
3819 | spill_reg_order[i] = n_spills; | |
3820 | spill_regs[n_spills++] = i; | |
6fb5fa3c | 3821 | if (num_eliminable && ! df_regs_ever_live_p (i)) |
03acd8f8 | 3822 | something_changed = 1; |
6fb5fa3c | 3823 | df_set_regs_ever_live (i, true); |
03acd8f8 BS |
3824 | } |
3825 | else | |
3826 | spill_reg_order[i] = -1; | |
3827 | ||
a2041967 KH |
3828 | EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi) |
3829 | { | |
3830 | /* Record the current hard register the pseudo is allocated to in | |
3831 | pseudo_previous_regs so we avoid reallocating it to the same | |
3832 | hard reg in a later pass. */ | |
3833 | gcc_assert (reg_renumber[i] >= 0); | |
3834 | ||
3835 | SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); | |
3836 | /* Mark it as no longer having a hard register home. */ | |
3837 | reg_renumber[i] = -1; | |
3838 | /* We will need to scan everything again. */ | |
3839 | something_changed = 1; | |
3840 | } | |
7609e720 | 3841 | |
03acd8f8 BS |
3842 | /* Retry global register allocation if possible. */ |
3843 | if (global) | |
3844 | { | |
703ad42b | 3845 | memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET)); |
03acd8f8 BS |
3846 | /* For every insn that needs reloads, set the registers used as spill |
3847 | regs in pseudo_forbidden_regs for every pseudo live across the | |
3848 | insn. */ | |
3849 | for (chain = insns_need_reload; chain; chain = chain->next_need_reload) | |
3850 | { | |
3851 | EXECUTE_IF_SET_IN_REG_SET | |
a2041967 KH |
3852 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi) |
3853 | { | |
00268eb3 KH |
3854 | IOR_HARD_REG_SET (pseudo_forbidden_regs[i], |
3855 | chain->used_spill_regs); | |
a2041967 | 3856 | } |
03acd8f8 | 3857 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
3858 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi) |
3859 | { | |
00268eb3 KH |
3860 | IOR_HARD_REG_SET (pseudo_forbidden_regs[i], |
3861 | chain->used_spill_regs); | |
a2041967 | 3862 | } |
03acd8f8 | 3863 | } |
7609e720 | 3864 | |
03acd8f8 BS |
3865 | /* Retry allocating the spilled pseudos. For each reg, merge the |
3866 | various reg sets that indicate which hard regs can't be used, | |
3867 | and call retry_global_alloc. | |
05d10675 | 3868 | We change spill_pseudos here to only contain pseudos that did not |
03acd8f8 | 3869 | get a new hard register. */ |
3cd8c58a | 3870 | for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++) |
03acd8f8 | 3871 | if (reg_old_renumber[i] != reg_renumber[i]) |
32131a9c | 3872 | { |
03acd8f8 BS |
3873 | HARD_REG_SET forbidden; |
3874 | COPY_HARD_REG_SET (forbidden, bad_spill_regs_global); | |
3875 | IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]); | |
3876 | IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]); | |
3877 | retry_global_alloc (i, forbidden); | |
3878 | if (reg_renumber[i] >= 0) | |
f5d8c9f4 | 3879 | CLEAR_REGNO_REG_SET (&spilled_pseudos, i); |
32131a9c | 3880 | } |
03acd8f8 | 3881 | } |
7609e720 | 3882 | |
03acd8f8 BS |
3883 | /* Fix up the register information in the insn chain. |
3884 | This involves deleting those of the spilled pseudos which did not get | |
3885 | a new hard register home from the live_{before,after} sets. */ | |
7609e720 BS |
3886 | for (chain = reload_insn_chain; chain; chain = chain->next) |
3887 | { | |
03acd8f8 BS |
3888 | HARD_REG_SET used_by_pseudos; |
3889 | HARD_REG_SET used_by_pseudos2; | |
3890 | ||
239a0f5b BS |
3891 | AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); |
3892 | AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); | |
03acd8f8 BS |
3893 | |
3894 | /* Mark any unallocated hard regs as available for spills. That | |
3895 | makes inheritance work somewhat better. */ | |
3896 | if (chain->need_reload) | |
3897 | { | |
239a0f5b BS |
3898 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); |
3899 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
03acd8f8 BS |
3900 | IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); |
3901 | ||
3902 | /* Save the old value for the sanity test below. */ | |
3903 | COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs); | |
3904 | ||
239a0f5b BS |
3905 | compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); |
3906 | compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); | |
03acd8f8 BS |
3907 | COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); |
3908 | AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); | |
3909 | ||
3910 | /* Make sure we only enlarge the set. */ | |
56b138ae RS |
3911 | gcc_assert (hard_reg_set_subset_p (used_by_pseudos2, |
3912 | chain->used_spill_regs)); | |
03acd8f8 | 3913 | } |
7609e720 | 3914 | } |
03acd8f8 BS |
3915 | |
3916 | /* Let alter_reg modify the reg rtx's for the modified pseudos. */ | |
3cd8c58a | 3917 | for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++) |
03acd8f8 BS |
3918 | { |
3919 | int regno = reg_renumber[i]; | |
3920 | if (reg_old_renumber[i] == regno) | |
3921 | continue; | |
05d10675 | 3922 | |
03acd8f8 BS |
3923 | alter_reg (i, reg_old_renumber[i]); |
3924 | reg_old_renumber[i] = regno; | |
c263766c | 3925 | if (dump_file) |
03acd8f8 BS |
3926 | { |
3927 | if (regno == -1) | |
c263766c | 3928 | fprintf (dump_file, " Register %d now on stack.\n\n", i); |
03acd8f8 | 3929 | else |
c263766c | 3930 | fprintf (dump_file, " Register %d now in %d.\n\n", |
03acd8f8 BS |
3931 | i, reg_renumber[i]); |
3932 | } | |
3933 | } | |
3934 | ||
3935 | return something_changed; | |
7609e720 | 3936 | } |
32131a9c | 3937 | \f |
d754127f | 3938 | /* Find all paradoxical subregs within X and update reg_max_ref_width. */ |
32131a9c RK |
3939 | |
3940 | static void | |
0c20a65f | 3941 | scan_paradoxical_subregs (rtx x) |
32131a9c | 3942 | { |
b3694847 SS |
3943 | int i; |
3944 | const char *fmt; | |
3945 | enum rtx_code code = GET_CODE (x); | |
32131a9c RK |
3946 | |
3947 | switch (code) | |
3948 | { | |
56f58d3a | 3949 | case REG: |
32131a9c RK |
3950 | case CONST_INT: |
3951 | case CONST: | |
3952 | case SYMBOL_REF: | |
3953 | case LABEL_REF: | |
3954 | case CONST_DOUBLE: | |
69ef87e2 | 3955 | case CONST_VECTOR: /* shouldn't happen, but just in case. */ |
32131a9c RK |
3956 | case CC0: |
3957 | case PC: | |
32131a9c RK |
3958 | case USE: |
3959 | case CLOBBER: | |
3960 | return; | |
3961 | ||
3962 | case SUBREG: | |
f8cfc6aa | 3963 | if (REG_P (SUBREG_REG (x)) |
63a7a62b RS |
3964 | && (GET_MODE_SIZE (GET_MODE (x)) |
3965 | > reg_max_ref_width[REGNO (SUBREG_REG (x))])) | |
6fb5fa3c DB |
3966 | { |
3967 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
3968 | = GET_MODE_SIZE (GET_MODE (x)); | |
3969 | mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x)); | |
3970 | } | |
32131a9c | 3971 | return; |
05d10675 | 3972 | |
e9a25f70 JL |
3973 | default: |
3974 | break; | |
32131a9c RK |
3975 | } |
3976 | ||
3977 | fmt = GET_RTX_FORMAT (code); | |
3978 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3979 | { | |
3980 | if (fmt[i] == 'e') | |
3981 | scan_paradoxical_subregs (XEXP (x, i)); | |
3982 | else if (fmt[i] == 'E') | |
3983 | { | |
b3694847 | 3984 | int j; |
1d7254c5 | 3985 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
32131a9c RK |
3986 | scan_paradoxical_subregs (XVECEXP (x, i, j)); |
3987 | } | |
3988 | } | |
3989 | } | |
3990 | \f | |
be0c514c RH |
3991 | /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note, |
3992 | examine all of the reload insns between PREV and NEXT exclusive, and | |
3993 | annotate all that may trap. */ | |
3994 | ||
3995 | static void | |
3996 | fixup_eh_region_note (rtx insn, rtx prev, rtx next) | |
3997 | { | |
3998 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
3999 | unsigned int trap_count; | |
4000 | rtx i; | |
4001 | ||
4002 | if (note == NULL) | |
4003 | return; | |
4004 | ||
4005 | if (may_trap_p (PATTERN (insn))) | |
4006 | trap_count = 1; | |
4007 | else | |
4008 | { | |
4009 | remove_note (insn, note); | |
4010 | trap_count = 0; | |
4011 | } | |
4012 | ||
4013 | for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i)) | |
4014 | if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i))) | |
4015 | { | |
4016 | trap_count++; | |
4017 | REG_NOTES (i) | |
4018 | = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i)); | |
4019 | } | |
be0c514c RH |
4020 | } |
4021 | ||
32131a9c RK |
4022 | /* Reload pseudo-registers into hard regs around each insn as needed. |
4023 | Additional register load insns are output before the insn that needs it | |
4024 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
4025 | ||
4026 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
d08ea79f | 4027 | which registers are already available in reload registers. |
32131a9c RK |
4028 | We update these for the reloads that we perform, |
4029 | as the insns are scanned. */ | |
4030 | ||
4031 | static void | |
0c20a65f | 4032 | reload_as_needed (int live_known) |
32131a9c | 4033 | { |
7609e720 | 4034 | struct insn_chain *chain; |
553687c9 | 4035 | #if defined (AUTO_INC_DEC) |
b3694847 | 4036 | int i; |
973838fd | 4037 | #endif |
32131a9c | 4038 | rtx x; |
32131a9c | 4039 | |
703ad42b KG |
4040 | memset (spill_reg_rtx, 0, sizeof spill_reg_rtx); |
4041 | memset (spill_reg_store, 0, sizeof spill_reg_store); | |
5ed6ace5 | 4042 | reg_last_reload_reg = XCNEWVEC (rtx, max_regno); |
2c61f5f1 | 4043 | INIT_REG_SET (®_has_output_reload); |
e6e52be0 | 4044 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
e3e9336f | 4045 | CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered); |
32131a9c | 4046 | |
1f3b1e1a | 4047 | set_initial_elim_offsets (); |
32131a9c | 4048 | |
7609e720 | 4049 | for (chain = reload_insn_chain; chain; chain = chain->next) |
32131a9c | 4050 | { |
0334ef47 | 4051 | rtx prev = 0; |
7609e720 BS |
4052 | rtx insn = chain->insn; |
4053 | rtx old_next = NEXT_INSN (insn); | |
32131a9c RK |
4054 | |
4055 | /* If we pass a label, copy the offsets from the label information | |
4056 | into the current offsets of each elimination. */ | |
4b4bf941 | 4057 | if (LABEL_P (insn)) |
1f3b1e1a | 4058 | set_offsets_for_label (insn); |
32131a9c | 4059 | |
2c3c49de | 4060 | else if (INSN_P (insn)) |
32131a9c | 4061 | { |
db4c7386 JH |
4062 | regset_head regs_to_forget; |
4063 | INIT_REG_SET (®s_to_forget); | |
4064 | note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget); | |
7ffaaddc | 4065 | |
2758481d RS |
4066 | /* If this is a USE and CLOBBER of a MEM, ensure that any |
4067 | references to eliminable registers have been removed. */ | |
4068 | ||
4069 | if ((GET_CODE (PATTERN (insn)) == USE | |
4070 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
3c0cb5de | 4071 | && MEM_P (XEXP (PATTERN (insn), 0))) |
2758481d RS |
4072 | XEXP (XEXP (PATTERN (insn), 0), 0) |
4073 | = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), | |
29ae5012 | 4074 | GET_MODE (XEXP (PATTERN (insn), 0)), |
1914f5da | 4075 | NULL_RTX); |
2758481d | 4076 | |
32131a9c RK |
4077 | /* If we need to do register elimination processing, do so. |
4078 | This might delete the insn, in which case we are done. */ | |
2b49ee39 | 4079 | if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) |
32131a9c RK |
4080 | { |
4081 | eliminate_regs_in_insn (insn, 1); | |
4b4bf941 | 4082 | if (NOTE_P (insn)) |
cb2afeb3 R |
4083 | { |
4084 | update_eliminable_offsets (); | |
db4c7386 | 4085 | CLEAR_REG_SET (®s_to_forget); |
cb2afeb3 R |
4086 | continue; |
4087 | } | |
32131a9c RK |
4088 | } |
4089 | ||
7609e720 BS |
4090 | /* If need_elim is nonzero but need_reload is zero, one might think |
4091 | that we could simply set n_reloads to 0. However, find_reloads | |
4092 | could have done some manipulation of the insn (such as swapping | |
4093 | commutative operands), and these manipulations are lost during | |
4094 | the first pass for every insn that needs register elimination. | |
4095 | So the actions of find_reloads must be redone here. */ | |
4096 | ||
03acd8f8 BS |
4097 | if (! chain->need_elim && ! chain->need_reload |
4098 | && ! chain->need_operand_change) | |
32131a9c RK |
4099 | n_reloads = 0; |
4100 | /* First find the pseudo regs that must be reloaded for this insn. | |
4101 | This info is returned in the tables reload_... (see reload.h). | |
4102 | Also modify the body of INSN by substituting RELOAD | |
4103 | rtx's for those pseudo regs. */ | |
4104 | else | |
4105 | { | |
2c61f5f1 | 4106 | CLEAR_REG_SET (®_has_output_reload); |
32131a9c RK |
4107 | CLEAR_HARD_REG_SET (reg_is_output_reload); |
4108 | ||
4109 | find_reloads (insn, 1, spill_indirect_levels, live_known, | |
4110 | spill_reg_order); | |
4111 | } | |
4112 | ||
4113 | if (n_reloads > 0) | |
4114 | { | |
cb2afeb3 | 4115 | rtx next = NEXT_INSN (insn); |
3c3eeea6 | 4116 | rtx p; |
32131a9c | 4117 | |
cb2afeb3 R |
4118 | prev = PREV_INSN (insn); |
4119 | ||
32131a9c RK |
4120 | /* Now compute which reload regs to reload them into. Perhaps |
4121 | reusing reload regs from previous insns, or else output | |
4122 | load insns to reload them. Maybe output store insns too. | |
4123 | Record the choices of reload reg in reload_reg_rtx. */ | |
03acd8f8 | 4124 | choose_reload_regs (chain); |
32131a9c | 4125 | |
05d10675 | 4126 | /* Merge any reloads that we didn't combine for fear of |
546b63fb RK |
4127 | increasing the number of spill registers needed but now |
4128 | discover can be safely merged. */ | |
f95182a4 ILT |
4129 | if (SMALL_REGISTER_CLASSES) |
4130 | merge_assigned_reloads (insn); | |
546b63fb | 4131 | |
32131a9c RK |
4132 | /* Generate the insns to reload operands into or out of |
4133 | their reload regs. */ | |
e04ca094 | 4134 | emit_reload_insns (chain); |
32131a9c RK |
4135 | |
4136 | /* Substitute the chosen reload regs from reload_reg_rtx | |
4137 | into the insn's body (or perhaps into the bodies of other | |
4138 | load and store insn that we just made for reloading | |
4139 | and that we moved the structure into). */ | |
f759eb8b | 4140 | subst_reloads (insn); |
3c3eeea6 | 4141 | |
be0c514c | 4142 | /* Adjust the exception region notes for loads and stores. */ |
e3947b34 | 4143 | if (flag_non_call_exceptions && !CALL_P (insn)) |
be0c514c RH |
4144 | fixup_eh_region_note (insn, prev, next); |
4145 | ||
3c3eeea6 RK |
4146 | /* If this was an ASM, make sure that all the reload insns |
4147 | we have generated are valid. If not, give an error | |
4148 | and delete them. */ | |
3c3eeea6 RK |
4149 | if (asm_noperands (PATTERN (insn)) >= 0) |
4150 | for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) | |
2c3c49de | 4151 | if (p != insn && INSN_P (p) |
00dcfe80 | 4152 | && GET_CODE (PATTERN (p)) != USE |
3c3eeea6 | 4153 | && (recog_memoized (p) < 0 |
0eadeb15 | 4154 | || (extract_insn (p), ! constrain_operands (1)))) |
3c3eeea6 RK |
4155 | { |
4156 | error_for_asm (insn, | |
971801ff JM |
4157 | "%<asm%> operand requires " |
4158 | "impossible reload"); | |
ca6c03ca | 4159 | delete_insn (p); |
3c3eeea6 | 4160 | } |
32131a9c | 4161 | } |
5d7ef82a BS |
4162 | |
4163 | if (num_eliminable && chain->need_elim) | |
4164 | update_eliminable_offsets (); | |
4165 | ||
32131a9c RK |
4166 | /* Any previously reloaded spilled pseudo reg, stored in this insn, |
4167 | is no longer validly lying around to save a future reload. | |
4168 | Note that this does not detect pseudos that were reloaded | |
4169 | for this insn in order to be stored in | |
4170 | (obeying register constraints). That is correct; such reload | |
4171 | registers ARE still valid. */ | |
db4c7386 JH |
4172 | forget_marked_reloads (®s_to_forget); |
4173 | CLEAR_REG_SET (®s_to_forget); | |
32131a9c RK |
4174 | |
4175 | /* There may have been CLOBBER insns placed after INSN. So scan | |
4176 | between INSN and NEXT and use them to forget old reloads. */ | |
7609e720 | 4177 | for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) |
4b4bf941 | 4178 | if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER) |
84832317 | 4179 | note_stores (PATTERN (x), forget_old_reloads_1, NULL); |
32131a9c RK |
4180 | |
4181 | #ifdef AUTO_INC_DEC | |
cb2afeb3 R |
4182 | /* Likewise for regs altered by auto-increment in this insn. |
4183 | REG_INC notes have been changed by reloading: | |
4184 | find_reloads_address_1 records substitutions for them, | |
4185 | which have been performed by subst_reloads above. */ | |
4186 | for (i = n_reloads - 1; i >= 0; i--) | |
4187 | { | |
eceef4c9 | 4188 | rtx in_reg = rld[i].in_reg; |
cb2afeb3 R |
4189 | if (in_reg) |
4190 | { | |
4191 | enum rtx_code code = GET_CODE (in_reg); | |
4192 | /* PRE_INC / PRE_DEC will have the reload register ending up | |
4193 | with the same value as the stack slot, but that doesn't | |
4194 | hold true for POST_INC / POST_DEC. Either we have to | |
4195 | convert the memory access to a true POST_INC / POST_DEC, | |
4196 | or we can't use the reload register for inheritance. */ | |
4197 | if ((code == POST_INC || code == POST_DEC) | |
4198 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 4199 | REGNO (rld[i].reg_rtx)) |
04bbb0c5 JW |
4200 | /* Make sure it is the inc/dec pseudo, and not |
4201 | some other (e.g. output operand) pseudo. */ | |
fc555370 | 4202 | && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
04bbb0c5 | 4203 | == REGNO (XEXP (in_reg, 0)))) |
05d10675 | 4204 | |
cb2afeb3 | 4205 | { |
eceef4c9 | 4206 | rtx reload_reg = rld[i].reg_rtx; |
cb2afeb3 R |
4207 | enum machine_mode mode = GET_MODE (reload_reg); |
4208 | int n = 0; | |
4209 | rtx p; | |
4210 | ||
4211 | for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) | |
4212 | { | |
4213 | /* We really want to ignore REG_INC notes here, so | |
4214 | use PATTERN (p) as argument to reg_set_p . */ | |
4215 | if (reg_set_p (reload_reg, PATTERN (p))) | |
4216 | break; | |
4b983fdc | 4217 | n = count_occurrences (PATTERN (p), reload_reg, 0); |
cb2afeb3 R |
4218 | if (! n) |
4219 | continue; | |
4220 | if (n == 1) | |
f67c2384 JL |
4221 | { |
4222 | n = validate_replace_rtx (reload_reg, | |
2fb00d7f KH |
4223 | gen_rtx_fmt_e (code, |
4224 | mode, | |
4225 | reload_reg), | |
f67c2384 JL |
4226 | p); |
4227 | ||
4228 | /* We must also verify that the constraints | |
4229 | are met after the replacement. */ | |
4230 | extract_insn (p); | |
4231 | if (n) | |
4232 | n = constrain_operands (1); | |
4233 | else | |
4234 | break; | |
4235 | ||
4236 | /* If the constraints were not met, then | |
4237 | undo the replacement. */ | |
4238 | if (!n) | |
4239 | { | |
2fb00d7f KH |
4240 | validate_replace_rtx (gen_rtx_fmt_e (code, |
4241 | mode, | |
4242 | reload_reg), | |
f67c2384 JL |
4243 | reload_reg, p); |
4244 | break; | |
4245 | } | |
05d10675 | 4246 | |
f67c2384 | 4247 | } |
cb2afeb3 R |
4248 | break; |
4249 | } | |
4250 | if (n == 1) | |
02eb1393 R |
4251 | { |
4252 | REG_NOTES (p) | |
4253 | = gen_rtx_EXPR_LIST (REG_INC, reload_reg, | |
4254 | REG_NOTES (p)); | |
4255 | /* Mark this as having an output reload so that the | |
4256 | REG_INC processing code below won't invalidate | |
4257 | the reload for inheritance. */ | |
4258 | SET_HARD_REG_BIT (reg_is_output_reload, | |
4259 | REGNO (reload_reg)); | |
2c61f5f1 JH |
4260 | SET_REGNO_REG_SET (®_has_output_reload, |
4261 | REGNO (XEXP (in_reg, 0))); | |
02eb1393 | 4262 | } |
cb2afeb3 | 4263 | else |
1d7254c5 | 4264 | forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, |
84832317 | 4265 | NULL); |
cb2afeb3 | 4266 | } |
02eb1393 R |
4267 | else if ((code == PRE_INC || code == PRE_DEC) |
4268 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 4269 | REGNO (rld[i].reg_rtx)) |
02eb1393 R |
4270 | /* Make sure it is the inc/dec pseudo, and not |
4271 | some other (e.g. output operand) pseudo. */ | |
fc555370 | 4272 | && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
02eb1393 R |
4273 | == REGNO (XEXP (in_reg, 0)))) |
4274 | { | |
4275 | SET_HARD_REG_BIT (reg_is_output_reload, | |
eceef4c9 | 4276 | REGNO (rld[i].reg_rtx)); |
2c61f5f1 JH |
4277 | SET_REGNO_REG_SET (®_has_output_reload, |
4278 | REGNO (XEXP (in_reg, 0))); | |
02eb1393 | 4279 | } |
cb2afeb3 R |
4280 | } |
4281 | } | |
02eb1393 R |
4282 | /* If a pseudo that got a hard register is auto-incremented, |
4283 | we must purge records of copying it into pseudos without | |
4284 | hard registers. */ | |
32131a9c RK |
4285 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) |
4286 | if (REG_NOTE_KIND (x) == REG_INC) | |
4287 | { | |
4288 | /* See if this pseudo reg was reloaded in this insn. | |
4289 | If so, its last-reload info is still valid | |
4290 | because it is based on this insn's reload. */ | |
4291 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 4292 | if (rld[i].out == XEXP (x, 0)) |
32131a9c RK |
4293 | break; |
4294 | ||
08fb99fa | 4295 | if (i == n_reloads) |
84832317 | 4296 | forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); |
32131a9c RK |
4297 | } |
4298 | #endif | |
4299 | } | |
4300 | /* A reload reg's contents are unknown after a label. */ | |
4b4bf941 | 4301 | if (LABEL_P (insn)) |
e6e52be0 | 4302 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c RK |
4303 | |
4304 | /* Don't assume a reload reg is still good after a call insn | |
e3e9336f DJ |
4305 | if it is a call-used reg, or if it contains a value that will |
4306 | be partially clobbered by the call. */ | |
4b4bf941 | 4307 | else if (CALL_P (insn)) |
e3e9336f | 4308 | { |
8e2e89f7 | 4309 | AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set); |
e3e9336f DJ |
4310 | AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered); |
4311 | } | |
32131a9c | 4312 | } |
ff154f78 MM |
4313 | |
4314 | /* Clean up. */ | |
4315 | free (reg_last_reload_reg); | |
2c61f5f1 | 4316 | CLEAR_REG_SET (®_has_output_reload); |
32131a9c RK |
4317 | } |
4318 | ||
4319 | /* Discard all record of any value reloaded from X, | |
4320 | or reloaded in X from someplace else; | |
4321 | unless X is an output reload reg of the current insn. | |
4322 | ||
4323 | X may be a hard reg (the reload reg) | |
db4c7386 JH |
4324 | or it may be a pseudo reg that was reloaded from. |
4325 | ||
4326 | When DATA is non-NULL just mark the registers in regset | |
4327 | to be forgotten later. */ | |
32131a9c RK |
4328 | |
4329 | static void | |
7bc980e1 | 4330 | forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED, |
db4c7386 | 4331 | void *data) |
32131a9c | 4332 | { |
770ae6cc RK |
4333 | unsigned int regno; |
4334 | unsigned int nr; | |
db4c7386 | 4335 | regset regs = (regset) data; |
0a2e51a9 | 4336 | |
ddef6bc7 | 4337 | /* note_stores does give us subregs of hard regs, |
0e61db61 | 4338 | subreg_regno_offset requires a hard reg. */ |
0a2e51a9 RS |
4339 | while (GET_CODE (x) == SUBREG) |
4340 | { | |
fefac463 AH |
4341 | /* We ignore the subreg offset when calculating the regno, |
4342 | because we are using the entire underlying hard register | |
4343 | below. */ | |
0a2e51a9 RS |
4344 | x = SUBREG_REG (x); |
4345 | } | |
32131a9c | 4346 | |
f8cfc6aa | 4347 | if (!REG_P (x)) |
32131a9c RK |
4348 | return; |
4349 | ||
fefac463 | 4350 | regno = REGNO (x); |
32131a9c RK |
4351 | |
4352 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4353 | nr = 1; | |
4354 | else | |
4355 | { | |
770ae6cc RK |
4356 | unsigned int i; |
4357 | ||
66fd46b6 | 4358 | nr = hard_regno_nregs[regno][GET_MODE (x)]; |
32131a9c RK |
4359 | /* Storing into a spilled-reg invalidates its contents. |
4360 | This can happen if a block-local pseudo is allocated to that reg | |
4361 | and it wasn't spilled because this block's total need is 0. | |
4362 | Then some insn might have an optional reload and use this reg. */ | |
db4c7386 JH |
4363 | if (!regs) |
4364 | for (i = 0; i < nr; i++) | |
4365 | /* But don't do this if the reg actually serves as an output | |
4366 | reload reg in the current instruction. */ | |
4367 | if (n_reloads == 0 | |
4368 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) | |
4369 | { | |
4370 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); | |
4371 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i); | |
4372 | spill_reg_store[regno + i] = 0; | |
4373 | } | |
32131a9c RK |
4374 | } |
4375 | ||
db4c7386 JH |
4376 | if (regs) |
4377 | while (nr-- > 0) | |
4378 | SET_REGNO_REG_SET (regs, regno + nr); | |
4379 | else | |
4380 | { | |
4381 | /* Since value of X has changed, | |
4382 | forget any value previously copied from it. */ | |
4383 | ||
4384 | while (nr-- > 0) | |
4385 | /* But don't forget a copy if this is the output reload | |
4386 | that establishes the copy's validity. */ | |
2c61f5f1 JH |
4387 | if (n_reloads == 0 |
4388 | || !REGNO_REG_SET_P (®_has_output_reload, regno + nr)) | |
db4c7386 JH |
4389 | reg_last_reload_reg[regno + nr] = 0; |
4390 | } | |
4391 | } | |
32131a9c | 4392 | |
db4c7386 JH |
4393 | /* Forget the reloads marked in regset by previous function. */ |
4394 | static void | |
4395 | forget_marked_reloads (regset regs) | |
4396 | { | |
4397 | unsigned int reg; | |
4398 | reg_set_iterator rsi; | |
4399 | EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi) | |
4400 | { | |
4401 | if (reg < FIRST_PSEUDO_REGISTER | |
4402 | /* But don't do this if the reg actually serves as an output | |
4403 | reload reg in the current instruction. */ | |
4404 | && (n_reloads == 0 | |
4405 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg))) | |
4406 | { | |
4407 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg); | |
4408 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg); | |
4409 | spill_reg_store[reg] = 0; | |
4410 | } | |
2c61f5f1 JH |
4411 | if (n_reloads == 0 |
4412 | || !REGNO_REG_SET_P (®_has_output_reload, reg)) | |
db4c7386 JH |
4413 | reg_last_reload_reg[reg] = 0; |
4414 | } | |
32131a9c RK |
4415 | } |
4416 | \f | |
32131a9c RK |
4417 | /* The following HARD_REG_SETs indicate when each hard register is |
4418 | used for a reload of various parts of the current insn. */ | |
4419 | ||
9e3a9cf2 BS |
4420 | /* If reg is unavailable for all reloads. */ |
4421 | static HARD_REG_SET reload_reg_unavailable; | |
32131a9c RK |
4422 | /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ |
4423 | static HARD_REG_SET reload_reg_used; | |
546b63fb RK |
4424 | /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ |
4425 | static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4426 | /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ |
4427 | static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4428 | /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ |
4429 | static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4430 | /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ |
4431 | static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4432 | /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ |
4433 | static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; | |
4434 | /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ | |
4435 | static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
4436 | /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ |
4437 | static HARD_REG_SET reload_reg_used_in_op_addr; | |
893bc853 RK |
4438 | /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ |
4439 | static HARD_REG_SET reload_reg_used_in_op_addr_reload; | |
546b63fb RK |
4440 | /* If reg is in use for a RELOAD_FOR_INSN reload. */ |
4441 | static HARD_REG_SET reload_reg_used_in_insn; | |
4442 | /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ | |
4443 | static HARD_REG_SET reload_reg_used_in_other_addr; | |
32131a9c RK |
4444 | |
4445 | /* If reg is in use as a reload reg for any sort of reload. */ | |
4446 | static HARD_REG_SET reload_reg_used_at_all; | |
4447 | ||
be7ae2a4 RK |
4448 | /* If reg is use as an inherited reload. We just mark the first register |
4449 | in the group. */ | |
4450 | static HARD_REG_SET reload_reg_used_for_inherit; | |
4451 | ||
f1db3576 JL |
4452 | /* Records which hard regs are used in any way, either as explicit use or |
4453 | by being allocated to a pseudo during any point of the current insn. */ | |
4454 | static HARD_REG_SET reg_used_in_insn; | |
297927a8 | 4455 | |
546b63fb RK |
4456 | /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and |
4457 | TYPE. MODE is used to indicate how many consecutive regs are | |
4458 | actually used. */ | |
32131a9c RK |
4459 | |
4460 | static void | |
0c20a65f AJ |
4461 | mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type, |
4462 | enum machine_mode mode) | |
32131a9c | 4463 | { |
66fd46b6 | 4464 | unsigned int nregs = hard_regno_nregs[regno][mode]; |
770ae6cc | 4465 | unsigned int i; |
32131a9c RK |
4466 | |
4467 | for (i = regno; i < nregs + regno; i++) | |
4468 | { | |
546b63fb | 4469 | switch (type) |
32131a9c RK |
4470 | { |
4471 | case RELOAD_OTHER: | |
4472 | SET_HARD_REG_BIT (reload_reg_used, i); | |
4473 | break; | |
4474 | ||
546b63fb RK |
4475 | case RELOAD_FOR_INPUT_ADDRESS: |
4476 | SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); | |
32131a9c RK |
4477 | break; |
4478 | ||
47c8cf91 ILT |
4479 | case RELOAD_FOR_INPADDR_ADDRESS: |
4480 | SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); | |
4481 | break; | |
4482 | ||
546b63fb RK |
4483 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4484 | SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); | |
32131a9c RK |
4485 | break; |
4486 | ||
47c8cf91 ILT |
4487 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4488 | SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); | |
4489 | break; | |
4490 | ||
32131a9c RK |
4491 | case RELOAD_FOR_OPERAND_ADDRESS: |
4492 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
4493 | break; | |
4494 | ||
893bc853 RK |
4495 | case RELOAD_FOR_OPADDR_ADDR: |
4496 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); | |
4497 | break; | |
4498 | ||
546b63fb RK |
4499 | case RELOAD_FOR_OTHER_ADDRESS: |
4500 | SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); | |
4501 | break; | |
4502 | ||
32131a9c | 4503 | case RELOAD_FOR_INPUT: |
546b63fb | 4504 | SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); |
32131a9c RK |
4505 | break; |
4506 | ||
4507 | case RELOAD_FOR_OUTPUT: | |
546b63fb RK |
4508 | SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); |
4509 | break; | |
4510 | ||
4511 | case RELOAD_FOR_INSN: | |
4512 | SET_HARD_REG_BIT (reload_reg_used_in_insn, i); | |
32131a9c RK |
4513 | break; |
4514 | } | |
4515 | ||
4516 | SET_HARD_REG_BIT (reload_reg_used_at_all, i); | |
4517 | } | |
4518 | } | |
4519 | ||
be7ae2a4 RK |
4520 | /* Similarly, but show REGNO is no longer in use for a reload. */ |
4521 | ||
4522 | static void | |
0c20a65f AJ |
4523 | clear_reload_reg_in_use (unsigned int regno, int opnum, |
4524 | enum reload_type type, enum machine_mode mode) | |
be7ae2a4 | 4525 | { |
66fd46b6 | 4526 | unsigned int nregs = hard_regno_nregs[regno][mode]; |
770ae6cc | 4527 | unsigned int start_regno, end_regno, r; |
be7ae2a4 | 4528 | int i; |
cb2afeb3 R |
4529 | /* A complication is that for some reload types, inheritance might |
4530 | allow multiple reloads of the same types to share a reload register. | |
4531 | We set check_opnum if we have to check only reloads with the same | |
4532 | operand number, and check_any if we have to check all reloads. */ | |
4533 | int check_opnum = 0; | |
4534 | int check_any = 0; | |
4535 | HARD_REG_SET *used_in_set; | |
be7ae2a4 | 4536 | |
cb2afeb3 | 4537 | switch (type) |
be7ae2a4 | 4538 | { |
cb2afeb3 R |
4539 | case RELOAD_OTHER: |
4540 | used_in_set = &reload_reg_used; | |
4541 | break; | |
be7ae2a4 | 4542 | |
cb2afeb3 R |
4543 | case RELOAD_FOR_INPUT_ADDRESS: |
4544 | used_in_set = &reload_reg_used_in_input_addr[opnum]; | |
4545 | break; | |
be7ae2a4 | 4546 | |
cb2afeb3 R |
4547 | case RELOAD_FOR_INPADDR_ADDRESS: |
4548 | check_opnum = 1; | |
4549 | used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; | |
4550 | break; | |
47c8cf91 | 4551 | |
cb2afeb3 R |
4552 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4553 | used_in_set = &reload_reg_used_in_output_addr[opnum]; | |
4554 | break; | |
be7ae2a4 | 4555 | |
cb2afeb3 R |
4556 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4557 | check_opnum = 1; | |
4558 | used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; | |
4559 | break; | |
47c8cf91 | 4560 | |
cb2afeb3 R |
4561 | case RELOAD_FOR_OPERAND_ADDRESS: |
4562 | used_in_set = &reload_reg_used_in_op_addr; | |
4563 | break; | |
be7ae2a4 | 4564 | |
cb2afeb3 R |
4565 | case RELOAD_FOR_OPADDR_ADDR: |
4566 | check_any = 1; | |
4567 | used_in_set = &reload_reg_used_in_op_addr_reload; | |
4568 | break; | |
893bc853 | 4569 | |
cb2afeb3 R |
4570 | case RELOAD_FOR_OTHER_ADDRESS: |
4571 | used_in_set = &reload_reg_used_in_other_addr; | |
4572 | check_any = 1; | |
4573 | break; | |
be7ae2a4 | 4574 | |
cb2afeb3 R |
4575 | case RELOAD_FOR_INPUT: |
4576 | used_in_set = &reload_reg_used_in_input[opnum]; | |
4577 | break; | |
be7ae2a4 | 4578 | |
cb2afeb3 R |
4579 | case RELOAD_FOR_OUTPUT: |
4580 | used_in_set = &reload_reg_used_in_output[opnum]; | |
4581 | break; | |
be7ae2a4 | 4582 | |
cb2afeb3 R |
4583 | case RELOAD_FOR_INSN: |
4584 | used_in_set = &reload_reg_used_in_insn; | |
4585 | break; | |
4586 | default: | |
41374e13 | 4587 | gcc_unreachable (); |
cb2afeb3 R |
4588 | } |
4589 | /* We resolve conflicts with remaining reloads of the same type by | |
68e82b83 | 4590 | excluding the intervals of reload registers by them from the |
cb2afeb3 R |
4591 | interval of freed reload registers. Since we only keep track of |
4592 | one set of interval bounds, we might have to exclude somewhat | |
3e92902c | 4593 | more than what would be necessary if we used a HARD_REG_SET here. |
cb2afeb3 R |
4594 | But this should only happen very infrequently, so there should |
4595 | be no reason to worry about it. */ | |
05d10675 | 4596 | |
cb2afeb3 R |
4597 | start_regno = regno; |
4598 | end_regno = regno + nregs; | |
4599 | if (check_opnum || check_any) | |
4600 | { | |
4601 | for (i = n_reloads - 1; i >= 0; i--) | |
4602 | { | |
eceef4c9 BS |
4603 | if (rld[i].when_needed == type |
4604 | && (check_any || rld[i].opnum == opnum) | |
4605 | && rld[i].reg_rtx) | |
cb2afeb3 | 4606 | { |
770ae6cc RK |
4607 | unsigned int conflict_start = true_regnum (rld[i].reg_rtx); |
4608 | unsigned int conflict_end | |
09e18274 | 4609 | = end_hard_regno (rld[i].mode, conflict_start); |
cb2afeb3 R |
4610 | |
4611 | /* If there is an overlap with the first to-be-freed register, | |
4612 | adjust the interval start. */ | |
4613 | if (conflict_start <= start_regno && conflict_end > start_regno) | |
4614 | start_regno = conflict_end; | |
4615 | /* Otherwise, if there is a conflict with one of the other | |
4616 | to-be-freed registers, adjust the interval end. */ | |
4617 | if (conflict_start > start_regno && conflict_start < end_regno) | |
4618 | end_regno = conflict_start; | |
4619 | } | |
be7ae2a4 RK |
4620 | } |
4621 | } | |
770ae6cc RK |
4622 | |
4623 | for (r = start_regno; r < end_regno; r++) | |
4624 | CLEAR_HARD_REG_BIT (*used_in_set, r); | |
be7ae2a4 RK |
4625 | } |
4626 | ||
32131a9c | 4627 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort |
546b63fb | 4628 | specified by OPNUM and TYPE. */ |
32131a9c RK |
4629 | |
4630 | static int | |
0c20a65f | 4631 | reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type) |
32131a9c | 4632 | { |
546b63fb RK |
4633 | int i; |
4634 | ||
2edc8d65 | 4635 | /* In use for a RELOAD_OTHER means it's not available for anything. */ |
9e3a9cf2 BS |
4636 | if (TEST_HARD_REG_BIT (reload_reg_used, regno) |
4637 | || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) | |
32131a9c | 4638 | return 0; |
546b63fb RK |
4639 | |
4640 | switch (type) | |
32131a9c RK |
4641 | { |
4642 | case RELOAD_OTHER: | |
2edc8d65 RK |
4643 | /* In use for anything means we can't use it for RELOAD_OTHER. */ |
4644 | if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) | |
224f1d71 | 4645 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
808ededc | 4646 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) |
224f1d71 RK |
4647 | || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) |
4648 | return 0; | |
4649 | ||
4650 | for (i = 0; i < reload_n_operands; i++) | |
4651 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4652 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
224f1d71 | 4653 | || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
47c8cf91 | 4654 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
224f1d71 RK |
4655 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) |
4656 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4657 | return 0; | |
4658 | ||
4659 | return 1; | |
32131a9c | 4660 | |
32131a9c | 4661 | case RELOAD_FOR_INPUT: |
546b63fb RK |
4662 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4663 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
4664 | return 0; | |
4665 | ||
893bc853 RK |
4666 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4667 | return 0; | |
4668 | ||
546b63fb RK |
4669 | /* If it is used for some other input, can't use it. */ |
4670 | for (i = 0; i < reload_n_operands; i++) | |
4671 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4672 | return 0; | |
4673 | ||
4674 | /* If it is used in a later operand's address, can't use it. */ | |
4675 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4676 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4677 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4678 | return 0; |
4679 | ||
4680 | return 1; | |
4681 | ||
4682 | case RELOAD_FOR_INPUT_ADDRESS: | |
4683 | /* Can't use a register if it is used for an input address for this | |
4684 | operand or used as an input in an earlier one. */ | |
47c8cf91 ILT |
4685 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) |
4686 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) | |
4687 | return 0; | |
4688 | ||
4689 | for (i = 0; i < opnum; i++) | |
4690 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4691 | return 0; | |
4692 | ||
4693 | return 1; | |
4694 | ||
4695 | case RELOAD_FOR_INPADDR_ADDRESS: | |
4696 | /* Can't use a register if it is used for an input address | |
05d10675 BS |
4697 | for this operand or used as an input in an earlier |
4698 | one. */ | |
47c8cf91 | 4699 | if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) |
546b63fb RK |
4700 | return 0; |
4701 | ||
4702 | for (i = 0; i < opnum; i++) | |
4703 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4704 | return 0; | |
4705 | ||
4706 | return 1; | |
4707 | ||
4708 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
4709 | /* Can't use a register if it is used for an output address for this | |
d1d18b46 DJ |
4710 | operand or used as an output in this or a later operand. Note |
4711 | that multiple output operands are emitted in reverse order, so | |
4712 | the conflicting ones are those with lower indices. */ | |
546b63fb RK |
4713 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) |
4714 | return 0; | |
4715 | ||
d1d18b46 | 4716 | for (i = 0; i <= opnum; i++) |
546b63fb RK |
4717 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4718 | return 0; | |
4719 | ||
4720 | return 1; | |
4721 | ||
47c8cf91 ILT |
4722 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4723 | /* Can't use a register if it is used for an output address | |
05d10675 | 4724 | for this operand or used as an output in this or a |
d1d18b46 DJ |
4725 | later operand. Note that multiple output operands are |
4726 | emitted in reverse order, so the conflicting ones are | |
4727 | those with lower indices. */ | |
47c8cf91 ILT |
4728 | if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) |
4729 | return 0; | |
4730 | ||
d1d18b46 | 4731 | for (i = 0; i <= opnum; i++) |
47c8cf91 ILT |
4732 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4733 | return 0; | |
4734 | ||
4735 | return 1; | |
4736 | ||
32131a9c | 4737 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4738 | for (i = 0; i < reload_n_operands; i++) |
4739 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4740 | return 0; | |
4741 | ||
4742 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4743 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4744 | ||
893bc853 RK |
4745 | case RELOAD_FOR_OPADDR_ADDR: |
4746 | for (i = 0; i < reload_n_operands; i++) | |
05d10675 BS |
4747 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4748 | return 0; | |
893bc853 | 4749 | |
a94ce333 | 4750 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); |
893bc853 | 4751 | |
32131a9c | 4752 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4753 | /* This cannot share a register with RELOAD_FOR_INSN reloads, other |
d1d18b46 DJ |
4754 | outputs, or an operand address for this or an earlier output. |
4755 | Note that multiple output operands are emitted in reverse order, | |
4756 | so the conflicting ones are those with higher indices. */ | |
546b63fb RK |
4757 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) |
4758 | return 0; | |
4759 | ||
4760 | for (i = 0; i < reload_n_operands; i++) | |
4761 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4762 | return 0; | |
4763 | ||
d1d18b46 | 4764 | for (i = opnum; i < reload_n_operands; i++) |
47c8cf91 ILT |
4765 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4766 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4767 | return 0; |
4768 | ||
4769 | return 1; | |
4770 | ||
4771 | case RELOAD_FOR_INSN: | |
4772 | for (i = 0; i < reload_n_operands; i++) | |
4773 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) | |
4774 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4775 | return 0; | |
4776 | ||
4777 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4778 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4779 | ||
4780 | case RELOAD_FOR_OTHER_ADDRESS: | |
4781 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
41374e13 NS |
4782 | |
4783 | default: | |
4784 | gcc_unreachable (); | |
32131a9c | 4785 | } |
32131a9c RK |
4786 | } |
4787 | ||
32131a9c | 4788 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
546b63fb | 4789 | needed for the part of the insn specified by OPNUM and TYPE, |
32131a9c RK |
4790 | is still available in REGNO at the end of the insn. |
4791 | ||
4792 | We can assume that the reload reg was already tested for availability | |
4793 | at the time it is needed, and we should not check this again, | |
4794 | in case the reg has already been marked in use. */ | |
4795 | ||
4796 | static int | |
0c20a65f | 4797 | reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type) |
32131a9c | 4798 | { |
546b63fb RK |
4799 | int i; |
4800 | ||
4801 | switch (type) | |
32131a9c RK |
4802 | { |
4803 | case RELOAD_OTHER: | |
4804 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
4805 | its value must reach the end. */ | |
4806 | return 1; | |
4807 | ||
4808 | /* If this use is for part of the insn, | |
05d10675 | 4809 | its value reaches if no subsequent part uses the same register. |
546b63fb RK |
4810 | Just like the above function, don't try to do this with lots |
4811 | of fallthroughs. */ | |
4812 | ||
4813 | case RELOAD_FOR_OTHER_ADDRESS: | |
4814 | /* Here we check for everything else, since these don't conflict | |
4815 | with anything else and everything comes later. */ | |
4816 | ||
4817 | for (i = 0; i < reload_n_operands; i++) | |
4818 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4819 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4820 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) |
4821 | || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4822 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4823 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4824 | return 0; | |
4825 | ||
4826 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
808ededc | 4827 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) |
546b63fb RK |
4828 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4829 | && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
4830 | ||
4831 | case RELOAD_FOR_INPUT_ADDRESS: | |
47c8cf91 | 4832 | case RELOAD_FOR_INPADDR_ADDRESS: |
546b63fb RK |
4833 | /* Similar, except that we check only for this and subsequent inputs |
4834 | and the address of only subsequent inputs and we do not need | |
4835 | to check for RELOAD_OTHER objects since they are known not to | |
4836 | conflict. */ | |
4837 | ||
4838 | for (i = opnum; i < reload_n_operands; i++) | |
4839 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4840 | return 0; | |
4841 | ||
4842 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4843 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4844 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4845 | return 0; |
4846 | ||
4847 | for (i = 0; i < reload_n_operands; i++) | |
4848 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4849 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4850 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4851 | return 0; | |
4852 | ||
893bc853 RK |
4853 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4854 | return 0; | |
4855 | ||
2af88768 GK |
4856 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4857 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4858 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
546b63fb | 4859 | |
32131a9c | 4860 | case RELOAD_FOR_INPUT: |
546b63fb | 4861 | /* Similar to input address, except we start at the next operand for |
05d10675 | 4862 | both input and input address and we do not check for |
546b63fb RK |
4863 | RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these |
4864 | would conflict. */ | |
4865 | ||
4866 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4867 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4868 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4869 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4870 | return 0; | |
4871 | ||
0f41302f | 4872 | /* ... fall through ... */ |
546b63fb | 4873 | |
32131a9c | 4874 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4875 | /* Check outputs and their addresses. */ |
4876 | ||
4877 | for (i = 0; i < reload_n_operands; i++) | |
4878 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4879 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4880 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4881 | return 0; | |
4882 | ||
2af88768 | 4883 | return (!TEST_HARD_REG_BIT (reload_reg_used, regno)); |
546b63fb | 4884 | |
893bc853 RK |
4885 | case RELOAD_FOR_OPADDR_ADDR: |
4886 | for (i = 0; i < reload_n_operands; i++) | |
4887 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4888 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
893bc853 RK |
4889 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4890 | return 0; | |
4891 | ||
2af88768 GK |
4892 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4893 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4894 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
893bc853 | 4895 | |
546b63fb | 4896 | case RELOAD_FOR_INSN: |
893bc853 | 4897 | /* These conflict with other outputs with RELOAD_OTHER. So |
546b63fb RK |
4898 | we need only check for output addresses. */ |
4899 | ||
d1d18b46 | 4900 | opnum = reload_n_operands; |
546b63fb | 4901 | |
0f41302f | 4902 | /* ... fall through ... */ |
546b63fb | 4903 | |
32131a9c | 4904 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4905 | case RELOAD_FOR_OUTPUT_ADDRESS: |
47c8cf91 | 4906 | case RELOAD_FOR_OUTADDR_ADDRESS: |
546b63fb | 4907 | /* We already know these can't conflict with a later output. So the |
d1d18b46 DJ |
4908 | only thing to check are later output addresses. |
4909 | Note that multiple output operands are emitted in reverse order, | |
4910 | so the conflicting ones are those with lower indices. */ | |
4911 | for (i = 0; i < opnum; i++) | |
47c8cf91 ILT |
4912 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4913 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4914 | return 0; |
4915 | ||
32131a9c | 4916 | return 1; |
546b63fb | 4917 | |
41374e13 NS |
4918 | default: |
4919 | gcc_unreachable (); | |
4920 | } | |
32131a9c RK |
4921 | } |
4922 | \f | |
d2c9375a DD |
4923 | |
4924 | /* Returns whether R1 and R2 are uniquely chained: the value of one | |
4925 | is used by the other, and that value is not used by any other | |
4926 | reload for this insn. This is used to partially undo the decision | |
4927 | made in find_reloads when in the case of multiple | |
4928 | RELOAD_FOR_OPERAND_ADDRESS reloads it converts all | |
4929 | RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS | |
4930 | reloads. This code tries to avoid the conflict created by that | |
4931 | change. It might be cleaner to explicitly keep track of which | |
4932 | RELOAD_FOR_OPADDR_ADDR reload is associated with which | |
4933 | RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect | |
4934 | this after the fact. */ | |
4935 | static bool | |
4936 | reloads_unique_chain_p (int r1, int r2) | |
4937 | { | |
4938 | int i; | |
4939 | ||
4940 | /* We only check input reloads. */ | |
4941 | if (! rld[r1].in || ! rld[r2].in) | |
4942 | return false; | |
4943 | ||
4944 | /* Avoid anything with output reloads. */ | |
4945 | if (rld[r1].out || rld[r2].out) | |
4946 | return false; | |
4947 | ||
4948 | /* "chained" means one reload is a component of the other reload, | |
4949 | not the same as the other reload. */ | |
4950 | if (rld[r1].opnum != rld[r2].opnum | |
4951 | || rtx_equal_p (rld[r1].in, rld[r2].in) | |
4952 | || rld[r1].optional || rld[r2].optional | |
4953 | || ! (reg_mentioned_p (rld[r1].in, rld[r2].in) | |
4954 | || reg_mentioned_p (rld[r2].in, rld[r1].in))) | |
4955 | return false; | |
4956 | ||
4957 | for (i = 0; i < n_reloads; i ++) | |
4958 | /* Look for input reloads that aren't our two */ | |
4959 | if (i != r1 && i != r2 && rld[i].in) | |
4960 | { | |
4961 | /* If our reload is mentioned at all, it isn't a simple chain. */ | |
4962 | if (reg_mentioned_p (rld[r1].in, rld[i].in)) | |
4963 | return false; | |
4964 | } | |
4965 | return true; | |
4966 | } | |
4967 | ||
351aa1c1 RK |
4968 | /* Return 1 if the reloads denoted by R1 and R2 cannot share a register. |
4969 | Return 0 otherwise. | |
4970 | ||
4971 | This function uses the same algorithm as reload_reg_free_p above. */ | |
4972 | ||
bf9a0db3 | 4973 | static int |
0c20a65f | 4974 | reloads_conflict (int r1, int r2) |
351aa1c1 | 4975 | { |
eceef4c9 BS |
4976 | enum reload_type r1_type = rld[r1].when_needed; |
4977 | enum reload_type r2_type = rld[r2].when_needed; | |
4978 | int r1_opnum = rld[r1].opnum; | |
4979 | int r2_opnum = rld[r2].opnum; | |
351aa1c1 | 4980 | |
2edc8d65 RK |
4981 | /* RELOAD_OTHER conflicts with everything. */ |
4982 | if (r2_type == RELOAD_OTHER) | |
351aa1c1 RK |
4983 | return 1; |
4984 | ||
4985 | /* Otherwise, check conflicts differently for each type. */ | |
4986 | ||
4987 | switch (r1_type) | |
4988 | { | |
4989 | case RELOAD_FOR_INPUT: | |
05d10675 | 4990 | return (r2_type == RELOAD_FOR_INSN |
351aa1c1 | 4991 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS |
893bc853 | 4992 | || r2_type == RELOAD_FOR_OPADDR_ADDR |
351aa1c1 | 4993 | || r2_type == RELOAD_FOR_INPUT |
47c8cf91 ILT |
4994 | || ((r2_type == RELOAD_FOR_INPUT_ADDRESS |
4995 | || r2_type == RELOAD_FOR_INPADDR_ADDRESS) | |
4996 | && r2_opnum > r1_opnum)); | |
351aa1c1 RK |
4997 | |
4998 | case RELOAD_FOR_INPUT_ADDRESS: | |
4999 | return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) | |
5000 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
5001 | ||
47c8cf91 ILT |
5002 | case RELOAD_FOR_INPADDR_ADDRESS: |
5003 | return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) | |
5004 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
5005 | ||
351aa1c1 RK |
5006 | case RELOAD_FOR_OUTPUT_ADDRESS: |
5007 | return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 5008 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
351aa1c1 | 5009 | |
47c8cf91 ILT |
5010 | case RELOAD_FOR_OUTADDR_ADDRESS: |
5011 | return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 5012 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
47c8cf91 | 5013 | |
351aa1c1 RK |
5014 | case RELOAD_FOR_OPERAND_ADDRESS: |
5015 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN | |
d2c9375a DD |
5016 | || (r2_type == RELOAD_FOR_OPERAND_ADDRESS |
5017 | && !reloads_unique_chain_p (r1, r2))); | |
351aa1c1 | 5018 | |
893bc853 | 5019 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 | 5020 | return (r2_type == RELOAD_FOR_INPUT |
a94ce333 | 5021 | || r2_type == RELOAD_FOR_OPADDR_ADDR); |
893bc853 | 5022 | |
351aa1c1 RK |
5023 | case RELOAD_FOR_OUTPUT: |
5024 | return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT | |
47c8cf91 ILT |
5025 | || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS |
5026 | || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) | |
d1d18b46 | 5027 | && r2_opnum >= r1_opnum)); |
351aa1c1 RK |
5028 | |
5029 | case RELOAD_FOR_INSN: | |
5030 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT | |
5031 | || r2_type == RELOAD_FOR_INSN | |
5032 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); | |
5033 | ||
5034 | case RELOAD_FOR_OTHER_ADDRESS: | |
5035 | return r2_type == RELOAD_FOR_OTHER_ADDRESS; | |
5036 | ||
adab4fc5 | 5037 | case RELOAD_OTHER: |
2edc8d65 | 5038 | return 1; |
adab4fc5 | 5039 | |
351aa1c1 | 5040 | default: |
41374e13 | 5041 | gcc_unreachable (); |
351aa1c1 RK |
5042 | } |
5043 | } | |
5044 | \f | |
32131a9c RK |
5045 | /* Indexed by reload number, 1 if incoming value |
5046 | inherited from previous insns. */ | |
cf0fa607 | 5047 | static char reload_inherited[MAX_RELOADS]; |
32131a9c RK |
5048 | |
5049 | /* For an inherited reload, this is the insn the reload was inherited from, | |
5050 | if we know it. Otherwise, this is 0. */ | |
cf0fa607 | 5051 | static rtx reload_inheritance_insn[MAX_RELOADS]; |
32131a9c | 5052 | |
40f03658 | 5053 | /* If nonzero, this is a place to get the value of the reload, |
32131a9c | 5054 | rather than using reload_in. */ |
cf0fa607 | 5055 | static rtx reload_override_in[MAX_RELOADS]; |
32131a9c | 5056 | |
e6e52be0 R |
5057 | /* For each reload, the hard register number of the register used, |
5058 | or -1 if we did not need a register for this reload. */ | |
cf0fa607 | 5059 | static int reload_spill_index[MAX_RELOADS]; |
32131a9c | 5060 | |
304a22dd R |
5061 | /* Subroutine of free_for_value_p, used to check a single register. |
5062 | START_REGNO is the starting regno of the full reload register | |
5063 | (possibly comprising multiple hard registers) that we are considering. */ | |
f5470689 | 5064 | |
6e684430 | 5065 | static int |
0c20a65f AJ |
5066 | reload_reg_free_for_value_p (int start_regno, int regno, int opnum, |
5067 | enum reload_type type, rtx value, rtx out, | |
5068 | int reloadnum, int ignore_address_reloads) | |
6e684430 R |
5069 | { |
5070 | int time1; | |
09a308fe R |
5071 | /* Set if we see an input reload that must not share its reload register |
5072 | with any new earlyclobber, but might otherwise share the reload | |
5073 | register with an output or input-output reload. */ | |
5074 | int check_earlyclobber = 0; | |
6e684430 | 5075 | int i; |
dfe96118 R |
5076 | int copy = 0; |
5077 | ||
9e3a9cf2 | 5078 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) |
dc8842bf AH |
5079 | return 0; |
5080 | ||
dfe96118 R |
5081 | if (out == const0_rtx) |
5082 | { | |
5083 | copy = 1; | |
5084 | out = NULL_RTX; | |
5085 | } | |
6e684430 R |
5086 | |
5087 | /* We use some pseudo 'time' value to check if the lifetimes of the | |
5088 | new register use would overlap with the one of a previous reload | |
5089 | that is not read-only or uses a different value. | |
5090 | The 'time' used doesn't have to be linear in any shape or form, just | |
5091 | monotonic. | |
5092 | Some reload types use different 'buckets' for each operand. | |
5093 | So there are MAX_RECOG_OPERANDS different time values for each | |
cecbf6e2 R |
5094 | such reload type. |
5095 | We compute TIME1 as the time when the register for the prospective | |
5096 | new reload ceases to be live, and TIME2 for each existing | |
5097 | reload as the time when that the reload register of that reload | |
5098 | becomes live. | |
5099 | Where there is little to be gained by exact lifetime calculations, | |
5100 | we just make conservative assumptions, i.e. a longer lifetime; | |
5101 | this is done in the 'default:' cases. */ | |
6e684430 R |
5102 | switch (type) |
5103 | { | |
5104 | case RELOAD_FOR_OTHER_ADDRESS: | |
203588e7 | 5105 | /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ |
c2b4b171 | 5106 | time1 = copy ? 0 : 1; |
6e684430 | 5107 | break; |
dfe96118 R |
5108 | case RELOAD_OTHER: |
5109 | time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; | |
5110 | break; | |
05d10675 BS |
5111 | /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, |
5112 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , | |
5113 | respectively, to the time values for these, we get distinct time | |
5114 | values. To get distinct time values for each operand, we have to | |
5115 | multiply opnum by at least three. We round that up to four because | |
5116 | multiply by four is often cheaper. */ | |
6e684430 | 5117 | case RELOAD_FOR_INPADDR_ADDRESS: |
dfe96118 | 5118 | time1 = opnum * 4 + 2; |
6e684430 R |
5119 | break; |
5120 | case RELOAD_FOR_INPUT_ADDRESS: | |
dfe96118 R |
5121 | time1 = opnum * 4 + 3; |
5122 | break; | |
5123 | case RELOAD_FOR_INPUT: | |
5124 | /* All RELOAD_FOR_INPUT reloads remain live till the instruction | |
5125 | executes (inclusive). */ | |
5126 | time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; | |
6e684430 | 5127 | break; |
cb2afeb3 | 5128 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 BS |
5129 | /* opnum * 4 + 4 |
5130 | <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ | |
cb2afeb3 R |
5131 | time1 = MAX_RECOG_OPERANDS * 4 + 1; |
5132 | break; | |
5133 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5134 | /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn | |
5135 | is executed. */ | |
dfe96118 R |
5136 | time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; |
5137 | break; | |
5138 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
5139 | time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; | |
6e684430 | 5140 | break; |
6e684430 | 5141 | case RELOAD_FOR_OUTPUT_ADDRESS: |
dfe96118 | 5142 | time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; |
6e684430 R |
5143 | break; |
5144 | default: | |
dfe96118 | 5145 | time1 = MAX_RECOG_OPERANDS * 5 + 5; |
6e684430 R |
5146 | } |
5147 | ||
5148 | for (i = 0; i < n_reloads; i++) | |
5149 | { | |
eceef4c9 | 5150 | rtx reg = rld[i].reg_rtx; |
f8cfc6aa | 5151 | if (reg && REG_P (reg) |
6e684430 | 5152 | && ((unsigned) regno - true_regnum (reg) |
66fd46b6 | 5153 | <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1) |
f5470689 | 5154 | && i != reloadnum) |
6e684430 | 5155 | { |
304a22dd R |
5156 | rtx other_input = rld[i].in; |
5157 | ||
5158 | /* If the other reload loads the same input value, that | |
5159 | will not cause a conflict only if it's loading it into | |
5160 | the same register. */ | |
5161 | if (true_regnum (reg) != start_regno) | |
5162 | other_input = NULL_RTX; | |
5163 | if (! other_input || ! rtx_equal_p (other_input, value) | |
eceef4c9 | 5164 | || rld[i].out || out) |
6e684430 | 5165 | { |
09a308fe | 5166 | int time2; |
eceef4c9 | 5167 | switch (rld[i].when_needed) |
f5470689 R |
5168 | { |
5169 | case RELOAD_FOR_OTHER_ADDRESS: | |
5170 | time2 = 0; | |
5171 | break; | |
5172 | case RELOAD_FOR_INPADDR_ADDRESS: | |
cb2afeb3 R |
5173 | /* find_reloads makes sure that a |
5174 | RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used | |
5175 | by at most one - the first - | |
5176 | RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the | |
5177 | address reload is inherited, the address address reload | |
5178 | goes away, so we can ignore this conflict. */ | |
dfe96118 R |
5179 | if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 |
5180 | && ignore_address_reloads | |
5181 | /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. | |
5182 | Then the address address is still needed to store | |
5183 | back the new address. */ | |
eceef4c9 | 5184 | && ! rld[reloadnum].out) |
cb2afeb3 | 5185 | continue; |
dfe96118 R |
5186 | /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its |
5187 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS | |
5188 | reloads go away. */ | |
eceef4c9 | 5189 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 R |
5190 | && ignore_address_reloads |
5191 | /* Unless we are reloading an auto_inc expression. */ | |
eceef4c9 | 5192 | && ! rld[reloadnum].out) |
dfe96118 | 5193 | continue; |
eceef4c9 | 5194 | time2 = rld[i].opnum * 4 + 2; |
f5470689 R |
5195 | break; |
5196 | case RELOAD_FOR_INPUT_ADDRESS: | |
eceef4c9 | 5197 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 | 5198 | && ignore_address_reloads |
eceef4c9 | 5199 | && ! rld[reloadnum].out) |
dfe96118 | 5200 | continue; |
eceef4c9 | 5201 | time2 = rld[i].opnum * 4 + 3; |
f5470689 R |
5202 | break; |
5203 | case RELOAD_FOR_INPUT: | |
eceef4c9 | 5204 | time2 = rld[i].opnum * 4 + 4; |
09a308fe | 5205 | check_earlyclobber = 1; |
f5470689 | 5206 | break; |
eceef4c9 | 5207 | /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 |
05d10675 | 5208 | == MAX_RECOG_OPERAND * 4 */ |
cb2afeb3 | 5209 | case RELOAD_FOR_OPADDR_ADDR: |
dfe96118 R |
5210 | if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 |
5211 | && ignore_address_reloads | |
eceef4c9 | 5212 | && ! rld[reloadnum].out) |
cb2afeb3 | 5213 | continue; |
dfe96118 | 5214 | time2 = MAX_RECOG_OPERANDS * 4 + 1; |
cb2afeb3 R |
5215 | break; |
5216 | case RELOAD_FOR_OPERAND_ADDRESS: | |
dfe96118 | 5217 | time2 = MAX_RECOG_OPERANDS * 4 + 2; |
09a308fe | 5218 | check_earlyclobber = 1; |
dfe96118 R |
5219 | break; |
5220 | case RELOAD_FOR_INSN: | |
5221 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
cb2afeb3 | 5222 | break; |
f5470689 | 5223 | case RELOAD_FOR_OUTPUT: |
05d10675 BS |
5224 | /* All RELOAD_FOR_OUTPUT reloads become live just after the |
5225 | instruction is executed. */ | |
dfe96118 | 5226 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
f5470689 | 5227 | break; |
05d10675 BS |
5228 | /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with |
5229 | the RELOAD_FOR_OUTPUT reloads, so assign it the same time | |
5230 | value. */ | |
cb2afeb3 | 5231 | case RELOAD_FOR_OUTADDR_ADDRESS: |
dfe96118 R |
5232 | if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 |
5233 | && ignore_address_reloads | |
eceef4c9 | 5234 | && ! rld[reloadnum].out) |
cb2afeb3 | 5235 | continue; |
eceef4c9 | 5236 | time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; |
dfe96118 | 5237 | break; |
f5470689 | 5238 | case RELOAD_FOR_OUTPUT_ADDRESS: |
eceef4c9 | 5239 | time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; |
f5470689 R |
5240 | break; |
5241 | case RELOAD_OTHER: | |
dfe96118 R |
5242 | /* If there is no conflict in the input part, handle this |
5243 | like an output reload. */ | |
304a22dd | 5244 | if (! rld[i].in || rtx_equal_p (other_input, value)) |
f5470689 | 5245 | { |
dfe96118 | 5246 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
57850c85 | 5247 | /* Earlyclobbered outputs must conflict with inputs. */ |
09a308fe R |
5248 | if (earlyclobber_operand_p (rld[i].out)) |
5249 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
1d7254c5 | 5250 | |
f5470689 R |
5251 | break; |
5252 | } | |
dfe96118 R |
5253 | time2 = 1; |
5254 | /* RELOAD_OTHER might be live beyond instruction execution, | |
5255 | but this is not obvious when we set time2 = 1. So check | |
5256 | here if there might be a problem with the new reload | |
5257 | clobbering the register used by the RELOAD_OTHER. */ | |
5258 | if (out) | |
5259 | return 0; | |
5260 | break; | |
f5470689 | 5261 | default: |
dfe96118 | 5262 | return 0; |
f5470689 | 5263 | } |
25963977 | 5264 | if ((time1 >= time2 |
eceef4c9 | 5265 | && (! rld[i].in || rld[i].out |
304a22dd | 5266 | || ! rtx_equal_p (other_input, value))) |
eceef4c9 | 5267 | || (out && rld[reloadnum].out_reg |
701d55e8 | 5268 | && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) |
f5470689 | 5269 | return 0; |
6e684430 | 5270 | } |
6e684430 R |
5271 | } |
5272 | } | |
09a308fe R |
5273 | |
5274 | /* Earlyclobbered outputs must conflict with inputs. */ | |
5275 | if (check_earlyclobber && out && earlyclobber_operand_p (out)) | |
5276 | return 0; | |
5277 | ||
6e684430 R |
5278 | return 1; |
5279 | } | |
5280 | ||
c02cad8f BS |
5281 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
5282 | needed for the part of the insn specified by OPNUM and TYPE, | |
5283 | may be used to load VALUE into it. | |
5284 | ||
5285 | MODE is the mode in which the register is used, this is needed to | |
5286 | determine how many hard regs to test. | |
5287 | ||
5288 | Other read-only reloads with the same value do not conflict | |
40f03658 | 5289 | unless OUT is nonzero and these other reloads have to live while |
c02cad8f BS |
5290 | output reloads live. |
5291 | If OUT is CONST0_RTX, this is a special case: it means that the | |
5292 | test should not be for using register REGNO as reload register, but | |
5293 | for copying from register REGNO into the reload register. | |
5294 | ||
5295 | RELOADNUM is the number of the reload we want to load this value for; | |
5296 | a reload does not conflict with itself. | |
5297 | ||
5298 | When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with | |
5299 | reloads that load an address for the very reload we are considering. | |
5300 | ||
5301 | The caller has to make sure that there is no conflict with the return | |
5302 | register. */ | |
5303 | ||
5304 | static int | |
0c20a65f AJ |
5305 | free_for_value_p (int regno, enum machine_mode mode, int opnum, |
5306 | enum reload_type type, rtx value, rtx out, int reloadnum, | |
5307 | int ignore_address_reloads) | |
c02cad8f | 5308 | { |
66fd46b6 | 5309 | int nregs = hard_regno_nregs[regno][mode]; |
c02cad8f | 5310 | while (nregs-- > 0) |
304a22dd R |
5311 | if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type, |
5312 | value, out, reloadnum, | |
5313 | ignore_address_reloads)) | |
c02cad8f BS |
5314 | return 0; |
5315 | return 1; | |
5316 | } | |
5317 | ||
86caf04d | 5318 | /* Return nonzero if the rtx X is invariant over the current function. */ |
0e61db61 NS |
5319 | /* ??? Actually, the places where we use this expect exactly what is |
5320 | tested here, and not everything that is function invariant. In | |
5321 | particular, the frame pointer and arg pointer are special cased; | |
5322 | pic_offset_table_rtx is not, and we must not spill these things to | |
5323 | memory. */ | |
86caf04d | 5324 | |
5fffc382 | 5325 | int |
4f588890 | 5326 | function_invariant_p (const_rtx x) |
86caf04d PB |
5327 | { |
5328 | if (CONSTANT_P (x)) | |
5329 | return 1; | |
5330 | if (x == frame_pointer_rtx || x == arg_pointer_rtx) | |
5331 | return 1; | |
5332 | if (GET_CODE (x) == PLUS | |
5333 | && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx) | |
5334 | && CONSTANT_P (XEXP (x, 1))) | |
5335 | return 1; | |
5336 | return 0; | |
5337 | } | |
5338 | ||
ff6534ad BS |
5339 | /* Determine whether the reload reg X overlaps any rtx'es used for |
5340 | overriding inheritance. Return nonzero if so. */ | |
5341 | ||
5342 | static int | |
0c20a65f | 5343 | conflicts_with_override (rtx x) |
ff6534ad BS |
5344 | { |
5345 | int i; | |
5346 | for (i = 0; i < n_reloads; i++) | |
5347 | if (reload_override_in[i] | |
5348 | && reg_overlap_mentioned_p (x, reload_override_in[i])) | |
5349 | return 1; | |
5350 | return 0; | |
5351 | } | |
5352 | \f | |
67e61fe7 BS |
5353 | /* Give an error message saying we failed to find a reload for INSN, |
5354 | and clear out reload R. */ | |
5355 | static void | |
0c20a65f | 5356 | failed_reload (rtx insn, int r) |
67e61fe7 BS |
5357 | { |
5358 | if (asm_noperands (PATTERN (insn)) < 0) | |
5359 | /* It's the compiler's fault. */ | |
1f978f5f | 5360 | fatal_insn ("could not find a spill register", insn); |
67e61fe7 BS |
5361 | |
5362 | /* It's the user's fault; the operand's mode and constraint | |
5363 | don't match. Disable this reload so we don't crash in final. */ | |
5364 | error_for_asm (insn, | |
971801ff | 5365 | "%<asm%> operand constraint incompatible with operand size"); |
67e61fe7 BS |
5366 | rld[r].in = 0; |
5367 | rld[r].out = 0; | |
5368 | rld[r].reg_rtx = 0; | |
5369 | rld[r].optional = 1; | |
5370 | rld[r].secondary_p = 1; | |
5371 | } | |
5372 | ||
5373 | /* I is the index in SPILL_REG_RTX of the reload register we are to allocate | |
5374 | for reload R. If it's valid, get an rtx for it. Return nonzero if | |
5375 | successful. */ | |
5376 | static int | |
0c20a65f | 5377 | set_reload_reg (int i, int r) |
67e61fe7 BS |
5378 | { |
5379 | int regno; | |
5380 | rtx reg = spill_reg_rtx[i]; | |
5381 | ||
5382 | if (reg == 0 || GET_MODE (reg) != rld[r].mode) | |
5383 | spill_reg_rtx[i] = reg | |
5384 | = gen_rtx_REG (rld[r].mode, spill_regs[i]); | |
5385 | ||
5386 | regno = true_regnum (reg); | |
5387 | ||
5388 | /* Detect when the reload reg can't hold the reload mode. | |
5389 | This used to be one `if', but Sequent compiler can't handle that. */ | |
5390 | if (HARD_REGNO_MODE_OK (regno, rld[r].mode)) | |
5391 | { | |
5392 | enum machine_mode test_mode = VOIDmode; | |
5393 | if (rld[r].in) | |
5394 | test_mode = GET_MODE (rld[r].in); | |
5395 | /* If rld[r].in has VOIDmode, it means we will load it | |
5396 | in whatever mode the reload reg has: to wit, rld[r].mode. | |
5397 | We have already tested that for validity. */ | |
5398 | /* Aside from that, we need to test that the expressions | |
5399 | to reload from or into have modes which are valid for this | |
5400 | reload register. Otherwise the reload insns would be invalid. */ | |
5401 | if (! (rld[r].in != 0 && test_mode != VOIDmode | |
5402 | && ! HARD_REGNO_MODE_OK (regno, test_mode))) | |
5403 | if (! (rld[r].out != 0 | |
5404 | && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out)))) | |
5405 | { | |
5406 | /* The reg is OK. */ | |
5407 | last_spill_reg = i; | |
5408 | ||
5409 | /* Mark as in use for this insn the reload regs we use | |
5410 | for this. */ | |
5411 | mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, | |
5412 | rld[r].when_needed, rld[r].mode); | |
5413 | ||
5414 | rld[r].reg_rtx = reg; | |
5415 | reload_spill_index[r] = spill_regs[i]; | |
5416 | return 1; | |
5417 | } | |
5418 | } | |
5419 | return 0; | |
5420 | } | |
5421 | ||
32131a9c | 5422 | /* Find a spill register to use as a reload register for reload R. |
40f03658 | 5423 | LAST_RELOAD is nonzero if this is the last reload for the insn being |
32131a9c RK |
5424 | processed. |
5425 | ||
eceef4c9 | 5426 | Set rld[R].reg_rtx to the register allocated. |
32131a9c | 5427 | |
f5d8c9f4 BS |
5428 | We return 1 if successful, or 0 if we couldn't find a spill reg and |
5429 | we didn't change anything. */ | |
32131a9c RK |
5430 | |
5431 | static int | |
0c20a65f AJ |
5432 | allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r, |
5433 | int last_reload) | |
32131a9c | 5434 | { |
67e61fe7 | 5435 | int i, pass, count; |
32131a9c RK |
5436 | |
5437 | /* If we put this reload ahead, thinking it is a group, | |
5438 | then insist on finding a group. Otherwise we can grab a | |
a8fdc208 | 5439 | reg that some other reload needs. |
32131a9c RK |
5440 | (That can happen when we have a 68000 DATA_OR_FP_REG |
5441 | which is a group of data regs or one fp reg.) | |
5442 | We need not be so restrictive if there are no more reloads | |
5443 | for this insn. | |
5444 | ||
5445 | ??? Really it would be nicer to have smarter handling | |
5446 | for that kind of reg class, where a problem like this is normal. | |
5447 | Perhaps those classes should be avoided for reloading | |
5448 | by use of more alternatives. */ | |
5449 | ||
8ec450a4 | 5450 | int force_group = rld[r].nregs > 1 && ! last_reload; |
32131a9c RK |
5451 | |
5452 | /* If we want a single register and haven't yet found one, | |
5453 | take any reg in the right class and not in use. | |
5454 | If we want a consecutive group, here is where we look for it. | |
5455 | ||
5456 | We use two passes so we can first look for reload regs to | |
5457 | reuse, which are already in use for other reloads in this insn, | |
5458 | and only then use additional registers. | |
5459 | I think that maximizing reuse is needed to make sure we don't | |
5460 | run out of reload regs. Suppose we have three reloads, and | |
5461 | reloads A and B can share regs. These need two regs. | |
5462 | Suppose A and B are given different regs. | |
5463 | That leaves none for C. */ | |
5464 | for (pass = 0; pass < 2; pass++) | |
5465 | { | |
5466 | /* I is the index in spill_regs. | |
5467 | We advance it round-robin between insns to use all spill regs | |
5468 | equally, so that inherited reloads have a chance | |
f5d8c9f4 BS |
5469 | of leapfrogging each other. */ |
5470 | ||
5471 | i = last_spill_reg; | |
05d10675 | 5472 | |
a5339699 | 5473 | for (count = 0; count < n_spills; count++) |
32131a9c | 5474 | { |
eceef4c9 | 5475 | int class = (int) rld[r].class; |
03acd8f8 | 5476 | int regnum; |
32131a9c | 5477 | |
03acd8f8 BS |
5478 | i++; |
5479 | if (i >= n_spills) | |
5480 | i -= n_spills; | |
5481 | regnum = spill_regs[i]; | |
32131a9c | 5482 | |
eceef4c9 BS |
5483 | if ((reload_reg_free_p (regnum, rld[r].opnum, |
5484 | rld[r].when_needed) | |
5485 | || (rld[r].in | |
05d10675 BS |
5486 | /* We check reload_reg_used to make sure we |
5487 | don't clobber the return register. */ | |
03acd8f8 | 5488 | && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) |
c02cad8f BS |
5489 | && free_for_value_p (regnum, rld[r].mode, rld[r].opnum, |
5490 | rld[r].when_needed, rld[r].in, | |
5491 | rld[r].out, r, 1))) | |
03acd8f8 | 5492 | && TEST_HARD_REG_BIT (reg_class_contents[class], regnum) |
8ec450a4 | 5493 | && HARD_REGNO_MODE_OK (regnum, rld[r].mode) |
be7ae2a4 RK |
5494 | /* Look first for regs to share, then for unshared. But |
5495 | don't share regs used for inherited reloads; they are | |
5496 | the ones we want to preserve. */ | |
5497 | && (pass | |
5498 | || (TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
03acd8f8 | 5499 | regnum) |
be7ae2a4 | 5500 | && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, |
03acd8f8 | 5501 | regnum)))) |
32131a9c | 5502 | { |
66fd46b6 | 5503 | int nr = hard_regno_nregs[regnum][rld[r].mode]; |
32131a9c RK |
5504 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG |
5505 | (on 68000) got us two FP regs. If NR is 1, | |
5506 | we would reject both of them. */ | |
5507 | if (force_group) | |
67e61fe7 | 5508 | nr = rld[r].nregs; |
32131a9c RK |
5509 | /* If we need only one reg, we have already won. */ |
5510 | if (nr == 1) | |
5511 | { | |
5512 | /* But reject a single reg if we demand a group. */ | |
5513 | if (force_group) | |
5514 | continue; | |
5515 | break; | |
5516 | } | |
5517 | /* Otherwise check that as many consecutive regs as we need | |
f5d8c9f4 BS |
5518 | are available here. */ |
5519 | while (nr > 1) | |
5520 | { | |
5521 | int regno = regnum + nr - 1; | |
5522 | if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
5523 | && spill_reg_order[regno] >= 0 | |
5524 | && reload_reg_free_p (regno, rld[r].opnum, | |
5525 | rld[r].when_needed))) | |
5526 | break; | |
5527 | nr--; | |
5528 | } | |
32131a9c RK |
5529 | if (nr == 1) |
5530 | break; | |
5531 | } | |
5532 | } | |
5533 | ||
5534 | /* If we found something on pass 1, omit pass 2. */ | |
5535 | if (count < n_spills) | |
5536 | break; | |
5537 | } | |
1d7254c5 | 5538 | |
32131a9c | 5539 | /* We should have found a spill register by now. */ |
f5d8c9f4 | 5540 | if (count >= n_spills) |
32131a9c RK |
5541 | return 0; |
5542 | ||
f5d8c9f4 BS |
5543 | /* I is the index in SPILL_REG_RTX of the reload register we are to |
5544 | allocate. Get an rtx for it and find its register number. */ | |
32131a9c | 5545 | |
f5d8c9f4 | 5546 | return set_reload_reg (i, r); |
32131a9c RK |
5547 | } |
5548 | \f | |
67e61fe7 BS |
5549 | /* Initialize all the tables needed to allocate reload registers. |
5550 | CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX | |
5551 | is the array we use to restore the reg_rtx field for every reload. */ | |
efc9bd41 | 5552 | |
32131a9c | 5553 | static void |
0c20a65f | 5554 | choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx) |
32131a9c | 5555 | { |
67e61fe7 | 5556 | int i; |
32131a9c | 5557 | |
67e61fe7 BS |
5558 | for (i = 0; i < n_reloads; i++) |
5559 | rld[i].reg_rtx = save_reload_reg_rtx[i]; | |
32131a9c | 5560 | |
961192e1 | 5561 | memset (reload_inherited, 0, MAX_RELOADS); |
703ad42b KG |
5562 | memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx)); |
5563 | memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx)); | |
32131a9c RK |
5564 | |
5565 | CLEAR_HARD_REG_SET (reload_reg_used); | |
5566 | CLEAR_HARD_REG_SET (reload_reg_used_at_all); | |
32131a9c | 5567 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); |
893bc853 | 5568 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); |
546b63fb RK |
5569 | CLEAR_HARD_REG_SET (reload_reg_used_in_insn); |
5570 | CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); | |
32131a9c | 5571 | |
f1db3576 JL |
5572 | CLEAR_HARD_REG_SET (reg_used_in_insn); |
5573 | { | |
5574 | HARD_REG_SET tmp; | |
239a0f5b | 5575 | REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); |
f1db3576 | 5576 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b | 5577 | REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); |
f1db3576 | 5578 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b BS |
5579 | compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); |
5580 | compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); | |
f1db3576 | 5581 | } |
efc9bd41 | 5582 | |
546b63fb RK |
5583 | for (i = 0; i < reload_n_operands; i++) |
5584 | { | |
5585 | CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); | |
5586 | CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); | |
5587 | CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); | |
47c8cf91 | 5588 | CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); |
546b63fb | 5589 | CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); |
47c8cf91 | 5590 | CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); |
546b63fb | 5591 | } |
32131a9c | 5592 | |
9e3a9cf2 | 5593 | COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs); |
05d10675 | 5594 | |
67e61fe7 | 5595 | CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); |
32131a9c | 5596 | |
67e61fe7 BS |
5597 | for (i = 0; i < n_reloads; i++) |
5598 | /* If we have already decided to use a certain register, | |
5599 | don't use it in another way. */ | |
5600 | if (rld[i].reg_rtx) | |
5601 | mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, | |
5602 | rld[i].when_needed, rld[i].mode); | |
5603 | } | |
32131a9c | 5604 | |
67e61fe7 BS |
5605 | /* Assign hard reg targets for the pseudo-registers we must reload |
5606 | into hard regs for this insn. | |
5607 | Also output the instructions to copy them in and out of the hard regs. | |
5608 | ||
5609 | For machines with register classes, we are responsible for | |
5610 | finding a reload reg in the proper class. */ | |
5611 | ||
5612 | static void | |
0c20a65f | 5613 | choose_reload_regs (struct insn_chain *chain) |
67e61fe7 BS |
5614 | { |
5615 | rtx insn = chain->insn; | |
b3694847 | 5616 | int i, j; |
770ae6cc | 5617 | unsigned int max_group_size = 1; |
67e61fe7 | 5618 | enum reg_class group_class = NO_REGS; |
f5d8c9f4 | 5619 | int pass, win, inheritance; |
67e61fe7 BS |
5620 | |
5621 | rtx save_reload_reg_rtx[MAX_RELOADS]; | |
32131a9c | 5622 | |
32131a9c RK |
5623 | /* In order to be certain of getting the registers we need, |
5624 | we must sort the reloads into order of increasing register class. | |
5625 | Then our grabbing of reload registers will parallel the process | |
a8fdc208 | 5626 | that provided the reload registers. |
32131a9c RK |
5627 | |
5628 | Also note whether any of the reloads wants a consecutive group of regs. | |
5629 | If so, record the maximum size of the group desired and what | |
5630 | register class contains all the groups needed by this insn. */ | |
5631 | ||
5632 | for (j = 0; j < n_reloads; j++) | |
5633 | { | |
5634 | reload_order[j] = j; | |
374d961c BS |
5635 | if (rld[j].reg_rtx != NULL_RTX) |
5636 | { | |
5637 | gcc_assert (REG_P (rld[j].reg_rtx) | |
5638 | && HARD_REGISTER_P (rld[j].reg_rtx)); | |
5639 | reload_spill_index[j] = REGNO (rld[j].reg_rtx); | |
5640 | } | |
5641 | else | |
5642 | reload_spill_index[j] = -1; | |
32131a9c | 5643 | |
8ec450a4 | 5644 | if (rld[j].nregs > 1) |
32131a9c | 5645 | { |
8ec450a4 | 5646 | max_group_size = MAX (rld[j].nregs, max_group_size); |
770ae6cc | 5647 | group_class |
8e2e89f7 | 5648 | = reg_class_superunion[(int) rld[j].class][(int) group_class]; |
32131a9c RK |
5649 | } |
5650 | ||
eceef4c9 | 5651 | save_reload_reg_rtx[j] = rld[j].reg_rtx; |
32131a9c RK |
5652 | } |
5653 | ||
5654 | if (n_reloads > 1) | |
5655 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
5656 | ||
58b1581b RS |
5657 | /* If -O, try first with inheritance, then turning it off. |
5658 | If not -O, don't do inheritance. | |
5659 | Using inheritance when not optimizing leads to paradoxes | |
5660 | with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves | |
5661 | because one side of the comparison might be inherited. */ | |
f5d8c9f4 | 5662 | win = 0; |
58b1581b | 5663 | for (inheritance = optimize > 0; inheritance >= 0; inheritance--) |
32131a9c | 5664 | { |
67e61fe7 BS |
5665 | choose_reload_regs_init (chain, save_reload_reg_rtx); |
5666 | ||
32131a9c RK |
5667 | /* Process the reloads in order of preference just found. |
5668 | Beyond this point, subregs can be found in reload_reg_rtx. | |
5669 | ||
770ae6cc RK |
5670 | This used to look for an existing reloaded home for all of the |
5671 | reloads, and only then perform any new reloads. But that could lose | |
5672 | if the reloads were done out of reg-class order because a later | |
5673 | reload with a looser constraint might have an old home in a register | |
5674 | needed by an earlier reload with a tighter constraint. | |
32131a9c RK |
5675 | |
5676 | To solve this, we make two passes over the reloads, in the order | |
5677 | described above. In the first pass we try to inherit a reload | |
5678 | from a previous insn. If there is a later reload that needs a | |
5679 | class that is a proper subset of the class being processed, we must | |
5680 | also allocate a spill register during the first pass. | |
5681 | ||
5682 | Then make a second pass over the reloads to allocate any reloads | |
5683 | that haven't been given registers yet. */ | |
5684 | ||
5685 | for (j = 0; j < n_reloads; j++) | |
5686 | { | |
b3694847 | 5687 | int r = reload_order[j]; |
8593b745 | 5688 | rtx search_equiv = NULL_RTX; |
32131a9c RK |
5689 | |
5690 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 BS |
5691 | if (rld[r].out == 0 && rld[r].in == 0 |
5692 | && ! rld[r].secondary_p) | |
32131a9c RK |
5693 | continue; |
5694 | ||
b29514ee | 5695 | /* If find_reloads chose to use reload_in or reload_out as a reload |
b080c137 RK |
5696 | register, we don't need to chose one. Otherwise, try even if it |
5697 | found one since we might save an insn if we find the value lying | |
b29514ee R |
5698 | around. |
5699 | Try also when reload_in is a pseudo without a hard reg. */ | |
eceef4c9 BS |
5700 | if (rld[r].in != 0 && rld[r].reg_rtx != 0 |
5701 | && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) | |
5702 | || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) | |
3c0cb5de | 5703 | && !MEM_P (rld[r].in) |
eceef4c9 | 5704 | && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) |
32131a9c RK |
5705 | continue; |
5706 | ||
5707 | #if 0 /* No longer needed for correct operation. | |
5708 | It might give better code, or might not; worth an experiment? */ | |
5709 | /* If this is an optional reload, we can't inherit from earlier insns | |
5710 | until we are sure that any non-optional reloads have been allocated. | |
5711 | The following code takes advantage of the fact that optional reloads | |
5712 | are at the end of reload_order. */ | |
eceef4c9 | 5713 | if (rld[r].optional != 0) |
32131a9c | 5714 | for (i = 0; i < j; i++) |
eceef4c9 BS |
5715 | if ((rld[reload_order[i]].out != 0 |
5716 | || rld[reload_order[i]].in != 0 | |
5717 | || rld[reload_order[i]].secondary_p) | |
5718 | && ! rld[reload_order[i]].optional | |
5719 | && rld[reload_order[i]].reg_rtx == 0) | |
f5d8c9f4 | 5720 | allocate_reload_reg (chain, reload_order[i], 0); |
32131a9c RK |
5721 | #endif |
5722 | ||
5723 | /* First see if this pseudo is already available as reloaded | |
5724 | for a previous insn. We cannot try to inherit for reloads | |
5725 | that are smaller than the maximum number of registers needed | |
5726 | for groups unless the register we would allocate cannot be used | |
5727 | for the groups. | |
5728 | ||
5729 | We could check here to see if this is a secondary reload for | |
5730 | an object that is already in a register of the desired class. | |
5731 | This would avoid the need for the secondary reload register. | |
5732 | But this is complex because we can't easily determine what | |
b080c137 RK |
5733 | objects might want to be loaded via this reload. So let a |
5734 | register be allocated here. In `emit_reload_insns' we suppress | |
5735 | one of the loads in the case described above. */ | |
32131a9c RK |
5736 | |
5737 | if (inheritance) | |
5738 | { | |
ddef6bc7 | 5739 | int byte = 0; |
b3694847 | 5740 | int regno = -1; |
6a651371 | 5741 | enum machine_mode mode = VOIDmode; |
32131a9c | 5742 | |
eceef4c9 | 5743 | if (rld[r].in == 0) |
32131a9c | 5744 | ; |
f8cfc6aa | 5745 | else if (REG_P (rld[r].in)) |
db660765 | 5746 | { |
eceef4c9 BS |
5747 | regno = REGNO (rld[r].in); |
5748 | mode = GET_MODE (rld[r].in); | |
db660765 | 5749 | } |
f8cfc6aa | 5750 | else if (REG_P (rld[r].in_reg)) |
db660765 | 5751 | { |
eceef4c9 BS |
5752 | regno = REGNO (rld[r].in_reg); |
5753 | mode = GET_MODE (rld[r].in_reg); | |
db660765 | 5754 | } |
eceef4c9 | 5755 | else if (GET_CODE (rld[r].in_reg) == SUBREG |
f8cfc6aa | 5756 | && REG_P (SUBREG_REG (rld[r].in_reg))) |
b60a8416 | 5757 | { |
eceef4c9 | 5758 | regno = REGNO (SUBREG_REG (rld[r].in_reg)); |
cb2afeb3 | 5759 | if (regno < FIRST_PSEUDO_REGISTER) |
ddef6bc7 | 5760 | regno = subreg_regno (rld[r].in_reg); |
15447fae RIL |
5761 | else |
5762 | byte = SUBREG_BYTE (rld[r].in_reg); | |
eceef4c9 | 5763 | mode = GET_MODE (rld[r].in_reg); |
cb2afeb3 R |
5764 | } |
5765 | #ifdef AUTO_INC_DEC | |
67f07489 | 5766 | else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC |
f8cfc6aa | 5767 | && REG_P (XEXP (rld[r].in_reg, 0))) |
cb2afeb3 | 5768 | { |
eceef4c9 BS |
5769 | regno = REGNO (XEXP (rld[r].in_reg, 0)); |
5770 | mode = GET_MODE (XEXP (rld[r].in_reg, 0)); | |
5771 | rld[r].out = rld[r].in; | |
b60a8416 | 5772 | } |
cb2afeb3 | 5773 | #endif |
32131a9c RK |
5774 | #if 0 |
5775 | /* This won't work, since REGNO can be a pseudo reg number. | |
5776 | Also, it takes much more hair to keep track of all the things | |
5777 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
eceef4c9 | 5778 | else if (GET_CODE (rld[r].in) == SUBREG |
f8cfc6aa | 5779 | && REG_P (SUBREG_REG (rld[r].in))) |
ddef6bc7 | 5780 | regno = subreg_regno (rld[r].in); |
32131a9c RK |
5781 | #endif |
5782 | ||
21f14ff9 DD |
5783 | if (regno >= 0 |
5784 | && reg_last_reload_reg[regno] != 0 | |
5785 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
5786 | /* Verify that the register it's in can be used in | |
5787 | mode MODE. */ | |
5788 | && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]), | |
5789 | GET_MODE (reg_last_reload_reg[regno]), | |
5790 | mode) | |
5791 | #endif | |
5792 | ) | |
32131a9c | 5793 | { |
eceef4c9 | 5794 | enum reg_class class = rld[r].class, last_class; |
cb2afeb3 | 5795 | rtx last_reg = reg_last_reload_reg[regno]; |
02188693 | 5796 | enum machine_mode need_mode; |
05d10675 | 5797 | |
ddef6bc7 JJ |
5798 | i = REGNO (last_reg); |
5799 | i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode); | |
cb2afeb3 | 5800 | last_class = REGNO_REG_CLASS (i); |
02188693 | 5801 | |
ddef6bc7 | 5802 | if (byte == 0) |
ce701d1b BS |
5803 | need_mode = mode; |
5804 | else | |
5805 | need_mode | |
1de80b0e RS |
5806 | = smallest_mode_for_size (GET_MODE_BITSIZE (mode) |
5807 | + byte * BITS_PER_UNIT, | |
ce701d1b | 5808 | GET_MODE_CLASS (mode)); |
02188693 | 5809 | |
1de80b0e | 5810 | if ((GET_MODE_SIZE (GET_MODE (last_reg)) |
02188693 | 5811 | >= GET_MODE_SIZE (need_mode)) |
cb2afeb3 | 5812 | && reg_reloaded_contents[i] == regno |
e6e52be0 | 5813 | && TEST_HARD_REG_BIT (reg_reloaded_valid, i) |
8ec450a4 | 5814 | && HARD_REGNO_MODE_OK (i, rld[r].mode) |
cb2afeb3 R |
5815 | && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i) |
5816 | /* Even if we can't use this register as a reload | |
5817 | register, we might use it for reload_override_in, | |
5818 | if copying it to the desired class is cheap | |
5819 | enough. */ | |
e56b4594 | 5820 | || ((REGISTER_MOVE_COST (mode, last_class, class) |
cb2afeb3 | 5821 | < MEMORY_MOVE_COST (mode, class, 1)) |
8a99f6f9 R |
5822 | && (secondary_reload_class (1, class, mode, |
5823 | last_reg) | |
cb2afeb3 | 5824 | == NO_REGS) |
cb2afeb3 R |
5825 | #ifdef SECONDARY_MEMORY_NEEDED |
5826 | && ! SECONDARY_MEMORY_NEEDED (last_class, class, | |
5827 | mode) | |
5828 | #endif | |
5829 | )) | |
5830 | ||
8ec450a4 | 5831 | && (rld[r].nregs == max_group_size |
32131a9c | 5832 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], |
e6e52be0 | 5833 | i)) |
c02cad8f BS |
5834 | && free_for_value_p (i, rld[r].mode, rld[r].opnum, |
5835 | rld[r].when_needed, rld[r].in, | |
5836 | const0_rtx, r, 1)) | |
32131a9c RK |
5837 | { |
5838 | /* If a group is needed, verify that all the subsequent | |
0f41302f | 5839 | registers still have their values intact. */ |
66fd46b6 | 5840 | int nr = hard_regno_nregs[i][rld[r].mode]; |
32131a9c RK |
5841 | int k; |
5842 | ||
5843 | for (k = 1; k < nr; k++) | |
e6e52be0 R |
5844 | if (reg_reloaded_contents[i + k] != regno |
5845 | || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) | |
32131a9c RK |
5846 | break; |
5847 | ||
5848 | if (k == nr) | |
5849 | { | |
c74fa651 | 5850 | int i1; |
eb4d554e | 5851 | int bad_for_class; |
c74fa651 | 5852 | |
cb2afeb3 R |
5853 | last_reg = (GET_MODE (last_reg) == mode |
5854 | ? last_reg : gen_rtx_REG (mode, i)); | |
5855 | ||
eb4d554e GK |
5856 | bad_for_class = 0; |
5857 | for (k = 0; k < nr; k++) | |
5858 | bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], | |
5859 | i+k); | |
5860 | ||
c74fa651 RS |
5861 | /* We found a register that contains the |
5862 | value we need. If this register is the | |
5863 | same as an `earlyclobber' operand of the | |
5864 | current insn, just mark it as a place to | |
5865 | reload from since we can't use it as the | |
5866 | reload register itself. */ | |
5867 | ||
5868 | for (i1 = 0; i1 < n_earlyclobbers; i1++) | |
5869 | if (reg_overlap_mentioned_for_reload_p | |
5870 | (reg_last_reload_reg[regno], | |
5871 | reload_earlyclobbers[i1])) | |
5872 | break; | |
5873 | ||
8908158d | 5874 | if (i1 != n_earlyclobbers |
c02cad8f BS |
5875 | || ! (free_for_value_p (i, rld[r].mode, |
5876 | rld[r].opnum, | |
5877 | rld[r].when_needed, rld[r].in, | |
5878 | rld[r].out, r, 1)) | |
e6e52be0 | 5879 | /* Don't use it if we'd clobber a pseudo reg. */ |
f1db3576 | 5880 | || (TEST_HARD_REG_BIT (reg_used_in_insn, i) |
eceef4c9 | 5881 | && rld[r].out |
e6e52be0 | 5882 | && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) |
0c7f2259 | 5883 | /* Don't clobber the frame pointer. */ |
1d7254c5 | 5884 | || (i == HARD_FRAME_POINTER_REGNUM |
2f460a0a | 5885 | && frame_pointer_needed |
1d7254c5 | 5886 | && rld[r].out) |
8908158d RS |
5887 | /* Don't really use the inherited spill reg |
5888 | if we need it wider than we've got it. */ | |
8ec450a4 | 5889 | || (GET_MODE_SIZE (rld[r].mode) |
b29514ee | 5890 | > GET_MODE_SIZE (mode)) |
eb4d554e | 5891 | || bad_for_class |
cb2afeb3 | 5892 | |
b29514ee R |
5893 | /* If find_reloads chose reload_out as reload |
5894 | register, stay with it - that leaves the | |
5895 | inherited register for subsequent reloads. */ | |
eceef4c9 | 5896 | || (rld[r].out && rld[r].reg_rtx |
67e61fe7 | 5897 | && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) |
cb2afeb3 | 5898 | { |
4c3a2649 BS |
5899 | if (! rld[r].optional) |
5900 | { | |
5901 | reload_override_in[r] = last_reg; | |
5902 | reload_inheritance_insn[r] | |
5903 | = reg_reloaded_insn[i]; | |
5904 | } | |
cb2afeb3 | 5905 | } |
c74fa651 RS |
5906 | else |
5907 | { | |
54c40e68 | 5908 | int k; |
c74fa651 RS |
5909 | /* We can use this as a reload reg. */ |
5910 | /* Mark the register as in use for this part of | |
5911 | the insn. */ | |
e6e52be0 | 5912 | mark_reload_reg_in_use (i, |
eceef4c9 BS |
5913 | rld[r].opnum, |
5914 | rld[r].when_needed, | |
8ec450a4 | 5915 | rld[r].mode); |
eceef4c9 | 5916 | rld[r].reg_rtx = last_reg; |
c74fa651 RS |
5917 | reload_inherited[r] = 1; |
5918 | reload_inheritance_insn[r] | |
5919 | = reg_reloaded_insn[i]; | |
5920 | reload_spill_index[r] = i; | |
54c40e68 RS |
5921 | for (k = 0; k < nr; k++) |
5922 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, | |
e6e52be0 | 5923 | i + k); |
c74fa651 | 5924 | } |
32131a9c RK |
5925 | } |
5926 | } | |
5927 | } | |
5928 | } | |
5929 | ||
5930 | /* Here's another way to see if the value is already lying around. */ | |
5931 | if (inheritance | |
eceef4c9 | 5932 | && rld[r].in != 0 |
32131a9c | 5933 | && ! reload_inherited[r] |
eceef4c9 BS |
5934 | && rld[r].out == 0 |
5935 | && (CONSTANT_P (rld[r].in) | |
5936 | || GET_CODE (rld[r].in) == PLUS | |
f8cfc6aa | 5937 | || REG_P (rld[r].in) |
3c0cb5de | 5938 | || MEM_P (rld[r].in)) |
8ec450a4 | 5939 | && (rld[r].nregs == max_group_size |
eceef4c9 BS |
5940 | || ! reg_classes_intersect_p (rld[r].class, group_class))) |
5941 | search_equiv = rld[r].in; | |
8593b745 R |
5942 | /* If this is an output reload from a simple move insn, look |
5943 | if an equivalence for the input is available. */ | |
eceef4c9 | 5944 | else if (inheritance && rld[r].in == 0 && rld[r].out != 0) |
8593b745 R |
5945 | { |
5946 | rtx set = single_set (insn); | |
5947 | ||
5948 | if (set | |
eceef4c9 | 5949 | && rtx_equal_p (rld[r].out, SET_DEST (set)) |
8593b745 R |
5950 | && CONSTANT_P (SET_SRC (set))) |
5951 | search_equiv = SET_SRC (set); | |
5952 | } | |
5953 | ||
5954 | if (search_equiv) | |
32131a9c | 5955 | { |
b3694847 | 5956 | rtx equiv |
eceef4c9 | 5957 | = find_equiv_reg (search_equiv, insn, rld[r].class, |
9714cf43 | 5958 | -1, NULL, 0, rld[r].mode); |
f428f252 | 5959 | int regno = 0; |
32131a9c RK |
5960 | |
5961 | if (equiv != 0) | |
5962 | { | |
f8cfc6aa | 5963 | if (REG_P (equiv)) |
32131a9c | 5964 | regno = REGNO (equiv); |
41374e13 | 5965 | else |
32131a9c | 5966 | { |
f8a9e02b RK |
5967 | /* This must be a SUBREG of a hard register. |
5968 | Make a new REG since this might be used in an | |
5969 | address and not all machines support SUBREGs | |
5970 | there. */ | |
41374e13 | 5971 | gcc_assert (GET_CODE (equiv) == SUBREG); |
ddef6bc7 | 5972 | regno = subreg_regno (equiv); |
8ec450a4 | 5973 | equiv = gen_rtx_REG (rld[r].mode, regno); |
9c0a30c3 EB |
5974 | /* If we choose EQUIV as the reload register, but the |
5975 | loop below decides to cancel the inheritance, we'll | |
5976 | end up reloading EQUIV in rld[r].mode, not the mode | |
5977 | it had originally. That isn't safe when EQUIV isn't | |
5978 | available as a spill register since its value might | |
5979 | still be live at this point. */ | |
5980 | for (i = regno; i < regno + (int) rld[r].nregs; i++) | |
5981 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, i)) | |
5982 | equiv = 0; | |
32131a9c | 5983 | } |
32131a9c RK |
5984 | } |
5985 | ||
5986 | /* If we found a spill reg, reject it unless it is free | |
5987 | and of the desired class. */ | |
f58d8c95 JW |
5988 | if (equiv != 0) |
5989 | { | |
5990 | int regs_used = 0; | |
5991 | int bad_for_class = 0; | |
5992 | int max_regno = regno + rld[r].nregs; | |
5993 | ||
5994 | for (i = regno; i < max_regno; i++) | |
5995 | { | |
5996 | regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
5997 | i); | |
0c20a65f | 5998 | bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], |
f58d8c95 JW |
5999 | i); |
6000 | } | |
6001 | ||
6002 | if ((regs_used | |
c02cad8f BS |
6003 | && ! free_for_value_p (regno, rld[r].mode, |
6004 | rld[r].opnum, rld[r].when_needed, | |
6005 | rld[r].in, rld[r].out, r, 1)) | |
f58d8c95 JW |
6006 | || bad_for_class) |
6007 | equiv = 0; | |
6008 | } | |
32131a9c | 6009 | |
8ec450a4 | 6010 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) |
32131a9c RK |
6011 | equiv = 0; |
6012 | ||
6013 | /* We found a register that contains the value we need. | |
6014 | If this register is the same as an `earlyclobber' operand | |
6015 | of the current insn, just mark it as a place to reload from | |
6016 | since we can't use it as the reload register itself. */ | |
6017 | ||
6018 | if (equiv != 0) | |
6019 | for (i = 0; i < n_earlyclobbers; i++) | |
bfa30b22 RK |
6020 | if (reg_overlap_mentioned_for_reload_p (equiv, |
6021 | reload_earlyclobbers[i])) | |
32131a9c | 6022 | { |
4c3a2649 BS |
6023 | if (! rld[r].optional) |
6024 | reload_override_in[r] = equiv; | |
32131a9c RK |
6025 | equiv = 0; |
6026 | break; | |
6027 | } | |
6028 | ||
3c785e47 R |
6029 | /* If the equiv register we have found is explicitly clobbered |
6030 | in the current insn, it depends on the reload type if we | |
6031 | can use it, use it for reload_override_in, or not at all. | |
6032 | In particular, we then can't use EQUIV for a | |
6033 | RELOAD_FOR_OUTPUT_ADDRESS reload. */ | |
32131a9c | 6034 | |
9532e31f | 6035 | if (equiv != 0) |
174fa2c4 | 6036 | { |
d0236c3b | 6037 | if (regno_clobbered_p (regno, insn, rld[r].mode, 2)) |
9532e31f BS |
6038 | switch (rld[r].when_needed) |
6039 | { | |
6040 | case RELOAD_FOR_OTHER_ADDRESS: | |
6041 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6042 | case RELOAD_FOR_INPUT_ADDRESS: | |
6043 | case RELOAD_FOR_OPADDR_ADDR: | |
6044 | break; | |
6045 | case RELOAD_OTHER: | |
6046 | case RELOAD_FOR_INPUT: | |
6047 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6048 | if (! rld[r].optional) | |
6049 | reload_override_in[r] = equiv; | |
6050 | /* Fall through. */ | |
6051 | default: | |
6052 | equiv = 0; | |
6053 | break; | |
6054 | } | |
6055 | else if (regno_clobbered_p (regno, insn, rld[r].mode, 1)) | |
6056 | switch (rld[r].when_needed) | |
6057 | { | |
6058 | case RELOAD_FOR_OTHER_ADDRESS: | |
6059 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6060 | case RELOAD_FOR_INPUT_ADDRESS: | |
6061 | case RELOAD_FOR_OPADDR_ADDR: | |
6062 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6063 | case RELOAD_FOR_INPUT: | |
6064 | break; | |
6065 | case RELOAD_OTHER: | |
6066 | if (! rld[r].optional) | |
6067 | reload_override_in[r] = equiv; | |
6068 | /* Fall through. */ | |
6069 | default: | |
6070 | equiv = 0; | |
6071 | break; | |
6072 | } | |
32131a9c RK |
6073 | } |
6074 | ||
6075 | /* If we found an equivalent reg, say no code need be generated | |
6076 | to load it, and use it as our reload reg. */ | |
a6a2274a KH |
6077 | if (equiv != 0 |
6078 | && (regno != HARD_FRAME_POINTER_REGNUM | |
2f460a0a | 6079 | || !frame_pointer_needed)) |
32131a9c | 6080 | { |
66fd46b6 | 6081 | int nr = hard_regno_nregs[regno][rld[r].mode]; |
100338df | 6082 | int k; |
eceef4c9 | 6083 | rld[r].reg_rtx = equiv; |
32131a9c | 6084 | reload_inherited[r] = 1; |
100338df | 6085 | |
91d7e7ac R |
6086 | /* If reg_reloaded_valid is not set for this register, |
6087 | there might be a stale spill_reg_store lying around. | |
6088 | We must clear it, since otherwise emit_reload_insns | |
6089 | might delete the store. */ | |
6090 | if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) | |
6091 | spill_reg_store[regno] = NULL_RTX; | |
100338df JL |
6092 | /* If any of the hard registers in EQUIV are spill |
6093 | registers, mark them as in use for this insn. */ | |
6094 | for (k = 0; k < nr; k++) | |
be7ae2a4 | 6095 | { |
100338df JL |
6096 | i = spill_reg_order[regno + k]; |
6097 | if (i >= 0) | |
6098 | { | |
eceef4c9 BS |
6099 | mark_reload_reg_in_use (regno, rld[r].opnum, |
6100 | rld[r].when_needed, | |
8ec450a4 | 6101 | rld[r].mode); |
100338df JL |
6102 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, |
6103 | regno + k); | |
6104 | } | |
be7ae2a4 | 6105 | } |
32131a9c RK |
6106 | } |
6107 | } | |
6108 | ||
6109 | /* If we found a register to use already, or if this is an optional | |
6110 | reload, we are done. */ | |
eceef4c9 | 6111 | if (rld[r].reg_rtx != 0 || rld[r].optional != 0) |
32131a9c RK |
6112 | continue; |
6113 | ||
1d7254c5 KH |
6114 | #if 0 |
6115 | /* No longer needed for correct operation. Might or might | |
6116 | not give better code on the average. Want to experiment? */ | |
32131a9c RK |
6117 | |
6118 | /* See if there is a later reload that has a class different from our | |
6119 | class that intersects our class or that requires less register | |
6120 | than our reload. If so, we must allocate a register to this | |
6121 | reload now, since that reload might inherit a previous reload | |
6122 | and take the only available register in our class. Don't do this | |
6123 | for optional reloads since they will force all previous reloads | |
6124 | to be allocated. Also don't do this for reloads that have been | |
6125 | turned off. */ | |
6126 | ||
6127 | for (i = j + 1; i < n_reloads; i++) | |
6128 | { | |
6129 | int s = reload_order[i]; | |
6130 | ||
eceef4c9 BS |
6131 | if ((rld[s].in == 0 && rld[s].out == 0 |
6132 | && ! rld[s].secondary_p) | |
6133 | || rld[s].optional) | |
32131a9c RK |
6134 | continue; |
6135 | ||
eceef4c9 BS |
6136 | if ((rld[s].class != rld[r].class |
6137 | && reg_classes_intersect_p (rld[r].class, | |
6138 | rld[s].class)) | |
8ec450a4 | 6139 | || rld[s].nregs < rld[r].nregs) |
05d10675 | 6140 | break; |
32131a9c RK |
6141 | } |
6142 | ||
6143 | if (i == n_reloads) | |
6144 | continue; | |
6145 | ||
f5d8c9f4 | 6146 | allocate_reload_reg (chain, r, j == n_reloads - 1); |
32131a9c RK |
6147 | #endif |
6148 | } | |
6149 | ||
6150 | /* Now allocate reload registers for anything non-optional that | |
6151 | didn't get one yet. */ | |
6152 | for (j = 0; j < n_reloads; j++) | |
6153 | { | |
b3694847 | 6154 | int r = reload_order[j]; |
32131a9c RK |
6155 | |
6156 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 | 6157 | if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) |
32131a9c RK |
6158 | continue; |
6159 | ||
6160 | /* Skip reloads that already have a register allocated or are | |
0f41302f | 6161 | optional. */ |
eceef4c9 | 6162 | if (rld[r].reg_rtx != 0 || rld[r].optional) |
32131a9c RK |
6163 | continue; |
6164 | ||
f5d8c9f4 | 6165 | if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) |
32131a9c RK |
6166 | break; |
6167 | } | |
6168 | ||
6169 | /* If that loop got all the way, we have won. */ | |
6170 | if (j == n_reloads) | |
f5d8c9f4 BS |
6171 | { |
6172 | win = 1; | |
6173 | break; | |
6174 | } | |
32131a9c | 6175 | |
32131a9c | 6176 | /* Loop around and try without any inheritance. */ |
32131a9c RK |
6177 | } |
6178 | ||
f5d8c9f4 BS |
6179 | if (! win) |
6180 | { | |
6181 | /* First undo everything done by the failed attempt | |
6182 | to allocate with inheritance. */ | |
6183 | choose_reload_regs_init (chain, save_reload_reg_rtx); | |
6184 | ||
6185 | /* Some sanity tests to verify that the reloads found in the first | |
6186 | pass are identical to the ones we have now. */ | |
41374e13 | 6187 | gcc_assert (chain->n_reloads == n_reloads); |
f5d8c9f4 BS |
6188 | |
6189 | for (i = 0; i < n_reloads; i++) | |
6190 | { | |
6191 | if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) | |
6192 | continue; | |
41374e13 | 6193 | gcc_assert (chain->rld[i].when_needed == rld[i].when_needed); |
f5d8c9f4 BS |
6194 | for (j = 0; j < n_spills; j++) |
6195 | if (spill_regs[j] == chain->rld[i].regno) | |
6196 | if (! set_reload_reg (j, i)) | |
6197 | failed_reload (chain->insn, i); | |
6198 | } | |
6199 | } | |
6200 | ||
32131a9c RK |
6201 | /* If we thought we could inherit a reload, because it seemed that |
6202 | nothing else wanted the same reload register earlier in the insn, | |
cb2afeb3 R |
6203 | verify that assumption, now that all reloads have been assigned. |
6204 | Likewise for reloads where reload_override_in has been set. */ | |
32131a9c | 6205 | |
cb2afeb3 R |
6206 | /* If doing expensive optimizations, do one preliminary pass that doesn't |
6207 | cancel any inheritance, but removes reloads that have been needed only | |
6208 | for reloads that we know can be inherited. */ | |
6209 | for (pass = flag_expensive_optimizations; pass >= 0; pass--) | |
32131a9c | 6210 | { |
cb2afeb3 | 6211 | for (j = 0; j < n_reloads; j++) |
029b38ff | 6212 | { |
b3694847 | 6213 | int r = reload_order[j]; |
cb2afeb3 | 6214 | rtx check_reg; |
eceef4c9 BS |
6215 | if (reload_inherited[r] && rld[r].reg_rtx) |
6216 | check_reg = rld[r].reg_rtx; | |
cb2afeb3 | 6217 | else if (reload_override_in[r] |
f8cfc6aa | 6218 | && (REG_P (reload_override_in[r]) |
05d10675 | 6219 | || GET_CODE (reload_override_in[r]) == SUBREG)) |
cb2afeb3 R |
6220 | check_reg = reload_override_in[r]; |
6221 | else | |
6222 | continue; | |
c02cad8f BS |
6223 | if (! free_for_value_p (true_regnum (check_reg), rld[r].mode, |
6224 | rld[r].opnum, rld[r].when_needed, rld[r].in, | |
6225 | (reload_inherited[r] | |
6226 | ? rld[r].out : const0_rtx), | |
6227 | r, 1)) | |
029b38ff | 6228 | { |
cb2afeb3 R |
6229 | if (pass) |
6230 | continue; | |
6231 | reload_inherited[r] = 0; | |
6232 | reload_override_in[r] = 0; | |
029b38ff | 6233 | } |
cb2afeb3 R |
6234 | /* If we can inherit a RELOAD_FOR_INPUT, or can use a |
6235 | reload_override_in, then we do not need its related | |
6236 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; | |
6237 | likewise for other reload types. | |
6238 | We handle this by removing a reload when its only replacement | |
6239 | is mentioned in reload_in of the reload we are going to inherit. | |
6240 | A special case are auto_inc expressions; even if the input is | |
6241 | inherited, we still need the address for the output. We can | |
fe92fe26 | 6242 | recognize them because they have RELOAD_OUT set to RELOAD_IN. |
eaec9b3d | 6243 | If we succeeded removing some reload and we are doing a preliminary |
cb2afeb3 R |
6244 | pass just to remove such reloads, make another pass, since the |
6245 | removal of one reload might allow us to inherit another one. */ | |
eceef4c9 BS |
6246 | else if (rld[r].in |
6247 | && rld[r].out != rld[r].in | |
6248 | && remove_address_replacements (rld[r].in) && pass) | |
cb2afeb3 | 6249 | pass = 2; |
32131a9c RK |
6250 | } |
6251 | } | |
6252 | ||
6253 | /* Now that reload_override_in is known valid, | |
6254 | actually override reload_in. */ | |
6255 | for (j = 0; j < n_reloads; j++) | |
6256 | if (reload_override_in[j]) | |
eceef4c9 | 6257 | rld[j].in = reload_override_in[j]; |
32131a9c | 6258 | |
272d0bee | 6259 | /* If this reload won't be done because it has been canceled or is |
32131a9c RK |
6260 | optional and not inherited, clear reload_reg_rtx so other |
6261 | routines (such as subst_reloads) don't get confused. */ | |
6262 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
6263 | if (rld[j].reg_rtx != 0 |
6264 | && ((rld[j].optional && ! reload_inherited[j]) | |
6265 | || (rld[j].in == 0 && rld[j].out == 0 | |
6266 | && ! rld[j].secondary_p))) | |
be7ae2a4 | 6267 | { |
eceef4c9 | 6268 | int regno = true_regnum (rld[j].reg_rtx); |
be7ae2a4 RK |
6269 | |
6270 | if (spill_reg_order[regno] >= 0) | |
eceef4c9 | 6271 | clear_reload_reg_in_use (regno, rld[j].opnum, |
8ec450a4 | 6272 | rld[j].when_needed, rld[j].mode); |
eceef4c9 | 6273 | rld[j].reg_rtx = 0; |
c0029be5 | 6274 | reload_spill_index[j] = -1; |
be7ae2a4 | 6275 | } |
32131a9c RK |
6276 | |
6277 | /* Record which pseudos and which spill regs have output reloads. */ | |
6278 | for (j = 0; j < n_reloads; j++) | |
6279 | { | |
b3694847 | 6280 | int r = reload_order[j]; |
32131a9c RK |
6281 | |
6282 | i = reload_spill_index[r]; | |
6283 | ||
e6e52be0 | 6284 | /* I is nonneg if this reload uses a register. |
eceef4c9 | 6285 | If rld[r].reg_rtx is 0, this is an optional reload |
32131a9c | 6286 | that we opted to ignore. */ |
f8cfc6aa | 6287 | if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg) |
eceef4c9 | 6288 | && rld[r].reg_rtx != 0) |
32131a9c | 6289 | { |
b3694847 | 6290 | int nregno = REGNO (rld[r].out_reg); |
372e033b RS |
6291 | int nr = 1; |
6292 | ||
6293 | if (nregno < FIRST_PSEUDO_REGISTER) | |
66fd46b6 | 6294 | nr = hard_regno_nregs[nregno][rld[r].mode]; |
32131a9c RK |
6295 | |
6296 | while (--nr >= 0) | |
2c61f5f1 JH |
6297 | SET_REGNO_REG_SET (®_has_output_reload, |
6298 | nregno + nr); | |
372e033b RS |
6299 | |
6300 | if (i >= 0) | |
32131a9c | 6301 | { |
66fd46b6 | 6302 | nr = hard_regno_nregs[i][rld[r].mode]; |
372e033b | 6303 | while (--nr >= 0) |
e6e52be0 | 6304 | SET_HARD_REG_BIT (reg_is_output_reload, i + nr); |
32131a9c RK |
6305 | } |
6306 | ||
41374e13 NS |
6307 | gcc_assert (rld[r].when_needed == RELOAD_OTHER |
6308 | || rld[r].when_needed == RELOAD_FOR_OUTPUT | |
6309 | || rld[r].when_needed == RELOAD_FOR_INSN); | |
32131a9c RK |
6310 | } |
6311 | } | |
6312 | } | |
cb2afeb3 R |
6313 | |
6314 | /* Deallocate the reload register for reload R. This is called from | |
6315 | remove_address_replacements. */ | |
1d813780 | 6316 | |
cb2afeb3 | 6317 | void |
0c20a65f | 6318 | deallocate_reload_reg (int r) |
cb2afeb3 R |
6319 | { |
6320 | int regno; | |
6321 | ||
eceef4c9 | 6322 | if (! rld[r].reg_rtx) |
cb2afeb3 | 6323 | return; |
eceef4c9 BS |
6324 | regno = true_regnum (rld[r].reg_rtx); |
6325 | rld[r].reg_rtx = 0; | |
cb2afeb3 | 6326 | if (spill_reg_order[regno] >= 0) |
eceef4c9 | 6327 | clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, |
8ec450a4 | 6328 | rld[r].mode); |
cb2afeb3 R |
6329 | reload_spill_index[r] = -1; |
6330 | } | |
32131a9c | 6331 | \f |
40f03658 | 6332 | /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two |
546b63fb RK |
6333 | reloads of the same item for fear that we might not have enough reload |
6334 | registers. However, normally they will get the same reload register | |
05d10675 | 6335 | and hence actually need not be loaded twice. |
546b63fb RK |
6336 | |
6337 | Here we check for the most common case of this phenomenon: when we have | |
6338 | a number of reloads for the same object, each of which were allocated | |
6339 | the same reload_reg_rtx, that reload_reg_rtx is not used for any other | |
6340 | reload, and is not modified in the insn itself. If we find such, | |
6341 | merge all the reloads and set the resulting reload to RELOAD_OTHER. | |
6342 | This will not increase the number of spill registers needed and will | |
6343 | prevent redundant code. */ | |
6344 | ||
546b63fb | 6345 | static void |
0c20a65f | 6346 | merge_assigned_reloads (rtx insn) |
546b63fb RK |
6347 | { |
6348 | int i, j; | |
6349 | ||
6350 | /* Scan all the reloads looking for ones that only load values and | |
6351 | are not already RELOAD_OTHER and ones whose reload_reg_rtx are | |
6352 | assigned and not modified by INSN. */ | |
6353 | ||
6354 | for (i = 0; i < n_reloads; i++) | |
6355 | { | |
d668e863 R |
6356 | int conflicting_input = 0; |
6357 | int max_input_address_opnum = -1; | |
6358 | int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; | |
6359 | ||
eceef4c9 BS |
6360 | if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER |
6361 | || rld[i].out != 0 || rld[i].reg_rtx == 0 | |
6362 | || reg_set_p (rld[i].reg_rtx, insn)) | |
546b63fb RK |
6363 | continue; |
6364 | ||
6365 | /* Look at all other reloads. Ensure that the only use of this | |
6366 | reload_reg_rtx is in a reload that just loads the same value | |
6367 | as we do. Note that any secondary reloads must be of the identical | |
6368 | class since the values, modes, and result registers are the | |
6369 | same, so we need not do anything with any secondary reloads. */ | |
6370 | ||
6371 | for (j = 0; j < n_reloads; j++) | |
6372 | { | |
eceef4c9 BS |
6373 | if (i == j || rld[j].reg_rtx == 0 |
6374 | || ! reg_overlap_mentioned_p (rld[j].reg_rtx, | |
6375 | rld[i].reg_rtx)) | |
546b63fb RK |
6376 | continue; |
6377 | ||
eceef4c9 BS |
6378 | if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6379 | && rld[j].opnum > max_input_address_opnum) | |
6380 | max_input_address_opnum = rld[j].opnum; | |
d668e863 | 6381 | |
546b63fb | 6382 | /* If the reload regs aren't exactly the same (e.g, different modes) |
d668e863 R |
6383 | or if the values are different, we can't merge this reload. |
6384 | But if it is an input reload, we might still merge | |
6385 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ | |
546b63fb | 6386 | |
eceef4c9 BS |
6387 | if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) |
6388 | || rld[j].out != 0 || rld[j].in == 0 | |
6389 | || ! rtx_equal_p (rld[i].in, rld[j].in)) | |
d668e863 | 6390 | { |
eceef4c9 BS |
6391 | if (rld[j].when_needed != RELOAD_FOR_INPUT |
6392 | || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS | |
6393 | || rld[i].opnum > rld[j].opnum) | |
6394 | && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS)) | |
d668e863 R |
6395 | break; |
6396 | conflicting_input = 1; | |
eceef4c9 BS |
6397 | if (min_conflicting_input_opnum > rld[j].opnum) |
6398 | min_conflicting_input_opnum = rld[j].opnum; | |
d668e863 | 6399 | } |
546b63fb RK |
6400 | } |
6401 | ||
6402 | /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if | |
6403 | we, in fact, found any matching reloads. */ | |
6404 | ||
d668e863 R |
6405 | if (j == n_reloads |
6406 | && max_input_address_opnum <= min_conflicting_input_opnum) | |
546b63fb | 6407 | { |
3f27846b DJ |
6408 | gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT); |
6409 | ||
546b63fb | 6410 | for (j = 0; j < n_reloads; j++) |
eceef4c9 BS |
6411 | if (i != j && rld[j].reg_rtx != 0 |
6412 | && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) | |
d668e863 | 6413 | && (! conflicting_input |
eceef4c9 BS |
6414 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6415 | || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
546b63fb | 6416 | { |
eceef4c9 BS |
6417 | rld[i].when_needed = RELOAD_OTHER; |
6418 | rld[j].in = 0; | |
efdb3590 | 6419 | reload_spill_index[j] = -1; |
546b63fb RK |
6420 | transfer_replacements (i, j); |
6421 | } | |
6422 | ||
b883ab57 HMC |
6423 | /* If this is now RELOAD_OTHER, look for any reloads that |
6424 | load parts of this operand and set them to | |
6425 | RELOAD_FOR_OTHER_ADDRESS if they were for inputs, | |
6426 | RELOAD_OTHER for outputs. Note that this test is | |
6427 | equivalent to looking for reloads for this operand | |
6428 | number. | |
6429 | ||
6430 | We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; | |
6431 | it may share registers with a RELOAD_FOR_INPUT, so we can | |
6432 | not change it to RELOAD_FOR_OTHER_ADDRESS. We should | |
6433 | never need to, since we do not modify RELOAD_FOR_OUTPUT. | |
6434 | ||
6435 | It is possible that the RELOAD_FOR_OPERAND_ADDRESS | |
6436 | instruction is assigned the same register as the earlier | |
6437 | RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two | |
6438 | instructions will cause the RELOAD_FOR_OTHER_ADDRESS | |
6439 | instruction to be deleted later on. */ | |
546b63fb | 6440 | |
eceef4c9 | 6441 | if (rld[i].when_needed == RELOAD_OTHER) |
546b63fb | 6442 | for (j = 0; j < n_reloads; j++) |
eceef4c9 | 6443 | if (rld[j].in != 0 |
91667711 | 6444 | && rld[j].when_needed != RELOAD_OTHER |
dec0798e | 6445 | && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS |
3f27846b | 6446 | && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS |
b883ab57 | 6447 | && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS |
dec0798e R |
6448 | && (! conflicting_input |
6449 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
6450 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
eceef4c9 BS |
6451 | && reg_overlap_mentioned_for_reload_p (rld[j].in, |
6452 | rld[i].in)) | |
c15c18c5 JW |
6453 | { |
6454 | int k; | |
6455 | ||
6456 | rld[j].when_needed | |
6457 | = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
6458 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
6459 | ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); | |
6460 | ||
0e61db61 NS |
6461 | /* Check to see if we accidentally converted two |
6462 | reloads that use the same reload register with | |
6463 | different inputs to the same type. If so, the | |
6464 | resulting code won't work. */ | |
c15c18c5 JW |
6465 | if (rld[j].reg_rtx) |
6466 | for (k = 0; k < j; k++) | |
41374e13 NS |
6467 | gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0 |
6468 | || rld[k].when_needed != rld[j].when_needed | |
6469 | || !rtx_equal_p (rld[k].reg_rtx, | |
6470 | rld[j].reg_rtx) | |
6471 | || rtx_equal_p (rld[k].in, | |
6472 | rld[j].in)); | |
c15c18c5 | 6473 | } |
546b63fb RK |
6474 | } |
6475 | } | |
05d10675 | 6476 | } |
546b63fb | 6477 | \f |
367b1cf5 BS |
6478 | /* These arrays are filled by emit_reload_insns and its subroutines. */ |
6479 | static rtx input_reload_insns[MAX_RECOG_OPERANDS]; | |
6480 | static rtx other_input_address_reload_insns = 0; | |
6481 | static rtx other_input_reload_insns = 0; | |
6482 | static rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6483 | static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6484 | static rtx output_reload_insns[MAX_RECOG_OPERANDS]; | |
6485 | static rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6486 | static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6487 | static rtx operand_reload_insns = 0; | |
6488 | static rtx other_operand_reload_insns = 0; | |
6489 | static rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; | |
6490 | ||
6491 | /* Values to be put in spill_reg_store are put here first. */ | |
6492 | static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
6493 | static HARD_REG_SET reg_reloaded_died; | |
6494 | ||
8a99f6f9 R |
6495 | /* Check if *RELOAD_REG is suitable as an intermediate or scratch register |
6496 | of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg | |
6497 | is nonzero, if that is suitable. On success, change *RELOAD_REG to the | |
6498 | adjusted register, and return true. Otherwise, return false. */ | |
6499 | static bool | |
6500 | reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg, | |
6501 | enum reg_class new_class, | |
6502 | enum machine_mode new_mode) | |
6503 | ||
6504 | { | |
6505 | rtx reg; | |
6506 | ||
6507 | for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0) | |
6508 | { | |
6509 | unsigned regno = REGNO (reg); | |
6510 | ||
6511 | if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno)) | |
6512 | continue; | |
6513 | if (GET_MODE (reg) != new_mode) | |
6514 | { | |
6515 | if (!HARD_REGNO_MODE_OK (regno, new_mode)) | |
6516 | continue; | |
6517 | if (hard_regno_nregs[regno][new_mode] | |
6518 | > hard_regno_nregs[regno][GET_MODE (reg)]) | |
6519 | continue; | |
6520 | reg = reload_adjust_reg_for_mode (reg, new_mode); | |
6521 | } | |
6522 | *reload_reg = reg; | |
6523 | return true; | |
6524 | } | |
6525 | return false; | |
6526 | } | |
6527 | ||
6528 | /* Check if *RELOAD_REG is suitable as a scratch register for the reload | |
6529 | pattern with insn_code ICODE, or alternatively, if alt_reload_reg is | |
6530 | nonzero, if that is suitable. On success, change *RELOAD_REG to the | |
6531 | adjusted register, and return true. Otherwise, return false. */ | |
6532 | static bool | |
6533 | reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg, | |
6534 | enum insn_code icode) | |
6535 | ||
6536 | { | |
6537 | enum reg_class new_class = scratch_reload_class (icode); | |
6538 | enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode; | |
6539 | ||
6540 | return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg, | |
6541 | new_class, new_mode); | |
6542 | } | |
6543 | ||
367b1cf5 BS |
6544 | /* Generate insns to perform reload RL, which is for the insn in CHAIN and |
6545 | has the number J. OLD contains the value to be used as input. */ | |
770ae6cc | 6546 | |
32131a9c | 6547 | static void |
0c20a65f AJ |
6548 | emit_input_reload_insns (struct insn_chain *chain, struct reload *rl, |
6549 | rtx old, int j) | |
32131a9c | 6550 | { |
7609e720 | 6551 | rtx insn = chain->insn; |
b3694847 | 6552 | rtx reloadreg = rl->reg_rtx; |
367b1cf5 BS |
6553 | rtx oldequiv_reg = 0; |
6554 | rtx oldequiv = 0; | |
6555 | int special = 0; | |
6556 | enum machine_mode mode; | |
6557 | rtx *where; | |
6558 | ||
6559 | /* Determine the mode to reload in. | |
6560 | This is very tricky because we have three to choose from. | |
6561 | There is the mode the insn operand wants (rl->inmode). | |
6562 | There is the mode of the reload register RELOADREG. | |
6563 | There is the intrinsic mode of the operand, which we could find | |
6564 | by stripping some SUBREGs. | |
6565 | It turns out that RELOADREG's mode is irrelevant: | |
6566 | we can change that arbitrarily. | |
6567 | ||
6568 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
6569 | then the reload reg may not support QImode moves, so use SImode. | |
6570 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
6571 | because the QImode value is in the least significant part of a | |
6572 | slot big enough for a SImode. If foo is some other sort of | |
6573 | memory reference, then it is impossible to reload this case, | |
6574 | so previous passes had better make sure this never happens. | |
6575 | ||
6576 | Then consider a one-word union which has SImode and one of its | |
6577 | members is a float, being fetched as (SUBREG:SF union:SI). | |
6578 | We must fetch that as SFmode because we could be loading into | |
6579 | a float-only register. In this case OLD's mode is correct. | |
6580 | ||
6581 | Consider an immediate integer: it has VOIDmode. Here we need | |
6582 | to get a mode from something else. | |
6583 | ||
6584 | In some cases, there is a fourth mode, the operand's | |
6585 | containing mode. If the insn specifies a containing mode for | |
6586 | this operand, it overrides all others. | |
6587 | ||
6588 | I am not sure whether the algorithm here is always right, | |
6589 | but it does the right things in those cases. */ | |
6590 | ||
6591 | mode = GET_MODE (old); | |
6592 | if (mode == VOIDmode) | |
6593 | mode = rl->inmode; | |
7609e720 | 6594 | |
367b1cf5 BS |
6595 | /* delete_output_reload is only invoked properly if old contains |
6596 | the original pseudo register. Since this is replaced with a | |
6597 | hard reg when RELOAD_OVERRIDE_IN is set, see if we can | |
6598 | find the pseudo in RELOAD_IN_REG. */ | |
75803b85 | 6599 | if (reload_override_in[j] |
f8cfc6aa | 6600 | && REG_P (rl->in_reg)) |
367b1cf5 BS |
6601 | { |
6602 | oldequiv = old; | |
6603 | old = rl->in_reg; | |
6604 | } | |
6605 | if (oldequiv == 0) | |
6606 | oldequiv = old; | |
f8cfc6aa | 6607 | else if (REG_P (oldequiv)) |
367b1cf5 BS |
6608 | oldequiv_reg = oldequiv; |
6609 | else if (GET_CODE (oldequiv) == SUBREG) | |
6610 | oldequiv_reg = SUBREG_REG (oldequiv); | |
6611 | ||
6612 | /* If we are reloading from a register that was recently stored in | |
6613 | with an output-reload, see if we can prove there was | |
6614 | actually no need to store the old value in it. */ | |
6615 | ||
f8cfc6aa | 6616 | if (optimize && REG_P (oldequiv) |
367b1cf5 BS |
6617 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER |
6618 | && spill_reg_store[REGNO (oldequiv)] | |
f8cfc6aa | 6619 | && REG_P (old) |
367b1cf5 BS |
6620 | && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) |
6621 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6622 | rl->out_reg))) | |
6623 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6624 | ||
6625 | /* Encapsulate both RELOADREG and OLDEQUIV into that mode, | |
6626 | then load RELOADREG from OLDEQUIV. Note that we cannot use | |
6627 | gen_lowpart_common since it can do the wrong thing when | |
6628 | RELOADREG has a multi-word mode. Note that RELOADREG | |
6629 | must always be a REG here. */ | |
6630 | ||
6631 | if (GET_MODE (reloadreg) != mode) | |
f12448c8 | 6632 | reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); |
367b1cf5 BS |
6633 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) |
6634 | oldequiv = SUBREG_REG (oldequiv); | |
6635 | if (GET_MODE (oldequiv) != VOIDmode | |
6636 | && mode != GET_MODE (oldequiv)) | |
ddef6bc7 | 6637 | oldequiv = gen_lowpart_SUBREG (mode, oldequiv); |
367b1cf5 BS |
6638 | |
6639 | /* Switch to the right place to emit the reload insns. */ | |
6640 | switch (rl->when_needed) | |
6641 | { | |
6642 | case RELOAD_OTHER: | |
6643 | where = &other_input_reload_insns; | |
6644 | break; | |
6645 | case RELOAD_FOR_INPUT: | |
6646 | where = &input_reload_insns[rl->opnum]; | |
6647 | break; | |
6648 | case RELOAD_FOR_INPUT_ADDRESS: | |
6649 | where = &input_address_reload_insns[rl->opnum]; | |
6650 | break; | |
6651 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6652 | where = &inpaddr_address_reload_insns[rl->opnum]; | |
6653 | break; | |
6654 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
6655 | where = &output_address_reload_insns[rl->opnum]; | |
6656 | break; | |
6657 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
6658 | where = &outaddr_address_reload_insns[rl->opnum]; | |
6659 | break; | |
6660 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6661 | where = &operand_reload_insns; | |
6662 | break; | |
6663 | case RELOAD_FOR_OPADDR_ADDR: | |
6664 | where = &other_operand_reload_insns; | |
6665 | break; | |
6666 | case RELOAD_FOR_OTHER_ADDRESS: | |
6667 | where = &other_input_address_reload_insns; | |
6668 | break; | |
6669 | default: | |
41374e13 | 6670 | gcc_unreachable (); |
367b1cf5 | 6671 | } |
546b63fb | 6672 | |
367b1cf5 | 6673 | push_to_sequence (*where); |
32131a9c | 6674 | |
367b1cf5 BS |
6675 | /* Auto-increment addresses must be reloaded in a special way. */ |
6676 | if (rl->out && ! rl->out_reg) | |
32131a9c | 6677 | { |
367b1cf5 BS |
6678 | /* We are not going to bother supporting the case where a |
6679 | incremented register can't be copied directly from | |
6680 | OLDEQUIV since this seems highly unlikely. */ | |
41374e13 | 6681 | gcc_assert (rl->secondary_in_reload < 0); |
32131a9c | 6682 | |
367b1cf5 BS |
6683 | if (reload_inherited[j]) |
6684 | oldequiv = reloadreg; | |
cb2afeb3 | 6685 | |
367b1cf5 | 6686 | old = XEXP (rl->in_reg, 0); |
32131a9c | 6687 | |
f8cfc6aa | 6688 | if (optimize && REG_P (oldequiv) |
367b1cf5 BS |
6689 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER |
6690 | && spill_reg_store[REGNO (oldequiv)] | |
f8cfc6aa | 6691 | && REG_P (old) |
367b1cf5 BS |
6692 | && (dead_or_set_p (insn, |
6693 | spill_reg_stored_to[REGNO (oldequiv)]) | |
6694 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6695 | old))) | |
6696 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6697 | ||
6698 | /* Prevent normal processing of this reload. */ | |
6699 | special = 1; | |
6700 | /* Output a special code sequence for this case. */ | |
6701 | new_spill_reg_store[REGNO (reloadreg)] | |
6702 | = inc_for_reload (reloadreg, oldequiv, rl->out, | |
6703 | rl->inc); | |
6704 | } | |
32131a9c | 6705 | |
367b1cf5 BS |
6706 | /* If we are reloading a pseudo-register that was set by the previous |
6707 | insn, see if we can get rid of that pseudo-register entirely | |
6708 | by redirecting the previous insn into our reload register. */ | |
6709 | ||
f8cfc6aa | 6710 | else if (optimize && REG_P (old) |
367b1cf5 BS |
6711 | && REGNO (old) >= FIRST_PSEUDO_REGISTER |
6712 | && dead_or_set_p (insn, old) | |
6713 | /* This is unsafe if some other reload | |
6714 | uses the same reg first. */ | |
ff6534ad | 6715 | && ! conflicts_with_override (reloadreg) |
c02cad8f BS |
6716 | && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum, |
6717 | rl->when_needed, old, rl->out, j, 0)) | |
367b1cf5 BS |
6718 | { |
6719 | rtx temp = PREV_INSN (insn); | |
4b4bf941 | 6720 | while (temp && NOTE_P (temp)) |
367b1cf5 BS |
6721 | temp = PREV_INSN (temp); |
6722 | if (temp | |
4b4bf941 | 6723 | && NONJUMP_INSN_P (temp) |
367b1cf5 BS |
6724 | && GET_CODE (PATTERN (temp)) == SET |
6725 | && SET_DEST (PATTERN (temp)) == old | |
6726 | /* Make sure we can access insn_operand_constraint. */ | |
6727 | && asm_noperands (PATTERN (temp)) < 0 | |
367b1cf5 BS |
6728 | /* This is unsafe if operand occurs more than once in current |
6729 | insn. Perhaps some occurrences aren't reloaded. */ | |
10d1bb36 | 6730 | && count_occurrences (PATTERN (insn), old, 0) == 1) |
367b1cf5 | 6731 | { |
10d1bb36 | 6732 | rtx old = SET_DEST (PATTERN (temp)); |
367b1cf5 BS |
6733 | /* Store into the reload register instead of the pseudo. */ |
6734 | SET_DEST (PATTERN (temp)) = reloadreg; | |
6735 | ||
10d1bb36 JH |
6736 | /* Verify that resulting insn is valid. */ |
6737 | extract_insn (temp); | |
6738 | if (constrain_operands (1)) | |
32131a9c | 6739 | { |
10d1bb36 JH |
6740 | /* If the previous insn is an output reload, the source is |
6741 | a reload register, and its spill_reg_store entry will | |
6742 | contain the previous destination. This is now | |
6743 | invalid. */ | |
f8cfc6aa | 6744 | if (REG_P (SET_SRC (PATTERN (temp))) |
10d1bb36 JH |
6745 | && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) |
6746 | { | |
6747 | spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
6748 | spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
6749 | } | |
32131a9c | 6750 | |
10d1bb36 JH |
6751 | /* If these are the only uses of the pseudo reg, |
6752 | pretend for GDB it lives in the reload reg we used. */ | |
6753 | if (REG_N_DEATHS (REGNO (old)) == 1 | |
6754 | && REG_N_SETS (REGNO (old)) == 1) | |
6755 | { | |
6756 | reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx); | |
6757 | alter_reg (REGNO (old), -1); | |
6758 | } | |
6759 | special = 1; | |
6760 | } | |
6761 | else | |
cb2afeb3 | 6762 | { |
10d1bb36 | 6763 | SET_DEST (PATTERN (temp)) = old; |
32131a9c | 6764 | } |
367b1cf5 BS |
6765 | } |
6766 | } | |
32131a9c | 6767 | |
367b1cf5 | 6768 | /* We can't do that, so output an insn to load RELOADREG. */ |
32131a9c | 6769 | |
367b1cf5 BS |
6770 | /* If we have a secondary reload, pick up the secondary register |
6771 | and icode, if any. If OLDEQUIV and OLD are different or | |
6772 | if this is an in-out reload, recompute whether or not we | |
6773 | still need a secondary register and what the icode should | |
6774 | be. If we still need a secondary register and the class or | |
6775 | icode is different, go back to reloading from OLD if using | |
6776 | OLDEQUIV means that we got the wrong type of register. We | |
6777 | cannot have different class or icode due to an in-out reload | |
6778 | because we don't make such reloads when both the input and | |
6779 | output need secondary reload registers. */ | |
6780 | ||
07875628 | 6781 | if (! special && rl->secondary_in_reload >= 0) |
367b1cf5 BS |
6782 | { |
6783 | rtx second_reload_reg = 0; | |
8a99f6f9 | 6784 | rtx third_reload_reg = 0; |
367b1cf5 BS |
6785 | int secondary_reload = rl->secondary_in_reload; |
6786 | rtx real_oldequiv = oldequiv; | |
6787 | rtx real_old = old; | |
6788 | rtx tmp; | |
6789 | enum insn_code icode; | |
8a99f6f9 | 6790 | enum insn_code tertiary_icode = CODE_FOR_nothing; |
367b1cf5 BS |
6791 | |
6792 | /* If OLDEQUIV is a pseudo with a MEM, get the real MEM | |
6793 | and similarly for OLD. | |
6794 | See comments in get_secondary_reload in reload.c. */ | |
6795 | /* If it is a pseudo that cannot be replaced with its | |
6796 | equivalent MEM, we must fall back to reload_in, which | |
6797 | will have all the necessary substitutions registered. | |
6798 | Likewise for a pseudo that can't be replaced with its | |
6799 | equivalent constant. | |
6800 | ||
6801 | Take extra care for subregs of such pseudos. Note that | |
6802 | we cannot use reg_equiv_mem in this case because it is | |
6803 | not in the right mode. */ | |
6804 | ||
6805 | tmp = oldequiv; | |
6806 | if (GET_CODE (tmp) == SUBREG) | |
6807 | tmp = SUBREG_REG (tmp); | |
f8cfc6aa | 6808 | if (REG_P (tmp) |
367b1cf5 BS |
6809 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER |
6810 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6811 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6812 | { | |
6813 | if (! reg_equiv_mem[REGNO (tmp)] | |
6814 | || num_not_at_initial_offset | |
6815 | || GET_CODE (oldequiv) == SUBREG) | |
6816 | real_oldequiv = rl->in; | |
6817 | else | |
6818 | real_oldequiv = reg_equiv_mem[REGNO (tmp)]; | |
6819 | } | |
32131a9c | 6820 | |
367b1cf5 BS |
6821 | tmp = old; |
6822 | if (GET_CODE (tmp) == SUBREG) | |
6823 | tmp = SUBREG_REG (tmp); | |
f8cfc6aa | 6824 | if (REG_P (tmp) |
367b1cf5 BS |
6825 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER |
6826 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6827 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6828 | { | |
6829 | if (! reg_equiv_mem[REGNO (tmp)] | |
6830 | || num_not_at_initial_offset | |
6831 | || GET_CODE (old) == SUBREG) | |
6832 | real_old = rl->in; | |
6833 | else | |
6834 | real_old = reg_equiv_mem[REGNO (tmp)]; | |
6835 | } | |
6836 | ||
6837 | second_reload_reg = rld[secondary_reload].reg_rtx; | |
8a99f6f9 R |
6838 | if (rld[secondary_reload].secondary_in_reload >= 0) |
6839 | { | |
6840 | int tertiary_reload = rld[secondary_reload].secondary_in_reload; | |
6841 | ||
6842 | third_reload_reg = rld[tertiary_reload].reg_rtx; | |
6843 | tertiary_icode = rld[secondary_reload].secondary_in_icode; | |
6844 | /* We'd have to add more code for quartary reloads. */ | |
6845 | gcc_assert (rld[tertiary_reload].secondary_in_reload < 0); | |
6846 | } | |
367b1cf5 BS |
6847 | icode = rl->secondary_in_icode; |
6848 | ||
6849 | if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) | |
6850 | || (rl->in != 0 && rl->out != 0)) | |
6851 | { | |
8a99f6f9 R |
6852 | secondary_reload_info sri, sri2; |
6853 | enum reg_class new_class, new_t_class; | |
367b1cf5 | 6854 | |
8a99f6f9 R |
6855 | sri.icode = CODE_FOR_nothing; |
6856 | sri.prev_sri = NULL; | |
6857 | new_class = targetm.secondary_reload (1, real_oldequiv, rl->class, | |
6858 | mode, &sri); | |
6859 | ||
6860 | if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
367b1cf5 | 6861 | second_reload_reg = 0; |
8a99f6f9 | 6862 | else if (new_class == NO_REGS) |
32131a9c | 6863 | { |
8a99f6f9 R |
6864 | if (reload_adjust_reg_for_icode (&second_reload_reg, |
6865 | third_reload_reg, sri.icode)) | |
6866 | icode = sri.icode, third_reload_reg = 0; | |
367b1cf5 | 6867 | else |
8a99f6f9 R |
6868 | oldequiv = old, real_oldequiv = real_old; |
6869 | } | |
6870 | else if (sri.icode != CODE_FOR_nothing) | |
6871 | /* We currently lack a way to express this in reloads. */ | |
6872 | gcc_unreachable (); | |
6873 | else | |
6874 | { | |
6875 | sri2.icode = CODE_FOR_nothing; | |
6876 | sri2.prev_sri = &sri; | |
6877 | new_t_class = targetm.secondary_reload (1, real_oldequiv, | |
6878 | new_class, mode, &sri); | |
6879 | if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing) | |
32131a9c | 6880 | { |
8a99f6f9 R |
6881 | if (reload_adjust_reg_for_temp (&second_reload_reg, |
6882 | third_reload_reg, | |
6883 | new_class, mode)) | |
6884 | third_reload_reg = 0, tertiary_icode = sri2.icode; | |
367b1cf5 | 6885 | else |
8a99f6f9 R |
6886 | oldequiv = old, real_oldequiv = real_old; |
6887 | } | |
6888 | else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing) | |
6889 | { | |
6890 | rtx intermediate = second_reload_reg; | |
d30e8ef0 | 6891 | |
8a99f6f9 R |
6892 | if (reload_adjust_reg_for_temp (&intermediate, NULL, |
6893 | new_class, mode) | |
6894 | && reload_adjust_reg_for_icode (&third_reload_reg, NULL, | |
6895 | sri2.icode)) | |
32131a9c | 6896 | { |
8a99f6f9 R |
6897 | second_reload_reg = intermediate; |
6898 | tertiary_icode = sri2.icode; | |
6899 | } | |
6900 | else | |
6901 | oldequiv = old, real_oldequiv = real_old; | |
6902 | } | |
6903 | else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing) | |
6904 | { | |
6905 | rtx intermediate = second_reload_reg; | |
6906 | ||
6907 | if (reload_adjust_reg_for_temp (&intermediate, NULL, | |
6908 | new_class, mode) | |
6909 | && reload_adjust_reg_for_temp (&third_reload_reg, NULL, | |
6910 | new_t_class, mode)) | |
6911 | { | |
6912 | second_reload_reg = intermediate; | |
6913 | tertiary_icode = sri2.icode; | |
32131a9c | 6914 | } |
8a99f6f9 R |
6915 | else |
6916 | oldequiv = old, real_oldequiv = real_old; | |
32131a9c | 6917 | } |
8a99f6f9 R |
6918 | else |
6919 | /* This could be handled more intelligently too. */ | |
6920 | oldequiv = old, real_oldequiv = real_old; | |
32131a9c | 6921 | } |
367b1cf5 | 6922 | } |
32131a9c | 6923 | |
367b1cf5 BS |
6924 | /* If we still need a secondary reload register, check |
6925 | to see if it is being used as a scratch or intermediate | |
6926 | register and generate code appropriately. If we need | |
6927 | a scratch register, use REAL_OLDEQUIV since the form of | |
6928 | the insn may depend on the actual address if it is | |
6929 | a MEM. */ | |
546b63fb | 6930 | |
367b1cf5 BS |
6931 | if (second_reload_reg) |
6932 | { | |
6933 | if (icode != CODE_FOR_nothing) | |
32131a9c | 6934 | { |
8a99f6f9 R |
6935 | /* We'd have to add extra code to handle this case. */ |
6936 | gcc_assert (!third_reload_reg); | |
6937 | ||
367b1cf5 BS |
6938 | emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, |
6939 | second_reload_reg)); | |
07875628 | 6940 | special = 1; |
367b1cf5 BS |
6941 | } |
6942 | else | |
6943 | { | |
6944 | /* See if we need a scratch register to load the | |
6945 | intermediate register (a tertiary reload). */ | |
367b1cf5 BS |
6946 | if (tertiary_icode != CODE_FOR_nothing) |
6947 | { | |
367b1cf5 BS |
6948 | emit_insn ((GEN_FCN (tertiary_icode) |
6949 | (second_reload_reg, real_oldequiv, | |
6950 | third_reload_reg))); | |
6951 | } | |
8a99f6f9 R |
6952 | else if (third_reload_reg) |
6953 | { | |
6954 | gen_reload (third_reload_reg, real_oldequiv, | |
6955 | rl->opnum, | |
6956 | rl->when_needed); | |
6957 | gen_reload (second_reload_reg, third_reload_reg, | |
6958 | rl->opnum, | |
6959 | rl->when_needed); | |
6960 | } | |
367b1cf5 BS |
6961 | else |
6962 | gen_reload (second_reload_reg, real_oldequiv, | |
6963 | rl->opnum, | |
6964 | rl->when_needed); | |
32131a9c | 6965 | |
367b1cf5 BS |
6966 | oldequiv = second_reload_reg; |
6967 | } | |
6968 | } | |
6969 | } | |
32131a9c | 6970 | |
07875628 | 6971 | if (! special && ! rtx_equal_p (reloadreg, oldequiv)) |
367b1cf5 BS |
6972 | { |
6973 | rtx real_oldequiv = oldequiv; | |
6974 | ||
f8cfc6aa | 6975 | if ((REG_P (oldequiv) |
367b1cf5 BS |
6976 | && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER |
6977 | && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 | |
6978 | || reg_equiv_constant[REGNO (oldequiv)] != 0)) | |
6979 | || (GET_CODE (oldequiv) == SUBREG | |
f8cfc6aa | 6980 | && REG_P (SUBREG_REG (oldequiv)) |
367b1cf5 BS |
6981 | && (REGNO (SUBREG_REG (oldequiv)) |
6982 | >= FIRST_PSEUDO_REGISTER) | |
6983 | && ((reg_equiv_memory_loc | |
6984 | [REGNO (SUBREG_REG (oldequiv))] != 0) | |
6985 | || (reg_equiv_constant | |
716120a7 JJ |
6986 | [REGNO (SUBREG_REG (oldequiv))] != 0))) |
6987 | || (CONSTANT_P (oldequiv) | |
019d2e99 AS |
6988 | && (PREFERRED_RELOAD_CLASS (oldequiv, |
6989 | REGNO_REG_CLASS (REGNO (reloadreg))) | |
6990 | == NO_REGS))) | |
367b1cf5 BS |
6991 | real_oldequiv = rl->in; |
6992 | gen_reload (reloadreg, real_oldequiv, rl->opnum, | |
6993 | rl->when_needed); | |
6994 | } | |
32131a9c | 6995 | |
94bd63e5 AH |
6996 | if (flag_non_call_exceptions) |
6997 | copy_eh_notes (insn, get_insns ()); | |
6998 | ||
367b1cf5 BS |
6999 | /* End this sequence. */ |
7000 | *where = get_insns (); | |
7001 | end_sequence (); | |
a6a2274a | 7002 | |
367b1cf5 BS |
7003 | /* Update reload_override_in so that delete_address_reloads_1 |
7004 | can see the actual register usage. */ | |
7005 | if (oldequiv_reg) | |
7006 | reload_override_in[j] = oldequiv; | |
7007 | } | |
32131a9c | 7008 | |
367b1cf5 BS |
7009 | /* Generate insns to for the output reload RL, which is for the insn described |
7010 | by CHAIN and has the number J. */ | |
7011 | static void | |
0c20a65f AJ |
7012 | emit_output_reload_insns (struct insn_chain *chain, struct reload *rl, |
7013 | int j) | |
367b1cf5 BS |
7014 | { |
7015 | rtx reloadreg = rl->reg_rtx; | |
7016 | rtx insn = chain->insn; | |
7017 | int special = 0; | |
7018 | rtx old = rl->out; | |
7019 | enum machine_mode mode = GET_MODE (old); | |
7020 | rtx p; | |
32131a9c | 7021 | |
367b1cf5 BS |
7022 | if (rl->when_needed == RELOAD_OTHER) |
7023 | start_sequence (); | |
7024 | else | |
7025 | push_to_sequence (output_reload_insns[rl->opnum]); | |
32131a9c | 7026 | |
367b1cf5 BS |
7027 | /* Determine the mode to reload in. |
7028 | See comments above (for input reloading). */ | |
32131a9c | 7029 | |
367b1cf5 BS |
7030 | if (mode == VOIDmode) |
7031 | { | |
7032 | /* VOIDmode should never happen for an output. */ | |
7033 | if (asm_noperands (PATTERN (insn)) < 0) | |
7034 | /* It's the compiler's fault. */ | |
7035 | fatal_insn ("VOIDmode on an output", insn); | |
971801ff | 7036 | error_for_asm (insn, "output operand is constant in %<asm%>"); |
367b1cf5 BS |
7037 | /* Prevent crash--use something we know is valid. */ |
7038 | mode = word_mode; | |
7039 | old = gen_rtx_REG (mode, REGNO (reloadreg)); | |
7040 | } | |
546b63fb | 7041 | |
367b1cf5 | 7042 | if (GET_MODE (reloadreg) != mode) |
f12448c8 | 7043 | reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); |
32131a9c | 7044 | |
367b1cf5 BS |
7045 | /* If we need two reload regs, set RELOADREG to the intermediate |
7046 | one, since it will be stored into OLD. We might need a secondary | |
7047 | register only for an input reload, so check again here. */ | |
32131a9c | 7048 | |
367b1cf5 BS |
7049 | if (rl->secondary_out_reload >= 0) |
7050 | { | |
7051 | rtx real_old = old; | |
8a99f6f9 R |
7052 | int secondary_reload = rl->secondary_out_reload; |
7053 | int tertiary_reload = rld[secondary_reload].secondary_out_reload; | |
cb2afeb3 | 7054 | |
f8cfc6aa | 7055 | if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER |
367b1cf5 BS |
7056 | && reg_equiv_mem[REGNO (old)] != 0) |
7057 | real_old = reg_equiv_mem[REGNO (old)]; | |
32131a9c | 7058 | |
8a99f6f9 | 7059 | if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS) |
b60a8416 | 7060 | { |
367b1cf5 | 7061 | rtx second_reloadreg = reloadreg; |
8a99f6f9 | 7062 | reloadreg = rld[secondary_reload].reg_rtx; |
32131a9c | 7063 | |
367b1cf5 BS |
7064 | /* See if RELOADREG is to be used as a scratch register |
7065 | or as an intermediate register. */ | |
7066 | if (rl->secondary_out_icode != CODE_FOR_nothing) | |
7067 | { | |
8a99f6f9 R |
7068 | /* We'd have to add extra code to handle this case. */ |
7069 | gcc_assert (tertiary_reload < 0); | |
7070 | ||
367b1cf5 BS |
7071 | emit_insn ((GEN_FCN (rl->secondary_out_icode) |
7072 | (real_old, second_reloadreg, reloadreg))); | |
7073 | special = 1; | |
7074 | } | |
7075 | else | |
7076 | { | |
7077 | /* See if we need both a scratch and intermediate reload | |
7078 | register. */ | |
32131a9c | 7079 | |
367b1cf5 BS |
7080 | enum insn_code tertiary_icode |
7081 | = rld[secondary_reload].secondary_out_icode; | |
32131a9c | 7082 | |
8a99f6f9 R |
7083 | /* We'd have to add more code for quartary reloads. */ |
7084 | gcc_assert (tertiary_reload < 0 | |
7085 | || rld[tertiary_reload].secondary_out_reload < 0); | |
7086 | ||
367b1cf5 | 7087 | if (GET_MODE (reloadreg) != mode) |
f12448c8 | 7088 | reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); |
cb2afeb3 | 7089 | |
367b1cf5 BS |
7090 | if (tertiary_icode != CODE_FOR_nothing) |
7091 | { | |
8a99f6f9 | 7092 | rtx third_reloadreg = rld[tertiary_reload].reg_rtx; |
367b1cf5 BS |
7093 | rtx tem; |
7094 | ||
7095 | /* Copy primary reload reg to secondary reload reg. | |
7096 | (Note that these have been swapped above, then | |
78adc5a0 | 7097 | secondary reload reg to OLD using our insn.) */ |
367b1cf5 BS |
7098 | |
7099 | /* If REAL_OLD is a paradoxical SUBREG, remove it | |
7100 | and try to put the opposite SUBREG on | |
7101 | RELOADREG. */ | |
7102 | if (GET_CODE (real_old) == SUBREG | |
7103 | && (GET_MODE_SIZE (GET_MODE (real_old)) | |
7104 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) | |
7105 | && 0 != (tem = gen_lowpart_common | |
7106 | (GET_MODE (SUBREG_REG (real_old)), | |
7107 | reloadreg))) | |
7108 | real_old = SUBREG_REG (real_old), reloadreg = tem; | |
7109 | ||
7110 | gen_reload (reloadreg, second_reloadreg, | |
7111 | rl->opnum, rl->when_needed); | |
7112 | emit_insn ((GEN_FCN (tertiary_icode) | |
7113 | (real_old, reloadreg, third_reloadreg))); | |
7114 | special = 1; | |
7115 | } | |
05d10675 | 7116 | |
367b1cf5 | 7117 | else |
8a99f6f9 R |
7118 | { |
7119 | /* Copy between the reload regs here and then to | |
7120 | OUT later. */ | |
7121 | ||
7122 | gen_reload (reloadreg, second_reloadreg, | |
7123 | rl->opnum, rl->when_needed); | |
7124 | if (tertiary_reload >= 0) | |
7125 | { | |
7126 | rtx third_reloadreg = rld[tertiary_reload].reg_rtx; | |
cb2afeb3 | 7127 | |
8a99f6f9 R |
7128 | gen_reload (third_reloadreg, reloadreg, |
7129 | rl->opnum, rl->when_needed); | |
7130 | reloadreg = third_reloadreg; | |
7131 | } | |
7132 | } | |
a7911cd2 | 7133 | } |
367b1cf5 BS |
7134 | } |
7135 | } | |
32131a9c | 7136 | |
367b1cf5 BS |
7137 | /* Output the last reload insn. */ |
7138 | if (! special) | |
7139 | { | |
7140 | rtx set; | |
7141 | ||
7142 | /* Don't output the last reload if OLD is not the dest of | |
1d7254c5 | 7143 | INSN and is in the src and is clobbered by INSN. */ |
367b1cf5 | 7144 | if (! flag_expensive_optimizations |
f8cfc6aa | 7145 | || !REG_P (old) |
367b1cf5 BS |
7146 | || !(set = single_set (insn)) |
7147 | || rtx_equal_p (old, SET_DEST (set)) | |
7148 | || !reg_mentioned_p (old, SET_SRC (set)) | |
2ca39620 KK |
7149 | || !((REGNO (old) < FIRST_PSEUDO_REGISTER) |
7150 | && regno_clobbered_p (REGNO (old), insn, rl->mode, 0))) | |
367b1cf5 BS |
7151 | gen_reload (old, reloadreg, rl->opnum, |
7152 | rl->when_needed); | |
7153 | } | |
32131a9c | 7154 | |
367b1cf5 BS |
7155 | /* Look at all insns we emitted, just to be safe. */ |
7156 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2c3c49de | 7157 | if (INSN_P (p)) |
367b1cf5 BS |
7158 | { |
7159 | rtx pat = PATTERN (p); | |
546b63fb | 7160 | |
367b1cf5 BS |
7161 | /* If this output reload doesn't come from a spill reg, |
7162 | clear any memory of reloaded copies of the pseudo reg. | |
7163 | If this output reload comes from a spill reg, | |
7164 | reg_has_output_reload will make this do nothing. */ | |
7165 | note_stores (pat, forget_old_reloads_1, NULL); | |
cb2afeb3 | 7166 | |
367b1cf5 BS |
7167 | if (reg_mentioned_p (rl->reg_rtx, pat)) |
7168 | { | |
7169 | rtx set = single_set (insn); | |
7170 | if (reload_spill_index[j] < 0 | |
7171 | && set | |
7172 | && SET_SRC (set) == rl->reg_rtx) | |
7173 | { | |
7174 | int src = REGNO (SET_SRC (set)); | |
32131a9c | 7175 | |
367b1cf5 BS |
7176 | reload_spill_index[j] = src; |
7177 | SET_HARD_REG_BIT (reg_is_output_reload, src); | |
7178 | if (find_regno_note (insn, REG_DEAD, src)) | |
7179 | SET_HARD_REG_BIT (reg_reloaded_died, src); | |
7180 | } | |
7181 | if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER) | |
7182 | { | |
7183 | int s = rl->secondary_out_reload; | |
7184 | set = single_set (p); | |
7185 | /* If this reload copies only to the secondary reload | |
7186 | register, the secondary reload does the actual | |
7187 | store. */ | |
7188 | if (s >= 0 && set == NULL_RTX) | |
1d7254c5 KH |
7189 | /* We can't tell what function the secondary reload |
7190 | has and where the actual store to the pseudo is | |
7191 | made; leave new_spill_reg_store alone. */ | |
7192 | ; | |
367b1cf5 BS |
7193 | else if (s >= 0 |
7194 | && SET_SRC (set) == rl->reg_rtx | |
7195 | && SET_DEST (set) == rld[s].reg_rtx) | |
7196 | { | |
7197 | /* Usually the next instruction will be the | |
7198 | secondary reload insn; if we can confirm | |
7199 | that it is, setting new_spill_reg_store to | |
7200 | that insn will allow an extra optimization. */ | |
7201 | rtx s_reg = rld[s].reg_rtx; | |
7202 | rtx next = NEXT_INSN (p); | |
7203 | rld[s].out = rl->out; | |
7204 | rld[s].out_reg = rl->out_reg; | |
7205 | set = single_set (next); | |
7206 | if (set && SET_SRC (set) == s_reg | |
7207 | && ! new_spill_reg_store[REGNO (s_reg)]) | |
7208 | { | |
7209 | SET_HARD_REG_BIT (reg_is_output_reload, | |
7210 | REGNO (s_reg)); | |
7211 | new_spill_reg_store[REGNO (s_reg)] = next; | |
7212 | } | |
7213 | } | |
7214 | else | |
7215 | new_spill_reg_store[REGNO (rl->reg_rtx)] = p; | |
7216 | } | |
7217 | } | |
7218 | } | |
32131a9c | 7219 | |
367b1cf5 BS |
7220 | if (rl->when_needed == RELOAD_OTHER) |
7221 | { | |
2f937369 | 7222 | emit_insn (other_output_reload_insns[rl->opnum]); |
367b1cf5 BS |
7223 | other_output_reload_insns[rl->opnum] = get_insns (); |
7224 | } | |
7225 | else | |
7226 | output_reload_insns[rl->opnum] = get_insns (); | |
32131a9c | 7227 | |
94bd63e5 AH |
7228 | if (flag_non_call_exceptions) |
7229 | copy_eh_notes (insn, get_insns ()); | |
7230 | ||
1d7254c5 | 7231 | end_sequence (); |
367b1cf5 | 7232 | } |
32131a9c | 7233 | |
367b1cf5 BS |
7234 | /* Do input reloading for reload RL, which is for the insn described by CHAIN |
7235 | and has the number J. */ | |
7236 | static void | |
0c20a65f | 7237 | do_input_reload (struct insn_chain *chain, struct reload *rl, int j) |
367b1cf5 | 7238 | { |
367b1cf5 | 7239 | rtx insn = chain->insn; |
3c0cb5de | 7240 | rtx old = (rl->in && MEM_P (rl->in) |
367b1cf5 BS |
7241 | ? rl->in_reg : rl->in); |
7242 | ||
7243 | if (old != 0 | |
7244 | /* AUTO_INC reloads need to be handled even if inherited. We got an | |
7245 | AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ | |
7246 | && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) | |
7247 | && ! rtx_equal_p (rl->reg_rtx, old) | |
7248 | && rl->reg_rtx != 0) | |
1d813780 | 7249 | emit_input_reload_insns (chain, rld + j, old, j); |
32131a9c | 7250 | |
367b1cf5 BS |
7251 | /* When inheriting a wider reload, we have a MEM in rl->in, |
7252 | e.g. inheriting a SImode output reload for | |
7253 | (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ | |
7254 | if (optimize && reload_inherited[j] && rl->in | |
3c0cb5de JQ |
7255 | && MEM_P (rl->in) |
7256 | && MEM_P (rl->in_reg) | |
367b1cf5 BS |
7257 | && reload_spill_index[j] >= 0 |
7258 | && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) | |
4977bab6 | 7259 | rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; |
32131a9c | 7260 | |
367b1cf5 BS |
7261 | /* If we are reloading a register that was recently stored in with an |
7262 | output-reload, see if we can prove there was | |
7263 | actually no need to store the old value in it. */ | |
32131a9c | 7264 | |
367b1cf5 BS |
7265 | if (optimize |
7266 | && (reload_inherited[j] || reload_override_in[j]) | |
7267 | && rl->reg_rtx | |
f8cfc6aa | 7268 | && REG_P (rl->reg_rtx) |
367b1cf5 BS |
7269 | && spill_reg_store[REGNO (rl->reg_rtx)] != 0 |
7270 | #if 0 | |
7271 | /* There doesn't seem to be any reason to restrict this to pseudos | |
7272 | and doing so loses in the case where we are copying from a | |
7273 | register of the wrong class. */ | |
7274 | && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
7275 | >= FIRST_PSEUDO_REGISTER) | |
7276 | #endif | |
7277 | /* The insn might have already some references to stackslots | |
7278 | replaced by MEMs, while reload_out_reg still names the | |
7279 | original pseudo. */ | |
7280 | && (dead_or_set_p (insn, | |
7281 | spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
7282 | || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], | |
7283 | rl->out_reg))) | |
7284 | delete_output_reload (insn, j, REGNO (rl->reg_rtx)); | |
7285 | } | |
32131a9c | 7286 | |
367b1cf5 BS |
7287 | /* Do output reloading for reload RL, which is for the insn described by |
7288 | CHAIN and has the number J. | |
7289 | ??? At some point we need to support handling output reloads of | |
7290 | JUMP_INSNs or insns that set cc0. */ | |
7291 | static void | |
0c20a65f | 7292 | do_output_reload (struct insn_chain *chain, struct reload *rl, int j) |
367b1cf5 BS |
7293 | { |
7294 | rtx note, old; | |
7295 | rtx insn = chain->insn; | |
7296 | /* If this is an output reload that stores something that is | |
7297 | not loaded in this same reload, see if we can eliminate a previous | |
7298 | store. */ | |
7299 | rtx pseudo = rl->out_reg; | |
7300 | ||
7301 | if (pseudo | |
159d5964 | 7302 | && optimize |
f8cfc6aa | 7303 | && REG_P (pseudo) |
367b1cf5 BS |
7304 | && ! rtx_equal_p (rl->in_reg, pseudo) |
7305 | && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER | |
7306 | && reg_last_reload_reg[REGNO (pseudo)]) | |
7307 | { | |
7308 | int pseudo_no = REGNO (pseudo); | |
7309 | int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); | |
7310 | ||
7311 | /* We don't need to test full validity of last_regno for | |
7312 | inherit here; we only want to know if the store actually | |
7313 | matches the pseudo. */ | |
60ef417d GK |
7314 | if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno) |
7315 | && reg_reloaded_contents[last_regno] == pseudo_no | |
367b1cf5 BS |
7316 | && spill_reg_store[last_regno] |
7317 | && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) | |
7318 | delete_output_reload (insn, j, last_regno); | |
7319 | } | |
5e03c156 | 7320 | |
367b1cf5 BS |
7321 | old = rl->out_reg; |
7322 | if (old == 0 | |
7323 | || rl->reg_rtx == old | |
7324 | || rl->reg_rtx == 0) | |
7325 | return; | |
32131a9c | 7326 | |
367b1cf5 BS |
7327 | /* An output operand that dies right away does need a reload, |
7328 | but need not be copied from it. Show the new location in the | |
7329 | REG_UNUSED note. */ | |
f8cfc6aa | 7330 | if ((REG_P (old) || GET_CODE (old) == SCRATCH) |
367b1cf5 BS |
7331 | && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) |
7332 | { | |
7333 | XEXP (note, 0) = rl->reg_rtx; | |
7334 | return; | |
7335 | } | |
7336 | /* Likewise for a SUBREG of an operand that dies. */ | |
7337 | else if (GET_CODE (old) == SUBREG | |
f8cfc6aa | 7338 | && REG_P (SUBREG_REG (old)) |
367b1cf5 BS |
7339 | && 0 != (note = find_reg_note (insn, REG_UNUSED, |
7340 | SUBREG_REG (old)))) | |
7341 | { | |
7342 | XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), | |
7343 | rl->reg_rtx); | |
7344 | return; | |
7345 | } | |
7346 | else if (GET_CODE (old) == SCRATCH) | |
7347 | /* If we aren't optimizing, there won't be a REG_UNUSED note, | |
7348 | but we don't want to make an output reload. */ | |
7349 | return; | |
1554c2c6 | 7350 | |
367b1cf5 | 7351 | /* If is a JUMP_INSN, we can't support output reloads yet. */ |
ce99549f | 7352 | gcc_assert (NONJUMP_INSN_P (insn)); |
5e03c156 | 7353 | |
367b1cf5 BS |
7354 | emit_output_reload_insns (chain, rld + j, j); |
7355 | } | |
1554c2c6 | 7356 | |
b5ba341f RS |
7357 | /* Reload number R reloads from or to a group of hard registers starting at |
7358 | register REGNO. Return true if it can be treated for inheritance purposes | |
7359 | like a group of reloads, each one reloading a single hard register. | |
7360 | The caller has already checked that the spill register and REGNO use | |
7361 | the same number of registers to store the reload value. */ | |
7362 | ||
7363 | static bool | |
cf9c6ca5 | 7364 | inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED) |
b5ba341f RS |
7365 | { |
7366 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
7367 | return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r], | |
7368 | GET_MODE (rld[r].reg_rtx), | |
7369 | reg_raw_mode[reload_spill_index[r]]) | |
7370 | && !REG_CANNOT_CHANGE_MODE_P (regno, | |
7371 | GET_MODE (rld[r].reg_rtx), | |
7372 | reg_raw_mode[regno])); | |
7373 | #else | |
7374 | return true; | |
7375 | #endif | |
7376 | } | |
7377 | ||
367b1cf5 | 7378 | /* Output insns to reload values in and out of the chosen reload regs. */ |
32131a9c | 7379 | |
367b1cf5 | 7380 | static void |
0c20a65f | 7381 | emit_reload_insns (struct insn_chain *chain) |
367b1cf5 BS |
7382 | { |
7383 | rtx insn = chain->insn; | |
32131a9c | 7384 | |
b3694847 | 7385 | int j; |
e6e52be0 | 7386 | |
367b1cf5 | 7387 | CLEAR_HARD_REG_SET (reg_reloaded_died); |
e6e52be0 | 7388 | |
367b1cf5 BS |
7389 | for (j = 0; j < reload_n_operands; j++) |
7390 | input_reload_insns[j] = input_address_reload_insns[j] | |
7391 | = inpaddr_address_reload_insns[j] | |
7392 | = output_reload_insns[j] = output_address_reload_insns[j] | |
7393 | = outaddr_address_reload_insns[j] | |
7394 | = other_output_reload_insns[j] = 0; | |
7395 | other_input_address_reload_insns = 0; | |
7396 | other_input_reload_insns = 0; | |
7397 | operand_reload_insns = 0; | |
7398 | other_operand_reload_insns = 0; | |
32131a9c | 7399 | |
850aac53 | 7400 | /* Dump reloads into the dump file. */ |
c263766c | 7401 | if (dump_file) |
850aac53 | 7402 | { |
c263766c RH |
7403 | fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); |
7404 | debug_reload_to_stream (dump_file); | |
850aac53 JL |
7405 | } |
7406 | ||
367b1cf5 BS |
7407 | /* Now output the instructions to copy the data into and out of the |
7408 | reload registers. Do these in the order that the reloads were reported, | |
7409 | since reloads of base and index registers precede reloads of operands | |
7410 | and the operands may need the base and index registers reloaded. */ | |
32131a9c | 7411 | |
367b1cf5 BS |
7412 | for (j = 0; j < n_reloads; j++) |
7413 | { | |
7414 | if (rld[j].reg_rtx | |
7415 | && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER) | |
7416 | new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0; | |
d7e0324f | 7417 | |
367b1cf5 BS |
7418 | do_input_reload (chain, rld + j, j); |
7419 | do_output_reload (chain, rld + j, j); | |
32131a9c RK |
7420 | } |
7421 | ||
546b63fb RK |
7422 | /* Now write all the insns we made for reloads in the order expected by |
7423 | the allocation functions. Prior to the insn being reloaded, we write | |
7424 | the following reloads: | |
7425 | ||
7426 | RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. | |
7427 | ||
2edc8d65 | 7428 | RELOAD_OTHER reloads. |
546b63fb | 7429 | |
47c8cf91 ILT |
7430 | For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed |
7431 | by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the | |
7432 | RELOAD_FOR_INPUT reload for the operand. | |
546b63fb | 7433 | |
893bc853 RK |
7434 | RELOAD_FOR_OPADDR_ADDRS reloads. |
7435 | ||
546b63fb RK |
7436 | RELOAD_FOR_OPERAND_ADDRESS reloads. |
7437 | ||
7438 | After the insn being reloaded, we write the following: | |
7439 | ||
47c8cf91 ILT |
7440 | For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed |
7441 | by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the | |
7442 | RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output | |
7443 | reloads for the operand. The RELOAD_OTHER output reloads are | |
7444 | output in descending order by reload number. */ | |
546b63fb | 7445 | |
a7102479 JH |
7446 | emit_insn_before (other_input_address_reload_insns, insn); |
7447 | emit_insn_before (other_input_reload_insns, insn); | |
546b63fb RK |
7448 | |
7449 | for (j = 0; j < reload_n_operands; j++) | |
7450 | { | |
a7102479 JH |
7451 | emit_insn_before (inpaddr_address_reload_insns[j], insn); |
7452 | emit_insn_before (input_address_reload_insns[j], insn); | |
7453 | emit_insn_before (input_reload_insns[j], insn); | |
546b63fb RK |
7454 | } |
7455 | ||
a7102479 JH |
7456 | emit_insn_before (other_operand_reload_insns, insn); |
7457 | emit_insn_before (operand_reload_insns, insn); | |
546b63fb RK |
7458 | |
7459 | for (j = 0; j < reload_n_operands; j++) | |
7460 | { | |
a7102479 JH |
7461 | rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn); |
7462 | x = emit_insn_after (output_address_reload_insns[j], x); | |
7463 | x = emit_insn_after (output_reload_insns[j], x); | |
7464 | emit_insn_after (other_output_reload_insns[j], x); | |
546b63fb RK |
7465 | } |
7466 | ||
32131a9c RK |
7467 | /* For all the spill regs newly reloaded in this instruction, |
7468 | record what they were reloaded from, so subsequent instructions | |
d445b551 RK |
7469 | can inherit the reloads. |
7470 | ||
7471 | Update spill_reg_store for the reloads of this insn. | |
e9e79d69 | 7472 | Copy the elements that were updated in the loop above. */ |
32131a9c RK |
7473 | |
7474 | for (j = 0; j < n_reloads; j++) | |
7475 | { | |
b3694847 SS |
7476 | int r = reload_order[j]; |
7477 | int i = reload_spill_index[r]; | |
32131a9c | 7478 | |
78a2bc08 | 7479 | /* If this is a non-inherited input reload from a pseudo, we must |
05d10675 BS |
7480 | clear any memory of a previous store to the same pseudo. Only do |
7481 | something if there will not be an output reload for the pseudo | |
7482 | being reloaded. */ | |
eceef4c9 | 7483 | if (rld[r].in_reg != 0 |
05d10675 BS |
7484 | && ! (reload_inherited[r] || reload_override_in[r])) |
7485 | { | |
eceef4c9 | 7486 | rtx reg = rld[r].in_reg; |
78a2bc08 | 7487 | |
05d10675 | 7488 | if (GET_CODE (reg) == SUBREG) |
78a2bc08 | 7489 | reg = SUBREG_REG (reg); |
05d10675 | 7490 | |
f8cfc6aa | 7491 | if (REG_P (reg) |
78a2bc08 | 7492 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER |
2c61f5f1 | 7493 | && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg))) |
78a2bc08 R |
7494 | { |
7495 | int nregno = REGNO (reg); | |
7496 | ||
7497 | if (reg_last_reload_reg[nregno]) | |
05d10675 BS |
7498 | { |
7499 | int last_regno = REGNO (reg_last_reload_reg[nregno]); | |
78a2bc08 | 7500 | |
05d10675 | 7501 | if (reg_reloaded_contents[last_regno] == nregno) |
78a2bc08 | 7502 | spill_reg_store[last_regno] = 0; |
05d10675 | 7503 | } |
78a2bc08 R |
7504 | } |
7505 | } | |
05d10675 | 7506 | |
e6e52be0 | 7507 | /* I is nonneg if this reload used a register. |
eceef4c9 | 7508 | If rld[r].reg_rtx is 0, this is an optional reload |
51f0c3b7 | 7509 | that we opted to ignore. */ |
d445b551 | 7510 | |
eceef4c9 | 7511 | if (i >= 0 && rld[r].reg_rtx != 0) |
32131a9c | 7512 | { |
66fd46b6 | 7513 | int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)]; |
32131a9c | 7514 | int k; |
51f0c3b7 JW |
7515 | int part_reaches_end = 0; |
7516 | int all_reaches_end = 1; | |
32131a9c | 7517 | |
51f0c3b7 JW |
7518 | /* For a multi register reload, we need to check if all or part |
7519 | of the value lives to the end. */ | |
32131a9c RK |
7520 | for (k = 0; k < nr; k++) |
7521 | { | |
eceef4c9 BS |
7522 | if (reload_reg_reaches_end_p (i + k, rld[r].opnum, |
7523 | rld[r].when_needed)) | |
51f0c3b7 JW |
7524 | part_reaches_end = 1; |
7525 | else | |
7526 | all_reaches_end = 0; | |
32131a9c RK |
7527 | } |
7528 | ||
51f0c3b7 JW |
7529 | /* Ignore reloads that don't reach the end of the insn in |
7530 | entirety. */ | |
7531 | if (all_reaches_end) | |
32131a9c | 7532 | { |
51f0c3b7 JW |
7533 | /* First, clear out memory of what used to be in this spill reg. |
7534 | If consecutive registers are used, clear them all. */ | |
d08ea79f | 7535 | |
32131a9c | 7536 | for (k = 0; k < nr; k++) |
e3e9336f | 7537 | { |
e6e52be0 | 7538 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
e3e9336f DJ |
7539 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k); |
7540 | } | |
d08ea79f | 7541 | |
51f0c3b7 | 7542 | /* Maybe the spill reg contains a copy of reload_out. */ |
eceef4c9 | 7543 | if (rld[r].out != 0 |
f8cfc6aa | 7544 | && (REG_P (rld[r].out) |
cb2afeb3 | 7545 | #ifdef AUTO_INC_DEC |
eceef4c9 | 7546 | || ! rld[r].out_reg |
cb2afeb3 | 7547 | #endif |
f8cfc6aa | 7548 | || REG_P (rld[r].out_reg))) |
51f0c3b7 | 7549 | { |
f8cfc6aa | 7550 | rtx out = (REG_P (rld[r].out) |
eceef4c9 BS |
7551 | ? rld[r].out |
7552 | : rld[r].out_reg | |
7553 | ? rld[r].out_reg | |
7554 | /* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); | |
b3694847 | 7555 | int nregno = REGNO (out); |
51f0c3b7 | 7556 | int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
66fd46b6 JH |
7557 | : hard_regno_nregs[nregno] |
7558 | [GET_MODE (rld[r].reg_rtx)]); | |
b5ba341f | 7559 | bool piecemeal; |
51f0c3b7 JW |
7560 | |
7561 | spill_reg_store[i] = new_spill_reg_store[i]; | |
cb2afeb3 | 7562 | spill_reg_stored_to[i] = out; |
eceef4c9 | 7563 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 | 7564 | |
b5ba341f RS |
7565 | piecemeal = (nregno < FIRST_PSEUDO_REGISTER |
7566 | && nr == nnr | |
7567 | && inherit_piecemeal_p (r, nregno)); | |
7568 | ||
51f0c3b7 | 7569 | /* If NREGNO is a hard register, it may occupy more than |
05d10675 | 7570 | one register. If it does, say what is in the |
51f0c3b7 JW |
7571 | rest of the registers assuming that both registers |
7572 | agree on how many words the object takes. If not, | |
7573 | invalidate the subsequent registers. */ | |
7574 | ||
7575 | if (nregno < FIRST_PSEUDO_REGISTER) | |
7576 | for (k = 1; k < nnr; k++) | |
7577 | reg_last_reload_reg[nregno + k] | |
b5ba341f | 7578 | = (piecemeal |
39d31de8 | 7579 | ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k] |
51f0c3b7 JW |
7580 | : 0); |
7581 | ||
7582 | /* Now do the inverse operation. */ | |
7583 | for (k = 0; k < nr; k++) | |
7584 | { | |
e6e52be0 R |
7585 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7586 | reg_reloaded_contents[i + k] | |
b5ba341f | 7587 | = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal |
51f0c3b7 JW |
7588 | ? nregno |
7589 | : nregno + k); | |
e6e52be0 R |
7590 | reg_reloaded_insn[i + k] = insn; |
7591 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
e3e9336f DJ |
7592 | if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out))) |
7593 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k); | |
51f0c3b7 JW |
7594 | } |
7595 | } | |
d08ea79f | 7596 | |
51f0c3b7 JW |
7597 | /* Maybe the spill reg contains a copy of reload_in. Only do |
7598 | something if there will not be an output reload for | |
7599 | the register being reloaded. */ | |
eceef4c9 BS |
7600 | else if (rld[r].out_reg == 0 |
7601 | && rld[r].in != 0 | |
f8cfc6aa | 7602 | && ((REG_P (rld[r].in) |
eceef4c9 | 7603 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER |
2c61f5f1 | 7604 | && !REGNO_REG_SET_P (®_has_output_reload, |
1f6c68ed | 7605 | REGNO (rld[r].in))) |
f8cfc6aa | 7606 | || (REG_P (rld[r].in_reg) |
2c61f5f1 | 7607 | && !REGNO_REG_SET_P (®_has_output_reload, |
7ef701a8 | 7608 | REGNO (rld[r].in_reg)))) |
eceef4c9 | 7609 | && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn))) |
51f0c3b7 | 7610 | { |
b3694847 | 7611 | int nregno; |
51f0c3b7 | 7612 | int nnr; |
e3e9336f | 7613 | rtx in; |
b5ba341f | 7614 | bool piecemeal; |
d445b551 | 7615 | |
f8cfc6aa | 7616 | if (REG_P (rld[r].in) |
eceef4c9 | 7617 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) |
e3e9336f | 7618 | in = rld[r].in; |
f8cfc6aa | 7619 | else if (REG_P (rld[r].in_reg)) |
e3e9336f | 7620 | in = rld[r].in_reg; |
cb2afeb3 | 7621 | else |
e3e9336f DJ |
7622 | in = XEXP (rld[r].in_reg, 0); |
7623 | nregno = REGNO (in); | |
d08ea79f | 7624 | |
51f0c3b7 | 7625 | nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
66fd46b6 JH |
7626 | : hard_regno_nregs[nregno] |
7627 | [GET_MODE (rld[r].reg_rtx)]); | |
05d10675 | 7628 | |
eceef4c9 | 7629 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 | 7630 | |
b5ba341f RS |
7631 | piecemeal = (nregno < FIRST_PSEUDO_REGISTER |
7632 | && nr == nnr | |
7633 | && inherit_piecemeal_p (r, nregno)); | |
7634 | ||
51f0c3b7 JW |
7635 | if (nregno < FIRST_PSEUDO_REGISTER) |
7636 | for (k = 1; k < nnr; k++) | |
7637 | reg_last_reload_reg[nregno + k] | |
b5ba341f | 7638 | = (piecemeal |
39d31de8 | 7639 | ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k] |
51f0c3b7 JW |
7640 | : 0); |
7641 | ||
7642 | /* Unless we inherited this reload, show we haven't | |
cb2afeb3 R |
7643 | recently done a store. |
7644 | Previous stores of inherited auto_inc expressions | |
7645 | also have to be discarded. */ | |
7646 | if (! reload_inherited[r] | |
eceef4c9 | 7647 | || (rld[r].out && ! rld[r].out_reg)) |
51f0c3b7 JW |
7648 | spill_reg_store[i] = 0; |
7649 | ||
7650 | for (k = 0; k < nr; k++) | |
7651 | { | |
e6e52be0 R |
7652 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7653 | reg_reloaded_contents[i + k] | |
b5ba341f | 7654 | = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal |
51f0c3b7 JW |
7655 | ? nregno |
7656 | : nregno + k); | |
e6e52be0 R |
7657 | reg_reloaded_insn[i + k] = insn; |
7658 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
e3e9336f DJ |
7659 | if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in))) |
7660 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k); | |
51f0c3b7 JW |
7661 | } |
7662 | } | |
7663 | } | |
d445b551 | 7664 | |
51f0c3b7 JW |
7665 | /* However, if part of the reload reaches the end, then we must |
7666 | invalidate the old info for the part that survives to the end. */ | |
7667 | else if (part_reaches_end) | |
7668 | { | |
546b63fb | 7669 | for (k = 0; k < nr; k++) |
e6e52be0 | 7670 | if (reload_reg_reaches_end_p (i + k, |
eceef4c9 BS |
7671 | rld[r].opnum, |
7672 | rld[r].when_needed)) | |
e6e52be0 | 7673 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
32131a9c RK |
7674 | } |
7675 | } | |
7676 | ||
7677 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
7678 | It's reenabled in 1.35 because supposedly nothing else | |
7679 | deals with this problem. */ | |
7680 | ||
7681 | /* If a register gets output-reloaded from a non-spill register, | |
7682 | that invalidates any previous reloaded copy of it. | |
7683 | But forget_old_reloads_1 won't get to see it, because | |
b81ac288 PB |
7684 | it thinks only about the original insn. So invalidate it here. |
7685 | Also do the same thing for RELOAD_OTHER constraints where the | |
7686 | output is discarded. */ | |
7687 | if (i < 0 | |
7688 | && ((rld[r].out != 0 | |
7689 | && (REG_P (rld[r].out) | |
7690 | || (MEM_P (rld[r].out) | |
7691 | && REG_P (rld[r].out_reg)))) | |
7692 | || (rld[r].out == 0 && rld[r].out_reg | |
f8cfc6aa | 7693 | && REG_P (rld[r].out_reg)))) |
32131a9c | 7694 | { |
b81ac288 | 7695 | rtx out = ((rld[r].out && REG_P (rld[r].out)) |
eceef4c9 | 7696 | ? rld[r].out : rld[r].out_reg); |
b3694847 | 7697 | int nregno = REGNO (out); |
92d54592 RS |
7698 | |
7699 | /* REG_RTX is now set or clobbered by the main instruction. | |
7700 | As the comment above explains, forget_old_reloads_1 only | |
7701 | sees the original instruction, and there is no guarantee | |
7702 | that the original instruction also clobbered REG_RTX. | |
7703 | For example, if find_reloads sees that the input side of | |
7704 | a matched operand pair dies in this instruction, it may | |
7705 | use the input register as the reload register. | |
7706 | ||
7707 | Calling forget_old_reloads_1 is a waste of effort if | |
7708 | REG_RTX is also the output register. | |
7709 | ||
7710 | If we know that REG_RTX holds the value of a pseudo | |
7711 | register, the code after the call will record that fact. */ | |
7712 | if (rld[r].reg_rtx && rld[r].reg_rtx != out) | |
7713 | forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL); | |
7714 | ||
c7093272 | 7715 | if (nregno >= FIRST_PSEUDO_REGISTER) |
cb2afeb3 | 7716 | { |
6a651371 | 7717 | rtx src_reg, store_insn = NULL_RTX; |
cb2afeb3 R |
7718 | |
7719 | reg_last_reload_reg[nregno] = 0; | |
7720 | ||
7721 | /* If we can find a hard register that is stored, record | |
7722 | the storing insn so that we may delete this insn with | |
7723 | delete_output_reload. */ | |
eceef4c9 | 7724 | src_reg = rld[r].reg_rtx; |
cb2afeb3 R |
7725 | |
7726 | /* If this is an optional reload, try to find the source reg | |
7727 | from an input reload. */ | |
7728 | if (! src_reg) | |
7729 | { | |
7730 | rtx set = single_set (insn); | |
eceef4c9 | 7731 | if (set && SET_DEST (set) == rld[r].out) |
cb2afeb3 R |
7732 | { |
7733 | int k; | |
7734 | ||
7735 | src_reg = SET_SRC (set); | |
7736 | store_insn = insn; | |
7737 | for (k = 0; k < n_reloads; k++) | |
7738 | { | |
eceef4c9 | 7739 | if (rld[k].in == src_reg) |
cb2afeb3 | 7740 | { |
eceef4c9 | 7741 | src_reg = rld[k].reg_rtx; |
cb2afeb3 R |
7742 | break; |
7743 | } | |
7744 | } | |
7745 | } | |
7746 | } | |
7747 | else | |
7748 | store_insn = new_spill_reg_store[REGNO (src_reg)]; | |
f8cfc6aa | 7749 | if (src_reg && REG_P (src_reg) |
cb2afeb3 R |
7750 | && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) |
7751 | { | |
7752 | int src_regno = REGNO (src_reg); | |
66fd46b6 | 7753 | int nr = hard_regno_nregs[src_regno][rld[r].mode]; |
cb2afeb3 R |
7754 | /* The place where to find a death note varies with |
7755 | PRESERVE_DEATH_INFO_REGNO_P . The condition is not | |
7756 | necessarily checked exactly in the code that moves | |
7757 | notes, so just check both locations. */ | |
7758 | rtx note = find_regno_note (insn, REG_DEAD, src_regno); | |
1558b970 | 7759 | if (! note && store_insn) |
cb2afeb3 R |
7760 | note = find_regno_note (store_insn, REG_DEAD, src_regno); |
7761 | while (nr-- > 0) | |
7762 | { | |
7763 | spill_reg_store[src_regno + nr] = store_insn; | |
7764 | spill_reg_stored_to[src_regno + nr] = out; | |
7765 | reg_reloaded_contents[src_regno + nr] = nregno; | |
7766 | reg_reloaded_insn[src_regno + nr] = store_insn; | |
00f9f1bc | 7767 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr); |
cb2afeb3 | 7768 | SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr); |
e3e9336f DJ |
7769 | if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr, |
7770 | GET_MODE (src_reg))) | |
7771 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, | |
7772 | src_regno + nr); | |
cb2afeb3 R |
7773 | SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr); |
7774 | if (note) | |
7775 | SET_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7776 | else | |
7777 | CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7778 | } | |
7779 | reg_last_reload_reg[nregno] = src_reg; | |
9532c14f UW |
7780 | /* We have to set reg_has_output_reload here, or else |
7781 | forget_old_reloads_1 will clear reg_last_reload_reg | |
7782 | right away. */ | |
2c61f5f1 JH |
7783 | SET_REGNO_REG_SET (®_has_output_reload, |
7784 | nregno); | |
cb2afeb3 R |
7785 | } |
7786 | } | |
c7093272 RK |
7787 | else |
7788 | { | |
b81ac288 | 7789 | int num_regs = hard_regno_nregs[nregno][GET_MODE (out)]; |
36281332 | 7790 | |
c7093272 RK |
7791 | while (num_regs-- > 0) |
7792 | reg_last_reload_reg[nregno + num_regs] = 0; | |
7793 | } | |
32131a9c RK |
7794 | } |
7795 | } | |
e6e52be0 | 7796 | IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); |
32131a9c RK |
7797 | } |
7798 | \f | |
ff0d9879 HPN |
7799 | /* Go through the motions to emit INSN and test if it is strictly valid. |
7800 | Return the emitted insn if valid, else return NULL. */ | |
7801 | ||
7802 | static rtx | |
7803 | emit_insn_if_valid_for_reload (rtx insn) | |
7804 | { | |
7805 | rtx last = get_last_insn (); | |
7806 | int code; | |
7807 | ||
7808 | insn = emit_insn (insn); | |
7809 | code = recog_memoized (insn); | |
7810 | ||
7811 | if (code >= 0) | |
7812 | { | |
7813 | extract_insn (insn); | |
7814 | /* We want constrain operands to treat this insn strictly in its | |
7815 | validity determination, i.e., the way it would after reload has | |
7816 | completed. */ | |
7817 | if (constrain_operands (1)) | |
7818 | return insn; | |
7819 | } | |
7820 | ||
7821 | delete_insns_since (last); | |
7822 | return NULL; | |
7823 | } | |
7824 | ||
5e03c156 RK |
7825 | /* Emit code to perform a reload from IN (which may be a reload register) to |
7826 | OUT (which may also be a reload register). IN or OUT is from operand | |
05d10675 | 7827 | OPNUM with reload type TYPE. |
546b63fb | 7828 | |
3c3eeea6 | 7829 | Returns first insn emitted. */ |
32131a9c | 7830 | |
bf9a0db3 | 7831 | static rtx |
0c20a65f | 7832 | gen_reload (rtx out, rtx in, int opnum, enum reload_type type) |
32131a9c | 7833 | { |
546b63fb | 7834 | rtx last = get_last_insn (); |
7a5b18b0 RK |
7835 | rtx tem; |
7836 | ||
7837 | /* If IN is a paradoxical SUBREG, remove it and try to put the | |
7838 | opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ | |
7839 | if (GET_CODE (in) == SUBREG | |
7840 | && (GET_MODE_SIZE (GET_MODE (in)) | |
7841 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
7842 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) | |
7843 | in = SUBREG_REG (in), out = tem; | |
7844 | else if (GET_CODE (out) == SUBREG | |
eceef4c9 BS |
7845 | && (GET_MODE_SIZE (GET_MODE (out)) |
7846 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
7847 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) | |
7a5b18b0 | 7848 | out = SUBREG_REG (out), in = tem; |
32131a9c | 7849 | |
a8fdc208 | 7850 | /* How to do this reload can get quite tricky. Normally, we are being |
32131a9c RK |
7851 | asked to reload a simple operand, such as a MEM, a constant, or a pseudo |
7852 | register that didn't get a hard register. In that case we can just | |
7853 | call emit_move_insn. | |
7854 | ||
a7fd196c JW |
7855 | We can also be asked to reload a PLUS that adds a register or a MEM to |
7856 | another register, constant or MEM. This can occur during frame pointer | |
7857 | elimination and while reloading addresses. This case is handled by | |
7858 | trying to emit a single insn to perform the add. If it is not valid, | |
7859 | we use a two insn sequence. | |
32131a9c | 7860 | |
ff0d9879 HPN |
7861 | Or we can be asked to reload an unary operand that was a fragment of |
7862 | an addressing mode, into a register. If it isn't recognized as-is, | |
7863 | we try making the unop operand and the reload-register the same: | |
7864 | (set reg:X (unop:X expr:Y)) | |
7865 | -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)). | |
7866 | ||
32131a9c RK |
7867 | Finally, we could be called to handle an 'o' constraint by putting |
7868 | an address into a register. In that case, we first try to do this | |
7869 | with a named pattern of "reload_load_address". If no such pattern | |
7870 | exists, we just emit a SET insn and hope for the best (it will normally | |
7871 | be valid on machines that use 'o'). | |
7872 | ||
7873 | This entire process is made complex because reload will never | |
7874 | process the insns we generate here and so we must ensure that | |
7875 | they will fit their constraints and also by the fact that parts of | |
7876 | IN might be being reloaded separately and replaced with spill registers. | |
7877 | Because of this, we are, in some sense, just guessing the right approach | |
7878 | here. The one listed above seems to work. | |
7879 | ||
7880 | ??? At some point, this whole thing needs to be rethought. */ | |
7881 | ||
7882 | if (GET_CODE (in) == PLUS | |
f8cfc6aa | 7883 | && (REG_P (XEXP (in, 0)) |
5c6b1bd2 | 7884 | || GET_CODE (XEXP (in, 0)) == SUBREG |
3c0cb5de | 7885 | || MEM_P (XEXP (in, 0))) |
f8cfc6aa | 7886 | && (REG_P (XEXP (in, 1)) |
5c6b1bd2 | 7887 | || GET_CODE (XEXP (in, 1)) == SUBREG |
a7fd196c | 7888 | || CONSTANT_P (XEXP (in, 1)) |
3c0cb5de | 7889 | || MEM_P (XEXP (in, 1)))) |
32131a9c | 7890 | { |
a7fd196c JW |
7891 | /* We need to compute the sum of a register or a MEM and another |
7892 | register, constant, or MEM, and put it into the reload | |
3002e160 JW |
7893 | register. The best possible way of doing this is if the machine |
7894 | has a three-operand ADD insn that accepts the required operands. | |
32131a9c RK |
7895 | |
7896 | The simplest approach is to try to generate such an insn and see if it | |
7897 | is recognized and matches its constraints. If so, it can be used. | |
7898 | ||
7899 | It might be better not to actually emit the insn unless it is valid, | |
0009eff2 | 7900 | but we need to pass the insn as an operand to `recog' and |
0eadeb15 | 7901 | `extract_insn' and it is simpler to emit and then delete the insn if |
0009eff2 | 7902 | not valid than to dummy things up. */ |
a8fdc208 | 7903 | |
af929c62 | 7904 | rtx op0, op1, tem, insn; |
32131a9c | 7905 | int code; |
a8fdc208 | 7906 | |
af929c62 RK |
7907 | op0 = find_replacement (&XEXP (in, 0)); |
7908 | op1 = find_replacement (&XEXP (in, 1)); | |
7909 | ||
32131a9c RK |
7910 | /* Since constraint checking is strict, commutativity won't be |
7911 | checked, so we need to do that here to avoid spurious failure | |
7912 | if the add instruction is two-address and the second operand | |
7913 | of the add is the same as the reload reg, which is frequently | |
7914 | the case. If the insn would be A = B + A, rearrange it so | |
0f41302f | 7915 | it will be A = A + B as constrain_operands expects. */ |
a8fdc208 | 7916 | |
f8cfc6aa | 7917 | if (REG_P (XEXP (in, 1)) |
5e03c156 | 7918 | && REGNO (out) == REGNO (XEXP (in, 1))) |
af929c62 RK |
7919 | tem = op0, op0 = op1, op1 = tem; |
7920 | ||
7921 | if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) | |
38a448ca | 7922 | in = gen_rtx_PLUS (GET_MODE (in), op0, op1); |
32131a9c | 7923 | |
ff0d9879 HPN |
7924 | insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in)); |
7925 | if (insn) | |
7926 | return insn; | |
32131a9c RK |
7927 | |
7928 | /* If that failed, we must use a conservative two-insn sequence. | |
09522f21 FS |
7929 | |
7930 | Use a move to copy one operand into the reload register. Prefer | |
7931 | to reload a constant, MEM or pseudo since the move patterns can | |
7932 | handle an arbitrary operand. If OP1 is not a constant, MEM or | |
7933 | pseudo and OP1 is not a valid operand for an add instruction, then | |
7934 | reload OP1. | |
7935 | ||
7936 | After reloading one of the operands into the reload register, add | |
7937 | the reload register to the output register. | |
32131a9c RK |
7938 | |
7939 | If there is another way to do this for a specific machine, a | |
7940 | DEFINE_PEEPHOLE should be specified that recognizes the sequence | |
7941 | we emit below. */ | |
7942 | ||
09522f21 FS |
7943 | code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code; |
7944 | ||
3c0cb5de | 7945 | if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG |
f8cfc6aa | 7946 | || (REG_P (op1) |
09522f21 FS |
7947 | && REGNO (op1) >= FIRST_PSEUDO_REGISTER) |
7948 | || (code != CODE_FOR_nothing | |
a995e389 RH |
7949 | && ! ((*insn_data[code].operand[2].predicate) |
7950 | (op1, insn_data[code].operand[2].mode)))) | |
af929c62 | 7951 | tem = op0, op0 = op1, op1 = tem; |
32131a9c | 7952 | |
5c6b1bd2 | 7953 | gen_reload (out, op0, opnum, type); |
39b56c2a | 7954 | |
5e03c156 | 7955 | /* If OP0 and OP1 are the same, we can use OUT for OP1. |
39b56c2a RK |
7956 | This fixes a problem on the 32K where the stack pointer cannot |
7957 | be used as an operand of an add insn. */ | |
7958 | ||
7959 | if (rtx_equal_p (op0, op1)) | |
5e03c156 | 7960 | op1 = out; |
39b56c2a | 7961 | |
ff0d9879 HPN |
7962 | insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1)); |
7963 | if (insn) | |
c77c9766 | 7964 | { |
ff0d9879 | 7965 | /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ |
a31830a7 | 7966 | set_unique_reg_note (insn, REG_EQUIV, in); |
ff0d9879 | 7967 | return insn; |
c77c9766 RK |
7968 | } |
7969 | ||
ff0d9879 HPN |
7970 | /* If that failed, copy the address register to the reload register. |
7971 | Then add the constant to the reload register. */ | |
c77c9766 | 7972 | |
8c74fb06 | 7973 | gcc_assert (!reg_overlap_mentioned_p (out, op0)); |
5c6b1bd2 | 7974 | gen_reload (out, op1, opnum, type); |
4117a96b | 7975 | insn = emit_insn (gen_add2_insn (out, op0)); |
a31830a7 | 7976 | set_unique_reg_note (insn, REG_EQUIV, in); |
32131a9c RK |
7977 | } |
7978 | ||
0dadecf6 RK |
7979 | #ifdef SECONDARY_MEMORY_NEEDED |
7980 | /* If we need a memory location to do the move, do it that way. */ | |
f8cfc6aa | 7981 | else if ((REG_P (in) || GET_CODE (in) == SUBREG) |
344b78b8 | 7982 | && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER |
f8cfc6aa | 7983 | && (REG_P (out) || GET_CODE (out) == SUBREG) |
344b78b8 JH |
7984 | && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER |
7985 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)), | |
7986 | REGNO_REG_CLASS (reg_or_subregno (out)), | |
5e03c156 | 7987 | GET_MODE (out))) |
0dadecf6 RK |
7988 | { |
7989 | /* Get the memory to use and rewrite both registers to its mode. */ | |
5e03c156 | 7990 | rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); |
0dadecf6 | 7991 | |
5e03c156 | 7992 | if (GET_MODE (loc) != GET_MODE (out)) |
38a448ca | 7993 | out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); |
0dadecf6 RK |
7994 | |
7995 | if (GET_MODE (loc) != GET_MODE (in)) | |
38a448ca | 7996 | in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); |
0dadecf6 | 7997 | |
5c6b1bd2 RK |
7998 | gen_reload (loc, in, opnum, type); |
7999 | gen_reload (out, loc, opnum, type); | |
0dadecf6 RK |
8000 | } |
8001 | #endif | |
ff0d9879 HPN |
8002 | else if (REG_P (out) && UNARY_P (in)) |
8003 | { | |
8004 | rtx insn; | |
8005 | rtx op1; | |
8006 | rtx out_moded; | |
8007 | rtx set; | |
0dadecf6 | 8008 | |
d0ab13fd R |
8009 | op1 = find_replacement (&XEXP (in, 0)); |
8010 | if (op1 != XEXP (in, 0)) | |
8011 | in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1); | |
8012 | ||
ff0d9879 HPN |
8013 | /* First, try a plain SET. */ |
8014 | set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in)); | |
8015 | if (set) | |
8016 | return set; | |
8017 | ||
8018 | /* If that failed, move the inner operand to the reload | |
8019 | register, and try the same unop with the inner expression | |
8020 | replaced with the reload register. */ | |
ff0d9879 HPN |
8021 | |
8022 | if (GET_MODE (op1) != GET_MODE (out)) | |
8023 | out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out)); | |
8024 | else | |
8025 | out_moded = out; | |
8026 | ||
8027 | gen_reload (out_moded, op1, opnum, type); | |
8028 | ||
8029 | insn | |
8030 | = gen_rtx_SET (VOIDmode, out, | |
8031 | gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), | |
8032 | out_moded)); | |
8033 | insn = emit_insn_if_valid_for_reload (insn); | |
8034 | if (insn) | |
8035 | { | |
a31830a7 | 8036 | set_unique_reg_note (insn, REG_EQUIV, in); |
ff0d9879 HPN |
8037 | return insn; |
8038 | } | |
8039 | ||
8040 | fatal_insn ("Failure trying to reload:", set); | |
8041 | } | |
32131a9c | 8042 | /* If IN is a simple operand, use gen_move_insn. */ |
ec8e098d | 8043 | else if (OBJECT_P (in) || GET_CODE (in) == SUBREG) |
8c339083 RS |
8044 | { |
8045 | tem = emit_insn (gen_move_insn (out, in)); | |
8046 | /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */ | |
8047 | mark_jump_label (in, tem, 0); | |
8048 | } | |
32131a9c RK |
8049 | |
8050 | #ifdef HAVE_reload_load_address | |
8051 | else if (HAVE_reload_load_address) | |
5e03c156 | 8052 | emit_insn (gen_reload_load_address (out, in)); |
32131a9c RK |
8053 | #endif |
8054 | ||
5e03c156 | 8055 | /* Otherwise, just write (set OUT IN) and hope for the best. */ |
32131a9c | 8056 | else |
38a448ca | 8057 | emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
8058 | |
8059 | /* Return the first insn emitted. | |
546b63fb | 8060 | We can not just return get_last_insn, because there may have |
32131a9c RK |
8061 | been multiple instructions emitted. Also note that gen_move_insn may |
8062 | emit more than one insn itself, so we can not assume that there is one | |
8063 | insn emitted per emit_insn_before call. */ | |
8064 | ||
546b63fb | 8065 | return last ? NEXT_INSN (last) : get_insns (); |
32131a9c RK |
8066 | } |
8067 | \f | |
cda94cbb RH |
8068 | /* Delete a previously made output-reload whose result we now believe |
8069 | is not needed. First we double-check. | |
32131a9c RK |
8070 | |
8071 | INSN is the insn now being processed. | |
cb2afeb3 R |
8072 | LAST_RELOAD_REG is the hard register number for which we want to delete |
8073 | the last output reload. | |
8074 | J is the reload-number that originally used REG. The caller has made | |
8075 | certain that reload J doesn't use REG any longer for input. */ | |
32131a9c RK |
8076 | |
8077 | static void | |
0c20a65f | 8078 | delete_output_reload (rtx insn, int j, int last_reload_reg) |
32131a9c | 8079 | { |
cb2afeb3 R |
8080 | rtx output_reload_insn = spill_reg_store[last_reload_reg]; |
8081 | rtx reg = spill_reg_stored_to[last_reload_reg]; | |
8082 | int k; | |
8083 | int n_occurrences; | |
8084 | int n_inherited = 0; | |
b3694847 | 8085 | rtx i1; |
cb2afeb3 | 8086 | rtx substed; |
05d10675 | 8087 | |
068f5dea JH |
8088 | /* It is possible that this reload has been only used to set another reload |
8089 | we eliminated earlier and thus deleted this instruction too. */ | |
8090 | if (INSN_DELETED_P (output_reload_insn)) | |
8091 | return; | |
8092 | ||
32131a9c RK |
8093 | /* Get the raw pseudo-register referred to. */ |
8094 | ||
32131a9c RK |
8095 | while (GET_CODE (reg) == SUBREG) |
8096 | reg = SUBREG_REG (reg); | |
cb2afeb3 R |
8097 | substed = reg_equiv_memory_loc[REGNO (reg)]; |
8098 | ||
8099 | /* This is unsafe if the operand occurs more often in the current | |
8100 | insn than it is inherited. */ | |
8101 | for (k = n_reloads - 1; k >= 0; k--) | |
8102 | { | |
eceef4c9 | 8103 | rtx reg2 = rld[k].in; |
cb2afeb3 R |
8104 | if (! reg2) |
8105 | continue; | |
3c0cb5de | 8106 | if (MEM_P (reg2) || reload_override_in[k]) |
eceef4c9 | 8107 | reg2 = rld[k].in_reg; |
cb2afeb3 | 8108 | #ifdef AUTO_INC_DEC |
eceef4c9 BS |
8109 | if (rld[k].out && ! rld[k].out_reg) |
8110 | reg2 = XEXP (rld[k].in_reg, 0); | |
cb2afeb3 R |
8111 | #endif |
8112 | while (GET_CODE (reg2) == SUBREG) | |
8113 | reg2 = SUBREG_REG (reg2); | |
8114 | if (rtx_equal_p (reg2, reg)) | |
2eb6dac7 AS |
8115 | { |
8116 | if (reload_inherited[k] || reload_override_in[k] || k == j) | |
f2eb49dc | 8117 | n_inherited++; |
2eb6dac7 AS |
8118 | else |
8119 | return; | |
8120 | } | |
cb2afeb3 | 8121 | } |
4b983fdc | 8122 | n_occurrences = count_occurrences (PATTERN (insn), reg, 0); |
2372a062 BS |
8123 | if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn)) |
8124 | n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn), | |
8125 | reg, 0); | |
cb2afeb3 | 8126 | if (substed) |
5d7ef82a BS |
8127 | n_occurrences += count_occurrences (PATTERN (insn), |
8128 | eliminate_regs (substed, 0, | |
8129 | NULL_RTX), 0); | |
3f1e3e70 AO |
8130 | for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1)) |
8131 | { | |
8132 | gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed)); | |
8133 | n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0); | |
8134 | } | |
cb2afeb3 R |
8135 | if (n_occurrences > n_inherited) |
8136 | return; | |
32131a9c RK |
8137 | |
8138 | /* If the pseudo-reg we are reloading is no longer referenced | |
8139 | anywhere between the store into it and here, | |
0149f412 HPN |
8140 | and we're within the same basic block, then the value can only |
8141 | pass through the reload reg and end up here. | |
32131a9c RK |
8142 | Otherwise, give up--return. */ |
8143 | for (i1 = NEXT_INSN (output_reload_insn); | |
8144 | i1 != insn; i1 = NEXT_INSN (i1)) | |
8145 | { | |
0149f412 | 8146 | if (NOTE_INSN_BASIC_BLOCK_P (i1)) |
32131a9c | 8147 | return; |
4b4bf941 | 8148 | if ((NONJUMP_INSN_P (i1) || CALL_P (i1)) |
32131a9c | 8149 | && reg_mentioned_p (reg, PATTERN (i1))) |
aa6498c2 | 8150 | { |
cb2afeb3 R |
8151 | /* If this is USE in front of INSN, we only have to check that |
8152 | there are no more references than accounted for by inheritance. */ | |
4b4bf941 | 8153 | while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE) |
aa6498c2 | 8154 | { |
cb2afeb3 | 8155 | n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; |
aa6498c2 R |
8156 | i1 = NEXT_INSN (i1); |
8157 | } | |
cb2afeb3 | 8158 | if (n_occurrences <= n_inherited && i1 == insn) |
aa6498c2 R |
8159 | break; |
8160 | return; | |
8161 | } | |
32131a9c RK |
8162 | } |
8163 | ||
cda94cbb | 8164 | /* We will be deleting the insn. Remove the spill reg information. */ |
66fd46b6 | 8165 | for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; ) |
cda94cbb RH |
8166 | { |
8167 | spill_reg_store[last_reload_reg + k] = 0; | |
8168 | spill_reg_stored_to[last_reload_reg + k] = 0; | |
8169 | } | |
8170 | ||
aa6498c2 | 8171 | /* The caller has already checked that REG dies or is set in INSN. |
cda94cbb | 8172 | It has also checked that we are optimizing, and thus some |
14b493d6 | 8173 | inaccuracies in the debugging information are acceptable. |
cda94cbb RH |
8174 | So we could just delete output_reload_insn. But in some cases |
8175 | we can improve the debugging information without sacrificing | |
8176 | optimization - maybe even improving the code: See if the pseudo | |
8177 | reg has been completely replaced with reload regs. If so, delete | |
8178 | the store insn and forget we had a stack slot for the pseudo. */ | |
eceef4c9 | 8179 | if (rld[j].out != rld[j].in |
aa6498c2 | 8180 | && REG_N_DEATHS (REGNO (reg)) == 1 |
a3a24aa6 | 8181 | && REG_N_SETS (REGNO (reg)) == 1 |
6fb5fa3c | 8182 | && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS |
aa6498c2 | 8183 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) |
32131a9c RK |
8184 | { |
8185 | rtx i2; | |
8186 | ||
cda94cbb RH |
8187 | /* We know that it was used only between here and the beginning of |
8188 | the current basic block. (We also know that the last use before | |
8189 | INSN was the output reload we are thinking of deleting, but never | |
8190 | mind that.) Search that range; see if any ref remains. */ | |
32131a9c RK |
8191 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) |
8192 | { | |
d445b551 RK |
8193 | rtx set = single_set (i2); |
8194 | ||
32131a9c RK |
8195 | /* Uses which just store in the pseudo don't count, |
8196 | since if they are the only uses, they are dead. */ | |
d445b551 | 8197 | if (set != 0 && SET_DEST (set) == reg) |
32131a9c | 8198 | continue; |
4b4bf941 JQ |
8199 | if (LABEL_P (i2) |
8200 | || JUMP_P (i2)) | |
32131a9c | 8201 | break; |
4b4bf941 | 8202 | if ((NONJUMP_INSN_P (i2) || CALL_P (i2)) |
32131a9c | 8203 | && reg_mentioned_p (reg, PATTERN (i2))) |
aa6498c2 R |
8204 | { |
8205 | /* Some other ref remains; just delete the output reload we | |
8206 | know to be dead. */ | |
cb2afeb3 | 8207 | delete_address_reloads (output_reload_insn, insn); |
ca6c03ca | 8208 | delete_insn (output_reload_insn); |
aa6498c2 R |
8209 | return; |
8210 | } | |
32131a9c RK |
8211 | } |
8212 | ||
cda94cbb RH |
8213 | /* Delete the now-dead stores into this pseudo. Note that this |
8214 | loop also takes care of deleting output_reload_insn. */ | |
32131a9c RK |
8215 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) |
8216 | { | |
d445b551 RK |
8217 | rtx set = single_set (i2); |
8218 | ||
8219 | if (set != 0 && SET_DEST (set) == reg) | |
5507b94b | 8220 | { |
cb2afeb3 | 8221 | delete_address_reloads (i2, insn); |
ca6c03ca | 8222 | delete_insn (i2); |
5507b94b | 8223 | } |
4b4bf941 JQ |
8224 | if (LABEL_P (i2) |
8225 | || JUMP_P (i2)) | |
32131a9c RK |
8226 | break; |
8227 | } | |
8228 | ||
cda94cbb | 8229 | /* For the debugging info, say the pseudo lives in this reload reg. */ |
eceef4c9 | 8230 | reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx); |
32131a9c RK |
8231 | alter_reg (REGNO (reg), -1); |
8232 | } | |
cda94cbb RH |
8233 | else |
8234 | { | |
8235 | delete_address_reloads (output_reload_insn, insn); | |
8236 | delete_insn (output_reload_insn); | |
8237 | } | |
cb2afeb3 R |
8238 | } |
8239 | ||
8240 | /* We are going to delete DEAD_INSN. Recursively delete loads of | |
8241 | reload registers used in DEAD_INSN that are not used till CURRENT_INSN. | |
8242 | CURRENT_INSN is being reloaded, so we have to check its reloads too. */ | |
8243 | static void | |
0c20a65f | 8244 | delete_address_reloads (rtx dead_insn, rtx current_insn) |
cb2afeb3 R |
8245 | { |
8246 | rtx set = single_set (dead_insn); | |
8247 | rtx set2, dst, prev, next; | |
8248 | if (set) | |
8249 | { | |
8250 | rtx dst = SET_DEST (set); | |
3c0cb5de | 8251 | if (MEM_P (dst)) |
cb2afeb3 R |
8252 | delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); |
8253 | } | |
8254 | /* If we deleted the store from a reloaded post_{in,de}c expression, | |
8255 | we can delete the matching adds. */ | |
8256 | prev = PREV_INSN (dead_insn); | |
8257 | next = NEXT_INSN (dead_insn); | |
8258 | if (! prev || ! next) | |
8259 | return; | |
8260 | set = single_set (next); | |
8261 | set2 = single_set (prev); | |
8262 | if (! set || ! set2 | |
8263 | || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS | |
8264 | || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT | |
8265 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT) | |
8266 | return; | |
8267 | dst = SET_DEST (set); | |
8268 | if (! rtx_equal_p (dst, SET_DEST (set2)) | |
8269 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) | |
8270 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) | |
8271 | || (INTVAL (XEXP (SET_SRC (set), 1)) | |
1d7254c5 | 8272 | != -INTVAL (XEXP (SET_SRC (set2), 1)))) |
cb2afeb3 | 8273 | return; |
53c17031 JH |
8274 | delete_related_insns (prev); |
8275 | delete_related_insns (next); | |
cb2afeb3 R |
8276 | } |
8277 | ||
8278 | /* Subfunction of delete_address_reloads: process registers found in X. */ | |
8279 | static void | |
0c20a65f | 8280 | delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn) |
cb2afeb3 R |
8281 | { |
8282 | rtx prev, set, dst, i2; | |
8283 | int i, j; | |
8284 | enum rtx_code code = GET_CODE (x); | |
8285 | ||
8286 | if (code != REG) | |
8287 | { | |
1d7254c5 | 8288 | const char *fmt = GET_RTX_FORMAT (code); |
cb2afeb3 R |
8289 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
8290 | { | |
8291 | if (fmt[i] == 'e') | |
8292 | delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); | |
8293 | else if (fmt[i] == 'E') | |
8294 | { | |
1d7254c5 | 8295 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
cb2afeb3 R |
8296 | delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), |
8297 | current_insn); | |
8298 | } | |
8299 | } | |
8300 | return; | |
8301 | } | |
8302 | ||
8303 | if (spill_reg_order[REGNO (x)] < 0) | |
8304 | return; | |
aa6498c2 | 8305 | |
cb2afeb3 R |
8306 | /* Scan backwards for the insn that sets x. This might be a way back due |
8307 | to inheritance. */ | |
8308 | for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) | |
8309 | { | |
8310 | code = GET_CODE (prev); | |
8311 | if (code == CODE_LABEL || code == JUMP_INSN) | |
8312 | return; | |
ec8e098d | 8313 | if (!INSN_P (prev)) |
cb2afeb3 R |
8314 | continue; |
8315 | if (reg_set_p (x, PATTERN (prev))) | |
8316 | break; | |
8317 | if (reg_referenced_p (x, PATTERN (prev))) | |
8318 | return; | |
8319 | } | |
8320 | if (! prev || INSN_UID (prev) < reload_first_uid) | |
8321 | return; | |
8322 | /* Check that PREV only sets the reload register. */ | |
8323 | set = single_set (prev); | |
8324 | if (! set) | |
8325 | return; | |
8326 | dst = SET_DEST (set); | |
f8cfc6aa | 8327 | if (!REG_P (dst) |
cb2afeb3 R |
8328 | || ! rtx_equal_p (dst, x)) |
8329 | return; | |
8330 | if (! reg_set_p (dst, PATTERN (dead_insn))) | |
8331 | { | |
8332 | /* Check if DST was used in a later insn - | |
8333 | it might have been inherited. */ | |
8334 | for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) | |
8335 | { | |
4b4bf941 | 8336 | if (LABEL_P (i2)) |
cb2afeb3 | 8337 | break; |
2c3c49de | 8338 | if (! INSN_P (i2)) |
cb2afeb3 R |
8339 | continue; |
8340 | if (reg_referenced_p (dst, PATTERN (i2))) | |
8341 | { | |
8342 | /* If there is a reference to the register in the current insn, | |
8343 | it might be loaded in a non-inherited reload. If no other | |
8344 | reload uses it, that means the register is set before | |
8345 | referenced. */ | |
8346 | if (i2 == current_insn) | |
8347 | { | |
8348 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 8349 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
8350 | || reload_override_in[j] == dst) |
8351 | return; | |
8352 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 8353 | if (rld[j].in && rld[j].reg_rtx == dst) |
cb2afeb3 R |
8354 | break; |
8355 | if (j >= 0) | |
8356 | break; | |
8357 | } | |
8358 | return; | |
8359 | } | |
4b4bf941 | 8360 | if (JUMP_P (i2)) |
cb2afeb3 | 8361 | break; |
cb2afeb3 | 8362 | /* If DST is still live at CURRENT_INSN, check if it is used for |
3900dc09 R |
8363 | any reload. Note that even if CURRENT_INSN sets DST, we still |
8364 | have to check the reloads. */ | |
cb2afeb3 R |
8365 | if (i2 == current_insn) |
8366 | { | |
8367 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 8368 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
8369 | || reload_override_in[j] == dst) |
8370 | return; | |
8371 | /* ??? We can't finish the loop here, because dst might be | |
8372 | allocated to a pseudo in this block if no reload in this | |
14b493d6 | 8373 | block needs any of the classes containing DST - see |
cb2afeb3 R |
8374 | spill_hard_reg. There is no easy way to tell this, so we |
8375 | have to scan till the end of the basic block. */ | |
8376 | } | |
3900dc09 R |
8377 | if (reg_set_p (dst, PATTERN (i2))) |
8378 | break; | |
cb2afeb3 R |
8379 | } |
8380 | } | |
8381 | delete_address_reloads_1 (prev, SET_SRC (set), current_insn); | |
8382 | reg_reloaded_contents[REGNO (dst)] = -1; | |
ca6c03ca | 8383 | delete_insn (prev); |
32131a9c | 8384 | } |
32131a9c | 8385 | \f |
a8fdc208 | 8386 | /* Output reload-insns to reload VALUE into RELOADREG. |
858a47b1 | 8387 | VALUE is an autoincrement or autodecrement RTX whose operand |
32131a9c RK |
8388 | is a register or memory location; |
8389 | so reloading involves incrementing that location. | |
cb2afeb3 | 8390 | IN is either identical to VALUE, or some cheaper place to reload from. |
32131a9c RK |
8391 | |
8392 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
cb2afeb3 | 8393 | This cannot be deduced from VALUE. |
32131a9c | 8394 | |
cb2afeb3 R |
8395 | Return the instruction that stores into RELOADREG. */ |
8396 | ||
8397 | static rtx | |
0c20a65f | 8398 | inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount) |
32131a9c RK |
8399 | { |
8400 | /* REG or MEM to be copied and incremented. */ | |
4b7b277a | 8401 | rtx incloc = find_replacement (&XEXP (value, 0)); |
32131a9c | 8402 | /* Nonzero if increment after copying. */ |
67f07489 PB |
8403 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC |
8404 | || GET_CODE (value) == POST_MODIFY); | |
546b63fb | 8405 | rtx last; |
0009eff2 RK |
8406 | rtx inc; |
8407 | rtx add_insn; | |
8408 | int code; | |
cb2afeb3 | 8409 | rtx store; |
4b7b277a | 8410 | rtx real_in = in == value ? incloc : in; |
32131a9c RK |
8411 | |
8412 | /* No hard register is equivalent to this register after | |
40f03658 | 8413 | inc/dec operation. If REG_LAST_RELOAD_REG were nonzero, |
32131a9c RK |
8414 | we could inc/dec that register as well (maybe even using it for |
8415 | the source), but I'm not sure it's worth worrying about. */ | |
f8cfc6aa | 8416 | if (REG_P (incloc)) |
32131a9c RK |
8417 | reg_last_reload_reg[REGNO (incloc)] = 0; |
8418 | ||
67f07489 PB |
8419 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) |
8420 | { | |
8421 | gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS); | |
4b7b277a | 8422 | inc = find_replacement (&XEXP (XEXP (value, 1), 1)); |
67f07489 PB |
8423 | } |
8424 | else | |
8425 | { | |
8426 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
8427 | inc_amount = -inc_amount; | |
32131a9c | 8428 | |
67f07489 PB |
8429 | inc = GEN_INT (inc_amount); |
8430 | } | |
0009eff2 RK |
8431 | |
8432 | /* If this is post-increment, first copy the location to the reload reg. */ | |
cb2afeb3 R |
8433 | if (post && real_in != reloadreg) |
8434 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
0009eff2 | 8435 | |
cb2afeb3 R |
8436 | if (in == value) |
8437 | { | |
8438 | /* See if we can directly increment INCLOC. Use a method similar to | |
8439 | that in gen_reload. */ | |
0009eff2 | 8440 | |
cb2afeb3 R |
8441 | last = get_last_insn (); |
8442 | add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, | |
8443 | gen_rtx_PLUS (GET_MODE (incloc), | |
8444 | incloc, inc))); | |
05d10675 | 8445 | |
cb2afeb3 R |
8446 | code = recog_memoized (add_insn); |
8447 | if (code >= 0) | |
32131a9c | 8448 | { |
0eadeb15 BS |
8449 | extract_insn (add_insn); |
8450 | if (constrain_operands (1)) | |
cb2afeb3 R |
8451 | { |
8452 | /* If this is a pre-increment and we have incremented the value | |
8453 | where it lives, copy the incremented value to RELOADREG to | |
8454 | be used as an address. */ | |
0009eff2 | 8455 | |
cb2afeb3 R |
8456 | if (! post) |
8457 | emit_insn (gen_move_insn (reloadreg, incloc)); | |
546b63fb | 8458 | |
cb2afeb3 R |
8459 | return add_insn; |
8460 | } | |
32131a9c | 8461 | } |
cb2afeb3 | 8462 | delete_insns_since (last); |
32131a9c | 8463 | } |
0009eff2 | 8464 | |
0009eff2 RK |
8465 | /* If couldn't do the increment directly, must increment in RELOADREG. |
8466 | The way we do this depends on whether this is pre- or post-increment. | |
8467 | For pre-increment, copy INCLOC to the reload register, increment it | |
8468 | there, then save back. */ | |
8469 | ||
8470 | if (! post) | |
8471 | { | |
cb2afeb3 R |
8472 | if (in != reloadreg) |
8473 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
546b63fb | 8474 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 8475 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
0009eff2 | 8476 | } |
32131a9c RK |
8477 | else |
8478 | { | |
0009eff2 RK |
8479 | /* Postincrement. |
8480 | Because this might be a jump insn or a compare, and because RELOADREG | |
8481 | may not be available after the insn in an input reload, we must do | |
8482 | the incrementation before the insn being reloaded for. | |
8483 | ||
cb2afeb3 | 8484 | We have already copied IN to RELOADREG. Increment the copy in |
0009eff2 RK |
8485 | RELOADREG, save that back, then decrement RELOADREG so it has |
8486 | the original value. */ | |
8487 | ||
546b63fb | 8488 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 8489 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
67f07489 | 8490 | if (GET_CODE (inc) == CONST_INT) |
247140ea | 8491 | emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc)))); |
67f07489 PB |
8492 | else |
8493 | emit_insn (gen_sub2_insn (reloadreg, inc)); | |
32131a9c | 8494 | } |
0009eff2 | 8495 | |
cb2afeb3 | 8496 | return store; |
32131a9c RK |
8497 | } |
8498 | \f | |
2dfa9a87 MH |
8499 | #ifdef AUTO_INC_DEC |
8500 | static void | |
0c20a65f | 8501 | add_auto_inc_notes (rtx insn, rtx x) |
2dfa9a87 MH |
8502 | { |
8503 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 8504 | const char *fmt; |
2dfa9a87 MH |
8505 | int i, j; |
8506 | ||
8507 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
8508 | { | |
8509 | REG_NOTES (insn) | |
8510 | = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn)); | |
8511 | return; | |
8512 | } | |
8513 | ||
8514 | /* Scan all the operand sub-expressions. */ | |
8515 | fmt = GET_RTX_FORMAT (code); | |
8516 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
8517 | { | |
8518 | if (fmt[i] == 'e') | |
8519 | add_auto_inc_notes (insn, XEXP (x, i)); | |
8520 | else if (fmt[i] == 'E') | |
8521 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
8522 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
8523 | } | |
8524 | } | |
8525 | #endif | |
94bd63e5 AH |
8526 | |
8527 | /* Copy EH notes from an insn to its reloads. */ | |
8528 | static void | |
0c20a65f | 8529 | copy_eh_notes (rtx insn, rtx x) |
94bd63e5 AH |
8530 | { |
8531 | rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
8532 | if (eh_note) | |
8533 | { | |
8534 | for (; x != 0; x = NEXT_INSN (x)) | |
8535 | { | |
8536 | if (may_trap_p (PATTERN (x))) | |
a6a2274a | 8537 | REG_NOTES (x) |
94bd63e5 AH |
8538 | = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0), |
8539 | REG_NOTES (x)); | |
8540 | } | |
8541 | } | |
8542 | } | |
8543 | ||
f1330226 JH |
8544 | /* This is used by reload pass, that does emit some instructions after |
8545 | abnormal calls moving basic block end, but in fact it wants to emit | |
8546 | them on the edge. Looks for abnormal call edges, find backward the | |
8547 | proper call and fix the damage. | |
a6a2274a | 8548 | |
f1330226 | 8549 | Similar handle instructions throwing exceptions internally. */ |
068473ec | 8550 | void |
0c20a65f | 8551 | fixup_abnormal_edges (void) |
f1330226 | 8552 | { |
f1330226 | 8553 | bool inserted = false; |
e0082a72 | 8554 | basic_block bb; |
f1330226 | 8555 | |
e0082a72 | 8556 | FOR_EACH_BB (bb) |
f1330226 | 8557 | { |
f1330226 | 8558 | edge e; |
628f6a4e | 8559 | edge_iterator ei; |
f1330226 | 8560 | |
09da1532 | 8561 | /* Look for cases we are interested in - calls or instructions causing |
f1330226 | 8562 | exceptions. */ |
628f6a4e | 8563 | FOR_EACH_EDGE (e, ei, bb->succs) |
f1330226 JH |
8564 | { |
8565 | if (e->flags & EDGE_ABNORMAL_CALL) | |
8566 | break; | |
8567 | if ((e->flags & (EDGE_ABNORMAL | EDGE_EH)) | |
8568 | == (EDGE_ABNORMAL | EDGE_EH)) | |
8569 | break; | |
8570 | } | |
4b4bf941 | 8571 | if (e && !CALL_P (BB_END (bb)) |
a813c111 | 8572 | && !can_throw_internal (BB_END (bb))) |
f1330226 | 8573 | { |
be0c514c RH |
8574 | rtx insn; |
8575 | ||
8576 | /* Get past the new insns generated. Allow notes, as the insns | |
8577 | may be already deleted. */ | |
8578 | insn = BB_END (bb); | |
4b4bf941 | 8579 | while ((NONJUMP_INSN_P (insn) || NOTE_P (insn)) |
39f95a2c | 8580 | && !can_throw_internal (insn) |
a813c111 | 8581 | && insn != BB_HEAD (bb)) |
f1330226 | 8582 | insn = PREV_INSN (insn); |
be0c514c RH |
8583 | |
8584 | if (CALL_P (insn) || can_throw_internal (insn)) | |
f1330226 | 8585 | { |
be0c514c RH |
8586 | rtx stop, next; |
8587 | ||
8588 | stop = NEXT_INSN (BB_END (bb)); | |
8589 | BB_END (bb) = insn; | |
8590 | insn = NEXT_INSN (insn); | |
8591 | ||
8592 | FOR_EACH_EDGE (e, ei, bb->succs) | |
8593 | if (e->flags & EDGE_FALLTHRU) | |
8594 | break; | |
8595 | ||
8596 | while (insn && insn != stop) | |
0c4992b0 | 8597 | { |
be0c514c RH |
8598 | next = NEXT_INSN (insn); |
8599 | if (INSN_P (insn)) | |
ed8d2920 | 8600 | { |
36808d08 | 8601 | delete_insn (insn); |
be0c514c RH |
8602 | |
8603 | /* Sometimes there's still the return value USE. | |
8604 | If it's placed after a trapping call (i.e. that | |
8605 | call is the last insn anyway), we have no fallthru | |
8606 | edge. Simply delete this use and don't try to insert | |
8607 | on the non-existent edge. */ | |
8608 | if (GET_CODE (PATTERN (insn)) != USE) | |
8609 | { | |
8610 | /* We're not deleting it, we're moving it. */ | |
8611 | INSN_DELETED_P (insn) = 0; | |
8612 | PREV_INSN (insn) = NULL_RTX; | |
8613 | NEXT_INSN (insn) = NULL_RTX; | |
f8ed1958 | 8614 | |
be0c514c RH |
8615 | insert_insn_on_edge (insn, e); |
8616 | inserted = true; | |
8617 | } | |
ed8d2920 | 8618 | } |
36808d08 EB |
8619 | else if (!BARRIER_P (insn)) |
8620 | set_block_for_insn (insn, NULL); | |
be0c514c | 8621 | insn = next; |
0c4992b0 | 8622 | } |
f1330226 | 8623 | } |
be0c514c RH |
8624 | |
8625 | /* It may be that we don't find any such trapping insn. In this | |
8626 | case we discovered quite late that the insn that had been | |
8627 | marked as can_throw_internal in fact couldn't trap at all. | |
8628 | So we should in fact delete the EH edges out of the block. */ | |
8629 | else | |
8630 | purge_dead_edges (bb); | |
f1330226 JH |
8631 | } |
8632 | } | |
be0c514c | 8633 | |
b735f45d AK |
8634 | /* We've possibly turned single trapping insn into multiple ones. */ |
8635 | if (flag_non_call_exceptions) | |
8636 | { | |
8637 | sbitmap blocks; | |
8638 | blocks = sbitmap_alloc (last_basic_block); | |
8639 | sbitmap_ones (blocks); | |
8640 | find_many_sub_basic_blocks (blocks); | |
639d3040 | 8641 | sbitmap_free (blocks); |
b735f45d AK |
8642 | } |
8643 | ||
f1330226 JH |
8644 | if (inserted) |
8645 | commit_edge_insertions (); | |
be0c514c RH |
8646 | |
8647 | #ifdef ENABLE_CHECKING | |
8648 | /* Verify that we didn't turn one trapping insn into many, and that | |
8649 | we found and corrected all of the problems wrt fixups on the | |
8650 | fallthru edge. */ | |
8651 | verify_flow_info (); | |
8652 | #endif | |
f1330226 | 8653 | } |