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32131a9c | 1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
af841dbd | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
66647d44 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
4c9034c5 | 4 | Free Software Foundation, Inc. |
32131a9c | 5 | |
1322177d | 6 | This file is part of GCC. |
32131a9c | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
32131a9c | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
32131a9c RK |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
32131a9c | 21 | |
32131a9c | 22 | #include "config.h" |
670ee920 | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
cab634f2 KG |
26 | |
27 | #include "machmode.h" | |
28 | #include "hard-reg-set.h" | |
32131a9c | 29 | #include "rtl.h" |
6baf1cc8 | 30 | #include "tm_p.h" |
32131a9c RK |
31 | #include "obstack.h" |
32 | #include "insn-config.h" | |
32131a9c | 33 | #include "flags.h" |
49ad7cfa | 34 | #include "function.h" |
32131a9c | 35 | #include "expr.h" |
e78d8e51 | 36 | #include "optabs.h" |
32131a9c | 37 | #include "regs.h" |
c4963a0a | 38 | #include "addresses.h" |
cad6f7d0 | 39 | #include "basic-block.h" |
32131a9c RK |
40 | #include "reload.h" |
41 | #include "recog.h" | |
32131a9c | 42 | #include "output.h" |
a9c366bf | 43 | #include "real.h" |
10f0ad3d | 44 | #include "toplev.h" |
39f95a2c | 45 | #include "except.h" |
a20fd5ac | 46 | #include "tree.h" |
058e97ec | 47 | #include "ira.h" |
6fb5fa3c | 48 | #include "df.h" |
8a99f6f9 | 49 | #include "target.h" |
f6129d66 | 50 | #include "emit-rtl.h" |
32131a9c RK |
51 | |
52 | /* This file contains the reload pass of the compiler, which is | |
53 | run after register allocation has been done. It checks that | |
54 | each insn is valid (operands required to be in registers really | |
55 | are in registers of the proper class) and fixes up invalid ones | |
56 | by copying values temporarily into registers for the insns | |
57 | that need them. | |
58 | ||
59 | The results of register allocation are described by the vector | |
60 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
61 | can be used to find which hard reg, if any, a pseudo reg is in. | |
62 | ||
63 | The technique we always use is to free up a few hard regs that are | |
64 | called ``reload regs'', and for each place where a pseudo reg | |
65 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
66 | ||
03acd8f8 BS |
67 | Reload regs are allocated locally for every instruction that needs |
68 | reloads. When there are pseudos which are allocated to a register that | |
69 | has been chosen as a reload reg, such pseudos must be ``spilled''. | |
70 | This means that they go to other hard regs, or to stack slots if no other | |
32131a9c RK |
71 | available hard regs can be found. Spilling can invalidate more |
72 | insns, requiring additional need for reloads, so we must keep checking | |
73 | until the process stabilizes. | |
74 | ||
75 | For machines with different classes of registers, we must keep track | |
76 | of the register class needed for each reload, and make sure that | |
77 | we allocate enough reload registers of each class. | |
78 | ||
79 | The file reload.c contains the code that checks one insn for | |
80 | validity and reports the reloads that it needs. This file | |
81 | is in charge of scanning the entire rtl code, accumulating the | |
82 | reload needs, spilling, assigning reload registers to use for | |
83 | fixing up each insn, and generating the new insns to copy values | |
84 | into the reload registers. */ | |
85 | \f | |
86 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
0f41302f | 87 | into which reg N has been reloaded (perhaps for a previous insn). */ |
32131a9c RK |
88 | static rtx *reg_last_reload_reg; |
89 | ||
90 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
91 | for an output reload that stores into reg N. */ | |
2c61f5f1 | 92 | static regset_head reg_has_output_reload; |
32131a9c RK |
93 | |
94 | /* Indicates which hard regs are reload-registers for an output reload | |
95 | in the current insn. */ | |
96 | static HARD_REG_SET reg_is_output_reload; | |
97 | ||
98 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
99 | or zero if pseudo reg N is not equivalent to a constant. | |
100 | find_reloads looks at this in order to replace pseudo reg N | |
101 | with the constant it stands for. */ | |
102 | rtx *reg_equiv_constant; | |
103 | ||
ab156144 RH |
104 | /* Element N is an invariant value to which pseudo reg N is equivalent. |
105 | eliminate_regs_in_insn uses this to replace pseudos in particular | |
106 | contexts. */ | |
107 | rtx *reg_equiv_invariant; | |
108 | ||
32131a9c RK |
109 | /* Element N is a memory location to which pseudo reg N is equivalent, |
110 | prior to any register elimination (such as frame pointer to stack | |
111 | pointer). Depending on whether or not it is a valid address, this value | |
112 | is transferred to either reg_equiv_address or reg_equiv_mem. */ | |
4803a34a | 113 | rtx *reg_equiv_memory_loc; |
32131a9c | 114 | |
965ccc5a R |
115 | /* We allocate reg_equiv_memory_loc inside a varray so that the garbage |
116 | collector can keep track of what is inside. */ | |
43b373a2 | 117 | VEC(rtx,gc) *reg_equiv_memory_loc_vec; |
965ccc5a | 118 | |
32131a9c RK |
119 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. |
120 | This is used when the address is not valid as a memory address | |
121 | (because its displacement is too big for the machine.) */ | |
122 | rtx *reg_equiv_address; | |
123 | ||
124 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
125 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
126 | rtx *reg_equiv_mem; | |
127 | ||
3f1e3e70 AO |
128 | /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with |
129 | alternate representations of the location of pseudo reg N. */ | |
130 | rtx *reg_equiv_alt_mem_list; | |
131 | ||
32131a9c | 132 | /* Widest width in which each pseudo reg is referred to (via subreg). */ |
770ae6cc | 133 | static unsigned int *reg_max_ref_width; |
32131a9c | 134 | |
135eb61c | 135 | /* Element N is the list of insns that initialized reg N from its equivalent |
32131a9c | 136 | constant or memory slot. */ |
d7f88d86 BS |
137 | rtx *reg_equiv_init; |
138 | int reg_equiv_init_size; | |
32131a9c | 139 | |
03acd8f8 BS |
140 | /* Vector to remember old contents of reg_renumber before spilling. */ |
141 | static short *reg_old_renumber; | |
142 | ||
e6e52be0 | 143 | /* During reload_as_needed, element N contains the last pseudo regno reloaded |
03acd8f8 | 144 | into hard register N. If that pseudo reg occupied more than one register, |
32131a9c RK |
145 | reg_reloaded_contents points to that pseudo for each spill register in |
146 | use; all of these must remain set for an inheritance to occur. */ | |
147 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
148 | ||
149 | /* During reload_as_needed, element N contains the insn for which | |
e6e52be0 R |
150 | hard register N was last used. Its contents are significant only |
151 | when reg_reloaded_valid is set for this register. */ | |
32131a9c RK |
152 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; |
153 | ||
3eae4643 | 154 | /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */ |
e6e52be0 R |
155 | static HARD_REG_SET reg_reloaded_valid; |
156 | /* Indicate if the register was dead at the end of the reload. | |
157 | This is only valid if reg_reloaded_contents is set and valid. */ | |
158 | static HARD_REG_SET reg_reloaded_dead; | |
159 | ||
e3e9336f DJ |
160 | /* Indicate whether the register's current value is one that is not |
161 | safe to retain across a call, even for registers that are normally | |
fb959f72 | 162 | call-saved. This is only meaningful for members of reg_reloaded_valid. */ |
e3e9336f DJ |
163 | static HARD_REG_SET reg_reloaded_call_part_clobbered; |
164 | ||
32131a9c RK |
165 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ |
166 | static int n_spills; | |
167 | ||
168 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
169 | Holds the last rtx used for any given reg, or 0 if it has never | |
170 | been used for spilling yet. This rtx is reused, provided it has | |
171 | the proper mode. */ | |
172 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
173 | ||
174 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
175 | that was stored after the last time it was used. | |
176 | The precise value is the insn generated to do the store. */ | |
177 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
178 | ||
cb2afeb3 R |
179 | /* This is the register that was stored with spill_reg_store. This is a |
180 | copy of reload_out / reload_out_reg when the value was stored; if | |
181 | reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ | |
182 | static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; | |
183 | ||
32131a9c RK |
184 | /* This table is the inverse mapping of spill_regs: |
185 | indexed by hard reg number, | |
186 | it contains the position of that reg in spill_regs, | |
05d10675 | 187 | or -1 for something that is not in spill_regs. |
13c8e8e3 JL |
188 | |
189 | ?!? This is no longer accurate. */ | |
32131a9c RK |
190 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; |
191 | ||
03acd8f8 BS |
192 | /* This reg set indicates registers that can't be used as spill registers for |
193 | the currently processed insn. These are the hard registers which are live | |
194 | during the insn, but not allocated to pseudos, as well as fixed | |
195 | registers. */ | |
32131a9c RK |
196 | static HARD_REG_SET bad_spill_regs; |
197 | ||
03acd8f8 BS |
198 | /* These are the hard registers that can't be used as spill register for any |
199 | insn. This includes registers used for user variables and registers that | |
200 | we can't eliminate. A register that appears in this set also can't be used | |
201 | to retry register allocation. */ | |
202 | static HARD_REG_SET bad_spill_regs_global; | |
203 | ||
32131a9c | 204 | /* Describes order of use of registers for reloading |
03acd8f8 BS |
205 | of spilled pseudo-registers. `n_spills' is the number of |
206 | elements that are actually valid; new ones are added at the end. | |
207 | ||
208 | Both spill_regs and spill_reg_order are used on two occasions: | |
209 | once during find_reload_regs, where they keep track of the spill registers | |
210 | for a single insn, but also during reload_as_needed where they show all | |
211 | the registers ever used by reload. For the latter case, the information | |
212 | is calculated during finish_spills. */ | |
32131a9c RK |
213 | static short spill_regs[FIRST_PSEUDO_REGISTER]; |
214 | ||
03acd8f8 BS |
215 | /* This vector of reg sets indicates, for each pseudo, which hard registers |
216 | may not be used for retrying global allocation because the register was | |
217 | formerly spilled from one of them. If we allowed reallocating a pseudo to | |
218 | a register that it was already allocated to, reload might not | |
219 | terminate. */ | |
220 | static HARD_REG_SET *pseudo_previous_regs; | |
221 | ||
222 | /* This vector of reg sets indicates, for each pseudo, which hard | |
223 | registers may not be used for retrying global allocation because they | |
224 | are used as spill registers during one of the insns in which the | |
225 | pseudo is live. */ | |
226 | static HARD_REG_SET *pseudo_forbidden_regs; | |
227 | ||
228 | /* All hard regs that have been used as spill registers for any insn are | |
229 | marked in this set. */ | |
230 | static HARD_REG_SET used_spill_regs; | |
8b4f9969 | 231 | |
4079cd63 JW |
232 | /* Index of last register assigned as a spill register. We allocate in |
233 | a round-robin fashion. */ | |
4079cd63 JW |
234 | static int last_spill_reg; |
235 | ||
32131a9c RK |
236 | /* Nonzero if indirect addressing is supported on the machine; this means |
237 | that spilling (REG n) does not require reloading it into a register in | |
238 | order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The | |
239 | value indicates the level of indirect addressing supported, e.g., two | |
240 | means that (MEM (MEM (REG n))) is also valid if (REG n) does not get | |
241 | a hard register. */ | |
32131a9c RK |
242 | static char spill_indirect_levels; |
243 | ||
244 | /* Nonzero if indirect addressing is supported when the innermost MEM is | |
245 | of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to | |
6d2f8887 | 246 | which these are valid is the same as spill_indirect_levels, above. */ |
98af7219 | 247 | char indirect_symref_ok; |
32131a9c RK |
248 | |
249 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
32131a9c RK |
250 | char double_reg_address_ok; |
251 | ||
252 | /* Record the stack slot for each spilled hard register. */ | |
32131a9c RK |
253 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; |
254 | ||
255 | /* Width allocated so far for that stack slot. */ | |
770ae6cc | 256 | static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; |
32131a9c | 257 | |
7609e720 | 258 | /* Record which pseudos needed to be spilled. */ |
f5d8c9f4 BS |
259 | static regset_head spilled_pseudos; |
260 | ||
058e97ec VM |
261 | /* Record which pseudos changed their allocation in finish_spills. */ |
262 | static regset_head changed_allocation_pseudos; | |
263 | ||
f5d8c9f4 BS |
264 | /* Used for communication between order_regs_for_reload and count_pseudo. |
265 | Used to avoid counting one pseudo twice. */ | |
266 | static regset_head pseudos_counted; | |
7609e720 | 267 | |
32131a9c RK |
268 | /* First uid used by insns created by reload in this function. |
269 | Used in find_equiv_reg. */ | |
270 | int reload_first_uid; | |
271 | ||
272 | /* Flag set by local-alloc or global-alloc if anything is live in | |
273 | a call-clobbered reg across calls. */ | |
32131a9c RK |
274 | int caller_save_needed; |
275 | ||
276 | /* Set to 1 while reload_as_needed is operating. | |
277 | Required by some machines to handle any generated moves differently. */ | |
32131a9c RK |
278 | int reload_in_progress = 0; |
279 | ||
280 | /* These arrays record the insn_code of insns that may be needed to | |
281 | perform input and output reloads of special objects. They provide a | |
282 | place to pass a scratch register. */ | |
32131a9c RK |
283 | enum insn_code reload_in_optab[NUM_MACHINE_MODES]; |
284 | enum insn_code reload_out_optab[NUM_MACHINE_MODES]; | |
285 | ||
d45cf215 | 286 | /* This obstack is used for allocation of rtl during register elimination. |
32131a9c RK |
287 | The allocated storage can be freed once find_reloads has processed the |
288 | insn. */ | |
5983a90e | 289 | static struct obstack reload_obstack; |
cad6f7d0 BS |
290 | |
291 | /* Points to the beginning of the reload_obstack. All insn_chain structures | |
292 | are allocated first. */ | |
cf0fa607 | 293 | static char *reload_startobj; |
cad6f7d0 BS |
294 | |
295 | /* The point after all insn_chain structures. Used to quickly deallocate | |
f5d8c9f4 | 296 | memory allocated in copy_reloads during calculate_needs_all_insns. */ |
cf0fa607 | 297 | static char *reload_firstobj; |
32131a9c | 298 | |
f5d8c9f4 BS |
299 | /* This points before all local rtl generated by register elimination. |
300 | Used to quickly free all memory after processing one insn. */ | |
301 | static char *reload_insn_firstobj; | |
302 | ||
cad6f7d0 BS |
303 | /* List of insn_chain instructions, one for every insn that reload needs to |
304 | examine. */ | |
305 | struct insn_chain *reload_insn_chain; | |
7609e720 | 306 | |
03acd8f8 | 307 | /* List of all insns needing reloads. */ |
7609e720 | 308 | static struct insn_chain *insns_need_reload; |
32131a9c RK |
309 | \f |
310 | /* This structure is used to record information about register eliminations. | |
311 | Each array entry describes one possible way of eliminating a register | |
312 | in favor of another. If there is more than one way of eliminating a | |
313 | particular register, the most preferred should be specified first. */ | |
314 | ||
590cf94d | 315 | struct elim_table |
32131a9c | 316 | { |
0f41302f MS |
317 | int from; /* Register number to be eliminated. */ |
318 | int to; /* Register number used as replacement. */ | |
b19ee4bd | 319 | HOST_WIDE_INT initial_offset; /* Initial difference between values. */ |
272d0bee | 320 | int can_eliminate; /* Nonzero if this elimination can be done. */ |
7b5cbb57 AS |
321 | int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE |
322 | target hook in previous scan over insns | |
323 | made by reload. */ | |
b19ee4bd JJ |
324 | HOST_WIDE_INT offset; /* Current offset between the two regs. */ |
325 | HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */ | |
0f41302f | 326 | int ref_outside_mem; /* "to" has been referenced outside a MEM. */ |
32131a9c RK |
327 | rtx from_rtx; /* REG rtx for the register to be eliminated. |
328 | We cannot simply compare the number since | |
329 | we might then spuriously replace a hard | |
330 | register corresponding to a pseudo | |
0f41302f MS |
331 | assigned to the reg to be eliminated. */ |
332 | rtx to_rtx; /* REG rtx for the replacement. */ | |
590cf94d KG |
333 | }; |
334 | ||
1d7254c5 | 335 | static struct elim_table *reg_eliminate = 0; |
590cf94d KG |
336 | |
337 | /* This is an intermediate structure to initialize the table. It has | |
1d7254c5 | 338 | exactly the members provided by ELIMINABLE_REGS. */ |
0b5826ac | 339 | static const struct elim_table_1 |
590cf94d | 340 | { |
0b5826ac KG |
341 | const int from; |
342 | const int to; | |
590cf94d | 343 | } reg_eliminate_1[] = |
32131a9c RK |
344 | |
345 | /* If a set of eliminable registers was specified, define the table from it. | |
346 | Otherwise, default to the normal case of the frame pointer being | |
347 | replaced by the stack pointer. */ | |
348 | ||
349 | #ifdef ELIMINABLE_REGS | |
350 | ELIMINABLE_REGS; | |
351 | #else | |
352 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
353 | #endif | |
354 | ||
b6a1cbae | 355 | #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) |
32131a9c RK |
356 | |
357 | /* Record the number of pending eliminations that have an offset not equal | |
40f03658 | 358 | to their initial offset. If nonzero, we use a new copy of each |
32131a9c | 359 | replacement result in any insns encountered. */ |
cb2afeb3 | 360 | int num_not_at_initial_offset; |
32131a9c RK |
361 | |
362 | /* Count the number of registers that we may be able to eliminate. */ | |
363 | static int num_eliminable; | |
2b49ee39 R |
364 | /* And the number of registers that are equivalent to a constant that |
365 | can be eliminated to frame_pointer / arg_pointer + constant. */ | |
366 | static int num_eliminable_invariants; | |
32131a9c RK |
367 | |
368 | /* For each label, we record the offset of each elimination. If we reach | |
369 | a label by more than one path and an offset differs, we cannot do the | |
4cc0fdd2 JDA |
370 | elimination. This information is indexed by the difference of the |
371 | number of the label and the first label number. We can't offset the | |
372 | pointer itself as this can cause problems on machines with segmented | |
373 | memory. The first table is an array of flags that records whether we | |
374 | have yet encountered a label and the second table is an array of arrays, | |
375 | one entry in the latter array for each elimination. */ | |
376 | ||
377 | static int first_label_num; | |
32131a9c | 378 | static char *offsets_known_at; |
b19ee4bd | 379 | static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS]; |
32131a9c RK |
380 | |
381 | /* Number of labels in the current function. */ | |
382 | ||
383 | static int num_labels; | |
384 | \f | |
0c20a65f AJ |
385 | static void replace_pseudos_in (rtx *, enum machine_mode, rtx); |
386 | static void maybe_fix_stack_asms (void); | |
387 | static void copy_reloads (struct insn_chain *); | |
388 | static void calculate_needs_all_insns (int); | |
389 | static int find_reg (struct insn_chain *, int); | |
390 | static void find_reload_regs (struct insn_chain *); | |
391 | static void select_reload_regs (void); | |
392 | static void delete_caller_save_insns (void); | |
393 | ||
394 | static void spill_failure (rtx, enum reg_class); | |
395 | static void count_spilled_pseudo (int, int, int); | |
396 | static void delete_dead_insn (rtx); | |
058e97ec | 397 | static void alter_reg (int, int, bool); |
0c20a65f AJ |
398 | static void set_label_offsets (rtx, rtx, int); |
399 | static void check_eliminable_occurrences (rtx); | |
400 | static void elimination_effects (rtx, enum machine_mode); | |
401 | static int eliminate_regs_in_insn (rtx, int); | |
402 | static void update_eliminable_offsets (void); | |
7bc980e1 | 403 | static void mark_not_eliminable (rtx, const_rtx, void *); |
0c20a65f | 404 | static void set_initial_elim_offsets (void); |
9f938de1 | 405 | static bool verify_initial_elim_offsets (void); |
0c20a65f AJ |
406 | static void set_initial_label_offsets (void); |
407 | static void set_offsets_for_label (rtx); | |
408 | static void init_elim_table (void); | |
409 | static void update_eliminables (HARD_REG_SET *); | |
410 | static void spill_hard_reg (unsigned int, int); | |
411 | static int finish_spills (int); | |
0c20a65f AJ |
412 | static void scan_paradoxical_subregs (rtx); |
413 | static void count_pseudo (int); | |
414 | static void order_regs_for_reload (struct insn_chain *); | |
415 | static void reload_as_needed (int); | |
7bc980e1 | 416 | static void forget_old_reloads_1 (rtx, const_rtx, void *); |
db4c7386 | 417 | static void forget_marked_reloads (regset); |
0c20a65f AJ |
418 | static int reload_reg_class_lower (const void *, const void *); |
419 | static void mark_reload_reg_in_use (unsigned int, int, enum reload_type, | |
420 | enum machine_mode); | |
421 | static void clear_reload_reg_in_use (unsigned int, int, enum reload_type, | |
422 | enum machine_mode); | |
423 | static int reload_reg_free_p (unsigned int, int, enum reload_type); | |
424 | static int reload_reg_free_for_value_p (int, int, int, enum reload_type, | |
425 | rtx, rtx, int, int); | |
426 | static int free_for_value_p (int, enum machine_mode, int, enum reload_type, | |
427 | rtx, rtx, int, int); | |
428 | static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type); | |
429 | static int allocate_reload_reg (struct insn_chain *, int, int); | |
430 | static int conflicts_with_override (rtx); | |
431 | static void failed_reload (rtx, int); | |
432 | static int set_reload_reg (int, int); | |
433 | static void choose_reload_regs_init (struct insn_chain *, rtx *); | |
434 | static void choose_reload_regs (struct insn_chain *); | |
435 | static void merge_assigned_reloads (rtx); | |
436 | static void emit_input_reload_insns (struct insn_chain *, struct reload *, | |
437 | rtx, int); | |
438 | static void emit_output_reload_insns (struct insn_chain *, struct reload *, | |
439 | int); | |
440 | static void do_input_reload (struct insn_chain *, struct reload *, int); | |
441 | static void do_output_reload (struct insn_chain *, struct reload *, int); | |
442 | static void emit_reload_insns (struct insn_chain *); | |
fb959f72 | 443 | static void delete_output_reload (rtx, int, int, rtx); |
0c20a65f AJ |
444 | static void delete_address_reloads (rtx, rtx); |
445 | static void delete_address_reloads_1 (rtx, rtx, rtx); | |
446 | static rtx inc_for_reload (rtx, rtx, rtx, int); | |
2dfa9a87 | 447 | #ifdef AUTO_INC_DEC |
0c20a65f | 448 | static void add_auto_inc_notes (rtx, rtx); |
2dfa9a87 | 449 | #endif |
058e97ec VM |
450 | static void substitute (rtx *, const_rtx, rtx); |
451 | static bool gen_reload_chain_without_interm_reg_p (int, int); | |
bf9a0db3 KH |
452 | static int reloads_conflict (int, int); |
453 | static rtx gen_reload (rtx, rtx, int, enum reload_type); | |
ff0d9879 | 454 | static rtx emit_insn_if_valid_for_reload (rtx); |
32131a9c | 455 | \f |
b5deb7b6 SL |
456 | /* Initialize the reload pass. This is called at the beginning of compilation |
457 | and may be called again if the target is reinitialized. */ | |
546b63fb | 458 | |
32131a9c | 459 | void |
0c20a65f | 460 | init_reload (void) |
32131a9c | 461 | { |
b3694847 | 462 | int i; |
32131a9c RK |
463 | |
464 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
465 | Set spill_indirect_levels to the number of levels such addressing is | |
466 | permitted, zero if it is not permitted at all. */ | |
467 | ||
b3694847 | 468 | rtx tem |
38a448ca RH |
469 | = gen_rtx_MEM (Pmode, |
470 | gen_rtx_PLUS (Pmode, | |
c5c76735 JL |
471 | gen_rtx_REG (Pmode, |
472 | LAST_VIRTUAL_REGISTER + 1), | |
38a448ca | 473 | GEN_INT (4))); |
32131a9c RK |
474 | spill_indirect_levels = 0; |
475 | ||
476 | while (memory_address_p (QImode, tem)) | |
477 | { | |
478 | spill_indirect_levels++; | |
38a448ca | 479 | tem = gen_rtx_MEM (Pmode, tem); |
32131a9c RK |
480 | } |
481 | ||
482 | /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ | |
483 | ||
38a448ca | 484 | tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); |
32131a9c RK |
485 | indirect_symref_ok = memory_address_p (QImode, tem); |
486 | ||
487 | /* See if reg+reg is a valid (and offsettable) address. */ | |
488 | ||
65701fd2 | 489 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
57caa638 | 490 | { |
38a448ca RH |
491 | tem = gen_rtx_PLUS (Pmode, |
492 | gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), | |
493 | gen_rtx_REG (Pmode, i)); | |
c5c76735 | 494 | |
57caa638 RS |
495 | /* This way, we make sure that reg+reg is an offsettable address. */ |
496 | tem = plus_constant (tem, 4); | |
497 | ||
498 | if (memory_address_p (QImode, tem)) | |
499 | { | |
500 | double_reg_address_ok = 1; | |
501 | break; | |
502 | } | |
503 | } | |
32131a9c | 504 | |
0f41302f | 505 | /* Initialize obstack for our rtl allocation. */ |
32131a9c | 506 | gcc_obstack_init (&reload_obstack); |
1634b18f | 507 | reload_startobj = XOBNEWVAR (&reload_obstack, char, 0); |
f5d8c9f4 BS |
508 | |
509 | INIT_REG_SET (&spilled_pseudos); | |
058e97ec | 510 | INIT_REG_SET (&changed_allocation_pseudos); |
f5d8c9f4 | 511 | INIT_REG_SET (&pseudos_counted); |
32131a9c RK |
512 | } |
513 | ||
cad6f7d0 BS |
514 | /* List of insn chains that are currently unused. */ |
515 | static struct insn_chain *unused_insn_chains = 0; | |
516 | ||
517 | /* Allocate an empty insn_chain structure. */ | |
518 | struct insn_chain * | |
0c20a65f | 519 | new_insn_chain (void) |
cad6f7d0 BS |
520 | { |
521 | struct insn_chain *c; | |
522 | ||
523 | if (unused_insn_chains == 0) | |
524 | { | |
1634b18f | 525 | c = XOBNEW (&reload_obstack, struct insn_chain); |
239a0f5b BS |
526 | INIT_REG_SET (&c->live_throughout); |
527 | INIT_REG_SET (&c->dead_or_set); | |
cad6f7d0 BS |
528 | } |
529 | else | |
530 | { | |
531 | c = unused_insn_chains; | |
532 | unused_insn_chains = c->next; | |
533 | } | |
534 | c->is_caller_save_insn = 0; | |
03acd8f8 | 535 | c->need_operand_change = 0; |
cad6f7d0 BS |
536 | c->need_reload = 0; |
537 | c->need_elim = 0; | |
538 | return c; | |
539 | } | |
540 | ||
7609e720 BS |
541 | /* Small utility function to set all regs in hard reg set TO which are |
542 | allocated to pseudos in regset FROM. */ | |
770ae6cc | 543 | |
7609e720 | 544 | void |
0c20a65f | 545 | compute_use_by_pseudos (HARD_REG_SET *to, regset from) |
7609e720 | 546 | { |
770ae6cc | 547 | unsigned int regno; |
a2041967 | 548 | reg_set_iterator rsi; |
770ae6cc | 549 | |
a2041967 KH |
550 | EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi) |
551 | { | |
552 | int r = reg_renumber[regno]; | |
a2041967 KH |
553 | |
554 | if (r < 0) | |
555 | { | |
058e97ec VM |
556 | /* reload_combine uses the information from DF_LIVE_IN, |
557 | which might still contain registers that have not | |
558 | actually been allocated since they have an | |
559 | equivalence. */ | |
2af2dbdc | 560 | gcc_assert (ira_conflicts_p || reload_completed); |
a2041967 KH |
561 | } |
562 | else | |
09e18274 | 563 | add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r); |
a2041967 | 564 | } |
7609e720 | 565 | } |
f474c6f8 AO |
566 | |
567 | /* Replace all pseudos found in LOC with their corresponding | |
568 | equivalences. */ | |
569 | ||
570 | static void | |
0c20a65f | 571 | replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage) |
f474c6f8 AO |
572 | { |
573 | rtx x = *loc; | |
574 | enum rtx_code code; | |
575 | const char *fmt; | |
576 | int i, j; | |
577 | ||
578 | if (! x) | |
579 | return; | |
174fa2c4 | 580 | |
f474c6f8 AO |
581 | code = GET_CODE (x); |
582 | if (code == REG) | |
583 | { | |
ae0ed63a | 584 | unsigned int regno = REGNO (x); |
086fef9e AO |
585 | |
586 | if (regno < FIRST_PSEUDO_REGISTER) | |
f474c6f8 AO |
587 | return; |
588 | ||
589 | x = eliminate_regs (x, mem_mode, usage); | |
590 | if (x != *loc) | |
591 | { | |
592 | *loc = x; | |
ee960939 | 593 | replace_pseudos_in (loc, mem_mode, usage); |
f474c6f8 AO |
594 | return; |
595 | } | |
596 | ||
086fef9e AO |
597 | if (reg_equiv_constant[regno]) |
598 | *loc = reg_equiv_constant[regno]; | |
599 | else if (reg_equiv_mem[regno]) | |
600 | *loc = reg_equiv_mem[regno]; | |
601 | else if (reg_equiv_address[regno]) | |
602 | *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]); | |
f474c6f8 | 603 | else |
41374e13 NS |
604 | { |
605 | gcc_assert (!REG_P (regno_reg_rtx[regno]) | |
606 | || REGNO (regno_reg_rtx[regno]) != regno); | |
607 | *loc = regno_reg_rtx[regno]; | |
608 | } | |
f474c6f8 AO |
609 | |
610 | return; | |
611 | } | |
612 | else if (code == MEM) | |
613 | { | |
ee960939 | 614 | replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage); |
f474c6f8 AO |
615 | return; |
616 | } | |
174fa2c4 | 617 | |
f474c6f8 AO |
618 | /* Process each of our operands recursively. */ |
619 | fmt = GET_RTX_FORMAT (code); | |
620 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
621 | if (*fmt == 'e') | |
ee960939 | 622 | replace_pseudos_in (&XEXP (x, i), mem_mode, usage); |
f474c6f8 AO |
623 | else if (*fmt == 'E') |
624 | for (j = 0; j < XVECLEN (x, i); j++) | |
ee960939 | 625 | replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage); |
f474c6f8 AO |
626 | } |
627 | ||
ecaebb9e NS |
628 | /* Determine if the current function has an exception receiver block |
629 | that reaches the exit block via non-exceptional edges */ | |
630 | ||
631 | static bool | |
632 | has_nonexceptional_receiver (void) | |
633 | { | |
634 | edge e; | |
635 | edge_iterator ei; | |
636 | basic_block *tos, *worklist, bb; | |
637 | ||
638 | /* If we're not optimizing, then just err on the safe side. */ | |
639 | if (!optimize) | |
640 | return true; | |
641 | ||
642 | /* First determine which blocks can reach exit via normal paths. */ | |
1634b18f | 643 | tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1); |
ecaebb9e NS |
644 | |
645 | FOR_EACH_BB (bb) | |
646 | bb->flags &= ~BB_REACHABLE; | |
647 | ||
648 | /* Place the exit block on our worklist. */ | |
649 | EXIT_BLOCK_PTR->flags |= BB_REACHABLE; | |
650 | *tos++ = EXIT_BLOCK_PTR; | |
651 | ||
652 | /* Iterate: find everything reachable from what we've already seen. */ | |
653 | while (tos != worklist) | |
654 | { | |
655 | bb = *--tos; | |
656 | ||
657 | FOR_EACH_EDGE (e, ei, bb->preds) | |
658 | if (!(e->flags & EDGE_ABNORMAL)) | |
659 | { | |
660 | basic_block src = e->src; | |
661 | ||
662 | if (!(src->flags & BB_REACHABLE)) | |
663 | { | |
664 | src->flags |= BB_REACHABLE; | |
665 | *tos++ = src; | |
666 | } | |
667 | } | |
668 | } | |
669 | free (worklist); | |
670 | ||
671 | /* Now see if there's a reachable block with an exceptional incoming | |
672 | edge. */ | |
673 | FOR_EACH_BB (bb) | |
674 | if (bb->flags & BB_REACHABLE) | |
675 | FOR_EACH_EDGE (e, ei, bb->preds) | |
676 | if (e->flags & EDGE_ABNORMAL) | |
677 | return true; | |
678 | ||
679 | /* No exceptional block reached exit unexceptionally. */ | |
680 | return false; | |
681 | } | |
682 | ||
03acd8f8 | 683 | \f |
1e5bd841 BS |
684 | /* Global variables used by reload and its subroutines. */ |
685 | ||
1e5bd841 BS |
686 | /* Set during calculate_needs if an insn needs register elimination. */ |
687 | static int something_needs_elimination; | |
cb2afeb3 | 688 | /* Set during calculate_needs if an insn needs an operand changed. */ |
cf0fa607 | 689 | static int something_needs_operands_changed; |
1e5bd841 | 690 | |
1e5bd841 BS |
691 | /* Nonzero means we couldn't get enough spill regs. */ |
692 | static int failure; | |
693 | ||
058e97ec VM |
694 | /* Temporary array of pseudo-register number. */ |
695 | static int *temp_pseudo_reg_arr; | |
696 | ||
546b63fb | 697 | /* Main entry point for the reload pass. |
32131a9c RK |
698 | |
699 | FIRST is the first insn of the function being compiled. | |
700 | ||
701 | GLOBAL nonzero means we were called from global_alloc | |
702 | and should attempt to reallocate any pseudoregs that we | |
703 | displace from hard regs we will use for reloads. | |
704 | If GLOBAL is zero, we do not have enough information to do that, | |
705 | so any pseudo reg that is spilled must go to the stack. | |
706 | ||
5352b11a RS |
707 | Return value is nonzero if reload failed |
708 | and we must not do any more for this function. */ | |
709 | ||
710 | int | |
0c20a65f | 711 | reload (rtx first, int global) |
32131a9c | 712 | { |
058e97ec | 713 | int i, n; |
ba4807a0 | 714 | rtx insn; |
b3694847 | 715 | struct elim_table *ep; |
e0082a72 | 716 | basic_block bb; |
32131a9c | 717 | |
32131a9c RK |
718 | /* Make sure even insns with volatile mem refs are recognizable. */ |
719 | init_recog (); | |
720 | ||
1e5bd841 BS |
721 | failure = 0; |
722 | ||
1634b18f | 723 | reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0); |
cad6f7d0 | 724 | |
437a710d BS |
725 | /* Make sure that the last insn in the chain |
726 | is not something that needs reloading. */ | |
2e040219 | 727 | emit_note (NOTE_INSN_DELETED); |
437a710d | 728 | |
32131a9c RK |
729 | /* Enable find_equiv_reg to distinguish insns made by reload. */ |
730 | reload_first_uid = get_max_uid (); | |
731 | ||
0dadecf6 RK |
732 | #ifdef SECONDARY_MEMORY_NEEDED |
733 | /* Initialize the secondary memory table. */ | |
734 | clear_secondary_mem (); | |
735 | #endif | |
736 | ||
32131a9c | 737 | /* We don't have a stack slot for any spill reg yet. */ |
703ad42b KG |
738 | memset (spill_stack_slot, 0, sizeof spill_stack_slot); |
739 | memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width); | |
32131a9c | 740 | |
a8efe40d RK |
741 | /* Initialize the save area information for caller-save, in case some |
742 | are needed. */ | |
743 | init_save_areas (); | |
a8fdc208 | 744 | |
32131a9c RK |
745 | /* Compute which hard registers are now in use |
746 | as homes for pseudo registers. | |
747 | This is done here rather than (eg) in global_alloc | |
748 | because this point is reached even if not optimizing. */ | |
32131a9c RK |
749 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
750 | mark_home_live (i); | |
751 | ||
ecaebb9e NS |
752 | /* A function that has a nonlocal label that can reach the exit |
753 | block via non-exceptional paths must save all call-saved | |
8dddd002 | 754 | registers. */ |
e3b5732b | 755 | if (cfun->has_nonlocal_label |
215161e2 | 756 | && has_nonexceptional_receiver ()) |
e3b5732b | 757 | crtl->saves_all_registers = 1; |
215161e2 | 758 | |
e3b5732b | 759 | if (crtl->saves_all_registers) |
8dddd002 | 760 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
2a3e384f | 761 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) |
6fb5fa3c | 762 | df_set_regs_ever_live (i, true); |
8dddd002 | 763 | |
32131a9c RK |
764 | /* Find all the pseudo registers that didn't get hard regs |
765 | but do have known equivalent constants or memory slots. | |
766 | These include parameters (known equivalent to parameter slots) | |
767 | and cse'd or loop-moved constant memory addresses. | |
768 | ||
769 | Record constant equivalents in reg_equiv_constant | |
770 | so they will be substituted by find_reloads. | |
771 | Record memory equivalents in reg_mem_equiv so they can | |
772 | be substituted eventually by altering the REG-rtx's. */ | |
773 | ||
5ed6ace5 MD |
774 | reg_equiv_constant = XCNEWVEC (rtx, max_regno); |
775 | reg_equiv_invariant = XCNEWVEC (rtx, max_regno); | |
776 | reg_equiv_mem = XCNEWVEC (rtx, max_regno); | |
3f1e3e70 | 777 | reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno); |
5ed6ace5 MD |
778 | reg_equiv_address = XCNEWVEC (rtx, max_regno); |
779 | reg_max_ref_width = XCNEWVEC (unsigned int, max_regno); | |
780 | reg_old_renumber = XCNEWVEC (short, max_regno); | |
4e135bdd | 781 | memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); |
5ed6ace5 MD |
782 | pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno); |
783 | pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno); | |
32131a9c | 784 | |
03acd8f8 | 785 | CLEAR_HARD_REG_SET (bad_spill_regs_global); |
56f58d3a | 786 | |
d754127f ILT |
787 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent |
788 | to. Also find all paradoxical subregs and find largest such for | |
789 | each pseudo. */ | |
32131a9c | 790 | |
2b49ee39 | 791 | num_eliminable_invariants = 0; |
32131a9c RK |
792 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
793 | { | |
794 | rtx set = single_set (insn); | |
795 | ||
3d17d93d AO |
796 | /* We may introduce USEs that we want to remove at the end, so |
797 | we'll mark them with QImode. Make sure there are no | |
798 | previously-marked insns left by say regmove. */ | |
799 | if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE | |
800 | && GET_MODE (insn) != VOIDmode) | |
801 | PUT_MODE (insn, VOIDmode); | |
802 | ||
b5b8b0ac | 803 | if (NONDEBUG_INSN_P (insn)) |
d7f88d86 BS |
804 | scan_paradoxical_subregs (PATTERN (insn)); |
805 | ||
f8cfc6aa | 806 | if (set != 0 && REG_P (SET_DEST (set))) |
32131a9c | 807 | { |
fb3821f7 | 808 | rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
d7f88d86 BS |
809 | rtx x; |
810 | ||
811 | if (! note) | |
812 | continue; | |
813 | ||
814 | i = REGNO (SET_DEST (set)); | |
815 | x = XEXP (note, 0); | |
816 | ||
817 | if (i <= LAST_VIRTUAL_REGISTER) | |
818 | continue; | |
819 | ||
820 | if (! function_invariant_p (x) | |
821 | || ! flag_pic | |
822 | /* A function invariant is often CONSTANT_P but may | |
823 | include a register. We promise to only pass | |
824 | CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ | |
825 | || (CONSTANT_P (x) | |
826 | && LEGITIMATE_PIC_OPERAND_P (x))) | |
32131a9c | 827 | { |
d7f88d86 BS |
828 | /* It can happen that a REG_EQUIV note contains a MEM |
829 | that is not a legitimate memory operand. As later | |
830 | stages of reload assume that all addresses found | |
831 | in the reg_equiv_* arrays were originally legitimate, | |
832 | we ignore such REG_EQUIV notes. */ | |
833 | if (memory_operand (x, VOIDmode)) | |
32131a9c | 834 | { |
d7f88d86 BS |
835 | /* Always unshare the equivalence, so we can |
836 | substitute into this insn without touching the | |
837 | equivalence. */ | |
838 | reg_equiv_memory_loc[i] = copy_rtx (x); | |
839 | } | |
840 | else if (function_invariant_p (x)) | |
841 | { | |
842 | if (GET_CODE (x) == PLUS) | |
956d6950 | 843 | { |
d7f88d86 BS |
844 | /* This is PLUS of frame pointer and a constant, |
845 | and might be shared. Unshare it. */ | |
ab156144 | 846 | reg_equiv_invariant[i] = copy_rtx (x); |
d7f88d86 | 847 | num_eliminable_invariants++; |
956d6950 | 848 | } |
ab156144 | 849 | else if (x == frame_pointer_rtx || x == arg_pointer_rtx) |
32131a9c | 850 | { |
ab156144 | 851 | reg_equiv_invariant[i] = x; |
d7f88d86 | 852 | num_eliminable_invariants++; |
32131a9c | 853 | } |
d7f88d86 BS |
854 | else if (LEGITIMATE_CONSTANT_P (x)) |
855 | reg_equiv_constant[i] = x; | |
32131a9c | 856 | else |
d7f88d86 BS |
857 | { |
858 | reg_equiv_memory_loc[i] | |
859 | = force_const_mem (GET_MODE (SET_DEST (set)), x); | |
860 | if (! reg_equiv_memory_loc[i]) | |
861 | reg_equiv_init[i] = NULL_RTX; | |
862 | } | |
863 | } | |
864 | else | |
865 | { | |
866 | reg_equiv_init[i] = NULL_RTX; | |
867 | continue; | |
32131a9c RK |
868 | } |
869 | } | |
d7f88d86 BS |
870 | else |
871 | reg_equiv_init[i] = NULL_RTX; | |
32131a9c | 872 | } |
32131a9c RK |
873 | } |
874 | ||
d7f88d86 BS |
875 | if (dump_file) |
876 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
877 | if (reg_equiv_init[i]) | |
878 | { | |
879 | fprintf (dump_file, "init_insns for %u: ", i); | |
880 | print_inline_rtx (dump_file, reg_equiv_init[i], 20); | |
881 | fprintf (dump_file, "\n"); | |
882 | } | |
883 | ||
09dd1133 | 884 | init_elim_table (); |
32131a9c | 885 | |
4cc0fdd2 JDA |
886 | first_label_num = get_first_label_num (); |
887 | num_labels = max_label_num () - first_label_num; | |
32131a9c RK |
888 | |
889 | /* Allocate the tables used to store offset information at labels. */ | |
a68d4b75 BK |
890 | /* We used to use alloca here, but the size of what it would try to |
891 | allocate would occasionally cause it to exceed the stack limit and | |
892 | cause a core dump. */ | |
5ed6ace5 MD |
893 | offsets_known_at = XNEWVEC (char, num_labels); |
894 | offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT)); | |
32131a9c | 895 | |
058e97ec VM |
896 | /* Alter each pseudo-reg rtx to contain its hard reg number. Assign |
897 | stack slots to the pseudos that lack hard regs or equivalents. | |
32131a9c RK |
898 | Do not touch virtual registers. */ |
899 | ||
058e97ec VM |
900 | temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1); |
901 | for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) | |
902 | temp_pseudo_reg_arr[n++] = i; | |
903 | ||
2af2dbdc | 904 | if (ira_conflicts_p) |
058e97ec VM |
905 | /* Ask IRA to order pseudo-registers for better stack slot |
906 | sharing. */ | |
907 | ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width); | |
908 | ||
909 | for (i = 0; i < n; i++) | |
910 | alter_reg (temp_pseudo_reg_arr[i], -1, false); | |
32131a9c | 911 | |
32131a9c RK |
912 | /* If we have some registers we think can be eliminated, scan all insns to |
913 | see if there is an insn that sets one of these registers to something | |
914 | other than itself plus a constant. If so, the register cannot be | |
915 | eliminated. Doing this scan here eliminates an extra pass through the | |
916 | main reload loop in the most common case where register elimination | |
917 | cannot be done. */ | |
918 | for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) | |
4b4bf941 | 919 | if (INSN_P (insn)) |
84832317 | 920 | note_stores (PATTERN (insn), mark_not_eliminable, NULL); |
32131a9c | 921 | |
18a90182 BS |
922 | maybe_fix_stack_asms (); |
923 | ||
03acd8f8 BS |
924 | insns_need_reload = 0; |
925 | something_needs_elimination = 0; | |
05d10675 | 926 | |
4079cd63 JW |
927 | /* Initialize to -1, which means take the first spill register. */ |
928 | last_spill_reg = -1; | |
929 | ||
32131a9c | 930 | /* Spill any hard regs that we know we can't eliminate. */ |
03acd8f8 | 931 | CLEAR_HARD_REG_SET (used_spill_regs); |
4ab51fb5 R |
932 | /* There can be multiple ways to eliminate a register; |
933 | they should be listed adjacently. | |
934 | Elimination for any register fails only if all possible ways fail. */ | |
935 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ) | |
936 | { | |
937 | int from = ep->from; | |
938 | int can_eliminate = 0; | |
939 | do | |
940 | { | |
941 | can_eliminate |= ep->can_eliminate; | |
942 | ep++; | |
943 | } | |
944 | while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from); | |
945 | if (! can_eliminate) | |
946 | spill_hard_reg (from, 1); | |
947 | } | |
9ff3516a RK |
948 | |
949 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
950 | if (frame_pointer_needed) | |
e04ca094 | 951 | spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1); |
9ff3516a | 952 | #endif |
e04ca094 | 953 | finish_spills (global); |
7609e720 | 954 | |
f1db3576 JL |
955 | /* From now on, we may need to generate moves differently. We may also |
956 | allow modifications of insns which cause them to not be recognized. | |
957 | Any such modifications will be cleaned up during reload itself. */ | |
b2f15f94 RK |
958 | reload_in_progress = 1; |
959 | ||
32131a9c RK |
960 | /* This loop scans the entire function each go-round |
961 | and repeats until one repetition spills no additional hard regs. */ | |
03acd8f8 | 962 | for (;;) |
32131a9c | 963 | { |
03acd8f8 BS |
964 | int something_changed; |
965 | int did_spill; | |
03acd8f8 | 966 | HOST_WIDE_INT starting_frame_size; |
32131a9c | 967 | |
7657bf2f JW |
968 | starting_frame_size = get_frame_size (); |
969 | ||
09dd1133 | 970 | set_initial_elim_offsets (); |
1f3b1e1a | 971 | set_initial_label_offsets (); |
03acd8f8 | 972 | |
32131a9c RK |
973 | /* For each pseudo register that has an equivalent location defined, |
974 | try to eliminate any eliminable registers (such as the frame pointer) | |
975 | assuming initial offsets for the replacement register, which | |
976 | is the normal case. | |
977 | ||
978 | If the resulting location is directly addressable, substitute | |
979 | the MEM we just got directly for the old REG. | |
980 | ||
981 | If it is not addressable but is a constant or the sum of a hard reg | |
982 | and constant, it is probably not addressable because the constant is | |
983 | out of range, in that case record the address; we will generate | |
984 | hairy code to compute the address in a register each time it is | |
6491dbbb RK |
985 | needed. Similarly if it is a hard register, but one that is not |
986 | valid as an address register. | |
32131a9c RK |
987 | |
988 | If the location is not addressable, but does not have one of the | |
989 | above forms, assign a stack slot. We have to do this to avoid the | |
990 | potential of producing lots of reloads if, e.g., a location involves | |
991 | a pseudo that didn't get a hard register and has an equivalent memory | |
992 | location that also involves a pseudo that didn't get a hard register. | |
993 | ||
994 | Perhaps at some point we will improve reload_when_needed handling | |
995 | so this problem goes away. But that's very hairy. */ | |
996 | ||
997 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
998 | if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) | |
999 | { | |
bbbbb16a ILT |
1000 | rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode, |
1001 | NULL_RTX); | |
32131a9c | 1002 | |
09e881c9 BE |
1003 | if (strict_memory_address_addr_space_p |
1004 | (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0), | |
1005 | MEM_ADDR_SPACE (x))) | |
32131a9c | 1006 | reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; |
1f663989 | 1007 | else if (CONSTANT_P (XEXP (x, 0)) |
f8cfc6aa | 1008 | || (REG_P (XEXP (x, 0)) |
6491dbbb | 1009 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) |
32131a9c | 1010 | || (GET_CODE (XEXP (x, 0)) == PLUS |
f8cfc6aa | 1011 | && REG_P (XEXP (XEXP (x, 0), 0)) |
32131a9c RK |
1012 | && (REGNO (XEXP (XEXP (x, 0), 0)) |
1013 | < FIRST_PSEUDO_REGISTER) | |
1f663989 | 1014 | && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) |
32131a9c RK |
1015 | reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; |
1016 | else | |
1017 | { | |
1018 | /* Make a new stack slot. Then indicate that something | |
a8fdc208 | 1019 | changed so we go back and recompute offsets for |
32131a9c RK |
1020 | eliminable registers because the allocation of memory |
1021 | below might change some offset. reg_equiv_{mem,address} | |
1022 | will be set up for this pseudo on the next pass around | |
1023 | the loop. */ | |
1024 | reg_equiv_memory_loc[i] = 0; | |
1025 | reg_equiv_init[i] = 0; | |
058e97ec | 1026 | alter_reg (i, -1, true); |
32131a9c RK |
1027 | } |
1028 | } | |
a8fdc208 | 1029 | |
437a710d BS |
1030 | if (caller_save_needed) |
1031 | setup_save_areas (); | |
1032 | ||
03acd8f8 | 1033 | /* If we allocated another stack slot, redo elimination bookkeeping. */ |
437a710d | 1034 | if (starting_frame_size != get_frame_size ()) |
32131a9c | 1035 | continue; |
cb91fab0 | 1036 | if (starting_frame_size && crtl->stack_alignment_needed) |
970af867 NS |
1037 | { |
1038 | /* If we have a stack frame, we must align it now. The | |
1039 | stack size may be a part of the offset computation for | |
1040 | register elimination. So if this changes the stack size, | |
1041 | then repeat the elimination bookkeeping. We don't | |
1042 | realign when there is no stack, as that will cause a | |
1043 | stack frame when none is needed should | |
1044 | STARTING_FRAME_OFFSET not be already aligned to | |
1045 | STACK_BOUNDARY. */ | |
cb91fab0 | 1046 | assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed); |
970af867 NS |
1047 | if (starting_frame_size != get_frame_size ()) |
1048 | continue; | |
1049 | } | |
32131a9c | 1050 | |
437a710d | 1051 | if (caller_save_needed) |
a8efe40d | 1052 | { |
437a710d BS |
1053 | save_call_clobbered_regs (); |
1054 | /* That might have allocated new insn_chain structures. */ | |
1634b18f | 1055 | reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0); |
a8efe40d RK |
1056 | } |
1057 | ||
03acd8f8 BS |
1058 | calculate_needs_all_insns (global); |
1059 | ||
2af2dbdc | 1060 | if (! ira_conflicts_p) |
058e97ec VM |
1061 | /* Don't do it for IRA. We need this info because we don't |
1062 | change live_throughout and dead_or_set for chains when IRA | |
1063 | is used. */ | |
1064 | CLEAR_REG_SET (&spilled_pseudos); | |
1065 | ||
03acd8f8 BS |
1066 | did_spill = 0; |
1067 | ||
1068 | something_changed = 0; | |
32131a9c | 1069 | |
0dadecf6 RK |
1070 | /* If we allocated any new memory locations, make another pass |
1071 | since it might have changed elimination offsets. */ | |
1072 | if (starting_frame_size != get_frame_size ()) | |
1073 | something_changed = 1; | |
1074 | ||
9f938de1 UW |
1075 | /* Even if the frame size remained the same, we might still have |
1076 | changed elimination offsets, e.g. if find_reloads called | |
1077 | force_const_mem requiring the back end to allocate a constant | |
1078 | pool base register that needs to be saved on the stack. */ | |
1079 | else if (!verify_initial_elim_offsets ()) | |
1080 | something_changed = 1; | |
1081 | ||
09dd1133 BS |
1082 | { |
1083 | HARD_REG_SET to_spill; | |
1084 | CLEAR_HARD_REG_SET (to_spill); | |
1085 | update_eliminables (&to_spill); | |
247140ea | 1086 | AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill); |
184f4c56 | 1087 | |
09dd1133 BS |
1088 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1089 | if (TEST_HARD_REG_BIT (to_spill, i)) | |
32131a9c | 1090 | { |
e04ca094 | 1091 | spill_hard_reg (i, 1); |
03acd8f8 | 1092 | did_spill = 1; |
8f5db3c1 JL |
1093 | |
1094 | /* Regardless of the state of spills, if we previously had | |
e591c83d | 1095 | a register that we thought we could eliminate, but now can |
8f5db3c1 JL |
1096 | not eliminate, we must run another pass. |
1097 | ||
1098 | Consider pseudos which have an entry in reg_equiv_* which | |
1099 | reference an eliminable register. We must make another pass | |
1100 | to update reg_equiv_* so that we do not substitute in the | |
1101 | old value from when we thought the elimination could be | |
1102 | performed. */ | |
1103 | something_changed = 1; | |
32131a9c | 1104 | } |
09dd1133 | 1105 | } |
9ff3516a | 1106 | |
e04ca094 | 1107 | select_reload_regs (); |
e483bf9c BS |
1108 | if (failure) |
1109 | goto failed; | |
437a710d | 1110 | |
e483bf9c | 1111 | if (insns_need_reload != 0 || did_spill) |
e04ca094 | 1112 | something_changed |= finish_spills (global); |
7609e720 | 1113 | |
03acd8f8 BS |
1114 | if (! something_changed) |
1115 | break; | |
1116 | ||
1117 | if (caller_save_needed) | |
7609e720 | 1118 | delete_caller_save_insns (); |
f5d8c9f4 BS |
1119 | |
1120 | obstack_free (&reload_obstack, reload_firstobj); | |
32131a9c RK |
1121 | } |
1122 | ||
1123 | /* If global-alloc was run, notify it of any register eliminations we have | |
1124 | done. */ | |
1125 | if (global) | |
1126 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1127 | if (ep->can_eliminate) | |
1128 | mark_elimination (ep->from, ep->to); | |
1129 | ||
32131a9c RK |
1130 | /* If a pseudo has no hard reg, delete the insns that made the equivalence. |
1131 | If that insn didn't set the register (i.e., it copied the register to | |
1132 | memory), just delete that insn instead of the equivalencing insn plus | |
1133 | anything now dead. If we call delete_dead_insn on that insn, we may | |
135eb61c | 1134 | delete the insn that actually sets the register if the register dies |
32131a9c RK |
1135 | there and that is incorrect. */ |
1136 | ||
1137 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
135eb61c R |
1138 | { |
1139 | if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) | |
1140 | { | |
1141 | rtx list; | |
1142 | for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) | |
1143 | { | |
1144 | rtx equiv_insn = XEXP (list, 0); | |
78571511 RK |
1145 | |
1146 | /* If we already deleted the insn or if it may trap, we can't | |
1147 | delete it. The latter case shouldn't happen, but can | |
1148 | if an insn has a variable address, gets a REG_EH_REGION | |
569b7f6a | 1149 | note added to it, and then gets converted into a load |
78571511 | 1150 | from a constant address. */ |
4b4bf941 | 1151 | if (NOTE_P (equiv_insn) |
78571511 RK |
1152 | || can_throw_internal (equiv_insn)) |
1153 | ; | |
1154 | else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) | |
135eb61c R |
1155 | delete_dead_insn (equiv_insn); |
1156 | else | |
6773e15f | 1157 | SET_INSN_DELETED (equiv_insn); |
135eb61c R |
1158 | } |
1159 | } | |
1160 | } | |
32131a9c RK |
1161 | |
1162 | /* Use the reload registers where necessary | |
1163 | by generating move instructions to move the must-be-register | |
1164 | values into or out of the reload registers. */ | |
1165 | ||
03acd8f8 BS |
1166 | if (insns_need_reload != 0 || something_needs_elimination |
1167 | || something_needs_operands_changed) | |
c47f5ea5 | 1168 | { |
102870fb | 1169 | HOST_WIDE_INT old_frame_size = get_frame_size (); |
c47f5ea5 | 1170 | |
e04ca094 | 1171 | reload_as_needed (global); |
c47f5ea5 | 1172 | |
41374e13 | 1173 | gcc_assert (old_frame_size == get_frame_size ()); |
c47f5ea5 | 1174 | |
9f938de1 | 1175 | gcc_assert (verify_initial_elim_offsets ()); |
c47f5ea5 | 1176 | } |
32131a9c | 1177 | |
2a1f8b6b | 1178 | /* If we were able to eliminate the frame pointer, show that it is no |
546b63fb | 1179 | longer live at the start of any basic block. If it ls live by |
2a1f8b6b RK |
1180 | virtue of being in a pseudo, that pseudo will be marked live |
1181 | and hence the frame pointer will be known to be live via that | |
1182 | pseudo. */ | |
1183 | ||
1184 | if (! frame_pointer_needed) | |
e0082a72 | 1185 | FOR_EACH_BB (bb) |
ba49cb7b | 1186 | bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM); |
6fb5fa3c | 1187 | |
0e61db61 NS |
1188 | /* Come here (with failure set nonzero) if we can't get enough spill |
1189 | regs. */ | |
5352b11a RS |
1190 | failed: |
1191 | ||
058e97ec | 1192 | CLEAR_REG_SET (&changed_allocation_pseudos); |
f5d8c9f4 | 1193 | CLEAR_REG_SET (&spilled_pseudos); |
a3ec87a8 RS |
1194 | reload_in_progress = 0; |
1195 | ||
32131a9c RK |
1196 | /* Now eliminate all pseudo regs by modifying them into |
1197 | their equivalent memory references. | |
1198 | The REG-rtx's for the pseudos are modified in place, | |
1199 | so all insns that used to refer to them now refer to memory. | |
1200 | ||
1201 | For a reg that has a reg_equiv_address, all those insns | |
1202 | were changed by reloading so that no insns refer to it any longer; | |
1203 | but the DECL_RTL of a variable decl may refer to it, | |
1204 | and if so this causes the debugging info to mention the variable. */ | |
1205 | ||
1206 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1207 | { | |
1208 | rtx addr = 0; | |
9ec36da5 JL |
1209 | |
1210 | if (reg_equiv_mem[i]) | |
1211 | addr = XEXP (reg_equiv_mem[i], 0); | |
1212 | ||
32131a9c RK |
1213 | if (reg_equiv_address[i]) |
1214 | addr = reg_equiv_address[i]; | |
9ec36da5 | 1215 | |
32131a9c RK |
1216 | if (addr) |
1217 | { | |
1218 | if (reg_renumber[i] < 0) | |
1219 | { | |
1220 | rtx reg = regno_reg_rtx[i]; | |
173b24b9 | 1221 | |
5a63e069 | 1222 | REG_USERVAR_P (reg) = 0; |
ef178af3 | 1223 | PUT_CODE (reg, MEM); |
32131a9c | 1224 | XEXP (reg, 0) = addr; |
173b24b9 RK |
1225 | if (reg_equiv_memory_loc[i]) |
1226 | MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]); | |
1227 | else | |
1228 | { | |
389fdba0 | 1229 | MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0; |
173b24b9 RK |
1230 | MEM_ATTRS (reg) = 0; |
1231 | } | |
be0c514c | 1232 | MEM_NOTRAP_P (reg) = 1; |
32131a9c RK |
1233 | } |
1234 | else if (reg_equiv_mem[i]) | |
1235 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1236 | } | |
b5b8b0ac AO |
1237 | |
1238 | /* We don't want complex addressing modes in debug insns | |
1239 | if simpler ones will do, so delegitimize equivalences | |
1240 | in debug insns. */ | |
1241 | if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0) | |
1242 | { | |
1243 | rtx reg = regno_reg_rtx[i]; | |
1244 | rtx equiv = 0; | |
502a1e45 | 1245 | df_ref use, next; |
b5b8b0ac AO |
1246 | |
1247 | if (reg_equiv_constant[i]) | |
1248 | equiv = reg_equiv_constant[i]; | |
1249 | else if (reg_equiv_invariant[i]) | |
1250 | equiv = reg_equiv_invariant[i]; | |
1251 | else if (reg && MEM_P (reg)) | |
502a1e45 | 1252 | equiv = targetm.delegitimize_address (reg); |
b5b8b0ac AO |
1253 | else if (reg && REG_P (reg) && (int)REGNO (reg) != i) |
1254 | equiv = reg; | |
1255 | ||
502a1e45 AO |
1256 | if (equiv == reg) |
1257 | continue; | |
1258 | ||
1259 | for (use = DF_REG_USE_CHAIN (i); use; use = next) | |
1260 | { | |
502a1e45 | 1261 | insn = DF_REF_INSN (use); |
3af4ba41 RS |
1262 | |
1263 | /* Make sure the next ref is for a different instruction, | |
1264 | so that we're not affected by the rescan. */ | |
502a1e45 | 1265 | next = DF_REF_NEXT_REG (use); |
3af4ba41 RS |
1266 | while (next && DF_REF_INSN (next) == insn) |
1267 | next = DF_REF_NEXT_REG (next); | |
502a1e45 AO |
1268 | |
1269 | if (DEBUG_INSN_P (insn)) | |
b5b8b0ac | 1270 | { |
502a1e45 AO |
1271 | if (!equiv) |
1272 | { | |
1273 | INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC (); | |
1274 | df_insn_rescan_debug_internal (insn); | |
1275 | } | |
b5b8b0ac | 1276 | else |
3af4ba41 RS |
1277 | INSN_VAR_LOCATION_LOC (insn) |
1278 | = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn), | |
1279 | reg, equiv); | |
b5b8b0ac | 1280 | } |
502a1e45 | 1281 | } |
b5b8b0ac | 1282 | } |
32131a9c RK |
1283 | } |
1284 | ||
2ae74651 JL |
1285 | /* We must set reload_completed now since the cleanup_subreg_operands call |
1286 | below will re-recognize each insn and reload may have generated insns | |
1287 | which are only valid during and after reload. */ | |
1288 | reload_completed = 1; | |
1289 | ||
bd695e1e RH |
1290 | /* Make a pass over all the insns and delete all USEs which we inserted |
1291 | only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED | |
41e34bab DJ |
1292 | notes. Delete all CLOBBER insns, except those that refer to the return |
1293 | value and the special mem:BLK CLOBBERs added to prevent the scheduler | |
1294 | from misarranging variable-array code, and simplify (subreg (reg)) | |
4a8cae83 SB |
1295 | operands. Strip and regenerate REG_INC notes that may have been moved |
1296 | around. */ | |
32131a9c | 1297 | |
ba4807a0 LB |
1298 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
1299 | if (INSN_P (insn)) | |
1300 | { | |
1301 | rtx *pnote; | |
1302 | ||
1303 | if (CALL_P (insn)) | |
1304 | replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn), | |
1305 | VOIDmode, CALL_INSN_FUNCTION_USAGE (insn)); | |
1306 | ||
1307 | if ((GET_CODE (PATTERN (insn)) == USE | |
1308 | /* We mark with QImode USEs introduced by reload itself. */ | |
1309 | && (GET_MODE (insn) == QImode | |
1310 | || find_reg_note (insn, REG_EQUAL, NULL_RTX))) | |
1311 | || (GET_CODE (PATTERN (insn)) == CLOBBER | |
1312 | && (!MEM_P (XEXP (PATTERN (insn), 0)) | |
1313 | || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode | |
1314 | || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH | |
1315 | && XEXP (XEXP (PATTERN (insn), 0), 0) | |
1316 | != stack_pointer_rtx)) | |
1317 | && (!REG_P (XEXP (PATTERN (insn), 0)) | |
1318 | || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) | |
1319 | { | |
1320 | delete_insn (insn); | |
1321 | continue; | |
1322 | } | |
1323 | ||
1324 | /* Some CLOBBERs may survive until here and still reference unassigned | |
1325 | pseudos with const equivalent, which may in turn cause ICE in later | |
1326 | passes if the reference remains in place. */ | |
1327 | if (GET_CODE (PATTERN (insn)) == CLOBBER) | |
1328 | replace_pseudos_in (& XEXP (PATTERN (insn), 0), | |
1329 | VOIDmode, PATTERN (insn)); | |
1330 | ||
1331 | /* Discard obvious no-ops, even without -O. This optimization | |
1332 | is fast and doesn't interfere with debugging. */ | |
1333 | if (NONJUMP_INSN_P (insn) | |
1334 | && GET_CODE (PATTERN (insn)) == SET | |
1335 | && REG_P (SET_SRC (PATTERN (insn))) | |
1336 | && REG_P (SET_DEST (PATTERN (insn))) | |
1337 | && (REGNO (SET_SRC (PATTERN (insn))) | |
1338 | == REGNO (SET_DEST (PATTERN (insn))))) | |
1339 | { | |
1340 | delete_insn (insn); | |
1341 | continue; | |
1342 | } | |
1343 | ||
1344 | pnote = ®_NOTES (insn); | |
1345 | while (*pnote != 0) | |
1346 | { | |
1347 | if (REG_NOTE_KIND (*pnote) == REG_DEAD | |
1348 | || REG_NOTE_KIND (*pnote) == REG_UNUSED | |
4a8cae83 | 1349 | || REG_NOTE_KIND (*pnote) == REG_INC) |
ba4807a0 LB |
1350 | *pnote = XEXP (*pnote, 1); |
1351 | else | |
1352 | pnote = &XEXP (*pnote, 1); | |
1353 | } | |
0304f787 | 1354 | |
2dfa9a87 | 1355 | #ifdef AUTO_INC_DEC |
ba4807a0 | 1356 | add_auto_inc_notes (insn, PATTERN (insn)); |
2dfa9a87 MH |
1357 | #endif |
1358 | ||
ba4807a0 LB |
1359 | /* Simplify (subreg (reg)) if it appears as an operand. */ |
1360 | cleanup_subreg_operands (insn); | |
1361 | ||
1362 | /* Clean up invalid ASMs so that they don't confuse later passes. | |
1363 | See PR 21299. */ | |
1364 | if (asm_noperands (PATTERN (insn)) >= 0) | |
1365 | { | |
1366 | extract_insn (insn); | |
1367 | if (!constrain_operands (1)) | |
1368 | { | |
1369 | error_for_asm (insn, | |
1370 | "%<asm%> operand has impossible constraints"); | |
1371 | delete_insn (insn); | |
1372 | continue; | |
1373 | } | |
1374 | } | |
1375 | } | |
32131a9c | 1376 | |
b38f3813 EB |
1377 | /* If we are doing generic stack checking, give a warning if this |
1378 | function's frame size is larger than we expect. */ | |
1379 | if (flag_stack_check == GENERIC_STACK_CHECK) | |
ab87f8c8 JL |
1380 | { |
1381 | HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; | |
05d10675 BS |
1382 | static int verbose_warned = 0; |
1383 | ||
ab87f8c8 | 1384 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
6fb5fa3c | 1385 | if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i]) |
ab87f8c8 JL |
1386 | size += UNITS_PER_WORD; |
1387 | ||
1388 | if (size > STACK_CHECK_MAX_FRAME_SIZE) | |
05d10675 | 1389 | { |
d4ee4d25 | 1390 | warning (0, "frame size too large for reliable stack checking"); |
ab87f8c8 JL |
1391 | if (! verbose_warned) |
1392 | { | |
d4ee4d25 | 1393 | warning (0, "try reducing the number of local variables"); |
ab87f8c8 JL |
1394 | verbose_warned = 1; |
1395 | } | |
1396 | } | |
1397 | } | |
1398 | ||
32131a9c | 1399 | /* Indicate that we no longer have known memory locations or constants. */ |
58d9f9d9 JL |
1400 | if (reg_equiv_constant) |
1401 | free (reg_equiv_constant); | |
ab156144 RH |
1402 | if (reg_equiv_invariant) |
1403 | free (reg_equiv_invariant); | |
32131a9c | 1404 | reg_equiv_constant = 0; |
ab156144 | 1405 | reg_equiv_invariant = 0; |
43b373a2 | 1406 | VEC_free (rtx, gc, reg_equiv_memory_loc_vec); |
32131a9c | 1407 | reg_equiv_memory_loc = 0; |
5352b11a | 1408 | |
058e97ec VM |
1409 | free (temp_pseudo_reg_arr); |
1410 | ||
4cc0fdd2 JDA |
1411 | if (offsets_known_at) |
1412 | free (offsets_known_at); | |
1413 | if (offsets_at) | |
1414 | free (offsets_at); | |
a68d4b75 | 1415 | |
3f1e3e70 AO |
1416 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1417 | if (reg_equiv_alt_mem_list[i]) | |
1418 | free_EXPR_LIST_list (®_equiv_alt_mem_list[i]); | |
1419 | free (reg_equiv_alt_mem_list); | |
1420 | ||
56a65848 | 1421 | free (reg_equiv_mem); |
d7f88d86 | 1422 | reg_equiv_init = 0; |
56a65848 DB |
1423 | free (reg_equiv_address); |
1424 | free (reg_max_ref_width); | |
03acd8f8 BS |
1425 | free (reg_old_renumber); |
1426 | free (pseudo_previous_regs); | |
1427 | free (pseudo_forbidden_regs); | |
56a65848 | 1428 | |
8b4f9969 JW |
1429 | CLEAR_HARD_REG_SET (used_spill_regs); |
1430 | for (i = 0; i < n_spills; i++) | |
1431 | SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); | |
1432 | ||
7609e720 BS |
1433 | /* Free all the insn_chain structures at once. */ |
1434 | obstack_free (&reload_obstack, reload_startobj); | |
1435 | unused_insn_chains = 0; | |
f1330226 | 1436 | fixup_abnormal_edges (); |
7609e720 | 1437 | |
e16e3291 UW |
1438 | /* Replacing pseudos with their memory equivalents might have |
1439 | created shared rtx. Subsequent passes would get confused | |
1440 | by this, so unshare everything here. */ | |
1441 | unshare_all_rtl_again (first); | |
1442 | ||
b483cfb7 EB |
1443 | #ifdef STACK_BOUNDARY |
1444 | /* init_emit has set the alignment of the hard frame pointer | |
1445 | to STACK_BOUNDARY. It is very likely no longer valid if | |
1446 | the hard frame pointer was used for register allocation. */ | |
1447 | if (!frame_pointer_needed) | |
1448 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; | |
1449 | #endif | |
1450 | ||
5352b11a | 1451 | return failure; |
32131a9c | 1452 | } |
1e5bd841 | 1453 | |
18a90182 BS |
1454 | /* Yet another special case. Unfortunately, reg-stack forces people to |
1455 | write incorrect clobbers in asm statements. These clobbers must not | |
1456 | cause the register to appear in bad_spill_regs, otherwise we'll call | |
1457 | fatal_insn later. We clear the corresponding regnos in the live | |
1458 | register sets to avoid this. | |
1459 | The whole thing is rather sick, I'm afraid. */ | |
efc9bd41 | 1460 | |
18a90182 | 1461 | static void |
0c20a65f | 1462 | maybe_fix_stack_asms (void) |
18a90182 BS |
1463 | { |
1464 | #ifdef STACK_REGS | |
392dccb7 | 1465 | const char *constraints[MAX_RECOG_OPERANDS]; |
18a90182 BS |
1466 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
1467 | struct insn_chain *chain; | |
1468 | ||
1469 | for (chain = reload_insn_chain; chain != 0; chain = chain->next) | |
1470 | { | |
1471 | int i, noperands; | |
1472 | HARD_REG_SET clobbered, allowed; | |
1473 | rtx pat; | |
1474 | ||
2c3c49de | 1475 | if (! INSN_P (chain->insn) |
18a90182 BS |
1476 | || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) |
1477 | continue; | |
1478 | pat = PATTERN (chain->insn); | |
1479 | if (GET_CODE (pat) != PARALLEL) | |
1480 | continue; | |
1481 | ||
1482 | CLEAR_HARD_REG_SET (clobbered); | |
1483 | CLEAR_HARD_REG_SET (allowed); | |
1484 | ||
1485 | /* First, make a mask of all stack regs that are clobbered. */ | |
1486 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
1487 | { | |
1488 | rtx t = XVECEXP (pat, 0, i); | |
1489 | if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) | |
1490 | SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); | |
1491 | } | |
1492 | ||
1493 | /* Get the operand values and constraints out of the insn. */ | |
1ccbefce | 1494 | decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, |
bff4b63d | 1495 | constraints, operand_mode, NULL); |
18a90182 BS |
1496 | |
1497 | /* For every operand, see what registers are allowed. */ | |
1498 | for (i = 0; i < noperands; i++) | |
1499 | { | |
6b9c6f4f | 1500 | const char *p = constraints[i]; |
18a90182 BS |
1501 | /* For every alternative, we compute the class of registers allowed |
1502 | for reloading in CLS, and merge its contents into the reg set | |
1503 | ALLOWED. */ | |
1504 | int cls = (int) NO_REGS; | |
1505 | ||
1506 | for (;;) | |
1507 | { | |
97488870 | 1508 | char c = *p; |
18a90182 BS |
1509 | |
1510 | if (c == '\0' || c == ',' || c == '#') | |
1511 | { | |
1512 | /* End of one alternative - mark the regs in the current | |
1513 | class, and reset the class. */ | |
1514 | IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); | |
1515 | cls = NO_REGS; | |
97488870 | 1516 | p++; |
18a90182 BS |
1517 | if (c == '#') |
1518 | do { | |
1519 | c = *p++; | |
1520 | } while (c != '\0' && c != ','); | |
1521 | if (c == '\0') | |
1522 | break; | |
1523 | continue; | |
1524 | } | |
1525 | ||
1526 | switch (c) | |
1527 | { | |
1528 | case '=': case '+': case '*': case '%': case '?': case '!': | |
a4edaf83 AK |
1529 | case '0': case '1': case '2': case '3': case '4': case '<': |
1530 | case '>': case 'V': case 'o': case '&': case 'E': case 'F': | |
1531 | case 's': case 'i': case 'n': case 'X': case 'I': case 'J': | |
1532 | case 'K': case 'L': case 'M': case 'N': case 'O': case 'P': | |
1533 | case TARGET_MEM_CONSTRAINT: | |
18a90182 BS |
1534 | break; |
1535 | ||
1536 | case 'p': | |
3dcc68a4 | 1537 | cls = (int) reg_class_subunion[cls] |
c4963a0a | 1538 | [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; |
18a90182 BS |
1539 | break; |
1540 | ||
1541 | case 'g': | |
1542 | case 'r': | |
1543 | cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; | |
1544 | break; | |
1545 | ||
1546 | default: | |
97488870 | 1547 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) |
ccfc6cc8 | 1548 | cls = (int) reg_class_subunion[cls] |
c4963a0a | 1549 | [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; |
ccfc6cc8 UW |
1550 | else |
1551 | cls = (int) reg_class_subunion[cls] | |
97488870 | 1552 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; |
18a90182 | 1553 | } |
97488870 | 1554 | p += CONSTRAINT_LEN (c, p); |
18a90182 BS |
1555 | } |
1556 | } | |
1557 | /* Those of the registers which are clobbered, but allowed by the | |
1558 | constraints, must be usable as reload registers. So clear them | |
1559 | out of the life information. */ | |
1560 | AND_HARD_REG_SET (allowed, clobbered); | |
1561 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1562 | if (TEST_HARD_REG_BIT (allowed, i)) | |
1563 | { | |
239a0f5b BS |
1564 | CLEAR_REGNO_REG_SET (&chain->live_throughout, i); |
1565 | CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); | |
18a90182 BS |
1566 | } |
1567 | } | |
1568 | ||
1569 | #endif | |
1570 | } | |
03acd8f8 | 1571 | \f |
f5d8c9f4 BS |
1572 | /* Copy the global variables n_reloads and rld into the corresponding elts |
1573 | of CHAIN. */ | |
1574 | static void | |
0c20a65f | 1575 | copy_reloads (struct insn_chain *chain) |
f5d8c9f4 BS |
1576 | { |
1577 | chain->n_reloads = n_reloads; | |
1634b18f | 1578 | chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads); |
f5d8c9f4 | 1579 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
1634b18f | 1580 | reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0); |
f5d8c9f4 BS |
1581 | } |
1582 | ||
03acd8f8 BS |
1583 | /* Walk the chain of insns, and determine for each whether it needs reloads |
1584 | and/or eliminations. Build the corresponding insns_need_reload list, and | |
1585 | set something_needs_elimination as appropriate. */ | |
1586 | static void | |
0c20a65f | 1587 | calculate_needs_all_insns (int global) |
1e5bd841 | 1588 | { |
7609e720 | 1589 | struct insn_chain **pprev_reload = &insns_need_reload; |
462561b7 | 1590 | struct insn_chain *chain, *next = 0; |
1e5bd841 | 1591 | |
03acd8f8 BS |
1592 | something_needs_elimination = 0; |
1593 | ||
1634b18f | 1594 | reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0); |
462561b7 | 1595 | for (chain = reload_insn_chain; chain != 0; chain = next) |
1e5bd841 | 1596 | { |
67e61fe7 | 1597 | rtx insn = chain->insn; |
03acd8f8 | 1598 | |
462561b7 JJ |
1599 | next = chain->next; |
1600 | ||
f5d8c9f4 BS |
1601 | /* Clear out the shortcuts. */ |
1602 | chain->n_reloads = 0; | |
67e61fe7 BS |
1603 | chain->need_elim = 0; |
1604 | chain->need_reload = 0; | |
1605 | chain->need_operand_change = 0; | |
1e5bd841 | 1606 | |
03acd8f8 | 1607 | /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might |
cf7c4aa6 HPN |
1608 | include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see |
1609 | what effects this has on the known offsets at labels. */ | |
1e5bd841 | 1610 | |
4b4bf941 | 1611 | if (LABEL_P (insn) || JUMP_P (insn) |
2c3c49de | 1612 | || (INSN_P (insn) && REG_NOTES (insn) != 0)) |
1e5bd841 BS |
1613 | set_label_offsets (insn, insn, 0); |
1614 | ||
2c3c49de | 1615 | if (INSN_P (insn)) |
1e5bd841 BS |
1616 | { |
1617 | rtx old_body = PATTERN (insn); | |
1618 | int old_code = INSN_CODE (insn); | |
1619 | rtx old_notes = REG_NOTES (insn); | |
1620 | int did_elimination = 0; | |
cb2afeb3 | 1621 | int operands_changed = 0; |
2b49ee39 R |
1622 | rtx set = single_set (insn); |
1623 | ||
1624 | /* Skip insns that only set an equivalence. */ | |
f8cfc6aa | 1625 | if (set && REG_P (SET_DEST (set)) |
2b49ee39 | 1626 | && reg_renumber[REGNO (SET_DEST (set))] < 0 |
ab156144 RH |
1627 | && (reg_equiv_constant[REGNO (SET_DEST (set))] |
1628 | || (reg_equiv_invariant[REGNO (SET_DEST (set))])) | |
1629 | && reg_equiv_init[REGNO (SET_DEST (set))]) | |
67e61fe7 | 1630 | continue; |
1e5bd841 | 1631 | |
1e5bd841 | 1632 | /* If needed, eliminate any eliminable registers. */ |
2b49ee39 | 1633 | if (num_eliminable || num_eliminable_invariants) |
1e5bd841 BS |
1634 | did_elimination = eliminate_regs_in_insn (insn, 0); |
1635 | ||
1636 | /* Analyze the instruction. */ | |
cb2afeb3 R |
1637 | operands_changed = find_reloads (insn, 0, spill_indirect_levels, |
1638 | global, spill_reg_order); | |
1639 | ||
1640 | /* If a no-op set needs more than one reload, this is likely | |
1641 | to be something that needs input address reloads. We | |
1642 | can't get rid of this cleanly later, and it is of no use | |
1643 | anyway, so discard it now. | |
1644 | We only do this when expensive_optimizations is enabled, | |
1645 | since this complements reload inheritance / output | |
1646 | reload deletion, and it can make debugging harder. */ | |
1647 | if (flag_expensive_optimizations && n_reloads > 1) | |
1648 | { | |
1649 | rtx set = single_set (insn); | |
1650 | if (set | |
058e97ec VM |
1651 | && |
1652 | ((SET_SRC (set) == SET_DEST (set) | |
1653 | && REG_P (SET_SRC (set)) | |
1654 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1655 | || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set)) | |
1656 | && reg_renumber[REGNO (SET_SRC (set))] < 0 | |
1657 | && reg_renumber[REGNO (SET_DEST (set))] < 0 | |
1658 | && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL | |
1659 | && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL | |
1660 | && rtx_equal_p (reg_equiv_memory_loc | |
1661 | [REGNO (SET_SRC (set))], | |
1662 | reg_equiv_memory_loc | |
1663 | [REGNO (SET_DEST (set))])))) | |
cb2afeb3 | 1664 | { |
2af2dbdc | 1665 | if (ira_conflicts_p) |
058e97ec VM |
1666 | /* Inform IRA about the insn deletion. */ |
1667 | ira_mark_memory_move_deletion (REGNO (SET_DEST (set)), | |
1668 | REGNO (SET_SRC (set))); | |
ca6c03ca | 1669 | delete_insn (insn); |
3eae4643 | 1670 | /* Delete it from the reload chain. */ |
462561b7 JJ |
1671 | if (chain->prev) |
1672 | chain->prev->next = next; | |
1673 | else | |
1674 | reload_insn_chain = next; | |
1675 | if (next) | |
1676 | next->prev = chain->prev; | |
1677 | chain->next = unused_insn_chains; | |
1678 | unused_insn_chains = chain; | |
cb2afeb3 R |
1679 | continue; |
1680 | } | |
1681 | } | |
1682 | if (num_eliminable) | |
1683 | update_eliminable_offsets (); | |
1e5bd841 BS |
1684 | |
1685 | /* Remember for later shortcuts which insns had any reloads or | |
7609e720 BS |
1686 | register eliminations. */ |
1687 | chain->need_elim = did_elimination; | |
03acd8f8 BS |
1688 | chain->need_reload = n_reloads > 0; |
1689 | chain->need_operand_change = operands_changed; | |
1e5bd841 BS |
1690 | |
1691 | /* Discard any register replacements done. */ | |
1692 | if (did_elimination) | |
1693 | { | |
f5d8c9f4 | 1694 | obstack_free (&reload_obstack, reload_insn_firstobj); |
1e5bd841 BS |
1695 | PATTERN (insn) = old_body; |
1696 | INSN_CODE (insn) = old_code; | |
1697 | REG_NOTES (insn) = old_notes; | |
1698 | something_needs_elimination = 1; | |
1699 | } | |
1700 | ||
cb2afeb3 R |
1701 | something_needs_operands_changed |= operands_changed; |
1702 | ||
437a710d | 1703 | if (n_reloads != 0) |
7609e720 | 1704 | { |
f5d8c9f4 | 1705 | copy_reloads (chain); |
7609e720 BS |
1706 | *pprev_reload = chain; |
1707 | pprev_reload = &chain->next_need_reload; | |
7609e720 | 1708 | } |
1e5bd841 | 1709 | } |
1e5bd841 | 1710 | } |
7609e720 | 1711 | *pprev_reload = 0; |
1e5bd841 | 1712 | } |
f5d8c9f4 BS |
1713 | \f |
1714 | /* Comparison function for qsort to decide which of two reloads | |
1715 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
1e5bd841 | 1716 | |
f5d8c9f4 | 1717 | static int |
0c20a65f | 1718 | reload_reg_class_lower (const void *r1p, const void *r2p) |
1e5bd841 | 1719 | { |
b3694847 SS |
1720 | int r1 = *(const short *) r1p, r2 = *(const short *) r2p; |
1721 | int t; | |
1e5bd841 | 1722 | |
f5d8c9f4 BS |
1723 | /* Consider required reloads before optional ones. */ |
1724 | t = rld[r1].optional - rld[r2].optional; | |
1725 | if (t != 0) | |
1726 | return t; | |
1e5bd841 | 1727 | |
f5d8c9f4 | 1728 | /* Count all solitary classes before non-solitary ones. */ |
48c54229 KG |
1729 | t = ((reg_class_size[(int) rld[r2].rclass] == 1) |
1730 | - (reg_class_size[(int) rld[r1].rclass] == 1)); | |
f5d8c9f4 BS |
1731 | if (t != 0) |
1732 | return t; | |
1e5bd841 | 1733 | |
f5d8c9f4 BS |
1734 | /* Aside from solitaires, consider all multi-reg groups first. */ |
1735 | t = rld[r2].nregs - rld[r1].nregs; | |
1736 | if (t != 0) | |
1737 | return t; | |
1e5bd841 | 1738 | |
f5d8c9f4 | 1739 | /* Consider reloads in order of increasing reg-class number. */ |
48c54229 | 1740 | t = (int) rld[r1].rclass - (int) rld[r2].rclass; |
f5d8c9f4 BS |
1741 | if (t != 0) |
1742 | return t; | |
1e5bd841 | 1743 | |
f5d8c9f4 BS |
1744 | /* If reloads are equally urgent, sort by reload number, |
1745 | so that the results of qsort leave nothing to chance. */ | |
1746 | return r1 - r2; | |
1747 | } | |
1748 | \f | |
1749 | /* The cost of spilling each hard reg. */ | |
1750 | static int spill_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1751 | |
f5d8c9f4 BS |
1752 | /* When spilling multiple hard registers, we use SPILL_COST for the first |
1753 | spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST | |
1754 | only the first hard reg for a multi-reg pseudo. */ | |
1755 | static int spill_add_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1756 | |
058e97ec VM |
1757 | /* Map of hard regno to pseudo regno currently occupying the hard |
1758 | reg. */ | |
1759 | static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER]; | |
1760 | ||
f5d8c9f4 | 1761 | /* Update the spill cost arrays, considering that pseudo REG is live. */ |
770ae6cc | 1762 | |
f5d8c9f4 | 1763 | static void |
0c20a65f | 1764 | count_pseudo (int reg) |
f5d8c9f4 | 1765 | { |
b2aec5c0 | 1766 | int freq = REG_FREQ (reg); |
f5d8c9f4 BS |
1767 | int r = reg_renumber[reg]; |
1768 | int nregs; | |
1e5bd841 | 1769 | |
f5d8c9f4 | 1770 | if (REGNO_REG_SET_P (&pseudos_counted, reg) |
058e97ec VM |
1771 | || REGNO_REG_SET_P (&spilled_pseudos, reg) |
1772 | /* Ignore spilled pseudo-registers which can be here only if IRA | |
1773 | is used. */ | |
2af2dbdc | 1774 | || (ira_conflicts_p && r < 0)) |
f5d8c9f4 | 1775 | return; |
1e5bd841 | 1776 | |
f5d8c9f4 | 1777 | SET_REGNO_REG_SET (&pseudos_counted, reg); |
1e5bd841 | 1778 | |
41374e13 | 1779 | gcc_assert (r >= 0); |
1d7254c5 | 1780 | |
b2aec5c0 | 1781 | spill_add_cost[r] += freq; |
66fd46b6 | 1782 | nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)]; |
f5d8c9f4 | 1783 | while (nregs-- > 0) |
058e97ec VM |
1784 | { |
1785 | hard_regno_to_pseudo_regno[r + nregs] = reg; | |
1786 | spill_cost[r + nregs] += freq; | |
1787 | } | |
f5d8c9f4 | 1788 | } |
1e5bd841 | 1789 | |
f5d8c9f4 BS |
1790 | /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the |
1791 | contents of BAD_SPILL_REGS for the insn described by CHAIN. */ | |
efc9bd41 | 1792 | |
f5d8c9f4 | 1793 | static void |
0c20a65f | 1794 | order_regs_for_reload (struct insn_chain *chain) |
f5d8c9f4 | 1795 | { |
3cd8c58a | 1796 | unsigned i; |
efc9bd41 RK |
1797 | HARD_REG_SET used_by_pseudos; |
1798 | HARD_REG_SET used_by_pseudos2; | |
a2041967 | 1799 | reg_set_iterator rsi; |
1e5bd841 | 1800 | |
efc9bd41 | 1801 | COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set); |
1e5bd841 | 1802 | |
f5d8c9f4 BS |
1803 | memset (spill_cost, 0, sizeof spill_cost); |
1804 | memset (spill_add_cost, 0, sizeof spill_add_cost); | |
058e97ec VM |
1805 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1806 | hard_regno_to_pseudo_regno[i] = -1; | |
1e5bd841 | 1807 | |
f5d8c9f4 | 1808 | /* Count number of uses of each hard reg by pseudo regs allocated to it |
efc9bd41 RK |
1809 | and then order them by decreasing use. First exclude hard registers |
1810 | that are live in or across this insn. */ | |
1811 | ||
1812 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); | |
1813 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
1814 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos); | |
1815 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2); | |
1e5bd841 | 1816 | |
f5d8c9f4 BS |
1817 | /* Now find out which pseudos are allocated to it, and update |
1818 | hard_reg_n_uses. */ | |
1819 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1820 | |
f5d8c9f4 | 1821 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
1822 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi) |
1823 | { | |
1824 | count_pseudo (i); | |
1825 | } | |
f5d8c9f4 | 1826 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
1827 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi) |
1828 | { | |
1829 | count_pseudo (i); | |
1830 | } | |
f5d8c9f4 | 1831 | CLEAR_REG_SET (&pseudos_counted); |
1e5bd841 | 1832 | } |
03acd8f8 | 1833 | \f |
f5d8c9f4 BS |
1834 | /* Vector of reload-numbers showing the order in which the reloads should |
1835 | be processed. */ | |
1836 | static short reload_order[MAX_RELOADS]; | |
1e5bd841 | 1837 | |
f5d8c9f4 BS |
1838 | /* This is used to keep track of the spill regs used in one insn. */ |
1839 | static HARD_REG_SET used_spill_regs_local; | |
03acd8f8 | 1840 | |
f5d8c9f4 BS |
1841 | /* We decided to spill hard register SPILLED, which has a size of |
1842 | SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, | |
1843 | is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will | |
1844 | update SPILL_COST/SPILL_ADD_COST. */ | |
770ae6cc | 1845 | |
03acd8f8 | 1846 | static void |
0c20a65f | 1847 | count_spilled_pseudo (int spilled, int spilled_nregs, int reg) |
1e5bd841 | 1848 | { |
058e97ec | 1849 | int freq = REG_FREQ (reg); |
f5d8c9f4 | 1850 | int r = reg_renumber[reg]; |
66fd46b6 | 1851 | int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)]; |
1e5bd841 | 1852 | |
058e97ec VM |
1853 | /* Ignore spilled pseudo-registers which can be here only if IRA is |
1854 | used. */ | |
2af2dbdc | 1855 | if ((ira_conflicts_p && r < 0) |
058e97ec | 1856 | || REGNO_REG_SET_P (&spilled_pseudos, reg) |
f5d8c9f4 BS |
1857 | || spilled + spilled_nregs <= r || r + nregs <= spilled) |
1858 | return; | |
1e5bd841 | 1859 | |
f5d8c9f4 | 1860 | SET_REGNO_REG_SET (&spilled_pseudos, reg); |
1e5bd841 | 1861 | |
058e97ec | 1862 | spill_add_cost[r] -= freq; |
f5d8c9f4 | 1863 | while (nregs-- > 0) |
058e97ec VM |
1864 | { |
1865 | hard_regno_to_pseudo_regno[r + nregs] = -1; | |
1866 | spill_cost[r + nregs] -= freq; | |
1867 | } | |
1e5bd841 BS |
1868 | } |
1869 | ||
f5d8c9f4 | 1870 | /* Find reload register to use for reload number ORDER. */ |
03acd8f8 | 1871 | |
f5d8c9f4 | 1872 | static int |
0c20a65f | 1873 | find_reg (struct insn_chain *chain, int order) |
1e5bd841 | 1874 | { |
f5d8c9f4 BS |
1875 | int rnum = reload_order[order]; |
1876 | struct reload *rl = rld + rnum; | |
1877 | int best_cost = INT_MAX; | |
1878 | int best_reg = -1; | |
058e97ec | 1879 | unsigned int i, j, n; |
770ae6cc | 1880 | int k; |
f5d8c9f4 BS |
1881 | HARD_REG_SET not_usable; |
1882 | HARD_REG_SET used_by_other_reload; | |
a2041967 | 1883 | reg_set_iterator rsi; |
058e97ec VM |
1884 | static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER]; |
1885 | static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1886 | |
f5d8c9f4 BS |
1887 | COPY_HARD_REG_SET (not_usable, bad_spill_regs); |
1888 | IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); | |
48c54229 | 1889 | IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]); |
f5d8c9f4 BS |
1890 | |
1891 | CLEAR_HARD_REG_SET (used_by_other_reload); | |
770ae6cc | 1892 | for (k = 0; k < order; k++) |
1e5bd841 | 1893 | { |
770ae6cc RK |
1894 | int other = reload_order[k]; |
1895 | ||
f5d8c9f4 BS |
1896 | if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) |
1897 | for (j = 0; j < rld[other].nregs; j++) | |
1898 | SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); | |
1899 | } | |
1e5bd841 | 1900 | |
f5d8c9f4 BS |
1901 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1902 | { | |
058e97ec VM |
1903 | #ifdef REG_ALLOC_ORDER |
1904 | unsigned int regno = reg_alloc_order[i]; | |
1905 | #else | |
770ae6cc | 1906 | unsigned int regno = i; |
058e97ec | 1907 | #endif |
770ae6cc | 1908 | |
f5d8c9f4 BS |
1909 | if (! TEST_HARD_REG_BIT (not_usable, regno) |
1910 | && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) | |
1911 | && HARD_REGNO_MODE_OK (regno, rl->mode)) | |
1e5bd841 | 1912 | { |
f5d8c9f4 BS |
1913 | int this_cost = spill_cost[regno]; |
1914 | int ok = 1; | |
66fd46b6 | 1915 | unsigned int this_nregs = hard_regno_nregs[regno][rl->mode]; |
1e5bd841 | 1916 | |
f5d8c9f4 BS |
1917 | for (j = 1; j < this_nregs; j++) |
1918 | { | |
1919 | this_cost += spill_add_cost[regno + j]; | |
1920 | if ((TEST_HARD_REG_BIT (not_usable, regno + j)) | |
1921 | || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) | |
1922 | ok = 0; | |
1923 | } | |
1924 | if (! ok) | |
1925 | continue; | |
058e97ec | 1926 | |
2af2dbdc | 1927 | if (ira_conflicts_p) |
058e97ec VM |
1928 | { |
1929 | /* Ask IRA to find a better pseudo-register for | |
1930 | spilling. */ | |
1931 | for (n = j = 0; j < this_nregs; j++) | |
1932 | { | |
1933 | int r = hard_regno_to_pseudo_regno[regno + j]; | |
1934 | ||
1935 | if (r < 0) | |
1936 | continue; | |
1937 | if (n == 0 || regno_pseudo_regs[n - 1] != r) | |
1938 | regno_pseudo_regs[n++] = r; | |
1939 | } | |
1940 | regno_pseudo_regs[n++] = -1; | |
1941 | if (best_reg < 0 | |
1942 | || ira_better_spill_reload_regno_p (regno_pseudo_regs, | |
1943 | best_regno_pseudo_regs, | |
1944 | rl->in, rl->out, | |
1945 | chain->insn)) | |
1946 | { | |
1947 | best_reg = regno; | |
1948 | for (j = 0;; j++) | |
1949 | { | |
1950 | best_regno_pseudo_regs[j] = regno_pseudo_regs[j]; | |
1951 | if (regno_pseudo_regs[j] < 0) | |
1952 | break; | |
1953 | } | |
1954 | } | |
1955 | continue; | |
1956 | } | |
1957 | ||
f8cfc6aa | 1958 | if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno) |
f5d8c9f4 | 1959 | this_cost--; |
f8cfc6aa | 1960 | if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno) |
f5d8c9f4 BS |
1961 | this_cost--; |
1962 | if (this_cost < best_cost | |
1963 | /* Among registers with equal cost, prefer caller-saved ones, or | |
1964 | use REG_ALLOC_ORDER if it is defined. */ | |
1965 | || (this_cost == best_cost | |
1966 | #ifdef REG_ALLOC_ORDER | |
1967 | && (inv_reg_alloc_order[regno] | |
1968 | < inv_reg_alloc_order[best_reg]) | |
1969 | #else | |
1970 | && call_used_regs[regno] | |
1971 | && ! call_used_regs[best_reg] | |
1972 | #endif | |
1973 | )) | |
1974 | { | |
1975 | best_reg = regno; | |
1976 | best_cost = this_cost; | |
1e5bd841 BS |
1977 | } |
1978 | } | |
1979 | } | |
f5d8c9f4 BS |
1980 | if (best_reg == -1) |
1981 | return 0; | |
770ae6cc | 1982 | |
c263766c RH |
1983 | if (dump_file) |
1984 | fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum); | |
770ae6cc | 1985 | |
66fd46b6 | 1986 | rl->nregs = hard_regno_nregs[best_reg][rl->mode]; |
f5d8c9f4 | 1987 | rl->regno = best_reg; |
1e5bd841 | 1988 | |
f5d8c9f4 | 1989 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
1990 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi) |
1991 | { | |
1992 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1993 | } | |
770ae6cc | 1994 | |
f5d8c9f4 | 1995 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
1996 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi) |
1997 | { | |
1998 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1999 | } | |
03acd8f8 | 2000 | |
f5d8c9f4 BS |
2001 | for (i = 0; i < rl->nregs; i++) |
2002 | { | |
41374e13 NS |
2003 | gcc_assert (spill_cost[best_reg + i] == 0); |
2004 | gcc_assert (spill_add_cost[best_reg + i] == 0); | |
058e97ec | 2005 | gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1); |
f5d8c9f4 BS |
2006 | SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); |
2007 | } | |
2008 | return 1; | |
03acd8f8 BS |
2009 | } |
2010 | ||
2011 | /* Find more reload regs to satisfy the remaining need of an insn, which | |
2012 | is given by CHAIN. | |
1e5bd841 BS |
2013 | Do it by ascending class number, since otherwise a reg |
2014 | might be spilled for a big class and might fail to count | |
f5d8c9f4 | 2015 | for a smaller class even though it belongs to that class. */ |
1e5bd841 | 2016 | |
03acd8f8 | 2017 | static void |
0c20a65f | 2018 | find_reload_regs (struct insn_chain *chain) |
1e5bd841 | 2019 | { |
f5d8c9f4 | 2020 | int i; |
1e5bd841 | 2021 | |
f5d8c9f4 BS |
2022 | /* In order to be certain of getting the registers we need, |
2023 | we must sort the reloads into order of increasing register class. | |
2024 | Then our grabbing of reload registers will parallel the process | |
2025 | that provided the reload registers. */ | |
2026 | for (i = 0; i < chain->n_reloads; i++) | |
1e5bd841 | 2027 | { |
f5d8c9f4 BS |
2028 | /* Show whether this reload already has a hard reg. */ |
2029 | if (chain->rld[i].reg_rtx) | |
1e5bd841 | 2030 | { |
f5d8c9f4 BS |
2031 | int regno = REGNO (chain->rld[i].reg_rtx); |
2032 | chain->rld[i].regno = regno; | |
770ae6cc | 2033 | chain->rld[i].nregs |
66fd46b6 | 2034 | = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)]; |
1e5bd841 | 2035 | } |
f5d8c9f4 BS |
2036 | else |
2037 | chain->rld[i].regno = -1; | |
2038 | reload_order[i] = i; | |
2039 | } | |
1e5bd841 | 2040 | |
f5d8c9f4 BS |
2041 | n_reloads = chain->n_reloads; |
2042 | memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); | |
1e5bd841 | 2043 | |
f5d8c9f4 | 2044 | CLEAR_HARD_REG_SET (used_spill_regs_local); |
03acd8f8 | 2045 | |
c263766c RH |
2046 | if (dump_file) |
2047 | fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn)); | |
1e5bd841 | 2048 | |
f5d8c9f4 | 2049 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); |
1e5bd841 | 2050 | |
f5d8c9f4 | 2051 | /* Compute the order of preference for hard registers to spill. */ |
1e5bd841 | 2052 | |
f5d8c9f4 | 2053 | order_regs_for_reload (chain); |
1e5bd841 | 2054 | |
f5d8c9f4 BS |
2055 | for (i = 0; i < n_reloads; i++) |
2056 | { | |
2057 | int r = reload_order[i]; | |
1e5bd841 | 2058 | |
f5d8c9f4 BS |
2059 | /* Ignore reloads that got marked inoperative. */ |
2060 | if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) | |
2061 | && ! rld[r].optional | |
2062 | && rld[r].regno == -1) | |
e04ca094 | 2063 | if (! find_reg (chain, i)) |
f5d8c9f4 | 2064 | { |
ff182b5c | 2065 | if (dump_file) |
247140ea | 2066 | fprintf (dump_file, "reload failure for reload %d\n", r); |
48c54229 | 2067 | spill_failure (chain->insn, rld[r].rclass); |
f5d8c9f4 | 2068 | failure = 1; |
03acd8f8 | 2069 | return; |
f5d8c9f4 | 2070 | } |
1e5bd841 | 2071 | } |
05d10675 | 2072 | |
f5d8c9f4 BS |
2073 | COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local); |
2074 | IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local); | |
03acd8f8 | 2075 | |
f5d8c9f4 | 2076 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
1e5bd841 BS |
2077 | } |
2078 | ||
f5d8c9f4 | 2079 | static void |
0c20a65f | 2080 | select_reload_regs (void) |
09dd1133 | 2081 | { |
f5d8c9f4 | 2082 | struct insn_chain *chain; |
09dd1133 | 2083 | |
f5d8c9f4 BS |
2084 | /* Try to satisfy the needs for each insn. */ |
2085 | for (chain = insns_need_reload; chain != 0; | |
2086 | chain = chain->next_need_reload) | |
e04ca094 | 2087 | find_reload_regs (chain); |
09dd1133 | 2088 | } |
32131a9c | 2089 | \f |
437a710d BS |
2090 | /* Delete all insns that were inserted by emit_caller_save_insns during |
2091 | this iteration. */ | |
2092 | static void | |
0c20a65f | 2093 | delete_caller_save_insns (void) |
437a710d | 2094 | { |
7609e720 | 2095 | struct insn_chain *c = reload_insn_chain; |
437a710d | 2096 | |
7609e720 | 2097 | while (c != 0) |
437a710d | 2098 | { |
7609e720 | 2099 | while (c != 0 && c->is_caller_save_insn) |
437a710d | 2100 | { |
7609e720 BS |
2101 | struct insn_chain *next = c->next; |
2102 | rtx insn = c->insn; | |
2103 | ||
7609e720 BS |
2104 | if (c == reload_insn_chain) |
2105 | reload_insn_chain = next; | |
ca6c03ca | 2106 | delete_insn (insn); |
7609e720 BS |
2107 | |
2108 | if (next) | |
2109 | next->prev = c->prev; | |
2110 | if (c->prev) | |
2111 | c->prev->next = next; | |
2112 | c->next = unused_insn_chains; | |
2113 | unused_insn_chains = c; | |
2114 | c = next; | |
437a710d | 2115 | } |
7609e720 BS |
2116 | if (c != 0) |
2117 | c = c->next; | |
437a710d BS |
2118 | } |
2119 | } | |
2120 | \f | |
5352b11a RS |
2121 | /* Handle the failure to find a register to spill. |
2122 | INSN should be one of the insns which needed this particular spill reg. */ | |
2123 | ||
2124 | static void | |
55d796da | 2125 | spill_failure (rtx insn, enum reg_class rclass) |
5352b11a RS |
2126 | { |
2127 | if (asm_noperands (PATTERN (insn)) >= 0) | |
971801ff JM |
2128 | error_for_asm (insn, "can't find a register in class %qs while " |
2129 | "reloading %<asm%>", | |
55d796da | 2130 | reg_class_names[rclass]); |
5352b11a | 2131 | else |
ecf3151a | 2132 | { |
971801ff | 2133 | error ("unable to find a register to spill in class %qs", |
55d796da | 2134 | reg_class_names[rclass]); |
ff182b5c DD |
2135 | |
2136 | if (dump_file) | |
2137 | { | |
2138 | fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); | |
2139 | debug_reload_to_stream (dump_file); | |
2140 | } | |
1f978f5f | 2141 | fatal_insn ("this is the insn:", insn); |
ecf3151a | 2142 | } |
5352b11a | 2143 | } |
32131a9c RK |
2144 | \f |
2145 | /* Delete an unneeded INSN and any previous insns who sole purpose is loading | |
2146 | data that is dead in INSN. */ | |
2147 | ||
2148 | static void | |
0c20a65f | 2149 | delete_dead_insn (rtx insn) |
32131a9c RK |
2150 | { |
2151 | rtx prev = prev_real_insn (insn); | |
2152 | rtx prev_dest; | |
2153 | ||
2154 | /* If the previous insn sets a register that dies in our insn, delete it | |
2155 | too. */ | |
2156 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
f8cfc6aa | 2157 | && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest)) |
32131a9c | 2158 | && reg_mentioned_p (prev_dest, PATTERN (insn)) |
b294ca38 R |
2159 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) |
2160 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
32131a9c RK |
2161 | delete_dead_insn (prev); |
2162 | ||
6773e15f | 2163 | SET_INSN_DELETED (insn); |
32131a9c RK |
2164 | } |
2165 | ||
2166 | /* Modify the home of pseudo-reg I. | |
2167 | The new home is present in reg_renumber[I]. | |
2168 | ||
2169 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
2170 | or it may be -1, meaning there is none or it is not relevant. | |
2171 | This is used so that all pseudos spilled from a given hard reg | |
2172 | can share one stack slot. */ | |
2173 | ||
2174 | static void | |
058e97ec | 2175 | alter_reg (int i, int from_reg, bool dont_share_p) |
32131a9c RK |
2176 | { |
2177 | /* When outputting an inline function, this can happen | |
2178 | for a reg that isn't actually used. */ | |
2179 | if (regno_reg_rtx[i] == 0) | |
2180 | return; | |
2181 | ||
2182 | /* If the reg got changed to a MEM at rtl-generation time, | |
2183 | ignore it. */ | |
f8cfc6aa | 2184 | if (!REG_P (regno_reg_rtx[i])) |
32131a9c RK |
2185 | return; |
2186 | ||
2187 | /* Modify the reg-rtx to contain the new hard reg | |
2188 | number or else to contain its pseudo reg number. */ | |
6fb5fa3c DB |
2189 | SET_REGNO (regno_reg_rtx[i], |
2190 | reg_renumber[i] >= 0 ? reg_renumber[i] : i); | |
32131a9c RK |
2191 | |
2192 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
2193 | allocate a stack slot for it. */ | |
2194 | ||
2195 | if (reg_renumber[i] < 0 | |
b1f21e0a | 2196 | && REG_N_REFS (i) > 0 |
32131a9c | 2197 | && reg_equiv_constant[i] == 0 |
ab156144 | 2198 | && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0) |
32131a9c RK |
2199 | && reg_equiv_memory_loc[i] == 0) |
2200 | { | |
f6129d66 | 2201 | rtx x = NULL_RTX; |
63a7a62b | 2202 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); |
770ae6cc | 2203 | unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); |
63a7a62b | 2204 | unsigned int inherent_align = GET_MODE_ALIGNMENT (mode); |
770ae6cc | 2205 | unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]); |
63a7a62b | 2206 | unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT; |
32131a9c | 2207 | int adjust = 0; |
058e97ec | 2208 | |
2af2dbdc | 2209 | if (ira_conflicts_p) |
f6129d66 RH |
2210 | { |
2211 | /* Mark the spill for IRA. */ | |
2212 | SET_REGNO_REG_SET (&spilled_pseudos, i); | |
2213 | if (!dont_share_p) | |
2214 | x = ira_reuse_stack_slot (i, inherent_size, total_size); | |
2215 | } | |
2216 | ||
058e97ec | 2217 | if (x) |
f6129d66 RH |
2218 | ; |
2219 | ||
32131a9c RK |
2220 | /* Each pseudo reg has an inherent size which comes from its own mode, |
2221 | and a total size which provides room for paradoxical subregs | |
2222 | which refer to the pseudo reg in wider modes. | |
2223 | ||
2224 | We can use a slot already allocated if it provides both | |
2225 | enough inherent space and enough total space. | |
2226 | Otherwise, we allocate a new slot, making sure that it has no less | |
2227 | inherent space, and no less total space, then the previous slot. */ | |
2af2dbdc | 2228 | else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p)) |
32131a9c | 2229 | { |
13d7e8af | 2230 | rtx stack_slot; |
6fb5fa3c | 2231 | |
32131a9c | 2232 | /* No known place to spill from => no slot to reuse. */ |
63a7a62b RS |
2233 | x = assign_stack_local (mode, total_size, |
2234 | min_align > inherent_align | |
2235 | || total_size > inherent_size ? -1 : 0); | |
13d7e8af JL |
2236 | |
2237 | stack_slot = x; | |
2238 | ||
f6129d66 RH |
2239 | /* Cancel the big-endian correction done in assign_stack_local. |
2240 | Get the address of the beginning of the slot. This is so we | |
2241 | can do a big-endian correction unconditionally below. */ | |
f76b9db2 | 2242 | if (BYTES_BIG_ENDIAN) |
6b5676ce | 2243 | { |
6b5676ce JL |
2244 | adjust = inherent_size - total_size; |
2245 | if (adjust) | |
2246 | stack_slot | |
2247 | = adjust_address_nv (x, mode_for_size (total_size | |
2248 | * BITS_PER_UNIT, | |
2249 | MODE_INT, 1), | |
2250 | adjust); | |
2251 | } | |
02db8dd0 | 2252 | |
2af2dbdc | 2253 | if (! dont_share_p && ira_conflicts_p) |
058e97ec | 2254 | /* Inform IRA about allocation a new stack slot. */ |
13d7e8af | 2255 | ira_mark_new_stack_slot (stack_slot, i, total_size); |
32131a9c | 2256 | } |
3bdf5ad1 | 2257 | |
32131a9c RK |
2258 | /* Reuse a stack slot if possible. */ |
2259 | else if (spill_stack_slot[from_reg] != 0 | |
2260 | && spill_stack_slot_width[from_reg] >= total_size | |
2261 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
63a7a62b RS |
2262 | >= inherent_size) |
2263 | && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align) | |
32131a9c | 2264 | x = spill_stack_slot[from_reg]; |
f6129d66 | 2265 | |
32131a9c RK |
2266 | /* Allocate a bigger slot. */ |
2267 | else | |
2268 | { | |
2269 | /* Compute maximum size needed, both for inherent size | |
2270 | and for total size. */ | |
4f2d3674 | 2271 | rtx stack_slot; |
3bdf5ad1 | 2272 | |
32131a9c RK |
2273 | if (spill_stack_slot[from_reg]) |
2274 | { | |
2275 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
2276 | > inherent_size) | |
2277 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
2278 | if (spill_stack_slot_width[from_reg] > total_size) | |
2279 | total_size = spill_stack_slot_width[from_reg]; | |
63a7a62b RS |
2280 | if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align) |
2281 | min_align = MEM_ALIGN (spill_stack_slot[from_reg]); | |
32131a9c | 2282 | } |
3bdf5ad1 | 2283 | |
32131a9c | 2284 | /* Make a slot with that size. */ |
cabcf079 | 2285 | x = assign_stack_local (mode, total_size, |
63a7a62b RS |
2286 | min_align > inherent_align |
2287 | || total_size > inherent_size ? -1 : 0); | |
4f2d3674 | 2288 | stack_slot = x; |
3bdf5ad1 | 2289 | |
f6129d66 RH |
2290 | /* Cancel the big-endian correction done in assign_stack_local. |
2291 | Get the address of the beginning of the slot. This is so we | |
2292 | can do a big-endian correction unconditionally below. */ | |
f76b9db2 ILT |
2293 | if (BYTES_BIG_ENDIAN) |
2294 | { | |
f76b9db2 | 2295 | adjust = GET_MODE_SIZE (mode) - total_size; |
4f2d3674 | 2296 | if (adjust) |
8ac61af7 RK |
2297 | stack_slot |
2298 | = adjust_address_nv (x, mode_for_size (total_size | |
38a448ca RH |
2299 | * BITS_PER_UNIT, |
2300 | MODE_INT, 1), | |
8ac61af7 | 2301 | adjust); |
f76b9db2 | 2302 | } |
3bdf5ad1 | 2303 | |
4f2d3674 | 2304 | spill_stack_slot[from_reg] = stack_slot; |
32131a9c RK |
2305 | spill_stack_slot_width[from_reg] = total_size; |
2306 | } | |
2307 | ||
32131a9c RK |
2308 | /* On a big endian machine, the "address" of the slot |
2309 | is the address of the low part that fits its inherent mode. */ | |
f76b9db2 | 2310 | if (BYTES_BIG_ENDIAN && inherent_size < total_size) |
32131a9c | 2311 | adjust += (total_size - inherent_size); |
32131a9c RK |
2312 | |
2313 | /* If we have any adjustment to make, or if the stack slot is the | |
2314 | wrong mode, make a new stack slot. */ | |
1285011e RK |
2315 | x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); |
2316 | ||
f6129d66 RH |
2317 | /* Set all of the memory attributes as appropriate for a spill. */ |
2318 | set_mem_attrs_for_spill (x); | |
32131a9c | 2319 | |
6d2f8887 | 2320 | /* Save the stack slot for later. */ |
32131a9c RK |
2321 | reg_equiv_memory_loc[i] = x; |
2322 | } | |
2323 | } | |
2324 | ||
6fb5fa3c DB |
2325 | /* Mark the slots in regs_ever_live for the hard regs used by |
2326 | pseudo-reg number REGNO, accessed in MODE. */ | |
32131a9c | 2327 | |
6fb5fa3c DB |
2328 | static void |
2329 | mark_home_live_1 (int regno, enum machine_mode mode) | |
32131a9c | 2330 | { |
b3694847 | 2331 | int i, lim; |
770ae6cc | 2332 | |
32131a9c RK |
2333 | i = reg_renumber[regno]; |
2334 | if (i < 0) | |
2335 | return; | |
b0384c54 | 2336 | lim = end_hard_regno (mode, i); |
32131a9c | 2337 | while (i < lim) |
6fb5fa3c DB |
2338 | df_set_regs_ever_live(i++, true); |
2339 | } | |
2340 | ||
2341 | /* Mark the slots in regs_ever_live for the hard regs | |
2342 | used by pseudo-reg number REGNO. */ | |
2343 | ||
2344 | void | |
2345 | mark_home_live (int regno) | |
2346 | { | |
2347 | if (reg_renumber[regno] >= 0) | |
2348 | mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno)); | |
32131a9c RK |
2349 | } |
2350 | \f | |
2351 | /* This function handles the tracking of elimination offsets around branches. | |
2352 | ||
2353 | X is a piece of RTL being scanned. | |
2354 | ||
2355 | INSN is the insn that it came from, if any. | |
2356 | ||
40f03658 | 2357 | INITIAL_P is nonzero if we are to set the offset to be the initial |
32131a9c RK |
2358 | offset and zero if we are setting the offset of the label to be the |
2359 | current offset. */ | |
2360 | ||
2361 | static void | |
0c20a65f | 2362 | set_label_offsets (rtx x, rtx insn, int initial_p) |
32131a9c RK |
2363 | { |
2364 | enum rtx_code code = GET_CODE (x); | |
2365 | rtx tem; | |
e51712db | 2366 | unsigned int i; |
32131a9c RK |
2367 | struct elim_table *p; |
2368 | ||
2369 | switch (code) | |
2370 | { | |
2371 | case LABEL_REF: | |
8be386d9 RS |
2372 | if (LABEL_REF_NONLOCAL_P (x)) |
2373 | return; | |
2374 | ||
32131a9c RK |
2375 | x = XEXP (x, 0); |
2376 | ||
0f41302f | 2377 | /* ... fall through ... */ |
32131a9c RK |
2378 | |
2379 | case CODE_LABEL: | |
2380 | /* If we know nothing about this label, set the desired offsets. Note | |
2381 | that this sets the offset at a label to be the offset before a label | |
2382 | if we don't know anything about the label. This is not correct for | |
2383 | the label after a BARRIER, but is the best guess we can make. If | |
2384 | we guessed wrong, we will suppress an elimination that might have | |
2385 | been possible had we been able to guess correctly. */ | |
2386 | ||
4cc0fdd2 | 2387 | if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num]) |
32131a9c RK |
2388 | { |
2389 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
4cc0fdd2 | 2390 | offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] |
32131a9c RK |
2391 | = (initial_p ? reg_eliminate[i].initial_offset |
2392 | : reg_eliminate[i].offset); | |
4cc0fdd2 | 2393 | offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1; |
32131a9c RK |
2394 | } |
2395 | ||
2396 | /* Otherwise, if this is the definition of a label and it is | |
d45cf215 | 2397 | preceded by a BARRIER, set our offsets to the known offset of |
32131a9c RK |
2398 | that label. */ |
2399 | ||
2400 | else if (x == insn | |
2401 | && (tem = prev_nonnote_insn (insn)) != 0 | |
4b4bf941 | 2402 | && BARRIER_P (tem)) |
1f3b1e1a | 2403 | set_offsets_for_label (insn); |
32131a9c RK |
2404 | else |
2405 | /* If neither of the above cases is true, compare each offset | |
2406 | with those previously recorded and suppress any eliminations | |
2407 | where the offsets disagree. */ | |
a8fdc208 | 2408 | |
32131a9c | 2409 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) |
4cc0fdd2 | 2410 | if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] |
32131a9c RK |
2411 | != (initial_p ? reg_eliminate[i].initial_offset |
2412 | : reg_eliminate[i].offset)) | |
2413 | reg_eliminate[i].can_eliminate = 0; | |
2414 | ||
2415 | return; | |
2416 | ||
2417 | case JUMP_INSN: | |
2418 | set_label_offsets (PATTERN (insn), insn, initial_p); | |
2419 | ||
0f41302f | 2420 | /* ... fall through ... */ |
32131a9c RK |
2421 | |
2422 | case INSN: | |
2423 | case CALL_INSN: | |
cf7c4aa6 HPN |
2424 | /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched |
2425 | to indirectly and hence must have all eliminations at their | |
2426 | initial offsets. */ | |
32131a9c | 2427 | for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) |
cf7c4aa6 | 2428 | if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND) |
32131a9c RK |
2429 | set_label_offsets (XEXP (tem, 0), insn, 1); |
2430 | return; | |
2431 | ||
0c0ba09c | 2432 | case PARALLEL: |
32131a9c RK |
2433 | case ADDR_VEC: |
2434 | case ADDR_DIFF_VEC: | |
0c0ba09c JJ |
2435 | /* Each of the labels in the parallel or address vector must be |
2436 | at their initial offsets. We want the first field for PARALLEL | |
2437 | and ADDR_VEC and the second field for ADDR_DIFF_VEC. */ | |
32131a9c | 2438 | |
e51712db | 2439 | for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) |
32131a9c RK |
2440 | set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), |
2441 | insn, initial_p); | |
2442 | return; | |
2443 | ||
2444 | case SET: | |
2445 | /* We only care about setting PC. If the source is not RETURN, | |
2446 | IF_THEN_ELSE, or a label, disable any eliminations not at | |
2447 | their initial offsets. Similarly if any arm of the IF_THEN_ELSE | |
2448 | isn't one of those possibilities. For branches to a label, | |
2449 | call ourselves recursively. | |
2450 | ||
2451 | Note that this can disable elimination unnecessarily when we have | |
2452 | a non-local goto since it will look like a non-constant jump to | |
2453 | someplace in the current function. This isn't a significant | |
2454 | problem since such jumps will normally be when all elimination | |
2455 | pairs are back to their initial offsets. */ | |
2456 | ||
2457 | if (SET_DEST (x) != pc_rtx) | |
2458 | return; | |
2459 | ||
2460 | switch (GET_CODE (SET_SRC (x))) | |
2461 | { | |
2462 | case PC: | |
2463 | case RETURN: | |
2464 | return; | |
2465 | ||
2466 | case LABEL_REF: | |
8f235343 | 2467 | set_label_offsets (SET_SRC (x), insn, initial_p); |
32131a9c RK |
2468 | return; |
2469 | ||
2470 | case IF_THEN_ELSE: | |
2471 | tem = XEXP (SET_SRC (x), 1); | |
2472 | if (GET_CODE (tem) == LABEL_REF) | |
2473 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2474 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2475 | break; | |
2476 | ||
2477 | tem = XEXP (SET_SRC (x), 2); | |
2478 | if (GET_CODE (tem) == LABEL_REF) | |
2479 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2480 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2481 | break; | |
2482 | return; | |
e9a25f70 JL |
2483 | |
2484 | default: | |
2485 | break; | |
32131a9c RK |
2486 | } |
2487 | ||
2488 | /* If we reach here, all eliminations must be at their initial | |
2489 | offset because we are doing a jump to a variable address. */ | |
2490 | for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) | |
2491 | if (p->offset != p->initial_offset) | |
2492 | p->can_eliminate = 0; | |
e9a25f70 | 2493 | break; |
05d10675 | 2494 | |
e9a25f70 JL |
2495 | default: |
2496 | break; | |
32131a9c RK |
2497 | } |
2498 | } | |
2499 | \f | |
a8fdc208 | 2500 | /* Scan X and replace any eliminable registers (such as fp) with a |
32131a9c RK |
2501 | replacement (such as sp), plus an offset. |
2502 | ||
2503 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
2504 | much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a | |
2505 | MEM, we are allowed to replace a sum of a register and the constant zero | |
2506 | with the register, which we cannot do outside a MEM. In addition, we need | |
2507 | to record the fact that a register is referenced outside a MEM. | |
2508 | ||
ff32812a | 2509 | If INSN is an insn, it is the insn containing X. If we replace a REG |
40f03658 | 2510 | in a SET_DEST with an equivalent MEM and INSN is nonzero, write a |
32131a9c | 2511 | CLOBBER of the pseudo after INSN so find_equiv_regs will know that |
38e01259 | 2512 | the REG is being modified. |
32131a9c | 2513 | |
ff32812a RS |
2514 | Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). |
2515 | That's used when we eliminate in expressions stored in notes. | |
2516 | This means, do not set ref_outside_mem even if the reference | |
2517 | is outside of MEMs. | |
2518 | ||
32131a9c RK |
2519 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had |
2520 | replacements done assuming all offsets are at their initial values. If | |
2521 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | |
2522 | encounter, return the actual location so that find_reloads will do | |
2523 | the proper thing. */ | |
2524 | ||
ab156144 RH |
2525 | static rtx |
2526 | eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn, | |
2527 | bool may_use_invariant) | |
32131a9c RK |
2528 | { |
2529 | enum rtx_code code = GET_CODE (x); | |
2530 | struct elim_table *ep; | |
2531 | int regno; | |
55d796da | 2532 | rtx new_rtx; |
32131a9c | 2533 | int i, j; |
6f7d635c | 2534 | const char *fmt; |
32131a9c RK |
2535 | int copied = 0; |
2536 | ||
d6633f01 NS |
2537 | if (! current_function_decl) |
2538 | return x; | |
9969bb2c | 2539 | |
32131a9c RK |
2540 | switch (code) |
2541 | { | |
2542 | case CONST_INT: | |
2543 | case CONST_DOUBLE: | |
091a3ac7 | 2544 | case CONST_FIXED: |
69ef87e2 | 2545 | case CONST_VECTOR: |
32131a9c RK |
2546 | case CONST: |
2547 | case SYMBOL_REF: | |
2548 | case CODE_LABEL: | |
2549 | case PC: | |
2550 | case CC0: | |
2551 | case ASM_INPUT: | |
2552 | case ADDR_VEC: | |
2553 | case ADDR_DIFF_VEC: | |
2554 | case RETURN: | |
2555 | return x; | |
2556 | ||
2557 | case REG: | |
2558 | regno = REGNO (x); | |
2559 | ||
2560 | /* First handle the case where we encounter a bare register that | |
2561 | is eliminable. Replace it with a PLUS. */ | |
2562 | if (regno < FIRST_PSEUDO_REGISTER) | |
2563 | { | |
2564 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2565 | ep++) | |
2566 | if (ep->from_rtx == x && ep->can_eliminate) | |
dfac187e | 2567 | return plus_constant (ep->to_rtx, ep->previous_offset); |
32131a9c RK |
2568 | |
2569 | } | |
cd7c9015 | 2570 | else if (reg_renumber && reg_renumber[regno] < 0 |
ab156144 RH |
2571 | && reg_equiv_invariant && reg_equiv_invariant[regno]) |
2572 | { | |
2573 | if (may_use_invariant) | |
2574 | return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]), | |
2575 | mem_mode, insn, true); | |
2576 | /* There exists at least one use of REGNO that cannot be | |
2577 | eliminated. Prevent the defining insn from being deleted. */ | |
2578 | reg_equiv_init[regno] = NULL_RTX; | |
058e97ec | 2579 | alter_reg (regno, -1, true); |
ab156144 | 2580 | } |
32131a9c RK |
2581 | return x; |
2582 | ||
c5c76735 JL |
2583 | /* You might think handling MINUS in a manner similar to PLUS is a |
2584 | good idea. It is not. It has been tried multiple times and every | |
2585 | time the change has had to have been reverted. | |
2586 | ||
2587 | Other parts of reload know a PLUS is special (gen_reload for example) | |
2588 | and require special code to handle code a reloaded PLUS operand. | |
2589 | ||
2590 | Also consider backends where the flags register is clobbered by a | |
a457ee07 | 2591 | MINUS, but we can emit a PLUS that does not clobber flags (IA-32, |
c5c76735 JL |
2592 | lea instruction comes to mind). If we try to reload a MINUS, we |
2593 | may kill the flags register that was holding a useful value. | |
2594 | ||
2595 | So, please before trying to handle MINUS, consider reload as a | |
2596 | whole instead of this little section as well as the backend issues. */ | |
32131a9c RK |
2597 | case PLUS: |
2598 | /* If this is the sum of an eliminable register and a constant, rework | |
6d2f8887 | 2599 | the sum. */ |
f8cfc6aa | 2600 | if (REG_P (XEXP (x, 0)) |
32131a9c RK |
2601 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER |
2602 | && CONSTANT_P (XEXP (x, 1))) | |
2603 | { | |
2604 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2605 | ep++) | |
2606 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2607 | { | |
32131a9c RK |
2608 | /* The only time we want to replace a PLUS with a REG (this |
2609 | occurs when the constant operand of the PLUS is the negative | |
2610 | of the offset) is when we are inside a MEM. We won't want | |
2611 | to do so at other times because that would change the | |
2612 | structure of the insn in a way that reload can't handle. | |
2613 | We special-case the commonest situation in | |
2614 | eliminate_regs_in_insn, so just replace a PLUS with a | |
2615 | PLUS here, unless inside a MEM. */ | |
481683e1 | 2616 | if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1)) |
32131a9c RK |
2617 | && INTVAL (XEXP (x, 1)) == - ep->previous_offset) |
2618 | return ep->to_rtx; | |
2619 | else | |
38a448ca RH |
2620 | return gen_rtx_PLUS (Pmode, ep->to_rtx, |
2621 | plus_constant (XEXP (x, 1), | |
2622 | ep->previous_offset)); | |
32131a9c RK |
2623 | } |
2624 | ||
2625 | /* If the register is not eliminable, we are done since the other | |
2626 | operand is a constant. */ | |
2627 | return x; | |
2628 | } | |
2629 | ||
2630 | /* If this is part of an address, we want to bring any constant to the | |
2631 | outermost PLUS. We will do this by doing register replacement in | |
2632 | our operands and seeing if a constant shows up in one of them. | |
2633 | ||
dfac187e BS |
2634 | Note that there is no risk of modifying the structure of the insn, |
2635 | since we only get called for its operands, thus we are either | |
2636 | modifying the address inside a MEM, or something like an address | |
2637 | operand of a load-address insn. */ | |
32131a9c RK |
2638 | |
2639 | { | |
ab156144 RH |
2640 | rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); |
2641 | rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); | |
32131a9c | 2642 | |
cd7c9015 | 2643 | if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))) |
32131a9c RK |
2644 | { |
2645 | /* If one side is a PLUS and the other side is a pseudo that | |
a8fdc208 | 2646 | didn't get a hard register but has a reg_equiv_constant, |
32131a9c RK |
2647 | we must replace the constant here since it may no longer |
2648 | be in the position of any operand. */ | |
f8cfc6aa | 2649 | if (GET_CODE (new0) == PLUS && REG_P (new1) |
32131a9c RK |
2650 | && REGNO (new1) >= FIRST_PSEUDO_REGISTER |
2651 | && reg_renumber[REGNO (new1)] < 0 | |
2652 | && reg_equiv_constant != 0 | |
2653 | && reg_equiv_constant[REGNO (new1)] != 0) | |
2654 | new1 = reg_equiv_constant[REGNO (new1)]; | |
f8cfc6aa | 2655 | else if (GET_CODE (new1) == PLUS && REG_P (new0) |
32131a9c RK |
2656 | && REGNO (new0) >= FIRST_PSEUDO_REGISTER |
2657 | && reg_renumber[REGNO (new0)] < 0 | |
2658 | && reg_equiv_constant[REGNO (new0)] != 0) | |
2659 | new0 = reg_equiv_constant[REGNO (new0)]; | |
2660 | ||
d4ebfa65 | 2661 | new_rtx = form_sum (GET_MODE (x), new0, new1); |
32131a9c RK |
2662 | |
2663 | /* As above, if we are not inside a MEM we do not want to | |
2664 | turn a PLUS into something else. We might try to do so here | |
2665 | for an addition of 0 if we aren't optimizing. */ | |
55d796da KG |
2666 | if (! mem_mode && GET_CODE (new_rtx) != PLUS) |
2667 | return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx); | |
32131a9c | 2668 | else |
55d796da | 2669 | return new_rtx; |
32131a9c RK |
2670 | } |
2671 | } | |
2672 | return x; | |
2673 | ||
981c7390 | 2674 | case MULT: |
05d10675 | 2675 | /* If this is the product of an eliminable register and a |
981c7390 RK |
2676 | constant, apply the distribute law and move the constant out |
2677 | so that we have (plus (mult ..) ..). This is needed in order | |
9faa82d8 | 2678 | to keep load-address insns valid. This case is pathological. |
981c7390 | 2679 | We ignore the possibility of overflow here. */ |
f8cfc6aa | 2680 | if (REG_P (XEXP (x, 0)) |
981c7390 | 2681 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER |
481683e1 | 2682 | && CONST_INT_P (XEXP (x, 1))) |
981c7390 RK |
2683 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; |
2684 | ep++) | |
2685 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2686 | { | |
2687 | if (! mem_mode | |
2688 | /* Refs inside notes don't count for this purpose. */ | |
2689 | && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST | |
2690 | || GET_CODE (insn) == INSN_LIST))) | |
2691 | ep->ref_outside_mem = 1; | |
2692 | ||
2693 | return | |
38a448ca | 2694 | plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), |
981c7390 RK |
2695 | ep->previous_offset * INTVAL (XEXP (x, 1))); |
2696 | } | |
32131a9c | 2697 | |
0f41302f | 2698 | /* ... fall through ... */ |
32131a9c | 2699 | |
32131a9c RK |
2700 | case CALL: |
2701 | case COMPARE: | |
c5c76735 | 2702 | /* See comments before PLUS about handling MINUS. */ |
930aeef3 | 2703 | case MINUS: |
32131a9c RK |
2704 | case DIV: case UDIV: |
2705 | case MOD: case UMOD: | |
2706 | case AND: case IOR: case XOR: | |
45620ed4 RK |
2707 | case ROTATERT: case ROTATE: |
2708 | case ASHIFTRT: case LSHIFTRT: case ASHIFT: | |
32131a9c RK |
2709 | case NE: case EQ: |
2710 | case GE: case GT: case GEU: case GTU: | |
2711 | case LE: case LT: case LEU: case LTU: | |
2712 | { | |
ab156144 RH |
2713 | rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); |
2714 | rtx new1 = XEXP (x, 1) | |
2715 | ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0; | |
32131a9c RK |
2716 | |
2717 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
38a448ca | 2718 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); |
32131a9c RK |
2719 | } |
2720 | return x; | |
2721 | ||
981c7390 RK |
2722 | case EXPR_LIST: |
2723 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | |
2724 | if (XEXP (x, 0)) | |
2725 | { | |
55d796da KG |
2726 | new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); |
2727 | if (new_rtx != XEXP (x, 0)) | |
13bb79d4 R |
2728 | { |
2729 | /* If this is a REG_DEAD note, it is not valid anymore. | |
2730 | Using the eliminated version could result in creating a | |
2731 | REG_DEAD note for the stack or frame pointer. */ | |
e0c68ce9 | 2732 | if (REG_NOTE_KIND (x) == REG_DEAD) |
13bb79d4 | 2733 | return (XEXP (x, 1) |
ab156144 | 2734 | ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true) |
13bb79d4 R |
2735 | : NULL_RTX); |
2736 | ||
efc0b2bd | 2737 | x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1)); |
13bb79d4 | 2738 | } |
981c7390 RK |
2739 | } |
2740 | ||
0f41302f | 2741 | /* ... fall through ... */ |
981c7390 RK |
2742 | |
2743 | case INSN_LIST: | |
2744 | /* Now do eliminations in the rest of the chain. If this was | |
2745 | an EXPR_LIST, this might result in allocating more memory than is | |
2746 | strictly needed, but it simplifies the code. */ | |
2747 | if (XEXP (x, 1)) | |
2748 | { | |
55d796da KG |
2749 | new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); |
2750 | if (new_rtx != XEXP (x, 1)) | |
cd7c9015 | 2751 | return |
55d796da | 2752 | gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx); |
981c7390 RK |
2753 | } |
2754 | return x; | |
2755 | ||
32131a9c RK |
2756 | case PRE_INC: |
2757 | case POST_INC: | |
2758 | case PRE_DEC: | |
2759 | case POST_DEC: | |
b098aaf2 UW |
2760 | /* We do not support elimination of a register that is modified. |
2761 | elimination_effects has already make sure that this does not | |
2762 | happen. */ | |
2763 | return x; | |
2764 | ||
2765 | case PRE_MODIFY: | |
2766 | case POST_MODIFY: | |
2767 | /* We do not support elimination of a register that is modified. | |
2768 | elimination_effects has already make sure that this does not | |
2769 | happen. The only remaining case we need to consider here is | |
2770 | that the increment value may be an eliminable register. */ | |
2771 | if (GET_CODE (XEXP (x, 1)) == PLUS | |
2772 | && XEXP (XEXP (x, 1), 0) == XEXP (x, 0)) | |
2773 | { | |
55d796da | 2774 | rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode, |
b098aaf2 UW |
2775 | insn, true); |
2776 | ||
55d796da | 2777 | if (new_rtx != XEXP (XEXP (x, 1), 1)) |
b098aaf2 UW |
2778 | return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0), |
2779 | gen_rtx_PLUS (GET_MODE (x), | |
55d796da | 2780 | XEXP (x, 0), new_rtx)); |
b098aaf2 UW |
2781 | } |
2782 | return x; | |
2783 | ||
32131a9c RK |
2784 | case STRICT_LOW_PART: |
2785 | case NEG: case NOT: | |
2786 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2787 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2788 | case FLOAT: case FIX: | |
2789 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2790 | case ABS: | |
2791 | case SQRT: | |
2792 | case FFS: | |
2928cd7a RH |
2793 | case CLZ: |
2794 | case CTZ: | |
2795 | case POPCOUNT: | |
2796 | case PARITY: | |
167fa32c | 2797 | case BSWAP: |
55d796da KG |
2798 | new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); |
2799 | if (new_rtx != XEXP (x, 0)) | |
2800 | return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx); | |
32131a9c RK |
2801 | return x; |
2802 | ||
2803 | case SUBREG: | |
ddef6bc7 | 2804 | /* Similar to above processing, but preserve SUBREG_BYTE. |
32131a9c RK |
2805 | Convert (subreg (mem)) to (mem) if not paradoxical. |
2806 | Also, if we have a non-paradoxical (subreg (pseudo)) and the | |
2807 | pseudo didn't get a hard reg, we must replace this with the | |
bd235d86 | 2808 | eliminated version of the memory location because push_reload |
32131a9c | 2809 | may do the replacement in certain circumstances. */ |
f8cfc6aa | 2810 | if (REG_P (SUBREG_REG (x)) |
32131a9c RK |
2811 | && (GET_MODE_SIZE (GET_MODE (x)) |
2812 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2813 | && reg_equiv_memory_loc != 0 | |
2814 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2815 | { | |
55d796da | 2816 | new_rtx = SUBREG_REG (x); |
32131a9c RK |
2817 | } |
2818 | else | |
55d796da | 2819 | new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false); |
32131a9c | 2820 | |
55d796da | 2821 | if (new_rtx != SUBREG_REG (x)) |
32131a9c | 2822 | { |
29ae5012 | 2823 | int x_size = GET_MODE_SIZE (GET_MODE (x)); |
55d796da | 2824 | int new_size = GET_MODE_SIZE (GET_MODE (new_rtx)); |
29ae5012 | 2825 | |
55d796da | 2826 | if (MEM_P (new_rtx) |
6d49a073 | 2827 | && ((x_size < new_size |
1914f5da | 2828 | #ifdef WORD_REGISTER_OPERATIONS |
6d49a073 JW |
2829 | /* On these machines, combine can create rtl of the form |
2830 | (set (subreg:m1 (reg:m2 R) 0) ...) | |
05d10675 | 2831 | where m1 < m2, and expects something interesting to |
6d49a073 JW |
2832 | happen to the entire word. Moreover, it will use the |
2833 | (reg:m2 R) later, expecting all bits to be preserved. | |
05d10675 | 2834 | So if the number of words is the same, preserve the |
bd235d86 | 2835 | subreg so that push_reload can see it. */ |
5d9669fd RK |
2836 | && ! ((x_size - 1) / UNITS_PER_WORD |
2837 | == (new_size -1 ) / UNITS_PER_WORD) | |
1914f5da | 2838 | #endif |
6d49a073 | 2839 | ) |
5d9669fd | 2840 | || x_size == new_size) |
1914f5da | 2841 | ) |
55d796da | 2842 | return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x)); |
32131a9c | 2843 | else |
55d796da | 2844 | return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x)); |
32131a9c RK |
2845 | } |
2846 | ||
2847 | return x; | |
2848 | ||
32131a9c RK |
2849 | case MEM: |
2850 | /* Our only special processing is to pass the mode of the MEM to our | |
2851 | recursive call and copy the flags. While we are here, handle this | |
2852 | case more efficiently. */ | |
f1ec5147 RK |
2853 | return |
2854 | replace_equiv_address_nv (x, | |
ab156144 RH |
2855 | eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), |
2856 | insn, true)); | |
05d10675 | 2857 | |
dfac187e | 2858 | case USE: |
055c7759 | 2859 | /* Handle insn_list USE that a call to a pure function may generate. */ |
bbbbb16a | 2860 | new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false); |
55d796da KG |
2861 | if (new_rtx != XEXP (x, 0)) |
2862 | return gen_rtx_USE (GET_MODE (x), new_rtx); | |
055c7759 JDA |
2863 | return x; |
2864 | ||
dfac187e BS |
2865 | case CLOBBER: |
2866 | case ASM_OPERANDS: | |
2867 | case SET: | |
41374e13 | 2868 | gcc_unreachable (); |
dfac187e | 2869 | |
e9a25f70 JL |
2870 | default: |
2871 | break; | |
32131a9c RK |
2872 | } |
2873 | ||
2874 | /* Process each of our operands recursively. If any have changed, make a | |
2875 | copy of the rtx. */ | |
2876 | fmt = GET_RTX_FORMAT (code); | |
2877 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2878 | { | |
2879 | if (*fmt == 'e') | |
2880 | { | |
55d796da KG |
2881 | new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false); |
2882 | if (new_rtx != XEXP (x, i) && ! copied) | |
32131a9c | 2883 | { |
aacd3885 | 2884 | x = shallow_copy_rtx (x); |
32131a9c RK |
2885 | copied = 1; |
2886 | } | |
55d796da | 2887 | XEXP (x, i) = new_rtx; |
32131a9c RK |
2888 | } |
2889 | else if (*fmt == 'E') | |
2890 | { | |
2891 | int copied_vec = 0; | |
2892 | for (j = 0; j < XVECLEN (x, i); j++) | |
2893 | { | |
55d796da KG |
2894 | new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false); |
2895 | if (new_rtx != XVECEXP (x, i, j) && ! copied_vec) | |
32131a9c | 2896 | { |
8f985ec4 ZW |
2897 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), |
2898 | XVEC (x, i)->elem); | |
32131a9c RK |
2899 | if (! copied) |
2900 | { | |
aacd3885 | 2901 | x = shallow_copy_rtx (x); |
32131a9c RK |
2902 | copied = 1; |
2903 | } | |
2904 | XVEC (x, i) = new_v; | |
2905 | copied_vec = 1; | |
2906 | } | |
55d796da | 2907 | XVECEXP (x, i, j) = new_rtx; |
32131a9c RK |
2908 | } |
2909 | } | |
2910 | } | |
2911 | ||
2912 | return x; | |
2913 | } | |
dfac187e | 2914 | |
ab156144 RH |
2915 | rtx |
2916 | eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn) | |
2917 | { | |
2918 | return eliminate_regs_1 (x, mem_mode, insn, false); | |
2919 | } | |
2920 | ||
dfac187e BS |
2921 | /* Scan rtx X for modifications of elimination target registers. Update |
2922 | the table of eliminables to reflect the changed state. MEM_MODE is | |
2923 | the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ | |
2924 | ||
2925 | static void | |
0c20a65f | 2926 | elimination_effects (rtx x, enum machine_mode mem_mode) |
dfac187e BS |
2927 | { |
2928 | enum rtx_code code = GET_CODE (x); | |
2929 | struct elim_table *ep; | |
2930 | int regno; | |
2931 | int i, j; | |
2932 | const char *fmt; | |
2933 | ||
2934 | switch (code) | |
2935 | { | |
2936 | case CONST_INT: | |
2937 | case CONST_DOUBLE: | |
091a3ac7 | 2938 | case CONST_FIXED: |
69ef87e2 | 2939 | case CONST_VECTOR: |
dfac187e BS |
2940 | case CONST: |
2941 | case SYMBOL_REF: | |
2942 | case CODE_LABEL: | |
2943 | case PC: | |
2944 | case CC0: | |
2945 | case ASM_INPUT: | |
2946 | case ADDR_VEC: | |
2947 | case ADDR_DIFF_VEC: | |
2948 | case RETURN: | |
2949 | return; | |
2950 | ||
dfac187e BS |
2951 | case REG: |
2952 | regno = REGNO (x); | |
2953 | ||
2954 | /* First handle the case where we encounter a bare register that | |
2955 | is eliminable. Replace it with a PLUS. */ | |
2956 | if (regno < FIRST_PSEUDO_REGISTER) | |
2957 | { | |
2958 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2959 | ep++) | |
2960 | if (ep->from_rtx == x && ep->can_eliminate) | |
2961 | { | |
2962 | if (! mem_mode) | |
2963 | ep->ref_outside_mem = 1; | |
2964 | return; | |
2965 | } | |
2966 | ||
2967 | } | |
2968 | else if (reg_renumber[regno] < 0 && reg_equiv_constant | |
2969 | && reg_equiv_constant[regno] | |
92a21141 | 2970 | && ! function_invariant_p (reg_equiv_constant[regno])) |
dfac187e BS |
2971 | elimination_effects (reg_equiv_constant[regno], mem_mode); |
2972 | return; | |
2973 | ||
2974 | case PRE_INC: | |
2975 | case POST_INC: | |
2976 | case PRE_DEC: | |
2977 | case POST_DEC: | |
4b983fdc RH |
2978 | case POST_MODIFY: |
2979 | case PRE_MODIFY: | |
b098aaf2 UW |
2980 | /* If we modify the source of an elimination rule, disable it. */ |
2981 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2982 | if (ep->from_rtx == XEXP (x, 0)) | |
2983 | ep->can_eliminate = 0; | |
2984 | ||
2985 | /* If we modify the target of an elimination rule by adding a constant, | |
2986 | update its offset. If we modify the target in any other way, we'll | |
2987 | have to disable the rule as well. */ | |
dfac187e BS |
2988 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
2989 | if (ep->to_rtx == XEXP (x, 0)) | |
2990 | { | |
2991 | int size = GET_MODE_SIZE (mem_mode); | |
2992 | ||
2993 | /* If more bytes than MEM_MODE are pushed, account for them. */ | |
2994 | #ifdef PUSH_ROUNDING | |
2995 | if (ep->to_rtx == stack_pointer_rtx) | |
2996 | size = PUSH_ROUNDING (size); | |
2997 | #endif | |
2998 | if (code == PRE_DEC || code == POST_DEC) | |
2999 | ep->offset += size; | |
4b983fdc | 3000 | else if (code == PRE_INC || code == POST_INC) |
dfac187e | 3001 | ep->offset -= size; |
b098aaf2 UW |
3002 | else if (code == PRE_MODIFY || code == POST_MODIFY) |
3003 | { | |
3004 | if (GET_CODE (XEXP (x, 1)) == PLUS | |
3005 | && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) | |
3006 | && CONST_INT_P (XEXP (XEXP (x, 1), 1))) | |
3007 | ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1)); | |
3008 | else | |
3009 | ep->can_eliminate = 0; | |
3010 | } | |
dfac187e BS |
3011 | } |
3012 | ||
4b983fdc RH |
3013 | /* These two aren't unary operators. */ |
3014 | if (code == POST_MODIFY || code == PRE_MODIFY) | |
3015 | break; | |
3016 | ||
dfac187e BS |
3017 | /* Fall through to generic unary operation case. */ |
3018 | case STRICT_LOW_PART: | |
3019 | case NEG: case NOT: | |
3020 | case SIGN_EXTEND: case ZERO_EXTEND: | |
3021 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
3022 | case FLOAT: case FIX: | |
3023 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
3024 | case ABS: | |
3025 | case SQRT: | |
3026 | case FFS: | |
2928cd7a RH |
3027 | case CLZ: |
3028 | case CTZ: | |
3029 | case POPCOUNT: | |
3030 | case PARITY: | |
167fa32c | 3031 | case BSWAP: |
dfac187e BS |
3032 | elimination_effects (XEXP (x, 0), mem_mode); |
3033 | return; | |
3034 | ||
3035 | case SUBREG: | |
f8cfc6aa | 3036 | if (REG_P (SUBREG_REG (x)) |
dfac187e BS |
3037 | && (GET_MODE_SIZE (GET_MODE (x)) |
3038 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
3039 | && reg_equiv_memory_loc != 0 | |
3040 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
3041 | return; | |
3042 | ||
3043 | elimination_effects (SUBREG_REG (x), mem_mode); | |
3044 | return; | |
3045 | ||
3046 | case USE: | |
3047 | /* If using a register that is the source of an eliminate we still | |
3048 | think can be performed, note it cannot be performed since we don't | |
3049 | know how this register is used. */ | |
3050 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3051 | if (ep->from_rtx == XEXP (x, 0)) | |
3052 | ep->can_eliminate = 0; | |
3053 | ||
3054 | elimination_effects (XEXP (x, 0), mem_mode); | |
3055 | return; | |
3056 | ||
3057 | case CLOBBER: | |
3058 | /* If clobbering a register that is the replacement register for an | |
3059 | elimination we still think can be performed, note that it cannot | |
3060 | be performed. Otherwise, we need not be concerned about it. */ | |
3061 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3062 | if (ep->to_rtx == XEXP (x, 0)) | |
3063 | ep->can_eliminate = 0; | |
3064 | ||
3065 | elimination_effects (XEXP (x, 0), mem_mode); | |
3066 | return; | |
3067 | ||
3068 | case SET: | |
3069 | /* Check for setting a register that we know about. */ | |
f8cfc6aa | 3070 | if (REG_P (SET_DEST (x))) |
dfac187e BS |
3071 | { |
3072 | /* See if this is setting the replacement register for an | |
3073 | elimination. | |
3074 | ||
3075 | If DEST is the hard frame pointer, we do nothing because we | |
3076 | assume that all assignments to the frame pointer are for | |
3077 | non-local gotos and are being done at a time when they are valid | |
3078 | and do not disturb anything else. Some machines want to | |
3079 | eliminate a fake argument pointer (or even a fake frame pointer) | |
3080 | with either the real frame or the stack pointer. Assignments to | |
3081 | the hard frame pointer must not prevent this elimination. */ | |
3082 | ||
3083 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
3084 | ep++) | |
3085 | if (ep->to_rtx == SET_DEST (x) | |
3086 | && SET_DEST (x) != hard_frame_pointer_rtx) | |
3087 | { | |
3088 | /* If it is being incremented, adjust the offset. Otherwise, | |
3089 | this elimination can't be done. */ | |
3090 | rtx src = SET_SRC (x); | |
3091 | ||
3092 | if (GET_CODE (src) == PLUS | |
3093 | && XEXP (src, 0) == SET_DEST (x) | |
481683e1 | 3094 | && CONST_INT_P (XEXP (src, 1))) |
dfac187e BS |
3095 | ep->offset -= INTVAL (XEXP (src, 1)); |
3096 | else | |
3097 | ep->can_eliminate = 0; | |
3098 | } | |
3099 | } | |
3100 | ||
bbbbb16a ILT |
3101 | elimination_effects (SET_DEST (x), VOIDmode); |
3102 | elimination_effects (SET_SRC (x), VOIDmode); | |
dfac187e BS |
3103 | return; |
3104 | ||
3105 | case MEM: | |
dfac187e BS |
3106 | /* Our only special processing is to pass the mode of the MEM to our |
3107 | recursive call. */ | |
3108 | elimination_effects (XEXP (x, 0), GET_MODE (x)); | |
3109 | return; | |
3110 | ||
3111 | default: | |
3112 | break; | |
3113 | } | |
3114 | ||
3115 | fmt = GET_RTX_FORMAT (code); | |
3116 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
3117 | { | |
3118 | if (*fmt == 'e') | |
3119 | elimination_effects (XEXP (x, i), mem_mode); | |
3120 | else if (*fmt == 'E') | |
3121 | for (j = 0; j < XVECLEN (x, i); j++) | |
3122 | elimination_effects (XVECEXP (x, i, j), mem_mode); | |
3123 | } | |
3124 | } | |
3125 | ||
3126 | /* Descend through rtx X and verify that no references to eliminable registers | |
3127 | remain. If any do remain, mark the involved register as not | |
3128 | eliminable. */ | |
1d813780 | 3129 | |
dfac187e | 3130 | static void |
0c20a65f | 3131 | check_eliminable_occurrences (rtx x) |
dfac187e BS |
3132 | { |
3133 | const char *fmt; | |
3134 | int i; | |
3135 | enum rtx_code code; | |
3136 | ||
3137 | if (x == 0) | |
3138 | return; | |
1d7254c5 | 3139 | |
dfac187e BS |
3140 | code = GET_CODE (x); |
3141 | ||
3142 | if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
3143 | { | |
3144 | struct elim_table *ep; | |
3145 | ||
3146 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
761fa0f7 | 3147 | if (ep->from_rtx == x) |
dfac187e BS |
3148 | ep->can_eliminate = 0; |
3149 | return; | |
3150 | } | |
1d7254c5 | 3151 | |
dfac187e BS |
3152 | fmt = GET_RTX_FORMAT (code); |
3153 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
3154 | { | |
3155 | if (*fmt == 'e') | |
3156 | check_eliminable_occurrences (XEXP (x, i)); | |
3157 | else if (*fmt == 'E') | |
3158 | { | |
3159 | int j; | |
3160 | for (j = 0; j < XVECLEN (x, i); j++) | |
3161 | check_eliminable_occurrences (XVECEXP (x, i, j)); | |
3162 | } | |
3163 | } | |
3164 | } | |
32131a9c RK |
3165 | \f |
3166 | /* Scan INSN and eliminate all eliminable registers in it. | |
3167 | ||
3168 | If REPLACE is nonzero, do the replacement destructively. Also | |
3169 | delete the insn as dead it if it is setting an eliminable register. | |
3170 | ||
3171 | If REPLACE is zero, do all our allocations in reload_obstack. | |
3172 | ||
3173 | If no eliminations were done and this insn doesn't require any elimination | |
3174 | processing (these are not identical conditions: it might be updating sp, | |
3175 | but not referencing fp; this needs to be seen during reload_as_needed so | |
3176 | that the offset between fp and sp can be taken into consideration), zero | |
3177 | is returned. Otherwise, 1 is returned. */ | |
3178 | ||
3179 | static int | |
0c20a65f | 3180 | eliminate_regs_in_insn (rtx insn, int replace) |
32131a9c | 3181 | { |
dfac187e | 3182 | int icode = recog_memoized (insn); |
32131a9c | 3183 | rtx old_body = PATTERN (insn); |
dfac187e | 3184 | int insn_is_asm = asm_noperands (old_body) >= 0; |
774672d2 | 3185 | rtx old_set = single_set (insn); |
32131a9c RK |
3186 | rtx new_body; |
3187 | int val = 0; | |
4977bab6 | 3188 | int i; |
dfac187e BS |
3189 | rtx substed_operand[MAX_RECOG_OPERANDS]; |
3190 | rtx orig_operand[MAX_RECOG_OPERANDS]; | |
32131a9c | 3191 | struct elim_table *ep; |
ab156144 | 3192 | rtx plus_src, plus_cst_src; |
32131a9c | 3193 | |
dfac187e BS |
3194 | if (! insn_is_asm && icode < 0) |
3195 | { | |
41374e13 NS |
3196 | gcc_assert (GET_CODE (PATTERN (insn)) == USE |
3197 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
3198 | || GET_CODE (PATTERN (insn)) == ADDR_VEC | |
3199 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
b5b8b0ac AO |
3200 | || GET_CODE (PATTERN (insn)) == ASM_INPUT |
3201 | || DEBUG_INSN_P (insn)); | |
41374e13 | 3202 | return 0; |
dfac187e BS |
3203 | } |
3204 | ||
f8cfc6aa | 3205 | if (old_set != 0 && REG_P (SET_DEST (old_set)) |
774672d2 | 3206 | && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) |
32131a9c RK |
3207 | { |
3208 | /* Check for setting an eliminable register. */ | |
3209 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
774672d2 | 3210 | if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) |
32131a9c | 3211 | { |
dd1eab0a RK |
3212 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
3213 | /* If this is setting the frame pointer register to the | |
3214 | hardware frame pointer register and this is an elimination | |
3215 | that will be done (tested above), this insn is really | |
3216 | adjusting the frame pointer downward to compensate for | |
3217 | the adjustment done before a nonlocal goto. */ | |
3218 | if (ep->from == FRAME_POINTER_REGNUM | |
3219 | && ep->to == HARD_FRAME_POINTER_REGNUM) | |
3220 | { | |
75eefe3f UW |
3221 | rtx base = SET_SRC (old_set); |
3222 | rtx base_insn = insn; | |
b19ee4bd | 3223 | HOST_WIDE_INT offset = 0; |
75eefe3f UW |
3224 | |
3225 | while (base != ep->to_rtx) | |
8026ebba | 3226 | { |
75eefe3f UW |
3227 | rtx prev_insn, prev_set; |
3228 | ||
3229 | if (GET_CODE (base) == PLUS | |
481683e1 | 3230 | && CONST_INT_P (XEXP (base, 1))) |
75eefe3f UW |
3231 | { |
3232 | offset += INTVAL (XEXP (base, 1)); | |
3233 | base = XEXP (base, 0); | |
3234 | } | |
3235 | else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0 | |
3236 | && (prev_set = single_set (prev_insn)) != 0 | |
3237 | && rtx_equal_p (SET_DEST (prev_set), base)) | |
3238 | { | |
3239 | base = SET_SRC (prev_set); | |
3240 | base_insn = prev_insn; | |
3241 | } | |
3242 | else | |
3243 | break; | |
8026ebba | 3244 | } |
dd1eab0a | 3245 | |
75eefe3f | 3246 | if (base == ep->to_rtx) |
dd1eab0a | 3247 | { |
c77fbfbe GK |
3248 | rtx src |
3249 | = plus_constant (ep->to_rtx, offset - ep->offset); | |
3250 | ||
3251 | new_body = old_body; | |
3252 | if (! replace) | |
3253 | { | |
3254 | new_body = copy_insn (old_body); | |
3255 | if (REG_NOTES (insn)) | |
3256 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3257 | } | |
3258 | PATTERN (insn) = new_body; | |
3259 | old_set = single_set (insn); | |
3260 | ||
3261 | /* First see if this insn remains valid when we | |
3262 | make the change. If not, keep the INSN_CODE | |
3263 | the same and let reload fit it up. */ | |
3264 | validate_change (insn, &SET_SRC (old_set), src, 1); | |
3265 | validate_change (insn, &SET_DEST (old_set), | |
3266 | ep->to_rtx, 1); | |
3267 | if (! apply_change_group ()) | |
dd1eab0a | 3268 | { |
c77fbfbe GK |
3269 | SET_SRC (old_set) = src; |
3270 | SET_DEST (old_set) = ep->to_rtx; | |
dd1eab0a RK |
3271 | } |
3272 | ||
3273 | val = 1; | |
3274 | goto done; | |
3275 | } | |
3276 | } | |
3277 | #endif | |
3278 | ||
32131a9c RK |
3279 | /* In this case this insn isn't serving a useful purpose. We |
3280 | will delete it in reload_as_needed once we know that this | |
3281 | elimination is, in fact, being done. | |
3282 | ||
abc95ed3 | 3283 | If REPLACE isn't set, we can't delete this insn, but needn't |
32131a9c RK |
3284 | process it since it won't be used unless something changes. */ |
3285 | if (replace) | |
8a34409d | 3286 | { |
1d7254c5 | 3287 | delete_dead_insn (insn); |
8a34409d RH |
3288 | return 1; |
3289 | } | |
32131a9c RK |
3290 | val = 1; |
3291 | goto done; | |
3292 | } | |
aa5524a9 | 3293 | } |
32131a9c | 3294 | |
aa5524a9 | 3295 | /* We allow one special case which happens to work on all machines we |
ace3ffcd KH |
3296 | currently support: a single set with the source or a REG_EQUAL |
3297 | note being a PLUS of an eliminable register and a constant. */ | |
ab156144 | 3298 | plus_src = plus_cst_src = 0; |
f8cfc6aa | 3299 | if (old_set && REG_P (SET_DEST (old_set))) |
aa5524a9 | 3300 | { |
ab156144 | 3301 | if (GET_CODE (SET_SRC (old_set)) == PLUS) |
ace3ffcd | 3302 | plus_src = SET_SRC (old_set); |
7efd40b5 | 3303 | /* First see if the source is of the form (plus (...) CST). */ |
ab156144 | 3304 | if (plus_src |
481683e1 | 3305 | && CONST_INT_P (XEXP (plus_src, 1))) |
ab156144 RH |
3306 | plus_cst_src = plus_src; |
3307 | else if (REG_P (SET_SRC (old_set)) | |
3308 | || plus_src) | |
ace3ffcd KH |
3309 | { |
3310 | /* Otherwise, see if we have a REG_EQUAL note of the form | |
7efd40b5 | 3311 | (plus (...) CST). */ |
ace3ffcd KH |
3312 | rtx links; |
3313 | for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) | |
3314 | { | |
7c11b28c BS |
3315 | if ((REG_NOTE_KIND (links) == REG_EQUAL |
3316 | || REG_NOTE_KIND (links) == REG_EQUIV) | |
ace3ffcd | 3317 | && GET_CODE (XEXP (links, 0)) == PLUS |
481683e1 | 3318 | && CONST_INT_P (XEXP (XEXP (links, 0), 1))) |
ace3ffcd | 3319 | { |
ab156144 | 3320 | plus_cst_src = XEXP (links, 0); |
ace3ffcd KH |
3321 | break; |
3322 | } | |
3323 | } | |
3324 | } | |
7efd40b5 UW |
3325 | |
3326 | /* Check that the first operand of the PLUS is a hard reg or | |
3327 | the lowpart subreg of one. */ | |
3328 | if (plus_cst_src) | |
3329 | { | |
3330 | rtx reg = XEXP (plus_cst_src, 0); | |
3331 | if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg)) | |
3332 | reg = SUBREG_REG (reg); | |
3333 | ||
3334 | if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) | |
3335 | plus_cst_src = 0; | |
3336 | } | |
ace3ffcd | 3337 | } |
ab156144 | 3338 | if (plus_cst_src) |
ace3ffcd | 3339 | { |
ab156144 RH |
3340 | rtx reg = XEXP (plus_cst_src, 0); |
3341 | HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1)); | |
32131a9c | 3342 | |
7efd40b5 UW |
3343 | if (GET_CODE (reg) == SUBREG) |
3344 | reg = SUBREG_REG (reg); | |
3345 | ||
aa5524a9 BS |
3346 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3347 | if (ep->from_rtx == reg && ep->can_eliminate) | |
3348 | { | |
7efd40b5 | 3349 | rtx to_rtx = ep->to_rtx; |
aa5524a9 | 3350 | offset += ep->offset; |
231a1e52 | 3351 | offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src)); |
32131a9c | 3352 | |
7efd40b5 UW |
3353 | if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG) |
3354 | to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)), | |
3355 | to_rtx); | |
8c1249f9 PB |
3356 | /* If we have a nonzero offset, and the source is already |
3357 | a simple REG, the following transformation would | |
3358 | increase the cost of the insn by replacing a simple REG | |
3359 | with (plus (reg sp) CST). So try only when we already | |
3360 | had a PLUS before. */ | |
551d6929 | 3361 | if (offset == 0 || plus_src) |
8c1249f9 | 3362 | { |
551d6929 UW |
3363 | rtx new_src = plus_constant (to_rtx, offset); |
3364 | ||
8c1249f9 PB |
3365 | new_body = old_body; |
3366 | if (! replace) | |
3367 | { | |
3368 | new_body = copy_insn (old_body); | |
3369 | if (REG_NOTES (insn)) | |
3370 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3371 | } | |
3372 | PATTERN (insn) = new_body; | |
3373 | old_set = single_set (insn); | |
3374 | ||
551d6929 UW |
3375 | /* First see if this insn remains valid when we make the |
3376 | change. If not, try to replace the whole pattern with | |
3377 | a simple set (this may help if the original insn was a | |
3378 | PARALLEL that was only recognized as single_set due to | |
3379 | REG_UNUSED notes). If this isn't valid either, keep | |
3380 | the INSN_CODE the same and let reload fix it up. */ | |
3381 | if (!validate_change (insn, &SET_SRC (old_set), new_src, 0)) | |
3382 | { | |
3383 | rtx new_pat = gen_rtx_SET (VOIDmode, | |
3384 | SET_DEST (old_set), new_src); | |
3385 | ||
3386 | if (!validate_change (insn, &PATTERN (insn), new_pat, 0)) | |
3387 | SET_SRC (old_set) = new_src; | |
3388 | } | |
8c1249f9 | 3389 | } |
ace3ffcd KH |
3390 | else |
3391 | break; | |
3392 | ||
aa5524a9 BS |
3393 | val = 1; |
3394 | /* This can't have an effect on elimination offsets, so skip right | |
3395 | to the end. */ | |
3396 | goto done; | |
3397 | } | |
32131a9c RK |
3398 | } |
3399 | ||
dfac187e | 3400 | /* Determine the effects of this insn on elimination offsets. */ |
bbbbb16a | 3401 | elimination_effects (old_body, VOIDmode); |
dfac187e BS |
3402 | |
3403 | /* Eliminate all eliminable registers occurring in operands that | |
3404 | can be handled by reload. */ | |
3405 | extract_insn (insn); | |
dfac187e BS |
3406 | for (i = 0; i < recog_data.n_operands; i++) |
3407 | { | |
3408 | orig_operand[i] = recog_data.operand[i]; | |
3409 | substed_operand[i] = recog_data.operand[i]; | |
3410 | ||
3411 | /* For an asm statement, every operand is eliminable. */ | |
3412 | if (insn_is_asm || insn_data[icode].operand[i].eliminable) | |
3413 | { | |
ab156144 RH |
3414 | bool is_set_src, in_plus; |
3415 | ||
dfac187e BS |
3416 | /* Check for setting a register that we know about. */ |
3417 | if (recog_data.operand_type[i] != OP_IN | |
f8cfc6aa | 3418 | && REG_P (orig_operand[i])) |
dfac187e BS |
3419 | { |
3420 | /* If we are assigning to a register that can be eliminated, it | |
3421 | must be as part of a PARALLEL, since the code above handles | |
3422 | single SETs. We must indicate that we can no longer | |
3423 | eliminate this reg. */ | |
3424 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
3425 | ep++) | |
761fa0f7 | 3426 | if (ep->from_rtx == orig_operand[i]) |
dfac187e BS |
3427 | ep->can_eliminate = 0; |
3428 | } | |
3429 | ||
ab156144 RH |
3430 | /* Companion to the above plus substitution, we can allow |
3431 | invariants as the source of a plain move. */ | |
3432 | is_set_src = false; | |
3433 | if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set)) | |
3434 | is_set_src = true; | |
3435 | in_plus = false; | |
3436 | if (plus_src | |
3437 | && (recog_data.operand_loc[i] == &XEXP (plus_src, 0) | |
3438 | || recog_data.operand_loc[i] == &XEXP (plus_src, 1))) | |
3439 | in_plus = true; | |
3440 | ||
3441 | substed_operand[i] | |
bbbbb16a | 3442 | = eliminate_regs_1 (recog_data.operand[i], VOIDmode, |
ab156144 RH |
3443 | replace ? insn : NULL_RTX, |
3444 | is_set_src || in_plus); | |
dfac187e | 3445 | if (substed_operand[i] != orig_operand[i]) |
4977bab6 | 3446 | val = 1; |
dfac187e BS |
3447 | /* Terminate the search in check_eliminable_occurrences at |
3448 | this point. */ | |
3449 | *recog_data.operand_loc[i] = 0; | |
3450 | ||
c41c1387 RS |
3451 | /* If an output operand changed from a REG to a MEM and INSN is an |
3452 | insn, write a CLOBBER insn. */ | |
dfac187e | 3453 | if (recog_data.operand_type[i] != OP_IN |
f8cfc6aa | 3454 | && REG_P (orig_operand[i]) |
3c0cb5de | 3455 | && MEM_P (substed_operand[i]) |
dfac187e | 3456 | && replace) |
c41c1387 | 3457 | emit_insn_after (gen_clobber (orig_operand[i]), insn); |
dfac187e BS |
3458 | } |
3459 | } | |
3460 | ||
3461 | for (i = 0; i < recog_data.n_dups; i++) | |
3462 | *recog_data.dup_loc[i] | |
1d7254c5 | 3463 | = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; |
dfac187e BS |
3464 | |
3465 | /* If any eliminable remain, they aren't eliminable anymore. */ | |
3466 | check_eliminable_occurrences (old_body); | |
32131a9c | 3467 | |
dfac187e BS |
3468 | /* Substitute the operands; the new values are in the substed_operand |
3469 | array. */ | |
3470 | for (i = 0; i < recog_data.n_operands; i++) | |
3471 | *recog_data.operand_loc[i] = substed_operand[i]; | |
3472 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3473 | *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3474 | |
dfac187e | 3475 | /* If we are replacing a body that was a (set X (plus Y Z)), try to |
32131a9c RK |
3476 | re-recognize the insn. We do this in case we had a simple addition |
3477 | but now can do this as a load-address. This saves an insn in this | |
dfac187e BS |
3478 | common case. |
3479 | If re-recognition fails, the old insn code number will still be used, | |
3480 | and some register operands may have changed into PLUS expressions. | |
3481 | These will be handled by find_reloads by loading them into a register | |
1d7254c5 | 3482 | again. */ |
32131a9c | 3483 | |
dfac187e | 3484 | if (val) |
32131a9c | 3485 | { |
7c791b13 RK |
3486 | /* If we aren't replacing things permanently and we changed something, |
3487 | make another copy to ensure that all the RTL is new. Otherwise | |
3488 | things can go wrong if find_reload swaps commutative operands | |
0f41302f | 3489 | and one is inside RTL that has been copied while the other is not. */ |
dfac187e BS |
3490 | new_body = old_body; |
3491 | if (! replace) | |
1b3b5765 BS |
3492 | { |
3493 | new_body = copy_insn (old_body); | |
3494 | if (REG_NOTES (insn)) | |
3495 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3496 | } | |
dfac187e | 3497 | PATTERN (insn) = new_body; |
7c791b13 | 3498 | |
774672d2 RK |
3499 | /* If we had a move insn but now we don't, rerecognize it. This will |
3500 | cause spurious re-recognition if the old move had a PARALLEL since | |
3501 | the new one still will, but we can't call single_set without | |
3502 | having put NEW_BODY into the insn and the re-recognition won't | |
3503 | hurt in this rare case. */ | |
dfac187e BS |
3504 | /* ??? Why this huge if statement - why don't we just rerecognize the |
3505 | thing always? */ | |
3506 | if (! insn_is_asm | |
3507 | && old_set != 0 | |
f8cfc6aa | 3508 | && ((REG_P (SET_SRC (old_set)) |
774672d2 | 3509 | && (GET_CODE (new_body) != SET |
f8cfc6aa | 3510 | || !REG_P (SET_SRC (new_body)))) |
774672d2 | 3511 | /* If this was a load from or store to memory, compare |
1ccbefce RH |
3512 | the MEM in recog_data.operand to the one in the insn. |
3513 | If they are not equal, then rerecognize the insn. */ | |
774672d2 | 3514 | || (old_set != 0 |
3c0cb5de | 3515 | && ((MEM_P (SET_SRC (old_set)) |
1ccbefce | 3516 | && SET_SRC (old_set) != recog_data.operand[1]) |
3c0cb5de | 3517 | || (MEM_P (SET_DEST (old_set)) |
1ccbefce | 3518 | && SET_DEST (old_set) != recog_data.operand[0]))) |
774672d2 RK |
3519 | /* If this was an add insn before, rerecognize. */ |
3520 | || GET_CODE (SET_SRC (old_set)) == PLUS)) | |
4a5d0fb5 | 3521 | { |
dfac187e | 3522 | int new_icode = recog (PATTERN (insn), insn, 0); |
a5ee7cba AM |
3523 | if (new_icode >= 0) |
3524 | INSN_CODE (insn) = new_icode; | |
4a5d0fb5 | 3525 | } |
dfac187e | 3526 | } |
32131a9c | 3527 | |
dfac187e BS |
3528 | /* Restore the old body. If there were any changes to it, we made a copy |
3529 | of it while the changes were still in place, so we'll correctly return | |
3530 | a modified insn below. */ | |
3531 | if (! replace) | |
3532 | { | |
3533 | /* Restore the old body. */ | |
3534 | for (i = 0; i < recog_data.n_operands; i++) | |
3535 | *recog_data.operand_loc[i] = orig_operand[i]; | |
3536 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3537 | *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3538 | } |
a8fdc208 | 3539 | |
dfac187e BS |
3540 | /* Update all elimination pairs to reflect the status after the current |
3541 | insn. The changes we make were determined by the earlier call to | |
3542 | elimination_effects. | |
a8efe40d | 3543 | |
423adbb9 | 3544 | We also detect cases where register elimination cannot be done, |
32131a9c RK |
3545 | namely, if a register would be both changed and referenced outside a MEM |
3546 | in the resulting insn since such an insn is often undefined and, even if | |
3547 | not, we cannot know what meaning will be given to it. Note that it is | |
3548 | valid to have a register used in an address in an insn that changes it | |
3549 | (presumably with a pre- or post-increment or decrement). | |
3550 | ||
3551 | If anything changes, return nonzero. */ | |
3552 | ||
32131a9c RK |
3553 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3554 | { | |
3555 | if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | |
3556 | ep->can_eliminate = 0; | |
3557 | ||
3558 | ep->ref_outside_mem = 0; | |
3559 | ||
3560 | if (ep->previous_offset != ep->offset) | |
3561 | val = 1; | |
32131a9c RK |
3562 | } |
3563 | ||
3564 | done: | |
9faa82d8 | 3565 | /* If we changed something, perform elimination in REG_NOTES. This is |
05b4c365 RK |
3566 | needed even when REPLACE is zero because a REG_DEAD note might refer |
3567 | to a register that we eliminate and could cause a different number | |
3568 | of spill registers to be needed in the final reload pass than in | |
3569 | the pre-passes. */ | |
20748cab | 3570 | if (val && REG_NOTES (insn) != 0) |
ab156144 | 3571 | REG_NOTES (insn) |
bbbbb16a | 3572 | = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true); |
05b4c365 | 3573 | |
32131a9c RK |
3574 | return val; |
3575 | } | |
3576 | ||
cb2afeb3 R |
3577 | /* Loop through all elimination pairs. |
3578 | Recalculate the number not at initial offset. | |
3579 | ||
3580 | Compute the maximum offset (minimum offset if the stack does not | |
3581 | grow downward) for each elimination pair. */ | |
3582 | ||
3583 | static void | |
0c20a65f | 3584 | update_eliminable_offsets (void) |
cb2afeb3 R |
3585 | { |
3586 | struct elim_table *ep; | |
3587 | ||
3588 | num_not_at_initial_offset = 0; | |
3589 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3590 | { | |
3591 | ep->previous_offset = ep->offset; | |
3592 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3593 | num_not_at_initial_offset++; | |
cb2afeb3 R |
3594 | } |
3595 | } | |
3596 | ||
32131a9c RK |
3597 | /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register |
3598 | replacement we currently believe is valid, mark it as not eliminable if X | |
3599 | modifies DEST in any way other than by adding a constant integer to it. | |
3600 | ||
3601 | If DEST is the frame pointer, we do nothing because we assume that | |
3ec2ea3e DE |
3602 | all assignments to the hard frame pointer are nonlocal gotos and are being |
3603 | done at a time when they are valid and do not disturb anything else. | |
32131a9c | 3604 | Some machines want to eliminate a fake argument pointer with either the |
3ec2ea3e DE |
3605 | frame or stack pointer. Assignments to the hard frame pointer must not |
3606 | prevent this elimination. | |
32131a9c RK |
3607 | |
3608 | Called via note_stores from reload before starting its passes to scan | |
3609 | the insns of the function. */ | |
3610 | ||
3611 | static void | |
7bc980e1 | 3612 | mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) |
32131a9c | 3613 | { |
b3694847 | 3614 | unsigned int i; |
32131a9c RK |
3615 | |
3616 | /* A SUBREG of a hard register here is just changing its mode. We should | |
3617 | not see a SUBREG of an eliminable hard register, but check just in | |
3618 | case. */ | |
3619 | if (GET_CODE (dest) == SUBREG) | |
3620 | dest = SUBREG_REG (dest); | |
3621 | ||
3ec2ea3e | 3622 | if (dest == hard_frame_pointer_rtx) |
32131a9c RK |
3623 | return; |
3624 | ||
3625 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3626 | if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx | |
3627 | && (GET_CODE (x) != SET | |
3628 | || GET_CODE (SET_SRC (x)) != PLUS | |
3629 | || XEXP (SET_SRC (x), 0) != dest | |
481683e1 | 3630 | || !CONST_INT_P (XEXP (SET_SRC (x), 1)))) |
32131a9c RK |
3631 | { |
3632 | reg_eliminate[i].can_eliminate_previous | |
3633 | = reg_eliminate[i].can_eliminate = 0; | |
3634 | num_eliminable--; | |
3635 | } | |
3636 | } | |
09dd1133 | 3637 | |
c47f5ea5 BS |
3638 | /* Verify that the initial elimination offsets did not change since the |
3639 | last call to set_initial_elim_offsets. This is used to catch cases | |
3640 | where something illegal happened during reload_as_needed that could | |
3641 | cause incorrect code to be generated if we did not check for it. */ | |
c8d8ed65 | 3642 | |
9f938de1 | 3643 | static bool |
0c20a65f | 3644 | verify_initial_elim_offsets (void) |
c47f5ea5 | 3645 | { |
b19ee4bd | 3646 | HOST_WIDE_INT t; |
c47f5ea5 | 3647 | |
9f938de1 UW |
3648 | if (!num_eliminable) |
3649 | return true; | |
3650 | ||
c47f5ea5 | 3651 | #ifdef ELIMINABLE_REGS |
67730e23 ILT |
3652 | { |
3653 | struct elim_table *ep; | |
3654 | ||
3655 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3656 | { | |
3657 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); | |
3658 | if (t != ep->initial_offset) | |
3659 | return false; | |
3660 | } | |
3661 | } | |
c47f5ea5 BS |
3662 | #else |
3663 | INITIAL_FRAME_POINTER_OFFSET (t); | |
9f938de1 UW |
3664 | if (t != reg_eliminate[0].initial_offset) |
3665 | return false; | |
05d10675 | 3666 | #endif |
9f938de1 UW |
3667 | |
3668 | return true; | |
c47f5ea5 BS |
3669 | } |
3670 | ||
09dd1133 | 3671 | /* Reset all offsets on eliminable registers to their initial values. */ |
1d813780 | 3672 | |
09dd1133 | 3673 | static void |
0c20a65f | 3674 | set_initial_elim_offsets (void) |
09dd1133 | 3675 | { |
1f3b1e1a | 3676 | struct elim_table *ep = reg_eliminate; |
09dd1133 BS |
3677 | |
3678 | #ifdef ELIMINABLE_REGS | |
1f3b1e1a | 3679 | for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
09dd1133 BS |
3680 | { |
3681 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); | |
1f3b1e1a | 3682 | ep->previous_offset = ep->offset = ep->initial_offset; |
09dd1133 BS |
3683 | } |
3684 | #else | |
1f3b1e1a JL |
3685 | INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); |
3686 | ep->previous_offset = ep->offset = ep->initial_offset; | |
09dd1133 BS |
3687 | #endif |
3688 | ||
3689 | num_not_at_initial_offset = 0; | |
1f3b1e1a | 3690 | } |
09dd1133 | 3691 | |
58767f00 RH |
3692 | /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */ |
3693 | ||
3694 | static void | |
3695 | set_initial_eh_label_offset (rtx label) | |
3696 | { | |
3697 | set_label_offsets (label, NULL_RTX, 1); | |
3698 | } | |
3699 | ||
1f3b1e1a JL |
3700 | /* Initialize the known label offsets. |
3701 | Set a known offset for each forced label to be at the initial offset | |
3702 | of each elimination. We do this because we assume that all | |
3703 | computed jumps occur from a location where each elimination is | |
3704 | at its initial offset. | |
3705 | For all other labels, show that we don't know the offsets. */ | |
09dd1133 | 3706 | |
1f3b1e1a | 3707 | static void |
0c20a65f | 3708 | set_initial_label_offsets (void) |
1f3b1e1a JL |
3709 | { |
3710 | rtx x; | |
4cc0fdd2 | 3711 | memset (offsets_known_at, 0, num_labels); |
09dd1133 BS |
3712 | |
3713 | for (x = forced_labels; x; x = XEXP (x, 1)) | |
3714 | if (XEXP (x, 0)) | |
3715 | set_label_offsets (XEXP (x, 0), NULL_RTX, 1); | |
58767f00 RH |
3716 | |
3717 | for_each_eh_label (set_initial_eh_label_offset); | |
09dd1133 BS |
3718 | } |
3719 | ||
1f3b1e1a JL |
3720 | /* Set all elimination offsets to the known values for the code label given |
3721 | by INSN. */ | |
1d813780 | 3722 | |
1f3b1e1a | 3723 | static void |
0c20a65f | 3724 | set_offsets_for_label (rtx insn) |
1f3b1e1a | 3725 | { |
973838fd | 3726 | unsigned int i; |
1f3b1e1a JL |
3727 | int label_nr = CODE_LABEL_NUMBER (insn); |
3728 | struct elim_table *ep; | |
3729 | ||
3730 | num_not_at_initial_offset = 0; | |
3731 | for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) | |
3732 | { | |
4cc0fdd2 JDA |
3733 | ep->offset = ep->previous_offset |
3734 | = offsets_at[label_nr - first_label_num][i]; | |
1f3b1e1a JL |
3735 | if (ep->can_eliminate && ep->offset != ep->initial_offset) |
3736 | num_not_at_initial_offset++; | |
3737 | } | |
3738 | } | |
3739 | ||
09dd1133 | 3740 | /* See if anything that happened changes which eliminations are valid. |
981f6289 | 3741 | For example, on the SPARC, whether or not the frame pointer can |
09dd1133 BS |
3742 | be eliminated can depend on what registers have been used. We need |
3743 | not check some conditions again (such as flag_omit_frame_pointer) | |
3744 | since they can't have changed. */ | |
3745 | ||
3746 | static void | |
0c20a65f | 3747 | update_eliminables (HARD_REG_SET *pset) |
09dd1133 | 3748 | { |
09dd1133 | 3749 | int previous_frame_pointer_needed = frame_pointer_needed; |
09dd1133 BS |
3750 | struct elim_table *ep; |
3751 | ||
3752 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
b52b1749 AS |
3753 | if ((ep->from == HARD_FRAME_POINTER_REGNUM |
3754 | && targetm.frame_pointer_required ()) | |
09dd1133 | 3755 | #ifdef ELIMINABLE_REGS |
7b5cbb57 | 3756 | || ! targetm.can_eliminate (ep->from, ep->to) |
09dd1133 BS |
3757 | #endif |
3758 | ) | |
3759 | ep->can_eliminate = 0; | |
3760 | ||
3761 | /* Look for the case where we have discovered that we can't replace | |
3762 | register A with register B and that means that we will now be | |
3763 | trying to replace register A with register C. This means we can | |
3764 | no longer replace register C with register B and we need to disable | |
3765 | such an elimination, if it exists. This occurs often with A == ap, | |
3766 | B == sp, and C == fp. */ | |
3767 | ||
3768 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3769 | { | |
3770 | struct elim_table *op; | |
b3694847 | 3771 | int new_to = -1; |
09dd1133 BS |
3772 | |
3773 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3774 | { | |
3775 | /* Find the current elimination for ep->from, if there is a | |
3776 | new one. */ | |
3777 | for (op = reg_eliminate; | |
3778 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3779 | if (op->from == ep->from && op->can_eliminate) | |
3780 | { | |
3781 | new_to = op->to; | |
3782 | break; | |
3783 | } | |
3784 | ||
3785 | /* See if there is an elimination of NEW_TO -> EP->TO. If so, | |
3786 | disable it. */ | |
3787 | for (op = reg_eliminate; | |
3788 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3789 | if (op->from == new_to && op->to == ep->to) | |
3790 | op->can_eliminate = 0; | |
3791 | } | |
3792 | } | |
3793 | ||
3794 | /* See if any registers that we thought we could eliminate the previous | |
3795 | time are no longer eliminable. If so, something has changed and we | |
3796 | must spill the register. Also, recompute the number of eliminable | |
3797 | registers and see if the frame pointer is needed; it is if there is | |
3798 | no elimination of the frame pointer that we can perform. */ | |
3799 | ||
3800 | frame_pointer_needed = 1; | |
3801 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3802 | { | |
2e3f842f L |
3803 | if (ep->can_eliminate |
3804 | && ep->from == FRAME_POINTER_REGNUM | |
3805 | && ep->to != HARD_FRAME_POINTER_REGNUM | |
3806 | && (! SUPPORTS_STACK_ALIGNMENT | |
3807 | || ! crtl->stack_realign_needed)) | |
09dd1133 BS |
3808 | frame_pointer_needed = 0; |
3809 | ||
3810 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3811 | { | |
3812 | ep->can_eliminate_previous = 0; | |
3813 | SET_HARD_REG_BIT (*pset, ep->from); | |
3814 | num_eliminable--; | |
3815 | } | |
3816 | } | |
3817 | ||
09dd1133 BS |
3818 | /* If we didn't need a frame pointer last time, but we do now, spill |
3819 | the hard frame pointer. */ | |
3820 | if (frame_pointer_needed && ! previous_frame_pointer_needed) | |
3821 | SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); | |
09dd1133 BS |
3822 | } |
3823 | ||
8c74fb06 RS |
3824 | /* Return true if X is used as the target register of an elimination. */ |
3825 | ||
3826 | bool | |
3827 | elimination_target_reg_p (rtx x) | |
3828 | { | |
3829 | struct elim_table *ep; | |
3830 | ||
3831 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3832 | if (ep->to_rtx == x && ep->can_eliminate) | |
3833 | return true; | |
3834 | ||
3835 | return false; | |
3836 | } | |
3837 | ||
38aa4d08 JY |
3838 | /* Initialize the table of registers to eliminate. |
3839 | Pre-condition: global flag frame_pointer_needed has been set before | |
3840 | calling this function. */ | |
1d813780 | 3841 | |
09dd1133 | 3842 | static void |
0c20a65f | 3843 | init_elim_table (void) |
09dd1133 BS |
3844 | { |
3845 | struct elim_table *ep; | |
590cf94d | 3846 | #ifdef ELIMINABLE_REGS |
0b5826ac | 3847 | const struct elim_table_1 *ep1; |
590cf94d | 3848 | #endif |
09dd1133 | 3849 | |
590cf94d | 3850 | if (!reg_eliminate) |
1634b18f | 3851 | reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS); |
05d10675 | 3852 | |
09dd1133 BS |
3853 | num_eliminable = 0; |
3854 | ||
3855 | #ifdef ELIMINABLE_REGS | |
590cf94d KG |
3856 | for (ep = reg_eliminate, ep1 = reg_eliminate_1; |
3857 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) | |
09dd1133 | 3858 | { |
590cf94d KG |
3859 | ep->from = ep1->from; |
3860 | ep->to = ep1->to; | |
09dd1133 | 3861 | ep->can_eliminate = ep->can_eliminate_previous |
7b5cbb57 | 3862 | = (targetm.can_eliminate (ep->from, ep->to) |
2e3f842f L |
3863 | && ! (ep->to == STACK_POINTER_REGNUM |
3864 | && frame_pointer_needed | |
3865 | && (! SUPPORTS_STACK_ALIGNMENT | |
3866 | || ! stack_realign_fp))); | |
09dd1133 BS |
3867 | } |
3868 | #else | |
590cf94d KG |
3869 | reg_eliminate[0].from = reg_eliminate_1[0].from; |
3870 | reg_eliminate[0].to = reg_eliminate_1[0].to; | |
09dd1133 BS |
3871 | reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous |
3872 | = ! frame_pointer_needed; | |
3873 | #endif | |
3874 | ||
3875 | /* Count the number of eliminable registers and build the FROM and TO | |
2fb00d7f | 3876 | REG rtx's. Note that code in gen_rtx_REG will cause, e.g., |
f84d109f | 3877 | gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. |
09dd1133 BS |
3878 | We depend on this. */ |
3879 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3880 | { | |
3881 | num_eliminable += ep->can_eliminate; | |
3882 | ep->from_rtx = gen_rtx_REG (Pmode, ep->from); | |
3883 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | |
3884 | } | |
3885 | } | |
32131a9c RK |
3886 | \f |
3887 | /* Kick all pseudos out of hard register REGNO. | |
32131a9c RK |
3888 | |
3889 | If CANT_ELIMINATE is nonzero, it means that we are doing this spill | |
3890 | because we found we can't eliminate some register. In the case, no pseudos | |
3891 | are allowed to be in the register, even if they are only in a block that | |
3892 | doesn't require spill registers, unlike the case when we are spilling this | |
3893 | hard reg to produce another spill register. | |
3894 | ||
3895 | Return nonzero if any pseudos needed to be kicked out. */ | |
3896 | ||
03acd8f8 | 3897 | static void |
0c20a65f | 3898 | spill_hard_reg (unsigned int regno, int cant_eliminate) |
32131a9c | 3899 | { |
b3694847 | 3900 | int i; |
32131a9c | 3901 | |
9ff3516a | 3902 | if (cant_eliminate) |
03acd8f8 BS |
3903 | { |
3904 | SET_HARD_REG_BIT (bad_spill_regs_global, regno); | |
6fb5fa3c | 3905 | df_set_regs_ever_live (regno, true); |
03acd8f8 | 3906 | } |
9ff3516a | 3907 | |
32131a9c RK |
3908 | /* Spill every pseudo reg that was allocated to this reg |
3909 | or to something that overlaps this reg. */ | |
3910 | ||
3911 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3912 | if (reg_renumber[i] >= 0 | |
770ae6cc | 3913 | && (unsigned int) reg_renumber[i] <= regno |
09e18274 | 3914 | && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno) |
f5d8c9f4 | 3915 | SET_REGNO_REG_SET (&spilled_pseudos, i); |
03acd8f8 | 3916 | } |
32131a9c | 3917 | |
03acd8f8 BS |
3918 | /* After find_reload_regs has been run for all insn that need reloads, |
3919 | and/or spill_hard_regs was called, this function is used to actually | |
3920 | spill pseudo registers and try to reallocate them. It also sets up the | |
3921 | spill_regs array for use by choose_reload_regs. */ | |
a8fdc208 | 3922 | |
03acd8f8 | 3923 | static int |
0c20a65f | 3924 | finish_spills (int global) |
03acd8f8 BS |
3925 | { |
3926 | struct insn_chain *chain; | |
3927 | int something_changed = 0; | |
3cd8c58a | 3928 | unsigned i; |
a2041967 | 3929 | reg_set_iterator rsi; |
03acd8f8 BS |
3930 | |
3931 | /* Build the spill_regs array for the function. */ | |
3932 | /* If there are some registers still to eliminate and one of the spill regs | |
3933 | wasn't ever used before, additional stack space may have to be | |
3934 | allocated to store this register. Thus, we may have changed the offset | |
3935 | between the stack and frame pointers, so mark that something has changed. | |
32131a9c | 3936 | |
03acd8f8 BS |
3937 | One might think that we need only set VAL to 1 if this is a call-used |
3938 | register. However, the set of registers that must be saved by the | |
3939 | prologue is not identical to the call-used set. For example, the | |
3940 | register used by the call insn for the return PC is a call-used register, | |
3941 | but must be saved by the prologue. */ | |
3942 | ||
3943 | n_spills = 0; | |
3944 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3945 | if (TEST_HARD_REG_BIT (used_spill_regs, i)) | |
3946 | { | |
3947 | spill_reg_order[i] = n_spills; | |
3948 | spill_regs[n_spills++] = i; | |
6fb5fa3c | 3949 | if (num_eliminable && ! df_regs_ever_live_p (i)) |
03acd8f8 | 3950 | something_changed = 1; |
6fb5fa3c | 3951 | df_set_regs_ever_live (i, true); |
03acd8f8 BS |
3952 | } |
3953 | else | |
3954 | spill_reg_order[i] = -1; | |
3955 | ||
a2041967 | 3956 | EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi) |
2af2dbdc | 3957 | if (! ira_conflicts_p || reg_renumber[i] >= 0) |
058e97ec VM |
3958 | { |
3959 | /* Record the current hard register the pseudo is allocated to | |
3960 | in pseudo_previous_regs so we avoid reallocating it to the | |
3961 | same hard reg in a later pass. */ | |
3962 | gcc_assert (reg_renumber[i] >= 0); | |
3963 | ||
3964 | SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); | |
3965 | /* Mark it as no longer having a hard register home. */ | |
3966 | reg_renumber[i] = -1; | |
2af2dbdc | 3967 | if (ira_conflicts_p) |
058e97ec VM |
3968 | /* Inform IRA about the change. */ |
3969 | ira_mark_allocation_change (i); | |
3970 | /* We will need to scan everything again. */ | |
3971 | something_changed = 1; | |
3972 | } | |
7609e720 | 3973 | |
03acd8f8 | 3974 | /* Retry global register allocation if possible. */ |
2af2dbdc | 3975 | if (global && ira_conflicts_p) |
03acd8f8 | 3976 | { |
2af2dbdc VM |
3977 | unsigned int n; |
3978 | ||
703ad42b | 3979 | memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET)); |
03acd8f8 BS |
3980 | /* For every insn that needs reloads, set the registers used as spill |
3981 | regs in pseudo_forbidden_regs for every pseudo live across the | |
3982 | insn. */ | |
3983 | for (chain = insns_need_reload; chain; chain = chain->next_need_reload) | |
3984 | { | |
3985 | EXECUTE_IF_SET_IN_REG_SET | |
a2041967 KH |
3986 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi) |
3987 | { | |
00268eb3 KH |
3988 | IOR_HARD_REG_SET (pseudo_forbidden_regs[i], |
3989 | chain->used_spill_regs); | |
a2041967 | 3990 | } |
03acd8f8 | 3991 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
3992 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi) |
3993 | { | |
00268eb3 KH |
3994 | IOR_HARD_REG_SET (pseudo_forbidden_regs[i], |
3995 | chain->used_spill_regs); | |
a2041967 | 3996 | } |
03acd8f8 | 3997 | } |
7609e720 | 3998 | |
2af2dbdc VM |
3999 | /* Retry allocating the pseudos spilled in IRA and the |
4000 | reload. For each reg, merge the various reg sets that | |
4001 | indicate which hard regs can't be used, and call | |
4002 | ira_reassign_pseudos. */ | |
4003 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++) | |
4004 | if (reg_old_renumber[i] != reg_renumber[i]) | |
4005 | { | |
4006 | if (reg_renumber[i] < 0) | |
4007 | temp_pseudo_reg_arr[n++] = i; | |
4008 | else | |
4009 | CLEAR_REGNO_REG_SET (&spilled_pseudos, i); | |
4010 | } | |
4011 | if (ira_reassign_pseudos (temp_pseudo_reg_arr, n, | |
4012 | bad_spill_regs_global, | |
4013 | pseudo_forbidden_regs, pseudo_previous_regs, | |
4014 | &spilled_pseudos)) | |
4015 | something_changed = 1; | |
03acd8f8 | 4016 | } |
03acd8f8 BS |
4017 | /* Fix up the register information in the insn chain. |
4018 | This involves deleting those of the spilled pseudos which did not get | |
4019 | a new hard register home from the live_{before,after} sets. */ | |
7609e720 BS |
4020 | for (chain = reload_insn_chain; chain; chain = chain->next) |
4021 | { | |
03acd8f8 BS |
4022 | HARD_REG_SET used_by_pseudos; |
4023 | HARD_REG_SET used_by_pseudos2; | |
4024 | ||
2af2dbdc | 4025 | if (! ira_conflicts_p) |
058e97ec VM |
4026 | { |
4027 | /* Don't do it for IRA because IRA and the reload still can | |
4028 | assign hard registers to the spilled pseudos on next | |
4029 | reload iterations. */ | |
4030 | AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); | |
4031 | AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); | |
4032 | } | |
03acd8f8 BS |
4033 | /* Mark any unallocated hard regs as available for spills. That |
4034 | makes inheritance work somewhat better. */ | |
4035 | if (chain->need_reload) | |
4036 | { | |
239a0f5b BS |
4037 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); |
4038 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
03acd8f8 BS |
4039 | IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); |
4040 | ||
239a0f5b BS |
4041 | compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); |
4042 | compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); | |
058e97ec VM |
4043 | /* Value of chain->used_spill_regs from previous iteration |
4044 | may be not included in the value calculated here because | |
4045 | of possible removing caller-saves insns (see function | |
4046 | delete_caller_save_insns. */ | |
03acd8f8 BS |
4047 | COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); |
4048 | AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); | |
03acd8f8 | 4049 | } |
7609e720 | 4050 | } |
03acd8f8 | 4051 | |
058e97ec | 4052 | CLEAR_REG_SET (&changed_allocation_pseudos); |
03acd8f8 | 4053 | /* Let alter_reg modify the reg rtx's for the modified pseudos. */ |
3cd8c58a | 4054 | for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++) |
03acd8f8 BS |
4055 | { |
4056 | int regno = reg_renumber[i]; | |
4057 | if (reg_old_renumber[i] == regno) | |
4058 | continue; | |
05d10675 | 4059 | |
058e97ec VM |
4060 | SET_REGNO_REG_SET (&changed_allocation_pseudos, i); |
4061 | ||
4062 | alter_reg (i, reg_old_renumber[i], false); | |
03acd8f8 | 4063 | reg_old_renumber[i] = regno; |
c263766c | 4064 | if (dump_file) |
03acd8f8 BS |
4065 | { |
4066 | if (regno == -1) | |
c263766c | 4067 | fprintf (dump_file, " Register %d now on stack.\n\n", i); |
03acd8f8 | 4068 | else |
c263766c | 4069 | fprintf (dump_file, " Register %d now in %d.\n\n", |
03acd8f8 BS |
4070 | i, reg_renumber[i]); |
4071 | } | |
4072 | } | |
4073 | ||
4074 | return something_changed; | |
7609e720 | 4075 | } |
32131a9c | 4076 | \f |
d754127f | 4077 | /* Find all paradoxical subregs within X and update reg_max_ref_width. */ |
32131a9c RK |
4078 | |
4079 | static void | |
0c20a65f | 4080 | scan_paradoxical_subregs (rtx x) |
32131a9c | 4081 | { |
b3694847 SS |
4082 | int i; |
4083 | const char *fmt; | |
4084 | enum rtx_code code = GET_CODE (x); | |
32131a9c RK |
4085 | |
4086 | switch (code) | |
4087 | { | |
56f58d3a | 4088 | case REG: |
32131a9c RK |
4089 | case CONST_INT: |
4090 | case CONST: | |
4091 | case SYMBOL_REF: | |
4092 | case LABEL_REF: | |
4093 | case CONST_DOUBLE: | |
091a3ac7 | 4094 | case CONST_FIXED: |
69ef87e2 | 4095 | case CONST_VECTOR: /* shouldn't happen, but just in case. */ |
32131a9c RK |
4096 | case CC0: |
4097 | case PC: | |
32131a9c RK |
4098 | case USE: |
4099 | case CLOBBER: | |
4100 | return; | |
4101 | ||
4102 | case SUBREG: | |
f8cfc6aa | 4103 | if (REG_P (SUBREG_REG (x)) |
63a7a62b RS |
4104 | && (GET_MODE_SIZE (GET_MODE (x)) |
4105 | > reg_max_ref_width[REGNO (SUBREG_REG (x))])) | |
6fb5fa3c DB |
4106 | { |
4107 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
4108 | = GET_MODE_SIZE (GET_MODE (x)); | |
4109 | mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x)); | |
4110 | } | |
32131a9c | 4111 | return; |
05d10675 | 4112 | |
e9a25f70 JL |
4113 | default: |
4114 | break; | |
32131a9c RK |
4115 | } |
4116 | ||
4117 | fmt = GET_RTX_FORMAT (code); | |
4118 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4119 | { | |
4120 | if (fmt[i] == 'e') | |
4121 | scan_paradoxical_subregs (XEXP (x, i)); | |
4122 | else if (fmt[i] == 'E') | |
4123 | { | |
b3694847 | 4124 | int j; |
1d7254c5 | 4125 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
32131a9c RK |
4126 | scan_paradoxical_subregs (XVECEXP (x, i, j)); |
4127 | } | |
4128 | } | |
4129 | } | |
4130 | \f | |
be0c514c RH |
4131 | /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note, |
4132 | examine all of the reload insns between PREV and NEXT exclusive, and | |
4133 | annotate all that may trap. */ | |
4134 | ||
4135 | static void | |
4136 | fixup_eh_region_note (rtx insn, rtx prev, rtx next) | |
4137 | { | |
4138 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
be0c514c RH |
4139 | if (note == NULL) |
4140 | return; | |
1d65f45c | 4141 | if (!insn_could_throw_p (insn)) |
d3aa398e | 4142 | remove_note (insn, note); |
1d65f45c | 4143 | copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next); |
be0c514c RH |
4144 | } |
4145 | ||
32131a9c RK |
4146 | /* Reload pseudo-registers into hard regs around each insn as needed. |
4147 | Additional register load insns are output before the insn that needs it | |
4148 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
4149 | ||
4150 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
d08ea79f | 4151 | which registers are already available in reload registers. |
32131a9c RK |
4152 | We update these for the reloads that we perform, |
4153 | as the insns are scanned. */ | |
4154 | ||
4155 | static void | |
0c20a65f | 4156 | reload_as_needed (int live_known) |
32131a9c | 4157 | { |
7609e720 | 4158 | struct insn_chain *chain; |
553687c9 | 4159 | #if defined (AUTO_INC_DEC) |
b3694847 | 4160 | int i; |
973838fd | 4161 | #endif |
32131a9c | 4162 | rtx x; |
32131a9c | 4163 | |
703ad42b KG |
4164 | memset (spill_reg_rtx, 0, sizeof spill_reg_rtx); |
4165 | memset (spill_reg_store, 0, sizeof spill_reg_store); | |
5ed6ace5 | 4166 | reg_last_reload_reg = XCNEWVEC (rtx, max_regno); |
2c61f5f1 | 4167 | INIT_REG_SET (®_has_output_reload); |
e6e52be0 | 4168 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
e3e9336f | 4169 | CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered); |
32131a9c | 4170 | |
1f3b1e1a | 4171 | set_initial_elim_offsets (); |
32131a9c | 4172 | |
7609e720 | 4173 | for (chain = reload_insn_chain; chain; chain = chain->next) |
32131a9c | 4174 | { |
0334ef47 | 4175 | rtx prev = 0; |
7609e720 BS |
4176 | rtx insn = chain->insn; |
4177 | rtx old_next = NEXT_INSN (insn); | |
bf8ba8ab VM |
4178 | #ifdef AUTO_INC_DEC |
4179 | rtx old_prev = PREV_INSN (insn); | |
4180 | #endif | |
32131a9c RK |
4181 | |
4182 | /* If we pass a label, copy the offsets from the label information | |
4183 | into the current offsets of each elimination. */ | |
4b4bf941 | 4184 | if (LABEL_P (insn)) |
1f3b1e1a | 4185 | set_offsets_for_label (insn); |
32131a9c | 4186 | |
2c3c49de | 4187 | else if (INSN_P (insn)) |
32131a9c | 4188 | { |
db4c7386 JH |
4189 | regset_head regs_to_forget; |
4190 | INIT_REG_SET (®s_to_forget); | |
4191 | note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget); | |
7ffaaddc | 4192 | |
2758481d RS |
4193 | /* If this is a USE and CLOBBER of a MEM, ensure that any |
4194 | references to eliminable registers have been removed. */ | |
4195 | ||
4196 | if ((GET_CODE (PATTERN (insn)) == USE | |
4197 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
3c0cb5de | 4198 | && MEM_P (XEXP (PATTERN (insn), 0))) |
2758481d RS |
4199 | XEXP (XEXP (PATTERN (insn), 0), 0) |
4200 | = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), | |
29ae5012 | 4201 | GET_MODE (XEXP (PATTERN (insn), 0)), |
1914f5da | 4202 | NULL_RTX); |
2758481d | 4203 | |
32131a9c RK |
4204 | /* If we need to do register elimination processing, do so. |
4205 | This might delete the insn, in which case we are done. */ | |
2b49ee39 | 4206 | if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) |
32131a9c RK |
4207 | { |
4208 | eliminate_regs_in_insn (insn, 1); | |
4b4bf941 | 4209 | if (NOTE_P (insn)) |
cb2afeb3 R |
4210 | { |
4211 | update_eliminable_offsets (); | |
db4c7386 | 4212 | CLEAR_REG_SET (®s_to_forget); |
cb2afeb3 R |
4213 | continue; |
4214 | } | |
32131a9c RK |
4215 | } |
4216 | ||
7609e720 BS |
4217 | /* If need_elim is nonzero but need_reload is zero, one might think |
4218 | that we could simply set n_reloads to 0. However, find_reloads | |
4219 | could have done some manipulation of the insn (such as swapping | |
4220 | commutative operands), and these manipulations are lost during | |
4221 | the first pass for every insn that needs register elimination. | |
4222 | So the actions of find_reloads must be redone here. */ | |
4223 | ||
03acd8f8 BS |
4224 | if (! chain->need_elim && ! chain->need_reload |
4225 | && ! chain->need_operand_change) | |
32131a9c RK |
4226 | n_reloads = 0; |
4227 | /* First find the pseudo regs that must be reloaded for this insn. | |
4228 | This info is returned in the tables reload_... (see reload.h). | |
4229 | Also modify the body of INSN by substituting RELOAD | |
4230 | rtx's for those pseudo regs. */ | |
4231 | else | |
4232 | { | |
2c61f5f1 | 4233 | CLEAR_REG_SET (®_has_output_reload); |
32131a9c RK |
4234 | CLEAR_HARD_REG_SET (reg_is_output_reload); |
4235 | ||
4236 | find_reloads (insn, 1, spill_indirect_levels, live_known, | |
4237 | spill_reg_order); | |
4238 | } | |
4239 | ||
4240 | if (n_reloads > 0) | |
4241 | { | |
cb2afeb3 | 4242 | rtx next = NEXT_INSN (insn); |
3c3eeea6 | 4243 | rtx p; |
32131a9c | 4244 | |
cb2afeb3 R |
4245 | prev = PREV_INSN (insn); |
4246 | ||
32131a9c RK |
4247 | /* Now compute which reload regs to reload them into. Perhaps |
4248 | reusing reload regs from previous insns, or else output | |
4249 | load insns to reload them. Maybe output store insns too. | |
4250 | Record the choices of reload reg in reload_reg_rtx. */ | |
03acd8f8 | 4251 | choose_reload_regs (chain); |
32131a9c | 4252 | |
05d10675 | 4253 | /* Merge any reloads that we didn't combine for fear of |
546b63fb RK |
4254 | increasing the number of spill registers needed but now |
4255 | discover can be safely merged. */ | |
f95182a4 ILT |
4256 | if (SMALL_REGISTER_CLASSES) |
4257 | merge_assigned_reloads (insn); | |
546b63fb | 4258 | |
32131a9c RK |
4259 | /* Generate the insns to reload operands into or out of |
4260 | their reload regs. */ | |
e04ca094 | 4261 | emit_reload_insns (chain); |
32131a9c RK |
4262 | |
4263 | /* Substitute the chosen reload regs from reload_reg_rtx | |
4264 | into the insn's body (or perhaps into the bodies of other | |
4265 | load and store insn that we just made for reloading | |
4266 | and that we moved the structure into). */ | |
f759eb8b | 4267 | subst_reloads (insn); |
3c3eeea6 | 4268 | |
be0c514c | 4269 | /* Adjust the exception region notes for loads and stores. */ |
e3947b34 | 4270 | if (flag_non_call_exceptions && !CALL_P (insn)) |
be0c514c RH |
4271 | fixup_eh_region_note (insn, prev, next); |
4272 | ||
3c3eeea6 RK |
4273 | /* If this was an ASM, make sure that all the reload insns |
4274 | we have generated are valid. If not, give an error | |
4275 | and delete them. */ | |
3c3eeea6 RK |
4276 | if (asm_noperands (PATTERN (insn)) >= 0) |
4277 | for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) | |
2c3c49de | 4278 | if (p != insn && INSN_P (p) |
00dcfe80 | 4279 | && GET_CODE (PATTERN (p)) != USE |
3c3eeea6 | 4280 | && (recog_memoized (p) < 0 |
0eadeb15 | 4281 | || (extract_insn (p), ! constrain_operands (1)))) |
3c3eeea6 RK |
4282 | { |
4283 | error_for_asm (insn, | |
971801ff JM |
4284 | "%<asm%> operand requires " |
4285 | "impossible reload"); | |
ca6c03ca | 4286 | delete_insn (p); |
3c3eeea6 | 4287 | } |
32131a9c | 4288 | } |
5d7ef82a BS |
4289 | |
4290 | if (num_eliminable && chain->need_elim) | |
4291 | update_eliminable_offsets (); | |
4292 | ||
32131a9c RK |
4293 | /* Any previously reloaded spilled pseudo reg, stored in this insn, |
4294 | is no longer validly lying around to save a future reload. | |
4295 | Note that this does not detect pseudos that were reloaded | |
4296 | for this insn in order to be stored in | |
4297 | (obeying register constraints). That is correct; such reload | |
4298 | registers ARE still valid. */ | |
db4c7386 JH |
4299 | forget_marked_reloads (®s_to_forget); |
4300 | CLEAR_REG_SET (®s_to_forget); | |
32131a9c RK |
4301 | |
4302 | /* There may have been CLOBBER insns placed after INSN. So scan | |
4303 | between INSN and NEXT and use them to forget old reloads. */ | |
7609e720 | 4304 | for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) |
4b4bf941 | 4305 | if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER) |
84832317 | 4306 | note_stores (PATTERN (x), forget_old_reloads_1, NULL); |
32131a9c RK |
4307 | |
4308 | #ifdef AUTO_INC_DEC | |
cb2afeb3 R |
4309 | /* Likewise for regs altered by auto-increment in this insn. |
4310 | REG_INC notes have been changed by reloading: | |
4311 | find_reloads_address_1 records substitutions for them, | |
4312 | which have been performed by subst_reloads above. */ | |
4313 | for (i = n_reloads - 1; i >= 0; i--) | |
4314 | { | |
eceef4c9 | 4315 | rtx in_reg = rld[i].in_reg; |
cb2afeb3 R |
4316 | if (in_reg) |
4317 | { | |
4318 | enum rtx_code code = GET_CODE (in_reg); | |
4319 | /* PRE_INC / PRE_DEC will have the reload register ending up | |
4320 | with the same value as the stack slot, but that doesn't | |
4321 | hold true for POST_INC / POST_DEC. Either we have to | |
4322 | convert the memory access to a true POST_INC / POST_DEC, | |
4323 | or we can't use the reload register for inheritance. */ | |
4324 | if ((code == POST_INC || code == POST_DEC) | |
4325 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 4326 | REGNO (rld[i].reg_rtx)) |
04bbb0c5 JW |
4327 | /* Make sure it is the inc/dec pseudo, and not |
4328 | some other (e.g. output operand) pseudo. */ | |
fc555370 | 4329 | && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
04bbb0c5 | 4330 | == REGNO (XEXP (in_reg, 0)))) |
05d10675 | 4331 | |
cb2afeb3 | 4332 | { |
eceef4c9 | 4333 | rtx reload_reg = rld[i].reg_rtx; |
cb2afeb3 R |
4334 | enum machine_mode mode = GET_MODE (reload_reg); |
4335 | int n = 0; | |
4336 | rtx p; | |
4337 | ||
4338 | for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) | |
4339 | { | |
4340 | /* We really want to ignore REG_INC notes here, so | |
4341 | use PATTERN (p) as argument to reg_set_p . */ | |
4342 | if (reg_set_p (reload_reg, PATTERN (p))) | |
4343 | break; | |
4b983fdc | 4344 | n = count_occurrences (PATTERN (p), reload_reg, 0); |
cb2afeb3 R |
4345 | if (! n) |
4346 | continue; | |
4347 | if (n == 1) | |
f67c2384 | 4348 | { |
0159ec79 UW |
4349 | rtx replace_reg |
4350 | = gen_rtx_fmt_e (code, mode, reload_reg); | |
4351 | ||
4352 | validate_replace_rtx_group (reload_reg, | |
4353 | replace_reg, p); | |
4354 | n = verify_changes (0); | |
f67c2384 JL |
4355 | |
4356 | /* We must also verify that the constraints | |
94aca67a HPN |
4357 | are met after the replacement. Make sure |
4358 | extract_insn is only called for an insn | |
4359 | where the replacements were found to be | |
4360 | valid so far. */ | |
f67c2384 | 4361 | if (n) |
94aca67a HPN |
4362 | { |
4363 | extract_insn (p); | |
4364 | n = constrain_operands (1); | |
4365 | } | |
f67c2384 JL |
4366 | |
4367 | /* If the constraints were not met, then | |
0159ec79 | 4368 | undo the replacement, else confirm it. */ |
f67c2384 | 4369 | if (!n) |
0159ec79 UW |
4370 | cancel_changes (0); |
4371 | else | |
4372 | confirm_change_group (); | |
f67c2384 | 4373 | } |
cb2afeb3 R |
4374 | break; |
4375 | } | |
4376 | if (n == 1) | |
02eb1393 | 4377 | { |
65c5f2a6 | 4378 | add_reg_note (p, REG_INC, reload_reg); |
02eb1393 R |
4379 | /* Mark this as having an output reload so that the |
4380 | REG_INC processing code below won't invalidate | |
4381 | the reload for inheritance. */ | |
4382 | SET_HARD_REG_BIT (reg_is_output_reload, | |
4383 | REGNO (reload_reg)); | |
2c61f5f1 JH |
4384 | SET_REGNO_REG_SET (®_has_output_reload, |
4385 | REGNO (XEXP (in_reg, 0))); | |
02eb1393 | 4386 | } |
cb2afeb3 | 4387 | else |
1d7254c5 | 4388 | forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, |
84832317 | 4389 | NULL); |
cb2afeb3 | 4390 | } |
02eb1393 R |
4391 | else if ((code == PRE_INC || code == PRE_DEC) |
4392 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 4393 | REGNO (rld[i].reg_rtx)) |
02eb1393 R |
4394 | /* Make sure it is the inc/dec pseudo, and not |
4395 | some other (e.g. output operand) pseudo. */ | |
fc555370 | 4396 | && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
02eb1393 R |
4397 | == REGNO (XEXP (in_reg, 0)))) |
4398 | { | |
4399 | SET_HARD_REG_BIT (reg_is_output_reload, | |
eceef4c9 | 4400 | REGNO (rld[i].reg_rtx)); |
2c61f5f1 JH |
4401 | SET_REGNO_REG_SET (®_has_output_reload, |
4402 | REGNO (XEXP (in_reg, 0))); | |
02eb1393 | 4403 | } |
d5f89b53 VM |
4404 | else if (code == PRE_INC || code == PRE_DEC |
4405 | || code == POST_INC || code == POST_DEC) | |
bf8ba8ab | 4406 | { |
bf8ba8ab VM |
4407 | int in_regno = REGNO (XEXP (in_reg, 0)); |
4408 | ||
4409 | if (reg_last_reload_reg[in_regno] != NULL_RTX) | |
4410 | { | |
d5f89b53 VM |
4411 | int in_hard_regno; |
4412 | bool forget_p = true; | |
4413 | ||
bf8ba8ab | 4414 | in_hard_regno = REGNO (reg_last_reload_reg[in_regno]); |
d5f89b53 VM |
4415 | if (TEST_HARD_REG_BIT (reg_reloaded_valid, |
4416 | in_hard_regno)) | |
4417 | { | |
4418 | for (x = old_prev ? NEXT_INSN (old_prev) : insn; | |
4419 | x != old_next; | |
4420 | x = NEXT_INSN (x)) | |
4421 | if (x == reg_reloaded_insn[in_hard_regno]) | |
4422 | { | |
4423 | forget_p = false; | |
4424 | break; | |
4425 | } | |
4426 | } | |
bf8ba8ab VM |
4427 | /* If for some reasons, we didn't set up |
4428 | reg_last_reload_reg in this insn, | |
4429 | invalidate inheritance from previous | |
4430 | insns for the incremented/decremented | |
4431 | register. Such registers will be not in | |
d5f89b53 VM |
4432 | reg_has_output_reload. Invalidate it |
4433 | also if the corresponding element in | |
4434 | reg_reloaded_insn is also | |
4435 | invalidated. */ | |
4436 | if (forget_p) | |
bf8ba8ab VM |
4437 | forget_old_reloads_1 (XEXP (in_reg, 0), |
4438 | NULL_RTX, NULL); | |
4439 | } | |
4440 | } | |
cb2afeb3 R |
4441 | } |
4442 | } | |
02eb1393 R |
4443 | /* If a pseudo that got a hard register is auto-incremented, |
4444 | we must purge records of copying it into pseudos without | |
4445 | hard registers. */ | |
32131a9c RK |
4446 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) |
4447 | if (REG_NOTE_KIND (x) == REG_INC) | |
4448 | { | |
4449 | /* See if this pseudo reg was reloaded in this insn. | |
4450 | If so, its last-reload info is still valid | |
4451 | because it is based on this insn's reload. */ | |
4452 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 4453 | if (rld[i].out == XEXP (x, 0)) |
32131a9c RK |
4454 | break; |
4455 | ||
08fb99fa | 4456 | if (i == n_reloads) |
84832317 | 4457 | forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); |
32131a9c RK |
4458 | } |
4459 | #endif | |
4460 | } | |
4461 | /* A reload reg's contents are unknown after a label. */ | |
4b4bf941 | 4462 | if (LABEL_P (insn)) |
e6e52be0 | 4463 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c RK |
4464 | |
4465 | /* Don't assume a reload reg is still good after a call insn | |
e3e9336f DJ |
4466 | if it is a call-used reg, or if it contains a value that will |
4467 | be partially clobbered by the call. */ | |
4b4bf941 | 4468 | else if (CALL_P (insn)) |
e3e9336f | 4469 | { |
058e97ec VM |
4470 | AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set); |
4471 | AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered); | |
e3e9336f | 4472 | } |
32131a9c | 4473 | } |
ff154f78 MM |
4474 | |
4475 | /* Clean up. */ | |
4476 | free (reg_last_reload_reg); | |
2c61f5f1 | 4477 | CLEAR_REG_SET (®_has_output_reload); |
32131a9c RK |
4478 | } |
4479 | ||
4480 | /* Discard all record of any value reloaded from X, | |
4481 | or reloaded in X from someplace else; | |
4482 | unless X is an output reload reg of the current insn. | |
4483 | ||
4484 | X may be a hard reg (the reload reg) | |
db4c7386 JH |
4485 | or it may be a pseudo reg that was reloaded from. |
4486 | ||
4487 | When DATA is non-NULL just mark the registers in regset | |
4488 | to be forgotten later. */ | |
32131a9c RK |
4489 | |
4490 | static void | |
7bc980e1 | 4491 | forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED, |
db4c7386 | 4492 | void *data) |
32131a9c | 4493 | { |
770ae6cc RK |
4494 | unsigned int regno; |
4495 | unsigned int nr; | |
db4c7386 | 4496 | regset regs = (regset) data; |
0a2e51a9 | 4497 | |
ddef6bc7 | 4498 | /* note_stores does give us subregs of hard regs, |
0e61db61 | 4499 | subreg_regno_offset requires a hard reg. */ |
0a2e51a9 RS |
4500 | while (GET_CODE (x) == SUBREG) |
4501 | { | |
fefac463 AH |
4502 | /* We ignore the subreg offset when calculating the regno, |
4503 | because we are using the entire underlying hard register | |
4504 | below. */ | |
0a2e51a9 RS |
4505 | x = SUBREG_REG (x); |
4506 | } | |
32131a9c | 4507 | |
f8cfc6aa | 4508 | if (!REG_P (x)) |
32131a9c RK |
4509 | return; |
4510 | ||
fefac463 | 4511 | regno = REGNO (x); |
32131a9c RK |
4512 | |
4513 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4514 | nr = 1; | |
4515 | else | |
4516 | { | |
770ae6cc RK |
4517 | unsigned int i; |
4518 | ||
66fd46b6 | 4519 | nr = hard_regno_nregs[regno][GET_MODE (x)]; |
32131a9c RK |
4520 | /* Storing into a spilled-reg invalidates its contents. |
4521 | This can happen if a block-local pseudo is allocated to that reg | |
4522 | and it wasn't spilled because this block's total need is 0. | |
4523 | Then some insn might have an optional reload and use this reg. */ | |
db4c7386 JH |
4524 | if (!regs) |
4525 | for (i = 0; i < nr; i++) | |
4526 | /* But don't do this if the reg actually serves as an output | |
4527 | reload reg in the current instruction. */ | |
4528 | if (n_reloads == 0 | |
4529 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) | |
4530 | { | |
4531 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); | |
db4c7386 JH |
4532 | spill_reg_store[regno + i] = 0; |
4533 | } | |
32131a9c RK |
4534 | } |
4535 | ||
db4c7386 JH |
4536 | if (regs) |
4537 | while (nr-- > 0) | |
4538 | SET_REGNO_REG_SET (regs, regno + nr); | |
4539 | else | |
4540 | { | |
4541 | /* Since value of X has changed, | |
4542 | forget any value previously copied from it. */ | |
4543 | ||
4544 | while (nr-- > 0) | |
4545 | /* But don't forget a copy if this is the output reload | |
4546 | that establishes the copy's validity. */ | |
2c61f5f1 JH |
4547 | if (n_reloads == 0 |
4548 | || !REGNO_REG_SET_P (®_has_output_reload, regno + nr)) | |
db4c7386 JH |
4549 | reg_last_reload_reg[regno + nr] = 0; |
4550 | } | |
4551 | } | |
32131a9c | 4552 | |
db4c7386 JH |
4553 | /* Forget the reloads marked in regset by previous function. */ |
4554 | static void | |
4555 | forget_marked_reloads (regset regs) | |
4556 | { | |
4557 | unsigned int reg; | |
4558 | reg_set_iterator rsi; | |
4559 | EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi) | |
4560 | { | |
4561 | if (reg < FIRST_PSEUDO_REGISTER | |
4562 | /* But don't do this if the reg actually serves as an output | |
4563 | reload reg in the current instruction. */ | |
4564 | && (n_reloads == 0 | |
4565 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg))) | |
4566 | { | |
4567 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg); | |
db4c7386 JH |
4568 | spill_reg_store[reg] = 0; |
4569 | } | |
2c61f5f1 JH |
4570 | if (n_reloads == 0 |
4571 | || !REGNO_REG_SET_P (®_has_output_reload, reg)) | |
db4c7386 JH |
4572 | reg_last_reload_reg[reg] = 0; |
4573 | } | |
32131a9c RK |
4574 | } |
4575 | \f | |
32131a9c RK |
4576 | /* The following HARD_REG_SETs indicate when each hard register is |
4577 | used for a reload of various parts of the current insn. */ | |
4578 | ||
9e3a9cf2 BS |
4579 | /* If reg is unavailable for all reloads. */ |
4580 | static HARD_REG_SET reload_reg_unavailable; | |
32131a9c RK |
4581 | /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ |
4582 | static HARD_REG_SET reload_reg_used; | |
546b63fb RK |
4583 | /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ |
4584 | static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4585 | /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ |
4586 | static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4587 | /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ |
4588 | static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4589 | /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ |
4590 | static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4591 | /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ |
4592 | static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; | |
4593 | /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ | |
4594 | static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
4595 | /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ |
4596 | static HARD_REG_SET reload_reg_used_in_op_addr; | |
893bc853 RK |
4597 | /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ |
4598 | static HARD_REG_SET reload_reg_used_in_op_addr_reload; | |
546b63fb RK |
4599 | /* If reg is in use for a RELOAD_FOR_INSN reload. */ |
4600 | static HARD_REG_SET reload_reg_used_in_insn; | |
4601 | /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ | |
4602 | static HARD_REG_SET reload_reg_used_in_other_addr; | |
32131a9c RK |
4603 | |
4604 | /* If reg is in use as a reload reg for any sort of reload. */ | |
4605 | static HARD_REG_SET reload_reg_used_at_all; | |
4606 | ||
be7ae2a4 RK |
4607 | /* If reg is use as an inherited reload. We just mark the first register |
4608 | in the group. */ | |
4609 | static HARD_REG_SET reload_reg_used_for_inherit; | |
4610 | ||
f1db3576 JL |
4611 | /* Records which hard regs are used in any way, either as explicit use or |
4612 | by being allocated to a pseudo during any point of the current insn. */ | |
4613 | static HARD_REG_SET reg_used_in_insn; | |
297927a8 | 4614 | |
546b63fb RK |
4615 | /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and |
4616 | TYPE. MODE is used to indicate how many consecutive regs are | |
4617 | actually used. */ | |
32131a9c RK |
4618 | |
4619 | static void | |
0c20a65f AJ |
4620 | mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type, |
4621 | enum machine_mode mode) | |
32131a9c | 4622 | { |
66fd46b6 | 4623 | unsigned int nregs = hard_regno_nregs[regno][mode]; |
770ae6cc | 4624 | unsigned int i; |
32131a9c RK |
4625 | |
4626 | for (i = regno; i < nregs + regno; i++) | |
4627 | { | |
546b63fb | 4628 | switch (type) |
32131a9c RK |
4629 | { |
4630 | case RELOAD_OTHER: | |
4631 | SET_HARD_REG_BIT (reload_reg_used, i); | |
4632 | break; | |
4633 | ||
546b63fb RK |
4634 | case RELOAD_FOR_INPUT_ADDRESS: |
4635 | SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); | |
32131a9c RK |
4636 | break; |
4637 | ||
47c8cf91 ILT |
4638 | case RELOAD_FOR_INPADDR_ADDRESS: |
4639 | SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); | |
4640 | break; | |
4641 | ||
546b63fb RK |
4642 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4643 | SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); | |
32131a9c RK |
4644 | break; |
4645 | ||
47c8cf91 ILT |
4646 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4647 | SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); | |
4648 | break; | |
4649 | ||
32131a9c RK |
4650 | case RELOAD_FOR_OPERAND_ADDRESS: |
4651 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
4652 | break; | |
4653 | ||
893bc853 RK |
4654 | case RELOAD_FOR_OPADDR_ADDR: |
4655 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); | |
4656 | break; | |
4657 | ||
546b63fb RK |
4658 | case RELOAD_FOR_OTHER_ADDRESS: |
4659 | SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); | |
4660 | break; | |
4661 | ||
32131a9c | 4662 | case RELOAD_FOR_INPUT: |
546b63fb | 4663 | SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); |
32131a9c RK |
4664 | break; |
4665 | ||
4666 | case RELOAD_FOR_OUTPUT: | |
546b63fb RK |
4667 | SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); |
4668 | break; | |
4669 | ||
4670 | case RELOAD_FOR_INSN: | |
4671 | SET_HARD_REG_BIT (reload_reg_used_in_insn, i); | |
32131a9c RK |
4672 | break; |
4673 | } | |
4674 | ||
4675 | SET_HARD_REG_BIT (reload_reg_used_at_all, i); | |
4676 | } | |
4677 | } | |
4678 | ||
be7ae2a4 RK |
4679 | /* Similarly, but show REGNO is no longer in use for a reload. */ |
4680 | ||
4681 | static void | |
0c20a65f AJ |
4682 | clear_reload_reg_in_use (unsigned int regno, int opnum, |
4683 | enum reload_type type, enum machine_mode mode) | |
be7ae2a4 | 4684 | { |
66fd46b6 | 4685 | unsigned int nregs = hard_regno_nregs[regno][mode]; |
770ae6cc | 4686 | unsigned int start_regno, end_regno, r; |
be7ae2a4 | 4687 | int i; |
cb2afeb3 R |
4688 | /* A complication is that for some reload types, inheritance might |
4689 | allow multiple reloads of the same types to share a reload register. | |
4690 | We set check_opnum if we have to check only reloads with the same | |
4691 | operand number, and check_any if we have to check all reloads. */ | |
4692 | int check_opnum = 0; | |
4693 | int check_any = 0; | |
4694 | HARD_REG_SET *used_in_set; | |
be7ae2a4 | 4695 | |
cb2afeb3 | 4696 | switch (type) |
be7ae2a4 | 4697 | { |
cb2afeb3 R |
4698 | case RELOAD_OTHER: |
4699 | used_in_set = &reload_reg_used; | |
4700 | break; | |
be7ae2a4 | 4701 | |
cb2afeb3 R |
4702 | case RELOAD_FOR_INPUT_ADDRESS: |
4703 | used_in_set = &reload_reg_used_in_input_addr[opnum]; | |
4704 | break; | |
be7ae2a4 | 4705 | |
cb2afeb3 R |
4706 | case RELOAD_FOR_INPADDR_ADDRESS: |
4707 | check_opnum = 1; | |
4708 | used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; | |
4709 | break; | |
47c8cf91 | 4710 | |
cb2afeb3 R |
4711 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4712 | used_in_set = &reload_reg_used_in_output_addr[opnum]; | |
4713 | break; | |
be7ae2a4 | 4714 | |
cb2afeb3 R |
4715 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4716 | check_opnum = 1; | |
4717 | used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; | |
4718 | break; | |
47c8cf91 | 4719 | |
cb2afeb3 R |
4720 | case RELOAD_FOR_OPERAND_ADDRESS: |
4721 | used_in_set = &reload_reg_used_in_op_addr; | |
4722 | break; | |
be7ae2a4 | 4723 | |
cb2afeb3 R |
4724 | case RELOAD_FOR_OPADDR_ADDR: |
4725 | check_any = 1; | |
4726 | used_in_set = &reload_reg_used_in_op_addr_reload; | |
4727 | break; | |
893bc853 | 4728 | |
cb2afeb3 R |
4729 | case RELOAD_FOR_OTHER_ADDRESS: |
4730 | used_in_set = &reload_reg_used_in_other_addr; | |
4731 | check_any = 1; | |
4732 | break; | |
be7ae2a4 | 4733 | |
cb2afeb3 R |
4734 | case RELOAD_FOR_INPUT: |
4735 | used_in_set = &reload_reg_used_in_input[opnum]; | |
4736 | break; | |
be7ae2a4 | 4737 | |
cb2afeb3 R |
4738 | case RELOAD_FOR_OUTPUT: |
4739 | used_in_set = &reload_reg_used_in_output[opnum]; | |
4740 | break; | |
be7ae2a4 | 4741 | |
cb2afeb3 R |
4742 | case RELOAD_FOR_INSN: |
4743 | used_in_set = &reload_reg_used_in_insn; | |
4744 | break; | |
4745 | default: | |
41374e13 | 4746 | gcc_unreachable (); |
cb2afeb3 R |
4747 | } |
4748 | /* We resolve conflicts with remaining reloads of the same type by | |
68e82b83 | 4749 | excluding the intervals of reload registers by them from the |
cb2afeb3 R |
4750 | interval of freed reload registers. Since we only keep track of |
4751 | one set of interval bounds, we might have to exclude somewhat | |
3e92902c | 4752 | more than what would be necessary if we used a HARD_REG_SET here. |
cb2afeb3 R |
4753 | But this should only happen very infrequently, so there should |
4754 | be no reason to worry about it. */ | |
05d10675 | 4755 | |
cb2afeb3 R |
4756 | start_regno = regno; |
4757 | end_regno = regno + nregs; | |
4758 | if (check_opnum || check_any) | |
4759 | { | |
4760 | for (i = n_reloads - 1; i >= 0; i--) | |
4761 | { | |
eceef4c9 BS |
4762 | if (rld[i].when_needed == type |
4763 | && (check_any || rld[i].opnum == opnum) | |
4764 | && rld[i].reg_rtx) | |
cb2afeb3 | 4765 | { |
770ae6cc RK |
4766 | unsigned int conflict_start = true_regnum (rld[i].reg_rtx); |
4767 | unsigned int conflict_end | |
09e18274 | 4768 | = end_hard_regno (rld[i].mode, conflict_start); |
cb2afeb3 R |
4769 | |
4770 | /* If there is an overlap with the first to-be-freed register, | |
4771 | adjust the interval start. */ | |
4772 | if (conflict_start <= start_regno && conflict_end > start_regno) | |
4773 | start_regno = conflict_end; | |
4774 | /* Otherwise, if there is a conflict with one of the other | |
4775 | to-be-freed registers, adjust the interval end. */ | |
4776 | if (conflict_start > start_regno && conflict_start < end_regno) | |
4777 | end_regno = conflict_start; | |
4778 | } | |
be7ae2a4 RK |
4779 | } |
4780 | } | |
770ae6cc RK |
4781 | |
4782 | for (r = start_regno; r < end_regno; r++) | |
4783 | CLEAR_HARD_REG_BIT (*used_in_set, r); | |
be7ae2a4 RK |
4784 | } |
4785 | ||
32131a9c | 4786 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort |
546b63fb | 4787 | specified by OPNUM and TYPE. */ |
32131a9c RK |
4788 | |
4789 | static int | |
0c20a65f | 4790 | reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type) |
32131a9c | 4791 | { |
546b63fb RK |
4792 | int i; |
4793 | ||
2edc8d65 | 4794 | /* In use for a RELOAD_OTHER means it's not available for anything. */ |
9e3a9cf2 BS |
4795 | if (TEST_HARD_REG_BIT (reload_reg_used, regno) |
4796 | || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) | |
32131a9c | 4797 | return 0; |
546b63fb RK |
4798 | |
4799 | switch (type) | |
32131a9c RK |
4800 | { |
4801 | case RELOAD_OTHER: | |
2edc8d65 RK |
4802 | /* In use for anything means we can't use it for RELOAD_OTHER. */ |
4803 | if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) | |
224f1d71 | 4804 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
808ededc | 4805 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) |
224f1d71 RK |
4806 | || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) |
4807 | return 0; | |
4808 | ||
4809 | for (i = 0; i < reload_n_operands; i++) | |
4810 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4811 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
224f1d71 | 4812 | || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
47c8cf91 | 4813 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
224f1d71 RK |
4814 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) |
4815 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4816 | return 0; | |
4817 | ||
4818 | return 1; | |
32131a9c | 4819 | |
32131a9c | 4820 | case RELOAD_FOR_INPUT: |
546b63fb RK |
4821 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4822 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
4823 | return 0; | |
4824 | ||
893bc853 RK |
4825 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4826 | return 0; | |
4827 | ||
546b63fb RK |
4828 | /* If it is used for some other input, can't use it. */ |
4829 | for (i = 0; i < reload_n_operands; i++) | |
4830 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4831 | return 0; | |
4832 | ||
4833 | /* If it is used in a later operand's address, can't use it. */ | |
4834 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4835 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4836 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4837 | return 0; |
4838 | ||
4839 | return 1; | |
4840 | ||
4841 | case RELOAD_FOR_INPUT_ADDRESS: | |
4842 | /* Can't use a register if it is used for an input address for this | |
4843 | operand or used as an input in an earlier one. */ | |
47c8cf91 ILT |
4844 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) |
4845 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) | |
4846 | return 0; | |
4847 | ||
4848 | for (i = 0; i < opnum; i++) | |
4849 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4850 | return 0; | |
4851 | ||
4852 | return 1; | |
4853 | ||
4854 | case RELOAD_FOR_INPADDR_ADDRESS: | |
4855 | /* Can't use a register if it is used for an input address | |
05d10675 BS |
4856 | for this operand or used as an input in an earlier |
4857 | one. */ | |
47c8cf91 | 4858 | if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) |
546b63fb RK |
4859 | return 0; |
4860 | ||
4861 | for (i = 0; i < opnum; i++) | |
4862 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4863 | return 0; | |
4864 | ||
4865 | return 1; | |
4866 | ||
4867 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
4868 | /* Can't use a register if it is used for an output address for this | |
d1d18b46 DJ |
4869 | operand or used as an output in this or a later operand. Note |
4870 | that multiple output operands are emitted in reverse order, so | |
4871 | the conflicting ones are those with lower indices. */ | |
546b63fb RK |
4872 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) |
4873 | return 0; | |
4874 | ||
d1d18b46 | 4875 | for (i = 0; i <= opnum; i++) |
546b63fb RK |
4876 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4877 | return 0; | |
4878 | ||
4879 | return 1; | |
4880 | ||
47c8cf91 ILT |
4881 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4882 | /* Can't use a register if it is used for an output address | |
05d10675 | 4883 | for this operand or used as an output in this or a |
d1d18b46 DJ |
4884 | later operand. Note that multiple output operands are |
4885 | emitted in reverse order, so the conflicting ones are | |
4886 | those with lower indices. */ | |
47c8cf91 ILT |
4887 | if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) |
4888 | return 0; | |
4889 | ||
d1d18b46 | 4890 | for (i = 0; i <= opnum; i++) |
47c8cf91 ILT |
4891 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4892 | return 0; | |
4893 | ||
4894 | return 1; | |
4895 | ||
32131a9c | 4896 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4897 | for (i = 0; i < reload_n_operands; i++) |
4898 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4899 | return 0; | |
4900 | ||
4901 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4902 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4903 | ||
893bc853 RK |
4904 | case RELOAD_FOR_OPADDR_ADDR: |
4905 | for (i = 0; i < reload_n_operands; i++) | |
05d10675 BS |
4906 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4907 | return 0; | |
893bc853 | 4908 | |
a94ce333 | 4909 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); |
893bc853 | 4910 | |
32131a9c | 4911 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4912 | /* This cannot share a register with RELOAD_FOR_INSN reloads, other |
d1d18b46 DJ |
4913 | outputs, or an operand address for this or an earlier output. |
4914 | Note that multiple output operands are emitted in reverse order, | |
4915 | so the conflicting ones are those with higher indices. */ | |
546b63fb RK |
4916 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) |
4917 | return 0; | |
4918 | ||
4919 | for (i = 0; i < reload_n_operands; i++) | |
4920 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4921 | return 0; | |
4922 | ||
d1d18b46 | 4923 | for (i = opnum; i < reload_n_operands; i++) |
47c8cf91 ILT |
4924 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4925 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4926 | return 0; |
4927 | ||
4928 | return 1; | |
4929 | ||
4930 | case RELOAD_FOR_INSN: | |
4931 | for (i = 0; i < reload_n_operands; i++) | |
4932 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) | |
4933 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4934 | return 0; | |
4935 | ||
4936 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4937 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4938 | ||
4939 | case RELOAD_FOR_OTHER_ADDRESS: | |
4940 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
41374e13 NS |
4941 | |
4942 | default: | |
4943 | gcc_unreachable (); | |
32131a9c | 4944 | } |
32131a9c RK |
4945 | } |
4946 | ||
32131a9c | 4947 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
546b63fb | 4948 | needed for the part of the insn specified by OPNUM and TYPE, |
32131a9c RK |
4949 | is still available in REGNO at the end of the insn. |
4950 | ||
4951 | We can assume that the reload reg was already tested for availability | |
4952 | at the time it is needed, and we should not check this again, | |
4953 | in case the reg has already been marked in use. */ | |
4954 | ||
4955 | static int | |
0c20a65f | 4956 | reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type) |
32131a9c | 4957 | { |
546b63fb RK |
4958 | int i; |
4959 | ||
4960 | switch (type) | |
32131a9c RK |
4961 | { |
4962 | case RELOAD_OTHER: | |
4963 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
4964 | its value must reach the end. */ | |
4965 | return 1; | |
4966 | ||
4967 | /* If this use is for part of the insn, | |
05d10675 | 4968 | its value reaches if no subsequent part uses the same register. |
546b63fb RK |
4969 | Just like the above function, don't try to do this with lots |
4970 | of fallthroughs. */ | |
4971 | ||
4972 | case RELOAD_FOR_OTHER_ADDRESS: | |
4973 | /* Here we check for everything else, since these don't conflict | |
4974 | with anything else and everything comes later. */ | |
4975 | ||
4976 | for (i = 0; i < reload_n_operands; i++) | |
4977 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4978 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4979 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) |
4980 | || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4981 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4982 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4983 | return 0; | |
4984 | ||
4985 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
808ededc | 4986 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) |
546b63fb RK |
4987 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4988 | && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
4989 | ||
4990 | case RELOAD_FOR_INPUT_ADDRESS: | |
47c8cf91 | 4991 | case RELOAD_FOR_INPADDR_ADDRESS: |
546b63fb RK |
4992 | /* Similar, except that we check only for this and subsequent inputs |
4993 | and the address of only subsequent inputs and we do not need | |
4994 | to check for RELOAD_OTHER objects since they are known not to | |
4995 | conflict. */ | |
4996 | ||
4997 | for (i = opnum; i < reload_n_operands; i++) | |
4998 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4999 | return 0; | |
5000 | ||
5001 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
5002 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
5003 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
5004 | return 0; |
5005 | ||
5006 | for (i = 0; i < reload_n_operands; i++) | |
5007 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 5008 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
5009 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
5010 | return 0; | |
5011 | ||
893bc853 RK |
5012 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
5013 | return 0; | |
5014 | ||
2af88768 GK |
5015 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
5016 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
5017 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
546b63fb | 5018 | |
32131a9c | 5019 | case RELOAD_FOR_INPUT: |
546b63fb | 5020 | /* Similar to input address, except we start at the next operand for |
05d10675 | 5021 | both input and input address and we do not check for |
546b63fb RK |
5022 | RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these |
5023 | would conflict. */ | |
5024 | ||
5025 | for (i = opnum + 1; i < reload_n_operands; i++) | |
5026 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 5027 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
5028 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
5029 | return 0; | |
5030 | ||
0f41302f | 5031 | /* ... fall through ... */ |
546b63fb | 5032 | |
32131a9c | 5033 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
5034 | /* Check outputs and their addresses. */ |
5035 | ||
5036 | for (i = 0; i < reload_n_operands; i++) | |
5037 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 5038 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
5039 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
5040 | return 0; | |
5041 | ||
2af88768 | 5042 | return (!TEST_HARD_REG_BIT (reload_reg_used, regno)); |
546b63fb | 5043 | |
893bc853 RK |
5044 | case RELOAD_FOR_OPADDR_ADDR: |
5045 | for (i = 0; i < reload_n_operands; i++) | |
5046 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 5047 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
893bc853 RK |
5048 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
5049 | return 0; | |
5050 | ||
2af88768 GK |
5051 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
5052 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
5053 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
893bc853 | 5054 | |
546b63fb | 5055 | case RELOAD_FOR_INSN: |
893bc853 | 5056 | /* These conflict with other outputs with RELOAD_OTHER. So |
546b63fb RK |
5057 | we need only check for output addresses. */ |
5058 | ||
d1d18b46 | 5059 | opnum = reload_n_operands; |
546b63fb | 5060 | |
0f41302f | 5061 | /* ... fall through ... */ |
546b63fb | 5062 | |
32131a9c | 5063 | case RELOAD_FOR_OUTPUT: |
546b63fb | 5064 | case RELOAD_FOR_OUTPUT_ADDRESS: |
47c8cf91 | 5065 | case RELOAD_FOR_OUTADDR_ADDRESS: |
546b63fb | 5066 | /* We already know these can't conflict with a later output. So the |
d1d18b46 DJ |
5067 | only thing to check are later output addresses. |
5068 | Note that multiple output operands are emitted in reverse order, | |
5069 | so the conflicting ones are those with lower indices. */ | |
5070 | for (i = 0; i < opnum; i++) | |
47c8cf91 ILT |
5071 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
5072 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
5073 | return 0; |
5074 | ||
32131a9c | 5075 | return 1; |
546b63fb | 5076 | |
41374e13 NS |
5077 | default: |
5078 | gcc_unreachable (); | |
5079 | } | |
32131a9c | 5080 | } |
fb959f72 RS |
5081 | |
5082 | /* Like reload_reg_reaches_end_p, but check that the condition holds for | |
5083 | every register in the range [REGNO, REGNO + NREGS). */ | |
5084 | ||
5085 | static bool | |
5086 | reload_regs_reach_end_p (unsigned int regno, int nregs, | |
5087 | int opnum, enum reload_type type) | |
5088 | { | |
5089 | int i; | |
5090 | ||
5091 | for (i = 0; i < nregs; i++) | |
5092 | if (!reload_reg_reaches_end_p (regno + i, opnum, type)) | |
5093 | return false; | |
5094 | return true; | |
5095 | } | |
32131a9c | 5096 | \f |
d2c9375a DD |
5097 | |
5098 | /* Returns whether R1 and R2 are uniquely chained: the value of one | |
5099 | is used by the other, and that value is not used by any other | |
5100 | reload for this insn. This is used to partially undo the decision | |
5101 | made in find_reloads when in the case of multiple | |
5102 | RELOAD_FOR_OPERAND_ADDRESS reloads it converts all | |
5103 | RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS | |
5104 | reloads. This code tries to avoid the conflict created by that | |
5105 | change. It might be cleaner to explicitly keep track of which | |
5106 | RELOAD_FOR_OPADDR_ADDR reload is associated with which | |
5107 | RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect | |
5108 | this after the fact. */ | |
5109 | static bool | |
5110 | reloads_unique_chain_p (int r1, int r2) | |
5111 | { | |
5112 | int i; | |
5113 | ||
5114 | /* We only check input reloads. */ | |
5115 | if (! rld[r1].in || ! rld[r2].in) | |
5116 | return false; | |
5117 | ||
5118 | /* Avoid anything with output reloads. */ | |
5119 | if (rld[r1].out || rld[r2].out) | |
5120 | return false; | |
5121 | ||
5122 | /* "chained" means one reload is a component of the other reload, | |
5123 | not the same as the other reload. */ | |
5124 | if (rld[r1].opnum != rld[r2].opnum | |
5125 | || rtx_equal_p (rld[r1].in, rld[r2].in) | |
5126 | || rld[r1].optional || rld[r2].optional | |
5127 | || ! (reg_mentioned_p (rld[r1].in, rld[r2].in) | |
5128 | || reg_mentioned_p (rld[r2].in, rld[r1].in))) | |
5129 | return false; | |
5130 | ||
5131 | for (i = 0; i < n_reloads; i ++) | |
5132 | /* Look for input reloads that aren't our two */ | |
5133 | if (i != r1 && i != r2 && rld[i].in) | |
5134 | { | |
5135 | /* If our reload is mentioned at all, it isn't a simple chain. */ | |
5136 | if (reg_mentioned_p (rld[r1].in, rld[i].in)) | |
5137 | return false; | |
5138 | } | |
5139 | return true; | |
5140 | } | |
5141 | ||
058e97ec VM |
5142 | |
5143 | /* The recursive function change all occurrences of WHAT in *WHERE | |
5144 | onto REPL. */ | |
5145 | static void | |
5146 | substitute (rtx *where, const_rtx what, rtx repl) | |
5147 | { | |
5148 | const char *fmt; | |
5149 | int i; | |
5150 | enum rtx_code code; | |
5151 | ||
5152 | if (*where == 0) | |
5153 | return; | |
5154 | ||
5155 | if (*where == what || rtx_equal_p (*where, what)) | |
5156 | { | |
5157 | *where = repl; | |
5158 | return; | |
5159 | } | |
5160 | ||
5161 | code = GET_CODE (*where); | |
5162 | fmt = GET_RTX_FORMAT (code); | |
5163 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5164 | { | |
5165 | if (fmt[i] == 'E') | |
5166 | { | |
5167 | int j; | |
5168 | ||
5169 | for (j = XVECLEN (*where, i) - 1; j >= 0; j--) | |
5170 | substitute (&XVECEXP (*where, i, j), what, repl); | |
5171 | } | |
5172 | else if (fmt[i] == 'e') | |
5173 | substitute (&XEXP (*where, i), what, repl); | |
5174 | } | |
5175 | } | |
5176 | ||
5177 | /* The function returns TRUE if chain of reload R1 and R2 (in any | |
5178 | order) can be evaluated without usage of intermediate register for | |
5179 | the reload containing another reload. It is important to see | |
5180 | gen_reload to understand what the function is trying to do. As an | |
5181 | example, let us have reload chain | |
5182 | ||
5183 | r2: const | |
5184 | r1: <something> + const | |
5185 | ||
5186 | and reload R2 got reload reg HR. The function returns true if | |
5187 | there is a correct insn HR = HR + <something>. Otherwise, | |
5188 | gen_reload will use intermediate register (and this is the reload | |
5189 | reg for R1) to reload <something>. | |
5190 | ||
5191 | We need this function to find a conflict for chain reloads. In our | |
5192 | example, if HR = HR + <something> is incorrect insn, then we cannot | |
5193 | use HR as a reload register for R2. If we do use it then we get a | |
5194 | wrong code: | |
5195 | ||
5196 | HR = const | |
5197 | HR = <something> | |
5198 | HR = HR + HR | |
5199 | ||
5200 | */ | |
5201 | static bool | |
5202 | gen_reload_chain_without_interm_reg_p (int r1, int r2) | |
5203 | { | |
5204 | bool result; | |
5205 | int regno, n, code; | |
5206 | rtx out, in, tem, insn; | |
5207 | rtx last = get_last_insn (); | |
5208 | ||
5209 | /* Make r2 a component of r1. */ | |
5210 | if (reg_mentioned_p (rld[r1].in, rld[r2].in)) | |
5211 | { | |
5212 | n = r1; | |
5213 | r1 = r2; | |
5214 | r2 = n; | |
5215 | } | |
5216 | gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in)); | |
5217 | regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno; | |
5218 | gcc_assert (regno >= 0); | |
5219 | out = gen_rtx_REG (rld[r1].mode, regno); | |
5220 | in = copy_rtx (rld[r1].in); | |
5221 | substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno)); | |
5222 | ||
5223 | /* If IN is a paradoxical SUBREG, remove it and try to put the | |
5224 | opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ | |
5225 | if (GET_CODE (in) == SUBREG | |
5226 | && (GET_MODE_SIZE (GET_MODE (in)) | |
5227 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
5228 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) | |
5229 | in = SUBREG_REG (in), out = tem; | |
5230 | ||
5231 | if (GET_CODE (in) == PLUS | |
5232 | && (REG_P (XEXP (in, 0)) | |
5233 | || GET_CODE (XEXP (in, 0)) == SUBREG | |
5234 | || MEM_P (XEXP (in, 0))) | |
5235 | && (REG_P (XEXP (in, 1)) | |
5236 | || GET_CODE (XEXP (in, 1)) == SUBREG | |
5237 | || CONSTANT_P (XEXP (in, 1)) | |
5238 | || MEM_P (XEXP (in, 1)))) | |
5239 | { | |
5240 | insn = emit_insn (gen_rtx_SET (VOIDmode, out, in)); | |
5241 | code = recog_memoized (insn); | |
5242 | result = false; | |
5243 | ||
5244 | if (code >= 0) | |
5245 | { | |
5246 | extract_insn (insn); | |
5247 | /* We want constrain operands to treat this insn strictly in | |
5248 | its validity determination, i.e., the way it would after | |
5249 | reload has completed. */ | |
5250 | result = constrain_operands (1); | |
5251 | } | |
5252 | ||
5253 | delete_insns_since (last); | |
5254 | return result; | |
5255 | } | |
5256 | ||
5257 | /* It looks like other cases in gen_reload are not possible for | |
5258 | chain reloads or do need an intermediate hard registers. */ | |
5259 | return true; | |
5260 | } | |
5261 | ||
351aa1c1 RK |
5262 | /* Return 1 if the reloads denoted by R1 and R2 cannot share a register. |
5263 | Return 0 otherwise. | |
5264 | ||
5265 | This function uses the same algorithm as reload_reg_free_p above. */ | |
5266 | ||
bf9a0db3 | 5267 | static int |
0c20a65f | 5268 | reloads_conflict (int r1, int r2) |
351aa1c1 | 5269 | { |
eceef4c9 BS |
5270 | enum reload_type r1_type = rld[r1].when_needed; |
5271 | enum reload_type r2_type = rld[r2].when_needed; | |
5272 | int r1_opnum = rld[r1].opnum; | |
5273 | int r2_opnum = rld[r2].opnum; | |
351aa1c1 | 5274 | |
2edc8d65 RK |
5275 | /* RELOAD_OTHER conflicts with everything. */ |
5276 | if (r2_type == RELOAD_OTHER) | |
351aa1c1 RK |
5277 | return 1; |
5278 | ||
5279 | /* Otherwise, check conflicts differently for each type. */ | |
5280 | ||
5281 | switch (r1_type) | |
5282 | { | |
5283 | case RELOAD_FOR_INPUT: | |
05d10675 | 5284 | return (r2_type == RELOAD_FOR_INSN |
351aa1c1 | 5285 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS |
893bc853 | 5286 | || r2_type == RELOAD_FOR_OPADDR_ADDR |
351aa1c1 | 5287 | || r2_type == RELOAD_FOR_INPUT |
47c8cf91 ILT |
5288 | || ((r2_type == RELOAD_FOR_INPUT_ADDRESS |
5289 | || r2_type == RELOAD_FOR_INPADDR_ADDRESS) | |
5290 | && r2_opnum > r1_opnum)); | |
351aa1c1 RK |
5291 | |
5292 | case RELOAD_FOR_INPUT_ADDRESS: | |
5293 | return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) | |
5294 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
5295 | ||
47c8cf91 ILT |
5296 | case RELOAD_FOR_INPADDR_ADDRESS: |
5297 | return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) | |
5298 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
5299 | ||
351aa1c1 RK |
5300 | case RELOAD_FOR_OUTPUT_ADDRESS: |
5301 | return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 5302 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
351aa1c1 | 5303 | |
47c8cf91 ILT |
5304 | case RELOAD_FOR_OUTADDR_ADDRESS: |
5305 | return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 5306 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
47c8cf91 | 5307 | |
351aa1c1 RK |
5308 | case RELOAD_FOR_OPERAND_ADDRESS: |
5309 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN | |
d2c9375a | 5310 | || (r2_type == RELOAD_FOR_OPERAND_ADDRESS |
058e97ec VM |
5311 | && (!reloads_unique_chain_p (r1, r2) |
5312 | || !gen_reload_chain_without_interm_reg_p (r1, r2)))); | |
351aa1c1 | 5313 | |
893bc853 | 5314 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 | 5315 | return (r2_type == RELOAD_FOR_INPUT |
a94ce333 | 5316 | || r2_type == RELOAD_FOR_OPADDR_ADDR); |
893bc853 | 5317 | |
351aa1c1 RK |
5318 | case RELOAD_FOR_OUTPUT: |
5319 | return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT | |
47c8cf91 ILT |
5320 | || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS |
5321 | || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) | |
d1d18b46 | 5322 | && r2_opnum >= r1_opnum)); |
351aa1c1 RK |
5323 | |
5324 | case RELOAD_FOR_INSN: | |
5325 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT | |
5326 | || r2_type == RELOAD_FOR_INSN | |
5327 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); | |
5328 | ||
5329 | case RELOAD_FOR_OTHER_ADDRESS: | |
5330 | return r2_type == RELOAD_FOR_OTHER_ADDRESS; | |
5331 | ||
adab4fc5 | 5332 | case RELOAD_OTHER: |
2edc8d65 | 5333 | return 1; |
adab4fc5 | 5334 | |
351aa1c1 | 5335 | default: |
41374e13 | 5336 | gcc_unreachable (); |
351aa1c1 RK |
5337 | } |
5338 | } | |
5339 | \f | |
32131a9c RK |
5340 | /* Indexed by reload number, 1 if incoming value |
5341 | inherited from previous insns. */ | |
cf0fa607 | 5342 | static char reload_inherited[MAX_RELOADS]; |
32131a9c RK |
5343 | |
5344 | /* For an inherited reload, this is the insn the reload was inherited from, | |
5345 | if we know it. Otherwise, this is 0. */ | |
cf0fa607 | 5346 | static rtx reload_inheritance_insn[MAX_RELOADS]; |
32131a9c | 5347 | |
40f03658 | 5348 | /* If nonzero, this is a place to get the value of the reload, |
32131a9c | 5349 | rather than using reload_in. */ |
cf0fa607 | 5350 | static rtx reload_override_in[MAX_RELOADS]; |
32131a9c | 5351 | |
e6e52be0 R |
5352 | /* For each reload, the hard register number of the register used, |
5353 | or -1 if we did not need a register for this reload. */ | |
cf0fa607 | 5354 | static int reload_spill_index[MAX_RELOADS]; |
32131a9c | 5355 | |
fb959f72 RS |
5356 | /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */ |
5357 | static rtx reload_reg_rtx_for_input[MAX_RELOADS]; | |
5358 | ||
5359 | /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */ | |
5360 | static rtx reload_reg_rtx_for_output[MAX_RELOADS]; | |
5361 | ||
304a22dd R |
5362 | /* Subroutine of free_for_value_p, used to check a single register. |
5363 | START_REGNO is the starting regno of the full reload register | |
5364 | (possibly comprising multiple hard registers) that we are considering. */ | |
f5470689 | 5365 | |
6e684430 | 5366 | static int |
0c20a65f AJ |
5367 | reload_reg_free_for_value_p (int start_regno, int regno, int opnum, |
5368 | enum reload_type type, rtx value, rtx out, | |
5369 | int reloadnum, int ignore_address_reloads) | |
6e684430 R |
5370 | { |
5371 | int time1; | |
09a308fe R |
5372 | /* Set if we see an input reload that must not share its reload register |
5373 | with any new earlyclobber, but might otherwise share the reload | |
5374 | register with an output or input-output reload. */ | |
5375 | int check_earlyclobber = 0; | |
6e684430 | 5376 | int i; |
dfe96118 R |
5377 | int copy = 0; |
5378 | ||
9e3a9cf2 | 5379 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) |
dc8842bf AH |
5380 | return 0; |
5381 | ||
dfe96118 R |
5382 | if (out == const0_rtx) |
5383 | { | |
5384 | copy = 1; | |
5385 | out = NULL_RTX; | |
5386 | } | |
6e684430 R |
5387 | |
5388 | /* We use some pseudo 'time' value to check if the lifetimes of the | |
5389 | new register use would overlap with the one of a previous reload | |
5390 | that is not read-only or uses a different value. | |
5391 | The 'time' used doesn't have to be linear in any shape or form, just | |
5392 | monotonic. | |
5393 | Some reload types use different 'buckets' for each operand. | |
5394 | So there are MAX_RECOG_OPERANDS different time values for each | |
cecbf6e2 R |
5395 | such reload type. |
5396 | We compute TIME1 as the time when the register for the prospective | |
5397 | new reload ceases to be live, and TIME2 for each existing | |
5398 | reload as the time when that the reload register of that reload | |
5399 | becomes live. | |
5400 | Where there is little to be gained by exact lifetime calculations, | |
5401 | we just make conservative assumptions, i.e. a longer lifetime; | |
5402 | this is done in the 'default:' cases. */ | |
6e684430 R |
5403 | switch (type) |
5404 | { | |
5405 | case RELOAD_FOR_OTHER_ADDRESS: | |
203588e7 | 5406 | /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ |
c2b4b171 | 5407 | time1 = copy ? 0 : 1; |
6e684430 | 5408 | break; |
dfe96118 R |
5409 | case RELOAD_OTHER: |
5410 | time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; | |
5411 | break; | |
05d10675 BS |
5412 | /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, |
5413 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , | |
5414 | respectively, to the time values for these, we get distinct time | |
5415 | values. To get distinct time values for each operand, we have to | |
5416 | multiply opnum by at least three. We round that up to four because | |
5417 | multiply by four is often cheaper. */ | |
6e684430 | 5418 | case RELOAD_FOR_INPADDR_ADDRESS: |
dfe96118 | 5419 | time1 = opnum * 4 + 2; |
6e684430 R |
5420 | break; |
5421 | case RELOAD_FOR_INPUT_ADDRESS: | |
dfe96118 R |
5422 | time1 = opnum * 4 + 3; |
5423 | break; | |
5424 | case RELOAD_FOR_INPUT: | |
5425 | /* All RELOAD_FOR_INPUT reloads remain live till the instruction | |
5426 | executes (inclusive). */ | |
5427 | time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; | |
6e684430 | 5428 | break; |
cb2afeb3 | 5429 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 BS |
5430 | /* opnum * 4 + 4 |
5431 | <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ | |
cb2afeb3 R |
5432 | time1 = MAX_RECOG_OPERANDS * 4 + 1; |
5433 | break; | |
5434 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5435 | /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn | |
5436 | is executed. */ | |
dfe96118 R |
5437 | time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; |
5438 | break; | |
5439 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
5440 | time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; | |
6e684430 | 5441 | break; |
6e684430 | 5442 | case RELOAD_FOR_OUTPUT_ADDRESS: |
dfe96118 | 5443 | time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; |
6e684430 R |
5444 | break; |
5445 | default: | |
dfe96118 | 5446 | time1 = MAX_RECOG_OPERANDS * 5 + 5; |
6e684430 R |
5447 | } |
5448 | ||
5449 | for (i = 0; i < n_reloads; i++) | |
5450 | { | |
eceef4c9 | 5451 | rtx reg = rld[i].reg_rtx; |
f8cfc6aa | 5452 | if (reg && REG_P (reg) |
6e684430 | 5453 | && ((unsigned) regno - true_regnum (reg) |
66fd46b6 | 5454 | <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1) |
f5470689 | 5455 | && i != reloadnum) |
6e684430 | 5456 | { |
304a22dd R |
5457 | rtx other_input = rld[i].in; |
5458 | ||
5459 | /* If the other reload loads the same input value, that | |
5460 | will not cause a conflict only if it's loading it into | |
5461 | the same register. */ | |
5462 | if (true_regnum (reg) != start_regno) | |
5463 | other_input = NULL_RTX; | |
5464 | if (! other_input || ! rtx_equal_p (other_input, value) | |
eceef4c9 | 5465 | || rld[i].out || out) |
6e684430 | 5466 | { |
09a308fe | 5467 | int time2; |
eceef4c9 | 5468 | switch (rld[i].when_needed) |
f5470689 R |
5469 | { |
5470 | case RELOAD_FOR_OTHER_ADDRESS: | |
5471 | time2 = 0; | |
5472 | break; | |
5473 | case RELOAD_FOR_INPADDR_ADDRESS: | |
cb2afeb3 R |
5474 | /* find_reloads makes sure that a |
5475 | RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used | |
5476 | by at most one - the first - | |
5477 | RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the | |
5478 | address reload is inherited, the address address reload | |
5479 | goes away, so we can ignore this conflict. */ | |
dfe96118 R |
5480 | if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 |
5481 | && ignore_address_reloads | |
5482 | /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. | |
5483 | Then the address address is still needed to store | |
5484 | back the new address. */ | |
eceef4c9 | 5485 | && ! rld[reloadnum].out) |
cb2afeb3 | 5486 | continue; |
dfe96118 R |
5487 | /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its |
5488 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS | |
5489 | reloads go away. */ | |
eceef4c9 | 5490 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 R |
5491 | && ignore_address_reloads |
5492 | /* Unless we are reloading an auto_inc expression. */ | |
eceef4c9 | 5493 | && ! rld[reloadnum].out) |
dfe96118 | 5494 | continue; |
eceef4c9 | 5495 | time2 = rld[i].opnum * 4 + 2; |
f5470689 R |
5496 | break; |
5497 | case RELOAD_FOR_INPUT_ADDRESS: | |
eceef4c9 | 5498 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 | 5499 | && ignore_address_reloads |
eceef4c9 | 5500 | && ! rld[reloadnum].out) |
dfe96118 | 5501 | continue; |
eceef4c9 | 5502 | time2 = rld[i].opnum * 4 + 3; |
f5470689 R |
5503 | break; |
5504 | case RELOAD_FOR_INPUT: | |
eceef4c9 | 5505 | time2 = rld[i].opnum * 4 + 4; |
09a308fe | 5506 | check_earlyclobber = 1; |
f5470689 | 5507 | break; |
eceef4c9 | 5508 | /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 |
05d10675 | 5509 | == MAX_RECOG_OPERAND * 4 */ |
cb2afeb3 | 5510 | case RELOAD_FOR_OPADDR_ADDR: |
dfe96118 R |
5511 | if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 |
5512 | && ignore_address_reloads | |
eceef4c9 | 5513 | && ! rld[reloadnum].out) |
cb2afeb3 | 5514 | continue; |
dfe96118 | 5515 | time2 = MAX_RECOG_OPERANDS * 4 + 1; |
cb2afeb3 R |
5516 | break; |
5517 | case RELOAD_FOR_OPERAND_ADDRESS: | |
dfe96118 | 5518 | time2 = MAX_RECOG_OPERANDS * 4 + 2; |
09a308fe | 5519 | check_earlyclobber = 1; |
dfe96118 R |
5520 | break; |
5521 | case RELOAD_FOR_INSN: | |
5522 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
cb2afeb3 | 5523 | break; |
f5470689 | 5524 | case RELOAD_FOR_OUTPUT: |
05d10675 BS |
5525 | /* All RELOAD_FOR_OUTPUT reloads become live just after the |
5526 | instruction is executed. */ | |
dfe96118 | 5527 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
f5470689 | 5528 | break; |
05d10675 BS |
5529 | /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with |
5530 | the RELOAD_FOR_OUTPUT reloads, so assign it the same time | |
5531 | value. */ | |
cb2afeb3 | 5532 | case RELOAD_FOR_OUTADDR_ADDRESS: |
dfe96118 R |
5533 | if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 |
5534 | && ignore_address_reloads | |
eceef4c9 | 5535 | && ! rld[reloadnum].out) |
cb2afeb3 | 5536 | continue; |
eceef4c9 | 5537 | time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; |
dfe96118 | 5538 | break; |
f5470689 | 5539 | case RELOAD_FOR_OUTPUT_ADDRESS: |
eceef4c9 | 5540 | time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; |
f5470689 R |
5541 | break; |
5542 | case RELOAD_OTHER: | |
dfe96118 R |
5543 | /* If there is no conflict in the input part, handle this |
5544 | like an output reload. */ | |
304a22dd | 5545 | if (! rld[i].in || rtx_equal_p (other_input, value)) |
f5470689 | 5546 | { |
dfe96118 | 5547 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
57850c85 | 5548 | /* Earlyclobbered outputs must conflict with inputs. */ |
09a308fe R |
5549 | if (earlyclobber_operand_p (rld[i].out)) |
5550 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
1d7254c5 | 5551 | |
f5470689 R |
5552 | break; |
5553 | } | |
dfe96118 R |
5554 | time2 = 1; |
5555 | /* RELOAD_OTHER might be live beyond instruction execution, | |
5556 | but this is not obvious when we set time2 = 1. So check | |
5557 | here if there might be a problem with the new reload | |
5558 | clobbering the register used by the RELOAD_OTHER. */ | |
5559 | if (out) | |
5560 | return 0; | |
5561 | break; | |
f5470689 | 5562 | default: |
dfe96118 | 5563 | return 0; |
f5470689 | 5564 | } |
25963977 | 5565 | if ((time1 >= time2 |
eceef4c9 | 5566 | && (! rld[i].in || rld[i].out |
304a22dd | 5567 | || ! rtx_equal_p (other_input, value))) |
eceef4c9 | 5568 | || (out && rld[reloadnum].out_reg |
701d55e8 | 5569 | && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) |
f5470689 | 5570 | return 0; |
6e684430 | 5571 | } |
6e684430 R |
5572 | } |
5573 | } | |
09a308fe R |
5574 | |
5575 | /* Earlyclobbered outputs must conflict with inputs. */ | |
5576 | if (check_earlyclobber && out && earlyclobber_operand_p (out)) | |
5577 | return 0; | |
5578 | ||
6e684430 R |
5579 | return 1; |
5580 | } | |
5581 | ||
c02cad8f BS |
5582 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
5583 | needed for the part of the insn specified by OPNUM and TYPE, | |
5584 | may be used to load VALUE into it. | |
5585 | ||
5586 | MODE is the mode in which the register is used, this is needed to | |
5587 | determine how many hard regs to test. | |
5588 | ||
5589 | Other read-only reloads with the same value do not conflict | |
40f03658 | 5590 | unless OUT is nonzero and these other reloads have to live while |
c02cad8f BS |
5591 | output reloads live. |
5592 | If OUT is CONST0_RTX, this is a special case: it means that the | |
5593 | test should not be for using register REGNO as reload register, but | |
5594 | for copying from register REGNO into the reload register. | |
5595 | ||
5596 | RELOADNUM is the number of the reload we want to load this value for; | |
5597 | a reload does not conflict with itself. | |
5598 | ||
5599 | When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with | |
5600 | reloads that load an address for the very reload we are considering. | |
5601 | ||
5602 | The caller has to make sure that there is no conflict with the return | |
5603 | register. */ | |
5604 | ||
5605 | static int | |
0c20a65f AJ |
5606 | free_for_value_p (int regno, enum machine_mode mode, int opnum, |
5607 | enum reload_type type, rtx value, rtx out, int reloadnum, | |
5608 | int ignore_address_reloads) | |
c02cad8f | 5609 | { |
66fd46b6 | 5610 | int nregs = hard_regno_nregs[regno][mode]; |
c02cad8f | 5611 | while (nregs-- > 0) |
304a22dd R |
5612 | if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type, |
5613 | value, out, reloadnum, | |
5614 | ignore_address_reloads)) | |
c02cad8f BS |
5615 | return 0; |
5616 | return 1; | |
5617 | } | |
5618 | ||
86caf04d | 5619 | /* Return nonzero if the rtx X is invariant over the current function. */ |
0e61db61 NS |
5620 | /* ??? Actually, the places where we use this expect exactly what is |
5621 | tested here, and not everything that is function invariant. In | |
5622 | particular, the frame pointer and arg pointer are special cased; | |
5623 | pic_offset_table_rtx is not, and we must not spill these things to | |
5624 | memory. */ | |
86caf04d | 5625 | |
5fffc382 | 5626 | int |
4f588890 | 5627 | function_invariant_p (const_rtx x) |
86caf04d PB |
5628 | { |
5629 | if (CONSTANT_P (x)) | |
5630 | return 1; | |
5631 | if (x == frame_pointer_rtx || x == arg_pointer_rtx) | |
5632 | return 1; | |
5633 | if (GET_CODE (x) == PLUS | |
5634 | && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx) | |
5635 | && CONSTANT_P (XEXP (x, 1))) | |
5636 | return 1; | |
5637 | return 0; | |
5638 | } | |
5639 | ||
ff6534ad BS |
5640 | /* Determine whether the reload reg X overlaps any rtx'es used for |
5641 | overriding inheritance. Return nonzero if so. */ | |
5642 | ||
5643 | static int | |
0c20a65f | 5644 | conflicts_with_override (rtx x) |
ff6534ad BS |
5645 | { |
5646 | int i; | |
5647 | for (i = 0; i < n_reloads; i++) | |
5648 | if (reload_override_in[i] | |
5649 | && reg_overlap_mentioned_p (x, reload_override_in[i])) | |
5650 | return 1; | |
5651 | return 0; | |
5652 | } | |
5653 | \f | |
67e61fe7 BS |
5654 | /* Give an error message saying we failed to find a reload for INSN, |
5655 | and clear out reload R. */ | |
5656 | static void | |
0c20a65f | 5657 | failed_reload (rtx insn, int r) |
67e61fe7 BS |
5658 | { |
5659 | if (asm_noperands (PATTERN (insn)) < 0) | |
5660 | /* It's the compiler's fault. */ | |
1f978f5f | 5661 | fatal_insn ("could not find a spill register", insn); |
67e61fe7 BS |
5662 | |
5663 | /* It's the user's fault; the operand's mode and constraint | |
5664 | don't match. Disable this reload so we don't crash in final. */ | |
5665 | error_for_asm (insn, | |
971801ff | 5666 | "%<asm%> operand constraint incompatible with operand size"); |
67e61fe7 BS |
5667 | rld[r].in = 0; |
5668 | rld[r].out = 0; | |
5669 | rld[r].reg_rtx = 0; | |
5670 | rld[r].optional = 1; | |
5671 | rld[r].secondary_p = 1; | |
5672 | } | |
5673 | ||
5674 | /* I is the index in SPILL_REG_RTX of the reload register we are to allocate | |
5675 | for reload R. If it's valid, get an rtx for it. Return nonzero if | |
5676 | successful. */ | |
5677 | static int | |
0c20a65f | 5678 | set_reload_reg (int i, int r) |
67e61fe7 BS |
5679 | { |
5680 | int regno; | |
5681 | rtx reg = spill_reg_rtx[i]; | |
5682 | ||
5683 | if (reg == 0 || GET_MODE (reg) != rld[r].mode) | |
5684 | spill_reg_rtx[i] = reg | |
5685 | = gen_rtx_REG (rld[r].mode, spill_regs[i]); | |
5686 | ||
5687 | regno = true_regnum (reg); | |
5688 | ||
5689 | /* Detect when the reload reg can't hold the reload mode. | |
5690 | This used to be one `if', but Sequent compiler can't handle that. */ | |
5691 | if (HARD_REGNO_MODE_OK (regno, rld[r].mode)) | |
5692 | { | |
5693 | enum machine_mode test_mode = VOIDmode; | |
5694 | if (rld[r].in) | |
5695 | test_mode = GET_MODE (rld[r].in); | |
5696 | /* If rld[r].in has VOIDmode, it means we will load it | |
5697 | in whatever mode the reload reg has: to wit, rld[r].mode. | |
5698 | We have already tested that for validity. */ | |
5699 | /* Aside from that, we need to test that the expressions | |
5700 | to reload from or into have modes which are valid for this | |
5701 | reload register. Otherwise the reload insns would be invalid. */ | |
5702 | if (! (rld[r].in != 0 && test_mode != VOIDmode | |
5703 | && ! HARD_REGNO_MODE_OK (regno, test_mode))) | |
5704 | if (! (rld[r].out != 0 | |
5705 | && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out)))) | |
5706 | { | |
5707 | /* The reg is OK. */ | |
5708 | last_spill_reg = i; | |
5709 | ||
5710 | /* Mark as in use for this insn the reload regs we use | |
5711 | for this. */ | |
5712 | mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, | |
5713 | rld[r].when_needed, rld[r].mode); | |
5714 | ||
5715 | rld[r].reg_rtx = reg; | |
5716 | reload_spill_index[r] = spill_regs[i]; | |
5717 | return 1; | |
5718 | } | |
5719 | } | |
5720 | return 0; | |
5721 | } | |
5722 | ||
32131a9c | 5723 | /* Find a spill register to use as a reload register for reload R. |
40f03658 | 5724 | LAST_RELOAD is nonzero if this is the last reload for the insn being |
32131a9c RK |
5725 | processed. |
5726 | ||
eceef4c9 | 5727 | Set rld[R].reg_rtx to the register allocated. |
32131a9c | 5728 | |
f5d8c9f4 BS |
5729 | We return 1 if successful, or 0 if we couldn't find a spill reg and |
5730 | we didn't change anything. */ | |
32131a9c RK |
5731 | |
5732 | static int | |
0c20a65f AJ |
5733 | allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r, |
5734 | int last_reload) | |
32131a9c | 5735 | { |
67e61fe7 | 5736 | int i, pass, count; |
32131a9c RK |
5737 | |
5738 | /* If we put this reload ahead, thinking it is a group, | |
5739 | then insist on finding a group. Otherwise we can grab a | |
a8fdc208 | 5740 | reg that some other reload needs. |
32131a9c RK |
5741 | (That can happen when we have a 68000 DATA_OR_FP_REG |
5742 | which is a group of data regs or one fp reg.) | |
5743 | We need not be so restrictive if there are no more reloads | |
5744 | for this insn. | |
5745 | ||
5746 | ??? Really it would be nicer to have smarter handling | |
5747 | for that kind of reg class, where a problem like this is normal. | |
5748 | Perhaps those classes should be avoided for reloading | |
5749 | by use of more alternatives. */ | |
5750 | ||
8ec450a4 | 5751 | int force_group = rld[r].nregs > 1 && ! last_reload; |
32131a9c RK |
5752 | |
5753 | /* If we want a single register and haven't yet found one, | |
5754 | take any reg in the right class and not in use. | |
5755 | If we want a consecutive group, here is where we look for it. | |
5756 | ||
5757 | We use two passes so we can first look for reload regs to | |
5758 | reuse, which are already in use for other reloads in this insn, | |
5759 | and only then use additional registers. | |
5760 | I think that maximizing reuse is needed to make sure we don't | |
5761 | run out of reload regs. Suppose we have three reloads, and | |
5762 | reloads A and B can share regs. These need two regs. | |
5763 | Suppose A and B are given different regs. | |
5764 | That leaves none for C. */ | |
5765 | for (pass = 0; pass < 2; pass++) | |
5766 | { | |
5767 | /* I is the index in spill_regs. | |
5768 | We advance it round-robin between insns to use all spill regs | |
5769 | equally, so that inherited reloads have a chance | |
f5d8c9f4 BS |
5770 | of leapfrogging each other. */ |
5771 | ||
5772 | i = last_spill_reg; | |
05d10675 | 5773 | |
a5339699 | 5774 | for (count = 0; count < n_spills; count++) |
32131a9c | 5775 | { |
48c54229 | 5776 | int rclass = (int) rld[r].rclass; |
03acd8f8 | 5777 | int regnum; |
32131a9c | 5778 | |
03acd8f8 BS |
5779 | i++; |
5780 | if (i >= n_spills) | |
5781 | i -= n_spills; | |
5782 | regnum = spill_regs[i]; | |
32131a9c | 5783 | |
eceef4c9 BS |
5784 | if ((reload_reg_free_p (regnum, rld[r].opnum, |
5785 | rld[r].when_needed) | |
5786 | || (rld[r].in | |
05d10675 BS |
5787 | /* We check reload_reg_used to make sure we |
5788 | don't clobber the return register. */ | |
03acd8f8 | 5789 | && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) |
c02cad8f BS |
5790 | && free_for_value_p (regnum, rld[r].mode, rld[r].opnum, |
5791 | rld[r].when_needed, rld[r].in, | |
5792 | rld[r].out, r, 1))) | |
55d796da | 5793 | && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum) |
8ec450a4 | 5794 | && HARD_REGNO_MODE_OK (regnum, rld[r].mode) |
be7ae2a4 RK |
5795 | /* Look first for regs to share, then for unshared. But |
5796 | don't share regs used for inherited reloads; they are | |
5797 | the ones we want to preserve. */ | |
5798 | && (pass | |
5799 | || (TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
03acd8f8 | 5800 | regnum) |
be7ae2a4 | 5801 | && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, |
03acd8f8 | 5802 | regnum)))) |
32131a9c | 5803 | { |
66fd46b6 | 5804 | int nr = hard_regno_nregs[regnum][rld[r].mode]; |
32131a9c RK |
5805 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG |
5806 | (on 68000) got us two FP regs. If NR is 1, | |
5807 | we would reject both of them. */ | |
5808 | if (force_group) | |
67e61fe7 | 5809 | nr = rld[r].nregs; |
32131a9c RK |
5810 | /* If we need only one reg, we have already won. */ |
5811 | if (nr == 1) | |
5812 | { | |
5813 | /* But reject a single reg if we demand a group. */ | |
5814 | if (force_group) | |
5815 | continue; | |
5816 | break; | |
5817 | } | |
5818 | /* Otherwise check that as many consecutive regs as we need | |
f5d8c9f4 BS |
5819 | are available here. */ |
5820 | while (nr > 1) | |
5821 | { | |
5822 | int regno = regnum + nr - 1; | |
55d796da | 5823 | if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno) |
f5d8c9f4 BS |
5824 | && spill_reg_order[regno] >= 0 |
5825 | && reload_reg_free_p (regno, rld[r].opnum, | |
5826 | rld[r].when_needed))) | |
5827 | break; | |
5828 | nr--; | |
5829 | } | |
32131a9c RK |
5830 | if (nr == 1) |
5831 | break; | |
5832 | } | |
5833 | } | |
5834 | ||
5835 | /* If we found something on pass 1, omit pass 2. */ | |
5836 | if (count < n_spills) | |
5837 | break; | |
5838 | } | |
1d7254c5 | 5839 | |
32131a9c | 5840 | /* We should have found a spill register by now. */ |
f5d8c9f4 | 5841 | if (count >= n_spills) |
32131a9c RK |
5842 | return 0; |
5843 | ||
f5d8c9f4 BS |
5844 | /* I is the index in SPILL_REG_RTX of the reload register we are to |
5845 | allocate. Get an rtx for it and find its register number. */ | |
32131a9c | 5846 | |
f5d8c9f4 | 5847 | return set_reload_reg (i, r); |
32131a9c RK |
5848 | } |
5849 | \f | |
67e61fe7 BS |
5850 | /* Initialize all the tables needed to allocate reload registers. |
5851 | CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX | |
5852 | is the array we use to restore the reg_rtx field for every reload. */ | |
efc9bd41 | 5853 | |
32131a9c | 5854 | static void |
0c20a65f | 5855 | choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx) |
32131a9c | 5856 | { |
67e61fe7 | 5857 | int i; |
32131a9c | 5858 | |
67e61fe7 BS |
5859 | for (i = 0; i < n_reloads; i++) |
5860 | rld[i].reg_rtx = save_reload_reg_rtx[i]; | |
32131a9c | 5861 | |
961192e1 | 5862 | memset (reload_inherited, 0, MAX_RELOADS); |
703ad42b KG |
5863 | memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx)); |
5864 | memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx)); | |
32131a9c RK |
5865 | |
5866 | CLEAR_HARD_REG_SET (reload_reg_used); | |
5867 | CLEAR_HARD_REG_SET (reload_reg_used_at_all); | |
32131a9c | 5868 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); |
893bc853 | 5869 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); |
546b63fb RK |
5870 | CLEAR_HARD_REG_SET (reload_reg_used_in_insn); |
5871 | CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); | |
32131a9c | 5872 | |
f1db3576 JL |
5873 | CLEAR_HARD_REG_SET (reg_used_in_insn); |
5874 | { | |
5875 | HARD_REG_SET tmp; | |
239a0f5b | 5876 | REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); |
f1db3576 | 5877 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b | 5878 | REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); |
f1db3576 | 5879 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b BS |
5880 | compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); |
5881 | compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); | |
f1db3576 | 5882 | } |
efc9bd41 | 5883 | |
546b63fb RK |
5884 | for (i = 0; i < reload_n_operands; i++) |
5885 | { | |
5886 | CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); | |
5887 | CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); | |
5888 | CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); | |
47c8cf91 | 5889 | CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); |
546b63fb | 5890 | CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); |
47c8cf91 | 5891 | CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); |
546b63fb | 5892 | } |
32131a9c | 5893 | |
9e3a9cf2 | 5894 | COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs); |
05d10675 | 5895 | |
67e61fe7 | 5896 | CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); |
32131a9c | 5897 | |
67e61fe7 BS |
5898 | for (i = 0; i < n_reloads; i++) |
5899 | /* If we have already decided to use a certain register, | |
5900 | don't use it in another way. */ | |
5901 | if (rld[i].reg_rtx) | |
5902 | mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, | |
5903 | rld[i].when_needed, rld[i].mode); | |
5904 | } | |
32131a9c | 5905 | |
67e61fe7 BS |
5906 | /* Assign hard reg targets for the pseudo-registers we must reload |
5907 | into hard regs for this insn. | |
5908 | Also output the instructions to copy them in and out of the hard regs. | |
5909 | ||
5910 | For machines with register classes, we are responsible for | |
5911 | finding a reload reg in the proper class. */ | |
5912 | ||
5913 | static void | |
0c20a65f | 5914 | choose_reload_regs (struct insn_chain *chain) |
67e61fe7 BS |
5915 | { |
5916 | rtx insn = chain->insn; | |
b3694847 | 5917 | int i, j; |
770ae6cc | 5918 | unsigned int max_group_size = 1; |
67e61fe7 | 5919 | enum reg_class group_class = NO_REGS; |
f5d8c9f4 | 5920 | int pass, win, inheritance; |
67e61fe7 BS |
5921 | |
5922 | rtx save_reload_reg_rtx[MAX_RELOADS]; | |
32131a9c | 5923 | |
32131a9c RK |
5924 | /* In order to be certain of getting the registers we need, |
5925 | we must sort the reloads into order of increasing register class. | |
5926 | Then our grabbing of reload registers will parallel the process | |
a8fdc208 | 5927 | that provided the reload registers. |
32131a9c RK |
5928 | |
5929 | Also note whether any of the reloads wants a consecutive group of regs. | |
5930 | If so, record the maximum size of the group desired and what | |
5931 | register class contains all the groups needed by this insn. */ | |
5932 | ||
5933 | for (j = 0; j < n_reloads; j++) | |
5934 | { | |
5935 | reload_order[j] = j; | |
374d961c BS |
5936 | if (rld[j].reg_rtx != NULL_RTX) |
5937 | { | |
5938 | gcc_assert (REG_P (rld[j].reg_rtx) | |
5939 | && HARD_REGISTER_P (rld[j].reg_rtx)); | |
5940 | reload_spill_index[j] = REGNO (rld[j].reg_rtx); | |
5941 | } | |
5942 | else | |
5943 | reload_spill_index[j] = -1; | |
32131a9c | 5944 | |
8ec450a4 | 5945 | if (rld[j].nregs > 1) |
32131a9c | 5946 | { |
8ec450a4 | 5947 | max_group_size = MAX (rld[j].nregs, max_group_size); |
770ae6cc | 5948 | group_class |
48c54229 | 5949 | = reg_class_superunion[(int) rld[j].rclass][(int) group_class]; |
32131a9c RK |
5950 | } |
5951 | ||
eceef4c9 | 5952 | save_reload_reg_rtx[j] = rld[j].reg_rtx; |
32131a9c RK |
5953 | } |
5954 | ||
5955 | if (n_reloads > 1) | |
5956 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
5957 | ||
58b1581b RS |
5958 | /* If -O, try first with inheritance, then turning it off. |
5959 | If not -O, don't do inheritance. | |
5960 | Using inheritance when not optimizing leads to paradoxes | |
5961 | with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves | |
5962 | because one side of the comparison might be inherited. */ | |
f5d8c9f4 | 5963 | win = 0; |
58b1581b | 5964 | for (inheritance = optimize > 0; inheritance >= 0; inheritance--) |
32131a9c | 5965 | { |
67e61fe7 BS |
5966 | choose_reload_regs_init (chain, save_reload_reg_rtx); |
5967 | ||
32131a9c RK |
5968 | /* Process the reloads in order of preference just found. |
5969 | Beyond this point, subregs can be found in reload_reg_rtx. | |
5970 | ||
770ae6cc RK |
5971 | This used to look for an existing reloaded home for all of the |
5972 | reloads, and only then perform any new reloads. But that could lose | |
5973 | if the reloads were done out of reg-class order because a later | |
5974 | reload with a looser constraint might have an old home in a register | |
5975 | needed by an earlier reload with a tighter constraint. | |
32131a9c RK |
5976 | |
5977 | To solve this, we make two passes over the reloads, in the order | |
5978 | described above. In the first pass we try to inherit a reload | |
5979 | from a previous insn. If there is a later reload that needs a | |
5980 | class that is a proper subset of the class being processed, we must | |
5981 | also allocate a spill register during the first pass. | |
5982 | ||
5983 | Then make a second pass over the reloads to allocate any reloads | |
5984 | that haven't been given registers yet. */ | |
5985 | ||
5986 | for (j = 0; j < n_reloads; j++) | |
5987 | { | |
b3694847 | 5988 | int r = reload_order[j]; |
8593b745 | 5989 | rtx search_equiv = NULL_RTX; |
32131a9c RK |
5990 | |
5991 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 BS |
5992 | if (rld[r].out == 0 && rld[r].in == 0 |
5993 | && ! rld[r].secondary_p) | |
32131a9c RK |
5994 | continue; |
5995 | ||
b29514ee | 5996 | /* If find_reloads chose to use reload_in or reload_out as a reload |
b080c137 RK |
5997 | register, we don't need to chose one. Otherwise, try even if it |
5998 | found one since we might save an insn if we find the value lying | |
b29514ee R |
5999 | around. |
6000 | Try also when reload_in is a pseudo without a hard reg. */ | |
eceef4c9 BS |
6001 | if (rld[r].in != 0 && rld[r].reg_rtx != 0 |
6002 | && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) | |
6003 | || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) | |
3c0cb5de | 6004 | && !MEM_P (rld[r].in) |
eceef4c9 | 6005 | && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) |
32131a9c RK |
6006 | continue; |
6007 | ||
6008 | #if 0 /* No longer needed for correct operation. | |
6009 | It might give better code, or might not; worth an experiment? */ | |
6010 | /* If this is an optional reload, we can't inherit from earlier insns | |
6011 | until we are sure that any non-optional reloads have been allocated. | |
6012 | The following code takes advantage of the fact that optional reloads | |
6013 | are at the end of reload_order. */ | |
eceef4c9 | 6014 | if (rld[r].optional != 0) |
32131a9c | 6015 | for (i = 0; i < j; i++) |
eceef4c9 BS |
6016 | if ((rld[reload_order[i]].out != 0 |
6017 | || rld[reload_order[i]].in != 0 | |
6018 | || rld[reload_order[i]].secondary_p) | |
6019 | && ! rld[reload_order[i]].optional | |
6020 | && rld[reload_order[i]].reg_rtx == 0) | |
f5d8c9f4 | 6021 | allocate_reload_reg (chain, reload_order[i], 0); |
32131a9c RK |
6022 | #endif |
6023 | ||
6024 | /* First see if this pseudo is already available as reloaded | |
6025 | for a previous insn. We cannot try to inherit for reloads | |
6026 | that are smaller than the maximum number of registers needed | |
6027 | for groups unless the register we would allocate cannot be used | |
6028 | for the groups. | |
6029 | ||
6030 | We could check here to see if this is a secondary reload for | |
6031 | an object that is already in a register of the desired class. | |
6032 | This would avoid the need for the secondary reload register. | |
6033 | But this is complex because we can't easily determine what | |
b080c137 RK |
6034 | objects might want to be loaded via this reload. So let a |
6035 | register be allocated here. In `emit_reload_insns' we suppress | |
6036 | one of the loads in the case described above. */ | |
32131a9c RK |
6037 | |
6038 | if (inheritance) | |
6039 | { | |
ddef6bc7 | 6040 | int byte = 0; |
b3694847 | 6041 | int regno = -1; |
6a651371 | 6042 | enum machine_mode mode = VOIDmode; |
32131a9c | 6043 | |
eceef4c9 | 6044 | if (rld[r].in == 0) |
32131a9c | 6045 | ; |
f8cfc6aa | 6046 | else if (REG_P (rld[r].in)) |
db660765 | 6047 | { |
eceef4c9 BS |
6048 | regno = REGNO (rld[r].in); |
6049 | mode = GET_MODE (rld[r].in); | |
db660765 | 6050 | } |
f8cfc6aa | 6051 | else if (REG_P (rld[r].in_reg)) |
db660765 | 6052 | { |
eceef4c9 BS |
6053 | regno = REGNO (rld[r].in_reg); |
6054 | mode = GET_MODE (rld[r].in_reg); | |
db660765 | 6055 | } |
eceef4c9 | 6056 | else if (GET_CODE (rld[r].in_reg) == SUBREG |
f8cfc6aa | 6057 | && REG_P (SUBREG_REG (rld[r].in_reg))) |
b60a8416 | 6058 | { |
eceef4c9 | 6059 | regno = REGNO (SUBREG_REG (rld[r].in_reg)); |
cb2afeb3 | 6060 | if (regno < FIRST_PSEUDO_REGISTER) |
ddef6bc7 | 6061 | regno = subreg_regno (rld[r].in_reg); |
15447fae RIL |
6062 | else |
6063 | byte = SUBREG_BYTE (rld[r].in_reg); | |
eceef4c9 | 6064 | mode = GET_MODE (rld[r].in_reg); |
cb2afeb3 R |
6065 | } |
6066 | #ifdef AUTO_INC_DEC | |
67f07489 | 6067 | else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC |
f8cfc6aa | 6068 | && REG_P (XEXP (rld[r].in_reg, 0))) |
cb2afeb3 | 6069 | { |
eceef4c9 BS |
6070 | regno = REGNO (XEXP (rld[r].in_reg, 0)); |
6071 | mode = GET_MODE (XEXP (rld[r].in_reg, 0)); | |
6072 | rld[r].out = rld[r].in; | |
b60a8416 | 6073 | } |
cb2afeb3 | 6074 | #endif |
32131a9c RK |
6075 | #if 0 |
6076 | /* This won't work, since REGNO can be a pseudo reg number. | |
6077 | Also, it takes much more hair to keep track of all the things | |
6078 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
eceef4c9 | 6079 | else if (GET_CODE (rld[r].in) == SUBREG |
f8cfc6aa | 6080 | && REG_P (SUBREG_REG (rld[r].in))) |
ddef6bc7 | 6081 | regno = subreg_regno (rld[r].in); |
32131a9c RK |
6082 | #endif |
6083 | ||
21f14ff9 DD |
6084 | if (regno >= 0 |
6085 | && reg_last_reload_reg[regno] != 0 | |
6086 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
6087 | /* Verify that the register it's in can be used in | |
6088 | mode MODE. */ | |
6089 | && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]), | |
6090 | GET_MODE (reg_last_reload_reg[regno]), | |
6091 | mode) | |
6092 | #endif | |
6093 | ) | |
32131a9c | 6094 | { |
48c54229 | 6095 | enum reg_class rclass = rld[r].rclass, last_class; |
cb2afeb3 | 6096 | rtx last_reg = reg_last_reload_reg[regno]; |
02188693 | 6097 | enum machine_mode need_mode; |
05d10675 | 6098 | |
ddef6bc7 JJ |
6099 | i = REGNO (last_reg); |
6100 | i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode); | |
cb2afeb3 | 6101 | last_class = REGNO_REG_CLASS (i); |
02188693 | 6102 | |
ddef6bc7 | 6103 | if (byte == 0) |
ce701d1b BS |
6104 | need_mode = mode; |
6105 | else | |
6106 | need_mode | |
7db7ed3c VM |
6107 | = smallest_mode_for_size |
6108 | (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT, | |
6109 | GET_MODE_CLASS (mode) == MODE_PARTIAL_INT | |
6110 | ? MODE_INT : GET_MODE_CLASS (mode)); | |
02188693 | 6111 | |
1de80b0e | 6112 | if ((GET_MODE_SIZE (GET_MODE (last_reg)) |
02188693 | 6113 | >= GET_MODE_SIZE (need_mode)) |
cb2afeb3 | 6114 | && reg_reloaded_contents[i] == regno |
e6e52be0 | 6115 | && TEST_HARD_REG_BIT (reg_reloaded_valid, i) |
8ec450a4 | 6116 | && HARD_REGNO_MODE_OK (i, rld[r].mode) |
55d796da | 6117 | && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i) |
cb2afeb3 R |
6118 | /* Even if we can't use this register as a reload |
6119 | register, we might use it for reload_override_in, | |
6120 | if copying it to the desired class is cheap | |
6121 | enough. */ | |
55d796da KG |
6122 | || ((REGISTER_MOVE_COST (mode, last_class, rclass) |
6123 | < MEMORY_MOVE_COST (mode, rclass, 1)) | |
6124 | && (secondary_reload_class (1, rclass, mode, | |
8a99f6f9 | 6125 | last_reg) |
cb2afeb3 | 6126 | == NO_REGS) |
cb2afeb3 | 6127 | #ifdef SECONDARY_MEMORY_NEEDED |
55d796da | 6128 | && ! SECONDARY_MEMORY_NEEDED (last_class, rclass, |
cb2afeb3 R |
6129 | mode) |
6130 | #endif | |
6131 | )) | |
6132 | ||
8ec450a4 | 6133 | && (rld[r].nregs == max_group_size |
32131a9c | 6134 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], |
e6e52be0 | 6135 | i)) |
c02cad8f BS |
6136 | && free_for_value_p (i, rld[r].mode, rld[r].opnum, |
6137 | rld[r].when_needed, rld[r].in, | |
6138 | const0_rtx, r, 1)) | |
32131a9c RK |
6139 | { |
6140 | /* If a group is needed, verify that all the subsequent | |
0f41302f | 6141 | registers still have their values intact. */ |
66fd46b6 | 6142 | int nr = hard_regno_nregs[i][rld[r].mode]; |
32131a9c RK |
6143 | int k; |
6144 | ||
6145 | for (k = 1; k < nr; k++) | |
e6e52be0 R |
6146 | if (reg_reloaded_contents[i + k] != regno |
6147 | || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) | |
32131a9c RK |
6148 | break; |
6149 | ||
6150 | if (k == nr) | |
6151 | { | |
c74fa651 | 6152 | int i1; |
eb4d554e | 6153 | int bad_for_class; |
c74fa651 | 6154 | |
cb2afeb3 R |
6155 | last_reg = (GET_MODE (last_reg) == mode |
6156 | ? last_reg : gen_rtx_REG (mode, i)); | |
6157 | ||
eb4d554e GK |
6158 | bad_for_class = 0; |
6159 | for (k = 0; k < nr; k++) | |
48c54229 | 6160 | bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass], |
eb4d554e GK |
6161 | i+k); |
6162 | ||
c74fa651 RS |
6163 | /* We found a register that contains the |
6164 | value we need. If this register is the | |
6165 | same as an `earlyclobber' operand of the | |
6166 | current insn, just mark it as a place to | |
6167 | reload from since we can't use it as the | |
6168 | reload register itself. */ | |
6169 | ||
6170 | for (i1 = 0; i1 < n_earlyclobbers; i1++) | |
6171 | if (reg_overlap_mentioned_for_reload_p | |
6172 | (reg_last_reload_reg[regno], | |
6173 | reload_earlyclobbers[i1])) | |
6174 | break; | |
6175 | ||
8908158d | 6176 | if (i1 != n_earlyclobbers |
c02cad8f BS |
6177 | || ! (free_for_value_p (i, rld[r].mode, |
6178 | rld[r].opnum, | |
6179 | rld[r].when_needed, rld[r].in, | |
6180 | rld[r].out, r, 1)) | |
e6e52be0 | 6181 | /* Don't use it if we'd clobber a pseudo reg. */ |
f1db3576 | 6182 | || (TEST_HARD_REG_BIT (reg_used_in_insn, i) |
eceef4c9 | 6183 | && rld[r].out |
e6e52be0 | 6184 | && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) |
0c7f2259 | 6185 | /* Don't clobber the frame pointer. */ |
1d7254c5 | 6186 | || (i == HARD_FRAME_POINTER_REGNUM |
2f460a0a | 6187 | && frame_pointer_needed |
1d7254c5 | 6188 | && rld[r].out) |
8908158d RS |
6189 | /* Don't really use the inherited spill reg |
6190 | if we need it wider than we've got it. */ | |
8ec450a4 | 6191 | || (GET_MODE_SIZE (rld[r].mode) |
b29514ee | 6192 | > GET_MODE_SIZE (mode)) |
eb4d554e | 6193 | || bad_for_class |
cb2afeb3 | 6194 | |
b29514ee R |
6195 | /* If find_reloads chose reload_out as reload |
6196 | register, stay with it - that leaves the | |
6197 | inherited register for subsequent reloads. */ | |
eceef4c9 | 6198 | || (rld[r].out && rld[r].reg_rtx |
67e61fe7 | 6199 | && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) |
cb2afeb3 | 6200 | { |
4c3a2649 BS |
6201 | if (! rld[r].optional) |
6202 | { | |
6203 | reload_override_in[r] = last_reg; | |
6204 | reload_inheritance_insn[r] | |
6205 | = reg_reloaded_insn[i]; | |
6206 | } | |
cb2afeb3 | 6207 | } |
c74fa651 RS |
6208 | else |
6209 | { | |
54c40e68 | 6210 | int k; |
c74fa651 RS |
6211 | /* We can use this as a reload reg. */ |
6212 | /* Mark the register as in use for this part of | |
6213 | the insn. */ | |
e6e52be0 | 6214 | mark_reload_reg_in_use (i, |
eceef4c9 BS |
6215 | rld[r].opnum, |
6216 | rld[r].when_needed, | |
8ec450a4 | 6217 | rld[r].mode); |
eceef4c9 | 6218 | rld[r].reg_rtx = last_reg; |
c74fa651 RS |
6219 | reload_inherited[r] = 1; |
6220 | reload_inheritance_insn[r] | |
6221 | = reg_reloaded_insn[i]; | |
6222 | reload_spill_index[r] = i; | |
54c40e68 RS |
6223 | for (k = 0; k < nr; k++) |
6224 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, | |
e6e52be0 | 6225 | i + k); |
c74fa651 | 6226 | } |
32131a9c RK |
6227 | } |
6228 | } | |
6229 | } | |
6230 | } | |
6231 | ||
6232 | /* Here's another way to see if the value is already lying around. */ | |
6233 | if (inheritance | |
eceef4c9 | 6234 | && rld[r].in != 0 |
32131a9c | 6235 | && ! reload_inherited[r] |
eceef4c9 BS |
6236 | && rld[r].out == 0 |
6237 | && (CONSTANT_P (rld[r].in) | |
6238 | || GET_CODE (rld[r].in) == PLUS | |
f8cfc6aa | 6239 | || REG_P (rld[r].in) |
3c0cb5de | 6240 | || MEM_P (rld[r].in)) |
8ec450a4 | 6241 | && (rld[r].nregs == max_group_size |
48c54229 | 6242 | || ! reg_classes_intersect_p (rld[r].rclass, group_class))) |
eceef4c9 | 6243 | search_equiv = rld[r].in; |
8593b745 R |
6244 | /* If this is an output reload from a simple move insn, look |
6245 | if an equivalence for the input is available. */ | |
eceef4c9 | 6246 | else if (inheritance && rld[r].in == 0 && rld[r].out != 0) |
8593b745 R |
6247 | { |
6248 | rtx set = single_set (insn); | |
6249 | ||
6250 | if (set | |
eceef4c9 | 6251 | && rtx_equal_p (rld[r].out, SET_DEST (set)) |
8593b745 R |
6252 | && CONSTANT_P (SET_SRC (set))) |
6253 | search_equiv = SET_SRC (set); | |
6254 | } | |
6255 | ||
6256 | if (search_equiv) | |
32131a9c | 6257 | { |
b3694847 | 6258 | rtx equiv |
48c54229 | 6259 | = find_equiv_reg (search_equiv, insn, rld[r].rclass, |
9714cf43 | 6260 | -1, NULL, 0, rld[r].mode); |
f428f252 | 6261 | int regno = 0; |
32131a9c RK |
6262 | |
6263 | if (equiv != 0) | |
6264 | { | |
f8cfc6aa | 6265 | if (REG_P (equiv)) |
32131a9c | 6266 | regno = REGNO (equiv); |
41374e13 | 6267 | else |
32131a9c | 6268 | { |
f8a9e02b RK |
6269 | /* This must be a SUBREG of a hard register. |
6270 | Make a new REG since this might be used in an | |
6271 | address and not all machines support SUBREGs | |
6272 | there. */ | |
41374e13 | 6273 | gcc_assert (GET_CODE (equiv) == SUBREG); |
ddef6bc7 | 6274 | regno = subreg_regno (equiv); |
8ec450a4 | 6275 | equiv = gen_rtx_REG (rld[r].mode, regno); |
9c0a30c3 EB |
6276 | /* If we choose EQUIV as the reload register, but the |
6277 | loop below decides to cancel the inheritance, we'll | |
6278 | end up reloading EQUIV in rld[r].mode, not the mode | |
6279 | it had originally. That isn't safe when EQUIV isn't | |
6280 | available as a spill register since its value might | |
6281 | still be live at this point. */ | |
6282 | for (i = regno; i < regno + (int) rld[r].nregs; i++) | |
6283 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, i)) | |
6284 | equiv = 0; | |
32131a9c | 6285 | } |
32131a9c RK |
6286 | } |
6287 | ||
6288 | /* If we found a spill reg, reject it unless it is free | |
6289 | and of the desired class. */ | |
f58d8c95 JW |
6290 | if (equiv != 0) |
6291 | { | |
6292 | int regs_used = 0; | |
6293 | int bad_for_class = 0; | |
6294 | int max_regno = regno + rld[r].nregs; | |
6295 | ||
6296 | for (i = regno; i < max_regno; i++) | |
6297 | { | |
6298 | regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
6299 | i); | |
48c54229 | 6300 | bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass], |
f58d8c95 JW |
6301 | i); |
6302 | } | |
6303 | ||
6304 | if ((regs_used | |
c02cad8f BS |
6305 | && ! free_for_value_p (regno, rld[r].mode, |
6306 | rld[r].opnum, rld[r].when_needed, | |
6307 | rld[r].in, rld[r].out, r, 1)) | |
f58d8c95 JW |
6308 | || bad_for_class) |
6309 | equiv = 0; | |
6310 | } | |
32131a9c | 6311 | |
8ec450a4 | 6312 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) |
32131a9c RK |
6313 | equiv = 0; |
6314 | ||
6315 | /* We found a register that contains the value we need. | |
6316 | If this register is the same as an `earlyclobber' operand | |
6317 | of the current insn, just mark it as a place to reload from | |
6318 | since we can't use it as the reload register itself. */ | |
6319 | ||
6320 | if (equiv != 0) | |
6321 | for (i = 0; i < n_earlyclobbers; i++) | |
bfa30b22 RK |
6322 | if (reg_overlap_mentioned_for_reload_p (equiv, |
6323 | reload_earlyclobbers[i])) | |
32131a9c | 6324 | { |
4c3a2649 BS |
6325 | if (! rld[r].optional) |
6326 | reload_override_in[r] = equiv; | |
32131a9c RK |
6327 | equiv = 0; |
6328 | break; | |
6329 | } | |
6330 | ||
3c785e47 R |
6331 | /* If the equiv register we have found is explicitly clobbered |
6332 | in the current insn, it depends on the reload type if we | |
6333 | can use it, use it for reload_override_in, or not at all. | |
6334 | In particular, we then can't use EQUIV for a | |
6335 | RELOAD_FOR_OUTPUT_ADDRESS reload. */ | |
32131a9c | 6336 | |
9532e31f | 6337 | if (equiv != 0) |
174fa2c4 | 6338 | { |
d0236c3b | 6339 | if (regno_clobbered_p (regno, insn, rld[r].mode, 2)) |
9532e31f BS |
6340 | switch (rld[r].when_needed) |
6341 | { | |
6342 | case RELOAD_FOR_OTHER_ADDRESS: | |
6343 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6344 | case RELOAD_FOR_INPUT_ADDRESS: | |
6345 | case RELOAD_FOR_OPADDR_ADDR: | |
6346 | break; | |
6347 | case RELOAD_OTHER: | |
6348 | case RELOAD_FOR_INPUT: | |
6349 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6350 | if (! rld[r].optional) | |
6351 | reload_override_in[r] = equiv; | |
6352 | /* Fall through. */ | |
6353 | default: | |
6354 | equiv = 0; | |
6355 | break; | |
6356 | } | |
6357 | else if (regno_clobbered_p (regno, insn, rld[r].mode, 1)) | |
6358 | switch (rld[r].when_needed) | |
6359 | { | |
6360 | case RELOAD_FOR_OTHER_ADDRESS: | |
6361 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6362 | case RELOAD_FOR_INPUT_ADDRESS: | |
6363 | case RELOAD_FOR_OPADDR_ADDR: | |
6364 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6365 | case RELOAD_FOR_INPUT: | |
6366 | break; | |
6367 | case RELOAD_OTHER: | |
6368 | if (! rld[r].optional) | |
6369 | reload_override_in[r] = equiv; | |
6370 | /* Fall through. */ | |
6371 | default: | |
6372 | equiv = 0; | |
6373 | break; | |
6374 | } | |
32131a9c RK |
6375 | } |
6376 | ||
6377 | /* If we found an equivalent reg, say no code need be generated | |
6378 | to load it, and use it as our reload reg. */ | |
a6a2274a KH |
6379 | if (equiv != 0 |
6380 | && (regno != HARD_FRAME_POINTER_REGNUM | |
2f460a0a | 6381 | || !frame_pointer_needed)) |
32131a9c | 6382 | { |
66fd46b6 | 6383 | int nr = hard_regno_nregs[regno][rld[r].mode]; |
100338df | 6384 | int k; |
eceef4c9 | 6385 | rld[r].reg_rtx = equiv; |
a2a6f3cf | 6386 | reload_spill_index[r] = regno; |
32131a9c | 6387 | reload_inherited[r] = 1; |
100338df | 6388 | |
91d7e7ac R |
6389 | /* If reg_reloaded_valid is not set for this register, |
6390 | there might be a stale spill_reg_store lying around. | |
6391 | We must clear it, since otherwise emit_reload_insns | |
6392 | might delete the store. */ | |
6393 | if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) | |
6394 | spill_reg_store[regno] = NULL_RTX; | |
100338df JL |
6395 | /* If any of the hard registers in EQUIV are spill |
6396 | registers, mark them as in use for this insn. */ | |
6397 | for (k = 0; k < nr; k++) | |
be7ae2a4 | 6398 | { |
100338df JL |
6399 | i = spill_reg_order[regno + k]; |
6400 | if (i >= 0) | |
6401 | { | |
eceef4c9 BS |
6402 | mark_reload_reg_in_use (regno, rld[r].opnum, |
6403 | rld[r].when_needed, | |
8ec450a4 | 6404 | rld[r].mode); |
100338df JL |
6405 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, |
6406 | regno + k); | |
6407 | } | |
be7ae2a4 | 6408 | } |
32131a9c RK |
6409 | } |
6410 | } | |
6411 | ||
6412 | /* If we found a register to use already, or if this is an optional | |
6413 | reload, we are done. */ | |
eceef4c9 | 6414 | if (rld[r].reg_rtx != 0 || rld[r].optional != 0) |
32131a9c RK |
6415 | continue; |
6416 | ||
1d7254c5 KH |
6417 | #if 0 |
6418 | /* No longer needed for correct operation. Might or might | |
6419 | not give better code on the average. Want to experiment? */ | |
32131a9c RK |
6420 | |
6421 | /* See if there is a later reload that has a class different from our | |
6422 | class that intersects our class or that requires less register | |
6423 | than our reload. If so, we must allocate a register to this | |
6424 | reload now, since that reload might inherit a previous reload | |
6425 | and take the only available register in our class. Don't do this | |
6426 | for optional reloads since they will force all previous reloads | |
6427 | to be allocated. Also don't do this for reloads that have been | |
6428 | turned off. */ | |
6429 | ||
6430 | for (i = j + 1; i < n_reloads; i++) | |
6431 | { | |
6432 | int s = reload_order[i]; | |
6433 | ||
eceef4c9 BS |
6434 | if ((rld[s].in == 0 && rld[s].out == 0 |
6435 | && ! rld[s].secondary_p) | |
6436 | || rld[s].optional) | |
32131a9c RK |
6437 | continue; |
6438 | ||
48c54229 KG |
6439 | if ((rld[s].rclass != rld[r].rclass |
6440 | && reg_classes_intersect_p (rld[r].rclass, | |
6441 | rld[s].rclass)) | |
8ec450a4 | 6442 | || rld[s].nregs < rld[r].nregs) |
05d10675 | 6443 | break; |
32131a9c RK |
6444 | } |
6445 | ||
6446 | if (i == n_reloads) | |
6447 | continue; | |
6448 | ||
f5d8c9f4 | 6449 | allocate_reload_reg (chain, r, j == n_reloads - 1); |
32131a9c RK |
6450 | #endif |
6451 | } | |
6452 | ||
6453 | /* Now allocate reload registers for anything non-optional that | |
6454 | didn't get one yet. */ | |
6455 | for (j = 0; j < n_reloads; j++) | |
6456 | { | |
b3694847 | 6457 | int r = reload_order[j]; |
32131a9c RK |
6458 | |
6459 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 | 6460 | if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) |
32131a9c RK |
6461 | continue; |
6462 | ||
6463 | /* Skip reloads that already have a register allocated or are | |
0f41302f | 6464 | optional. */ |
eceef4c9 | 6465 | if (rld[r].reg_rtx != 0 || rld[r].optional) |
32131a9c RK |
6466 | continue; |
6467 | ||
f5d8c9f4 | 6468 | if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) |
32131a9c RK |
6469 | break; |
6470 | } | |
6471 | ||
6472 | /* If that loop got all the way, we have won. */ | |
6473 | if (j == n_reloads) | |
f5d8c9f4 BS |
6474 | { |
6475 | win = 1; | |
6476 | break; | |
6477 | } | |
32131a9c | 6478 | |
32131a9c | 6479 | /* Loop around and try without any inheritance. */ |
32131a9c RK |
6480 | } |
6481 | ||
f5d8c9f4 BS |
6482 | if (! win) |
6483 | { | |
6484 | /* First undo everything done by the failed attempt | |
6485 | to allocate with inheritance. */ | |
6486 | choose_reload_regs_init (chain, save_reload_reg_rtx); | |
6487 | ||
6488 | /* Some sanity tests to verify that the reloads found in the first | |
6489 | pass are identical to the ones we have now. */ | |
41374e13 | 6490 | gcc_assert (chain->n_reloads == n_reloads); |
f5d8c9f4 BS |
6491 | |
6492 | for (i = 0; i < n_reloads; i++) | |
6493 | { | |
6494 | if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) | |
6495 | continue; | |
41374e13 | 6496 | gcc_assert (chain->rld[i].when_needed == rld[i].when_needed); |
f5d8c9f4 BS |
6497 | for (j = 0; j < n_spills; j++) |
6498 | if (spill_regs[j] == chain->rld[i].regno) | |
6499 | if (! set_reload_reg (j, i)) | |
6500 | failed_reload (chain->insn, i); | |
6501 | } | |
6502 | } | |
6503 | ||
32131a9c RK |
6504 | /* If we thought we could inherit a reload, because it seemed that |
6505 | nothing else wanted the same reload register earlier in the insn, | |
cb2afeb3 R |
6506 | verify that assumption, now that all reloads have been assigned. |
6507 | Likewise for reloads where reload_override_in has been set. */ | |
32131a9c | 6508 | |
cb2afeb3 R |
6509 | /* If doing expensive optimizations, do one preliminary pass that doesn't |
6510 | cancel any inheritance, but removes reloads that have been needed only | |
6511 | for reloads that we know can be inherited. */ | |
6512 | for (pass = flag_expensive_optimizations; pass >= 0; pass--) | |
32131a9c | 6513 | { |
cb2afeb3 | 6514 | for (j = 0; j < n_reloads; j++) |
029b38ff | 6515 | { |
b3694847 | 6516 | int r = reload_order[j]; |
cb2afeb3 | 6517 | rtx check_reg; |
eceef4c9 BS |
6518 | if (reload_inherited[r] && rld[r].reg_rtx) |
6519 | check_reg = rld[r].reg_rtx; | |
cb2afeb3 | 6520 | else if (reload_override_in[r] |
f8cfc6aa | 6521 | && (REG_P (reload_override_in[r]) |
05d10675 | 6522 | || GET_CODE (reload_override_in[r]) == SUBREG)) |
cb2afeb3 R |
6523 | check_reg = reload_override_in[r]; |
6524 | else | |
6525 | continue; | |
c02cad8f BS |
6526 | if (! free_for_value_p (true_regnum (check_reg), rld[r].mode, |
6527 | rld[r].opnum, rld[r].when_needed, rld[r].in, | |
6528 | (reload_inherited[r] | |
6529 | ? rld[r].out : const0_rtx), | |
6530 | r, 1)) | |
029b38ff | 6531 | { |
cb2afeb3 R |
6532 | if (pass) |
6533 | continue; | |
6534 | reload_inherited[r] = 0; | |
6535 | reload_override_in[r] = 0; | |
029b38ff | 6536 | } |
cb2afeb3 R |
6537 | /* If we can inherit a RELOAD_FOR_INPUT, or can use a |
6538 | reload_override_in, then we do not need its related | |
6539 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; | |
6540 | likewise for other reload types. | |
6541 | We handle this by removing a reload when its only replacement | |
6542 | is mentioned in reload_in of the reload we are going to inherit. | |
6543 | A special case are auto_inc expressions; even if the input is | |
6544 | inherited, we still need the address for the output. We can | |
fe92fe26 | 6545 | recognize them because they have RELOAD_OUT set to RELOAD_IN. |
eaec9b3d | 6546 | If we succeeded removing some reload and we are doing a preliminary |
cb2afeb3 R |
6547 | pass just to remove such reloads, make another pass, since the |
6548 | removal of one reload might allow us to inherit another one. */ | |
eceef4c9 BS |
6549 | else if (rld[r].in |
6550 | && rld[r].out != rld[r].in | |
6551 | && remove_address_replacements (rld[r].in) && pass) | |
cb2afeb3 | 6552 | pass = 2; |
32131a9c RK |
6553 | } |
6554 | } | |
6555 | ||
6556 | /* Now that reload_override_in is known valid, | |
6557 | actually override reload_in. */ | |
6558 | for (j = 0; j < n_reloads; j++) | |
6559 | if (reload_override_in[j]) | |
eceef4c9 | 6560 | rld[j].in = reload_override_in[j]; |
32131a9c | 6561 | |
272d0bee | 6562 | /* If this reload won't be done because it has been canceled or is |
32131a9c RK |
6563 | optional and not inherited, clear reload_reg_rtx so other |
6564 | routines (such as subst_reloads) don't get confused. */ | |
6565 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
6566 | if (rld[j].reg_rtx != 0 |
6567 | && ((rld[j].optional && ! reload_inherited[j]) | |
6568 | || (rld[j].in == 0 && rld[j].out == 0 | |
6569 | && ! rld[j].secondary_p))) | |
be7ae2a4 | 6570 | { |
eceef4c9 | 6571 | int regno = true_regnum (rld[j].reg_rtx); |
be7ae2a4 RK |
6572 | |
6573 | if (spill_reg_order[regno] >= 0) | |
eceef4c9 | 6574 | clear_reload_reg_in_use (regno, rld[j].opnum, |
8ec450a4 | 6575 | rld[j].when_needed, rld[j].mode); |
eceef4c9 | 6576 | rld[j].reg_rtx = 0; |
c0029be5 | 6577 | reload_spill_index[j] = -1; |
be7ae2a4 | 6578 | } |
32131a9c RK |
6579 | |
6580 | /* Record which pseudos and which spill regs have output reloads. */ | |
6581 | for (j = 0; j < n_reloads; j++) | |
6582 | { | |
b3694847 | 6583 | int r = reload_order[j]; |
32131a9c RK |
6584 | |
6585 | i = reload_spill_index[r]; | |
6586 | ||
e6e52be0 | 6587 | /* I is nonneg if this reload uses a register. |
eceef4c9 | 6588 | If rld[r].reg_rtx is 0, this is an optional reload |
32131a9c | 6589 | that we opted to ignore. */ |
f8cfc6aa | 6590 | if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg) |
eceef4c9 | 6591 | && rld[r].reg_rtx != 0) |
32131a9c | 6592 | { |
b3694847 | 6593 | int nregno = REGNO (rld[r].out_reg); |
372e033b RS |
6594 | int nr = 1; |
6595 | ||
6596 | if (nregno < FIRST_PSEUDO_REGISTER) | |
66fd46b6 | 6597 | nr = hard_regno_nregs[nregno][rld[r].mode]; |
32131a9c RK |
6598 | |
6599 | while (--nr >= 0) | |
2c61f5f1 JH |
6600 | SET_REGNO_REG_SET (®_has_output_reload, |
6601 | nregno + nr); | |
372e033b RS |
6602 | |
6603 | if (i >= 0) | |
32131a9c | 6604 | { |
66fd46b6 | 6605 | nr = hard_regno_nregs[i][rld[r].mode]; |
372e033b | 6606 | while (--nr >= 0) |
e6e52be0 | 6607 | SET_HARD_REG_BIT (reg_is_output_reload, i + nr); |
32131a9c RK |
6608 | } |
6609 | ||
41374e13 NS |
6610 | gcc_assert (rld[r].when_needed == RELOAD_OTHER |
6611 | || rld[r].when_needed == RELOAD_FOR_OUTPUT | |
6612 | || rld[r].when_needed == RELOAD_FOR_INSN); | |
32131a9c RK |
6613 | } |
6614 | } | |
6615 | } | |
cb2afeb3 R |
6616 | |
6617 | /* Deallocate the reload register for reload R. This is called from | |
6618 | remove_address_replacements. */ | |
1d813780 | 6619 | |
cb2afeb3 | 6620 | void |
0c20a65f | 6621 | deallocate_reload_reg (int r) |
cb2afeb3 R |
6622 | { |
6623 | int regno; | |
6624 | ||
eceef4c9 | 6625 | if (! rld[r].reg_rtx) |
cb2afeb3 | 6626 | return; |
eceef4c9 BS |
6627 | regno = true_regnum (rld[r].reg_rtx); |
6628 | rld[r].reg_rtx = 0; | |
cb2afeb3 | 6629 | if (spill_reg_order[regno] >= 0) |
eceef4c9 | 6630 | clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, |
8ec450a4 | 6631 | rld[r].mode); |
cb2afeb3 R |
6632 | reload_spill_index[r] = -1; |
6633 | } | |
32131a9c | 6634 | \f |
40f03658 | 6635 | /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two |
546b63fb RK |
6636 | reloads of the same item for fear that we might not have enough reload |
6637 | registers. However, normally they will get the same reload register | |
05d10675 | 6638 | and hence actually need not be loaded twice. |
546b63fb RK |
6639 | |
6640 | Here we check for the most common case of this phenomenon: when we have | |
6641 | a number of reloads for the same object, each of which were allocated | |
6642 | the same reload_reg_rtx, that reload_reg_rtx is not used for any other | |
6643 | reload, and is not modified in the insn itself. If we find such, | |
6644 | merge all the reloads and set the resulting reload to RELOAD_OTHER. | |
6645 | This will not increase the number of spill registers needed and will | |
6646 | prevent redundant code. */ | |
6647 | ||
546b63fb | 6648 | static void |
0c20a65f | 6649 | merge_assigned_reloads (rtx insn) |
546b63fb RK |
6650 | { |
6651 | int i, j; | |
6652 | ||
6653 | /* Scan all the reloads looking for ones that only load values and | |
6654 | are not already RELOAD_OTHER and ones whose reload_reg_rtx are | |
6655 | assigned and not modified by INSN. */ | |
6656 | ||
6657 | for (i = 0; i < n_reloads; i++) | |
6658 | { | |
d668e863 R |
6659 | int conflicting_input = 0; |
6660 | int max_input_address_opnum = -1; | |
6661 | int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; | |
6662 | ||
eceef4c9 BS |
6663 | if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER |
6664 | || rld[i].out != 0 || rld[i].reg_rtx == 0 | |
6665 | || reg_set_p (rld[i].reg_rtx, insn)) | |
546b63fb RK |
6666 | continue; |
6667 | ||
6668 | /* Look at all other reloads. Ensure that the only use of this | |
6669 | reload_reg_rtx is in a reload that just loads the same value | |
6670 | as we do. Note that any secondary reloads must be of the identical | |
6671 | class since the values, modes, and result registers are the | |
6672 | same, so we need not do anything with any secondary reloads. */ | |
6673 | ||
6674 | for (j = 0; j < n_reloads; j++) | |
6675 | { | |
eceef4c9 BS |
6676 | if (i == j || rld[j].reg_rtx == 0 |
6677 | || ! reg_overlap_mentioned_p (rld[j].reg_rtx, | |
6678 | rld[i].reg_rtx)) | |
546b63fb RK |
6679 | continue; |
6680 | ||
eceef4c9 BS |
6681 | if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6682 | && rld[j].opnum > max_input_address_opnum) | |
6683 | max_input_address_opnum = rld[j].opnum; | |
d668e863 | 6684 | |
546b63fb | 6685 | /* If the reload regs aren't exactly the same (e.g, different modes) |
d668e863 R |
6686 | or if the values are different, we can't merge this reload. |
6687 | But if it is an input reload, we might still merge | |
6688 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ | |
546b63fb | 6689 | |
eceef4c9 BS |
6690 | if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) |
6691 | || rld[j].out != 0 || rld[j].in == 0 | |
6692 | || ! rtx_equal_p (rld[i].in, rld[j].in)) | |
d668e863 | 6693 | { |
eceef4c9 BS |
6694 | if (rld[j].when_needed != RELOAD_FOR_INPUT |
6695 | || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS | |
6696 | || rld[i].opnum > rld[j].opnum) | |
6697 | && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS)) | |
d668e863 R |
6698 | break; |
6699 | conflicting_input = 1; | |
eceef4c9 BS |
6700 | if (min_conflicting_input_opnum > rld[j].opnum) |
6701 | min_conflicting_input_opnum = rld[j].opnum; | |
d668e863 | 6702 | } |
546b63fb RK |
6703 | } |
6704 | ||
6705 | /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if | |
6706 | we, in fact, found any matching reloads. */ | |
6707 | ||
d668e863 R |
6708 | if (j == n_reloads |
6709 | && max_input_address_opnum <= min_conflicting_input_opnum) | |
546b63fb | 6710 | { |
3f27846b DJ |
6711 | gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT); |
6712 | ||
546b63fb | 6713 | for (j = 0; j < n_reloads; j++) |
eceef4c9 BS |
6714 | if (i != j && rld[j].reg_rtx != 0 |
6715 | && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) | |
d668e863 | 6716 | && (! conflicting_input |
eceef4c9 BS |
6717 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6718 | || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
546b63fb | 6719 | { |
eceef4c9 BS |
6720 | rld[i].when_needed = RELOAD_OTHER; |
6721 | rld[j].in = 0; | |
efdb3590 | 6722 | reload_spill_index[j] = -1; |
546b63fb RK |
6723 | transfer_replacements (i, j); |
6724 | } | |
6725 | ||
b883ab57 HMC |
6726 | /* If this is now RELOAD_OTHER, look for any reloads that |
6727 | load parts of this operand and set them to | |
6728 | RELOAD_FOR_OTHER_ADDRESS if they were for inputs, | |
6729 | RELOAD_OTHER for outputs. Note that this test is | |
6730 | equivalent to looking for reloads for this operand | |
6731 | number. | |
6732 | ||
6733 | We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; | |
6734 | it may share registers with a RELOAD_FOR_INPUT, so we can | |
6735 | not change it to RELOAD_FOR_OTHER_ADDRESS. We should | |
6736 | never need to, since we do not modify RELOAD_FOR_OUTPUT. | |
6737 | ||
6738 | It is possible that the RELOAD_FOR_OPERAND_ADDRESS | |
6739 | instruction is assigned the same register as the earlier | |
6740 | RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two | |
6741 | instructions will cause the RELOAD_FOR_OTHER_ADDRESS | |
6742 | instruction to be deleted later on. */ | |
546b63fb | 6743 | |
eceef4c9 | 6744 | if (rld[i].when_needed == RELOAD_OTHER) |
546b63fb | 6745 | for (j = 0; j < n_reloads; j++) |
eceef4c9 | 6746 | if (rld[j].in != 0 |
91667711 | 6747 | && rld[j].when_needed != RELOAD_OTHER |
dec0798e | 6748 | && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS |
3f27846b | 6749 | && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS |
b883ab57 | 6750 | && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS |
dec0798e R |
6751 | && (! conflicting_input |
6752 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
6753 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
eceef4c9 BS |
6754 | && reg_overlap_mentioned_for_reload_p (rld[j].in, |
6755 | rld[i].in)) | |
c15c18c5 JW |
6756 | { |
6757 | int k; | |
6758 | ||
6759 | rld[j].when_needed | |
6760 | = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
6761 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
6762 | ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); | |
6763 | ||
0e61db61 NS |
6764 | /* Check to see if we accidentally converted two |
6765 | reloads that use the same reload register with | |
6766 | different inputs to the same type. If so, the | |
6767 | resulting code won't work. */ | |
c15c18c5 JW |
6768 | if (rld[j].reg_rtx) |
6769 | for (k = 0; k < j; k++) | |
41374e13 NS |
6770 | gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0 |
6771 | || rld[k].when_needed != rld[j].when_needed | |
6772 | || !rtx_equal_p (rld[k].reg_rtx, | |
6773 | rld[j].reg_rtx) | |
6774 | || rtx_equal_p (rld[k].in, | |
6775 | rld[j].in)); | |
c15c18c5 | 6776 | } |
546b63fb RK |
6777 | } |
6778 | } | |
05d10675 | 6779 | } |
546b63fb | 6780 | \f |
367b1cf5 BS |
6781 | /* These arrays are filled by emit_reload_insns and its subroutines. */ |
6782 | static rtx input_reload_insns[MAX_RECOG_OPERANDS]; | |
6783 | static rtx other_input_address_reload_insns = 0; | |
6784 | static rtx other_input_reload_insns = 0; | |
6785 | static rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6786 | static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6787 | static rtx output_reload_insns[MAX_RECOG_OPERANDS]; | |
6788 | static rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6789 | static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6790 | static rtx operand_reload_insns = 0; | |
6791 | static rtx other_operand_reload_insns = 0; | |
6792 | static rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; | |
6793 | ||
6794 | /* Values to be put in spill_reg_store are put here first. */ | |
6795 | static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
6796 | static HARD_REG_SET reg_reloaded_died; | |
6797 | ||
8a99f6f9 R |
6798 | /* Check if *RELOAD_REG is suitable as an intermediate or scratch register |
6799 | of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg | |
6800 | is nonzero, if that is suitable. On success, change *RELOAD_REG to the | |
6801 | adjusted register, and return true. Otherwise, return false. */ | |
6802 | static bool | |
6803 | reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg, | |
6804 | enum reg_class new_class, | |
6805 | enum machine_mode new_mode) | |
6806 | ||
6807 | { | |
6808 | rtx reg; | |
6809 | ||
6810 | for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0) | |
6811 | { | |
6812 | unsigned regno = REGNO (reg); | |
6813 | ||
6814 | if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno)) | |
6815 | continue; | |
6816 | if (GET_MODE (reg) != new_mode) | |
6817 | { | |
6818 | if (!HARD_REGNO_MODE_OK (regno, new_mode)) | |
6819 | continue; | |
6820 | if (hard_regno_nregs[regno][new_mode] | |
6821 | > hard_regno_nregs[regno][GET_MODE (reg)]) | |
6822 | continue; | |
6823 | reg = reload_adjust_reg_for_mode (reg, new_mode); | |
6824 | } | |
6825 | *reload_reg = reg; | |
6826 | return true; | |
6827 | } | |
6828 | return false; | |
6829 | } | |
6830 | ||
6831 | /* Check if *RELOAD_REG is suitable as a scratch register for the reload | |
6832 | pattern with insn_code ICODE, or alternatively, if alt_reload_reg is | |
6833 | nonzero, if that is suitable. On success, change *RELOAD_REG to the | |
6834 | adjusted register, and return true. Otherwise, return false. */ | |
6835 | static bool | |
6836 | reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg, | |
6837 | enum insn_code icode) | |
6838 | ||
6839 | { | |
6840 | enum reg_class new_class = scratch_reload_class (icode); | |
6841 | enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode; | |
6842 | ||
6843 | return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg, | |
6844 | new_class, new_mode); | |
6845 | } | |
6846 | ||
367b1cf5 BS |
6847 | /* Generate insns to perform reload RL, which is for the insn in CHAIN and |
6848 | has the number J. OLD contains the value to be used as input. */ | |
770ae6cc | 6849 | |
32131a9c | 6850 | static void |
0c20a65f AJ |
6851 | emit_input_reload_insns (struct insn_chain *chain, struct reload *rl, |
6852 | rtx old, int j) | |
32131a9c | 6853 | { |
7609e720 | 6854 | rtx insn = chain->insn; |
fb959f72 | 6855 | rtx reloadreg; |
367b1cf5 BS |
6856 | rtx oldequiv_reg = 0; |
6857 | rtx oldequiv = 0; | |
6858 | int special = 0; | |
6859 | enum machine_mode mode; | |
6860 | rtx *where; | |
6861 | ||
367b1cf5 BS |
6862 | /* delete_output_reload is only invoked properly if old contains |
6863 | the original pseudo register. Since this is replaced with a | |
6864 | hard reg when RELOAD_OVERRIDE_IN is set, see if we can | |
6865 | find the pseudo in RELOAD_IN_REG. */ | |
75803b85 | 6866 | if (reload_override_in[j] |
f8cfc6aa | 6867 | && REG_P (rl->in_reg)) |
367b1cf5 BS |
6868 | { |
6869 | oldequiv = old; | |
6870 | old = rl->in_reg; | |
6871 | } | |
6872 | if (oldequiv == 0) | |
6873 | oldequiv = old; | |
f8cfc6aa | 6874 | else if (REG_P (oldequiv)) |
367b1cf5 BS |
6875 | oldequiv_reg = oldequiv; |
6876 | else if (GET_CODE (oldequiv) == SUBREG) | |
6877 | oldequiv_reg = SUBREG_REG (oldequiv); | |
6878 | ||
fb959f72 RS |
6879 | reloadreg = reload_reg_rtx_for_input[j]; |
6880 | mode = GET_MODE (reloadreg); | |
6881 | ||
367b1cf5 BS |
6882 | /* If we are reloading from a register that was recently stored in |
6883 | with an output-reload, see if we can prove there was | |
6884 | actually no need to store the old value in it. */ | |
6885 | ||
f8cfc6aa | 6886 | if (optimize && REG_P (oldequiv) |
367b1cf5 BS |
6887 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER |
6888 | && spill_reg_store[REGNO (oldequiv)] | |
f8cfc6aa | 6889 | && REG_P (old) |
367b1cf5 BS |
6890 | && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) |
6891 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6892 | rl->out_reg))) | |
fb959f72 | 6893 | delete_output_reload (insn, j, REGNO (oldequiv), reloadreg); |
367b1cf5 | 6894 | |
fb959f72 RS |
6895 | /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from |
6896 | OLDEQUIV. */ | |
367b1cf5 | 6897 | |
367b1cf5 BS |
6898 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) |
6899 | oldequiv = SUBREG_REG (oldequiv); | |
6900 | if (GET_MODE (oldequiv) != VOIDmode | |
6901 | && mode != GET_MODE (oldequiv)) | |
ddef6bc7 | 6902 | oldequiv = gen_lowpart_SUBREG (mode, oldequiv); |
367b1cf5 BS |
6903 | |
6904 | /* Switch to the right place to emit the reload insns. */ | |
6905 | switch (rl->when_needed) | |
6906 | { | |
6907 | case RELOAD_OTHER: | |
6908 | where = &other_input_reload_insns; | |
6909 | break; | |
6910 | case RELOAD_FOR_INPUT: | |
6911 | where = &input_reload_insns[rl->opnum]; | |
6912 | break; | |
6913 | case RELOAD_FOR_INPUT_ADDRESS: | |
6914 | where = &input_address_reload_insns[rl->opnum]; | |
6915 | break; | |
6916 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6917 | where = &inpaddr_address_reload_insns[rl->opnum]; | |
6918 | break; | |
6919 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
6920 | where = &output_address_reload_insns[rl->opnum]; | |
6921 | break; | |
6922 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
6923 | where = &outaddr_address_reload_insns[rl->opnum]; | |
6924 | break; | |
6925 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6926 | where = &operand_reload_insns; | |
6927 | break; | |
6928 | case RELOAD_FOR_OPADDR_ADDR: | |
6929 | where = &other_operand_reload_insns; | |
6930 | break; | |
6931 | case RELOAD_FOR_OTHER_ADDRESS: | |
6932 | where = &other_input_address_reload_insns; | |
6933 | break; | |
6934 | default: | |
41374e13 | 6935 | gcc_unreachable (); |
367b1cf5 | 6936 | } |
546b63fb | 6937 | |
367b1cf5 | 6938 | push_to_sequence (*where); |
32131a9c | 6939 | |
367b1cf5 BS |
6940 | /* Auto-increment addresses must be reloaded in a special way. */ |
6941 | if (rl->out && ! rl->out_reg) | |
32131a9c | 6942 | { |
367b1cf5 BS |
6943 | /* We are not going to bother supporting the case where a |
6944 | incremented register can't be copied directly from | |
6945 | OLDEQUIV since this seems highly unlikely. */ | |
41374e13 | 6946 | gcc_assert (rl->secondary_in_reload < 0); |
32131a9c | 6947 | |
367b1cf5 BS |
6948 | if (reload_inherited[j]) |
6949 | oldequiv = reloadreg; | |
cb2afeb3 | 6950 | |
367b1cf5 | 6951 | old = XEXP (rl->in_reg, 0); |
32131a9c | 6952 | |
f8cfc6aa | 6953 | if (optimize && REG_P (oldequiv) |
367b1cf5 BS |
6954 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER |
6955 | && spill_reg_store[REGNO (oldequiv)] | |
f8cfc6aa | 6956 | && REG_P (old) |
367b1cf5 BS |
6957 | && (dead_or_set_p (insn, |
6958 | spill_reg_stored_to[REGNO (oldequiv)]) | |
6959 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6960 | old))) | |
fb959f72 | 6961 | delete_output_reload (insn, j, REGNO (oldequiv), reloadreg); |
367b1cf5 BS |
6962 | |
6963 | /* Prevent normal processing of this reload. */ | |
6964 | special = 1; | |
6965 | /* Output a special code sequence for this case. */ | |
6966 | new_spill_reg_store[REGNO (reloadreg)] | |
6967 | = inc_for_reload (reloadreg, oldequiv, rl->out, | |
6968 | rl->inc); | |
6969 | } | |
32131a9c | 6970 | |
367b1cf5 BS |
6971 | /* If we are reloading a pseudo-register that was set by the previous |
6972 | insn, see if we can get rid of that pseudo-register entirely | |
6973 | by redirecting the previous insn into our reload register. */ | |
6974 | ||
f8cfc6aa | 6975 | else if (optimize && REG_P (old) |
367b1cf5 BS |
6976 | && REGNO (old) >= FIRST_PSEUDO_REGISTER |
6977 | && dead_or_set_p (insn, old) | |
6978 | /* This is unsafe if some other reload | |
6979 | uses the same reg first. */ | |
ff6534ad | 6980 | && ! conflicts_with_override (reloadreg) |
c02cad8f BS |
6981 | && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum, |
6982 | rl->when_needed, old, rl->out, j, 0)) | |
367b1cf5 BS |
6983 | { |
6984 | rtx temp = PREV_INSN (insn); | |
b5b8b0ac | 6985 | while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp))) |
367b1cf5 BS |
6986 | temp = PREV_INSN (temp); |
6987 | if (temp | |
4b4bf941 | 6988 | && NONJUMP_INSN_P (temp) |
367b1cf5 BS |
6989 | && GET_CODE (PATTERN (temp)) == SET |
6990 | && SET_DEST (PATTERN (temp)) == old | |
6991 | /* Make sure we can access insn_operand_constraint. */ | |
6992 | && asm_noperands (PATTERN (temp)) < 0 | |
367b1cf5 BS |
6993 | /* This is unsafe if operand occurs more than once in current |
6994 | insn. Perhaps some occurrences aren't reloaded. */ | |
10d1bb36 | 6995 | && count_occurrences (PATTERN (insn), old, 0) == 1) |
367b1cf5 | 6996 | { |
10d1bb36 | 6997 | rtx old = SET_DEST (PATTERN (temp)); |
367b1cf5 BS |
6998 | /* Store into the reload register instead of the pseudo. */ |
6999 | SET_DEST (PATTERN (temp)) = reloadreg; | |
7000 | ||
10d1bb36 JH |
7001 | /* Verify that resulting insn is valid. */ |
7002 | extract_insn (temp); | |
7003 | if (constrain_operands (1)) | |
32131a9c | 7004 | { |
10d1bb36 JH |
7005 | /* If the previous insn is an output reload, the source is |
7006 | a reload register, and its spill_reg_store entry will | |
7007 | contain the previous destination. This is now | |
7008 | invalid. */ | |
f8cfc6aa | 7009 | if (REG_P (SET_SRC (PATTERN (temp))) |
10d1bb36 JH |
7010 | && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) |
7011 | { | |
7012 | spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
7013 | spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
7014 | } | |
32131a9c | 7015 | |
10d1bb36 JH |
7016 | /* If these are the only uses of the pseudo reg, |
7017 | pretend for GDB it lives in the reload reg we used. */ | |
7018 | if (REG_N_DEATHS (REGNO (old)) == 1 | |
7019 | && REG_N_SETS (REGNO (old)) == 1) | |
7020 | { | |
fb959f72 | 7021 | reg_renumber[REGNO (old)] = REGNO (reloadreg); |
2af2dbdc | 7022 | if (ira_conflicts_p) |
058e97ec VM |
7023 | /* Inform IRA about the change. */ |
7024 | ira_mark_allocation_change (REGNO (old)); | |
7025 | alter_reg (REGNO (old), -1, false); | |
10d1bb36 JH |
7026 | } |
7027 | special = 1; | |
b5b8b0ac AO |
7028 | |
7029 | /* Adjust any debug insns between temp and insn. */ | |
7030 | while ((temp = NEXT_INSN (temp)) != insn) | |
7031 | if (DEBUG_INSN_P (temp)) | |
7032 | replace_rtx (PATTERN (temp), old, reloadreg); | |
7033 | else | |
7034 | gcc_assert (NOTE_P (temp)); | |
10d1bb36 JH |
7035 | } |
7036 | else | |
cb2afeb3 | 7037 | { |
10d1bb36 | 7038 | SET_DEST (PATTERN (temp)) = old; |
32131a9c | 7039 | } |
367b1cf5 BS |
7040 | } |
7041 | } | |
32131a9c | 7042 | |
367b1cf5 | 7043 | /* We can't do that, so output an insn to load RELOADREG. */ |
32131a9c | 7044 | |
367b1cf5 BS |
7045 | /* If we have a secondary reload, pick up the secondary register |
7046 | and icode, if any. If OLDEQUIV and OLD are different or | |
7047 | if this is an in-out reload, recompute whether or not we | |
7048 | still need a secondary register and what the icode should | |
7049 | be. If we still need a secondary register and the class or | |
7050 | icode is different, go back to reloading from OLD if using | |
7051 | OLDEQUIV means that we got the wrong type of register. We | |
7052 | cannot have different class or icode due to an in-out reload | |
7053 | because we don't make such reloads when both the input and | |
7054 | output need secondary reload registers. */ | |
7055 | ||
07875628 | 7056 | if (! special && rl->secondary_in_reload >= 0) |
367b1cf5 BS |
7057 | { |
7058 | rtx second_reload_reg = 0; | |
8a99f6f9 | 7059 | rtx third_reload_reg = 0; |
367b1cf5 BS |
7060 | int secondary_reload = rl->secondary_in_reload; |
7061 | rtx real_oldequiv = oldequiv; | |
7062 | rtx real_old = old; | |
7063 | rtx tmp; | |
7064 | enum insn_code icode; | |
8a99f6f9 | 7065 | enum insn_code tertiary_icode = CODE_FOR_nothing; |
367b1cf5 BS |
7066 | |
7067 | /* If OLDEQUIV is a pseudo with a MEM, get the real MEM | |
7068 | and similarly for OLD. | |
7069 | See comments in get_secondary_reload in reload.c. */ | |
7070 | /* If it is a pseudo that cannot be replaced with its | |
7071 | equivalent MEM, we must fall back to reload_in, which | |
7072 | will have all the necessary substitutions registered. | |
7073 | Likewise for a pseudo that can't be replaced with its | |
7074 | equivalent constant. | |
7075 | ||
7076 | Take extra care for subregs of such pseudos. Note that | |
7077 | we cannot use reg_equiv_mem in this case because it is | |
7078 | not in the right mode. */ | |
7079 | ||
7080 | tmp = oldequiv; | |
7081 | if (GET_CODE (tmp) == SUBREG) | |
7082 | tmp = SUBREG_REG (tmp); | |
f8cfc6aa | 7083 | if (REG_P (tmp) |
367b1cf5 BS |
7084 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER |
7085 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
7086 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
7087 | { | |
7088 | if (! reg_equiv_mem[REGNO (tmp)] | |
7089 | || num_not_at_initial_offset | |
7090 | || GET_CODE (oldequiv) == SUBREG) | |
7091 | real_oldequiv = rl->in; | |
7092 | else | |
7093 | real_oldequiv = reg_equiv_mem[REGNO (tmp)]; | |
7094 | } | |
32131a9c | 7095 | |
367b1cf5 BS |
7096 | tmp = old; |
7097 | if (GET_CODE (tmp) == SUBREG) | |
7098 | tmp = SUBREG_REG (tmp); | |
f8cfc6aa | 7099 | if (REG_P (tmp) |
367b1cf5 BS |
7100 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER |
7101 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
7102 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
7103 | { | |
7104 | if (! reg_equiv_mem[REGNO (tmp)] | |
7105 | || num_not_at_initial_offset | |
7106 | || GET_CODE (old) == SUBREG) | |
7107 | real_old = rl->in; | |
7108 | else | |
7109 | real_old = reg_equiv_mem[REGNO (tmp)]; | |
7110 | } | |
7111 | ||
7112 | second_reload_reg = rld[secondary_reload].reg_rtx; | |
8a99f6f9 R |
7113 | if (rld[secondary_reload].secondary_in_reload >= 0) |
7114 | { | |
7115 | int tertiary_reload = rld[secondary_reload].secondary_in_reload; | |
7116 | ||
7117 | third_reload_reg = rld[tertiary_reload].reg_rtx; | |
7118 | tertiary_icode = rld[secondary_reload].secondary_in_icode; | |
7119 | /* We'd have to add more code for quartary reloads. */ | |
7120 | gcc_assert (rld[tertiary_reload].secondary_in_reload < 0); | |
7121 | } | |
367b1cf5 BS |
7122 | icode = rl->secondary_in_icode; |
7123 | ||
7124 | if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) | |
7125 | || (rl->in != 0 && rl->out != 0)) | |
7126 | { | |
8a99f6f9 R |
7127 | secondary_reload_info sri, sri2; |
7128 | enum reg_class new_class, new_t_class; | |
367b1cf5 | 7129 | |
8a99f6f9 R |
7130 | sri.icode = CODE_FOR_nothing; |
7131 | sri.prev_sri = NULL; | |
48c54229 | 7132 | new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass, |
8a99f6f9 R |
7133 | mode, &sri); |
7134 | ||
7135 | if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
367b1cf5 | 7136 | second_reload_reg = 0; |
8a99f6f9 | 7137 | else if (new_class == NO_REGS) |
32131a9c | 7138 | { |
8a99f6f9 | 7139 | if (reload_adjust_reg_for_icode (&second_reload_reg, |
bbbbb16a ILT |
7140 | third_reload_reg, |
7141 | (enum insn_code) sri.icode)) | |
32e8bb8e ILT |
7142 | { |
7143 | icode = (enum insn_code) sri.icode; | |
7144 | third_reload_reg = 0; | |
7145 | } | |
367b1cf5 | 7146 | else |
32e8bb8e ILT |
7147 | { |
7148 | oldequiv = old; | |
7149 | real_oldequiv = real_old; | |
7150 | } | |
8a99f6f9 R |
7151 | } |
7152 | else if (sri.icode != CODE_FOR_nothing) | |
7153 | /* We currently lack a way to express this in reloads. */ | |
7154 | gcc_unreachable (); | |
7155 | else | |
7156 | { | |
7157 | sri2.icode = CODE_FOR_nothing; | |
7158 | sri2.prev_sri = &sri; | |
7159 | new_t_class = targetm.secondary_reload (1, real_oldequiv, | |
7160 | new_class, mode, &sri); | |
7161 | if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing) | |
32131a9c | 7162 | { |
8a99f6f9 R |
7163 | if (reload_adjust_reg_for_temp (&second_reload_reg, |
7164 | third_reload_reg, | |
7165 | new_class, mode)) | |
32e8bb8e ILT |
7166 | { |
7167 | third_reload_reg = 0; | |
7168 | tertiary_icode = (enum insn_code) sri2.icode; | |
7169 | } | |
367b1cf5 | 7170 | else |
32e8bb8e ILT |
7171 | { |
7172 | oldequiv = old; | |
7173 | real_oldequiv = real_old; | |
7174 | } | |
8a99f6f9 R |
7175 | } |
7176 | else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing) | |
7177 | { | |
7178 | rtx intermediate = second_reload_reg; | |
d30e8ef0 | 7179 | |
8a99f6f9 R |
7180 | if (reload_adjust_reg_for_temp (&intermediate, NULL, |
7181 | new_class, mode) | |
7182 | && reload_adjust_reg_for_icode (&third_reload_reg, NULL, | |
bbbbb16a ILT |
7183 | ((enum insn_code) |
7184 | sri2.icode))) | |
32131a9c | 7185 | { |
8a99f6f9 | 7186 | second_reload_reg = intermediate; |
32e8bb8e | 7187 | tertiary_icode = (enum insn_code) sri2.icode; |
8a99f6f9 R |
7188 | } |
7189 | else | |
32e8bb8e ILT |
7190 | { |
7191 | oldequiv = old; | |
7192 | real_oldequiv = real_old; | |
7193 | } | |
8a99f6f9 R |
7194 | } |
7195 | else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing) | |
7196 | { | |
7197 | rtx intermediate = second_reload_reg; | |
7198 | ||
7199 | if (reload_adjust_reg_for_temp (&intermediate, NULL, | |
7200 | new_class, mode) | |
7201 | && reload_adjust_reg_for_temp (&third_reload_reg, NULL, | |
7202 | new_t_class, mode)) | |
7203 | { | |
7204 | second_reload_reg = intermediate; | |
32e8bb8e | 7205 | tertiary_icode = (enum insn_code) sri2.icode; |
32131a9c | 7206 | } |
8a99f6f9 | 7207 | else |
32e8bb8e ILT |
7208 | { |
7209 | oldequiv = old; | |
7210 | real_oldequiv = real_old; | |
7211 | } | |
32131a9c | 7212 | } |
8a99f6f9 | 7213 | else |
32e8bb8e ILT |
7214 | { |
7215 | /* This could be handled more intelligently too. */ | |
7216 | oldequiv = old; | |
7217 | real_oldequiv = real_old; | |
7218 | } | |
32131a9c | 7219 | } |
367b1cf5 | 7220 | } |
32131a9c | 7221 | |
367b1cf5 BS |
7222 | /* If we still need a secondary reload register, check |
7223 | to see if it is being used as a scratch or intermediate | |
7224 | register and generate code appropriately. If we need | |
7225 | a scratch register, use REAL_OLDEQUIV since the form of | |
7226 | the insn may depend on the actual address if it is | |
7227 | a MEM. */ | |
546b63fb | 7228 | |
367b1cf5 BS |
7229 | if (second_reload_reg) |
7230 | { | |
7231 | if (icode != CODE_FOR_nothing) | |
32131a9c | 7232 | { |
8a99f6f9 R |
7233 | /* We'd have to add extra code to handle this case. */ |
7234 | gcc_assert (!third_reload_reg); | |
7235 | ||
367b1cf5 BS |
7236 | emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, |
7237 | second_reload_reg)); | |
07875628 | 7238 | special = 1; |
367b1cf5 BS |
7239 | } |
7240 | else | |
7241 | { | |
7242 | /* See if we need a scratch register to load the | |
7243 | intermediate register (a tertiary reload). */ | |
367b1cf5 BS |
7244 | if (tertiary_icode != CODE_FOR_nothing) |
7245 | { | |
367b1cf5 BS |
7246 | emit_insn ((GEN_FCN (tertiary_icode) |
7247 | (second_reload_reg, real_oldequiv, | |
7248 | third_reload_reg))); | |
7249 | } | |
8a99f6f9 R |
7250 | else if (third_reload_reg) |
7251 | { | |
7252 | gen_reload (third_reload_reg, real_oldequiv, | |
7253 | rl->opnum, | |
7254 | rl->when_needed); | |
7255 | gen_reload (second_reload_reg, third_reload_reg, | |
7256 | rl->opnum, | |
7257 | rl->when_needed); | |
7258 | } | |
367b1cf5 BS |
7259 | else |
7260 | gen_reload (second_reload_reg, real_oldequiv, | |
7261 | rl->opnum, | |
7262 | rl->when_needed); | |
32131a9c | 7263 | |
367b1cf5 BS |
7264 | oldequiv = second_reload_reg; |
7265 | } | |
7266 | } | |
7267 | } | |
32131a9c | 7268 | |
07875628 | 7269 | if (! special && ! rtx_equal_p (reloadreg, oldequiv)) |
367b1cf5 BS |
7270 | { |
7271 | rtx real_oldequiv = oldequiv; | |
7272 | ||
f8cfc6aa | 7273 | if ((REG_P (oldequiv) |
367b1cf5 BS |
7274 | && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER |
7275 | && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 | |
7276 | || reg_equiv_constant[REGNO (oldequiv)] != 0)) | |
7277 | || (GET_CODE (oldequiv) == SUBREG | |
f8cfc6aa | 7278 | && REG_P (SUBREG_REG (oldequiv)) |
367b1cf5 BS |
7279 | && (REGNO (SUBREG_REG (oldequiv)) |
7280 | >= FIRST_PSEUDO_REGISTER) | |
7281 | && ((reg_equiv_memory_loc | |
7282 | [REGNO (SUBREG_REG (oldequiv))] != 0) | |
7283 | || (reg_equiv_constant | |
716120a7 JJ |
7284 | [REGNO (SUBREG_REG (oldequiv))] != 0))) |
7285 | || (CONSTANT_P (oldequiv) | |
019d2e99 AS |
7286 | && (PREFERRED_RELOAD_CLASS (oldequiv, |
7287 | REGNO_REG_CLASS (REGNO (reloadreg))) | |
7288 | == NO_REGS))) | |
367b1cf5 BS |
7289 | real_oldequiv = rl->in; |
7290 | gen_reload (reloadreg, real_oldequiv, rl->opnum, | |
7291 | rl->when_needed); | |
7292 | } | |
32131a9c | 7293 | |
94bd63e5 | 7294 | if (flag_non_call_exceptions) |
1d65f45c | 7295 | copy_reg_eh_region_note_forward (insn, get_insns (), NULL); |
94bd63e5 | 7296 | |
367b1cf5 BS |
7297 | /* End this sequence. */ |
7298 | *where = get_insns (); | |
7299 | end_sequence (); | |
a6a2274a | 7300 | |
367b1cf5 BS |
7301 | /* Update reload_override_in so that delete_address_reloads_1 |
7302 | can see the actual register usage. */ | |
7303 | if (oldequiv_reg) | |
7304 | reload_override_in[j] = oldequiv; | |
7305 | } | |
32131a9c | 7306 | |
367b1cf5 BS |
7307 | /* Generate insns to for the output reload RL, which is for the insn described |
7308 | by CHAIN and has the number J. */ | |
7309 | static void | |
0c20a65f AJ |
7310 | emit_output_reload_insns (struct insn_chain *chain, struct reload *rl, |
7311 | int j) | |
367b1cf5 | 7312 | { |
fb959f72 | 7313 | rtx reloadreg; |
367b1cf5 BS |
7314 | rtx insn = chain->insn; |
7315 | int special = 0; | |
7316 | rtx old = rl->out; | |
fb959f72 | 7317 | enum machine_mode mode; |
367b1cf5 | 7318 | rtx p; |
fb959f72 | 7319 | rtx rl_reg_rtx; |
32131a9c | 7320 | |
367b1cf5 BS |
7321 | if (rl->when_needed == RELOAD_OTHER) |
7322 | start_sequence (); | |
7323 | else | |
7324 | push_to_sequence (output_reload_insns[rl->opnum]); | |
32131a9c | 7325 | |
fb959f72 RS |
7326 | rl_reg_rtx = reload_reg_rtx_for_output[j]; |
7327 | mode = GET_MODE (rl_reg_rtx); | |
546b63fb | 7328 | |
fb959f72 | 7329 | reloadreg = rl_reg_rtx; |
32131a9c | 7330 | |
367b1cf5 BS |
7331 | /* If we need two reload regs, set RELOADREG to the intermediate |
7332 | one, since it will be stored into OLD. We might need a secondary | |
7333 | register only for an input reload, so check again here. */ | |
32131a9c | 7334 | |
367b1cf5 BS |
7335 | if (rl->secondary_out_reload >= 0) |
7336 | { | |
7337 | rtx real_old = old; | |
8a99f6f9 R |
7338 | int secondary_reload = rl->secondary_out_reload; |
7339 | int tertiary_reload = rld[secondary_reload].secondary_out_reload; | |
cb2afeb3 | 7340 | |
f8cfc6aa | 7341 | if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER |
367b1cf5 BS |
7342 | && reg_equiv_mem[REGNO (old)] != 0) |
7343 | real_old = reg_equiv_mem[REGNO (old)]; | |
32131a9c | 7344 | |
48c54229 | 7345 | if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS) |
b60a8416 | 7346 | { |
367b1cf5 | 7347 | rtx second_reloadreg = reloadreg; |
8a99f6f9 | 7348 | reloadreg = rld[secondary_reload].reg_rtx; |
32131a9c | 7349 | |
367b1cf5 BS |
7350 | /* See if RELOADREG is to be used as a scratch register |
7351 | or as an intermediate register. */ | |
7352 | if (rl->secondary_out_icode != CODE_FOR_nothing) | |
7353 | { | |
8a99f6f9 R |
7354 | /* We'd have to add extra code to handle this case. */ |
7355 | gcc_assert (tertiary_reload < 0); | |
7356 | ||
367b1cf5 BS |
7357 | emit_insn ((GEN_FCN (rl->secondary_out_icode) |
7358 | (real_old, second_reloadreg, reloadreg))); | |
7359 | special = 1; | |
7360 | } | |
7361 | else | |
7362 | { | |
7363 | /* See if we need both a scratch and intermediate reload | |
7364 | register. */ | |
32131a9c | 7365 | |
367b1cf5 BS |
7366 | enum insn_code tertiary_icode |
7367 | = rld[secondary_reload].secondary_out_icode; | |
32131a9c | 7368 | |
8a99f6f9 R |
7369 | /* We'd have to add more code for quartary reloads. */ |
7370 | gcc_assert (tertiary_reload < 0 | |
7371 | || rld[tertiary_reload].secondary_out_reload < 0); | |
7372 | ||
367b1cf5 | 7373 | if (GET_MODE (reloadreg) != mode) |
f12448c8 | 7374 | reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); |
cb2afeb3 | 7375 | |
367b1cf5 BS |
7376 | if (tertiary_icode != CODE_FOR_nothing) |
7377 | { | |
8a99f6f9 | 7378 | rtx third_reloadreg = rld[tertiary_reload].reg_rtx; |
367b1cf5 BS |
7379 | rtx tem; |
7380 | ||
7381 | /* Copy primary reload reg to secondary reload reg. | |
7382 | (Note that these have been swapped above, then | |
78adc5a0 | 7383 | secondary reload reg to OLD using our insn.) */ |
367b1cf5 BS |
7384 | |
7385 | /* If REAL_OLD is a paradoxical SUBREG, remove it | |
7386 | and try to put the opposite SUBREG on | |
7387 | RELOADREG. */ | |
7388 | if (GET_CODE (real_old) == SUBREG | |
7389 | && (GET_MODE_SIZE (GET_MODE (real_old)) | |
7390 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) | |
7391 | && 0 != (tem = gen_lowpart_common | |
7392 | (GET_MODE (SUBREG_REG (real_old)), | |
7393 | reloadreg))) | |
7394 | real_old = SUBREG_REG (real_old), reloadreg = tem; | |
7395 | ||
7396 | gen_reload (reloadreg, second_reloadreg, | |
7397 | rl->opnum, rl->when_needed); | |
7398 | emit_insn ((GEN_FCN (tertiary_icode) | |
7399 | (real_old, reloadreg, third_reloadreg))); | |
7400 | special = 1; | |
7401 | } | |
05d10675 | 7402 | |
367b1cf5 | 7403 | else |
8a99f6f9 R |
7404 | { |
7405 | /* Copy between the reload regs here and then to | |
7406 | OUT later. */ | |
7407 | ||
7408 | gen_reload (reloadreg, second_reloadreg, | |
7409 | rl->opnum, rl->when_needed); | |
7410 | if (tertiary_reload >= 0) | |
7411 | { | |
7412 | rtx third_reloadreg = rld[tertiary_reload].reg_rtx; | |
cb2afeb3 | 7413 | |
8a99f6f9 R |
7414 | gen_reload (third_reloadreg, reloadreg, |
7415 | rl->opnum, rl->when_needed); | |
7416 | reloadreg = third_reloadreg; | |
7417 | } | |
7418 | } | |
a7911cd2 | 7419 | } |
367b1cf5 BS |
7420 | } |
7421 | } | |
32131a9c | 7422 | |
367b1cf5 BS |
7423 | /* Output the last reload insn. */ |
7424 | if (! special) | |
7425 | { | |
7426 | rtx set; | |
7427 | ||
7428 | /* Don't output the last reload if OLD is not the dest of | |
1d7254c5 | 7429 | INSN and is in the src and is clobbered by INSN. */ |
367b1cf5 | 7430 | if (! flag_expensive_optimizations |
f8cfc6aa | 7431 | || !REG_P (old) |
367b1cf5 BS |
7432 | || !(set = single_set (insn)) |
7433 | || rtx_equal_p (old, SET_DEST (set)) | |
7434 | || !reg_mentioned_p (old, SET_SRC (set)) | |
2ca39620 KK |
7435 | || !((REGNO (old) < FIRST_PSEUDO_REGISTER) |
7436 | && regno_clobbered_p (REGNO (old), insn, rl->mode, 0))) | |
367b1cf5 BS |
7437 | gen_reload (old, reloadreg, rl->opnum, |
7438 | rl->when_needed); | |
7439 | } | |
32131a9c | 7440 | |
367b1cf5 BS |
7441 | /* Look at all insns we emitted, just to be safe. */ |
7442 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2c3c49de | 7443 | if (INSN_P (p)) |
367b1cf5 BS |
7444 | { |
7445 | rtx pat = PATTERN (p); | |
546b63fb | 7446 | |
367b1cf5 BS |
7447 | /* If this output reload doesn't come from a spill reg, |
7448 | clear any memory of reloaded copies of the pseudo reg. | |
7449 | If this output reload comes from a spill reg, | |
7450 | reg_has_output_reload will make this do nothing. */ | |
7451 | note_stores (pat, forget_old_reloads_1, NULL); | |
cb2afeb3 | 7452 | |
fb959f72 | 7453 | if (reg_mentioned_p (rl_reg_rtx, pat)) |
367b1cf5 BS |
7454 | { |
7455 | rtx set = single_set (insn); | |
7456 | if (reload_spill_index[j] < 0 | |
7457 | && set | |
fb959f72 | 7458 | && SET_SRC (set) == rl_reg_rtx) |
367b1cf5 BS |
7459 | { |
7460 | int src = REGNO (SET_SRC (set)); | |
32131a9c | 7461 | |
367b1cf5 BS |
7462 | reload_spill_index[j] = src; |
7463 | SET_HARD_REG_BIT (reg_is_output_reload, src); | |
7464 | if (find_regno_note (insn, REG_DEAD, src)) | |
7465 | SET_HARD_REG_BIT (reg_reloaded_died, src); | |
7466 | } | |
fb959f72 | 7467 | if (HARD_REGISTER_P (rl_reg_rtx)) |
367b1cf5 BS |
7468 | { |
7469 | int s = rl->secondary_out_reload; | |
7470 | set = single_set (p); | |
7471 | /* If this reload copies only to the secondary reload | |
7472 | register, the secondary reload does the actual | |
7473 | store. */ | |
7474 | if (s >= 0 && set == NULL_RTX) | |
1d7254c5 KH |
7475 | /* We can't tell what function the secondary reload |
7476 | has and where the actual store to the pseudo is | |
7477 | made; leave new_spill_reg_store alone. */ | |
7478 | ; | |
367b1cf5 | 7479 | else if (s >= 0 |
fb959f72 | 7480 | && SET_SRC (set) == rl_reg_rtx |
367b1cf5 BS |
7481 | && SET_DEST (set) == rld[s].reg_rtx) |
7482 | { | |
7483 | /* Usually the next instruction will be the | |
7484 | secondary reload insn; if we can confirm | |
7485 | that it is, setting new_spill_reg_store to | |
7486 | that insn will allow an extra optimization. */ | |
7487 | rtx s_reg = rld[s].reg_rtx; | |
7488 | rtx next = NEXT_INSN (p); | |
7489 | rld[s].out = rl->out; | |
7490 | rld[s].out_reg = rl->out_reg; | |
7491 | set = single_set (next); | |
7492 | if (set && SET_SRC (set) == s_reg | |
7493 | && ! new_spill_reg_store[REGNO (s_reg)]) | |
7494 | { | |
7495 | SET_HARD_REG_BIT (reg_is_output_reload, | |
7496 | REGNO (s_reg)); | |
7497 | new_spill_reg_store[REGNO (s_reg)] = next; | |
7498 | } | |
7499 | } | |
7500 | else | |
fb959f72 | 7501 | new_spill_reg_store[REGNO (rl_reg_rtx)] = p; |
367b1cf5 BS |
7502 | } |
7503 | } | |
7504 | } | |
32131a9c | 7505 | |
367b1cf5 BS |
7506 | if (rl->when_needed == RELOAD_OTHER) |
7507 | { | |
2f937369 | 7508 | emit_insn (other_output_reload_insns[rl->opnum]); |
367b1cf5 BS |
7509 | other_output_reload_insns[rl->opnum] = get_insns (); |
7510 | } | |
7511 | else | |
7512 | output_reload_insns[rl->opnum] = get_insns (); | |
32131a9c | 7513 | |
94bd63e5 | 7514 | if (flag_non_call_exceptions) |
1d65f45c | 7515 | copy_reg_eh_region_note_forward (insn, get_insns (), NULL); |
94bd63e5 | 7516 | |
1d7254c5 | 7517 | end_sequence (); |
367b1cf5 | 7518 | } |
32131a9c | 7519 | |
367b1cf5 BS |
7520 | /* Do input reloading for reload RL, which is for the insn described by CHAIN |
7521 | and has the number J. */ | |
7522 | static void | |
0c20a65f | 7523 | do_input_reload (struct insn_chain *chain, struct reload *rl, int j) |
367b1cf5 | 7524 | { |
367b1cf5 | 7525 | rtx insn = chain->insn; |
3c0cb5de | 7526 | rtx old = (rl->in && MEM_P (rl->in) |
367b1cf5 | 7527 | ? rl->in_reg : rl->in); |
fb959f72 RS |
7528 | rtx reg_rtx = rl->reg_rtx; |
7529 | ||
7530 | if (old && reg_rtx) | |
7531 | { | |
7532 | enum machine_mode mode; | |
7533 | ||
7534 | /* Determine the mode to reload in. | |
7535 | This is very tricky because we have three to choose from. | |
7536 | There is the mode the insn operand wants (rl->inmode). | |
7537 | There is the mode of the reload register RELOADREG. | |
7538 | There is the intrinsic mode of the operand, which we could find | |
7539 | by stripping some SUBREGs. | |
7540 | It turns out that RELOADREG's mode is irrelevant: | |
7541 | we can change that arbitrarily. | |
7542 | ||
7543 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
7544 | then the reload reg may not support QImode moves, so use SImode. | |
7545 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
7546 | because the QImode value is in the least significant part of a | |
7547 | slot big enough for a SImode. If foo is some other sort of | |
7548 | memory reference, then it is impossible to reload this case, | |
7549 | so previous passes had better make sure this never happens. | |
7550 | ||
7551 | Then consider a one-word union which has SImode and one of its | |
7552 | members is a float, being fetched as (SUBREG:SF union:SI). | |
7553 | We must fetch that as SFmode because we could be loading into | |
7554 | a float-only register. In this case OLD's mode is correct. | |
7555 | ||
7556 | Consider an immediate integer: it has VOIDmode. Here we need | |
7557 | to get a mode from something else. | |
7558 | ||
7559 | In some cases, there is a fourth mode, the operand's | |
7560 | containing mode. If the insn specifies a containing mode for | |
7561 | this operand, it overrides all others. | |
7562 | ||
7563 | I am not sure whether the algorithm here is always right, | |
7564 | but it does the right things in those cases. */ | |
7565 | ||
7566 | mode = GET_MODE (old); | |
7567 | if (mode == VOIDmode) | |
7568 | mode = rl->inmode; | |
7569 | ||
7570 | /* We cannot use gen_lowpart_common since it can do the wrong thing | |
7571 | when REG_RTX has a multi-word mode. Note that REG_RTX must | |
7572 | always be a REG here. */ | |
7573 | if (GET_MODE (reg_rtx) != mode) | |
7574 | reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode); | |
7575 | } | |
7576 | reload_reg_rtx_for_input[j] = reg_rtx; | |
367b1cf5 BS |
7577 | |
7578 | if (old != 0 | |
7579 | /* AUTO_INC reloads need to be handled even if inherited. We got an | |
7580 | AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ | |
7581 | && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) | |
fb959f72 RS |
7582 | && ! rtx_equal_p (reg_rtx, old) |
7583 | && reg_rtx != 0) | |
1d813780 | 7584 | emit_input_reload_insns (chain, rld + j, old, j); |
32131a9c | 7585 | |
367b1cf5 BS |
7586 | /* When inheriting a wider reload, we have a MEM in rl->in, |
7587 | e.g. inheriting a SImode output reload for | |
7588 | (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ | |
7589 | if (optimize && reload_inherited[j] && rl->in | |
3c0cb5de JQ |
7590 | && MEM_P (rl->in) |
7591 | && MEM_P (rl->in_reg) | |
367b1cf5 BS |
7592 | && reload_spill_index[j] >= 0 |
7593 | && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) | |
4977bab6 | 7594 | rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; |
32131a9c | 7595 | |
367b1cf5 BS |
7596 | /* If we are reloading a register that was recently stored in with an |
7597 | output-reload, see if we can prove there was | |
7598 | actually no need to store the old value in it. */ | |
32131a9c | 7599 | |
367b1cf5 BS |
7600 | if (optimize |
7601 | && (reload_inherited[j] || reload_override_in[j]) | |
fb959f72 RS |
7602 | && reg_rtx |
7603 | && REG_P (reg_rtx) | |
7604 | && spill_reg_store[REGNO (reg_rtx)] != 0 | |
367b1cf5 BS |
7605 | #if 0 |
7606 | /* There doesn't seem to be any reason to restrict this to pseudos | |
7607 | and doing so loses in the case where we are copying from a | |
7608 | register of the wrong class. */ | |
fb959f72 | 7609 | && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) |
367b1cf5 BS |
7610 | #endif |
7611 | /* The insn might have already some references to stackslots | |
7612 | replaced by MEMs, while reload_out_reg still names the | |
7613 | original pseudo. */ | |
fb959f72 RS |
7614 | && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) |
7615 | || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg))) | |
7616 | delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx); | |
367b1cf5 | 7617 | } |
32131a9c | 7618 | |
367b1cf5 BS |
7619 | /* Do output reloading for reload RL, which is for the insn described by |
7620 | CHAIN and has the number J. | |
7621 | ??? At some point we need to support handling output reloads of | |
7622 | JUMP_INSNs or insns that set cc0. */ | |
7623 | static void | |
0c20a65f | 7624 | do_output_reload (struct insn_chain *chain, struct reload *rl, int j) |
367b1cf5 BS |
7625 | { |
7626 | rtx note, old; | |
7627 | rtx insn = chain->insn; | |
7628 | /* If this is an output reload that stores something that is | |
7629 | not loaded in this same reload, see if we can eliminate a previous | |
7630 | store. */ | |
7631 | rtx pseudo = rl->out_reg; | |
fb959f72 RS |
7632 | rtx reg_rtx = rl->reg_rtx; |
7633 | ||
7634 | if (rl->out && reg_rtx) | |
7635 | { | |
7636 | enum machine_mode mode; | |
7637 | ||
7638 | /* Determine the mode to reload in. | |
7639 | See comments above (for input reloading). */ | |
7640 | mode = GET_MODE (rl->out); | |
7641 | if (mode == VOIDmode) | |
7642 | { | |
7643 | /* VOIDmode should never happen for an output. */ | |
7644 | if (asm_noperands (PATTERN (insn)) < 0) | |
7645 | /* It's the compiler's fault. */ | |
7646 | fatal_insn ("VOIDmode on an output", insn); | |
7647 | error_for_asm (insn, "output operand is constant in %<asm%>"); | |
7648 | /* Prevent crash--use something we know is valid. */ | |
7649 | mode = word_mode; | |
7650 | rl->out = gen_rtx_REG (mode, REGNO (reg_rtx)); | |
7651 | } | |
7652 | if (GET_MODE (reg_rtx) != mode) | |
7653 | reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode); | |
7654 | } | |
7655 | reload_reg_rtx_for_output[j] = reg_rtx; | |
367b1cf5 BS |
7656 | |
7657 | if (pseudo | |
159d5964 | 7658 | && optimize |
f8cfc6aa | 7659 | && REG_P (pseudo) |
367b1cf5 BS |
7660 | && ! rtx_equal_p (rl->in_reg, pseudo) |
7661 | && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER | |
7662 | && reg_last_reload_reg[REGNO (pseudo)]) | |
7663 | { | |
7664 | int pseudo_no = REGNO (pseudo); | |
7665 | int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); | |
7666 | ||
7667 | /* We don't need to test full validity of last_regno for | |
7668 | inherit here; we only want to know if the store actually | |
7669 | matches the pseudo. */ | |
60ef417d GK |
7670 | if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno) |
7671 | && reg_reloaded_contents[last_regno] == pseudo_no | |
367b1cf5 BS |
7672 | && spill_reg_store[last_regno] |
7673 | && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) | |
fb959f72 | 7674 | delete_output_reload (insn, j, last_regno, reg_rtx); |
367b1cf5 | 7675 | } |
5e03c156 | 7676 | |
367b1cf5 BS |
7677 | old = rl->out_reg; |
7678 | if (old == 0 | |
fb959f72 RS |
7679 | || reg_rtx == 0 |
7680 | || rtx_equal_p (old, reg_rtx)) | |
367b1cf5 | 7681 | return; |
32131a9c | 7682 | |
367b1cf5 BS |
7683 | /* An output operand that dies right away does need a reload, |
7684 | but need not be copied from it. Show the new location in the | |
7685 | REG_UNUSED note. */ | |
f8cfc6aa | 7686 | if ((REG_P (old) || GET_CODE (old) == SCRATCH) |
367b1cf5 BS |
7687 | && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) |
7688 | { | |
fb959f72 | 7689 | XEXP (note, 0) = reg_rtx; |
367b1cf5 BS |
7690 | return; |
7691 | } | |
7692 | /* Likewise for a SUBREG of an operand that dies. */ | |
7693 | else if (GET_CODE (old) == SUBREG | |
f8cfc6aa | 7694 | && REG_P (SUBREG_REG (old)) |
367b1cf5 BS |
7695 | && 0 != (note = find_reg_note (insn, REG_UNUSED, |
7696 | SUBREG_REG (old)))) | |
7697 | { | |
fb959f72 | 7698 | XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx); |
367b1cf5 BS |
7699 | return; |
7700 | } | |
7701 | else if (GET_CODE (old) == SCRATCH) | |
7702 | /* If we aren't optimizing, there won't be a REG_UNUSED note, | |
7703 | but we don't want to make an output reload. */ | |
7704 | return; | |
1554c2c6 | 7705 | |
367b1cf5 | 7706 | /* If is a JUMP_INSN, we can't support output reloads yet. */ |
ce99549f | 7707 | gcc_assert (NONJUMP_INSN_P (insn)); |
5e03c156 | 7708 | |
367b1cf5 BS |
7709 | emit_output_reload_insns (chain, rld + j, j); |
7710 | } | |
1554c2c6 | 7711 | |
fb959f72 RS |
7712 | /* A reload copies values of MODE from register SRC to register DEST. |
7713 | Return true if it can be treated for inheritance purposes like a | |
7714 | group of reloads, each one reloading a single hard register. The | |
7715 | caller has already checked that (reg:MODE SRC) and (reg:MODE DEST) | |
7716 | occupy the same number of hard registers. */ | |
b5ba341f RS |
7717 | |
7718 | static bool | |
fb959f72 RS |
7719 | inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED, |
7720 | int src ATTRIBUTE_UNUSED, | |
7721 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
b5ba341f RS |
7722 | { |
7723 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
fb959f72 RS |
7724 | return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest]) |
7725 | && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src])); | |
b5ba341f RS |
7726 | #else |
7727 | return true; | |
7728 | #endif | |
7729 | } | |
7730 | ||
367b1cf5 | 7731 | /* Output insns to reload values in and out of the chosen reload regs. */ |
32131a9c | 7732 | |
367b1cf5 | 7733 | static void |
0c20a65f | 7734 | emit_reload_insns (struct insn_chain *chain) |
367b1cf5 BS |
7735 | { |
7736 | rtx insn = chain->insn; | |
32131a9c | 7737 | |
b3694847 | 7738 | int j; |
e6e52be0 | 7739 | |
367b1cf5 | 7740 | CLEAR_HARD_REG_SET (reg_reloaded_died); |
e6e52be0 | 7741 | |
367b1cf5 BS |
7742 | for (j = 0; j < reload_n_operands; j++) |
7743 | input_reload_insns[j] = input_address_reload_insns[j] | |
7744 | = inpaddr_address_reload_insns[j] | |
7745 | = output_reload_insns[j] = output_address_reload_insns[j] | |
7746 | = outaddr_address_reload_insns[j] | |
7747 | = other_output_reload_insns[j] = 0; | |
7748 | other_input_address_reload_insns = 0; | |
7749 | other_input_reload_insns = 0; | |
7750 | operand_reload_insns = 0; | |
7751 | other_operand_reload_insns = 0; | |
32131a9c | 7752 | |
850aac53 | 7753 | /* Dump reloads into the dump file. */ |
c263766c | 7754 | if (dump_file) |
850aac53 | 7755 | { |
c263766c RH |
7756 | fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); |
7757 | debug_reload_to_stream (dump_file); | |
850aac53 JL |
7758 | } |
7759 | ||
367b1cf5 BS |
7760 | /* Now output the instructions to copy the data into and out of the |
7761 | reload registers. Do these in the order that the reloads were reported, | |
7762 | since reloads of base and index registers precede reloads of operands | |
7763 | and the operands may need the base and index registers reloaded. */ | |
32131a9c | 7764 | |
367b1cf5 BS |
7765 | for (j = 0; j < n_reloads; j++) |
7766 | { | |
fb959f72 RS |
7767 | if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx)) |
7768 | { | |
7769 | unsigned int i; | |
7770 | ||
7771 | for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++) | |
7772 | new_spill_reg_store[i] = 0; | |
7773 | } | |
d7e0324f | 7774 | |
367b1cf5 BS |
7775 | do_input_reload (chain, rld + j, j); |
7776 | do_output_reload (chain, rld + j, j); | |
32131a9c RK |
7777 | } |
7778 | ||
546b63fb RK |
7779 | /* Now write all the insns we made for reloads in the order expected by |
7780 | the allocation functions. Prior to the insn being reloaded, we write | |
7781 | the following reloads: | |
7782 | ||
7783 | RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. | |
7784 | ||
2edc8d65 | 7785 | RELOAD_OTHER reloads. |
546b63fb | 7786 | |
47c8cf91 ILT |
7787 | For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed |
7788 | by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the | |
7789 | RELOAD_FOR_INPUT reload for the operand. | |
546b63fb | 7790 | |
893bc853 RK |
7791 | RELOAD_FOR_OPADDR_ADDRS reloads. |
7792 | ||
546b63fb RK |
7793 | RELOAD_FOR_OPERAND_ADDRESS reloads. |
7794 | ||
7795 | After the insn being reloaded, we write the following: | |
7796 | ||
47c8cf91 ILT |
7797 | For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed |
7798 | by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the | |
7799 | RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output | |
7800 | reloads for the operand. The RELOAD_OTHER output reloads are | |
7801 | output in descending order by reload number. */ | |
546b63fb | 7802 | |
a7102479 JH |
7803 | emit_insn_before (other_input_address_reload_insns, insn); |
7804 | emit_insn_before (other_input_reload_insns, insn); | |
546b63fb RK |
7805 | |
7806 | for (j = 0; j < reload_n_operands; j++) | |
7807 | { | |
a7102479 JH |
7808 | emit_insn_before (inpaddr_address_reload_insns[j], insn); |
7809 | emit_insn_before (input_address_reload_insns[j], insn); | |
7810 | emit_insn_before (input_reload_insns[j], insn); | |
546b63fb RK |
7811 | } |
7812 | ||
a7102479 JH |
7813 | emit_insn_before (other_operand_reload_insns, insn); |
7814 | emit_insn_before (operand_reload_insns, insn); | |
546b63fb RK |
7815 | |
7816 | for (j = 0; j < reload_n_operands; j++) | |
7817 | { | |
a7102479 JH |
7818 | rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn); |
7819 | x = emit_insn_after (output_address_reload_insns[j], x); | |
7820 | x = emit_insn_after (output_reload_insns[j], x); | |
7821 | emit_insn_after (other_output_reload_insns[j], x); | |
546b63fb RK |
7822 | } |
7823 | ||
32131a9c RK |
7824 | /* For all the spill regs newly reloaded in this instruction, |
7825 | record what they were reloaded from, so subsequent instructions | |
d445b551 RK |
7826 | can inherit the reloads. |
7827 | ||
7828 | Update spill_reg_store for the reloads of this insn. | |
e9e79d69 | 7829 | Copy the elements that were updated in the loop above. */ |
32131a9c RK |
7830 | |
7831 | for (j = 0; j < n_reloads; j++) | |
7832 | { | |
b3694847 SS |
7833 | int r = reload_order[j]; |
7834 | int i = reload_spill_index[r]; | |
32131a9c | 7835 | |
78a2bc08 | 7836 | /* If this is a non-inherited input reload from a pseudo, we must |
05d10675 BS |
7837 | clear any memory of a previous store to the same pseudo. Only do |
7838 | something if there will not be an output reload for the pseudo | |
7839 | being reloaded. */ | |
eceef4c9 | 7840 | if (rld[r].in_reg != 0 |
05d10675 BS |
7841 | && ! (reload_inherited[r] || reload_override_in[r])) |
7842 | { | |
eceef4c9 | 7843 | rtx reg = rld[r].in_reg; |
78a2bc08 | 7844 | |
05d10675 | 7845 | if (GET_CODE (reg) == SUBREG) |
78a2bc08 | 7846 | reg = SUBREG_REG (reg); |
05d10675 | 7847 | |
f8cfc6aa | 7848 | if (REG_P (reg) |
78a2bc08 | 7849 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER |
2c61f5f1 | 7850 | && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg))) |
78a2bc08 R |
7851 | { |
7852 | int nregno = REGNO (reg); | |
7853 | ||
7854 | if (reg_last_reload_reg[nregno]) | |
05d10675 BS |
7855 | { |
7856 | int last_regno = REGNO (reg_last_reload_reg[nregno]); | |
78a2bc08 | 7857 | |
05d10675 | 7858 | if (reg_reloaded_contents[last_regno] == nregno) |
78a2bc08 | 7859 | spill_reg_store[last_regno] = 0; |
05d10675 | 7860 | } |
78a2bc08 R |
7861 | } |
7862 | } | |
05d10675 | 7863 | |
e6e52be0 | 7864 | /* I is nonneg if this reload used a register. |
eceef4c9 | 7865 | If rld[r].reg_rtx is 0, this is an optional reload |
51f0c3b7 | 7866 | that we opted to ignore. */ |
d445b551 | 7867 | |
eceef4c9 | 7868 | if (i >= 0 && rld[r].reg_rtx != 0) |
32131a9c | 7869 | { |
66fd46b6 | 7870 | int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)]; |
32131a9c RK |
7871 | int k; |
7872 | ||
51f0c3b7 JW |
7873 | /* For a multi register reload, we need to check if all or part |
7874 | of the value lives to the end. */ | |
32131a9c | 7875 | for (k = 0; k < nr; k++) |
fb959f72 RS |
7876 | if (reload_reg_reaches_end_p (i + k, rld[r].opnum, |
7877 | rld[r].when_needed)) | |
7878 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
32131a9c | 7879 | |
fb959f72 RS |
7880 | /* Maybe the spill reg contains a copy of reload_out. */ |
7881 | if (rld[r].out != 0 | |
7882 | && (REG_P (rld[r].out) | |
cb2afeb3 | 7883 | #ifdef AUTO_INC_DEC |
fb959f72 | 7884 | || ! rld[r].out_reg |
cb2afeb3 | 7885 | #endif |
fb959f72 RS |
7886 | || REG_P (rld[r].out_reg))) |
7887 | { | |
7888 | rtx reg; | |
7889 | enum machine_mode mode; | |
7890 | int regno, nregs; | |
7891 | ||
7892 | reg = reload_reg_rtx_for_output[r]; | |
7893 | mode = GET_MODE (reg); | |
7894 | regno = REGNO (reg); | |
7895 | nregs = hard_regno_nregs[regno][mode]; | |
7896 | if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum, | |
7897 | rld[r].when_needed)) | |
51f0c3b7 | 7898 | { |
f8cfc6aa | 7899 | rtx out = (REG_P (rld[r].out) |
eceef4c9 BS |
7900 | ? rld[r].out |
7901 | : rld[r].out_reg | |
7902 | ? rld[r].out_reg | |
7903 | /* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); | |
fb959f72 RS |
7904 | int out_regno = REGNO (out); |
7905 | int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1 | |
7906 | : hard_regno_nregs[out_regno][mode]); | |
b5ba341f | 7907 | bool piecemeal; |
51f0c3b7 | 7908 | |
fb959f72 RS |
7909 | spill_reg_store[regno] = new_spill_reg_store[regno]; |
7910 | spill_reg_stored_to[regno] = out; | |
7911 | reg_last_reload_reg[out_regno] = reg; | |
51f0c3b7 | 7912 | |
fb959f72 RS |
7913 | piecemeal = (HARD_REGISTER_NUM_P (out_regno) |
7914 | && nregs == out_nregs | |
7915 | && inherit_piecemeal_p (out_regno, regno, mode)); | |
b5ba341f | 7916 | |
fb959f72 | 7917 | /* If OUT_REGNO is a hard register, it may occupy more than |
05d10675 | 7918 | one register. If it does, say what is in the |
51f0c3b7 JW |
7919 | rest of the registers assuming that both registers |
7920 | agree on how many words the object takes. If not, | |
7921 | invalidate the subsequent registers. */ | |
7922 | ||
fb959f72 RS |
7923 | if (HARD_REGISTER_NUM_P (out_regno)) |
7924 | for (k = 1; k < out_nregs; k++) | |
7925 | reg_last_reload_reg[out_regno + k] | |
7926 | = (piecemeal ? regno_reg_rtx[regno + k] : 0); | |
51f0c3b7 JW |
7927 | |
7928 | /* Now do the inverse operation. */ | |
fb959f72 | 7929 | for (k = 0; k < nregs; k++) |
51f0c3b7 | 7930 | { |
fb959f72 RS |
7931 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k); |
7932 | reg_reloaded_contents[regno + k] | |
7933 | = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal | |
7934 | ? out_regno | |
7935 | : out_regno + k); | |
7936 | reg_reloaded_insn[regno + k] = insn; | |
7937 | SET_HARD_REG_BIT (reg_reloaded_valid, regno + k); | |
7938 | if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode)) | |
7939 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, | |
7940 | regno + k); | |
7941 | else | |
7942 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, | |
7943 | regno + k); | |
51f0c3b7 JW |
7944 | } |
7945 | } | |
fb959f72 RS |
7946 | } |
7947 | /* Maybe the spill reg contains a copy of reload_in. Only do | |
7948 | something if there will not be an output reload for | |
7949 | the register being reloaded. */ | |
7950 | else if (rld[r].out_reg == 0 | |
7951 | && rld[r].in != 0 | |
7952 | && ((REG_P (rld[r].in) | |
7953 | && !HARD_REGISTER_P (rld[r].in) | |
7954 | && !REGNO_REG_SET_P (®_has_output_reload, | |
7955 | REGNO (rld[r].in))) | |
7956 | || (REG_P (rld[r].in_reg) | |
7957 | && !REGNO_REG_SET_P (®_has_output_reload, | |
7958 | REGNO (rld[r].in_reg)))) | |
7959 | && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn))) | |
7960 | { | |
7961 | rtx reg; | |
7962 | enum machine_mode mode; | |
7963 | int regno, nregs; | |
7964 | ||
7965 | reg = reload_reg_rtx_for_input[r]; | |
7966 | mode = GET_MODE (reg); | |
7967 | regno = REGNO (reg); | |
7968 | nregs = hard_regno_nregs[regno][mode]; | |
7969 | if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum, | |
7970 | rld[r].when_needed)) | |
51f0c3b7 | 7971 | { |
fb959f72 RS |
7972 | int in_regno; |
7973 | int in_nregs; | |
e3e9336f | 7974 | rtx in; |
b5ba341f | 7975 | bool piecemeal; |
d445b551 | 7976 | |
f8cfc6aa | 7977 | if (REG_P (rld[r].in) |
eceef4c9 | 7978 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) |
e3e9336f | 7979 | in = rld[r].in; |
f8cfc6aa | 7980 | else if (REG_P (rld[r].in_reg)) |
e3e9336f | 7981 | in = rld[r].in_reg; |
cb2afeb3 | 7982 | else |
e3e9336f | 7983 | in = XEXP (rld[r].in_reg, 0); |
fb959f72 | 7984 | in_regno = REGNO (in); |
d08ea79f | 7985 | |
fb959f72 RS |
7986 | in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1 |
7987 | : hard_regno_nregs[in_regno][mode]); | |
05d10675 | 7988 | |
fb959f72 | 7989 | reg_last_reload_reg[in_regno] = reg; |
51f0c3b7 | 7990 | |
fb959f72 RS |
7991 | piecemeal = (HARD_REGISTER_NUM_P (in_regno) |
7992 | && nregs == in_nregs | |
7993 | && inherit_piecemeal_p (regno, in_regno, mode)); | |
b5ba341f | 7994 | |
fb959f72 RS |
7995 | if (HARD_REGISTER_NUM_P (in_regno)) |
7996 | for (k = 1; k < in_nregs; k++) | |
7997 | reg_last_reload_reg[in_regno + k] | |
7998 | = (piecemeal ? regno_reg_rtx[regno + k] : 0); | |
51f0c3b7 JW |
7999 | |
8000 | /* Unless we inherited this reload, show we haven't | |
cb2afeb3 R |
8001 | recently done a store. |
8002 | Previous stores of inherited auto_inc expressions | |
8003 | also have to be discarded. */ | |
8004 | if (! reload_inherited[r] | |
eceef4c9 | 8005 | || (rld[r].out && ! rld[r].out_reg)) |
fb959f72 | 8006 | spill_reg_store[regno] = 0; |
51f0c3b7 | 8007 | |
fb959f72 | 8008 | for (k = 0; k < nregs; k++) |
51f0c3b7 | 8009 | { |
fb959f72 RS |
8010 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k); |
8011 | reg_reloaded_contents[regno + k] | |
8012 | = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal | |
8013 | ? in_regno | |
8014 | : in_regno + k); | |
8015 | reg_reloaded_insn[regno + k] = insn; | |
8016 | SET_HARD_REG_BIT (reg_reloaded_valid, regno + k); | |
8017 | if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode)) | |
8018 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, | |
8019 | regno + k); | |
8020 | else | |
8021 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, | |
8022 | regno + k); | |
51f0c3b7 JW |
8023 | } |
8024 | } | |
8025 | } | |
32131a9c RK |
8026 | } |
8027 | ||
8028 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
8029 | It's reenabled in 1.35 because supposedly nothing else | |
8030 | deals with this problem. */ | |
8031 | ||
8032 | /* If a register gets output-reloaded from a non-spill register, | |
8033 | that invalidates any previous reloaded copy of it. | |
8034 | But forget_old_reloads_1 won't get to see it, because | |
b81ac288 PB |
8035 | it thinks only about the original insn. So invalidate it here. |
8036 | Also do the same thing for RELOAD_OTHER constraints where the | |
8037 | output is discarded. */ | |
fb959f72 | 8038 | if (i < 0 |
b81ac288 PB |
8039 | && ((rld[r].out != 0 |
8040 | && (REG_P (rld[r].out) | |
8041 | || (MEM_P (rld[r].out) | |
8042 | && REG_P (rld[r].out_reg)))) | |
8043 | || (rld[r].out == 0 && rld[r].out_reg | |
f8cfc6aa | 8044 | && REG_P (rld[r].out_reg)))) |
32131a9c | 8045 | { |
b81ac288 | 8046 | rtx out = ((rld[r].out && REG_P (rld[r].out)) |
eceef4c9 | 8047 | ? rld[r].out : rld[r].out_reg); |
fb959f72 RS |
8048 | int out_regno = REGNO (out); |
8049 | enum machine_mode mode = GET_MODE (out); | |
92d54592 RS |
8050 | |
8051 | /* REG_RTX is now set or clobbered by the main instruction. | |
8052 | As the comment above explains, forget_old_reloads_1 only | |
8053 | sees the original instruction, and there is no guarantee | |
8054 | that the original instruction also clobbered REG_RTX. | |
8055 | For example, if find_reloads sees that the input side of | |
8056 | a matched operand pair dies in this instruction, it may | |
8057 | use the input register as the reload register. | |
8058 | ||
8059 | Calling forget_old_reloads_1 is a waste of effort if | |
8060 | REG_RTX is also the output register. | |
8061 | ||
8062 | If we know that REG_RTX holds the value of a pseudo | |
8063 | register, the code after the call will record that fact. */ | |
8064 | if (rld[r].reg_rtx && rld[r].reg_rtx != out) | |
8065 | forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL); | |
8066 | ||
fb959f72 | 8067 | if (!HARD_REGISTER_NUM_P (out_regno)) |
cb2afeb3 | 8068 | { |
6a651371 | 8069 | rtx src_reg, store_insn = NULL_RTX; |
cb2afeb3 | 8070 | |
fb959f72 | 8071 | reg_last_reload_reg[out_regno] = 0; |
cb2afeb3 R |
8072 | |
8073 | /* If we can find a hard register that is stored, record | |
8074 | the storing insn so that we may delete this insn with | |
8075 | delete_output_reload. */ | |
fb959f72 | 8076 | src_reg = reload_reg_rtx_for_output[r]; |
cb2afeb3 R |
8077 | |
8078 | /* If this is an optional reload, try to find the source reg | |
8079 | from an input reload. */ | |
8080 | if (! src_reg) | |
8081 | { | |
8082 | rtx set = single_set (insn); | |
eceef4c9 | 8083 | if (set && SET_DEST (set) == rld[r].out) |
cb2afeb3 R |
8084 | { |
8085 | int k; | |
8086 | ||
8087 | src_reg = SET_SRC (set); | |
8088 | store_insn = insn; | |
8089 | for (k = 0; k < n_reloads; k++) | |
8090 | { | |
eceef4c9 | 8091 | if (rld[k].in == src_reg) |
cb2afeb3 | 8092 | { |
fb959f72 | 8093 | src_reg = reload_reg_rtx_for_input[k]; |
cb2afeb3 R |
8094 | break; |
8095 | } | |
8096 | } | |
8097 | } | |
8098 | } | |
8099 | else | |
8100 | store_insn = new_spill_reg_store[REGNO (src_reg)]; | |
f8cfc6aa | 8101 | if (src_reg && REG_P (src_reg) |
cb2afeb3 R |
8102 | && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) |
8103 | { | |
fb959f72 RS |
8104 | int src_regno, src_nregs, k; |
8105 | rtx note; | |
8106 | ||
8107 | gcc_assert (GET_MODE (src_reg) == mode); | |
8108 | src_regno = REGNO (src_reg); | |
8109 | src_nregs = hard_regno_nregs[src_regno][mode]; | |
cb2afeb3 R |
8110 | /* The place where to find a death note varies with |
8111 | PRESERVE_DEATH_INFO_REGNO_P . The condition is not | |
8112 | necessarily checked exactly in the code that moves | |
8113 | notes, so just check both locations. */ | |
fb959f72 | 8114 | note = find_regno_note (insn, REG_DEAD, src_regno); |
1558b970 | 8115 | if (! note && store_insn) |
cb2afeb3 | 8116 | note = find_regno_note (store_insn, REG_DEAD, src_regno); |
fb959f72 | 8117 | for (k = 0; k < src_nregs; k++) |
cb2afeb3 | 8118 | { |
fb959f72 RS |
8119 | spill_reg_store[src_regno + k] = store_insn; |
8120 | spill_reg_stored_to[src_regno + k] = out; | |
8121 | reg_reloaded_contents[src_regno + k] = out_regno; | |
8122 | reg_reloaded_insn[src_regno + k] = store_insn; | |
8123 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k); | |
8124 | SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k); | |
8125 | if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k, | |
8126 | mode)) | |
e3e9336f | 8127 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, |
fb959f72 RS |
8128 | src_regno + k); |
8129 | else | |
8130 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, | |
8131 | src_regno + k); | |
8132 | SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k); | |
cb2afeb3 R |
8133 | if (note) |
8134 | SET_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
8135 | else | |
8136 | CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
8137 | } | |
fb959f72 | 8138 | reg_last_reload_reg[out_regno] = src_reg; |
9532c14f UW |
8139 | /* We have to set reg_has_output_reload here, or else |
8140 | forget_old_reloads_1 will clear reg_last_reload_reg | |
8141 | right away. */ | |
2c61f5f1 | 8142 | SET_REGNO_REG_SET (®_has_output_reload, |
fb959f72 | 8143 | out_regno); |
cb2afeb3 R |
8144 | } |
8145 | } | |
c7093272 RK |
8146 | else |
8147 | { | |
fb959f72 | 8148 | int k, out_nregs = hard_regno_nregs[out_regno][mode]; |
36281332 | 8149 | |
fb959f72 RS |
8150 | for (k = 0; k < out_nregs; k++) |
8151 | reg_last_reload_reg[out_regno + k] = 0; | |
c7093272 | 8152 | } |
32131a9c RK |
8153 | } |
8154 | } | |
e6e52be0 | 8155 | IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); |
32131a9c RK |
8156 | } |
8157 | \f | |
ff0d9879 HPN |
8158 | /* Go through the motions to emit INSN and test if it is strictly valid. |
8159 | Return the emitted insn if valid, else return NULL. */ | |
8160 | ||
8161 | static rtx | |
8162 | emit_insn_if_valid_for_reload (rtx insn) | |
8163 | { | |
8164 | rtx last = get_last_insn (); | |
8165 | int code; | |
8166 | ||
8167 | insn = emit_insn (insn); | |
8168 | code = recog_memoized (insn); | |
8169 | ||
8170 | if (code >= 0) | |
8171 | { | |
8172 | extract_insn (insn); | |
8173 | /* We want constrain operands to treat this insn strictly in its | |
8174 | validity determination, i.e., the way it would after reload has | |
8175 | completed. */ | |
8176 | if (constrain_operands (1)) | |
8177 | return insn; | |
8178 | } | |
8179 | ||
8180 | delete_insns_since (last); | |
8181 | return NULL; | |
8182 | } | |
8183 | ||
5e03c156 RK |
8184 | /* Emit code to perform a reload from IN (which may be a reload register) to |
8185 | OUT (which may also be a reload register). IN or OUT is from operand | |
05d10675 | 8186 | OPNUM with reload type TYPE. |
546b63fb | 8187 | |
3c3eeea6 | 8188 | Returns first insn emitted. */ |
32131a9c | 8189 | |
bf9a0db3 | 8190 | static rtx |
0c20a65f | 8191 | gen_reload (rtx out, rtx in, int opnum, enum reload_type type) |
32131a9c | 8192 | { |
546b63fb | 8193 | rtx last = get_last_insn (); |
7a5b18b0 RK |
8194 | rtx tem; |
8195 | ||
8196 | /* If IN is a paradoxical SUBREG, remove it and try to put the | |
8197 | opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ | |
8198 | if (GET_CODE (in) == SUBREG | |
8199 | && (GET_MODE_SIZE (GET_MODE (in)) | |
8200 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
8201 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) | |
8202 | in = SUBREG_REG (in), out = tem; | |
8203 | else if (GET_CODE (out) == SUBREG | |
eceef4c9 BS |
8204 | && (GET_MODE_SIZE (GET_MODE (out)) |
8205 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
8206 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) | |
7a5b18b0 | 8207 | out = SUBREG_REG (out), in = tem; |
32131a9c | 8208 | |
a8fdc208 | 8209 | /* How to do this reload can get quite tricky. Normally, we are being |
32131a9c RK |
8210 | asked to reload a simple operand, such as a MEM, a constant, or a pseudo |
8211 | register that didn't get a hard register. In that case we can just | |
8212 | call emit_move_insn. | |
8213 | ||
a7fd196c JW |
8214 | We can also be asked to reload a PLUS that adds a register or a MEM to |
8215 | another register, constant or MEM. This can occur during frame pointer | |
8216 | elimination and while reloading addresses. This case is handled by | |
8217 | trying to emit a single insn to perform the add. If it is not valid, | |
8218 | we use a two insn sequence. | |
32131a9c | 8219 | |
ff0d9879 HPN |
8220 | Or we can be asked to reload an unary operand that was a fragment of |
8221 | an addressing mode, into a register. If it isn't recognized as-is, | |
8222 | we try making the unop operand and the reload-register the same: | |
8223 | (set reg:X (unop:X expr:Y)) | |
8224 | -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)). | |
8225 | ||
32131a9c RK |
8226 | Finally, we could be called to handle an 'o' constraint by putting |
8227 | an address into a register. In that case, we first try to do this | |
8228 | with a named pattern of "reload_load_address". If no such pattern | |
8229 | exists, we just emit a SET insn and hope for the best (it will normally | |
8230 | be valid on machines that use 'o'). | |
8231 | ||
8232 | This entire process is made complex because reload will never | |
8233 | process the insns we generate here and so we must ensure that | |
8234 | they will fit their constraints and also by the fact that parts of | |
8235 | IN might be being reloaded separately and replaced with spill registers. | |
8236 | Because of this, we are, in some sense, just guessing the right approach | |
8237 | here. The one listed above seems to work. | |
8238 | ||
8239 | ??? At some point, this whole thing needs to be rethought. */ | |
8240 | ||
8241 | if (GET_CODE (in) == PLUS | |
f8cfc6aa | 8242 | && (REG_P (XEXP (in, 0)) |
5c6b1bd2 | 8243 | || GET_CODE (XEXP (in, 0)) == SUBREG |
3c0cb5de | 8244 | || MEM_P (XEXP (in, 0))) |
f8cfc6aa | 8245 | && (REG_P (XEXP (in, 1)) |
5c6b1bd2 | 8246 | || GET_CODE (XEXP (in, 1)) == SUBREG |
a7fd196c | 8247 | || CONSTANT_P (XEXP (in, 1)) |
3c0cb5de | 8248 | || MEM_P (XEXP (in, 1)))) |
32131a9c | 8249 | { |
a7fd196c JW |
8250 | /* We need to compute the sum of a register or a MEM and another |
8251 | register, constant, or MEM, and put it into the reload | |
3002e160 JW |
8252 | register. The best possible way of doing this is if the machine |
8253 | has a three-operand ADD insn that accepts the required operands. | |
32131a9c RK |
8254 | |
8255 | The simplest approach is to try to generate such an insn and see if it | |
8256 | is recognized and matches its constraints. If so, it can be used. | |
8257 | ||
8258 | It might be better not to actually emit the insn unless it is valid, | |
0009eff2 | 8259 | but we need to pass the insn as an operand to `recog' and |
0eadeb15 | 8260 | `extract_insn' and it is simpler to emit and then delete the insn if |
0009eff2 | 8261 | not valid than to dummy things up. */ |
a8fdc208 | 8262 | |
af929c62 | 8263 | rtx op0, op1, tem, insn; |
32131a9c | 8264 | int code; |
a8fdc208 | 8265 | |
af929c62 RK |
8266 | op0 = find_replacement (&XEXP (in, 0)); |
8267 | op1 = find_replacement (&XEXP (in, 1)); | |
8268 | ||
32131a9c RK |
8269 | /* Since constraint checking is strict, commutativity won't be |
8270 | checked, so we need to do that here to avoid spurious failure | |
8271 | if the add instruction is two-address and the second operand | |
8272 | of the add is the same as the reload reg, which is frequently | |
8273 | the case. If the insn would be A = B + A, rearrange it so | |
0f41302f | 8274 | it will be A = A + B as constrain_operands expects. */ |
a8fdc208 | 8275 | |
f8cfc6aa | 8276 | if (REG_P (XEXP (in, 1)) |
5e03c156 | 8277 | && REGNO (out) == REGNO (XEXP (in, 1))) |
af929c62 RK |
8278 | tem = op0, op0 = op1, op1 = tem; |
8279 | ||
8280 | if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) | |
38a448ca | 8281 | in = gen_rtx_PLUS (GET_MODE (in), op0, op1); |
32131a9c | 8282 | |
ff0d9879 HPN |
8283 | insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in)); |
8284 | if (insn) | |
8285 | return insn; | |
32131a9c RK |
8286 | |
8287 | /* If that failed, we must use a conservative two-insn sequence. | |
09522f21 FS |
8288 | |
8289 | Use a move to copy one operand into the reload register. Prefer | |
8290 | to reload a constant, MEM or pseudo since the move patterns can | |
8291 | handle an arbitrary operand. If OP1 is not a constant, MEM or | |
8292 | pseudo and OP1 is not a valid operand for an add instruction, then | |
8293 | reload OP1. | |
8294 | ||
8295 | After reloading one of the operands into the reload register, add | |
8296 | the reload register to the output register. | |
32131a9c RK |
8297 | |
8298 | If there is another way to do this for a specific machine, a | |
8299 | DEFINE_PEEPHOLE should be specified that recognizes the sequence | |
8300 | we emit below. */ | |
8301 | ||
166cdb08 | 8302 | code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code; |
09522f21 | 8303 | |
3c0cb5de | 8304 | if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG |
f8cfc6aa | 8305 | || (REG_P (op1) |
09522f21 FS |
8306 | && REGNO (op1) >= FIRST_PSEUDO_REGISTER) |
8307 | || (code != CODE_FOR_nothing | |
a995e389 RH |
8308 | && ! ((*insn_data[code].operand[2].predicate) |
8309 | (op1, insn_data[code].operand[2].mode)))) | |
af929c62 | 8310 | tem = op0, op0 = op1, op1 = tem; |
32131a9c | 8311 | |
5c6b1bd2 | 8312 | gen_reload (out, op0, opnum, type); |
39b56c2a | 8313 | |
5e03c156 | 8314 | /* If OP0 and OP1 are the same, we can use OUT for OP1. |
39b56c2a RK |
8315 | This fixes a problem on the 32K where the stack pointer cannot |
8316 | be used as an operand of an add insn. */ | |
8317 | ||
8318 | if (rtx_equal_p (op0, op1)) | |
5e03c156 | 8319 | op1 = out; |
39b56c2a | 8320 | |
ff0d9879 HPN |
8321 | insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1)); |
8322 | if (insn) | |
c77c9766 | 8323 | { |
ff0d9879 | 8324 | /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ |
a31830a7 | 8325 | set_unique_reg_note (insn, REG_EQUIV, in); |
ff0d9879 | 8326 | return insn; |
c77c9766 RK |
8327 | } |
8328 | ||
ff0d9879 HPN |
8329 | /* If that failed, copy the address register to the reload register. |
8330 | Then add the constant to the reload register. */ | |
c77c9766 | 8331 | |
8c74fb06 | 8332 | gcc_assert (!reg_overlap_mentioned_p (out, op0)); |
5c6b1bd2 | 8333 | gen_reload (out, op1, opnum, type); |
4117a96b | 8334 | insn = emit_insn (gen_add2_insn (out, op0)); |
a31830a7 | 8335 | set_unique_reg_note (insn, REG_EQUIV, in); |
32131a9c RK |
8336 | } |
8337 | ||
0dadecf6 RK |
8338 | #ifdef SECONDARY_MEMORY_NEEDED |
8339 | /* If we need a memory location to do the move, do it that way. */ | |
d47c3b4e AP |
8340 | else if ((REG_P (in) |
8341 | || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in)))) | |
344b78b8 | 8342 | && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER |
d47c3b4e AP |
8343 | && (REG_P (out) |
8344 | || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out)))) | |
344b78b8 JH |
8345 | && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER |
8346 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)), | |
8347 | REGNO_REG_CLASS (reg_or_subregno (out)), | |
5e03c156 | 8348 | GET_MODE (out))) |
0dadecf6 RK |
8349 | { |
8350 | /* Get the memory to use and rewrite both registers to its mode. */ | |
5e03c156 | 8351 | rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); |
0dadecf6 | 8352 | |
5e03c156 | 8353 | if (GET_MODE (loc) != GET_MODE (out)) |
38a448ca | 8354 | out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); |
0dadecf6 RK |
8355 | |
8356 | if (GET_MODE (loc) != GET_MODE (in)) | |
38a448ca | 8357 | in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); |
0dadecf6 | 8358 | |
5c6b1bd2 RK |
8359 | gen_reload (loc, in, opnum, type); |
8360 | gen_reload (out, loc, opnum, type); | |
0dadecf6 RK |
8361 | } |
8362 | #endif | |
ff0d9879 HPN |
8363 | else if (REG_P (out) && UNARY_P (in)) |
8364 | { | |
8365 | rtx insn; | |
8366 | rtx op1; | |
8367 | rtx out_moded; | |
8368 | rtx set; | |
0dadecf6 | 8369 | |
d0ab13fd R |
8370 | op1 = find_replacement (&XEXP (in, 0)); |
8371 | if (op1 != XEXP (in, 0)) | |
8372 | in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1); | |
8373 | ||
ff0d9879 HPN |
8374 | /* First, try a plain SET. */ |
8375 | set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in)); | |
8376 | if (set) | |
8377 | return set; | |
8378 | ||
8379 | /* If that failed, move the inner operand to the reload | |
8380 | register, and try the same unop with the inner expression | |
8381 | replaced with the reload register. */ | |
ff0d9879 HPN |
8382 | |
8383 | if (GET_MODE (op1) != GET_MODE (out)) | |
8384 | out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out)); | |
8385 | else | |
8386 | out_moded = out; | |
8387 | ||
8388 | gen_reload (out_moded, op1, opnum, type); | |
8389 | ||
8390 | insn | |
8391 | = gen_rtx_SET (VOIDmode, out, | |
8392 | gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), | |
8393 | out_moded)); | |
8394 | insn = emit_insn_if_valid_for_reload (insn); | |
8395 | if (insn) | |
8396 | { | |
a31830a7 | 8397 | set_unique_reg_note (insn, REG_EQUIV, in); |
ff0d9879 HPN |
8398 | return insn; |
8399 | } | |
8400 | ||
8401 | fatal_insn ("Failure trying to reload:", set); | |
8402 | } | |
32131a9c | 8403 | /* If IN is a simple operand, use gen_move_insn. */ |
ec8e098d | 8404 | else if (OBJECT_P (in) || GET_CODE (in) == SUBREG) |
8c339083 RS |
8405 | { |
8406 | tem = emit_insn (gen_move_insn (out, in)); | |
cf7c4aa6 | 8407 | /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */ |
8c339083 RS |
8408 | mark_jump_label (in, tem, 0); |
8409 | } | |
32131a9c RK |
8410 | |
8411 | #ifdef HAVE_reload_load_address | |
8412 | else if (HAVE_reload_load_address) | |
5e03c156 | 8413 | emit_insn (gen_reload_load_address (out, in)); |
32131a9c RK |
8414 | #endif |
8415 | ||
5e03c156 | 8416 | /* Otherwise, just write (set OUT IN) and hope for the best. */ |
32131a9c | 8417 | else |
38a448ca | 8418 | emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
8419 | |
8420 | /* Return the first insn emitted. | |
546b63fb | 8421 | We can not just return get_last_insn, because there may have |
32131a9c RK |
8422 | been multiple instructions emitted. Also note that gen_move_insn may |
8423 | emit more than one insn itself, so we can not assume that there is one | |
8424 | insn emitted per emit_insn_before call. */ | |
8425 | ||
546b63fb | 8426 | return last ? NEXT_INSN (last) : get_insns (); |
32131a9c RK |
8427 | } |
8428 | \f | |
cda94cbb RH |
8429 | /* Delete a previously made output-reload whose result we now believe |
8430 | is not needed. First we double-check. | |
32131a9c RK |
8431 | |
8432 | INSN is the insn now being processed. | |
cb2afeb3 R |
8433 | LAST_RELOAD_REG is the hard register number for which we want to delete |
8434 | the last output reload. | |
8435 | J is the reload-number that originally used REG. The caller has made | |
fb959f72 RS |
8436 | certain that reload J doesn't use REG any longer for input. |
8437 | NEW_RELOAD_REG is reload register that reload J is using for REG. */ | |
32131a9c RK |
8438 | |
8439 | static void | |
fb959f72 | 8440 | delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg) |
32131a9c | 8441 | { |
cb2afeb3 R |
8442 | rtx output_reload_insn = spill_reg_store[last_reload_reg]; |
8443 | rtx reg = spill_reg_stored_to[last_reload_reg]; | |
8444 | int k; | |
8445 | int n_occurrences; | |
8446 | int n_inherited = 0; | |
b3694847 | 8447 | rtx i1; |
cb2afeb3 | 8448 | rtx substed; |
05d10675 | 8449 | |
068f5dea JH |
8450 | /* It is possible that this reload has been only used to set another reload |
8451 | we eliminated earlier and thus deleted this instruction too. */ | |
8452 | if (INSN_DELETED_P (output_reload_insn)) | |
8453 | return; | |
8454 | ||
32131a9c RK |
8455 | /* Get the raw pseudo-register referred to. */ |
8456 | ||
32131a9c RK |
8457 | while (GET_CODE (reg) == SUBREG) |
8458 | reg = SUBREG_REG (reg); | |
cb2afeb3 R |
8459 | substed = reg_equiv_memory_loc[REGNO (reg)]; |
8460 | ||
8461 | /* This is unsafe if the operand occurs more often in the current | |
8462 | insn than it is inherited. */ | |
8463 | for (k = n_reloads - 1; k >= 0; k--) | |
8464 | { | |
eceef4c9 | 8465 | rtx reg2 = rld[k].in; |
cb2afeb3 R |
8466 | if (! reg2) |
8467 | continue; | |
3c0cb5de | 8468 | if (MEM_P (reg2) || reload_override_in[k]) |
eceef4c9 | 8469 | reg2 = rld[k].in_reg; |
cb2afeb3 | 8470 | #ifdef AUTO_INC_DEC |
eceef4c9 BS |
8471 | if (rld[k].out && ! rld[k].out_reg) |
8472 | reg2 = XEXP (rld[k].in_reg, 0); | |
cb2afeb3 R |
8473 | #endif |
8474 | while (GET_CODE (reg2) == SUBREG) | |
8475 | reg2 = SUBREG_REG (reg2); | |
8476 | if (rtx_equal_p (reg2, reg)) | |
2eb6dac7 AS |
8477 | { |
8478 | if (reload_inherited[k] || reload_override_in[k] || k == j) | |
f2eb49dc | 8479 | n_inherited++; |
2eb6dac7 AS |
8480 | else |
8481 | return; | |
8482 | } | |
cb2afeb3 | 8483 | } |
4b983fdc | 8484 | n_occurrences = count_occurrences (PATTERN (insn), reg, 0); |
2372a062 BS |
8485 | if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn)) |
8486 | n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn), | |
8487 | reg, 0); | |
cb2afeb3 | 8488 | if (substed) |
5d7ef82a | 8489 | n_occurrences += count_occurrences (PATTERN (insn), |
bbbbb16a | 8490 | eliminate_regs (substed, VOIDmode, |
5d7ef82a | 8491 | NULL_RTX), 0); |
058e97ec | 8492 | for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1)) |
3f1e3e70 AO |
8493 | { |
8494 | gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed)); | |
8495 | n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0); | |
8496 | } | |
cb2afeb3 R |
8497 | if (n_occurrences > n_inherited) |
8498 | return; | |
32131a9c RK |
8499 | |
8500 | /* If the pseudo-reg we are reloading is no longer referenced | |
8501 | anywhere between the store into it and here, | |
0149f412 HPN |
8502 | and we're within the same basic block, then the value can only |
8503 | pass through the reload reg and end up here. | |
32131a9c RK |
8504 | Otherwise, give up--return. */ |
8505 | for (i1 = NEXT_INSN (output_reload_insn); | |
8506 | i1 != insn; i1 = NEXT_INSN (i1)) | |
8507 | { | |
0149f412 | 8508 | if (NOTE_INSN_BASIC_BLOCK_P (i1)) |
32131a9c | 8509 | return; |
4b4bf941 | 8510 | if ((NONJUMP_INSN_P (i1) || CALL_P (i1)) |
32131a9c | 8511 | && reg_mentioned_p (reg, PATTERN (i1))) |
aa6498c2 | 8512 | { |
cb2afeb3 R |
8513 | /* If this is USE in front of INSN, we only have to check that |
8514 | there are no more references than accounted for by inheritance. */ | |
4b4bf941 | 8515 | while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE) |
aa6498c2 | 8516 | { |
cb2afeb3 | 8517 | n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; |
aa6498c2 R |
8518 | i1 = NEXT_INSN (i1); |
8519 | } | |
cb2afeb3 | 8520 | if (n_occurrences <= n_inherited && i1 == insn) |
aa6498c2 R |
8521 | break; |
8522 | return; | |
8523 | } | |
32131a9c RK |
8524 | } |
8525 | ||
cda94cbb | 8526 | /* We will be deleting the insn. Remove the spill reg information. */ |
66fd46b6 | 8527 | for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; ) |
cda94cbb RH |
8528 | { |
8529 | spill_reg_store[last_reload_reg + k] = 0; | |
8530 | spill_reg_stored_to[last_reload_reg + k] = 0; | |
8531 | } | |
8532 | ||
aa6498c2 | 8533 | /* The caller has already checked that REG dies or is set in INSN. |
cda94cbb | 8534 | It has also checked that we are optimizing, and thus some |
14b493d6 | 8535 | inaccuracies in the debugging information are acceptable. |
cda94cbb RH |
8536 | So we could just delete output_reload_insn. But in some cases |
8537 | we can improve the debugging information without sacrificing | |
8538 | optimization - maybe even improving the code: See if the pseudo | |
8539 | reg has been completely replaced with reload regs. If so, delete | |
8540 | the store insn and forget we had a stack slot for the pseudo. */ | |
eceef4c9 | 8541 | if (rld[j].out != rld[j].in |
aa6498c2 | 8542 | && REG_N_DEATHS (REGNO (reg)) == 1 |
a3a24aa6 | 8543 | && REG_N_SETS (REGNO (reg)) == 1 |
6fb5fa3c | 8544 | && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS |
aa6498c2 | 8545 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) |
32131a9c | 8546 | { |
ba4807a0 | 8547 | rtx i2; |
32131a9c | 8548 | |
cda94cbb RH |
8549 | /* We know that it was used only between here and the beginning of |
8550 | the current basic block. (We also know that the last use before | |
8551 | INSN was the output reload we are thinking of deleting, but never | |
8552 | mind that.) Search that range; see if any ref remains. */ | |
ba4807a0 | 8553 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) |
32131a9c | 8554 | { |
ba4807a0 | 8555 | rtx set = single_set (i2); |
d445b551 | 8556 | |
32131a9c RK |
8557 | /* Uses which just store in the pseudo don't count, |
8558 | since if they are the only uses, they are dead. */ | |
d445b551 | 8559 | if (set != 0 && SET_DEST (set) == reg) |
32131a9c | 8560 | continue; |
4b4bf941 JQ |
8561 | if (LABEL_P (i2) |
8562 | || JUMP_P (i2)) | |
32131a9c | 8563 | break; |
4b4bf941 | 8564 | if ((NONJUMP_INSN_P (i2) || CALL_P (i2)) |
32131a9c | 8565 | && reg_mentioned_p (reg, PATTERN (i2))) |
aa6498c2 R |
8566 | { |
8567 | /* Some other ref remains; just delete the output reload we | |
8568 | know to be dead. */ | |
cb2afeb3 | 8569 | delete_address_reloads (output_reload_insn, insn); |
ca6c03ca | 8570 | delete_insn (output_reload_insn); |
aa6498c2 R |
8571 | return; |
8572 | } | |
32131a9c RK |
8573 | } |
8574 | ||
cda94cbb RH |
8575 | /* Delete the now-dead stores into this pseudo. Note that this |
8576 | loop also takes care of deleting output_reload_insn. */ | |
ba4807a0 | 8577 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) |
32131a9c | 8578 | { |
ba4807a0 | 8579 | rtx set = single_set (i2); |
d445b551 RK |
8580 | |
8581 | if (set != 0 && SET_DEST (set) == reg) | |
5507b94b | 8582 | { |
cb2afeb3 | 8583 | delete_address_reloads (i2, insn); |
ca6c03ca | 8584 | delete_insn (i2); |
5507b94b | 8585 | } |
4b4bf941 JQ |
8586 | if (LABEL_P (i2) |
8587 | || JUMP_P (i2)) | |
32131a9c RK |
8588 | break; |
8589 | } | |
8590 | ||
cda94cbb | 8591 | /* For the debugging info, say the pseudo lives in this reload reg. */ |
fb959f72 | 8592 | reg_renumber[REGNO (reg)] = REGNO (new_reload_reg); |
2af2dbdc | 8593 | if (ira_conflicts_p) |
058e97ec VM |
8594 | /* Inform IRA about the change. */ |
8595 | ira_mark_allocation_change (REGNO (reg)); | |
8596 | alter_reg (REGNO (reg), -1, false); | |
32131a9c | 8597 | } |
cda94cbb RH |
8598 | else |
8599 | { | |
8600 | delete_address_reloads (output_reload_insn, insn); | |
8601 | delete_insn (output_reload_insn); | |
8602 | } | |
cb2afeb3 R |
8603 | } |
8604 | ||
8605 | /* We are going to delete DEAD_INSN. Recursively delete loads of | |
8606 | reload registers used in DEAD_INSN that are not used till CURRENT_INSN. | |
8607 | CURRENT_INSN is being reloaded, so we have to check its reloads too. */ | |
8608 | static void | |
0c20a65f | 8609 | delete_address_reloads (rtx dead_insn, rtx current_insn) |
cb2afeb3 R |
8610 | { |
8611 | rtx set = single_set (dead_insn); | |
8612 | rtx set2, dst, prev, next; | |
8613 | if (set) | |
8614 | { | |
8615 | rtx dst = SET_DEST (set); | |
3c0cb5de | 8616 | if (MEM_P (dst)) |
cb2afeb3 R |
8617 | delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); |
8618 | } | |
8619 | /* If we deleted the store from a reloaded post_{in,de}c expression, | |
8620 | we can delete the matching adds. */ | |
8621 | prev = PREV_INSN (dead_insn); | |
8622 | next = NEXT_INSN (dead_insn); | |
8623 | if (! prev || ! next) | |
8624 | return; | |
8625 | set = single_set (next); | |
8626 | set2 = single_set (prev); | |
8627 | if (! set || ! set2 | |
8628 | || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS | |
481683e1 SZ |
8629 | || !CONST_INT_P (XEXP (SET_SRC (set), 1)) |
8630 | || !CONST_INT_P (XEXP (SET_SRC (set2), 1))) | |
cb2afeb3 R |
8631 | return; |
8632 | dst = SET_DEST (set); | |
8633 | if (! rtx_equal_p (dst, SET_DEST (set2)) | |
8634 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) | |
8635 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) | |
8636 | || (INTVAL (XEXP (SET_SRC (set), 1)) | |
1d7254c5 | 8637 | != -INTVAL (XEXP (SET_SRC (set2), 1)))) |
cb2afeb3 | 8638 | return; |
53c17031 JH |
8639 | delete_related_insns (prev); |
8640 | delete_related_insns (next); | |
cb2afeb3 R |
8641 | } |
8642 | ||
8643 | /* Subfunction of delete_address_reloads: process registers found in X. */ | |
8644 | static void | |
0c20a65f | 8645 | delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn) |
cb2afeb3 R |
8646 | { |
8647 | rtx prev, set, dst, i2; | |
8648 | int i, j; | |
8649 | enum rtx_code code = GET_CODE (x); | |
8650 | ||
8651 | if (code != REG) | |
8652 | { | |
1d7254c5 | 8653 | const char *fmt = GET_RTX_FORMAT (code); |
cb2afeb3 R |
8654 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
8655 | { | |
8656 | if (fmt[i] == 'e') | |
8657 | delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); | |
8658 | else if (fmt[i] == 'E') | |
8659 | { | |
1d7254c5 | 8660 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
cb2afeb3 R |
8661 | delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), |
8662 | current_insn); | |
8663 | } | |
8664 | } | |
8665 | return; | |
8666 | } | |
8667 | ||
8668 | if (spill_reg_order[REGNO (x)] < 0) | |
8669 | return; | |
aa6498c2 | 8670 | |
cb2afeb3 R |
8671 | /* Scan backwards for the insn that sets x. This might be a way back due |
8672 | to inheritance. */ | |
8673 | for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) | |
8674 | { | |
8675 | code = GET_CODE (prev); | |
8676 | if (code == CODE_LABEL || code == JUMP_INSN) | |
8677 | return; | |
ec8e098d | 8678 | if (!INSN_P (prev)) |
cb2afeb3 R |
8679 | continue; |
8680 | if (reg_set_p (x, PATTERN (prev))) | |
8681 | break; | |
8682 | if (reg_referenced_p (x, PATTERN (prev))) | |
8683 | return; | |
8684 | } | |
8685 | if (! prev || INSN_UID (prev) < reload_first_uid) | |
8686 | return; | |
8687 | /* Check that PREV only sets the reload register. */ | |
8688 | set = single_set (prev); | |
8689 | if (! set) | |
8690 | return; | |
8691 | dst = SET_DEST (set); | |
f8cfc6aa | 8692 | if (!REG_P (dst) |
cb2afeb3 R |
8693 | || ! rtx_equal_p (dst, x)) |
8694 | return; | |
8695 | if (! reg_set_p (dst, PATTERN (dead_insn))) | |
8696 | { | |
8697 | /* Check if DST was used in a later insn - | |
8698 | it might have been inherited. */ | |
8699 | for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) | |
8700 | { | |
4b4bf941 | 8701 | if (LABEL_P (i2)) |
cb2afeb3 | 8702 | break; |
2c3c49de | 8703 | if (! INSN_P (i2)) |
cb2afeb3 R |
8704 | continue; |
8705 | if (reg_referenced_p (dst, PATTERN (i2))) | |
8706 | { | |
8707 | /* If there is a reference to the register in the current insn, | |
8708 | it might be loaded in a non-inherited reload. If no other | |
8709 | reload uses it, that means the register is set before | |
8710 | referenced. */ | |
8711 | if (i2 == current_insn) | |
8712 | { | |
8713 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 8714 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
8715 | || reload_override_in[j] == dst) |
8716 | return; | |
8717 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 8718 | if (rld[j].in && rld[j].reg_rtx == dst) |
cb2afeb3 R |
8719 | break; |
8720 | if (j >= 0) | |
8721 | break; | |
8722 | } | |
8723 | return; | |
8724 | } | |
4b4bf941 | 8725 | if (JUMP_P (i2)) |
cb2afeb3 | 8726 | break; |
cb2afeb3 | 8727 | /* If DST is still live at CURRENT_INSN, check if it is used for |
3900dc09 R |
8728 | any reload. Note that even if CURRENT_INSN sets DST, we still |
8729 | have to check the reloads. */ | |
cb2afeb3 R |
8730 | if (i2 == current_insn) |
8731 | { | |
8732 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 8733 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
8734 | || reload_override_in[j] == dst) |
8735 | return; | |
8736 | /* ??? We can't finish the loop here, because dst might be | |
8737 | allocated to a pseudo in this block if no reload in this | |
14b493d6 | 8738 | block needs any of the classes containing DST - see |
cb2afeb3 R |
8739 | spill_hard_reg. There is no easy way to tell this, so we |
8740 | have to scan till the end of the basic block. */ | |
8741 | } | |
3900dc09 R |
8742 | if (reg_set_p (dst, PATTERN (i2))) |
8743 | break; | |
cb2afeb3 R |
8744 | } |
8745 | } | |
8746 | delete_address_reloads_1 (prev, SET_SRC (set), current_insn); | |
8747 | reg_reloaded_contents[REGNO (dst)] = -1; | |
ca6c03ca | 8748 | delete_insn (prev); |
32131a9c | 8749 | } |
32131a9c | 8750 | \f |
a8fdc208 | 8751 | /* Output reload-insns to reload VALUE into RELOADREG. |
858a47b1 | 8752 | VALUE is an autoincrement or autodecrement RTX whose operand |
32131a9c RK |
8753 | is a register or memory location; |
8754 | so reloading involves incrementing that location. | |
cb2afeb3 | 8755 | IN is either identical to VALUE, or some cheaper place to reload from. |
32131a9c RK |
8756 | |
8757 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
cb2afeb3 | 8758 | This cannot be deduced from VALUE. |
32131a9c | 8759 | |
cb2afeb3 R |
8760 | Return the instruction that stores into RELOADREG. */ |
8761 | ||
8762 | static rtx | |
0c20a65f | 8763 | inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount) |
32131a9c RK |
8764 | { |
8765 | /* REG or MEM to be copied and incremented. */ | |
4b7b277a | 8766 | rtx incloc = find_replacement (&XEXP (value, 0)); |
32131a9c | 8767 | /* Nonzero if increment after copying. */ |
67f07489 PB |
8768 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC |
8769 | || GET_CODE (value) == POST_MODIFY); | |
546b63fb | 8770 | rtx last; |
0009eff2 RK |
8771 | rtx inc; |
8772 | rtx add_insn; | |
8773 | int code; | |
cb2afeb3 | 8774 | rtx store; |
4b7b277a | 8775 | rtx real_in = in == value ? incloc : in; |
32131a9c RK |
8776 | |
8777 | /* No hard register is equivalent to this register after | |
40f03658 | 8778 | inc/dec operation. If REG_LAST_RELOAD_REG were nonzero, |
32131a9c RK |
8779 | we could inc/dec that register as well (maybe even using it for |
8780 | the source), but I'm not sure it's worth worrying about. */ | |
f8cfc6aa | 8781 | if (REG_P (incloc)) |
32131a9c RK |
8782 | reg_last_reload_reg[REGNO (incloc)] = 0; |
8783 | ||
67f07489 PB |
8784 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) |
8785 | { | |
8786 | gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS); | |
4b7b277a | 8787 | inc = find_replacement (&XEXP (XEXP (value, 1), 1)); |
67f07489 PB |
8788 | } |
8789 | else | |
8790 | { | |
8791 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
8792 | inc_amount = -inc_amount; | |
32131a9c | 8793 | |
67f07489 PB |
8794 | inc = GEN_INT (inc_amount); |
8795 | } | |
0009eff2 RK |
8796 | |
8797 | /* If this is post-increment, first copy the location to the reload reg. */ | |
cb2afeb3 R |
8798 | if (post && real_in != reloadreg) |
8799 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
0009eff2 | 8800 | |
cb2afeb3 R |
8801 | if (in == value) |
8802 | { | |
8803 | /* See if we can directly increment INCLOC. Use a method similar to | |
8804 | that in gen_reload. */ | |
0009eff2 | 8805 | |
cb2afeb3 R |
8806 | last = get_last_insn (); |
8807 | add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, | |
8808 | gen_rtx_PLUS (GET_MODE (incloc), | |
8809 | incloc, inc))); | |
05d10675 | 8810 | |
cb2afeb3 R |
8811 | code = recog_memoized (add_insn); |
8812 | if (code >= 0) | |
32131a9c | 8813 | { |
0eadeb15 BS |
8814 | extract_insn (add_insn); |
8815 | if (constrain_operands (1)) | |
cb2afeb3 R |
8816 | { |
8817 | /* If this is a pre-increment and we have incremented the value | |
8818 | where it lives, copy the incremented value to RELOADREG to | |
8819 | be used as an address. */ | |
0009eff2 | 8820 | |
cb2afeb3 R |
8821 | if (! post) |
8822 | emit_insn (gen_move_insn (reloadreg, incloc)); | |
546b63fb | 8823 | |
cb2afeb3 R |
8824 | return add_insn; |
8825 | } | |
32131a9c | 8826 | } |
cb2afeb3 | 8827 | delete_insns_since (last); |
32131a9c | 8828 | } |
0009eff2 | 8829 | |
0009eff2 RK |
8830 | /* If couldn't do the increment directly, must increment in RELOADREG. |
8831 | The way we do this depends on whether this is pre- or post-increment. | |
8832 | For pre-increment, copy INCLOC to the reload register, increment it | |
8833 | there, then save back. */ | |
8834 | ||
8835 | if (! post) | |
8836 | { | |
cb2afeb3 R |
8837 | if (in != reloadreg) |
8838 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
546b63fb | 8839 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 8840 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
0009eff2 | 8841 | } |
32131a9c RK |
8842 | else |
8843 | { | |
0009eff2 RK |
8844 | /* Postincrement. |
8845 | Because this might be a jump insn or a compare, and because RELOADREG | |
8846 | may not be available after the insn in an input reload, we must do | |
8847 | the incrementation before the insn being reloaded for. | |
8848 | ||
cb2afeb3 | 8849 | We have already copied IN to RELOADREG. Increment the copy in |
0009eff2 RK |
8850 | RELOADREG, save that back, then decrement RELOADREG so it has |
8851 | the original value. */ | |
8852 | ||
546b63fb | 8853 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 8854 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
481683e1 | 8855 | if (CONST_INT_P (inc)) |
247140ea | 8856 | emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc)))); |
67f07489 PB |
8857 | else |
8858 | emit_insn (gen_sub2_insn (reloadreg, inc)); | |
32131a9c | 8859 | } |
0009eff2 | 8860 | |
cb2afeb3 | 8861 | return store; |
32131a9c RK |
8862 | } |
8863 | \f | |
2dfa9a87 MH |
8864 | #ifdef AUTO_INC_DEC |
8865 | static void | |
0c20a65f | 8866 | add_auto_inc_notes (rtx insn, rtx x) |
2dfa9a87 MH |
8867 | { |
8868 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 8869 | const char *fmt; |
2dfa9a87 MH |
8870 | int i, j; |
8871 | ||
8872 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
8873 | { | |
65c5f2a6 | 8874 | add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0)); |
2dfa9a87 MH |
8875 | return; |
8876 | } | |
8877 | ||
8878 | /* Scan all the operand sub-expressions. */ | |
8879 | fmt = GET_RTX_FORMAT (code); | |
8880 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
8881 | { | |
8882 | if (fmt[i] == 'e') | |
8883 | add_auto_inc_notes (insn, XEXP (x, i)); | |
8884 | else if (fmt[i] == 'E') | |
8885 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
8886 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
8887 | } | |
8888 | } | |
8889 | #endif | |
94bd63e5 | 8890 | |
f1330226 JH |
8891 | /* This is used by reload pass, that does emit some instructions after |
8892 | abnormal calls moving basic block end, but in fact it wants to emit | |
8893 | them on the edge. Looks for abnormal call edges, find backward the | |
8894 | proper call and fix the damage. | |
a6a2274a | 8895 | |
f1330226 | 8896 | Similar handle instructions throwing exceptions internally. */ |
068473ec | 8897 | void |
0c20a65f | 8898 | fixup_abnormal_edges (void) |
f1330226 | 8899 | { |
f1330226 | 8900 | bool inserted = false; |
e0082a72 | 8901 | basic_block bb; |
f1330226 | 8902 | |
e0082a72 | 8903 | FOR_EACH_BB (bb) |
f1330226 | 8904 | { |
f1330226 | 8905 | edge e; |
628f6a4e | 8906 | edge_iterator ei; |
f1330226 | 8907 | |
09da1532 | 8908 | /* Look for cases we are interested in - calls or instructions causing |
f1330226 | 8909 | exceptions. */ |
628f6a4e | 8910 | FOR_EACH_EDGE (e, ei, bb->succs) |
f1330226 JH |
8911 | { |
8912 | if (e->flags & EDGE_ABNORMAL_CALL) | |
8913 | break; | |
8914 | if ((e->flags & (EDGE_ABNORMAL | EDGE_EH)) | |
8915 | == (EDGE_ABNORMAL | EDGE_EH)) | |
8916 | break; | |
8917 | } | |
4b4bf941 | 8918 | if (e && !CALL_P (BB_END (bb)) |
a813c111 | 8919 | && !can_throw_internal (BB_END (bb))) |
f1330226 | 8920 | { |
be0c514c RH |
8921 | rtx insn; |
8922 | ||
8923 | /* Get past the new insns generated. Allow notes, as the insns | |
8924 | may be already deleted. */ | |
8925 | insn = BB_END (bb); | |
4b4bf941 | 8926 | while ((NONJUMP_INSN_P (insn) || NOTE_P (insn)) |
39f95a2c | 8927 | && !can_throw_internal (insn) |
a813c111 | 8928 | && insn != BB_HEAD (bb)) |
f1330226 | 8929 | insn = PREV_INSN (insn); |
be0c514c RH |
8930 | |
8931 | if (CALL_P (insn) || can_throw_internal (insn)) | |
f1330226 | 8932 | { |
be0c514c RH |
8933 | rtx stop, next; |
8934 | ||
8935 | stop = NEXT_INSN (BB_END (bb)); | |
8936 | BB_END (bb) = insn; | |
8937 | insn = NEXT_INSN (insn); | |
8938 | ||
8939 | FOR_EACH_EDGE (e, ei, bb->succs) | |
8940 | if (e->flags & EDGE_FALLTHRU) | |
8941 | break; | |
8942 | ||
8943 | while (insn && insn != stop) | |
0c4992b0 | 8944 | { |
be0c514c RH |
8945 | next = NEXT_INSN (insn); |
8946 | if (INSN_P (insn)) | |
ed8d2920 | 8947 | { |
36808d08 | 8948 | delete_insn (insn); |
be0c514c RH |
8949 | |
8950 | /* Sometimes there's still the return value USE. | |
8951 | If it's placed after a trapping call (i.e. that | |
8952 | call is the last insn anyway), we have no fallthru | |
8953 | edge. Simply delete this use and don't try to insert | |
8954 | on the non-existent edge. */ | |
8955 | if (GET_CODE (PATTERN (insn)) != USE) | |
8956 | { | |
8957 | /* We're not deleting it, we're moving it. */ | |
8958 | INSN_DELETED_P (insn) = 0; | |
8959 | PREV_INSN (insn) = NULL_RTX; | |
8960 | NEXT_INSN (insn) = NULL_RTX; | |
f8ed1958 | 8961 | |
be0c514c RH |
8962 | insert_insn_on_edge (insn, e); |
8963 | inserted = true; | |
8964 | } | |
ed8d2920 | 8965 | } |
36808d08 EB |
8966 | else if (!BARRIER_P (insn)) |
8967 | set_block_for_insn (insn, NULL); | |
be0c514c | 8968 | insn = next; |
0c4992b0 | 8969 | } |
f1330226 | 8970 | } |
be0c514c RH |
8971 | |
8972 | /* It may be that we don't find any such trapping insn. In this | |
8973 | case we discovered quite late that the insn that had been | |
8974 | marked as can_throw_internal in fact couldn't trap at all. | |
8975 | So we should in fact delete the EH edges out of the block. */ | |
8976 | else | |
8977 | purge_dead_edges (bb); | |
f1330226 JH |
8978 | } |
8979 | } | |
be0c514c | 8980 | |
b735f45d AK |
8981 | /* We've possibly turned single trapping insn into multiple ones. */ |
8982 | if (flag_non_call_exceptions) | |
8983 | { | |
8984 | sbitmap blocks; | |
8985 | blocks = sbitmap_alloc (last_basic_block); | |
8986 | sbitmap_ones (blocks); | |
8987 | find_many_sub_basic_blocks (blocks); | |
639d3040 | 8988 | sbitmap_free (blocks); |
b735f45d AK |
8989 | } |
8990 | ||
f1330226 JH |
8991 | if (inserted) |
8992 | commit_edge_insertions (); | |
be0c514c RH |
8993 | |
8994 | #ifdef ENABLE_CHECKING | |
8995 | /* Verify that we didn't turn one trapping insn into many, and that | |
8996 | we found and corrected all of the problems wrt fixups on the | |
8997 | fallthru edge. */ | |
8998 | verify_flow_info (); | |
8999 | #endif | |
f1330226 | 9000 | } |