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32131a9c | 1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
af841dbd | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
dd3adcf8 | 3 | 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
32131a9c | 4 | |
1322177d | 5 | This file is part of GCC. |
32131a9c | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
32131a9c | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
32131a9c RK |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
32131a9c | 21 | |
32131a9c | 22 | #include "config.h" |
670ee920 | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
cab634f2 KG |
26 | |
27 | #include "machmode.h" | |
28 | #include "hard-reg-set.h" | |
32131a9c | 29 | #include "rtl.h" |
6baf1cc8 | 30 | #include "tm_p.h" |
32131a9c RK |
31 | #include "obstack.h" |
32 | #include "insn-config.h" | |
32131a9c | 33 | #include "flags.h" |
49ad7cfa | 34 | #include "function.h" |
32131a9c | 35 | #include "expr.h" |
e78d8e51 | 36 | #include "optabs.h" |
32131a9c | 37 | #include "regs.h" |
cad6f7d0 | 38 | #include "basic-block.h" |
32131a9c RK |
39 | #include "reload.h" |
40 | #include "recog.h" | |
32131a9c | 41 | #include "output.h" |
a9c366bf | 42 | #include "real.h" |
10f0ad3d | 43 | #include "toplev.h" |
39f95a2c | 44 | #include "except.h" |
a20fd5ac | 45 | #include "tree.h" |
32131a9c RK |
46 | |
47 | /* This file contains the reload pass of the compiler, which is | |
48 | run after register allocation has been done. It checks that | |
49 | each insn is valid (operands required to be in registers really | |
50 | are in registers of the proper class) and fixes up invalid ones | |
51 | by copying values temporarily into registers for the insns | |
52 | that need them. | |
53 | ||
54 | The results of register allocation are described by the vector | |
55 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
56 | can be used to find which hard reg, if any, a pseudo reg is in. | |
57 | ||
58 | The technique we always use is to free up a few hard regs that are | |
59 | called ``reload regs'', and for each place where a pseudo reg | |
60 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
61 | ||
03acd8f8 BS |
62 | Reload regs are allocated locally for every instruction that needs |
63 | reloads. When there are pseudos which are allocated to a register that | |
64 | has been chosen as a reload reg, such pseudos must be ``spilled''. | |
65 | This means that they go to other hard regs, or to stack slots if no other | |
32131a9c RK |
66 | available hard regs can be found. Spilling can invalidate more |
67 | insns, requiring additional need for reloads, so we must keep checking | |
68 | until the process stabilizes. | |
69 | ||
70 | For machines with different classes of registers, we must keep track | |
71 | of the register class needed for each reload, and make sure that | |
72 | we allocate enough reload registers of each class. | |
73 | ||
74 | The file reload.c contains the code that checks one insn for | |
75 | validity and reports the reloads that it needs. This file | |
76 | is in charge of scanning the entire rtl code, accumulating the | |
77 | reload needs, spilling, assigning reload registers to use for | |
78 | fixing up each insn, and generating the new insns to copy values | |
79 | into the reload registers. */ | |
80 | \f | |
81 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
0f41302f | 82 | into which reg N has been reloaded (perhaps for a previous insn). */ |
32131a9c RK |
83 | static rtx *reg_last_reload_reg; |
84 | ||
85 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
86 | for an output reload that stores into reg N. */ | |
87 | static char *reg_has_output_reload; | |
88 | ||
89 | /* Indicates which hard regs are reload-registers for an output reload | |
90 | in the current insn. */ | |
91 | static HARD_REG_SET reg_is_output_reload; | |
92 | ||
93 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
94 | or zero if pseudo reg N is not equivalent to a constant. | |
95 | find_reloads looks at this in order to replace pseudo reg N | |
96 | with the constant it stands for. */ | |
97 | rtx *reg_equiv_constant; | |
98 | ||
99 | /* Element N is a memory location to which pseudo reg N is equivalent, | |
100 | prior to any register elimination (such as frame pointer to stack | |
101 | pointer). Depending on whether or not it is a valid address, this value | |
102 | is transferred to either reg_equiv_address or reg_equiv_mem. */ | |
4803a34a | 103 | rtx *reg_equiv_memory_loc; |
32131a9c RK |
104 | |
105 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. | |
106 | This is used when the address is not valid as a memory address | |
107 | (because its displacement is too big for the machine.) */ | |
108 | rtx *reg_equiv_address; | |
109 | ||
110 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
111 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
112 | rtx *reg_equiv_mem; | |
113 | ||
114 | /* Widest width in which each pseudo reg is referred to (via subreg). */ | |
770ae6cc | 115 | static unsigned int *reg_max_ref_width; |
32131a9c | 116 | |
135eb61c | 117 | /* Element N is the list of insns that initialized reg N from its equivalent |
32131a9c RK |
118 | constant or memory slot. */ |
119 | static rtx *reg_equiv_init; | |
120 | ||
03acd8f8 BS |
121 | /* Vector to remember old contents of reg_renumber before spilling. */ |
122 | static short *reg_old_renumber; | |
123 | ||
e6e52be0 | 124 | /* During reload_as_needed, element N contains the last pseudo regno reloaded |
03acd8f8 | 125 | into hard register N. If that pseudo reg occupied more than one register, |
32131a9c RK |
126 | reg_reloaded_contents points to that pseudo for each spill register in |
127 | use; all of these must remain set for an inheritance to occur. */ | |
128 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
129 | ||
130 | /* During reload_as_needed, element N contains the insn for which | |
e6e52be0 R |
131 | hard register N was last used. Its contents are significant only |
132 | when reg_reloaded_valid is set for this register. */ | |
32131a9c RK |
133 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; |
134 | ||
3eae4643 | 135 | /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */ |
e6e52be0 R |
136 | static HARD_REG_SET reg_reloaded_valid; |
137 | /* Indicate if the register was dead at the end of the reload. | |
138 | This is only valid if reg_reloaded_contents is set and valid. */ | |
139 | static HARD_REG_SET reg_reloaded_dead; | |
140 | ||
e3e9336f DJ |
141 | /* Indicate whether the register's current value is one that is not |
142 | safe to retain across a call, even for registers that are normally | |
143 | call-saved. */ | |
144 | static HARD_REG_SET reg_reloaded_call_part_clobbered; | |
145 | ||
32131a9c RK |
146 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ |
147 | static int n_spills; | |
148 | ||
149 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
150 | Holds the last rtx used for any given reg, or 0 if it has never | |
151 | been used for spilling yet. This rtx is reused, provided it has | |
152 | the proper mode. */ | |
153 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
154 | ||
155 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
156 | that was stored after the last time it was used. | |
157 | The precise value is the insn generated to do the store. */ | |
158 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
159 | ||
cb2afeb3 R |
160 | /* This is the register that was stored with spill_reg_store. This is a |
161 | copy of reload_out / reload_out_reg when the value was stored; if | |
162 | reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ | |
163 | static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; | |
164 | ||
32131a9c RK |
165 | /* This table is the inverse mapping of spill_regs: |
166 | indexed by hard reg number, | |
167 | it contains the position of that reg in spill_regs, | |
05d10675 | 168 | or -1 for something that is not in spill_regs. |
13c8e8e3 JL |
169 | |
170 | ?!? This is no longer accurate. */ | |
32131a9c RK |
171 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; |
172 | ||
03acd8f8 BS |
173 | /* This reg set indicates registers that can't be used as spill registers for |
174 | the currently processed insn. These are the hard registers which are live | |
175 | during the insn, but not allocated to pseudos, as well as fixed | |
176 | registers. */ | |
32131a9c RK |
177 | static HARD_REG_SET bad_spill_regs; |
178 | ||
03acd8f8 BS |
179 | /* These are the hard registers that can't be used as spill register for any |
180 | insn. This includes registers used for user variables and registers that | |
181 | we can't eliminate. A register that appears in this set also can't be used | |
182 | to retry register allocation. */ | |
183 | static HARD_REG_SET bad_spill_regs_global; | |
184 | ||
32131a9c | 185 | /* Describes order of use of registers for reloading |
03acd8f8 BS |
186 | of spilled pseudo-registers. `n_spills' is the number of |
187 | elements that are actually valid; new ones are added at the end. | |
188 | ||
189 | Both spill_regs and spill_reg_order are used on two occasions: | |
190 | once during find_reload_regs, where they keep track of the spill registers | |
191 | for a single insn, but also during reload_as_needed where they show all | |
192 | the registers ever used by reload. For the latter case, the information | |
193 | is calculated during finish_spills. */ | |
32131a9c RK |
194 | static short spill_regs[FIRST_PSEUDO_REGISTER]; |
195 | ||
03acd8f8 BS |
196 | /* This vector of reg sets indicates, for each pseudo, which hard registers |
197 | may not be used for retrying global allocation because the register was | |
198 | formerly spilled from one of them. If we allowed reallocating a pseudo to | |
199 | a register that it was already allocated to, reload might not | |
200 | terminate. */ | |
201 | static HARD_REG_SET *pseudo_previous_regs; | |
202 | ||
203 | /* This vector of reg sets indicates, for each pseudo, which hard | |
204 | registers may not be used for retrying global allocation because they | |
205 | are used as spill registers during one of the insns in which the | |
206 | pseudo is live. */ | |
207 | static HARD_REG_SET *pseudo_forbidden_regs; | |
208 | ||
209 | /* All hard regs that have been used as spill registers for any insn are | |
210 | marked in this set. */ | |
211 | static HARD_REG_SET used_spill_regs; | |
8b4f9969 | 212 | |
4079cd63 JW |
213 | /* Index of last register assigned as a spill register. We allocate in |
214 | a round-robin fashion. */ | |
4079cd63 JW |
215 | static int last_spill_reg; |
216 | ||
32131a9c RK |
217 | /* Nonzero if indirect addressing is supported on the machine; this means |
218 | that spilling (REG n) does not require reloading it into a register in | |
219 | order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The | |
220 | value indicates the level of indirect addressing supported, e.g., two | |
221 | means that (MEM (MEM (REG n))) is also valid if (REG n) does not get | |
222 | a hard register. */ | |
32131a9c RK |
223 | static char spill_indirect_levels; |
224 | ||
225 | /* Nonzero if indirect addressing is supported when the innermost MEM is | |
226 | of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to | |
6d2f8887 | 227 | which these are valid is the same as spill_indirect_levels, above. */ |
32131a9c RK |
228 | char indirect_symref_ok; |
229 | ||
230 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
32131a9c RK |
231 | char double_reg_address_ok; |
232 | ||
233 | /* Record the stack slot for each spilled hard register. */ | |
32131a9c RK |
234 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; |
235 | ||
236 | /* Width allocated so far for that stack slot. */ | |
770ae6cc | 237 | static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; |
32131a9c | 238 | |
7609e720 | 239 | /* Record which pseudos needed to be spilled. */ |
f5d8c9f4 BS |
240 | static regset_head spilled_pseudos; |
241 | ||
242 | /* Used for communication between order_regs_for_reload and count_pseudo. | |
243 | Used to avoid counting one pseudo twice. */ | |
244 | static regset_head pseudos_counted; | |
7609e720 | 245 | |
32131a9c RK |
246 | /* First uid used by insns created by reload in this function. |
247 | Used in find_equiv_reg. */ | |
248 | int reload_first_uid; | |
249 | ||
250 | /* Flag set by local-alloc or global-alloc if anything is live in | |
251 | a call-clobbered reg across calls. */ | |
32131a9c RK |
252 | int caller_save_needed; |
253 | ||
254 | /* Set to 1 while reload_as_needed is operating. | |
255 | Required by some machines to handle any generated moves differently. */ | |
32131a9c RK |
256 | int reload_in_progress = 0; |
257 | ||
258 | /* These arrays record the insn_code of insns that may be needed to | |
259 | perform input and output reloads of special objects. They provide a | |
260 | place to pass a scratch register. */ | |
32131a9c RK |
261 | enum insn_code reload_in_optab[NUM_MACHINE_MODES]; |
262 | enum insn_code reload_out_optab[NUM_MACHINE_MODES]; | |
263 | ||
d45cf215 | 264 | /* This obstack is used for allocation of rtl during register elimination. |
32131a9c RK |
265 | The allocated storage can be freed once find_reloads has processed the |
266 | insn. */ | |
32131a9c | 267 | struct obstack reload_obstack; |
cad6f7d0 BS |
268 | |
269 | /* Points to the beginning of the reload_obstack. All insn_chain structures | |
270 | are allocated first. */ | |
271 | char *reload_startobj; | |
272 | ||
273 | /* The point after all insn_chain structures. Used to quickly deallocate | |
f5d8c9f4 | 274 | memory allocated in copy_reloads during calculate_needs_all_insns. */ |
32131a9c RK |
275 | char *reload_firstobj; |
276 | ||
f5d8c9f4 BS |
277 | /* This points before all local rtl generated by register elimination. |
278 | Used to quickly free all memory after processing one insn. */ | |
279 | static char *reload_insn_firstobj; | |
280 | ||
cad6f7d0 BS |
281 | /* List of insn_chain instructions, one for every insn that reload needs to |
282 | examine. */ | |
283 | struct insn_chain *reload_insn_chain; | |
7609e720 | 284 | |
03acd8f8 | 285 | /* List of all insns needing reloads. */ |
7609e720 | 286 | static struct insn_chain *insns_need_reload; |
32131a9c RK |
287 | \f |
288 | /* This structure is used to record information about register eliminations. | |
289 | Each array entry describes one possible way of eliminating a register | |
290 | in favor of another. If there is more than one way of eliminating a | |
291 | particular register, the most preferred should be specified first. */ | |
292 | ||
590cf94d | 293 | struct elim_table |
32131a9c | 294 | { |
0f41302f MS |
295 | int from; /* Register number to be eliminated. */ |
296 | int to; /* Register number used as replacement. */ | |
b19ee4bd | 297 | HOST_WIDE_INT initial_offset; /* Initial difference between values. */ |
272d0bee | 298 | int can_eliminate; /* Nonzero if this elimination can be done. */ |
32131a9c | 299 | int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over |
0f41302f | 300 | insns made by reload. */ |
b19ee4bd JJ |
301 | HOST_WIDE_INT offset; /* Current offset between the two regs. */ |
302 | HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */ | |
0f41302f | 303 | int ref_outside_mem; /* "to" has been referenced outside a MEM. */ |
32131a9c RK |
304 | rtx from_rtx; /* REG rtx for the register to be eliminated. |
305 | We cannot simply compare the number since | |
306 | we might then spuriously replace a hard | |
307 | register corresponding to a pseudo | |
0f41302f MS |
308 | assigned to the reg to be eliminated. */ |
309 | rtx to_rtx; /* REG rtx for the replacement. */ | |
590cf94d KG |
310 | }; |
311 | ||
1d7254c5 | 312 | static struct elim_table *reg_eliminate = 0; |
590cf94d KG |
313 | |
314 | /* This is an intermediate structure to initialize the table. It has | |
1d7254c5 | 315 | exactly the members provided by ELIMINABLE_REGS. */ |
0b5826ac | 316 | static const struct elim_table_1 |
590cf94d | 317 | { |
0b5826ac KG |
318 | const int from; |
319 | const int to; | |
590cf94d | 320 | } reg_eliminate_1[] = |
32131a9c RK |
321 | |
322 | /* If a set of eliminable registers was specified, define the table from it. | |
323 | Otherwise, default to the normal case of the frame pointer being | |
324 | replaced by the stack pointer. */ | |
325 | ||
326 | #ifdef ELIMINABLE_REGS | |
327 | ELIMINABLE_REGS; | |
328 | #else | |
329 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
330 | #endif | |
331 | ||
b6a1cbae | 332 | #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) |
32131a9c RK |
333 | |
334 | /* Record the number of pending eliminations that have an offset not equal | |
40f03658 | 335 | to their initial offset. If nonzero, we use a new copy of each |
32131a9c | 336 | replacement result in any insns encountered. */ |
cb2afeb3 | 337 | int num_not_at_initial_offset; |
32131a9c RK |
338 | |
339 | /* Count the number of registers that we may be able to eliminate. */ | |
340 | static int num_eliminable; | |
2b49ee39 R |
341 | /* And the number of registers that are equivalent to a constant that |
342 | can be eliminated to frame_pointer / arg_pointer + constant. */ | |
343 | static int num_eliminable_invariants; | |
32131a9c RK |
344 | |
345 | /* For each label, we record the offset of each elimination. If we reach | |
346 | a label by more than one path and an offset differs, we cannot do the | |
4cc0fdd2 JDA |
347 | elimination. This information is indexed by the difference of the |
348 | number of the label and the first label number. We can't offset the | |
349 | pointer itself as this can cause problems on machines with segmented | |
350 | memory. The first table is an array of flags that records whether we | |
351 | have yet encountered a label and the second table is an array of arrays, | |
352 | one entry in the latter array for each elimination. */ | |
353 | ||
354 | static int first_label_num; | |
32131a9c | 355 | static char *offsets_known_at; |
b19ee4bd | 356 | static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS]; |
32131a9c RK |
357 | |
358 | /* Number of labels in the current function. */ | |
359 | ||
360 | static int num_labels; | |
361 | \f | |
0c20a65f AJ |
362 | static void replace_pseudos_in (rtx *, enum machine_mode, rtx); |
363 | static void maybe_fix_stack_asms (void); | |
364 | static void copy_reloads (struct insn_chain *); | |
365 | static void calculate_needs_all_insns (int); | |
366 | static int find_reg (struct insn_chain *, int); | |
367 | static void find_reload_regs (struct insn_chain *); | |
368 | static void select_reload_regs (void); | |
369 | static void delete_caller_save_insns (void); | |
370 | ||
371 | static void spill_failure (rtx, enum reg_class); | |
372 | static void count_spilled_pseudo (int, int, int); | |
373 | static void delete_dead_insn (rtx); | |
374 | static void alter_reg (int, int); | |
375 | static void set_label_offsets (rtx, rtx, int); | |
376 | static void check_eliminable_occurrences (rtx); | |
377 | static void elimination_effects (rtx, enum machine_mode); | |
378 | static int eliminate_regs_in_insn (rtx, int); | |
379 | static void update_eliminable_offsets (void); | |
380 | static void mark_not_eliminable (rtx, rtx, void *); | |
381 | static void set_initial_elim_offsets (void); | |
382 | static void verify_initial_elim_offsets (void); | |
383 | static void set_initial_label_offsets (void); | |
384 | static void set_offsets_for_label (rtx); | |
385 | static void init_elim_table (void); | |
386 | static void update_eliminables (HARD_REG_SET *); | |
387 | static void spill_hard_reg (unsigned int, int); | |
388 | static int finish_spills (int); | |
389 | static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *); | |
390 | static void scan_paradoxical_subregs (rtx); | |
391 | static void count_pseudo (int); | |
392 | static void order_regs_for_reload (struct insn_chain *); | |
393 | static void reload_as_needed (int); | |
394 | static void forget_old_reloads_1 (rtx, rtx, void *); | |
395 | static int reload_reg_class_lower (const void *, const void *); | |
396 | static void mark_reload_reg_in_use (unsigned int, int, enum reload_type, | |
397 | enum machine_mode); | |
398 | static void clear_reload_reg_in_use (unsigned int, int, enum reload_type, | |
399 | enum machine_mode); | |
400 | static int reload_reg_free_p (unsigned int, int, enum reload_type); | |
401 | static int reload_reg_free_for_value_p (int, int, int, enum reload_type, | |
402 | rtx, rtx, int, int); | |
403 | static int free_for_value_p (int, enum machine_mode, int, enum reload_type, | |
404 | rtx, rtx, int, int); | |
405 | static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type); | |
406 | static int allocate_reload_reg (struct insn_chain *, int, int); | |
407 | static int conflicts_with_override (rtx); | |
408 | static void failed_reload (rtx, int); | |
409 | static int set_reload_reg (int, int); | |
410 | static void choose_reload_regs_init (struct insn_chain *, rtx *); | |
411 | static void choose_reload_regs (struct insn_chain *); | |
412 | static void merge_assigned_reloads (rtx); | |
413 | static void emit_input_reload_insns (struct insn_chain *, struct reload *, | |
414 | rtx, int); | |
415 | static void emit_output_reload_insns (struct insn_chain *, struct reload *, | |
416 | int); | |
417 | static void do_input_reload (struct insn_chain *, struct reload *, int); | |
418 | static void do_output_reload (struct insn_chain *, struct reload *, int); | |
419 | static void emit_reload_insns (struct insn_chain *); | |
420 | static void delete_output_reload (rtx, int, int); | |
421 | static void delete_address_reloads (rtx, rtx); | |
422 | static void delete_address_reloads_1 (rtx, rtx, rtx); | |
423 | static rtx inc_for_reload (rtx, rtx, rtx, int); | |
2dfa9a87 | 424 | #ifdef AUTO_INC_DEC |
0c20a65f | 425 | static void add_auto_inc_notes (rtx, rtx); |
2dfa9a87 | 426 | #endif |
0c20a65f | 427 | static void copy_eh_notes (rtx, rtx); |
32131a9c | 428 | \f |
546b63fb RK |
429 | /* Initialize the reload pass once per compilation. */ |
430 | ||
32131a9c | 431 | void |
0c20a65f | 432 | init_reload (void) |
32131a9c | 433 | { |
b3694847 | 434 | int i; |
32131a9c RK |
435 | |
436 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
437 | Set spill_indirect_levels to the number of levels such addressing is | |
438 | permitted, zero if it is not permitted at all. */ | |
439 | ||
b3694847 | 440 | rtx tem |
38a448ca RH |
441 | = gen_rtx_MEM (Pmode, |
442 | gen_rtx_PLUS (Pmode, | |
c5c76735 JL |
443 | gen_rtx_REG (Pmode, |
444 | LAST_VIRTUAL_REGISTER + 1), | |
38a448ca | 445 | GEN_INT (4))); |
32131a9c RK |
446 | spill_indirect_levels = 0; |
447 | ||
448 | while (memory_address_p (QImode, tem)) | |
449 | { | |
450 | spill_indirect_levels++; | |
38a448ca | 451 | tem = gen_rtx_MEM (Pmode, tem); |
32131a9c RK |
452 | } |
453 | ||
454 | /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ | |
455 | ||
38a448ca | 456 | tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); |
32131a9c RK |
457 | indirect_symref_ok = memory_address_p (QImode, tem); |
458 | ||
459 | /* See if reg+reg is a valid (and offsettable) address. */ | |
460 | ||
65701fd2 | 461 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
57caa638 | 462 | { |
38a448ca RH |
463 | tem = gen_rtx_PLUS (Pmode, |
464 | gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), | |
465 | gen_rtx_REG (Pmode, i)); | |
c5c76735 | 466 | |
57caa638 RS |
467 | /* This way, we make sure that reg+reg is an offsettable address. */ |
468 | tem = plus_constant (tem, 4); | |
469 | ||
470 | if (memory_address_p (QImode, tem)) | |
471 | { | |
472 | double_reg_address_ok = 1; | |
473 | break; | |
474 | } | |
475 | } | |
32131a9c | 476 | |
0f41302f | 477 | /* Initialize obstack for our rtl allocation. */ |
32131a9c | 478 | gcc_obstack_init (&reload_obstack); |
703ad42b | 479 | reload_startobj = obstack_alloc (&reload_obstack, 0); |
f5d8c9f4 BS |
480 | |
481 | INIT_REG_SET (&spilled_pseudos); | |
482 | INIT_REG_SET (&pseudos_counted); | |
32131a9c RK |
483 | } |
484 | ||
cad6f7d0 BS |
485 | /* List of insn chains that are currently unused. */ |
486 | static struct insn_chain *unused_insn_chains = 0; | |
487 | ||
488 | /* Allocate an empty insn_chain structure. */ | |
489 | struct insn_chain * | |
0c20a65f | 490 | new_insn_chain (void) |
cad6f7d0 BS |
491 | { |
492 | struct insn_chain *c; | |
493 | ||
494 | if (unused_insn_chains == 0) | |
495 | { | |
703ad42b | 496 | c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain)); |
239a0f5b BS |
497 | INIT_REG_SET (&c->live_throughout); |
498 | INIT_REG_SET (&c->dead_or_set); | |
cad6f7d0 BS |
499 | } |
500 | else | |
501 | { | |
502 | c = unused_insn_chains; | |
503 | unused_insn_chains = c->next; | |
504 | } | |
505 | c->is_caller_save_insn = 0; | |
03acd8f8 | 506 | c->need_operand_change = 0; |
cad6f7d0 BS |
507 | c->need_reload = 0; |
508 | c->need_elim = 0; | |
509 | return c; | |
510 | } | |
511 | ||
7609e720 BS |
512 | /* Small utility function to set all regs in hard reg set TO which are |
513 | allocated to pseudos in regset FROM. */ | |
770ae6cc | 514 | |
7609e720 | 515 | void |
0c20a65f | 516 | compute_use_by_pseudos (HARD_REG_SET *to, regset from) |
7609e720 | 517 | { |
770ae6cc RK |
518 | unsigned int regno; |
519 | ||
7609e720 BS |
520 | EXECUTE_IF_SET_IN_REG_SET |
521 | (from, FIRST_PSEUDO_REGISTER, regno, | |
522 | { | |
523 | int r = reg_renumber[regno]; | |
524 | int nregs; | |
770ae6cc | 525 | |
7609e720 | 526 | if (r < 0) |
404d95c4 R |
527 | { |
528 | /* reload_combine uses the information from | |
e881bb1b RH |
529 | BASIC_BLOCK->global_live_at_start, which might still |
530 | contain registers that have not actually been allocated | |
531 | since they have an equivalence. */ | |
404d95c4 R |
532 | if (! reload_completed) |
533 | abort (); | |
534 | } | |
535 | else | |
536 | { | |
66fd46b6 | 537 | nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; |
404d95c4 R |
538 | while (nregs-- > 0) |
539 | SET_HARD_REG_BIT (*to, r + nregs); | |
540 | } | |
7609e720 BS |
541 | }); |
542 | } | |
f474c6f8 AO |
543 | |
544 | /* Replace all pseudos found in LOC with their corresponding | |
545 | equivalences. */ | |
546 | ||
547 | static void | |
0c20a65f | 548 | replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage) |
f474c6f8 AO |
549 | { |
550 | rtx x = *loc; | |
551 | enum rtx_code code; | |
552 | const char *fmt; | |
553 | int i, j; | |
554 | ||
555 | if (! x) | |
556 | return; | |
174fa2c4 | 557 | |
f474c6f8 AO |
558 | code = GET_CODE (x); |
559 | if (code == REG) | |
560 | { | |
ae0ed63a | 561 | unsigned int regno = REGNO (x); |
086fef9e AO |
562 | |
563 | if (regno < FIRST_PSEUDO_REGISTER) | |
f474c6f8 AO |
564 | return; |
565 | ||
566 | x = eliminate_regs (x, mem_mode, usage); | |
567 | if (x != *loc) | |
568 | { | |
569 | *loc = x; | |
ee960939 | 570 | replace_pseudos_in (loc, mem_mode, usage); |
f474c6f8 AO |
571 | return; |
572 | } | |
573 | ||
086fef9e AO |
574 | if (reg_equiv_constant[regno]) |
575 | *loc = reg_equiv_constant[regno]; | |
576 | else if (reg_equiv_mem[regno]) | |
577 | *loc = reg_equiv_mem[regno]; | |
578 | else if (reg_equiv_address[regno]) | |
579 | *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]); | |
580 | else if (GET_CODE (regno_reg_rtx[regno]) != REG | |
581 | || REGNO (regno_reg_rtx[regno]) != regno) | |
582 | *loc = regno_reg_rtx[regno]; | |
f474c6f8 AO |
583 | else |
584 | abort (); | |
585 | ||
586 | return; | |
587 | } | |
588 | else if (code == MEM) | |
589 | { | |
ee960939 | 590 | replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage); |
f474c6f8 AO |
591 | return; |
592 | } | |
174fa2c4 | 593 | |
f474c6f8 AO |
594 | /* Process each of our operands recursively. */ |
595 | fmt = GET_RTX_FORMAT (code); | |
596 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
597 | if (*fmt == 'e') | |
ee960939 | 598 | replace_pseudos_in (&XEXP (x, i), mem_mode, usage); |
f474c6f8 AO |
599 | else if (*fmt == 'E') |
600 | for (j = 0; j < XVECLEN (x, i); j++) | |
ee960939 | 601 | replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage); |
f474c6f8 AO |
602 | } |
603 | ||
03acd8f8 | 604 | \f |
1e5bd841 BS |
605 | /* Global variables used by reload and its subroutines. */ |
606 | ||
1e5bd841 BS |
607 | /* Set during calculate_needs if an insn needs register elimination. */ |
608 | static int something_needs_elimination; | |
cb2afeb3 R |
609 | /* Set during calculate_needs if an insn needs an operand changed. */ |
610 | int something_needs_operands_changed; | |
1e5bd841 | 611 | |
1e5bd841 BS |
612 | /* Nonzero means we couldn't get enough spill regs. */ |
613 | static int failure; | |
614 | ||
546b63fb | 615 | /* Main entry point for the reload pass. |
32131a9c RK |
616 | |
617 | FIRST is the first insn of the function being compiled. | |
618 | ||
619 | GLOBAL nonzero means we were called from global_alloc | |
620 | and should attempt to reallocate any pseudoregs that we | |
621 | displace from hard regs we will use for reloads. | |
622 | If GLOBAL is zero, we do not have enough information to do that, | |
623 | so any pseudo reg that is spilled must go to the stack. | |
624 | ||
5352b11a RS |
625 | Return value is nonzero if reload failed |
626 | and we must not do any more for this function. */ | |
627 | ||
628 | int | |
0c20a65f | 629 | reload (rtx first, int global) |
32131a9c | 630 | { |
b3694847 SS |
631 | int i; |
632 | rtx insn; | |
633 | struct elim_table *ep; | |
e0082a72 | 634 | basic_block bb; |
32131a9c | 635 | |
32131a9c RK |
636 | /* Make sure even insns with volatile mem refs are recognizable. */ |
637 | init_recog (); | |
638 | ||
1e5bd841 BS |
639 | failure = 0; |
640 | ||
703ad42b | 641 | reload_firstobj = obstack_alloc (&reload_obstack, 0); |
cad6f7d0 | 642 | |
437a710d BS |
643 | /* Make sure that the last insn in the chain |
644 | is not something that needs reloading. */ | |
2e040219 | 645 | emit_note (NOTE_INSN_DELETED); |
437a710d | 646 | |
32131a9c RK |
647 | /* Enable find_equiv_reg to distinguish insns made by reload. */ |
648 | reload_first_uid = get_max_uid (); | |
649 | ||
0dadecf6 RK |
650 | #ifdef SECONDARY_MEMORY_NEEDED |
651 | /* Initialize the secondary memory table. */ | |
652 | clear_secondary_mem (); | |
653 | #endif | |
654 | ||
32131a9c | 655 | /* We don't have a stack slot for any spill reg yet. */ |
703ad42b KG |
656 | memset (spill_stack_slot, 0, sizeof spill_stack_slot); |
657 | memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width); | |
32131a9c | 658 | |
a8efe40d RK |
659 | /* Initialize the save area information for caller-save, in case some |
660 | are needed. */ | |
661 | init_save_areas (); | |
a8fdc208 | 662 | |
32131a9c RK |
663 | /* Compute which hard registers are now in use |
664 | as homes for pseudo registers. | |
665 | This is done here rather than (eg) in global_alloc | |
666 | because this point is reached even if not optimizing. */ | |
32131a9c RK |
667 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
668 | mark_home_live (i); | |
669 | ||
8dddd002 RK |
670 | /* A function that receives a nonlocal goto must save all call-saved |
671 | registers. */ | |
672 | if (current_function_has_nonlocal_label) | |
673 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2a3e384f RH |
674 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) |
675 | regs_ever_live[i] = 1; | |
8dddd002 | 676 | |
5583e33d JW |
677 | #ifdef NON_SAVING_SETJMP |
678 | /* A function that calls setjmp should save and restore all the | |
679 | call-saved registers on a system where longjmp clobbers them. */ | |
680 | if (NON_SAVING_SETJMP && current_function_calls_setjmp) | |
681 | { | |
682 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
683 | if (! call_used_regs[i]) | |
684 | regs_ever_live[i] = 1; | |
685 | } | |
686 | #endif | |
687 | ||
32131a9c RK |
688 | /* Find all the pseudo registers that didn't get hard regs |
689 | but do have known equivalent constants or memory slots. | |
690 | These include parameters (known equivalent to parameter slots) | |
691 | and cse'd or loop-moved constant memory addresses. | |
692 | ||
693 | Record constant equivalents in reg_equiv_constant | |
694 | so they will be substituted by find_reloads. | |
695 | Record memory equivalents in reg_mem_equiv so they can | |
696 | be substituted eventually by altering the REG-rtx's. */ | |
697 | ||
703ad42b KG |
698 | reg_equiv_constant = xcalloc (max_regno, sizeof (rtx)); |
699 | reg_equiv_mem = xcalloc (max_regno, sizeof (rtx)); | |
700 | reg_equiv_init = xcalloc (max_regno, sizeof (rtx)); | |
701 | reg_equiv_address = xcalloc (max_regno, sizeof (rtx)); | |
702 | reg_max_ref_width = xcalloc (max_regno, sizeof (int)); | |
703 | reg_old_renumber = xcalloc (max_regno, sizeof (short)); | |
4e135bdd | 704 | memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); |
703ad42b KG |
705 | pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET)); |
706 | pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET)); | |
32131a9c | 707 | |
03acd8f8 | 708 | CLEAR_HARD_REG_SET (bad_spill_regs_global); |
56f58d3a | 709 | |
d754127f ILT |
710 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent |
711 | to. Also find all paradoxical subregs and find largest such for | |
712 | each pseudo. */ | |
32131a9c | 713 | |
2b49ee39 | 714 | num_eliminable_invariants = 0; |
32131a9c RK |
715 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
716 | { | |
717 | rtx set = single_set (insn); | |
718 | ||
3d17d93d AO |
719 | /* We may introduce USEs that we want to remove at the end, so |
720 | we'll mark them with QImode. Make sure there are no | |
721 | previously-marked insns left by say regmove. */ | |
722 | if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE | |
723 | && GET_MODE (insn) != VOIDmode) | |
724 | PUT_MODE (insn, VOIDmode); | |
725 | ||
32131a9c RK |
726 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG) |
727 | { | |
fb3821f7 | 728 | rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
a8efe40d RK |
729 | if (note |
730 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
2b49ee39 R |
731 | && (! function_invariant_p (XEXP (note, 0)) |
732 | || ! flag_pic | |
129c0899 HPN |
733 | /* A function invariant is often CONSTANT_P but may |
734 | include a register. We promise to only pass | |
735 | CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ | |
736 | || (CONSTANT_P (XEXP (note, 0)) | |
737 | && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))) | |
a8efe40d RK |
738 | #endif |
739 | ) | |
32131a9c RK |
740 | { |
741 | rtx x = XEXP (note, 0); | |
742 | i = REGNO (SET_DEST (set)); | |
743 | if (i > LAST_VIRTUAL_REGISTER) | |
744 | { | |
6a45951f UW |
745 | /* It can happen that a REG_EQUIV note contains a MEM |
746 | that is not a legitimate memory operand. As later | |
747 | stages of reload assume that all addresses found | |
748 | in the reg_equiv_* arrays were originally legitimate, | |
749 | we ignore such REG_EQUIV notes. */ | |
750 | if (memory_operand (x, VOIDmode)) | |
956d6950 | 751 | { |
cf728d61 HPN |
752 | /* Always unshare the equivalence, so we can |
753 | substitute into this insn without touching the | |
2ba84f36 | 754 | equivalence. */ |
cf728d61 | 755 | reg_equiv_memory_loc[i] = copy_rtx (x); |
956d6950 | 756 | } |
2b49ee39 | 757 | else if (function_invariant_p (x)) |
32131a9c | 758 | { |
2b49ee39 R |
759 | if (GET_CODE (x) == PLUS) |
760 | { | |
761 | /* This is PLUS of frame pointer and a constant, | |
762 | and might be shared. Unshare it. */ | |
763 | reg_equiv_constant[i] = copy_rtx (x); | |
764 | num_eliminable_invariants++; | |
765 | } | |
766 | else if (x == frame_pointer_rtx | |
767 | || x == arg_pointer_rtx) | |
768 | { | |
769 | reg_equiv_constant[i] = x; | |
770 | num_eliminable_invariants++; | |
771 | } | |
772 | else if (LEGITIMATE_CONSTANT_P (x)) | |
32131a9c RK |
773 | reg_equiv_constant[i] = x; |
774 | else | |
3a04ff64 RH |
775 | { |
776 | reg_equiv_memory_loc[i] | |
777 | = force_const_mem (GET_MODE (SET_DEST (set)), x); | |
778 | if (!reg_equiv_memory_loc[i]) | |
779 | continue; | |
780 | } | |
32131a9c RK |
781 | } |
782 | else | |
783 | continue; | |
784 | ||
785 | /* If this register is being made equivalent to a MEM | |
786 | and the MEM is not SET_SRC, the equivalencing insn | |
787 | is one with the MEM as a SET_DEST and it occurs later. | |
788 | So don't mark this insn now. */ | |
789 | if (GET_CODE (x) != MEM | |
790 | || rtx_equal_p (SET_SRC (set), x)) | |
135eb61c R |
791 | reg_equiv_init[i] |
792 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]); | |
32131a9c RK |
793 | } |
794 | } | |
795 | } | |
796 | ||
797 | /* If this insn is setting a MEM from a register equivalent to it, | |
798 | this is the equivalencing insn. */ | |
799 | else if (set && GET_CODE (SET_DEST (set)) == MEM | |
800 | && GET_CODE (SET_SRC (set)) == REG | |
801 | && reg_equiv_memory_loc[REGNO (SET_SRC (set))] | |
802 | && rtx_equal_p (SET_DEST (set), | |
803 | reg_equiv_memory_loc[REGNO (SET_SRC (set))])) | |
135eb61c R |
804 | reg_equiv_init[REGNO (SET_SRC (set))] |
805 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
806 | reg_equiv_init[REGNO (SET_SRC (set))]); | |
32131a9c | 807 | |
2c3c49de | 808 | if (INSN_P (insn)) |
32131a9c RK |
809 | scan_paradoxical_subregs (PATTERN (insn)); |
810 | } | |
811 | ||
09dd1133 | 812 | init_elim_table (); |
32131a9c | 813 | |
4cc0fdd2 JDA |
814 | first_label_num = get_first_label_num (); |
815 | num_labels = max_label_num () - first_label_num; | |
32131a9c RK |
816 | |
817 | /* Allocate the tables used to store offset information at labels. */ | |
a68d4b75 BK |
818 | /* We used to use alloca here, but the size of what it would try to |
819 | allocate would occasionally cause it to exceed the stack limit and | |
820 | cause a core dump. */ | |
4cc0fdd2 | 821 | offsets_known_at = xmalloc (num_labels); |
b19ee4bd | 822 | offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT)); |
32131a9c | 823 | |
32131a9c RK |
824 | /* Alter each pseudo-reg rtx to contain its hard reg number. |
825 | Assign stack slots to the pseudos that lack hard regs or equivalents. | |
826 | Do not touch virtual registers. */ | |
827 | ||
828 | for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) | |
829 | alter_reg (i, -1); | |
830 | ||
32131a9c RK |
831 | /* If we have some registers we think can be eliminated, scan all insns to |
832 | see if there is an insn that sets one of these registers to something | |
833 | other than itself plus a constant. If so, the register cannot be | |
834 | eliminated. Doing this scan here eliminates an extra pass through the | |
835 | main reload loop in the most common case where register elimination | |
836 | cannot be done. */ | |
837 | for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) | |
838 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN | |
839 | || GET_CODE (insn) == CALL_INSN) | |
84832317 | 840 | note_stores (PATTERN (insn), mark_not_eliminable, NULL); |
32131a9c | 841 | |
18a90182 BS |
842 | maybe_fix_stack_asms (); |
843 | ||
03acd8f8 BS |
844 | insns_need_reload = 0; |
845 | something_needs_elimination = 0; | |
05d10675 | 846 | |
4079cd63 JW |
847 | /* Initialize to -1, which means take the first spill register. */ |
848 | last_spill_reg = -1; | |
849 | ||
32131a9c | 850 | /* Spill any hard regs that we know we can't eliminate. */ |
03acd8f8 | 851 | CLEAR_HARD_REG_SET (used_spill_regs); |
4ab51fb5 R |
852 | /* There can be multiple ways to eliminate a register; |
853 | they should be listed adjacently. | |
854 | Elimination for any register fails only if all possible ways fail. */ | |
855 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ) | |
856 | { | |
857 | int from = ep->from; | |
858 | int can_eliminate = 0; | |
859 | do | |
860 | { | |
861 | can_eliminate |= ep->can_eliminate; | |
862 | ep++; | |
863 | } | |
864 | while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from); | |
865 | if (! can_eliminate) | |
866 | spill_hard_reg (from, 1); | |
867 | } | |
9ff3516a RK |
868 | |
869 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
870 | if (frame_pointer_needed) | |
e04ca094 | 871 | spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1); |
9ff3516a | 872 | #endif |
e04ca094 | 873 | finish_spills (global); |
7609e720 | 874 | |
f1db3576 JL |
875 | /* From now on, we may need to generate moves differently. We may also |
876 | allow modifications of insns which cause them to not be recognized. | |
877 | Any such modifications will be cleaned up during reload itself. */ | |
b2f15f94 RK |
878 | reload_in_progress = 1; |
879 | ||
32131a9c RK |
880 | /* This loop scans the entire function each go-round |
881 | and repeats until one repetition spills no additional hard regs. */ | |
03acd8f8 | 882 | for (;;) |
32131a9c | 883 | { |
03acd8f8 BS |
884 | int something_changed; |
885 | int did_spill; | |
32131a9c | 886 | |
03acd8f8 | 887 | HOST_WIDE_INT starting_frame_size; |
32131a9c | 888 | |
665792eb | 889 | /* Round size of stack frame to stack_alignment_needed. This must be done |
7657bf2f JW |
890 | here because the stack size may be a part of the offset computation |
891 | for register elimination, and there might have been new stack slots | |
6d2f8887 | 892 | created in the last iteration of this loop. */ |
665792eb JH |
893 | if (cfun->stack_alignment_needed) |
894 | assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed); | |
7657bf2f JW |
895 | |
896 | starting_frame_size = get_frame_size (); | |
897 | ||
09dd1133 | 898 | set_initial_elim_offsets (); |
1f3b1e1a | 899 | set_initial_label_offsets (); |
03acd8f8 | 900 | |
32131a9c RK |
901 | /* For each pseudo register that has an equivalent location defined, |
902 | try to eliminate any eliminable registers (such as the frame pointer) | |
903 | assuming initial offsets for the replacement register, which | |
904 | is the normal case. | |
905 | ||
906 | If the resulting location is directly addressable, substitute | |
907 | the MEM we just got directly for the old REG. | |
908 | ||
909 | If it is not addressable but is a constant or the sum of a hard reg | |
910 | and constant, it is probably not addressable because the constant is | |
911 | out of range, in that case record the address; we will generate | |
912 | hairy code to compute the address in a register each time it is | |
6491dbbb RK |
913 | needed. Similarly if it is a hard register, but one that is not |
914 | valid as an address register. | |
32131a9c RK |
915 | |
916 | If the location is not addressable, but does not have one of the | |
917 | above forms, assign a stack slot. We have to do this to avoid the | |
918 | potential of producing lots of reloads if, e.g., a location involves | |
919 | a pseudo that didn't get a hard register and has an equivalent memory | |
920 | location that also involves a pseudo that didn't get a hard register. | |
921 | ||
922 | Perhaps at some point we will improve reload_when_needed handling | |
923 | so this problem goes away. But that's very hairy. */ | |
924 | ||
925 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
926 | if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) | |
927 | { | |
1914f5da | 928 | rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); |
32131a9c RK |
929 | |
930 | if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), | |
931 | XEXP (x, 0))) | |
932 | reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; | |
1f663989 | 933 | else if (CONSTANT_P (XEXP (x, 0)) |
6491dbbb RK |
934 | || (GET_CODE (XEXP (x, 0)) == REG |
935 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
936 | || (GET_CODE (XEXP (x, 0)) == PLUS |
937 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
938 | && (REGNO (XEXP (XEXP (x, 0), 0)) | |
939 | < FIRST_PSEUDO_REGISTER) | |
1f663989 | 940 | && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) |
32131a9c RK |
941 | reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; |
942 | else | |
943 | { | |
944 | /* Make a new stack slot. Then indicate that something | |
a8fdc208 | 945 | changed so we go back and recompute offsets for |
32131a9c RK |
946 | eliminable registers because the allocation of memory |
947 | below might change some offset. reg_equiv_{mem,address} | |
948 | will be set up for this pseudo on the next pass around | |
949 | the loop. */ | |
950 | reg_equiv_memory_loc[i] = 0; | |
951 | reg_equiv_init[i] = 0; | |
952 | alter_reg (i, -1); | |
32131a9c RK |
953 | } |
954 | } | |
a8fdc208 | 955 | |
437a710d BS |
956 | if (caller_save_needed) |
957 | setup_save_areas (); | |
958 | ||
03acd8f8 | 959 | /* If we allocated another stack slot, redo elimination bookkeeping. */ |
437a710d | 960 | if (starting_frame_size != get_frame_size ()) |
32131a9c RK |
961 | continue; |
962 | ||
437a710d | 963 | if (caller_save_needed) |
a8efe40d | 964 | { |
437a710d BS |
965 | save_call_clobbered_regs (); |
966 | /* That might have allocated new insn_chain structures. */ | |
703ad42b | 967 | reload_firstobj = obstack_alloc (&reload_obstack, 0); |
a8efe40d RK |
968 | } |
969 | ||
03acd8f8 BS |
970 | calculate_needs_all_insns (global); |
971 | ||
f5d8c9f4 | 972 | CLEAR_REG_SET (&spilled_pseudos); |
03acd8f8 BS |
973 | did_spill = 0; |
974 | ||
975 | something_changed = 0; | |
32131a9c | 976 | |
0dadecf6 RK |
977 | /* If we allocated any new memory locations, make another pass |
978 | since it might have changed elimination offsets. */ | |
979 | if (starting_frame_size != get_frame_size ()) | |
980 | something_changed = 1; | |
981 | ||
09dd1133 BS |
982 | { |
983 | HARD_REG_SET to_spill; | |
984 | CLEAR_HARD_REG_SET (to_spill); | |
985 | update_eliminables (&to_spill); | |
986 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
987 | if (TEST_HARD_REG_BIT (to_spill, i)) | |
32131a9c | 988 | { |
e04ca094 | 989 | spill_hard_reg (i, 1); |
03acd8f8 | 990 | did_spill = 1; |
8f5db3c1 JL |
991 | |
992 | /* Regardless of the state of spills, if we previously had | |
e591c83d | 993 | a register that we thought we could eliminate, but now can |
8f5db3c1 JL |
994 | not eliminate, we must run another pass. |
995 | ||
996 | Consider pseudos which have an entry in reg_equiv_* which | |
997 | reference an eliminable register. We must make another pass | |
998 | to update reg_equiv_* so that we do not substitute in the | |
999 | old value from when we thought the elimination could be | |
1000 | performed. */ | |
1001 | something_changed = 1; | |
32131a9c | 1002 | } |
09dd1133 | 1003 | } |
9ff3516a | 1004 | |
e04ca094 | 1005 | select_reload_regs (); |
e483bf9c BS |
1006 | if (failure) |
1007 | goto failed; | |
437a710d | 1008 | |
e483bf9c | 1009 | if (insns_need_reload != 0 || did_spill) |
e04ca094 | 1010 | something_changed |= finish_spills (global); |
7609e720 | 1011 | |
03acd8f8 BS |
1012 | if (! something_changed) |
1013 | break; | |
1014 | ||
1015 | if (caller_save_needed) | |
7609e720 | 1016 | delete_caller_save_insns (); |
f5d8c9f4 BS |
1017 | |
1018 | obstack_free (&reload_obstack, reload_firstobj); | |
32131a9c RK |
1019 | } |
1020 | ||
1021 | /* If global-alloc was run, notify it of any register eliminations we have | |
1022 | done. */ | |
1023 | if (global) | |
1024 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1025 | if (ep->can_eliminate) | |
1026 | mark_elimination (ep->from, ep->to); | |
1027 | ||
32131a9c RK |
1028 | /* If a pseudo has no hard reg, delete the insns that made the equivalence. |
1029 | If that insn didn't set the register (i.e., it copied the register to | |
1030 | memory), just delete that insn instead of the equivalencing insn plus | |
1031 | anything now dead. If we call delete_dead_insn on that insn, we may | |
135eb61c | 1032 | delete the insn that actually sets the register if the register dies |
32131a9c RK |
1033 | there and that is incorrect. */ |
1034 | ||
1035 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
135eb61c R |
1036 | { |
1037 | if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) | |
1038 | { | |
1039 | rtx list; | |
1040 | for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) | |
1041 | { | |
1042 | rtx equiv_insn = XEXP (list, 0); | |
78571511 RK |
1043 | |
1044 | /* If we already deleted the insn or if it may trap, we can't | |
1045 | delete it. The latter case shouldn't happen, but can | |
1046 | if an insn has a variable address, gets a REG_EH_REGION | |
1047 | note added to it, and then gets converted into an load | |
1048 | from a constant address. */ | |
1049 | if (GET_CODE (equiv_insn) == NOTE | |
1050 | || can_throw_internal (equiv_insn)) | |
1051 | ; | |
1052 | else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) | |
135eb61c R |
1053 | delete_dead_insn (equiv_insn); |
1054 | else | |
1055 | { | |
1056 | PUT_CODE (equiv_insn, NOTE); | |
1057 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
1058 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
1059 | } | |
1060 | } | |
1061 | } | |
1062 | } | |
32131a9c RK |
1063 | |
1064 | /* Use the reload registers where necessary | |
1065 | by generating move instructions to move the must-be-register | |
1066 | values into or out of the reload registers. */ | |
1067 | ||
03acd8f8 BS |
1068 | if (insns_need_reload != 0 || something_needs_elimination |
1069 | || something_needs_operands_changed) | |
c47f5ea5 | 1070 | { |
102870fb | 1071 | HOST_WIDE_INT old_frame_size = get_frame_size (); |
c47f5ea5 | 1072 | |
e04ca094 | 1073 | reload_as_needed (global); |
c47f5ea5 BS |
1074 | |
1075 | if (old_frame_size != get_frame_size ()) | |
1076 | abort (); | |
1077 | ||
1078 | if (num_eliminable) | |
1079 | verify_initial_elim_offsets (); | |
1080 | } | |
32131a9c | 1081 | |
2a1f8b6b | 1082 | /* If we were able to eliminate the frame pointer, show that it is no |
546b63fb | 1083 | longer live at the start of any basic block. If it ls live by |
2a1f8b6b RK |
1084 | virtue of being in a pseudo, that pseudo will be marked live |
1085 | and hence the frame pointer will be known to be live via that | |
1086 | pseudo. */ | |
1087 | ||
1088 | if (! frame_pointer_needed) | |
e0082a72 ZD |
1089 | FOR_EACH_BB (bb) |
1090 | CLEAR_REGNO_REG_SET (bb->global_live_at_start, | |
8e08106d | 1091 | HARD_FRAME_POINTER_REGNUM); |
2a1f8b6b | 1092 | |
5352b11a RS |
1093 | /* Come here (with failure set nonzero) if we can't get enough spill regs |
1094 | and we decide not to abort about it. */ | |
1095 | failed: | |
1096 | ||
f5d8c9f4 | 1097 | CLEAR_REG_SET (&spilled_pseudos); |
a3ec87a8 RS |
1098 | reload_in_progress = 0; |
1099 | ||
32131a9c RK |
1100 | /* Now eliminate all pseudo regs by modifying them into |
1101 | their equivalent memory references. | |
1102 | The REG-rtx's for the pseudos are modified in place, | |
1103 | so all insns that used to refer to them now refer to memory. | |
1104 | ||
1105 | For a reg that has a reg_equiv_address, all those insns | |
1106 | were changed by reloading so that no insns refer to it any longer; | |
1107 | but the DECL_RTL of a variable decl may refer to it, | |
1108 | and if so this causes the debugging info to mention the variable. */ | |
1109 | ||
1110 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1111 | { | |
1112 | rtx addr = 0; | |
9ec36da5 JL |
1113 | |
1114 | if (reg_equiv_mem[i]) | |
1115 | addr = XEXP (reg_equiv_mem[i], 0); | |
1116 | ||
32131a9c RK |
1117 | if (reg_equiv_address[i]) |
1118 | addr = reg_equiv_address[i]; | |
9ec36da5 | 1119 | |
32131a9c RK |
1120 | if (addr) |
1121 | { | |
1122 | if (reg_renumber[i] < 0) | |
1123 | { | |
1124 | rtx reg = regno_reg_rtx[i]; | |
173b24b9 | 1125 | |
5a63e069 | 1126 | REG_USERVAR_P (reg) = 0; |
ef178af3 | 1127 | PUT_CODE (reg, MEM); |
32131a9c | 1128 | XEXP (reg, 0) = addr; |
173b24b9 RK |
1129 | if (reg_equiv_memory_loc[i]) |
1130 | MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]); | |
1131 | else | |
1132 | { | |
1133 | RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg) | |
1134 | = MEM_SCALAR_P (reg) = 0; | |
1135 | MEM_ATTRS (reg) = 0; | |
1136 | } | |
32131a9c RK |
1137 | } |
1138 | else if (reg_equiv_mem[i]) | |
1139 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1140 | } | |
1141 | } | |
1142 | ||
2ae74651 JL |
1143 | /* We must set reload_completed now since the cleanup_subreg_operands call |
1144 | below will re-recognize each insn and reload may have generated insns | |
1145 | which are only valid during and after reload. */ | |
1146 | reload_completed = 1; | |
1147 | ||
bd695e1e RH |
1148 | /* Make a pass over all the insns and delete all USEs which we inserted |
1149 | only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED | |
41e34bab DJ |
1150 | notes. Delete all CLOBBER insns, except those that refer to the return |
1151 | value and the special mem:BLK CLOBBERs added to prevent the scheduler | |
1152 | from misarranging variable-array code, and simplify (subreg (reg)) | |
260f91c2 DJ |
1153 | operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they |
1154 | are no longer useful or accurate. Strip and regenerate REG_INC notes | |
1155 | that may have been moved around. */ | |
32131a9c RK |
1156 | |
1157 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 1158 | if (INSN_P (insn)) |
32131a9c | 1159 | { |
6764d250 | 1160 | rtx *pnote; |
32131a9c | 1161 | |
f474c6f8 | 1162 | if (GET_CODE (insn) == CALL_INSN) |
ee960939 OH |
1163 | replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn), |
1164 | VOIDmode, CALL_INSN_FUNCTION_USAGE (insn)); | |
f474c6f8 | 1165 | |
0304f787 | 1166 | if ((GET_CODE (PATTERN (insn)) == USE |
3d17d93d AO |
1167 | /* We mark with QImode USEs introduced by reload itself. */ |
1168 | && (GET_MODE (insn) == QImode | |
1169 | || find_reg_note (insn, REG_EQUAL, NULL_RTX))) | |
bd695e1e | 1170 | || (GET_CODE (PATTERN (insn)) == CLOBBER |
260f91c2 | 1171 | && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM |
41e34bab DJ |
1172 | || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode |
1173 | || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH | |
0c20a65f | 1174 | && XEXP (XEXP (PATTERN (insn), 0), 0) |
41e34bab | 1175 | != stack_pointer_rtx)) |
bd695e1e RH |
1176 | && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG |
1177 | || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) | |
b60a8416 | 1178 | { |
e5eac8ef | 1179 | delete_insn (insn); |
b60a8416 R |
1180 | continue; |
1181 | } | |
6764d250 | 1182 | |
ee960939 OH |
1183 | /* Some CLOBBERs may survive until here and still reference unassigned |
1184 | pseudos with const equivalent, which may in turn cause ICE in later | |
1185 | passes if the reference remains in place. */ | |
1186 | if (GET_CODE (PATTERN (insn)) == CLOBBER) | |
1187 | replace_pseudos_in (& XEXP (PATTERN (insn), 0), | |
1188 | VOIDmode, PATTERN (insn)); | |
1189 | ||
6764d250 BS |
1190 | pnote = ®_NOTES (insn); |
1191 | while (*pnote != 0) | |
32131a9c | 1192 | { |
6764d250 | 1193 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
80599fd9 | 1194 | || REG_NOTE_KIND (*pnote) == REG_UNUSED |
2dfa9a87 | 1195 | || REG_NOTE_KIND (*pnote) == REG_INC |
80599fd9 NC |
1196 | || REG_NOTE_KIND (*pnote) == REG_RETVAL |
1197 | || REG_NOTE_KIND (*pnote) == REG_LIBCALL) | |
6764d250 BS |
1198 | *pnote = XEXP (*pnote, 1); |
1199 | else | |
1200 | pnote = &XEXP (*pnote, 1); | |
32131a9c | 1201 | } |
0304f787 | 1202 | |
2dfa9a87 MH |
1203 | #ifdef AUTO_INC_DEC |
1204 | add_auto_inc_notes (insn, PATTERN (insn)); | |
1205 | #endif | |
1206 | ||
0304f787 JL |
1207 | /* And simplify (subreg (reg)) if it appears as an operand. */ |
1208 | cleanup_subreg_operands (insn); | |
b60a8416 | 1209 | } |
32131a9c | 1210 | |
ab87f8c8 JL |
1211 | /* If we are doing stack checking, give a warning if this function's |
1212 | frame size is larger than we expect. */ | |
1213 | if (flag_stack_check && ! STACK_CHECK_BUILTIN) | |
1214 | { | |
1215 | HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; | |
05d10675 BS |
1216 | static int verbose_warned = 0; |
1217 | ||
ab87f8c8 JL |
1218 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1219 | if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i]) | |
1220 | size += UNITS_PER_WORD; | |
1221 | ||
1222 | if (size > STACK_CHECK_MAX_FRAME_SIZE) | |
05d10675 | 1223 | { |
ab87f8c8 JL |
1224 | warning ("frame size too large for reliable stack checking"); |
1225 | if (! verbose_warned) | |
1226 | { | |
1227 | warning ("try reducing the number of local variables"); | |
1228 | verbose_warned = 1; | |
1229 | } | |
1230 | } | |
1231 | } | |
1232 | ||
32131a9c | 1233 | /* Indicate that we no longer have known memory locations or constants. */ |
58d9f9d9 JL |
1234 | if (reg_equiv_constant) |
1235 | free (reg_equiv_constant); | |
32131a9c | 1236 | reg_equiv_constant = 0; |
58d9f9d9 JL |
1237 | if (reg_equiv_memory_loc) |
1238 | free (reg_equiv_memory_loc); | |
32131a9c | 1239 | reg_equiv_memory_loc = 0; |
5352b11a | 1240 | |
4cc0fdd2 JDA |
1241 | if (offsets_known_at) |
1242 | free (offsets_known_at); | |
1243 | if (offsets_at) | |
1244 | free (offsets_at); | |
a68d4b75 | 1245 | |
56a65848 DB |
1246 | free (reg_equiv_mem); |
1247 | free (reg_equiv_init); | |
1248 | free (reg_equiv_address); | |
1249 | free (reg_max_ref_width); | |
03acd8f8 BS |
1250 | free (reg_old_renumber); |
1251 | free (pseudo_previous_regs); | |
1252 | free (pseudo_forbidden_regs); | |
56a65848 | 1253 | |
8b4f9969 JW |
1254 | CLEAR_HARD_REG_SET (used_spill_regs); |
1255 | for (i = 0; i < n_spills; i++) | |
1256 | SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); | |
1257 | ||
7609e720 BS |
1258 | /* Free all the insn_chain structures at once. */ |
1259 | obstack_free (&reload_obstack, reload_startobj); | |
1260 | unused_insn_chains = 0; | |
f1330226 | 1261 | fixup_abnormal_edges (); |
7609e720 | 1262 | |
e16e3291 UW |
1263 | /* Replacing pseudos with their memory equivalents might have |
1264 | created shared rtx. Subsequent passes would get confused | |
1265 | by this, so unshare everything here. */ | |
1266 | unshare_all_rtl_again (first); | |
1267 | ||
b483cfb7 EB |
1268 | #ifdef STACK_BOUNDARY |
1269 | /* init_emit has set the alignment of the hard frame pointer | |
1270 | to STACK_BOUNDARY. It is very likely no longer valid if | |
1271 | the hard frame pointer was used for register allocation. */ | |
1272 | if (!frame_pointer_needed) | |
1273 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; | |
1274 | #endif | |
1275 | ||
5352b11a | 1276 | return failure; |
32131a9c | 1277 | } |
1e5bd841 | 1278 | |
18a90182 BS |
1279 | /* Yet another special case. Unfortunately, reg-stack forces people to |
1280 | write incorrect clobbers in asm statements. These clobbers must not | |
1281 | cause the register to appear in bad_spill_regs, otherwise we'll call | |
1282 | fatal_insn later. We clear the corresponding regnos in the live | |
1283 | register sets to avoid this. | |
1284 | The whole thing is rather sick, I'm afraid. */ | |
efc9bd41 | 1285 | |
18a90182 | 1286 | static void |
0c20a65f | 1287 | maybe_fix_stack_asms (void) |
18a90182 BS |
1288 | { |
1289 | #ifdef STACK_REGS | |
392dccb7 | 1290 | const char *constraints[MAX_RECOG_OPERANDS]; |
18a90182 BS |
1291 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
1292 | struct insn_chain *chain; | |
1293 | ||
1294 | for (chain = reload_insn_chain; chain != 0; chain = chain->next) | |
1295 | { | |
1296 | int i, noperands; | |
1297 | HARD_REG_SET clobbered, allowed; | |
1298 | rtx pat; | |
1299 | ||
2c3c49de | 1300 | if (! INSN_P (chain->insn) |
18a90182 BS |
1301 | || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) |
1302 | continue; | |
1303 | pat = PATTERN (chain->insn); | |
1304 | if (GET_CODE (pat) != PARALLEL) | |
1305 | continue; | |
1306 | ||
1307 | CLEAR_HARD_REG_SET (clobbered); | |
1308 | CLEAR_HARD_REG_SET (allowed); | |
1309 | ||
1310 | /* First, make a mask of all stack regs that are clobbered. */ | |
1311 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
1312 | { | |
1313 | rtx t = XVECEXP (pat, 0, i); | |
1314 | if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) | |
1315 | SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); | |
1316 | } | |
1317 | ||
1318 | /* Get the operand values and constraints out of the insn. */ | |
1ccbefce | 1319 | decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, |
18a90182 BS |
1320 | constraints, operand_mode); |
1321 | ||
1322 | /* For every operand, see what registers are allowed. */ | |
1323 | for (i = 0; i < noperands; i++) | |
1324 | { | |
6b9c6f4f | 1325 | const char *p = constraints[i]; |
18a90182 BS |
1326 | /* For every alternative, we compute the class of registers allowed |
1327 | for reloading in CLS, and merge its contents into the reg set | |
1328 | ALLOWED. */ | |
1329 | int cls = (int) NO_REGS; | |
1330 | ||
1331 | for (;;) | |
1332 | { | |
97488870 | 1333 | char c = *p; |
18a90182 BS |
1334 | |
1335 | if (c == '\0' || c == ',' || c == '#') | |
1336 | { | |
1337 | /* End of one alternative - mark the regs in the current | |
1338 | class, and reset the class. */ | |
1339 | IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); | |
1340 | cls = NO_REGS; | |
97488870 | 1341 | p++; |
18a90182 BS |
1342 | if (c == '#') |
1343 | do { | |
1344 | c = *p++; | |
1345 | } while (c != '\0' && c != ','); | |
1346 | if (c == '\0') | |
1347 | break; | |
1348 | continue; | |
1349 | } | |
1350 | ||
1351 | switch (c) | |
1352 | { | |
1353 | case '=': case '+': case '*': case '%': case '?': case '!': | |
1354 | case '0': case '1': case '2': case '3': case '4': case 'm': | |
1355 | case '<': case '>': case 'V': case 'o': case '&': case 'E': | |
1356 | case 'F': case 's': case 'i': case 'n': case 'X': case 'I': | |
1357 | case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': | |
1358 | case 'P': | |
18a90182 BS |
1359 | break; |
1360 | ||
1361 | case 'p': | |
3dcc68a4 NC |
1362 | cls = (int) reg_class_subunion[cls] |
1363 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
18a90182 BS |
1364 | break; |
1365 | ||
1366 | case 'g': | |
1367 | case 'r': | |
1368 | cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; | |
1369 | break; | |
1370 | ||
1371 | default: | |
97488870 | 1372 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) |
ccfc6cc8 UW |
1373 | cls = (int) reg_class_subunion[cls] |
1374 | [(int) MODE_BASE_REG_CLASS (VOIDmode)]; | |
1375 | else | |
1376 | cls = (int) reg_class_subunion[cls] | |
97488870 | 1377 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; |
18a90182 | 1378 | } |
97488870 | 1379 | p += CONSTRAINT_LEN (c, p); |
18a90182 BS |
1380 | } |
1381 | } | |
1382 | /* Those of the registers which are clobbered, but allowed by the | |
1383 | constraints, must be usable as reload registers. So clear them | |
1384 | out of the life information. */ | |
1385 | AND_HARD_REG_SET (allowed, clobbered); | |
1386 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1387 | if (TEST_HARD_REG_BIT (allowed, i)) | |
1388 | { | |
239a0f5b BS |
1389 | CLEAR_REGNO_REG_SET (&chain->live_throughout, i); |
1390 | CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); | |
18a90182 BS |
1391 | } |
1392 | } | |
1393 | ||
1394 | #endif | |
1395 | } | |
03acd8f8 | 1396 | \f |
f5d8c9f4 BS |
1397 | /* Copy the global variables n_reloads and rld into the corresponding elts |
1398 | of CHAIN. */ | |
1399 | static void | |
0c20a65f | 1400 | copy_reloads (struct insn_chain *chain) |
f5d8c9f4 BS |
1401 | { |
1402 | chain->n_reloads = n_reloads; | |
703ad42b KG |
1403 | chain->rld = obstack_alloc (&reload_obstack, |
1404 | n_reloads * sizeof (struct reload)); | |
f5d8c9f4 | 1405 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
703ad42b | 1406 | reload_insn_firstobj = obstack_alloc (&reload_obstack, 0); |
f5d8c9f4 BS |
1407 | } |
1408 | ||
03acd8f8 BS |
1409 | /* Walk the chain of insns, and determine for each whether it needs reloads |
1410 | and/or eliminations. Build the corresponding insns_need_reload list, and | |
1411 | set something_needs_elimination as appropriate. */ | |
1412 | static void | |
0c20a65f | 1413 | calculate_needs_all_insns (int global) |
1e5bd841 | 1414 | { |
7609e720 | 1415 | struct insn_chain **pprev_reload = &insns_need_reload; |
462561b7 | 1416 | struct insn_chain *chain, *next = 0; |
1e5bd841 | 1417 | |
03acd8f8 BS |
1418 | something_needs_elimination = 0; |
1419 | ||
703ad42b | 1420 | reload_insn_firstobj = obstack_alloc (&reload_obstack, 0); |
462561b7 | 1421 | for (chain = reload_insn_chain; chain != 0; chain = next) |
1e5bd841 | 1422 | { |
67e61fe7 | 1423 | rtx insn = chain->insn; |
03acd8f8 | 1424 | |
462561b7 JJ |
1425 | next = chain->next; |
1426 | ||
f5d8c9f4 BS |
1427 | /* Clear out the shortcuts. */ |
1428 | chain->n_reloads = 0; | |
67e61fe7 BS |
1429 | chain->need_elim = 0; |
1430 | chain->need_reload = 0; | |
1431 | chain->need_operand_change = 0; | |
1e5bd841 | 1432 | |
03acd8f8 BS |
1433 | /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might |
1434 | include REG_LABEL), we need to see what effects this has on the | |
1435 | known offsets at labels. */ | |
1e5bd841 BS |
1436 | |
1437 | if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN | |
2c3c49de | 1438 | || (INSN_P (insn) && REG_NOTES (insn) != 0)) |
1e5bd841 BS |
1439 | set_label_offsets (insn, insn, 0); |
1440 | ||
2c3c49de | 1441 | if (INSN_P (insn)) |
1e5bd841 BS |
1442 | { |
1443 | rtx old_body = PATTERN (insn); | |
1444 | int old_code = INSN_CODE (insn); | |
1445 | rtx old_notes = REG_NOTES (insn); | |
1446 | int did_elimination = 0; | |
cb2afeb3 | 1447 | int operands_changed = 0; |
2b49ee39 R |
1448 | rtx set = single_set (insn); |
1449 | ||
1450 | /* Skip insns that only set an equivalence. */ | |
1451 | if (set && GET_CODE (SET_DEST (set)) == REG | |
1452 | && reg_renumber[REGNO (SET_DEST (set))] < 0 | |
1453 | && reg_equiv_constant[REGNO (SET_DEST (set))]) | |
67e61fe7 | 1454 | continue; |
1e5bd841 | 1455 | |
1e5bd841 | 1456 | /* If needed, eliminate any eliminable registers. */ |
2b49ee39 | 1457 | if (num_eliminable || num_eliminable_invariants) |
1e5bd841 BS |
1458 | did_elimination = eliminate_regs_in_insn (insn, 0); |
1459 | ||
1460 | /* Analyze the instruction. */ | |
cb2afeb3 R |
1461 | operands_changed = find_reloads (insn, 0, spill_indirect_levels, |
1462 | global, spill_reg_order); | |
1463 | ||
1464 | /* If a no-op set needs more than one reload, this is likely | |
1465 | to be something that needs input address reloads. We | |
1466 | can't get rid of this cleanly later, and it is of no use | |
1467 | anyway, so discard it now. | |
1468 | We only do this when expensive_optimizations is enabled, | |
1469 | since this complements reload inheritance / output | |
1470 | reload deletion, and it can make debugging harder. */ | |
1471 | if (flag_expensive_optimizations && n_reloads > 1) | |
1472 | { | |
1473 | rtx set = single_set (insn); | |
1474 | if (set | |
1475 | && SET_SRC (set) == SET_DEST (set) | |
1476 | && GET_CODE (SET_SRC (set)) == REG | |
1477 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1478 | { | |
ca6c03ca | 1479 | delete_insn (insn); |
3eae4643 | 1480 | /* Delete it from the reload chain. */ |
462561b7 JJ |
1481 | if (chain->prev) |
1482 | chain->prev->next = next; | |
1483 | else | |
1484 | reload_insn_chain = next; | |
1485 | if (next) | |
1486 | next->prev = chain->prev; | |
1487 | chain->next = unused_insn_chains; | |
1488 | unused_insn_chains = chain; | |
cb2afeb3 R |
1489 | continue; |
1490 | } | |
1491 | } | |
1492 | if (num_eliminable) | |
1493 | update_eliminable_offsets (); | |
1e5bd841 BS |
1494 | |
1495 | /* Remember for later shortcuts which insns had any reloads or | |
7609e720 BS |
1496 | register eliminations. */ |
1497 | chain->need_elim = did_elimination; | |
03acd8f8 BS |
1498 | chain->need_reload = n_reloads > 0; |
1499 | chain->need_operand_change = operands_changed; | |
1e5bd841 BS |
1500 | |
1501 | /* Discard any register replacements done. */ | |
1502 | if (did_elimination) | |
1503 | { | |
f5d8c9f4 | 1504 | obstack_free (&reload_obstack, reload_insn_firstobj); |
1e5bd841 BS |
1505 | PATTERN (insn) = old_body; |
1506 | INSN_CODE (insn) = old_code; | |
1507 | REG_NOTES (insn) = old_notes; | |
1508 | something_needs_elimination = 1; | |
1509 | } | |
1510 | ||
cb2afeb3 R |
1511 | something_needs_operands_changed |= operands_changed; |
1512 | ||
437a710d | 1513 | if (n_reloads != 0) |
7609e720 | 1514 | { |
f5d8c9f4 | 1515 | copy_reloads (chain); |
7609e720 BS |
1516 | *pprev_reload = chain; |
1517 | pprev_reload = &chain->next_need_reload; | |
7609e720 | 1518 | } |
1e5bd841 | 1519 | } |
1e5bd841 | 1520 | } |
7609e720 | 1521 | *pprev_reload = 0; |
1e5bd841 | 1522 | } |
f5d8c9f4 BS |
1523 | \f |
1524 | /* Comparison function for qsort to decide which of two reloads | |
1525 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
1e5bd841 | 1526 | |
f5d8c9f4 | 1527 | static int |
0c20a65f | 1528 | reload_reg_class_lower (const void *r1p, const void *r2p) |
1e5bd841 | 1529 | { |
b3694847 SS |
1530 | int r1 = *(const short *) r1p, r2 = *(const short *) r2p; |
1531 | int t; | |
1e5bd841 | 1532 | |
f5d8c9f4 BS |
1533 | /* Consider required reloads before optional ones. */ |
1534 | t = rld[r1].optional - rld[r2].optional; | |
1535 | if (t != 0) | |
1536 | return t; | |
1e5bd841 | 1537 | |
f5d8c9f4 BS |
1538 | /* Count all solitary classes before non-solitary ones. */ |
1539 | t = ((reg_class_size[(int) rld[r2].class] == 1) | |
1540 | - (reg_class_size[(int) rld[r1].class] == 1)); | |
1541 | if (t != 0) | |
1542 | return t; | |
1e5bd841 | 1543 | |
f5d8c9f4 BS |
1544 | /* Aside from solitaires, consider all multi-reg groups first. */ |
1545 | t = rld[r2].nregs - rld[r1].nregs; | |
1546 | if (t != 0) | |
1547 | return t; | |
1e5bd841 | 1548 | |
f5d8c9f4 BS |
1549 | /* Consider reloads in order of increasing reg-class number. */ |
1550 | t = (int) rld[r1].class - (int) rld[r2].class; | |
1551 | if (t != 0) | |
1552 | return t; | |
1e5bd841 | 1553 | |
f5d8c9f4 BS |
1554 | /* If reloads are equally urgent, sort by reload number, |
1555 | so that the results of qsort leave nothing to chance. */ | |
1556 | return r1 - r2; | |
1557 | } | |
1558 | \f | |
1559 | /* The cost of spilling each hard reg. */ | |
1560 | static int spill_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1561 | |
f5d8c9f4 BS |
1562 | /* When spilling multiple hard registers, we use SPILL_COST for the first |
1563 | spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST | |
1564 | only the first hard reg for a multi-reg pseudo. */ | |
1565 | static int spill_add_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1566 | |
f5d8c9f4 | 1567 | /* Update the spill cost arrays, considering that pseudo REG is live. */ |
770ae6cc | 1568 | |
f5d8c9f4 | 1569 | static void |
0c20a65f | 1570 | count_pseudo (int reg) |
f5d8c9f4 | 1571 | { |
b2aec5c0 | 1572 | int freq = REG_FREQ (reg); |
f5d8c9f4 BS |
1573 | int r = reg_renumber[reg]; |
1574 | int nregs; | |
1e5bd841 | 1575 | |
f5d8c9f4 BS |
1576 | if (REGNO_REG_SET_P (&pseudos_counted, reg) |
1577 | || REGNO_REG_SET_P (&spilled_pseudos, reg)) | |
1578 | return; | |
1e5bd841 | 1579 | |
f5d8c9f4 | 1580 | SET_REGNO_REG_SET (&pseudos_counted, reg); |
1e5bd841 | 1581 | |
f5d8c9f4 BS |
1582 | if (r < 0) |
1583 | abort (); | |
1d7254c5 | 1584 | |
b2aec5c0 | 1585 | spill_add_cost[r] += freq; |
1e5bd841 | 1586 | |
66fd46b6 | 1587 | nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)]; |
f5d8c9f4 | 1588 | while (nregs-- > 0) |
b2aec5c0 | 1589 | spill_cost[r + nregs] += freq; |
f5d8c9f4 | 1590 | } |
1e5bd841 | 1591 | |
f5d8c9f4 BS |
1592 | /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the |
1593 | contents of BAD_SPILL_REGS for the insn described by CHAIN. */ | |
efc9bd41 | 1594 | |
f5d8c9f4 | 1595 | static void |
0c20a65f | 1596 | order_regs_for_reload (struct insn_chain *chain) |
f5d8c9f4 | 1597 | { |
fbd40359 | 1598 | int i; |
efc9bd41 RK |
1599 | HARD_REG_SET used_by_pseudos; |
1600 | HARD_REG_SET used_by_pseudos2; | |
1e5bd841 | 1601 | |
efc9bd41 | 1602 | COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set); |
1e5bd841 | 1603 | |
f5d8c9f4 BS |
1604 | memset (spill_cost, 0, sizeof spill_cost); |
1605 | memset (spill_add_cost, 0, sizeof spill_add_cost); | |
1e5bd841 | 1606 | |
f5d8c9f4 | 1607 | /* Count number of uses of each hard reg by pseudo regs allocated to it |
efc9bd41 RK |
1608 | and then order them by decreasing use. First exclude hard registers |
1609 | that are live in or across this insn. */ | |
1610 | ||
1611 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); | |
1612 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
1613 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos); | |
1614 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2); | |
1e5bd841 | 1615 | |
f5d8c9f4 BS |
1616 | /* Now find out which pseudos are allocated to it, and update |
1617 | hard_reg_n_uses. */ | |
1618 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1619 | |
f5d8c9f4 | 1620 | EXECUTE_IF_SET_IN_REG_SET |
fbd40359 | 1621 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, |
f5d8c9f4 | 1622 | { |
fbd40359 | 1623 | count_pseudo (i); |
f5d8c9f4 BS |
1624 | }); |
1625 | EXECUTE_IF_SET_IN_REG_SET | |
fbd40359 | 1626 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, |
f5d8c9f4 | 1627 | { |
fbd40359 | 1628 | count_pseudo (i); |
f5d8c9f4 BS |
1629 | }); |
1630 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1631 | } |
03acd8f8 | 1632 | \f |
f5d8c9f4 BS |
1633 | /* Vector of reload-numbers showing the order in which the reloads should |
1634 | be processed. */ | |
1635 | static short reload_order[MAX_RELOADS]; | |
1e5bd841 | 1636 | |
f5d8c9f4 BS |
1637 | /* This is used to keep track of the spill regs used in one insn. */ |
1638 | static HARD_REG_SET used_spill_regs_local; | |
03acd8f8 | 1639 | |
f5d8c9f4 BS |
1640 | /* We decided to spill hard register SPILLED, which has a size of |
1641 | SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, | |
1642 | is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will | |
1643 | update SPILL_COST/SPILL_ADD_COST. */ | |
770ae6cc | 1644 | |
03acd8f8 | 1645 | static void |
0c20a65f | 1646 | count_spilled_pseudo (int spilled, int spilled_nregs, int reg) |
1e5bd841 | 1647 | { |
f5d8c9f4 | 1648 | int r = reg_renumber[reg]; |
66fd46b6 | 1649 | int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)]; |
1e5bd841 | 1650 | |
f5d8c9f4 BS |
1651 | if (REGNO_REG_SET_P (&spilled_pseudos, reg) |
1652 | || spilled + spilled_nregs <= r || r + nregs <= spilled) | |
1653 | return; | |
1e5bd841 | 1654 | |
f5d8c9f4 | 1655 | SET_REGNO_REG_SET (&spilled_pseudos, reg); |
1e5bd841 | 1656 | |
b2aec5c0 | 1657 | spill_add_cost[r] -= REG_FREQ (reg); |
f5d8c9f4 | 1658 | while (nregs-- > 0) |
b2aec5c0 | 1659 | spill_cost[r + nregs] -= REG_FREQ (reg); |
1e5bd841 BS |
1660 | } |
1661 | ||
f5d8c9f4 | 1662 | /* Find reload register to use for reload number ORDER. */ |
03acd8f8 | 1663 | |
f5d8c9f4 | 1664 | static int |
0c20a65f | 1665 | find_reg (struct insn_chain *chain, int order) |
1e5bd841 | 1666 | { |
f5d8c9f4 BS |
1667 | int rnum = reload_order[order]; |
1668 | struct reload *rl = rld + rnum; | |
1669 | int best_cost = INT_MAX; | |
1670 | int best_reg = -1; | |
770ae6cc RK |
1671 | unsigned int i, j; |
1672 | int k; | |
f5d8c9f4 BS |
1673 | HARD_REG_SET not_usable; |
1674 | HARD_REG_SET used_by_other_reload; | |
1e5bd841 | 1675 | |
f5d8c9f4 BS |
1676 | COPY_HARD_REG_SET (not_usable, bad_spill_regs); |
1677 | IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); | |
1678 | IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]); | |
1679 | ||
1680 | CLEAR_HARD_REG_SET (used_by_other_reload); | |
770ae6cc | 1681 | for (k = 0; k < order; k++) |
1e5bd841 | 1682 | { |
770ae6cc RK |
1683 | int other = reload_order[k]; |
1684 | ||
f5d8c9f4 BS |
1685 | if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) |
1686 | for (j = 0; j < rld[other].nregs; j++) | |
1687 | SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); | |
1688 | } | |
1e5bd841 | 1689 | |
f5d8c9f4 BS |
1690 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1691 | { | |
770ae6cc RK |
1692 | unsigned int regno = i; |
1693 | ||
f5d8c9f4 BS |
1694 | if (! TEST_HARD_REG_BIT (not_usable, regno) |
1695 | && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) | |
1696 | && HARD_REGNO_MODE_OK (regno, rl->mode)) | |
1e5bd841 | 1697 | { |
f5d8c9f4 BS |
1698 | int this_cost = spill_cost[regno]; |
1699 | int ok = 1; | |
66fd46b6 | 1700 | unsigned int this_nregs = hard_regno_nregs[regno][rl->mode]; |
1e5bd841 | 1701 | |
f5d8c9f4 BS |
1702 | for (j = 1; j < this_nregs; j++) |
1703 | { | |
1704 | this_cost += spill_add_cost[regno + j]; | |
1705 | if ((TEST_HARD_REG_BIT (not_usable, regno + j)) | |
1706 | || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) | |
1707 | ok = 0; | |
1708 | } | |
1709 | if (! ok) | |
1710 | continue; | |
1711 | if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno) | |
1712 | this_cost--; | |
1713 | if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno) | |
1714 | this_cost--; | |
1715 | if (this_cost < best_cost | |
1716 | /* Among registers with equal cost, prefer caller-saved ones, or | |
1717 | use REG_ALLOC_ORDER if it is defined. */ | |
1718 | || (this_cost == best_cost | |
1719 | #ifdef REG_ALLOC_ORDER | |
1720 | && (inv_reg_alloc_order[regno] | |
1721 | < inv_reg_alloc_order[best_reg]) | |
1722 | #else | |
1723 | && call_used_regs[regno] | |
1724 | && ! call_used_regs[best_reg] | |
1725 | #endif | |
1726 | )) | |
1727 | { | |
1728 | best_reg = regno; | |
1729 | best_cost = this_cost; | |
1e5bd841 BS |
1730 | } |
1731 | } | |
1732 | } | |
f5d8c9f4 BS |
1733 | if (best_reg == -1) |
1734 | return 0; | |
770ae6cc | 1735 | |
c263766c RH |
1736 | if (dump_file) |
1737 | fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum); | |
770ae6cc | 1738 | |
66fd46b6 | 1739 | rl->nregs = hard_regno_nregs[best_reg][rl->mode]; |
f5d8c9f4 | 1740 | rl->regno = best_reg; |
1e5bd841 | 1741 | |
f5d8c9f4 | 1742 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1743 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1744 | { |
1745 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1746 | }); | |
770ae6cc | 1747 | |
f5d8c9f4 | 1748 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1749 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1750 | { |
1751 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1752 | }); | |
03acd8f8 | 1753 | |
f5d8c9f4 BS |
1754 | for (i = 0; i < rl->nregs; i++) |
1755 | { | |
1756 | if (spill_cost[best_reg + i] != 0 | |
1757 | || spill_add_cost[best_reg + i] != 0) | |
1758 | abort (); | |
1759 | SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); | |
1760 | } | |
1761 | return 1; | |
03acd8f8 BS |
1762 | } |
1763 | ||
1764 | /* Find more reload regs to satisfy the remaining need of an insn, which | |
1765 | is given by CHAIN. | |
1e5bd841 BS |
1766 | Do it by ascending class number, since otherwise a reg |
1767 | might be spilled for a big class and might fail to count | |
f5d8c9f4 | 1768 | for a smaller class even though it belongs to that class. */ |
1e5bd841 | 1769 | |
03acd8f8 | 1770 | static void |
0c20a65f | 1771 | find_reload_regs (struct insn_chain *chain) |
1e5bd841 | 1772 | { |
f5d8c9f4 | 1773 | int i; |
1e5bd841 | 1774 | |
f5d8c9f4 BS |
1775 | /* In order to be certain of getting the registers we need, |
1776 | we must sort the reloads into order of increasing register class. | |
1777 | Then our grabbing of reload registers will parallel the process | |
1778 | that provided the reload registers. */ | |
1779 | for (i = 0; i < chain->n_reloads; i++) | |
1e5bd841 | 1780 | { |
f5d8c9f4 BS |
1781 | /* Show whether this reload already has a hard reg. */ |
1782 | if (chain->rld[i].reg_rtx) | |
1e5bd841 | 1783 | { |
f5d8c9f4 BS |
1784 | int regno = REGNO (chain->rld[i].reg_rtx); |
1785 | chain->rld[i].regno = regno; | |
770ae6cc | 1786 | chain->rld[i].nregs |
66fd46b6 | 1787 | = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)]; |
1e5bd841 | 1788 | } |
f5d8c9f4 BS |
1789 | else |
1790 | chain->rld[i].regno = -1; | |
1791 | reload_order[i] = i; | |
1792 | } | |
1e5bd841 | 1793 | |
f5d8c9f4 BS |
1794 | n_reloads = chain->n_reloads; |
1795 | memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); | |
1e5bd841 | 1796 | |
f5d8c9f4 | 1797 | CLEAR_HARD_REG_SET (used_spill_regs_local); |
03acd8f8 | 1798 | |
c263766c RH |
1799 | if (dump_file) |
1800 | fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn)); | |
1e5bd841 | 1801 | |
f5d8c9f4 | 1802 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); |
1e5bd841 | 1803 | |
f5d8c9f4 | 1804 | /* Compute the order of preference for hard registers to spill. */ |
1e5bd841 | 1805 | |
f5d8c9f4 | 1806 | order_regs_for_reload (chain); |
1e5bd841 | 1807 | |
f5d8c9f4 BS |
1808 | for (i = 0; i < n_reloads; i++) |
1809 | { | |
1810 | int r = reload_order[i]; | |
1e5bd841 | 1811 | |
f5d8c9f4 BS |
1812 | /* Ignore reloads that got marked inoperative. */ |
1813 | if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) | |
1814 | && ! rld[r].optional | |
1815 | && rld[r].regno == -1) | |
e04ca094 | 1816 | if (! find_reg (chain, i)) |
f5d8c9f4 | 1817 | { |
ecf3151a | 1818 | spill_failure (chain->insn, rld[r].class); |
f5d8c9f4 | 1819 | failure = 1; |
03acd8f8 | 1820 | return; |
f5d8c9f4 | 1821 | } |
1e5bd841 | 1822 | } |
05d10675 | 1823 | |
f5d8c9f4 BS |
1824 | COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local); |
1825 | IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local); | |
03acd8f8 | 1826 | |
f5d8c9f4 | 1827 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
1e5bd841 BS |
1828 | } |
1829 | ||
f5d8c9f4 | 1830 | static void |
0c20a65f | 1831 | select_reload_regs (void) |
09dd1133 | 1832 | { |
f5d8c9f4 | 1833 | struct insn_chain *chain; |
09dd1133 | 1834 | |
f5d8c9f4 BS |
1835 | /* Try to satisfy the needs for each insn. */ |
1836 | for (chain = insns_need_reload; chain != 0; | |
1837 | chain = chain->next_need_reload) | |
e04ca094 | 1838 | find_reload_regs (chain); |
09dd1133 | 1839 | } |
32131a9c | 1840 | \f |
437a710d BS |
1841 | /* Delete all insns that were inserted by emit_caller_save_insns during |
1842 | this iteration. */ | |
1843 | static void | |
0c20a65f | 1844 | delete_caller_save_insns (void) |
437a710d | 1845 | { |
7609e720 | 1846 | struct insn_chain *c = reload_insn_chain; |
437a710d | 1847 | |
7609e720 | 1848 | while (c != 0) |
437a710d | 1849 | { |
7609e720 | 1850 | while (c != 0 && c->is_caller_save_insn) |
437a710d | 1851 | { |
7609e720 BS |
1852 | struct insn_chain *next = c->next; |
1853 | rtx insn = c->insn; | |
1854 | ||
7609e720 BS |
1855 | if (c == reload_insn_chain) |
1856 | reload_insn_chain = next; | |
ca6c03ca | 1857 | delete_insn (insn); |
7609e720 BS |
1858 | |
1859 | if (next) | |
1860 | next->prev = c->prev; | |
1861 | if (c->prev) | |
1862 | c->prev->next = next; | |
1863 | c->next = unused_insn_chains; | |
1864 | unused_insn_chains = c; | |
1865 | c = next; | |
437a710d | 1866 | } |
7609e720 BS |
1867 | if (c != 0) |
1868 | c = c->next; | |
437a710d BS |
1869 | } |
1870 | } | |
1871 | \f | |
5352b11a RS |
1872 | /* Handle the failure to find a register to spill. |
1873 | INSN should be one of the insns which needed this particular spill reg. */ | |
1874 | ||
1875 | static void | |
0c20a65f | 1876 | spill_failure (rtx insn, enum reg_class class) |
5352b11a | 1877 | { |
ecf3151a | 1878 | static const char *const reg_class_names[] = REG_CLASS_NAMES; |
5352b11a | 1879 | if (asm_noperands (PATTERN (insn)) >= 0) |
1f978f5f | 1880 | error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'", |
ecf3151a | 1881 | reg_class_names[class]); |
5352b11a | 1882 | else |
ecf3151a | 1883 | { |
1f978f5f | 1884 | error ("unable to find a register to spill in class `%s'", |
ecf3151a | 1885 | reg_class_names[class]); |
1f978f5f | 1886 | fatal_insn ("this is the insn:", insn); |
ecf3151a | 1887 | } |
5352b11a | 1888 | } |
32131a9c RK |
1889 | \f |
1890 | /* Delete an unneeded INSN and any previous insns who sole purpose is loading | |
1891 | data that is dead in INSN. */ | |
1892 | ||
1893 | static void | |
0c20a65f | 1894 | delete_dead_insn (rtx insn) |
32131a9c RK |
1895 | { |
1896 | rtx prev = prev_real_insn (insn); | |
1897 | rtx prev_dest; | |
1898 | ||
1899 | /* If the previous insn sets a register that dies in our insn, delete it | |
1900 | too. */ | |
1901 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
1902 | && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) | |
1903 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
b294ca38 R |
1904 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) |
1905 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
32131a9c RK |
1906 | delete_dead_insn (prev); |
1907 | ||
1908 | PUT_CODE (insn, NOTE); | |
1909 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1910 | NOTE_SOURCE_FILE (insn) = 0; | |
1911 | } | |
1912 | ||
1913 | /* Modify the home of pseudo-reg I. | |
1914 | The new home is present in reg_renumber[I]. | |
1915 | ||
1916 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
1917 | or it may be -1, meaning there is none or it is not relevant. | |
1918 | This is used so that all pseudos spilled from a given hard reg | |
1919 | can share one stack slot. */ | |
1920 | ||
1921 | static void | |
0c20a65f | 1922 | alter_reg (int i, int from_reg) |
32131a9c RK |
1923 | { |
1924 | /* When outputting an inline function, this can happen | |
1925 | for a reg that isn't actually used. */ | |
1926 | if (regno_reg_rtx[i] == 0) | |
1927 | return; | |
1928 | ||
1929 | /* If the reg got changed to a MEM at rtl-generation time, | |
1930 | ignore it. */ | |
1931 | if (GET_CODE (regno_reg_rtx[i]) != REG) | |
1932 | return; | |
1933 | ||
1934 | /* Modify the reg-rtx to contain the new hard reg | |
1935 | number or else to contain its pseudo reg number. */ | |
1936 | REGNO (regno_reg_rtx[i]) | |
1937 | = reg_renumber[i] >= 0 ? reg_renumber[i] : i; | |
1938 | ||
1939 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
1940 | allocate a stack slot for it. */ | |
1941 | ||
1942 | if (reg_renumber[i] < 0 | |
b1f21e0a | 1943 | && REG_N_REFS (i) > 0 |
32131a9c RK |
1944 | && reg_equiv_constant[i] == 0 |
1945 | && reg_equiv_memory_loc[i] == 0) | |
1946 | { | |
b3694847 | 1947 | rtx x; |
770ae6cc RK |
1948 | unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); |
1949 | unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]); | |
32131a9c RK |
1950 | int adjust = 0; |
1951 | ||
1952 | /* Each pseudo reg has an inherent size which comes from its own mode, | |
1953 | and a total size which provides room for paradoxical subregs | |
1954 | which refer to the pseudo reg in wider modes. | |
1955 | ||
1956 | We can use a slot already allocated if it provides both | |
1957 | enough inherent space and enough total space. | |
1958 | Otherwise, we allocate a new slot, making sure that it has no less | |
1959 | inherent space, and no less total space, then the previous slot. */ | |
1960 | if (from_reg == -1) | |
1961 | { | |
1962 | /* No known place to spill from => no slot to reuse. */ | |
cabcf079 ILT |
1963 | x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, |
1964 | inherent_size == total_size ? 0 : -1); | |
f76b9db2 | 1965 | if (BYTES_BIG_ENDIAN) |
02db8dd0 RK |
1966 | /* Cancel the big-endian correction done in assign_stack_local. |
1967 | Get the address of the beginning of the slot. | |
1968 | This is so we can do a big-endian correction unconditionally | |
1969 | below. */ | |
1970 | adjust = inherent_size - total_size; | |
1971 | ||
1972 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); | |
3bdf5ad1 RK |
1973 | |
1974 | /* Nothing can alias this slot except this pseudo. */ | |
ba4828e0 | 1975 | set_mem_alias_set (x, new_alias_set ()); |
32131a9c | 1976 | } |
3bdf5ad1 | 1977 | |
32131a9c RK |
1978 | /* Reuse a stack slot if possible. */ |
1979 | else if (spill_stack_slot[from_reg] != 0 | |
1980 | && spill_stack_slot_width[from_reg] >= total_size | |
1981 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
1982 | >= inherent_size)) | |
1983 | x = spill_stack_slot[from_reg]; | |
3bdf5ad1 | 1984 | |
32131a9c RK |
1985 | /* Allocate a bigger slot. */ |
1986 | else | |
1987 | { | |
1988 | /* Compute maximum size needed, both for inherent size | |
1989 | and for total size. */ | |
1990 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); | |
4f2d3674 | 1991 | rtx stack_slot; |
3bdf5ad1 | 1992 | |
32131a9c RK |
1993 | if (spill_stack_slot[from_reg]) |
1994 | { | |
1995 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
1996 | > inherent_size) | |
1997 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
1998 | if (spill_stack_slot_width[from_reg] > total_size) | |
1999 | total_size = spill_stack_slot_width[from_reg]; | |
2000 | } | |
3bdf5ad1 | 2001 | |
32131a9c | 2002 | /* Make a slot with that size. */ |
cabcf079 ILT |
2003 | x = assign_stack_local (mode, total_size, |
2004 | inherent_size == total_size ? 0 : -1); | |
4f2d3674 | 2005 | stack_slot = x; |
3bdf5ad1 RK |
2006 | |
2007 | /* All pseudos mapped to this slot can alias each other. */ | |
2008 | if (spill_stack_slot[from_reg]) | |
ba4828e0 | 2009 | set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg])); |
3bdf5ad1 | 2010 | else |
ba4828e0 | 2011 | set_mem_alias_set (x, new_alias_set ()); |
3bdf5ad1 | 2012 | |
f76b9db2 ILT |
2013 | if (BYTES_BIG_ENDIAN) |
2014 | { | |
2015 | /* Cancel the big-endian correction done in assign_stack_local. | |
2016 | Get the address of the beginning of the slot. | |
2017 | This is so we can do a big-endian correction unconditionally | |
2018 | below. */ | |
2019 | adjust = GET_MODE_SIZE (mode) - total_size; | |
4f2d3674 | 2020 | if (adjust) |
8ac61af7 RK |
2021 | stack_slot |
2022 | = adjust_address_nv (x, mode_for_size (total_size | |
38a448ca RH |
2023 | * BITS_PER_UNIT, |
2024 | MODE_INT, 1), | |
8ac61af7 | 2025 | adjust); |
f76b9db2 | 2026 | } |
3bdf5ad1 | 2027 | |
4f2d3674 | 2028 | spill_stack_slot[from_reg] = stack_slot; |
32131a9c RK |
2029 | spill_stack_slot_width[from_reg] = total_size; |
2030 | } | |
2031 | ||
32131a9c RK |
2032 | /* On a big endian machine, the "address" of the slot |
2033 | is the address of the low part that fits its inherent mode. */ | |
f76b9db2 | 2034 | if (BYTES_BIG_ENDIAN && inherent_size < total_size) |
32131a9c | 2035 | adjust += (total_size - inherent_size); |
32131a9c RK |
2036 | |
2037 | /* If we have any adjustment to make, or if the stack slot is the | |
2038 | wrong mode, make a new stack slot. */ | |
1285011e RK |
2039 | x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); |
2040 | ||
2041 | /* If we have a decl for the original register, set it for the | |
2042 | memory. If this is a shared MEM, make a copy. */ | |
a560d4d4 JH |
2043 | if (REG_EXPR (regno_reg_rtx[i]) |
2044 | && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd') | |
1285011e | 2045 | { |
a560d4d4 | 2046 | rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i])); |
1285011e | 2047 | |
a20fd5ac JJ |
2048 | /* We can do this only for the DECLs home pseudo, not for |
2049 | any copies of it, since otherwise when the stack slot | |
2050 | is reused, nonoverlapping_memrefs_p might think they | |
2051 | cannot overlap. */ | |
2052 | if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i) | |
2053 | { | |
2054 | if (from_reg != -1 && spill_stack_slot[from_reg] == x) | |
2055 | x = copy_rtx (x); | |
2056 | ||
a560d4d4 | 2057 | set_mem_attrs_from_reg (x, regno_reg_rtx[i]); |
a20fd5ac | 2058 | } |
1285011e | 2059 | } |
32131a9c | 2060 | |
6d2f8887 | 2061 | /* Save the stack slot for later. */ |
32131a9c RK |
2062 | reg_equiv_memory_loc[i] = x; |
2063 | } | |
2064 | } | |
2065 | ||
2066 | /* Mark the slots in regs_ever_live for the hard regs | |
2067 | used by pseudo-reg number REGNO. */ | |
2068 | ||
2069 | void | |
0c20a65f | 2070 | mark_home_live (int regno) |
32131a9c | 2071 | { |
b3694847 | 2072 | int i, lim; |
770ae6cc | 2073 | |
32131a9c RK |
2074 | i = reg_renumber[regno]; |
2075 | if (i < 0) | |
2076 | return; | |
66fd46b6 | 2077 | lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)]; |
32131a9c RK |
2078 | while (i < lim) |
2079 | regs_ever_live[i++] = 1; | |
2080 | } | |
2081 | \f | |
2082 | /* This function handles the tracking of elimination offsets around branches. | |
2083 | ||
2084 | X is a piece of RTL being scanned. | |
2085 | ||
2086 | INSN is the insn that it came from, if any. | |
2087 | ||
40f03658 | 2088 | INITIAL_P is nonzero if we are to set the offset to be the initial |
32131a9c RK |
2089 | offset and zero if we are setting the offset of the label to be the |
2090 | current offset. */ | |
2091 | ||
2092 | static void | |
0c20a65f | 2093 | set_label_offsets (rtx x, rtx insn, int initial_p) |
32131a9c RK |
2094 | { |
2095 | enum rtx_code code = GET_CODE (x); | |
2096 | rtx tem; | |
e51712db | 2097 | unsigned int i; |
32131a9c RK |
2098 | struct elim_table *p; |
2099 | ||
2100 | switch (code) | |
2101 | { | |
2102 | case LABEL_REF: | |
8be386d9 RS |
2103 | if (LABEL_REF_NONLOCAL_P (x)) |
2104 | return; | |
2105 | ||
32131a9c RK |
2106 | x = XEXP (x, 0); |
2107 | ||
0f41302f | 2108 | /* ... fall through ... */ |
32131a9c RK |
2109 | |
2110 | case CODE_LABEL: | |
2111 | /* If we know nothing about this label, set the desired offsets. Note | |
2112 | that this sets the offset at a label to be the offset before a label | |
2113 | if we don't know anything about the label. This is not correct for | |
2114 | the label after a BARRIER, but is the best guess we can make. If | |
2115 | we guessed wrong, we will suppress an elimination that might have | |
2116 | been possible had we been able to guess correctly. */ | |
2117 | ||
4cc0fdd2 | 2118 | if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num]) |
32131a9c RK |
2119 | { |
2120 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
4cc0fdd2 | 2121 | offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] |
32131a9c RK |
2122 | = (initial_p ? reg_eliminate[i].initial_offset |
2123 | : reg_eliminate[i].offset); | |
4cc0fdd2 | 2124 | offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1; |
32131a9c RK |
2125 | } |
2126 | ||
2127 | /* Otherwise, if this is the definition of a label and it is | |
d45cf215 | 2128 | preceded by a BARRIER, set our offsets to the known offset of |
32131a9c RK |
2129 | that label. */ |
2130 | ||
2131 | else if (x == insn | |
2132 | && (tem = prev_nonnote_insn (insn)) != 0 | |
2133 | && GET_CODE (tem) == BARRIER) | |
1f3b1e1a | 2134 | set_offsets_for_label (insn); |
32131a9c RK |
2135 | else |
2136 | /* If neither of the above cases is true, compare each offset | |
2137 | with those previously recorded and suppress any eliminations | |
2138 | where the offsets disagree. */ | |
a8fdc208 | 2139 | |
32131a9c | 2140 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) |
4cc0fdd2 | 2141 | if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] |
32131a9c RK |
2142 | != (initial_p ? reg_eliminate[i].initial_offset |
2143 | : reg_eliminate[i].offset)) | |
2144 | reg_eliminate[i].can_eliminate = 0; | |
2145 | ||
2146 | return; | |
2147 | ||
2148 | case JUMP_INSN: | |
2149 | set_label_offsets (PATTERN (insn), insn, initial_p); | |
2150 | ||
0f41302f | 2151 | /* ... fall through ... */ |
32131a9c RK |
2152 | |
2153 | case INSN: | |
2154 | case CALL_INSN: | |
2155 | /* Any labels mentioned in REG_LABEL notes can be branched to indirectly | |
2156 | and hence must have all eliminations at their initial offsets. */ | |
2157 | for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) | |
2158 | if (REG_NOTE_KIND (tem) == REG_LABEL) | |
2159 | set_label_offsets (XEXP (tem, 0), insn, 1); | |
2160 | return; | |
2161 | ||
0c0ba09c | 2162 | case PARALLEL: |
32131a9c RK |
2163 | case ADDR_VEC: |
2164 | case ADDR_DIFF_VEC: | |
0c0ba09c JJ |
2165 | /* Each of the labels in the parallel or address vector must be |
2166 | at their initial offsets. We want the first field for PARALLEL | |
2167 | and ADDR_VEC and the second field for ADDR_DIFF_VEC. */ | |
32131a9c | 2168 | |
e51712db | 2169 | for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) |
32131a9c RK |
2170 | set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), |
2171 | insn, initial_p); | |
2172 | return; | |
2173 | ||
2174 | case SET: | |
2175 | /* We only care about setting PC. If the source is not RETURN, | |
2176 | IF_THEN_ELSE, or a label, disable any eliminations not at | |
2177 | their initial offsets. Similarly if any arm of the IF_THEN_ELSE | |
2178 | isn't one of those possibilities. For branches to a label, | |
2179 | call ourselves recursively. | |
2180 | ||
2181 | Note that this can disable elimination unnecessarily when we have | |
2182 | a non-local goto since it will look like a non-constant jump to | |
2183 | someplace in the current function. This isn't a significant | |
2184 | problem since such jumps will normally be when all elimination | |
2185 | pairs are back to their initial offsets. */ | |
2186 | ||
2187 | if (SET_DEST (x) != pc_rtx) | |
2188 | return; | |
2189 | ||
2190 | switch (GET_CODE (SET_SRC (x))) | |
2191 | { | |
2192 | case PC: | |
2193 | case RETURN: | |
2194 | return; | |
2195 | ||
2196 | case LABEL_REF: | |
2197 | set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); | |
2198 | return; | |
2199 | ||
2200 | case IF_THEN_ELSE: | |
2201 | tem = XEXP (SET_SRC (x), 1); | |
2202 | if (GET_CODE (tem) == LABEL_REF) | |
2203 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2204 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2205 | break; | |
2206 | ||
2207 | tem = XEXP (SET_SRC (x), 2); | |
2208 | if (GET_CODE (tem) == LABEL_REF) | |
2209 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2210 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2211 | break; | |
2212 | return; | |
e9a25f70 JL |
2213 | |
2214 | default: | |
2215 | break; | |
32131a9c RK |
2216 | } |
2217 | ||
2218 | /* If we reach here, all eliminations must be at their initial | |
2219 | offset because we are doing a jump to a variable address. */ | |
2220 | for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) | |
2221 | if (p->offset != p->initial_offset) | |
2222 | p->can_eliminate = 0; | |
e9a25f70 | 2223 | break; |
05d10675 | 2224 | |
e9a25f70 JL |
2225 | default: |
2226 | break; | |
32131a9c RK |
2227 | } |
2228 | } | |
2229 | \f | |
a8fdc208 | 2230 | /* Scan X and replace any eliminable registers (such as fp) with a |
32131a9c RK |
2231 | replacement (such as sp), plus an offset. |
2232 | ||
2233 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
2234 | much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a | |
2235 | MEM, we are allowed to replace a sum of a register and the constant zero | |
2236 | with the register, which we cannot do outside a MEM. In addition, we need | |
2237 | to record the fact that a register is referenced outside a MEM. | |
2238 | ||
ff32812a | 2239 | If INSN is an insn, it is the insn containing X. If we replace a REG |
40f03658 | 2240 | in a SET_DEST with an equivalent MEM and INSN is nonzero, write a |
32131a9c | 2241 | CLOBBER of the pseudo after INSN so find_equiv_regs will know that |
38e01259 | 2242 | the REG is being modified. |
32131a9c | 2243 | |
ff32812a RS |
2244 | Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). |
2245 | That's used when we eliminate in expressions stored in notes. | |
2246 | This means, do not set ref_outside_mem even if the reference | |
2247 | is outside of MEMs. | |
2248 | ||
32131a9c RK |
2249 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had |
2250 | replacements done assuming all offsets are at their initial values. If | |
2251 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | |
2252 | encounter, return the actual location so that find_reloads will do | |
2253 | the proper thing. */ | |
2254 | ||
2255 | rtx | |
0c20a65f | 2256 | eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn) |
32131a9c RK |
2257 | { |
2258 | enum rtx_code code = GET_CODE (x); | |
2259 | struct elim_table *ep; | |
2260 | int regno; | |
2261 | rtx new; | |
2262 | int i, j; | |
6f7d635c | 2263 | const char *fmt; |
32131a9c RK |
2264 | int copied = 0; |
2265 | ||
d6633f01 NS |
2266 | if (! current_function_decl) |
2267 | return x; | |
9969bb2c | 2268 | |
32131a9c RK |
2269 | switch (code) |
2270 | { | |
2271 | case CONST_INT: | |
2272 | case CONST_DOUBLE: | |
69ef87e2 | 2273 | case CONST_VECTOR: |
32131a9c RK |
2274 | case CONST: |
2275 | case SYMBOL_REF: | |
2276 | case CODE_LABEL: | |
2277 | case PC: | |
2278 | case CC0: | |
2279 | case ASM_INPUT: | |
2280 | case ADDR_VEC: | |
2281 | case ADDR_DIFF_VEC: | |
2282 | case RETURN: | |
2283 | return x; | |
2284 | ||
e9a25f70 JL |
2285 | case ADDRESSOF: |
2286 | /* This is only for the benefit of the debugging backends, which call | |
2287 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2288 | removed after CSE. */ | |
1914f5da | 2289 | new = eliminate_regs (XEXP (x, 0), 0, insn); |
e9a25f70 JL |
2290 | if (GET_CODE (new) == MEM) |
2291 | return XEXP (new, 0); | |
2292 | return x; | |
2293 | ||
32131a9c RK |
2294 | case REG: |
2295 | regno = REGNO (x); | |
2296 | ||
2297 | /* First handle the case where we encounter a bare register that | |
2298 | is eliminable. Replace it with a PLUS. */ | |
2299 | if (regno < FIRST_PSEUDO_REGISTER) | |
2300 | { | |
2301 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2302 | ep++) | |
2303 | if (ep->from_rtx == x && ep->can_eliminate) | |
dfac187e | 2304 | return plus_constant (ep->to_rtx, ep->previous_offset); |
32131a9c RK |
2305 | |
2306 | } | |
cd7c9015 RK |
2307 | else if (reg_renumber && reg_renumber[regno] < 0 |
2308 | && reg_equiv_constant && reg_equiv_constant[regno] | |
2b49ee39 R |
2309 | && ! CONSTANT_P (reg_equiv_constant[regno])) |
2310 | return eliminate_regs (copy_rtx (reg_equiv_constant[regno]), | |
2311 | mem_mode, insn); | |
32131a9c RK |
2312 | return x; |
2313 | ||
c5c76735 JL |
2314 | /* You might think handling MINUS in a manner similar to PLUS is a |
2315 | good idea. It is not. It has been tried multiple times and every | |
2316 | time the change has had to have been reverted. | |
2317 | ||
2318 | Other parts of reload know a PLUS is special (gen_reload for example) | |
2319 | and require special code to handle code a reloaded PLUS operand. | |
2320 | ||
2321 | Also consider backends where the flags register is clobbered by a | |
a457ee07 | 2322 | MINUS, but we can emit a PLUS that does not clobber flags (IA-32, |
c5c76735 JL |
2323 | lea instruction comes to mind). If we try to reload a MINUS, we |
2324 | may kill the flags register that was holding a useful value. | |
2325 | ||
2326 | So, please before trying to handle MINUS, consider reload as a | |
2327 | whole instead of this little section as well as the backend issues. */ | |
32131a9c RK |
2328 | case PLUS: |
2329 | /* If this is the sum of an eliminable register and a constant, rework | |
6d2f8887 | 2330 | the sum. */ |
32131a9c RK |
2331 | if (GET_CODE (XEXP (x, 0)) == REG |
2332 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2333 | && CONSTANT_P (XEXP (x, 1))) | |
2334 | { | |
2335 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2336 | ep++) | |
2337 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2338 | { | |
32131a9c RK |
2339 | /* The only time we want to replace a PLUS with a REG (this |
2340 | occurs when the constant operand of the PLUS is the negative | |
2341 | of the offset) is when we are inside a MEM. We won't want | |
2342 | to do so at other times because that would change the | |
2343 | structure of the insn in a way that reload can't handle. | |
2344 | We special-case the commonest situation in | |
2345 | eliminate_regs_in_insn, so just replace a PLUS with a | |
2346 | PLUS here, unless inside a MEM. */ | |
a23b64d5 | 2347 | if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT |
32131a9c RK |
2348 | && INTVAL (XEXP (x, 1)) == - ep->previous_offset) |
2349 | return ep->to_rtx; | |
2350 | else | |
38a448ca RH |
2351 | return gen_rtx_PLUS (Pmode, ep->to_rtx, |
2352 | plus_constant (XEXP (x, 1), | |
2353 | ep->previous_offset)); | |
32131a9c RK |
2354 | } |
2355 | ||
2356 | /* If the register is not eliminable, we are done since the other | |
2357 | operand is a constant. */ | |
2358 | return x; | |
2359 | } | |
2360 | ||
2361 | /* If this is part of an address, we want to bring any constant to the | |
2362 | outermost PLUS. We will do this by doing register replacement in | |
2363 | our operands and seeing if a constant shows up in one of them. | |
2364 | ||
dfac187e BS |
2365 | Note that there is no risk of modifying the structure of the insn, |
2366 | since we only get called for its operands, thus we are either | |
2367 | modifying the address inside a MEM, or something like an address | |
2368 | operand of a load-address insn. */ | |
32131a9c RK |
2369 | |
2370 | { | |
1914f5da RH |
2371 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
2372 | rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn); | |
32131a9c | 2373 | |
cd7c9015 | 2374 | if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))) |
32131a9c RK |
2375 | { |
2376 | /* If one side is a PLUS and the other side is a pseudo that | |
a8fdc208 | 2377 | didn't get a hard register but has a reg_equiv_constant, |
32131a9c RK |
2378 | we must replace the constant here since it may no longer |
2379 | be in the position of any operand. */ | |
2380 | if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG | |
2381 | && REGNO (new1) >= FIRST_PSEUDO_REGISTER | |
2382 | && reg_renumber[REGNO (new1)] < 0 | |
2383 | && reg_equiv_constant != 0 | |
2384 | && reg_equiv_constant[REGNO (new1)] != 0) | |
2385 | new1 = reg_equiv_constant[REGNO (new1)]; | |
2386 | else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG | |
2387 | && REGNO (new0) >= FIRST_PSEUDO_REGISTER | |
2388 | && reg_renumber[REGNO (new0)] < 0 | |
2389 | && reg_equiv_constant[REGNO (new0)] != 0) | |
2390 | new0 = reg_equiv_constant[REGNO (new0)]; | |
2391 | ||
2392 | new = form_sum (new0, new1); | |
2393 | ||
2394 | /* As above, if we are not inside a MEM we do not want to | |
2395 | turn a PLUS into something else. We might try to do so here | |
2396 | for an addition of 0 if we aren't optimizing. */ | |
2397 | if (! mem_mode && GET_CODE (new) != PLUS) | |
38a448ca | 2398 | return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx); |
32131a9c RK |
2399 | else |
2400 | return new; | |
2401 | } | |
2402 | } | |
2403 | return x; | |
2404 | ||
981c7390 | 2405 | case MULT: |
05d10675 | 2406 | /* If this is the product of an eliminable register and a |
981c7390 RK |
2407 | constant, apply the distribute law and move the constant out |
2408 | so that we have (plus (mult ..) ..). This is needed in order | |
9faa82d8 | 2409 | to keep load-address insns valid. This case is pathological. |
981c7390 RK |
2410 | We ignore the possibility of overflow here. */ |
2411 | if (GET_CODE (XEXP (x, 0)) == REG | |
2412 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2413 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2414 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2415 | ep++) | |
2416 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2417 | { | |
2418 | if (! mem_mode | |
2419 | /* Refs inside notes don't count for this purpose. */ | |
2420 | && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST | |
2421 | || GET_CODE (insn) == INSN_LIST))) | |
2422 | ep->ref_outside_mem = 1; | |
2423 | ||
2424 | return | |
38a448ca | 2425 | plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), |
981c7390 RK |
2426 | ep->previous_offset * INTVAL (XEXP (x, 1))); |
2427 | } | |
32131a9c | 2428 | |
0f41302f | 2429 | /* ... fall through ... */ |
32131a9c | 2430 | |
32131a9c RK |
2431 | case CALL: |
2432 | case COMPARE: | |
c5c76735 | 2433 | /* See comments before PLUS about handling MINUS. */ |
930aeef3 | 2434 | case MINUS: |
32131a9c RK |
2435 | case DIV: case UDIV: |
2436 | case MOD: case UMOD: | |
2437 | case AND: case IOR: case XOR: | |
45620ed4 RK |
2438 | case ROTATERT: case ROTATE: |
2439 | case ASHIFTRT: case LSHIFTRT: case ASHIFT: | |
32131a9c RK |
2440 | case NE: case EQ: |
2441 | case GE: case GT: case GEU: case GTU: | |
2442 | case LE: case LT: case LEU: case LTU: | |
2443 | { | |
1914f5da | 2444 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
fb3821f7 | 2445 | rtx new1 |
1914f5da | 2446 | = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0; |
32131a9c RK |
2447 | |
2448 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
38a448ca | 2449 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); |
32131a9c RK |
2450 | } |
2451 | return x; | |
2452 | ||
981c7390 RK |
2453 | case EXPR_LIST: |
2454 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | |
2455 | if (XEXP (x, 0)) | |
2456 | { | |
1914f5da | 2457 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
981c7390 | 2458 | if (new != XEXP (x, 0)) |
13bb79d4 R |
2459 | { |
2460 | /* If this is a REG_DEAD note, it is not valid anymore. | |
2461 | Using the eliminated version could result in creating a | |
2462 | REG_DEAD note for the stack or frame pointer. */ | |
2463 | if (GET_MODE (x) == REG_DEAD) | |
2464 | return (XEXP (x, 1) | |
2465 | ? eliminate_regs (XEXP (x, 1), mem_mode, insn) | |
2466 | : NULL_RTX); | |
2467 | ||
2468 | x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1)); | |
2469 | } | |
981c7390 RK |
2470 | } |
2471 | ||
0f41302f | 2472 | /* ... fall through ... */ |
981c7390 RK |
2473 | |
2474 | case INSN_LIST: | |
2475 | /* Now do eliminations in the rest of the chain. If this was | |
2476 | an EXPR_LIST, this might result in allocating more memory than is | |
2477 | strictly needed, but it simplifies the code. */ | |
2478 | if (XEXP (x, 1)) | |
2479 | { | |
1914f5da | 2480 | new = eliminate_regs (XEXP (x, 1), mem_mode, insn); |
981c7390 | 2481 | if (new != XEXP (x, 1)) |
cd7c9015 RK |
2482 | return |
2483 | gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new); | |
981c7390 RK |
2484 | } |
2485 | return x; | |
2486 | ||
32131a9c RK |
2487 | case PRE_INC: |
2488 | case POST_INC: | |
2489 | case PRE_DEC: | |
2490 | case POST_DEC: | |
32131a9c RK |
2491 | case STRICT_LOW_PART: |
2492 | case NEG: case NOT: | |
2493 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2494 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2495 | case FLOAT: case FIX: | |
2496 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2497 | case ABS: | |
2498 | case SQRT: | |
2499 | case FFS: | |
2928cd7a RH |
2500 | case CLZ: |
2501 | case CTZ: | |
2502 | case POPCOUNT: | |
2503 | case PARITY: | |
1914f5da | 2504 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
32131a9c | 2505 | if (new != XEXP (x, 0)) |
38a448ca | 2506 | return gen_rtx_fmt_e (code, GET_MODE (x), new); |
32131a9c RK |
2507 | return x; |
2508 | ||
2509 | case SUBREG: | |
ddef6bc7 | 2510 | /* Similar to above processing, but preserve SUBREG_BYTE. |
32131a9c RK |
2511 | Convert (subreg (mem)) to (mem) if not paradoxical. |
2512 | Also, if we have a non-paradoxical (subreg (pseudo)) and the | |
2513 | pseudo didn't get a hard reg, we must replace this with the | |
bd235d86 | 2514 | eliminated version of the memory location because push_reload |
32131a9c RK |
2515 | may do the replacement in certain circumstances. */ |
2516 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2517 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2518 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2519 | && reg_equiv_memory_loc != 0 | |
2520 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2521 | { | |
cb2afeb3 | 2522 | new = SUBREG_REG (x); |
32131a9c RK |
2523 | } |
2524 | else | |
1914f5da | 2525 | new = eliminate_regs (SUBREG_REG (x), mem_mode, insn); |
32131a9c | 2526 | |
ddef6bc7 | 2527 | if (new != SUBREG_REG (x)) |
32131a9c | 2528 | { |
29ae5012 RK |
2529 | int x_size = GET_MODE_SIZE (GET_MODE (x)); |
2530 | int new_size = GET_MODE_SIZE (GET_MODE (new)); | |
2531 | ||
1914f5da | 2532 | if (GET_CODE (new) == MEM |
6d49a073 | 2533 | && ((x_size < new_size |
1914f5da | 2534 | #ifdef WORD_REGISTER_OPERATIONS |
6d49a073 JW |
2535 | /* On these machines, combine can create rtl of the form |
2536 | (set (subreg:m1 (reg:m2 R) 0) ...) | |
05d10675 | 2537 | where m1 < m2, and expects something interesting to |
6d49a073 JW |
2538 | happen to the entire word. Moreover, it will use the |
2539 | (reg:m2 R) later, expecting all bits to be preserved. | |
05d10675 | 2540 | So if the number of words is the same, preserve the |
bd235d86 | 2541 | subreg so that push_reload can see it. */ |
5d9669fd RK |
2542 | && ! ((x_size - 1) / UNITS_PER_WORD |
2543 | == (new_size -1 ) / UNITS_PER_WORD) | |
1914f5da | 2544 | #endif |
6d49a073 | 2545 | ) |
5d9669fd | 2546 | || x_size == new_size) |
1914f5da | 2547 | ) |
a2ff290c | 2548 | return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x)); |
32131a9c | 2549 | else |
ddef6bc7 | 2550 | return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x)); |
32131a9c RK |
2551 | } |
2552 | ||
2553 | return x; | |
2554 | ||
32131a9c | 2555 | case MEM: |
e9a25f70 JL |
2556 | /* This is only for the benefit of the debugging backends, which call |
2557 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2558 | removed after CSE. */ | |
2559 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
1914f5da | 2560 | return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn); |
e9a25f70 | 2561 | |
32131a9c RK |
2562 | /* Our only special processing is to pass the mode of the MEM to our |
2563 | recursive call and copy the flags. While we are here, handle this | |
2564 | case more efficiently. */ | |
f1ec5147 RK |
2565 | return |
2566 | replace_equiv_address_nv (x, | |
2567 | eliminate_regs (XEXP (x, 0), | |
2568 | GET_MODE (x), insn)); | |
05d10675 | 2569 | |
dfac187e | 2570 | case USE: |
055c7759 JDA |
2571 | /* Handle insn_list USE that a call to a pure function may generate. */ |
2572 | new = eliminate_regs (XEXP (x, 0), 0, insn); | |
2573 | if (new != XEXP (x, 0)) | |
2574 | return gen_rtx_USE (GET_MODE (x), new); | |
2575 | return x; | |
2576 | ||
dfac187e BS |
2577 | case CLOBBER: |
2578 | case ASM_OPERANDS: | |
2579 | case SET: | |
2580 | abort (); | |
2581 | ||
e9a25f70 JL |
2582 | default: |
2583 | break; | |
32131a9c RK |
2584 | } |
2585 | ||
2586 | /* Process each of our operands recursively. If any have changed, make a | |
2587 | copy of the rtx. */ | |
2588 | fmt = GET_RTX_FORMAT (code); | |
2589 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2590 | { | |
2591 | if (*fmt == 'e') | |
2592 | { | |
1914f5da | 2593 | new = eliminate_regs (XEXP (x, i), mem_mode, insn); |
32131a9c RK |
2594 | if (new != XEXP (x, i) && ! copied) |
2595 | { | |
2596 | rtx new_x = rtx_alloc (code); | |
e1de1560 | 2597 | memcpy (new_x, x, RTX_SIZE (code)); |
32131a9c RK |
2598 | x = new_x; |
2599 | copied = 1; | |
2600 | } | |
2601 | XEXP (x, i) = new; | |
2602 | } | |
2603 | else if (*fmt == 'E') | |
2604 | { | |
2605 | int copied_vec = 0; | |
2606 | for (j = 0; j < XVECLEN (x, i); j++) | |
2607 | { | |
1914f5da | 2608 | new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); |
32131a9c RK |
2609 | if (new != XVECEXP (x, i, j) && ! copied_vec) |
2610 | { | |
8f985ec4 ZW |
2611 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), |
2612 | XVEC (x, i)->elem); | |
32131a9c RK |
2613 | if (! copied) |
2614 | { | |
2615 | rtx new_x = rtx_alloc (code); | |
e1de1560 | 2616 | memcpy (new_x, x, RTX_SIZE (code)); |
32131a9c RK |
2617 | x = new_x; |
2618 | copied = 1; | |
2619 | } | |
2620 | XVEC (x, i) = new_v; | |
2621 | copied_vec = 1; | |
2622 | } | |
2623 | XVECEXP (x, i, j) = new; | |
2624 | } | |
2625 | } | |
2626 | } | |
2627 | ||
2628 | return x; | |
2629 | } | |
dfac187e BS |
2630 | |
2631 | /* Scan rtx X for modifications of elimination target registers. Update | |
2632 | the table of eliminables to reflect the changed state. MEM_MODE is | |
2633 | the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ | |
2634 | ||
2635 | static void | |
0c20a65f | 2636 | elimination_effects (rtx x, enum machine_mode mem_mode) |
dfac187e BS |
2637 | { |
2638 | enum rtx_code code = GET_CODE (x); | |
2639 | struct elim_table *ep; | |
2640 | int regno; | |
2641 | int i, j; | |
2642 | const char *fmt; | |
2643 | ||
2644 | switch (code) | |
2645 | { | |
2646 | case CONST_INT: | |
2647 | case CONST_DOUBLE: | |
69ef87e2 | 2648 | case CONST_VECTOR: |
dfac187e BS |
2649 | case CONST: |
2650 | case SYMBOL_REF: | |
2651 | case CODE_LABEL: | |
2652 | case PC: | |
2653 | case CC0: | |
2654 | case ASM_INPUT: | |
2655 | case ADDR_VEC: | |
2656 | case ADDR_DIFF_VEC: | |
2657 | case RETURN: | |
2658 | return; | |
2659 | ||
2660 | case ADDRESSOF: | |
2661 | abort (); | |
2662 | ||
2663 | case REG: | |
2664 | regno = REGNO (x); | |
2665 | ||
2666 | /* First handle the case where we encounter a bare register that | |
2667 | is eliminable. Replace it with a PLUS. */ | |
2668 | if (regno < FIRST_PSEUDO_REGISTER) | |
2669 | { | |
2670 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2671 | ep++) | |
2672 | if (ep->from_rtx == x && ep->can_eliminate) | |
2673 | { | |
2674 | if (! mem_mode) | |
2675 | ep->ref_outside_mem = 1; | |
2676 | return; | |
2677 | } | |
2678 | ||
2679 | } | |
2680 | else if (reg_renumber[regno] < 0 && reg_equiv_constant | |
2681 | && reg_equiv_constant[regno] | |
92a21141 | 2682 | && ! function_invariant_p (reg_equiv_constant[regno])) |
dfac187e BS |
2683 | elimination_effects (reg_equiv_constant[regno], mem_mode); |
2684 | return; | |
2685 | ||
2686 | case PRE_INC: | |
2687 | case POST_INC: | |
2688 | case PRE_DEC: | |
2689 | case POST_DEC: | |
4b983fdc RH |
2690 | case POST_MODIFY: |
2691 | case PRE_MODIFY: | |
dfac187e BS |
2692 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
2693 | if (ep->to_rtx == XEXP (x, 0)) | |
2694 | { | |
2695 | int size = GET_MODE_SIZE (mem_mode); | |
2696 | ||
2697 | /* If more bytes than MEM_MODE are pushed, account for them. */ | |
2698 | #ifdef PUSH_ROUNDING | |
2699 | if (ep->to_rtx == stack_pointer_rtx) | |
2700 | size = PUSH_ROUNDING (size); | |
2701 | #endif | |
2702 | if (code == PRE_DEC || code == POST_DEC) | |
2703 | ep->offset += size; | |
4b983fdc | 2704 | else if (code == PRE_INC || code == POST_INC) |
dfac187e | 2705 | ep->offset -= size; |
4b983fdc RH |
2706 | else if ((code == PRE_MODIFY || code == POST_MODIFY) |
2707 | && GET_CODE (XEXP (x, 1)) == PLUS | |
2708 | && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) | |
2709 | && CONSTANT_P (XEXP (XEXP (x, 1), 1))) | |
2710 | ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1)); | |
dfac187e BS |
2711 | } |
2712 | ||
4b983fdc RH |
2713 | /* These two aren't unary operators. */ |
2714 | if (code == POST_MODIFY || code == PRE_MODIFY) | |
2715 | break; | |
2716 | ||
dfac187e BS |
2717 | /* Fall through to generic unary operation case. */ |
2718 | case STRICT_LOW_PART: | |
2719 | case NEG: case NOT: | |
2720 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2721 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2722 | case FLOAT: case FIX: | |
2723 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2724 | case ABS: | |
2725 | case SQRT: | |
2726 | case FFS: | |
2928cd7a RH |
2727 | case CLZ: |
2728 | case CTZ: | |
2729 | case POPCOUNT: | |
2730 | case PARITY: | |
dfac187e BS |
2731 | elimination_effects (XEXP (x, 0), mem_mode); |
2732 | return; | |
2733 | ||
2734 | case SUBREG: | |
2735 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2736 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2737 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2738 | && reg_equiv_memory_loc != 0 | |
2739 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2740 | return; | |
2741 | ||
2742 | elimination_effects (SUBREG_REG (x), mem_mode); | |
2743 | return; | |
2744 | ||
2745 | case USE: | |
2746 | /* If using a register that is the source of an eliminate we still | |
2747 | think can be performed, note it cannot be performed since we don't | |
2748 | know how this register is used. */ | |
2749 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2750 | if (ep->from_rtx == XEXP (x, 0)) | |
2751 | ep->can_eliminate = 0; | |
2752 | ||
2753 | elimination_effects (XEXP (x, 0), mem_mode); | |
2754 | return; | |
2755 | ||
2756 | case CLOBBER: | |
2757 | /* If clobbering a register that is the replacement register for an | |
2758 | elimination we still think can be performed, note that it cannot | |
2759 | be performed. Otherwise, we need not be concerned about it. */ | |
2760 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2761 | if (ep->to_rtx == XEXP (x, 0)) | |
2762 | ep->can_eliminate = 0; | |
2763 | ||
2764 | elimination_effects (XEXP (x, 0), mem_mode); | |
2765 | return; | |
2766 | ||
2767 | case SET: | |
2768 | /* Check for setting a register that we know about. */ | |
2769 | if (GET_CODE (SET_DEST (x)) == REG) | |
2770 | { | |
2771 | /* See if this is setting the replacement register for an | |
2772 | elimination. | |
2773 | ||
2774 | If DEST is the hard frame pointer, we do nothing because we | |
2775 | assume that all assignments to the frame pointer are for | |
2776 | non-local gotos and are being done at a time when they are valid | |
2777 | and do not disturb anything else. Some machines want to | |
2778 | eliminate a fake argument pointer (or even a fake frame pointer) | |
2779 | with either the real frame or the stack pointer. Assignments to | |
2780 | the hard frame pointer must not prevent this elimination. */ | |
2781 | ||
2782 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2783 | ep++) | |
2784 | if (ep->to_rtx == SET_DEST (x) | |
2785 | && SET_DEST (x) != hard_frame_pointer_rtx) | |
2786 | { | |
2787 | /* If it is being incremented, adjust the offset. Otherwise, | |
2788 | this elimination can't be done. */ | |
2789 | rtx src = SET_SRC (x); | |
2790 | ||
2791 | if (GET_CODE (src) == PLUS | |
2792 | && XEXP (src, 0) == SET_DEST (x) | |
2793 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2794 | ep->offset -= INTVAL (XEXP (src, 1)); | |
2795 | else | |
2796 | ep->can_eliminate = 0; | |
2797 | } | |
2798 | } | |
2799 | ||
2800 | elimination_effects (SET_DEST (x), 0); | |
2801 | elimination_effects (SET_SRC (x), 0); | |
2802 | return; | |
2803 | ||
2804 | case MEM: | |
2805 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
2806 | abort (); | |
2807 | ||
2808 | /* Our only special processing is to pass the mode of the MEM to our | |
2809 | recursive call. */ | |
2810 | elimination_effects (XEXP (x, 0), GET_MODE (x)); | |
2811 | return; | |
2812 | ||
2813 | default: | |
2814 | break; | |
2815 | } | |
2816 | ||
2817 | fmt = GET_RTX_FORMAT (code); | |
2818 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2819 | { | |
2820 | if (*fmt == 'e') | |
2821 | elimination_effects (XEXP (x, i), mem_mode); | |
2822 | else if (*fmt == 'E') | |
2823 | for (j = 0; j < XVECLEN (x, i); j++) | |
2824 | elimination_effects (XVECEXP (x, i, j), mem_mode); | |
2825 | } | |
2826 | } | |
2827 | ||
2828 | /* Descend through rtx X and verify that no references to eliminable registers | |
2829 | remain. If any do remain, mark the involved register as not | |
2830 | eliminable. */ | |
1d813780 | 2831 | |
dfac187e | 2832 | static void |
0c20a65f | 2833 | check_eliminable_occurrences (rtx x) |
dfac187e BS |
2834 | { |
2835 | const char *fmt; | |
2836 | int i; | |
2837 | enum rtx_code code; | |
2838 | ||
2839 | if (x == 0) | |
2840 | return; | |
1d7254c5 | 2841 | |
dfac187e BS |
2842 | code = GET_CODE (x); |
2843 | ||
2844 | if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
2845 | { | |
2846 | struct elim_table *ep; | |
2847 | ||
2848 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
761fa0f7 | 2849 | if (ep->from_rtx == x) |
dfac187e BS |
2850 | ep->can_eliminate = 0; |
2851 | return; | |
2852 | } | |
1d7254c5 | 2853 | |
dfac187e BS |
2854 | fmt = GET_RTX_FORMAT (code); |
2855 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2856 | { | |
2857 | if (*fmt == 'e') | |
2858 | check_eliminable_occurrences (XEXP (x, i)); | |
2859 | else if (*fmt == 'E') | |
2860 | { | |
2861 | int j; | |
2862 | for (j = 0; j < XVECLEN (x, i); j++) | |
2863 | check_eliminable_occurrences (XVECEXP (x, i, j)); | |
2864 | } | |
2865 | } | |
2866 | } | |
32131a9c RK |
2867 | \f |
2868 | /* Scan INSN and eliminate all eliminable registers in it. | |
2869 | ||
2870 | If REPLACE is nonzero, do the replacement destructively. Also | |
2871 | delete the insn as dead it if it is setting an eliminable register. | |
2872 | ||
2873 | If REPLACE is zero, do all our allocations in reload_obstack. | |
2874 | ||
2875 | If no eliminations were done and this insn doesn't require any elimination | |
2876 | processing (these are not identical conditions: it might be updating sp, | |
2877 | but not referencing fp; this needs to be seen during reload_as_needed so | |
2878 | that the offset between fp and sp can be taken into consideration), zero | |
2879 | is returned. Otherwise, 1 is returned. */ | |
2880 | ||
2881 | static int | |
0c20a65f | 2882 | eliminate_regs_in_insn (rtx insn, int replace) |
32131a9c | 2883 | { |
dfac187e | 2884 | int icode = recog_memoized (insn); |
32131a9c | 2885 | rtx old_body = PATTERN (insn); |
dfac187e | 2886 | int insn_is_asm = asm_noperands (old_body) >= 0; |
774672d2 | 2887 | rtx old_set = single_set (insn); |
32131a9c RK |
2888 | rtx new_body; |
2889 | int val = 0; | |
4977bab6 | 2890 | int i; |
dfac187e BS |
2891 | rtx substed_operand[MAX_RECOG_OPERANDS]; |
2892 | rtx orig_operand[MAX_RECOG_OPERANDS]; | |
32131a9c | 2893 | struct elim_table *ep; |
ace3ffcd | 2894 | rtx plus_src; |
32131a9c | 2895 | |
dfac187e BS |
2896 | if (! insn_is_asm && icode < 0) |
2897 | { | |
2898 | if (GET_CODE (PATTERN (insn)) == USE | |
2899 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
2900 | || GET_CODE (PATTERN (insn)) == ADDR_VEC | |
2901 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
2902 | || GET_CODE (PATTERN (insn)) == ASM_INPUT) | |
2903 | return 0; | |
2904 | abort (); | |
2905 | } | |
2906 | ||
774672d2 RK |
2907 | if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG |
2908 | && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
2909 | { |
2910 | /* Check for setting an eliminable register. */ | |
2911 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
774672d2 | 2912 | if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) |
32131a9c | 2913 | { |
dd1eab0a RK |
2914 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
2915 | /* If this is setting the frame pointer register to the | |
2916 | hardware frame pointer register and this is an elimination | |
2917 | that will be done (tested above), this insn is really | |
2918 | adjusting the frame pointer downward to compensate for | |
2919 | the adjustment done before a nonlocal goto. */ | |
2920 | if (ep->from == FRAME_POINTER_REGNUM | |
2921 | && ep->to == HARD_FRAME_POINTER_REGNUM) | |
2922 | { | |
75eefe3f UW |
2923 | rtx base = SET_SRC (old_set); |
2924 | rtx base_insn = insn; | |
b19ee4bd | 2925 | HOST_WIDE_INT offset = 0; |
75eefe3f UW |
2926 | |
2927 | while (base != ep->to_rtx) | |
8026ebba | 2928 | { |
75eefe3f UW |
2929 | rtx prev_insn, prev_set; |
2930 | ||
2931 | if (GET_CODE (base) == PLUS | |
2932 | && GET_CODE (XEXP (base, 1)) == CONST_INT) | |
2933 | { | |
2934 | offset += INTVAL (XEXP (base, 1)); | |
2935 | base = XEXP (base, 0); | |
2936 | } | |
2937 | else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0 | |
2938 | && (prev_set = single_set (prev_insn)) != 0 | |
2939 | && rtx_equal_p (SET_DEST (prev_set), base)) | |
2940 | { | |
2941 | base = SET_SRC (prev_set); | |
2942 | base_insn = prev_insn; | |
2943 | } | |
2944 | else | |
2945 | break; | |
8026ebba | 2946 | } |
dd1eab0a | 2947 | |
75eefe3f | 2948 | if (base == ep->to_rtx) |
dd1eab0a | 2949 | { |
c77fbfbe GK |
2950 | rtx src |
2951 | = plus_constant (ep->to_rtx, offset - ep->offset); | |
2952 | ||
2953 | new_body = old_body; | |
2954 | if (! replace) | |
2955 | { | |
2956 | new_body = copy_insn (old_body); | |
2957 | if (REG_NOTES (insn)) | |
2958 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
2959 | } | |
2960 | PATTERN (insn) = new_body; | |
2961 | old_set = single_set (insn); | |
2962 | ||
2963 | /* First see if this insn remains valid when we | |
2964 | make the change. If not, keep the INSN_CODE | |
2965 | the same and let reload fit it up. */ | |
2966 | validate_change (insn, &SET_SRC (old_set), src, 1); | |
2967 | validate_change (insn, &SET_DEST (old_set), | |
2968 | ep->to_rtx, 1); | |
2969 | if (! apply_change_group ()) | |
dd1eab0a | 2970 | { |
c77fbfbe GK |
2971 | SET_SRC (old_set) = src; |
2972 | SET_DEST (old_set) = ep->to_rtx; | |
dd1eab0a RK |
2973 | } |
2974 | ||
2975 | val = 1; | |
2976 | goto done; | |
2977 | } | |
2978 | } | |
2979 | #endif | |
2980 | ||
32131a9c RK |
2981 | /* In this case this insn isn't serving a useful purpose. We |
2982 | will delete it in reload_as_needed once we know that this | |
2983 | elimination is, in fact, being done. | |
2984 | ||
abc95ed3 | 2985 | If REPLACE isn't set, we can't delete this insn, but needn't |
32131a9c RK |
2986 | process it since it won't be used unless something changes. */ |
2987 | if (replace) | |
8a34409d | 2988 | { |
1d7254c5 | 2989 | delete_dead_insn (insn); |
8a34409d RH |
2990 | return 1; |
2991 | } | |
32131a9c RK |
2992 | val = 1; |
2993 | goto done; | |
2994 | } | |
aa5524a9 | 2995 | } |
32131a9c | 2996 | |
aa5524a9 | 2997 | /* We allow one special case which happens to work on all machines we |
ace3ffcd KH |
2998 | currently support: a single set with the source or a REG_EQUAL |
2999 | note being a PLUS of an eliminable register and a constant. */ | |
3000 | plus_src = 0; | |
3001 | if (old_set && GET_CODE (SET_DEST (old_set)) == REG) | |
aa5524a9 | 3002 | { |
ace3ffcd KH |
3003 | /* First see if the source is of the form (plus (reg) CST). */ |
3004 | if (GET_CODE (SET_SRC (old_set)) == PLUS | |
3005 | && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG | |
3006 | && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT | |
3007 | && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER) | |
3008 | plus_src = SET_SRC (old_set); | |
3009 | else if (GET_CODE (SET_SRC (old_set)) == REG) | |
3010 | { | |
3011 | /* Otherwise, see if we have a REG_EQUAL note of the form | |
3012 | (plus (reg) CST). */ | |
3013 | rtx links; | |
3014 | for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) | |
3015 | { | |
3016 | if (REG_NOTE_KIND (links) == REG_EQUAL | |
3017 | && GET_CODE (XEXP (links, 0)) == PLUS | |
3018 | && GET_CODE (XEXP (XEXP (links, 0), 0)) == REG | |
3019 | && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT | |
3020 | && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER) | |
3021 | { | |
3022 | plus_src = XEXP (links, 0); | |
3023 | break; | |
3024 | } | |
3025 | } | |
3026 | } | |
3027 | } | |
3028 | if (plus_src) | |
3029 | { | |
3030 | rtx reg = XEXP (plus_src, 0); | |
3031 | HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1)); | |
32131a9c | 3032 | |
aa5524a9 BS |
3033 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3034 | if (ep->from_rtx == reg && ep->can_eliminate) | |
3035 | { | |
3036 | offset += ep->offset; | |
32131a9c | 3037 | |
aa5524a9 BS |
3038 | if (offset == 0) |
3039 | { | |
f34c06e5 R |
3040 | int num_clobbers; |
3041 | /* We assume here that if we need a PARALLEL with | |
3042 | CLOBBERs for this assignment, we can do with the | |
3043 | MATCH_SCRATCHes that add_clobbers allocates. | |
3044 | There's not much we can do if that doesn't work. */ | |
aa5524a9 BS |
3045 | PATTERN (insn) = gen_rtx_SET (VOIDmode, |
3046 | SET_DEST (old_set), | |
3047 | ep->to_rtx); | |
f34c06e5 R |
3048 | num_clobbers = 0; |
3049 | INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers); | |
3050 | if (num_clobbers) | |
3051 | { | |
3052 | rtvec vec = rtvec_alloc (num_clobbers + 1); | |
3053 | ||
3054 | vec->elem[0] = PATTERN (insn); | |
3055 | PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); | |
3056 | add_clobbers (PATTERN (insn), INSN_CODE (insn)); | |
3057 | } | |
aa5524a9 BS |
3058 | if (INSN_CODE (insn) < 0) |
3059 | abort (); | |
3060 | } | |
ace3ffcd KH |
3061 | /* If we have a nonzero offset, and the source is already |
3062 | a simple REG, the following transformation would | |
3063 | increase the cost of the insn by replacing a simple REG | |
3064 | with (plus (reg sp) CST). So try only when plus_src | |
3065 | comes from old_set proper, not REG_NOTES. */ | |
3066 | else if (SET_SRC (old_set) == plus_src) | |
aa5524a9 BS |
3067 | { |
3068 | new_body = old_body; | |
3069 | if (! replace) | |
3070 | { | |
3071 | new_body = copy_insn (old_body); | |
3072 | if (REG_NOTES (insn)) | |
3073 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3074 | } | |
3075 | PATTERN (insn) = new_body; | |
3076 | old_set = single_set (insn); | |
922d9d40 | 3077 | |
aa5524a9 BS |
3078 | XEXP (SET_SRC (old_set), 0) = ep->to_rtx; |
3079 | XEXP (SET_SRC (old_set), 1) = GEN_INT (offset); | |
3080 | } | |
ace3ffcd KH |
3081 | else |
3082 | break; | |
3083 | ||
aa5524a9 BS |
3084 | val = 1; |
3085 | /* This can't have an effect on elimination offsets, so skip right | |
3086 | to the end. */ | |
3087 | goto done; | |
3088 | } | |
32131a9c RK |
3089 | } |
3090 | ||
dfac187e BS |
3091 | /* Determine the effects of this insn on elimination offsets. */ |
3092 | elimination_effects (old_body, 0); | |
3093 | ||
3094 | /* Eliminate all eliminable registers occurring in operands that | |
3095 | can be handled by reload. */ | |
3096 | extract_insn (insn); | |
dfac187e BS |
3097 | for (i = 0; i < recog_data.n_operands; i++) |
3098 | { | |
3099 | orig_operand[i] = recog_data.operand[i]; | |
3100 | substed_operand[i] = recog_data.operand[i]; | |
3101 | ||
3102 | /* For an asm statement, every operand is eliminable. */ | |
3103 | if (insn_is_asm || insn_data[icode].operand[i].eliminable) | |
3104 | { | |
3105 | /* Check for setting a register that we know about. */ | |
3106 | if (recog_data.operand_type[i] != OP_IN | |
3107 | && GET_CODE (orig_operand[i]) == REG) | |
3108 | { | |
3109 | /* If we are assigning to a register that can be eliminated, it | |
3110 | must be as part of a PARALLEL, since the code above handles | |
3111 | single SETs. We must indicate that we can no longer | |
3112 | eliminate this reg. */ | |
3113 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
3114 | ep++) | |
761fa0f7 | 3115 | if (ep->from_rtx == orig_operand[i]) |
dfac187e BS |
3116 | ep->can_eliminate = 0; |
3117 | } | |
3118 | ||
3119 | substed_operand[i] = eliminate_regs (recog_data.operand[i], 0, | |
3120 | replace ? insn : NULL_RTX); | |
3121 | if (substed_operand[i] != orig_operand[i]) | |
4977bab6 | 3122 | val = 1; |
dfac187e BS |
3123 | /* Terminate the search in check_eliminable_occurrences at |
3124 | this point. */ | |
3125 | *recog_data.operand_loc[i] = 0; | |
3126 | ||
3127 | /* If an output operand changed from a REG to a MEM and INSN is an | |
3128 | insn, write a CLOBBER insn. */ | |
3129 | if (recog_data.operand_type[i] != OP_IN | |
3130 | && GET_CODE (orig_operand[i]) == REG | |
3131 | && GET_CODE (substed_operand[i]) == MEM | |
3132 | && replace) | |
3133 | emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]), | |
3134 | insn); | |
3135 | } | |
3136 | } | |
3137 | ||
3138 | for (i = 0; i < recog_data.n_dups; i++) | |
3139 | *recog_data.dup_loc[i] | |
1d7254c5 | 3140 | = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; |
dfac187e BS |
3141 | |
3142 | /* If any eliminable remain, they aren't eliminable anymore. */ | |
3143 | check_eliminable_occurrences (old_body); | |
32131a9c | 3144 | |
dfac187e BS |
3145 | /* Substitute the operands; the new values are in the substed_operand |
3146 | array. */ | |
3147 | for (i = 0; i < recog_data.n_operands; i++) | |
3148 | *recog_data.operand_loc[i] = substed_operand[i]; | |
3149 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3150 | *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3151 | |
dfac187e | 3152 | /* If we are replacing a body that was a (set X (plus Y Z)), try to |
32131a9c RK |
3153 | re-recognize the insn. We do this in case we had a simple addition |
3154 | but now can do this as a load-address. This saves an insn in this | |
dfac187e BS |
3155 | common case. |
3156 | If re-recognition fails, the old insn code number will still be used, | |
3157 | and some register operands may have changed into PLUS expressions. | |
3158 | These will be handled by find_reloads by loading them into a register | |
1d7254c5 | 3159 | again. */ |
32131a9c | 3160 | |
dfac187e | 3161 | if (val) |
32131a9c | 3162 | { |
7c791b13 RK |
3163 | /* If we aren't replacing things permanently and we changed something, |
3164 | make another copy to ensure that all the RTL is new. Otherwise | |
3165 | things can go wrong if find_reload swaps commutative operands | |
0f41302f | 3166 | and one is inside RTL that has been copied while the other is not. */ |
dfac187e BS |
3167 | new_body = old_body; |
3168 | if (! replace) | |
1b3b5765 BS |
3169 | { |
3170 | new_body = copy_insn (old_body); | |
3171 | if (REG_NOTES (insn)) | |
3172 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3173 | } | |
dfac187e | 3174 | PATTERN (insn) = new_body; |
7c791b13 | 3175 | |
774672d2 RK |
3176 | /* If we had a move insn but now we don't, rerecognize it. This will |
3177 | cause spurious re-recognition if the old move had a PARALLEL since | |
3178 | the new one still will, but we can't call single_set without | |
3179 | having put NEW_BODY into the insn and the re-recognition won't | |
3180 | hurt in this rare case. */ | |
dfac187e BS |
3181 | /* ??? Why this huge if statement - why don't we just rerecognize the |
3182 | thing always? */ | |
3183 | if (! insn_is_asm | |
3184 | && old_set != 0 | |
774672d2 RK |
3185 | && ((GET_CODE (SET_SRC (old_set)) == REG |
3186 | && (GET_CODE (new_body) != SET | |
3187 | || GET_CODE (SET_SRC (new_body)) != REG)) | |
3188 | /* If this was a load from or store to memory, compare | |
1ccbefce RH |
3189 | the MEM in recog_data.operand to the one in the insn. |
3190 | If they are not equal, then rerecognize the insn. */ | |
774672d2 RK |
3191 | || (old_set != 0 |
3192 | && ((GET_CODE (SET_SRC (old_set)) == MEM | |
1ccbefce | 3193 | && SET_SRC (old_set) != recog_data.operand[1]) |
774672d2 | 3194 | || (GET_CODE (SET_DEST (old_set)) == MEM |
1ccbefce | 3195 | && SET_DEST (old_set) != recog_data.operand[0]))) |
774672d2 RK |
3196 | /* If this was an add insn before, rerecognize. */ |
3197 | || GET_CODE (SET_SRC (old_set)) == PLUS)) | |
4a5d0fb5 | 3198 | { |
dfac187e BS |
3199 | int new_icode = recog (PATTERN (insn), insn, 0); |
3200 | if (new_icode < 0) | |
3201 | INSN_CODE (insn) = icode; | |
4a5d0fb5 | 3202 | } |
dfac187e | 3203 | } |
32131a9c | 3204 | |
dfac187e BS |
3205 | /* Restore the old body. If there were any changes to it, we made a copy |
3206 | of it while the changes were still in place, so we'll correctly return | |
3207 | a modified insn below. */ | |
3208 | if (! replace) | |
3209 | { | |
3210 | /* Restore the old body. */ | |
3211 | for (i = 0; i < recog_data.n_operands; i++) | |
3212 | *recog_data.operand_loc[i] = orig_operand[i]; | |
3213 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3214 | *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3215 | } |
a8fdc208 | 3216 | |
dfac187e BS |
3217 | /* Update all elimination pairs to reflect the status after the current |
3218 | insn. The changes we make were determined by the earlier call to | |
3219 | elimination_effects. | |
a8efe40d | 3220 | |
423adbb9 | 3221 | We also detect cases where register elimination cannot be done, |
32131a9c RK |
3222 | namely, if a register would be both changed and referenced outside a MEM |
3223 | in the resulting insn since such an insn is often undefined and, even if | |
3224 | not, we cannot know what meaning will be given to it. Note that it is | |
3225 | valid to have a register used in an address in an insn that changes it | |
3226 | (presumably with a pre- or post-increment or decrement). | |
3227 | ||
3228 | If anything changes, return nonzero. */ | |
3229 | ||
32131a9c RK |
3230 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3231 | { | |
3232 | if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | |
3233 | ep->can_eliminate = 0; | |
3234 | ||
3235 | ep->ref_outside_mem = 0; | |
3236 | ||
3237 | if (ep->previous_offset != ep->offset) | |
3238 | val = 1; | |
32131a9c RK |
3239 | } |
3240 | ||
3241 | done: | |
9faa82d8 | 3242 | /* If we changed something, perform elimination in REG_NOTES. This is |
05b4c365 RK |
3243 | needed even when REPLACE is zero because a REG_DEAD note might refer |
3244 | to a register that we eliminate and could cause a different number | |
3245 | of spill registers to be needed in the final reload pass than in | |
3246 | the pre-passes. */ | |
20748cab | 3247 | if (val && REG_NOTES (insn) != 0) |
1914f5da | 3248 | REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn)); |
05b4c365 | 3249 | |
32131a9c RK |
3250 | return val; |
3251 | } | |
3252 | ||
cb2afeb3 R |
3253 | /* Loop through all elimination pairs. |
3254 | Recalculate the number not at initial offset. | |
3255 | ||
3256 | Compute the maximum offset (minimum offset if the stack does not | |
3257 | grow downward) for each elimination pair. */ | |
3258 | ||
3259 | static void | |
0c20a65f | 3260 | update_eliminable_offsets (void) |
cb2afeb3 R |
3261 | { |
3262 | struct elim_table *ep; | |
3263 | ||
3264 | num_not_at_initial_offset = 0; | |
3265 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3266 | { | |
3267 | ep->previous_offset = ep->offset; | |
3268 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3269 | num_not_at_initial_offset++; | |
cb2afeb3 R |
3270 | } |
3271 | } | |
3272 | ||
32131a9c RK |
3273 | /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register |
3274 | replacement we currently believe is valid, mark it as not eliminable if X | |
3275 | modifies DEST in any way other than by adding a constant integer to it. | |
3276 | ||
3277 | If DEST is the frame pointer, we do nothing because we assume that | |
3ec2ea3e DE |
3278 | all assignments to the hard frame pointer are nonlocal gotos and are being |
3279 | done at a time when they are valid and do not disturb anything else. | |
32131a9c | 3280 | Some machines want to eliminate a fake argument pointer with either the |
3ec2ea3e DE |
3281 | frame or stack pointer. Assignments to the hard frame pointer must not |
3282 | prevent this elimination. | |
32131a9c RK |
3283 | |
3284 | Called via note_stores from reload before starting its passes to scan | |
3285 | the insns of the function. */ | |
3286 | ||
3287 | static void | |
0c20a65f | 3288 | mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED) |
32131a9c | 3289 | { |
b3694847 | 3290 | unsigned int i; |
32131a9c RK |
3291 | |
3292 | /* A SUBREG of a hard register here is just changing its mode. We should | |
3293 | not see a SUBREG of an eliminable hard register, but check just in | |
3294 | case. */ | |
3295 | if (GET_CODE (dest) == SUBREG) | |
3296 | dest = SUBREG_REG (dest); | |
3297 | ||
3ec2ea3e | 3298 | if (dest == hard_frame_pointer_rtx) |
32131a9c RK |
3299 | return; |
3300 | ||
3301 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3302 | if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx | |
3303 | && (GET_CODE (x) != SET | |
3304 | || GET_CODE (SET_SRC (x)) != PLUS | |
3305 | || XEXP (SET_SRC (x), 0) != dest | |
3306 | || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) | |
3307 | { | |
3308 | reg_eliminate[i].can_eliminate_previous | |
3309 | = reg_eliminate[i].can_eliminate = 0; | |
3310 | num_eliminable--; | |
3311 | } | |
3312 | } | |
09dd1133 | 3313 | |
c47f5ea5 BS |
3314 | /* Verify that the initial elimination offsets did not change since the |
3315 | last call to set_initial_elim_offsets. This is used to catch cases | |
3316 | where something illegal happened during reload_as_needed that could | |
3317 | cause incorrect code to be generated if we did not check for it. */ | |
c8d8ed65 | 3318 | |
c47f5ea5 | 3319 | static void |
0c20a65f | 3320 | verify_initial_elim_offsets (void) |
c47f5ea5 | 3321 | { |
b19ee4bd | 3322 | HOST_WIDE_INT t; |
c47f5ea5 BS |
3323 | |
3324 | #ifdef ELIMINABLE_REGS | |
3325 | struct elim_table *ep; | |
3326 | ||
3327 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3328 | { | |
3329 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); | |
3330 | if (t != ep->initial_offset) | |
3331 | abort (); | |
3332 | } | |
3333 | #else | |
3334 | INITIAL_FRAME_POINTER_OFFSET (t); | |
3335 | if (t != reg_eliminate[0].initial_offset) | |
3336 | abort (); | |
05d10675 | 3337 | #endif |
c47f5ea5 BS |
3338 | } |
3339 | ||
09dd1133 | 3340 | /* Reset all offsets on eliminable registers to their initial values. */ |
1d813780 | 3341 | |
09dd1133 | 3342 | static void |
0c20a65f | 3343 | set_initial_elim_offsets (void) |
09dd1133 | 3344 | { |
1f3b1e1a | 3345 | struct elim_table *ep = reg_eliminate; |
09dd1133 BS |
3346 | |
3347 | #ifdef ELIMINABLE_REGS | |
1f3b1e1a | 3348 | for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
09dd1133 BS |
3349 | { |
3350 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); | |
1f3b1e1a | 3351 | ep->previous_offset = ep->offset = ep->initial_offset; |
09dd1133 BS |
3352 | } |
3353 | #else | |
1f3b1e1a JL |
3354 | INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); |
3355 | ep->previous_offset = ep->offset = ep->initial_offset; | |
09dd1133 BS |
3356 | #endif |
3357 | ||
3358 | num_not_at_initial_offset = 0; | |
1f3b1e1a | 3359 | } |
09dd1133 | 3360 | |
1f3b1e1a JL |
3361 | /* Initialize the known label offsets. |
3362 | Set a known offset for each forced label to be at the initial offset | |
3363 | of each elimination. We do this because we assume that all | |
3364 | computed jumps occur from a location where each elimination is | |
3365 | at its initial offset. | |
3366 | For all other labels, show that we don't know the offsets. */ | |
09dd1133 | 3367 | |
1f3b1e1a | 3368 | static void |
0c20a65f | 3369 | set_initial_label_offsets (void) |
1f3b1e1a JL |
3370 | { |
3371 | rtx x; | |
4cc0fdd2 | 3372 | memset (offsets_known_at, 0, num_labels); |
09dd1133 BS |
3373 | |
3374 | for (x = forced_labels; x; x = XEXP (x, 1)) | |
3375 | if (XEXP (x, 0)) | |
3376 | set_label_offsets (XEXP (x, 0), NULL_RTX, 1); | |
3377 | } | |
3378 | ||
1f3b1e1a JL |
3379 | /* Set all elimination offsets to the known values for the code label given |
3380 | by INSN. */ | |
1d813780 | 3381 | |
1f3b1e1a | 3382 | static void |
0c20a65f | 3383 | set_offsets_for_label (rtx insn) |
1f3b1e1a | 3384 | { |
973838fd | 3385 | unsigned int i; |
1f3b1e1a JL |
3386 | int label_nr = CODE_LABEL_NUMBER (insn); |
3387 | struct elim_table *ep; | |
3388 | ||
3389 | num_not_at_initial_offset = 0; | |
3390 | for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) | |
3391 | { | |
4cc0fdd2 JDA |
3392 | ep->offset = ep->previous_offset |
3393 | = offsets_at[label_nr - first_label_num][i]; | |
1f3b1e1a JL |
3394 | if (ep->can_eliminate && ep->offset != ep->initial_offset) |
3395 | num_not_at_initial_offset++; | |
3396 | } | |
3397 | } | |
3398 | ||
09dd1133 | 3399 | /* See if anything that happened changes which eliminations are valid. |
981f6289 | 3400 | For example, on the SPARC, whether or not the frame pointer can |
09dd1133 BS |
3401 | be eliminated can depend on what registers have been used. We need |
3402 | not check some conditions again (such as flag_omit_frame_pointer) | |
3403 | since they can't have changed. */ | |
3404 | ||
3405 | static void | |
0c20a65f | 3406 | update_eliminables (HARD_REG_SET *pset) |
09dd1133 | 3407 | { |
09dd1133 | 3408 | int previous_frame_pointer_needed = frame_pointer_needed; |
09dd1133 BS |
3409 | struct elim_table *ep; |
3410 | ||
3411 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3412 | if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) | |
3413 | #ifdef ELIMINABLE_REGS | |
3414 | || ! CAN_ELIMINATE (ep->from, ep->to) | |
3415 | #endif | |
3416 | ) | |
3417 | ep->can_eliminate = 0; | |
3418 | ||
3419 | /* Look for the case where we have discovered that we can't replace | |
3420 | register A with register B and that means that we will now be | |
3421 | trying to replace register A with register C. This means we can | |
3422 | no longer replace register C with register B and we need to disable | |
3423 | such an elimination, if it exists. This occurs often with A == ap, | |
3424 | B == sp, and C == fp. */ | |
3425 | ||
3426 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3427 | { | |
3428 | struct elim_table *op; | |
b3694847 | 3429 | int new_to = -1; |
09dd1133 BS |
3430 | |
3431 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3432 | { | |
3433 | /* Find the current elimination for ep->from, if there is a | |
3434 | new one. */ | |
3435 | for (op = reg_eliminate; | |
3436 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3437 | if (op->from == ep->from && op->can_eliminate) | |
3438 | { | |
3439 | new_to = op->to; | |
3440 | break; | |
3441 | } | |
3442 | ||
3443 | /* See if there is an elimination of NEW_TO -> EP->TO. If so, | |
3444 | disable it. */ | |
3445 | for (op = reg_eliminate; | |
3446 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3447 | if (op->from == new_to && op->to == ep->to) | |
3448 | op->can_eliminate = 0; | |
3449 | } | |
3450 | } | |
3451 | ||
3452 | /* See if any registers that we thought we could eliminate the previous | |
3453 | time are no longer eliminable. If so, something has changed and we | |
3454 | must spill the register. Also, recompute the number of eliminable | |
3455 | registers and see if the frame pointer is needed; it is if there is | |
3456 | no elimination of the frame pointer that we can perform. */ | |
3457 | ||
3458 | frame_pointer_needed = 1; | |
3459 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3460 | { | |
3461 | if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM | |
3462 | && ep->to != HARD_FRAME_POINTER_REGNUM) | |
3463 | frame_pointer_needed = 0; | |
3464 | ||
3465 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3466 | { | |
3467 | ep->can_eliminate_previous = 0; | |
3468 | SET_HARD_REG_BIT (*pset, ep->from); | |
3469 | num_eliminable--; | |
3470 | } | |
3471 | } | |
3472 | ||
09dd1133 BS |
3473 | /* If we didn't need a frame pointer last time, but we do now, spill |
3474 | the hard frame pointer. */ | |
3475 | if (frame_pointer_needed && ! previous_frame_pointer_needed) | |
3476 | SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); | |
09dd1133 BS |
3477 | } |
3478 | ||
3479 | /* Initialize the table of registers to eliminate. */ | |
1d813780 | 3480 | |
09dd1133 | 3481 | static void |
0c20a65f | 3482 | init_elim_table (void) |
09dd1133 BS |
3483 | { |
3484 | struct elim_table *ep; | |
590cf94d | 3485 | #ifdef ELIMINABLE_REGS |
0b5826ac | 3486 | const struct elim_table_1 *ep1; |
590cf94d | 3487 | #endif |
09dd1133 | 3488 | |
590cf94d | 3489 | if (!reg_eliminate) |
703ad42b | 3490 | reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS); |
05d10675 | 3491 | |
09dd1133 BS |
3492 | /* Does this function require a frame pointer? */ |
3493 | ||
3494 | frame_pointer_needed = (! flag_omit_frame_pointer | |
09dd1133 BS |
3495 | /* ?? If EXIT_IGNORE_STACK is set, we will not save |
3496 | and restore sp for alloca. So we can't eliminate | |
3497 | the frame pointer in that case. At some point, | |
3498 | we should improve this by emitting the | |
3499 | sp-adjusting insns for this case. */ | |
3500 | || (current_function_calls_alloca | |
3501 | && EXIT_IGNORE_STACK) | |
09dd1133 BS |
3502 | || FRAME_POINTER_REQUIRED); |
3503 | ||
3504 | num_eliminable = 0; | |
3505 | ||
3506 | #ifdef ELIMINABLE_REGS | |
590cf94d KG |
3507 | for (ep = reg_eliminate, ep1 = reg_eliminate_1; |
3508 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) | |
09dd1133 | 3509 | { |
590cf94d KG |
3510 | ep->from = ep1->from; |
3511 | ep->to = ep1->to; | |
09dd1133 BS |
3512 | ep->can_eliminate = ep->can_eliminate_previous |
3513 | = (CAN_ELIMINATE (ep->from, ep->to) | |
3514 | && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed)); | |
3515 | } | |
3516 | #else | |
590cf94d KG |
3517 | reg_eliminate[0].from = reg_eliminate_1[0].from; |
3518 | reg_eliminate[0].to = reg_eliminate_1[0].to; | |
09dd1133 BS |
3519 | reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous |
3520 | = ! frame_pointer_needed; | |
3521 | #endif | |
3522 | ||
3523 | /* Count the number of eliminable registers and build the FROM and TO | |
2fb00d7f | 3524 | REG rtx's. Note that code in gen_rtx_REG will cause, e.g., |
f84d109f | 3525 | gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. |
09dd1133 BS |
3526 | We depend on this. */ |
3527 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3528 | { | |
3529 | num_eliminable += ep->can_eliminate; | |
3530 | ep->from_rtx = gen_rtx_REG (Pmode, ep->from); | |
3531 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | |
3532 | } | |
3533 | } | |
32131a9c RK |
3534 | \f |
3535 | /* Kick all pseudos out of hard register REGNO. | |
32131a9c RK |
3536 | |
3537 | If CANT_ELIMINATE is nonzero, it means that we are doing this spill | |
3538 | because we found we can't eliminate some register. In the case, no pseudos | |
3539 | are allowed to be in the register, even if they are only in a block that | |
3540 | doesn't require spill registers, unlike the case when we are spilling this | |
3541 | hard reg to produce another spill register. | |
3542 | ||
3543 | Return nonzero if any pseudos needed to be kicked out. */ | |
3544 | ||
03acd8f8 | 3545 | static void |
0c20a65f | 3546 | spill_hard_reg (unsigned int regno, int cant_eliminate) |
32131a9c | 3547 | { |
b3694847 | 3548 | int i; |
32131a9c | 3549 | |
9ff3516a | 3550 | if (cant_eliminate) |
03acd8f8 BS |
3551 | { |
3552 | SET_HARD_REG_BIT (bad_spill_regs_global, regno); | |
3553 | regs_ever_live[regno] = 1; | |
3554 | } | |
9ff3516a | 3555 | |
32131a9c RK |
3556 | /* Spill every pseudo reg that was allocated to this reg |
3557 | or to something that overlaps this reg. */ | |
3558 | ||
3559 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3560 | if (reg_renumber[i] >= 0 | |
770ae6cc RK |
3561 | && (unsigned int) reg_renumber[i] <= regno |
3562 | && ((unsigned int) reg_renumber[i] | |
66fd46b6 JH |
3563 | + hard_regno_nregs[(unsigned int) reg_renumber[i]] |
3564 | [PSEUDO_REGNO_MODE (i)] | |
32131a9c | 3565 | > regno)) |
f5d8c9f4 | 3566 | SET_REGNO_REG_SET (&spilled_pseudos, i); |
03acd8f8 | 3567 | } |
32131a9c | 3568 | |
03acd8f8 BS |
3569 | /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET |
3570 | from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */ | |
770ae6cc | 3571 | |
03acd8f8 | 3572 | static void |
0c20a65f | 3573 | ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2) |
03acd8f8 BS |
3574 | { |
3575 | IOR_HARD_REG_SET (*set1, *set2); | |
3576 | } | |
05d10675 | 3577 | |
03acd8f8 BS |
3578 | /* After find_reload_regs has been run for all insn that need reloads, |
3579 | and/or spill_hard_regs was called, this function is used to actually | |
3580 | spill pseudo registers and try to reallocate them. It also sets up the | |
3581 | spill_regs array for use by choose_reload_regs. */ | |
a8fdc208 | 3582 | |
03acd8f8 | 3583 | static int |
0c20a65f | 3584 | finish_spills (int global) |
03acd8f8 BS |
3585 | { |
3586 | struct insn_chain *chain; | |
3587 | int something_changed = 0; | |
3588 | int i; | |
3589 | ||
3590 | /* Build the spill_regs array for the function. */ | |
3591 | /* If there are some registers still to eliminate and one of the spill regs | |
3592 | wasn't ever used before, additional stack space may have to be | |
3593 | allocated to store this register. Thus, we may have changed the offset | |
3594 | between the stack and frame pointers, so mark that something has changed. | |
32131a9c | 3595 | |
03acd8f8 BS |
3596 | One might think that we need only set VAL to 1 if this is a call-used |
3597 | register. However, the set of registers that must be saved by the | |
3598 | prologue is not identical to the call-used set. For example, the | |
3599 | register used by the call insn for the return PC is a call-used register, | |
3600 | but must be saved by the prologue. */ | |
3601 | ||
3602 | n_spills = 0; | |
3603 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3604 | if (TEST_HARD_REG_BIT (used_spill_regs, i)) | |
3605 | { | |
3606 | spill_reg_order[i] = n_spills; | |
3607 | spill_regs[n_spills++] = i; | |
3608 | if (num_eliminable && ! regs_ever_live[i]) | |
3609 | something_changed = 1; | |
3610 | regs_ever_live[i] = 1; | |
3611 | } | |
3612 | else | |
3613 | spill_reg_order[i] = -1; | |
3614 | ||
efc9bd41 RK |
3615 | EXECUTE_IF_SET_IN_REG_SET |
3616 | (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, | |
3617 | { | |
3618 | /* Record the current hard register the pseudo is allocated to in | |
3619 | pseudo_previous_regs so we avoid reallocating it to the same | |
3620 | hard reg in a later pass. */ | |
3621 | if (reg_renumber[i] < 0) | |
3622 | abort (); | |
3623 | ||
3624 | SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); | |
3625 | /* Mark it as no longer having a hard register home. */ | |
3626 | reg_renumber[i] = -1; | |
3627 | /* We will need to scan everything again. */ | |
3628 | something_changed = 1; | |
3629 | }); | |
7609e720 | 3630 | |
03acd8f8 BS |
3631 | /* Retry global register allocation if possible. */ |
3632 | if (global) | |
3633 | { | |
703ad42b | 3634 | memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET)); |
03acd8f8 BS |
3635 | /* For every insn that needs reloads, set the registers used as spill |
3636 | regs in pseudo_forbidden_regs for every pseudo live across the | |
3637 | insn. */ | |
3638 | for (chain = insns_need_reload; chain; chain = chain->next_need_reload) | |
3639 | { | |
3640 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3641 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3642 | { |
3643 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3644 | &chain->used_spill_regs); | |
3645 | }); | |
3646 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3647 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3648 | { |
3649 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3650 | &chain->used_spill_regs); | |
3651 | }); | |
3652 | } | |
7609e720 | 3653 | |
03acd8f8 BS |
3654 | /* Retry allocating the spilled pseudos. For each reg, merge the |
3655 | various reg sets that indicate which hard regs can't be used, | |
3656 | and call retry_global_alloc. | |
05d10675 | 3657 | We change spill_pseudos here to only contain pseudos that did not |
03acd8f8 BS |
3658 | get a new hard register. */ |
3659 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3660 | if (reg_old_renumber[i] != reg_renumber[i]) | |
32131a9c | 3661 | { |
03acd8f8 BS |
3662 | HARD_REG_SET forbidden; |
3663 | COPY_HARD_REG_SET (forbidden, bad_spill_regs_global); | |
3664 | IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]); | |
3665 | IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]); | |
3666 | retry_global_alloc (i, forbidden); | |
3667 | if (reg_renumber[i] >= 0) | |
f5d8c9f4 | 3668 | CLEAR_REGNO_REG_SET (&spilled_pseudos, i); |
32131a9c | 3669 | } |
03acd8f8 | 3670 | } |
7609e720 | 3671 | |
03acd8f8 BS |
3672 | /* Fix up the register information in the insn chain. |
3673 | This involves deleting those of the spilled pseudos which did not get | |
3674 | a new hard register home from the live_{before,after} sets. */ | |
7609e720 BS |
3675 | for (chain = reload_insn_chain; chain; chain = chain->next) |
3676 | { | |
03acd8f8 BS |
3677 | HARD_REG_SET used_by_pseudos; |
3678 | HARD_REG_SET used_by_pseudos2; | |
3679 | ||
239a0f5b BS |
3680 | AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); |
3681 | AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); | |
03acd8f8 BS |
3682 | |
3683 | /* Mark any unallocated hard regs as available for spills. That | |
3684 | makes inheritance work somewhat better. */ | |
3685 | if (chain->need_reload) | |
3686 | { | |
239a0f5b BS |
3687 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); |
3688 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
03acd8f8 BS |
3689 | IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); |
3690 | ||
3691 | /* Save the old value for the sanity test below. */ | |
3692 | COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs); | |
3693 | ||
239a0f5b BS |
3694 | compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); |
3695 | compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); | |
03acd8f8 BS |
3696 | COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); |
3697 | AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); | |
3698 | ||
3699 | /* Make sure we only enlarge the set. */ | |
3700 | GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok); | |
3701 | abort (); | |
3702 | ok:; | |
3703 | } | |
7609e720 | 3704 | } |
03acd8f8 BS |
3705 | |
3706 | /* Let alter_reg modify the reg rtx's for the modified pseudos. */ | |
3707 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3708 | { | |
3709 | int regno = reg_renumber[i]; | |
3710 | if (reg_old_renumber[i] == regno) | |
3711 | continue; | |
05d10675 | 3712 | |
03acd8f8 BS |
3713 | alter_reg (i, reg_old_renumber[i]); |
3714 | reg_old_renumber[i] = regno; | |
c263766c | 3715 | if (dump_file) |
03acd8f8 BS |
3716 | { |
3717 | if (regno == -1) | |
c263766c | 3718 | fprintf (dump_file, " Register %d now on stack.\n\n", i); |
03acd8f8 | 3719 | else |
c263766c | 3720 | fprintf (dump_file, " Register %d now in %d.\n\n", |
03acd8f8 BS |
3721 | i, reg_renumber[i]); |
3722 | } | |
3723 | } | |
3724 | ||
3725 | return something_changed; | |
7609e720 | 3726 | } |
32131a9c | 3727 | \f |
d754127f | 3728 | /* Find all paradoxical subregs within X and update reg_max_ref_width. */ |
32131a9c RK |
3729 | |
3730 | static void | |
0c20a65f | 3731 | scan_paradoxical_subregs (rtx x) |
32131a9c | 3732 | { |
b3694847 SS |
3733 | int i; |
3734 | const char *fmt; | |
3735 | enum rtx_code code = GET_CODE (x); | |
32131a9c RK |
3736 | |
3737 | switch (code) | |
3738 | { | |
56f58d3a | 3739 | case REG: |
32131a9c RK |
3740 | case CONST_INT: |
3741 | case CONST: | |
3742 | case SYMBOL_REF: | |
3743 | case LABEL_REF: | |
3744 | case CONST_DOUBLE: | |
69ef87e2 | 3745 | case CONST_VECTOR: /* shouldn't happen, but just in case. */ |
32131a9c RK |
3746 | case CC0: |
3747 | case PC: | |
32131a9c RK |
3748 | case USE: |
3749 | case CLOBBER: | |
3750 | return; | |
3751 | ||
3752 | case SUBREG: | |
3753 | if (GET_CODE (SUBREG_REG (x)) == REG | |
3754 | && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
3755 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
3756 | = GET_MODE_SIZE (GET_MODE (x)); | |
3757 | return; | |
05d10675 | 3758 | |
e9a25f70 JL |
3759 | default: |
3760 | break; | |
32131a9c RK |
3761 | } |
3762 | ||
3763 | fmt = GET_RTX_FORMAT (code); | |
3764 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3765 | { | |
3766 | if (fmt[i] == 'e') | |
3767 | scan_paradoxical_subregs (XEXP (x, i)); | |
3768 | else if (fmt[i] == 'E') | |
3769 | { | |
b3694847 | 3770 | int j; |
1d7254c5 | 3771 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
32131a9c RK |
3772 | scan_paradoxical_subregs (XVECEXP (x, i, j)); |
3773 | } | |
3774 | } | |
3775 | } | |
3776 | \f | |
32131a9c RK |
3777 | /* Reload pseudo-registers into hard regs around each insn as needed. |
3778 | Additional register load insns are output before the insn that needs it | |
3779 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
3780 | ||
3781 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
d08ea79f | 3782 | which registers are already available in reload registers. |
32131a9c RK |
3783 | We update these for the reloads that we perform, |
3784 | as the insns are scanned. */ | |
3785 | ||
3786 | static void | |
0c20a65f | 3787 | reload_as_needed (int live_known) |
32131a9c | 3788 | { |
7609e720 | 3789 | struct insn_chain *chain; |
553687c9 | 3790 | #if defined (AUTO_INC_DEC) |
b3694847 | 3791 | int i; |
973838fd | 3792 | #endif |
32131a9c | 3793 | rtx x; |
32131a9c | 3794 | |
703ad42b KG |
3795 | memset (spill_reg_rtx, 0, sizeof spill_reg_rtx); |
3796 | memset (spill_reg_store, 0, sizeof spill_reg_store); | |
3797 | reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx)); | |
3798 | reg_has_output_reload = xmalloc (max_regno); | |
e6e52be0 | 3799 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
e3e9336f | 3800 | CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered); |
32131a9c | 3801 | |
1f3b1e1a | 3802 | set_initial_elim_offsets (); |
32131a9c | 3803 | |
7609e720 | 3804 | for (chain = reload_insn_chain; chain; chain = chain->next) |
32131a9c | 3805 | { |
0334ef47 | 3806 | rtx prev = 0; |
7609e720 BS |
3807 | rtx insn = chain->insn; |
3808 | rtx old_next = NEXT_INSN (insn); | |
32131a9c RK |
3809 | |
3810 | /* If we pass a label, copy the offsets from the label information | |
3811 | into the current offsets of each elimination. */ | |
3812 | if (GET_CODE (insn) == CODE_LABEL) | |
1f3b1e1a | 3813 | set_offsets_for_label (insn); |
32131a9c | 3814 | |
2c3c49de | 3815 | else if (INSN_P (insn)) |
32131a9c | 3816 | { |
449655a6 | 3817 | rtx oldpat = copy_rtx (PATTERN (insn)); |
32131a9c | 3818 | |
2758481d RS |
3819 | /* If this is a USE and CLOBBER of a MEM, ensure that any |
3820 | references to eliminable registers have been removed. */ | |
3821 | ||
3822 | if ((GET_CODE (PATTERN (insn)) == USE | |
3823 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
3824 | && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) | |
3825 | XEXP (XEXP (PATTERN (insn), 0), 0) | |
3826 | = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), | |
29ae5012 | 3827 | GET_MODE (XEXP (PATTERN (insn), 0)), |
1914f5da | 3828 | NULL_RTX); |
2758481d | 3829 | |
32131a9c RK |
3830 | /* If we need to do register elimination processing, do so. |
3831 | This might delete the insn, in which case we are done. */ | |
2b49ee39 | 3832 | if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) |
32131a9c RK |
3833 | { |
3834 | eliminate_regs_in_insn (insn, 1); | |
3835 | if (GET_CODE (insn) == NOTE) | |
cb2afeb3 R |
3836 | { |
3837 | update_eliminable_offsets (); | |
3838 | continue; | |
3839 | } | |
32131a9c RK |
3840 | } |
3841 | ||
7609e720 BS |
3842 | /* If need_elim is nonzero but need_reload is zero, one might think |
3843 | that we could simply set n_reloads to 0. However, find_reloads | |
3844 | could have done some manipulation of the insn (such as swapping | |
3845 | commutative operands), and these manipulations are lost during | |
3846 | the first pass for every insn that needs register elimination. | |
3847 | So the actions of find_reloads must be redone here. */ | |
3848 | ||
03acd8f8 BS |
3849 | if (! chain->need_elim && ! chain->need_reload |
3850 | && ! chain->need_operand_change) | |
32131a9c RK |
3851 | n_reloads = 0; |
3852 | /* First find the pseudo regs that must be reloaded for this insn. | |
3853 | This info is returned in the tables reload_... (see reload.h). | |
3854 | Also modify the body of INSN by substituting RELOAD | |
3855 | rtx's for those pseudo regs. */ | |
3856 | else | |
3857 | { | |
961192e1 | 3858 | memset (reg_has_output_reload, 0, max_regno); |
32131a9c RK |
3859 | CLEAR_HARD_REG_SET (reg_is_output_reload); |
3860 | ||
3861 | find_reloads (insn, 1, spill_indirect_levels, live_known, | |
3862 | spill_reg_order); | |
3863 | } | |
3864 | ||
3865 | if (n_reloads > 0) | |
3866 | { | |
cb2afeb3 | 3867 | rtx next = NEXT_INSN (insn); |
3c3eeea6 | 3868 | rtx p; |
32131a9c | 3869 | |
cb2afeb3 R |
3870 | prev = PREV_INSN (insn); |
3871 | ||
32131a9c RK |
3872 | /* Now compute which reload regs to reload them into. Perhaps |
3873 | reusing reload regs from previous insns, or else output | |
3874 | load insns to reload them. Maybe output store insns too. | |
3875 | Record the choices of reload reg in reload_reg_rtx. */ | |
03acd8f8 | 3876 | choose_reload_regs (chain); |
32131a9c | 3877 | |
05d10675 | 3878 | /* Merge any reloads that we didn't combine for fear of |
546b63fb RK |
3879 | increasing the number of spill registers needed but now |
3880 | discover can be safely merged. */ | |
f95182a4 ILT |
3881 | if (SMALL_REGISTER_CLASSES) |
3882 | merge_assigned_reloads (insn); | |
546b63fb | 3883 | |
32131a9c RK |
3884 | /* Generate the insns to reload operands into or out of |
3885 | their reload regs. */ | |
e04ca094 | 3886 | emit_reload_insns (chain); |
32131a9c RK |
3887 | |
3888 | /* Substitute the chosen reload regs from reload_reg_rtx | |
3889 | into the insn's body (or perhaps into the bodies of other | |
3890 | load and store insn that we just made for reloading | |
3891 | and that we moved the structure into). */ | |
f759eb8b | 3892 | subst_reloads (insn); |
3c3eeea6 RK |
3893 | |
3894 | /* If this was an ASM, make sure that all the reload insns | |
3895 | we have generated are valid. If not, give an error | |
3896 | and delete them. */ | |
3897 | ||
3898 | if (asm_noperands (PATTERN (insn)) >= 0) | |
3899 | for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) | |
2c3c49de | 3900 | if (p != insn && INSN_P (p) |
00dcfe80 | 3901 | && GET_CODE (PATTERN (p)) != USE |
3c3eeea6 | 3902 | && (recog_memoized (p) < 0 |
0eadeb15 | 3903 | || (extract_insn (p), ! constrain_operands (1)))) |
3c3eeea6 RK |
3904 | { |
3905 | error_for_asm (insn, | |
3906 | "`asm' operand requires impossible reload"); | |
ca6c03ca | 3907 | delete_insn (p); |
3c3eeea6 | 3908 | } |
32131a9c | 3909 | } |
5d7ef82a BS |
3910 | |
3911 | if (num_eliminable && chain->need_elim) | |
3912 | update_eliminable_offsets (); | |
3913 | ||
32131a9c RK |
3914 | /* Any previously reloaded spilled pseudo reg, stored in this insn, |
3915 | is no longer validly lying around to save a future reload. | |
3916 | Note that this does not detect pseudos that were reloaded | |
3917 | for this insn in order to be stored in | |
3918 | (obeying register constraints). That is correct; such reload | |
3919 | registers ARE still valid. */ | |
84832317 | 3920 | note_stores (oldpat, forget_old_reloads_1, NULL); |
32131a9c RK |
3921 | |
3922 | /* There may have been CLOBBER insns placed after INSN. So scan | |
3923 | between INSN and NEXT and use them to forget old reloads. */ | |
7609e720 | 3924 | for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) |
32131a9c | 3925 | if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) |
84832317 | 3926 | note_stores (PATTERN (x), forget_old_reloads_1, NULL); |
32131a9c RK |
3927 | |
3928 | #ifdef AUTO_INC_DEC | |
cb2afeb3 R |
3929 | /* Likewise for regs altered by auto-increment in this insn. |
3930 | REG_INC notes have been changed by reloading: | |
3931 | find_reloads_address_1 records substitutions for them, | |
3932 | which have been performed by subst_reloads above. */ | |
3933 | for (i = n_reloads - 1; i >= 0; i--) | |
3934 | { | |
eceef4c9 | 3935 | rtx in_reg = rld[i].in_reg; |
cb2afeb3 R |
3936 | if (in_reg) |
3937 | { | |
3938 | enum rtx_code code = GET_CODE (in_reg); | |
3939 | /* PRE_INC / PRE_DEC will have the reload register ending up | |
3940 | with the same value as the stack slot, but that doesn't | |
3941 | hold true for POST_INC / POST_DEC. Either we have to | |
3942 | convert the memory access to a true POST_INC / POST_DEC, | |
3943 | or we can't use the reload register for inheritance. */ | |
3944 | if ((code == POST_INC || code == POST_DEC) | |
3945 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 3946 | REGNO (rld[i].reg_rtx)) |
04bbb0c5 JW |
3947 | /* Make sure it is the inc/dec pseudo, and not |
3948 | some other (e.g. output operand) pseudo. */ | |
fc555370 | 3949 | && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
04bbb0c5 | 3950 | == REGNO (XEXP (in_reg, 0)))) |
05d10675 | 3951 | |
cb2afeb3 | 3952 | { |
eceef4c9 | 3953 | rtx reload_reg = rld[i].reg_rtx; |
cb2afeb3 R |
3954 | enum machine_mode mode = GET_MODE (reload_reg); |
3955 | int n = 0; | |
3956 | rtx p; | |
3957 | ||
3958 | for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) | |
3959 | { | |
3960 | /* We really want to ignore REG_INC notes here, so | |
3961 | use PATTERN (p) as argument to reg_set_p . */ | |
3962 | if (reg_set_p (reload_reg, PATTERN (p))) | |
3963 | break; | |
4b983fdc | 3964 | n = count_occurrences (PATTERN (p), reload_reg, 0); |
cb2afeb3 R |
3965 | if (! n) |
3966 | continue; | |
3967 | if (n == 1) | |
f67c2384 JL |
3968 | { |
3969 | n = validate_replace_rtx (reload_reg, | |
2fb00d7f KH |
3970 | gen_rtx_fmt_e (code, |
3971 | mode, | |
3972 | reload_reg), | |
f67c2384 JL |
3973 | p); |
3974 | ||
3975 | /* We must also verify that the constraints | |
3976 | are met after the replacement. */ | |
3977 | extract_insn (p); | |
3978 | if (n) | |
3979 | n = constrain_operands (1); | |
3980 | else | |
3981 | break; | |
3982 | ||
3983 | /* If the constraints were not met, then | |
3984 | undo the replacement. */ | |
3985 | if (!n) | |
3986 | { | |
2fb00d7f KH |
3987 | validate_replace_rtx (gen_rtx_fmt_e (code, |
3988 | mode, | |
3989 | reload_reg), | |
f67c2384 JL |
3990 | reload_reg, p); |
3991 | break; | |
3992 | } | |
05d10675 | 3993 | |
f67c2384 | 3994 | } |
cb2afeb3 R |
3995 | break; |
3996 | } | |
3997 | if (n == 1) | |
02eb1393 R |
3998 | { |
3999 | REG_NOTES (p) | |
4000 | = gen_rtx_EXPR_LIST (REG_INC, reload_reg, | |
4001 | REG_NOTES (p)); | |
4002 | /* Mark this as having an output reload so that the | |
4003 | REG_INC processing code below won't invalidate | |
4004 | the reload for inheritance. */ | |
4005 | SET_HARD_REG_BIT (reg_is_output_reload, | |
4006 | REGNO (reload_reg)); | |
4007 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; | |
4008 | } | |
cb2afeb3 | 4009 | else |
1d7254c5 | 4010 | forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, |
84832317 | 4011 | NULL); |
cb2afeb3 | 4012 | } |
02eb1393 R |
4013 | else if ((code == PRE_INC || code == PRE_DEC) |
4014 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 4015 | REGNO (rld[i].reg_rtx)) |
02eb1393 R |
4016 | /* Make sure it is the inc/dec pseudo, and not |
4017 | some other (e.g. output operand) pseudo. */ | |
fc555370 | 4018 | && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
02eb1393 R |
4019 | == REGNO (XEXP (in_reg, 0)))) |
4020 | { | |
4021 | SET_HARD_REG_BIT (reg_is_output_reload, | |
eceef4c9 | 4022 | REGNO (rld[i].reg_rtx)); |
02eb1393 R |
4023 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; |
4024 | } | |
cb2afeb3 R |
4025 | } |
4026 | } | |
02eb1393 R |
4027 | /* If a pseudo that got a hard register is auto-incremented, |
4028 | we must purge records of copying it into pseudos without | |
4029 | hard registers. */ | |
32131a9c RK |
4030 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) |
4031 | if (REG_NOTE_KIND (x) == REG_INC) | |
4032 | { | |
4033 | /* See if this pseudo reg was reloaded in this insn. | |
4034 | If so, its last-reload info is still valid | |
4035 | because it is based on this insn's reload. */ | |
4036 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 4037 | if (rld[i].out == XEXP (x, 0)) |
32131a9c RK |
4038 | break; |
4039 | ||
08fb99fa | 4040 | if (i == n_reloads) |
84832317 | 4041 | forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); |
32131a9c RK |
4042 | } |
4043 | #endif | |
4044 | } | |
4045 | /* A reload reg's contents are unknown after a label. */ | |
4046 | if (GET_CODE (insn) == CODE_LABEL) | |
e6e52be0 | 4047 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c RK |
4048 | |
4049 | /* Don't assume a reload reg is still good after a call insn | |
e3e9336f DJ |
4050 | if it is a call-used reg, or if it contains a value that will |
4051 | be partially clobbered by the call. */ | |
546b63fb | 4052 | else if (GET_CODE (insn) == CALL_INSN) |
e3e9336f | 4053 | { |
8e2e89f7 | 4054 | AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set); |
e3e9336f DJ |
4055 | AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered); |
4056 | } | |
32131a9c | 4057 | } |
ff154f78 MM |
4058 | |
4059 | /* Clean up. */ | |
4060 | free (reg_last_reload_reg); | |
4061 | free (reg_has_output_reload); | |
32131a9c RK |
4062 | } |
4063 | ||
4064 | /* Discard all record of any value reloaded from X, | |
4065 | or reloaded in X from someplace else; | |
4066 | unless X is an output reload reg of the current insn. | |
4067 | ||
4068 | X may be a hard reg (the reload reg) | |
4069 | or it may be a pseudo reg that was reloaded from. */ | |
4070 | ||
4071 | static void | |
0c20a65f AJ |
4072 | forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED, |
4073 | void *data ATTRIBUTE_UNUSED) | |
32131a9c | 4074 | { |
770ae6cc RK |
4075 | unsigned int regno; |
4076 | unsigned int nr; | |
0a2e51a9 | 4077 | |
ddef6bc7 JJ |
4078 | /* note_stores does give us subregs of hard regs, |
4079 | subreg_regno_offset will abort if it is not a hard reg. */ | |
0a2e51a9 RS |
4080 | while (GET_CODE (x) == SUBREG) |
4081 | { | |
fefac463 AH |
4082 | /* We ignore the subreg offset when calculating the regno, |
4083 | because we are using the entire underlying hard register | |
4084 | below. */ | |
0a2e51a9 RS |
4085 | x = SUBREG_REG (x); |
4086 | } | |
32131a9c RK |
4087 | |
4088 | if (GET_CODE (x) != REG) | |
4089 | return; | |
4090 | ||
fefac463 | 4091 | regno = REGNO (x); |
32131a9c RK |
4092 | |
4093 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4094 | nr = 1; | |
4095 | else | |
4096 | { | |
770ae6cc RK |
4097 | unsigned int i; |
4098 | ||
66fd46b6 | 4099 | nr = hard_regno_nregs[regno][GET_MODE (x)]; |
32131a9c RK |
4100 | /* Storing into a spilled-reg invalidates its contents. |
4101 | This can happen if a block-local pseudo is allocated to that reg | |
4102 | and it wasn't spilled because this block's total need is 0. | |
4103 | Then some insn might have an optional reload and use this reg. */ | |
4104 | for (i = 0; i < nr; i++) | |
e6e52be0 R |
4105 | /* But don't do this if the reg actually serves as an output |
4106 | reload reg in the current instruction. */ | |
4107 | if (n_reloads == 0 | |
4108 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) | |
5d77a50c BS |
4109 | { |
4110 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); | |
e3e9336f | 4111 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i); |
5d77a50c BS |
4112 | spill_reg_store[regno + i] = 0; |
4113 | } | |
32131a9c RK |
4114 | } |
4115 | ||
4116 | /* Since value of X has changed, | |
4117 | forget any value previously copied from it. */ | |
4118 | ||
4119 | while (nr-- > 0) | |
4120 | /* But don't forget a copy if this is the output reload | |
4121 | that establishes the copy's validity. */ | |
4122 | if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) | |
4123 | reg_last_reload_reg[regno + nr] = 0; | |
4124 | } | |
4125 | \f | |
32131a9c RK |
4126 | /* The following HARD_REG_SETs indicate when each hard register is |
4127 | used for a reload of various parts of the current insn. */ | |
4128 | ||
9e3a9cf2 BS |
4129 | /* If reg is unavailable for all reloads. */ |
4130 | static HARD_REG_SET reload_reg_unavailable; | |
32131a9c RK |
4131 | /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ |
4132 | static HARD_REG_SET reload_reg_used; | |
546b63fb RK |
4133 | /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ |
4134 | static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4135 | /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ |
4136 | static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4137 | /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ |
4138 | static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4139 | /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ |
4140 | static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4141 | /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ |
4142 | static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; | |
4143 | /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ | |
4144 | static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
4145 | /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ |
4146 | static HARD_REG_SET reload_reg_used_in_op_addr; | |
893bc853 RK |
4147 | /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ |
4148 | static HARD_REG_SET reload_reg_used_in_op_addr_reload; | |
546b63fb RK |
4149 | /* If reg is in use for a RELOAD_FOR_INSN reload. */ |
4150 | static HARD_REG_SET reload_reg_used_in_insn; | |
4151 | /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ | |
4152 | static HARD_REG_SET reload_reg_used_in_other_addr; | |
32131a9c RK |
4153 | |
4154 | /* If reg is in use as a reload reg for any sort of reload. */ | |
4155 | static HARD_REG_SET reload_reg_used_at_all; | |
4156 | ||
be7ae2a4 RK |
4157 | /* If reg is use as an inherited reload. We just mark the first register |
4158 | in the group. */ | |
4159 | static HARD_REG_SET reload_reg_used_for_inherit; | |
4160 | ||
f1db3576 JL |
4161 | /* Records which hard regs are used in any way, either as explicit use or |
4162 | by being allocated to a pseudo during any point of the current insn. */ | |
4163 | static HARD_REG_SET reg_used_in_insn; | |
297927a8 | 4164 | |
546b63fb RK |
4165 | /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and |
4166 | TYPE. MODE is used to indicate how many consecutive regs are | |
4167 | actually used. */ | |
32131a9c RK |
4168 | |
4169 | static void | |
0c20a65f AJ |
4170 | mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type, |
4171 | enum machine_mode mode) | |
32131a9c | 4172 | { |
66fd46b6 | 4173 | unsigned int nregs = hard_regno_nregs[regno][mode]; |
770ae6cc | 4174 | unsigned int i; |
32131a9c RK |
4175 | |
4176 | for (i = regno; i < nregs + regno; i++) | |
4177 | { | |
546b63fb | 4178 | switch (type) |
32131a9c RK |
4179 | { |
4180 | case RELOAD_OTHER: | |
4181 | SET_HARD_REG_BIT (reload_reg_used, i); | |
4182 | break; | |
4183 | ||
546b63fb RK |
4184 | case RELOAD_FOR_INPUT_ADDRESS: |
4185 | SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); | |
32131a9c RK |
4186 | break; |
4187 | ||
47c8cf91 ILT |
4188 | case RELOAD_FOR_INPADDR_ADDRESS: |
4189 | SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); | |
4190 | break; | |
4191 | ||
546b63fb RK |
4192 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4193 | SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); | |
32131a9c RK |
4194 | break; |
4195 | ||
47c8cf91 ILT |
4196 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4197 | SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); | |
4198 | break; | |
4199 | ||
32131a9c RK |
4200 | case RELOAD_FOR_OPERAND_ADDRESS: |
4201 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
4202 | break; | |
4203 | ||
893bc853 RK |
4204 | case RELOAD_FOR_OPADDR_ADDR: |
4205 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); | |
4206 | break; | |
4207 | ||
546b63fb RK |
4208 | case RELOAD_FOR_OTHER_ADDRESS: |
4209 | SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); | |
4210 | break; | |
4211 | ||
32131a9c | 4212 | case RELOAD_FOR_INPUT: |
546b63fb | 4213 | SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); |
32131a9c RK |
4214 | break; |
4215 | ||
4216 | case RELOAD_FOR_OUTPUT: | |
546b63fb RK |
4217 | SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); |
4218 | break; | |
4219 | ||
4220 | case RELOAD_FOR_INSN: | |
4221 | SET_HARD_REG_BIT (reload_reg_used_in_insn, i); | |
32131a9c RK |
4222 | break; |
4223 | } | |
4224 | ||
4225 | SET_HARD_REG_BIT (reload_reg_used_at_all, i); | |
4226 | } | |
4227 | } | |
4228 | ||
be7ae2a4 RK |
4229 | /* Similarly, but show REGNO is no longer in use for a reload. */ |
4230 | ||
4231 | static void | |
0c20a65f AJ |
4232 | clear_reload_reg_in_use (unsigned int regno, int opnum, |
4233 | enum reload_type type, enum machine_mode mode) | |
be7ae2a4 | 4234 | { |
66fd46b6 | 4235 | unsigned int nregs = hard_regno_nregs[regno][mode]; |
770ae6cc | 4236 | unsigned int start_regno, end_regno, r; |
be7ae2a4 | 4237 | int i; |
cb2afeb3 R |
4238 | /* A complication is that for some reload types, inheritance might |
4239 | allow multiple reloads of the same types to share a reload register. | |
4240 | We set check_opnum if we have to check only reloads with the same | |
4241 | operand number, and check_any if we have to check all reloads. */ | |
4242 | int check_opnum = 0; | |
4243 | int check_any = 0; | |
4244 | HARD_REG_SET *used_in_set; | |
be7ae2a4 | 4245 | |
cb2afeb3 | 4246 | switch (type) |
be7ae2a4 | 4247 | { |
cb2afeb3 R |
4248 | case RELOAD_OTHER: |
4249 | used_in_set = &reload_reg_used; | |
4250 | break; | |
be7ae2a4 | 4251 | |
cb2afeb3 R |
4252 | case RELOAD_FOR_INPUT_ADDRESS: |
4253 | used_in_set = &reload_reg_used_in_input_addr[opnum]; | |
4254 | break; | |
be7ae2a4 | 4255 | |
cb2afeb3 R |
4256 | case RELOAD_FOR_INPADDR_ADDRESS: |
4257 | check_opnum = 1; | |
4258 | used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; | |
4259 | break; | |
47c8cf91 | 4260 | |
cb2afeb3 R |
4261 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4262 | used_in_set = &reload_reg_used_in_output_addr[opnum]; | |
4263 | break; | |
be7ae2a4 | 4264 | |
cb2afeb3 R |
4265 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4266 | check_opnum = 1; | |
4267 | used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; | |
4268 | break; | |
47c8cf91 | 4269 | |
cb2afeb3 R |
4270 | case RELOAD_FOR_OPERAND_ADDRESS: |
4271 | used_in_set = &reload_reg_used_in_op_addr; | |
4272 | break; | |
be7ae2a4 | 4273 | |
cb2afeb3 R |
4274 | case RELOAD_FOR_OPADDR_ADDR: |
4275 | check_any = 1; | |
4276 | used_in_set = &reload_reg_used_in_op_addr_reload; | |
4277 | break; | |
893bc853 | 4278 | |
cb2afeb3 R |
4279 | case RELOAD_FOR_OTHER_ADDRESS: |
4280 | used_in_set = &reload_reg_used_in_other_addr; | |
4281 | check_any = 1; | |
4282 | break; | |
be7ae2a4 | 4283 | |
cb2afeb3 R |
4284 | case RELOAD_FOR_INPUT: |
4285 | used_in_set = &reload_reg_used_in_input[opnum]; | |
4286 | break; | |
be7ae2a4 | 4287 | |
cb2afeb3 R |
4288 | case RELOAD_FOR_OUTPUT: |
4289 | used_in_set = &reload_reg_used_in_output[opnum]; | |
4290 | break; | |
be7ae2a4 | 4291 | |
cb2afeb3 R |
4292 | case RELOAD_FOR_INSN: |
4293 | used_in_set = &reload_reg_used_in_insn; | |
4294 | break; | |
4295 | default: | |
4296 | abort (); | |
4297 | } | |
4298 | /* We resolve conflicts with remaining reloads of the same type by | |
68e82b83 | 4299 | excluding the intervals of reload registers by them from the |
cb2afeb3 R |
4300 | interval of freed reload registers. Since we only keep track of |
4301 | one set of interval bounds, we might have to exclude somewhat | |
3e92902c | 4302 | more than what would be necessary if we used a HARD_REG_SET here. |
cb2afeb3 R |
4303 | But this should only happen very infrequently, so there should |
4304 | be no reason to worry about it. */ | |
05d10675 | 4305 | |
cb2afeb3 R |
4306 | start_regno = regno; |
4307 | end_regno = regno + nregs; | |
4308 | if (check_opnum || check_any) | |
4309 | { | |
4310 | for (i = n_reloads - 1; i >= 0; i--) | |
4311 | { | |
eceef4c9 BS |
4312 | if (rld[i].when_needed == type |
4313 | && (check_any || rld[i].opnum == opnum) | |
4314 | && rld[i].reg_rtx) | |
cb2afeb3 | 4315 | { |
770ae6cc RK |
4316 | unsigned int conflict_start = true_regnum (rld[i].reg_rtx); |
4317 | unsigned int conflict_end | |
cb2afeb3 | 4318 | = (conflict_start |
66fd46b6 | 4319 | + hard_regno_nregs[conflict_start][rld[i].mode]); |
cb2afeb3 R |
4320 | |
4321 | /* If there is an overlap with the first to-be-freed register, | |
4322 | adjust the interval start. */ | |
4323 | if (conflict_start <= start_regno && conflict_end > start_regno) | |
4324 | start_regno = conflict_end; | |
4325 | /* Otherwise, if there is a conflict with one of the other | |
4326 | to-be-freed registers, adjust the interval end. */ | |
4327 | if (conflict_start > start_regno && conflict_start < end_regno) | |
4328 | end_regno = conflict_start; | |
4329 | } | |
be7ae2a4 RK |
4330 | } |
4331 | } | |
770ae6cc RK |
4332 | |
4333 | for (r = start_regno; r < end_regno; r++) | |
4334 | CLEAR_HARD_REG_BIT (*used_in_set, r); | |
be7ae2a4 RK |
4335 | } |
4336 | ||
32131a9c | 4337 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort |
546b63fb | 4338 | specified by OPNUM and TYPE. */ |
32131a9c RK |
4339 | |
4340 | static int | |
0c20a65f | 4341 | reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type) |
32131a9c | 4342 | { |
546b63fb RK |
4343 | int i; |
4344 | ||
2edc8d65 | 4345 | /* In use for a RELOAD_OTHER means it's not available for anything. */ |
9e3a9cf2 BS |
4346 | if (TEST_HARD_REG_BIT (reload_reg_used, regno) |
4347 | || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) | |
32131a9c | 4348 | return 0; |
546b63fb RK |
4349 | |
4350 | switch (type) | |
32131a9c RK |
4351 | { |
4352 | case RELOAD_OTHER: | |
2edc8d65 RK |
4353 | /* In use for anything means we can't use it for RELOAD_OTHER. */ |
4354 | if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) | |
224f1d71 | 4355 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
808ededc | 4356 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) |
224f1d71 RK |
4357 | || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) |
4358 | return 0; | |
4359 | ||
4360 | for (i = 0; i < reload_n_operands; i++) | |
4361 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4362 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
224f1d71 | 4363 | || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
47c8cf91 | 4364 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
224f1d71 RK |
4365 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) |
4366 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4367 | return 0; | |
4368 | ||
4369 | return 1; | |
32131a9c | 4370 | |
32131a9c | 4371 | case RELOAD_FOR_INPUT: |
546b63fb RK |
4372 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4373 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
4374 | return 0; | |
4375 | ||
893bc853 RK |
4376 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4377 | return 0; | |
4378 | ||
546b63fb RK |
4379 | /* If it is used for some other input, can't use it. */ |
4380 | for (i = 0; i < reload_n_operands; i++) | |
4381 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4382 | return 0; | |
4383 | ||
4384 | /* If it is used in a later operand's address, can't use it. */ | |
4385 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4386 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4387 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4388 | return 0; |
4389 | ||
4390 | return 1; | |
4391 | ||
4392 | case RELOAD_FOR_INPUT_ADDRESS: | |
4393 | /* Can't use a register if it is used for an input address for this | |
4394 | operand or used as an input in an earlier one. */ | |
47c8cf91 ILT |
4395 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) |
4396 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) | |
4397 | return 0; | |
4398 | ||
4399 | for (i = 0; i < opnum; i++) | |
4400 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4401 | return 0; | |
4402 | ||
4403 | return 1; | |
4404 | ||
4405 | case RELOAD_FOR_INPADDR_ADDRESS: | |
4406 | /* Can't use a register if it is used for an input address | |
05d10675 BS |
4407 | for this operand or used as an input in an earlier |
4408 | one. */ | |
47c8cf91 | 4409 | if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) |
546b63fb RK |
4410 | return 0; |
4411 | ||
4412 | for (i = 0; i < opnum; i++) | |
4413 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4414 | return 0; | |
4415 | ||
4416 | return 1; | |
4417 | ||
4418 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
4419 | /* Can't use a register if it is used for an output address for this | |
d1d18b46 DJ |
4420 | operand or used as an output in this or a later operand. Note |
4421 | that multiple output operands are emitted in reverse order, so | |
4422 | the conflicting ones are those with lower indices. */ | |
546b63fb RK |
4423 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) |
4424 | return 0; | |
4425 | ||
d1d18b46 | 4426 | for (i = 0; i <= opnum; i++) |
546b63fb RK |
4427 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4428 | return 0; | |
4429 | ||
4430 | return 1; | |
4431 | ||
47c8cf91 ILT |
4432 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4433 | /* Can't use a register if it is used for an output address | |
05d10675 | 4434 | for this operand or used as an output in this or a |
d1d18b46 DJ |
4435 | later operand. Note that multiple output operands are |
4436 | emitted in reverse order, so the conflicting ones are | |
4437 | those with lower indices. */ | |
47c8cf91 ILT |
4438 | if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) |
4439 | return 0; | |
4440 | ||
d1d18b46 | 4441 | for (i = 0; i <= opnum; i++) |
47c8cf91 ILT |
4442 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4443 | return 0; | |
4444 | ||
4445 | return 1; | |
4446 | ||
32131a9c | 4447 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4448 | for (i = 0; i < reload_n_operands; i++) |
4449 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4450 | return 0; | |
4451 | ||
4452 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4453 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4454 | ||
893bc853 RK |
4455 | case RELOAD_FOR_OPADDR_ADDR: |
4456 | for (i = 0; i < reload_n_operands; i++) | |
05d10675 BS |
4457 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4458 | return 0; | |
893bc853 | 4459 | |
a94ce333 | 4460 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); |
893bc853 | 4461 | |
32131a9c | 4462 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4463 | /* This cannot share a register with RELOAD_FOR_INSN reloads, other |
d1d18b46 DJ |
4464 | outputs, or an operand address for this or an earlier output. |
4465 | Note that multiple output operands are emitted in reverse order, | |
4466 | so the conflicting ones are those with higher indices. */ | |
546b63fb RK |
4467 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) |
4468 | return 0; | |
4469 | ||
4470 | for (i = 0; i < reload_n_operands; i++) | |
4471 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4472 | return 0; | |
4473 | ||
d1d18b46 | 4474 | for (i = opnum; i < reload_n_operands; i++) |
47c8cf91 ILT |
4475 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4476 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4477 | return 0; |
4478 | ||
4479 | return 1; | |
4480 | ||
4481 | case RELOAD_FOR_INSN: | |
4482 | for (i = 0; i < reload_n_operands; i++) | |
4483 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) | |
4484 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4485 | return 0; | |
4486 | ||
4487 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4488 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4489 | ||
4490 | case RELOAD_FOR_OTHER_ADDRESS: | |
4491 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
32131a9c RK |
4492 | } |
4493 | abort (); | |
4494 | } | |
4495 | ||
32131a9c | 4496 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
546b63fb | 4497 | needed for the part of the insn specified by OPNUM and TYPE, |
32131a9c RK |
4498 | is still available in REGNO at the end of the insn. |
4499 | ||
4500 | We can assume that the reload reg was already tested for availability | |
4501 | at the time it is needed, and we should not check this again, | |
4502 | in case the reg has already been marked in use. */ | |
4503 | ||
4504 | static int | |
0c20a65f | 4505 | reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type) |
32131a9c | 4506 | { |
546b63fb RK |
4507 | int i; |
4508 | ||
4509 | switch (type) | |
32131a9c RK |
4510 | { |
4511 | case RELOAD_OTHER: | |
4512 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
4513 | its value must reach the end. */ | |
4514 | return 1; | |
4515 | ||
4516 | /* If this use is for part of the insn, | |
05d10675 | 4517 | its value reaches if no subsequent part uses the same register. |
546b63fb RK |
4518 | Just like the above function, don't try to do this with lots |
4519 | of fallthroughs. */ | |
4520 | ||
4521 | case RELOAD_FOR_OTHER_ADDRESS: | |
4522 | /* Here we check for everything else, since these don't conflict | |
4523 | with anything else and everything comes later. */ | |
4524 | ||
4525 | for (i = 0; i < reload_n_operands; i++) | |
4526 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4527 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4528 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) |
4529 | || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4530 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4531 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4532 | return 0; | |
4533 | ||
4534 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
808ededc | 4535 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) |
546b63fb RK |
4536 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4537 | && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
4538 | ||
4539 | case RELOAD_FOR_INPUT_ADDRESS: | |
47c8cf91 | 4540 | case RELOAD_FOR_INPADDR_ADDRESS: |
546b63fb RK |
4541 | /* Similar, except that we check only for this and subsequent inputs |
4542 | and the address of only subsequent inputs and we do not need | |
4543 | to check for RELOAD_OTHER objects since they are known not to | |
4544 | conflict. */ | |
4545 | ||
4546 | for (i = opnum; i < reload_n_operands; i++) | |
4547 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4548 | return 0; | |
4549 | ||
4550 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4551 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4552 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4553 | return 0; |
4554 | ||
4555 | for (i = 0; i < reload_n_operands; i++) | |
4556 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4557 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4558 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4559 | return 0; | |
4560 | ||
893bc853 RK |
4561 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4562 | return 0; | |
4563 | ||
2af88768 GK |
4564 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4565 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4566 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
546b63fb | 4567 | |
32131a9c | 4568 | case RELOAD_FOR_INPUT: |
546b63fb | 4569 | /* Similar to input address, except we start at the next operand for |
05d10675 | 4570 | both input and input address and we do not check for |
546b63fb RK |
4571 | RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these |
4572 | would conflict. */ | |
4573 | ||
4574 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4575 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4576 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4577 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4578 | return 0; | |
4579 | ||
0f41302f | 4580 | /* ... fall through ... */ |
546b63fb | 4581 | |
32131a9c | 4582 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4583 | /* Check outputs and their addresses. */ |
4584 | ||
4585 | for (i = 0; i < reload_n_operands; i++) | |
4586 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4587 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4588 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4589 | return 0; | |
4590 | ||
2af88768 | 4591 | return (!TEST_HARD_REG_BIT (reload_reg_used, regno)); |
546b63fb | 4592 | |
893bc853 RK |
4593 | case RELOAD_FOR_OPADDR_ADDR: |
4594 | for (i = 0; i < reload_n_operands; i++) | |
4595 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4596 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
893bc853 RK |
4597 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4598 | return 0; | |
4599 | ||
2af88768 GK |
4600 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4601 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4602 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
893bc853 | 4603 | |
546b63fb | 4604 | case RELOAD_FOR_INSN: |
893bc853 | 4605 | /* These conflict with other outputs with RELOAD_OTHER. So |
546b63fb RK |
4606 | we need only check for output addresses. */ |
4607 | ||
d1d18b46 | 4608 | opnum = reload_n_operands; |
546b63fb | 4609 | |
0f41302f | 4610 | /* ... fall through ... */ |
546b63fb | 4611 | |
32131a9c | 4612 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4613 | case RELOAD_FOR_OUTPUT_ADDRESS: |
47c8cf91 | 4614 | case RELOAD_FOR_OUTADDR_ADDRESS: |
546b63fb | 4615 | /* We already know these can't conflict with a later output. So the |
d1d18b46 DJ |
4616 | only thing to check are later output addresses. |
4617 | Note that multiple output operands are emitted in reverse order, | |
4618 | so the conflicting ones are those with lower indices. */ | |
4619 | for (i = 0; i < opnum; i++) | |
47c8cf91 ILT |
4620 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4621 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4622 | return 0; |
4623 | ||
32131a9c RK |
4624 | return 1; |
4625 | } | |
546b63fb | 4626 | |
32131a9c RK |
4627 | abort (); |
4628 | } | |
4629 | \f | |
351aa1c1 RK |
4630 | /* Return 1 if the reloads denoted by R1 and R2 cannot share a register. |
4631 | Return 0 otherwise. | |
4632 | ||
4633 | This function uses the same algorithm as reload_reg_free_p above. */ | |
4634 | ||
f5963e61 | 4635 | int |
0c20a65f | 4636 | reloads_conflict (int r1, int r2) |
351aa1c1 | 4637 | { |
eceef4c9 BS |
4638 | enum reload_type r1_type = rld[r1].when_needed; |
4639 | enum reload_type r2_type = rld[r2].when_needed; | |
4640 | int r1_opnum = rld[r1].opnum; | |
4641 | int r2_opnum = rld[r2].opnum; | |
351aa1c1 | 4642 | |
2edc8d65 RK |
4643 | /* RELOAD_OTHER conflicts with everything. */ |
4644 | if (r2_type == RELOAD_OTHER) | |
351aa1c1 RK |
4645 | return 1; |
4646 | ||
4647 | /* Otherwise, check conflicts differently for each type. */ | |
4648 | ||
4649 | switch (r1_type) | |
4650 | { | |
4651 | case RELOAD_FOR_INPUT: | |
05d10675 | 4652 | return (r2_type == RELOAD_FOR_INSN |
351aa1c1 | 4653 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS |
893bc853 | 4654 | || r2_type == RELOAD_FOR_OPADDR_ADDR |
351aa1c1 | 4655 | || r2_type == RELOAD_FOR_INPUT |
47c8cf91 ILT |
4656 | || ((r2_type == RELOAD_FOR_INPUT_ADDRESS |
4657 | || r2_type == RELOAD_FOR_INPADDR_ADDRESS) | |
4658 | && r2_opnum > r1_opnum)); | |
351aa1c1 RK |
4659 | |
4660 | case RELOAD_FOR_INPUT_ADDRESS: | |
4661 | return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) | |
4662 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4663 | ||
47c8cf91 ILT |
4664 | case RELOAD_FOR_INPADDR_ADDRESS: |
4665 | return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) | |
4666 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4667 | ||
351aa1c1 RK |
4668 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4669 | return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 4670 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
351aa1c1 | 4671 | |
47c8cf91 ILT |
4672 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4673 | return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 4674 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
47c8cf91 | 4675 | |
351aa1c1 RK |
4676 | case RELOAD_FOR_OPERAND_ADDRESS: |
4677 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN | |
a94ce333 | 4678 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); |
351aa1c1 | 4679 | |
893bc853 | 4680 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 | 4681 | return (r2_type == RELOAD_FOR_INPUT |
a94ce333 | 4682 | || r2_type == RELOAD_FOR_OPADDR_ADDR); |
893bc853 | 4683 | |
351aa1c1 RK |
4684 | case RELOAD_FOR_OUTPUT: |
4685 | return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT | |
47c8cf91 ILT |
4686 | || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS |
4687 | || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) | |
d1d18b46 | 4688 | && r2_opnum >= r1_opnum)); |
351aa1c1 RK |
4689 | |
4690 | case RELOAD_FOR_INSN: | |
4691 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT | |
4692 | || r2_type == RELOAD_FOR_INSN | |
4693 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); | |
4694 | ||
4695 | case RELOAD_FOR_OTHER_ADDRESS: | |
4696 | return r2_type == RELOAD_FOR_OTHER_ADDRESS; | |
4697 | ||
adab4fc5 | 4698 | case RELOAD_OTHER: |
2edc8d65 | 4699 | return 1; |
adab4fc5 | 4700 | |
351aa1c1 RK |
4701 | default: |
4702 | abort (); | |
4703 | } | |
4704 | } | |
4705 | \f | |
32131a9c RK |
4706 | /* Indexed by reload number, 1 if incoming value |
4707 | inherited from previous insns. */ | |
4708 | char reload_inherited[MAX_RELOADS]; | |
4709 | ||
4710 | /* For an inherited reload, this is the insn the reload was inherited from, | |
4711 | if we know it. Otherwise, this is 0. */ | |
4712 | rtx reload_inheritance_insn[MAX_RELOADS]; | |
4713 | ||
40f03658 | 4714 | /* If nonzero, this is a place to get the value of the reload, |
32131a9c RK |
4715 | rather than using reload_in. */ |
4716 | rtx reload_override_in[MAX_RELOADS]; | |
4717 | ||
e6e52be0 R |
4718 | /* For each reload, the hard register number of the register used, |
4719 | or -1 if we did not need a register for this reload. */ | |
32131a9c RK |
4720 | int reload_spill_index[MAX_RELOADS]; |
4721 | ||
304a22dd R |
4722 | /* Subroutine of free_for_value_p, used to check a single register. |
4723 | START_REGNO is the starting regno of the full reload register | |
4724 | (possibly comprising multiple hard registers) that we are considering. */ | |
f5470689 | 4725 | |
6e684430 | 4726 | static int |
0c20a65f AJ |
4727 | reload_reg_free_for_value_p (int start_regno, int regno, int opnum, |
4728 | enum reload_type type, rtx value, rtx out, | |
4729 | int reloadnum, int ignore_address_reloads) | |
6e684430 R |
4730 | { |
4731 | int time1; | |
09a308fe R |
4732 | /* Set if we see an input reload that must not share its reload register |
4733 | with any new earlyclobber, but might otherwise share the reload | |
4734 | register with an output or input-output reload. */ | |
4735 | int check_earlyclobber = 0; | |
6e684430 | 4736 | int i; |
dfe96118 R |
4737 | int copy = 0; |
4738 | ||
9e3a9cf2 | 4739 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) |
dc8842bf AH |
4740 | return 0; |
4741 | ||
dfe96118 R |
4742 | if (out == const0_rtx) |
4743 | { | |
4744 | copy = 1; | |
4745 | out = NULL_RTX; | |
4746 | } | |
6e684430 R |
4747 | |
4748 | /* We use some pseudo 'time' value to check if the lifetimes of the | |
4749 | new register use would overlap with the one of a previous reload | |
4750 | that is not read-only or uses a different value. | |
4751 | The 'time' used doesn't have to be linear in any shape or form, just | |
4752 | monotonic. | |
4753 | Some reload types use different 'buckets' for each operand. | |
4754 | So there are MAX_RECOG_OPERANDS different time values for each | |
cecbf6e2 R |
4755 | such reload type. |
4756 | We compute TIME1 as the time when the register for the prospective | |
4757 | new reload ceases to be live, and TIME2 for each existing | |
4758 | reload as the time when that the reload register of that reload | |
4759 | becomes live. | |
4760 | Where there is little to be gained by exact lifetime calculations, | |
4761 | we just make conservative assumptions, i.e. a longer lifetime; | |
4762 | this is done in the 'default:' cases. */ | |
6e684430 R |
4763 | switch (type) |
4764 | { | |
4765 | case RELOAD_FOR_OTHER_ADDRESS: | |
203588e7 | 4766 | /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ |
c2b4b171 | 4767 | time1 = copy ? 0 : 1; |
6e684430 | 4768 | break; |
dfe96118 R |
4769 | case RELOAD_OTHER: |
4770 | time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; | |
4771 | break; | |
05d10675 BS |
4772 | /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, |
4773 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , | |
4774 | respectively, to the time values for these, we get distinct time | |
4775 | values. To get distinct time values for each operand, we have to | |
4776 | multiply opnum by at least three. We round that up to four because | |
4777 | multiply by four is often cheaper. */ | |
6e684430 | 4778 | case RELOAD_FOR_INPADDR_ADDRESS: |
dfe96118 | 4779 | time1 = opnum * 4 + 2; |
6e684430 R |
4780 | break; |
4781 | case RELOAD_FOR_INPUT_ADDRESS: | |
dfe96118 R |
4782 | time1 = opnum * 4 + 3; |
4783 | break; | |
4784 | case RELOAD_FOR_INPUT: | |
4785 | /* All RELOAD_FOR_INPUT reloads remain live till the instruction | |
4786 | executes (inclusive). */ | |
4787 | time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; | |
6e684430 | 4788 | break; |
cb2afeb3 | 4789 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 BS |
4790 | /* opnum * 4 + 4 |
4791 | <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ | |
cb2afeb3 R |
4792 | time1 = MAX_RECOG_OPERANDS * 4 + 1; |
4793 | break; | |
4794 | case RELOAD_FOR_OPERAND_ADDRESS: | |
4795 | /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn | |
4796 | is executed. */ | |
dfe96118 R |
4797 | time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; |
4798 | break; | |
4799 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
4800 | time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; | |
6e684430 | 4801 | break; |
6e684430 | 4802 | case RELOAD_FOR_OUTPUT_ADDRESS: |
dfe96118 | 4803 | time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; |
6e684430 R |
4804 | break; |
4805 | default: | |
dfe96118 | 4806 | time1 = MAX_RECOG_OPERANDS * 5 + 5; |
6e684430 R |
4807 | } |
4808 | ||
4809 | for (i = 0; i < n_reloads; i++) | |
4810 | { | |
eceef4c9 | 4811 | rtx reg = rld[i].reg_rtx; |
6e684430 R |
4812 | if (reg && GET_CODE (reg) == REG |
4813 | && ((unsigned) regno - true_regnum (reg) | |
66fd46b6 | 4814 | <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1) |
f5470689 | 4815 | && i != reloadnum) |
6e684430 | 4816 | { |
304a22dd R |
4817 | rtx other_input = rld[i].in; |
4818 | ||
4819 | /* If the other reload loads the same input value, that | |
4820 | will not cause a conflict only if it's loading it into | |
4821 | the same register. */ | |
4822 | if (true_regnum (reg) != start_regno) | |
4823 | other_input = NULL_RTX; | |
4824 | if (! other_input || ! rtx_equal_p (other_input, value) | |
eceef4c9 | 4825 | || rld[i].out || out) |
6e684430 | 4826 | { |
09a308fe | 4827 | int time2; |
eceef4c9 | 4828 | switch (rld[i].when_needed) |
f5470689 R |
4829 | { |
4830 | case RELOAD_FOR_OTHER_ADDRESS: | |
4831 | time2 = 0; | |
4832 | break; | |
4833 | case RELOAD_FOR_INPADDR_ADDRESS: | |
cb2afeb3 R |
4834 | /* find_reloads makes sure that a |
4835 | RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used | |
4836 | by at most one - the first - | |
4837 | RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the | |
4838 | address reload is inherited, the address address reload | |
4839 | goes away, so we can ignore this conflict. */ | |
dfe96118 R |
4840 | if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 |
4841 | && ignore_address_reloads | |
4842 | /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. | |
4843 | Then the address address is still needed to store | |
4844 | back the new address. */ | |
eceef4c9 | 4845 | && ! rld[reloadnum].out) |
cb2afeb3 | 4846 | continue; |
dfe96118 R |
4847 | /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its |
4848 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS | |
4849 | reloads go away. */ | |
eceef4c9 | 4850 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 R |
4851 | && ignore_address_reloads |
4852 | /* Unless we are reloading an auto_inc expression. */ | |
eceef4c9 | 4853 | && ! rld[reloadnum].out) |
dfe96118 | 4854 | continue; |
eceef4c9 | 4855 | time2 = rld[i].opnum * 4 + 2; |
f5470689 R |
4856 | break; |
4857 | case RELOAD_FOR_INPUT_ADDRESS: | |
eceef4c9 | 4858 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 | 4859 | && ignore_address_reloads |
eceef4c9 | 4860 | && ! rld[reloadnum].out) |
dfe96118 | 4861 | continue; |
eceef4c9 | 4862 | time2 = rld[i].opnum * 4 + 3; |
f5470689 R |
4863 | break; |
4864 | case RELOAD_FOR_INPUT: | |
eceef4c9 | 4865 | time2 = rld[i].opnum * 4 + 4; |
09a308fe | 4866 | check_earlyclobber = 1; |
f5470689 | 4867 | break; |
eceef4c9 | 4868 | /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 |
05d10675 | 4869 | == MAX_RECOG_OPERAND * 4 */ |
cb2afeb3 | 4870 | case RELOAD_FOR_OPADDR_ADDR: |
dfe96118 R |
4871 | if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 |
4872 | && ignore_address_reloads | |
eceef4c9 | 4873 | && ! rld[reloadnum].out) |
cb2afeb3 | 4874 | continue; |
dfe96118 | 4875 | time2 = MAX_RECOG_OPERANDS * 4 + 1; |
cb2afeb3 R |
4876 | break; |
4877 | case RELOAD_FOR_OPERAND_ADDRESS: | |
dfe96118 | 4878 | time2 = MAX_RECOG_OPERANDS * 4 + 2; |
09a308fe | 4879 | check_earlyclobber = 1; |
dfe96118 R |
4880 | break; |
4881 | case RELOAD_FOR_INSN: | |
4882 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
cb2afeb3 | 4883 | break; |
f5470689 | 4884 | case RELOAD_FOR_OUTPUT: |
05d10675 BS |
4885 | /* All RELOAD_FOR_OUTPUT reloads become live just after the |
4886 | instruction is executed. */ | |
dfe96118 | 4887 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
f5470689 | 4888 | break; |
05d10675 BS |
4889 | /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with |
4890 | the RELOAD_FOR_OUTPUT reloads, so assign it the same time | |
4891 | value. */ | |
cb2afeb3 | 4892 | case RELOAD_FOR_OUTADDR_ADDRESS: |
dfe96118 R |
4893 | if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 |
4894 | && ignore_address_reloads | |
eceef4c9 | 4895 | && ! rld[reloadnum].out) |
cb2afeb3 | 4896 | continue; |
eceef4c9 | 4897 | time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; |
dfe96118 | 4898 | break; |
f5470689 | 4899 | case RELOAD_FOR_OUTPUT_ADDRESS: |
eceef4c9 | 4900 | time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; |
f5470689 R |
4901 | break; |
4902 | case RELOAD_OTHER: | |
dfe96118 R |
4903 | /* If there is no conflict in the input part, handle this |
4904 | like an output reload. */ | |
304a22dd | 4905 | if (! rld[i].in || rtx_equal_p (other_input, value)) |
f5470689 | 4906 | { |
dfe96118 | 4907 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
57850c85 | 4908 | /* Earlyclobbered outputs must conflict with inputs. */ |
09a308fe R |
4909 | if (earlyclobber_operand_p (rld[i].out)) |
4910 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
1d7254c5 | 4911 | |
f5470689 R |
4912 | break; |
4913 | } | |
dfe96118 R |
4914 | time2 = 1; |
4915 | /* RELOAD_OTHER might be live beyond instruction execution, | |
4916 | but this is not obvious when we set time2 = 1. So check | |
4917 | here if there might be a problem with the new reload | |
4918 | clobbering the register used by the RELOAD_OTHER. */ | |
4919 | if (out) | |
4920 | return 0; | |
4921 | break; | |
f5470689 | 4922 | default: |
dfe96118 | 4923 | return 0; |
f5470689 | 4924 | } |
25963977 | 4925 | if ((time1 >= time2 |
eceef4c9 | 4926 | && (! rld[i].in || rld[i].out |
304a22dd | 4927 | || ! rtx_equal_p (other_input, value))) |
eceef4c9 | 4928 | || (out && rld[reloadnum].out_reg |
701d55e8 | 4929 | && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) |
f5470689 | 4930 | return 0; |
6e684430 | 4931 | } |
6e684430 R |
4932 | } |
4933 | } | |
09a308fe R |
4934 | |
4935 | /* Earlyclobbered outputs must conflict with inputs. */ | |
4936 | if (check_earlyclobber && out && earlyclobber_operand_p (out)) | |
4937 | return 0; | |
4938 | ||
6e684430 R |
4939 | return 1; |
4940 | } | |
4941 | ||
c02cad8f BS |
4942 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
4943 | needed for the part of the insn specified by OPNUM and TYPE, | |
4944 | may be used to load VALUE into it. | |
4945 | ||
4946 | MODE is the mode in which the register is used, this is needed to | |
4947 | determine how many hard regs to test. | |
4948 | ||
4949 | Other read-only reloads with the same value do not conflict | |
40f03658 | 4950 | unless OUT is nonzero and these other reloads have to live while |
c02cad8f BS |
4951 | output reloads live. |
4952 | If OUT is CONST0_RTX, this is a special case: it means that the | |
4953 | test should not be for using register REGNO as reload register, but | |
4954 | for copying from register REGNO into the reload register. | |
4955 | ||
4956 | RELOADNUM is the number of the reload we want to load this value for; | |
4957 | a reload does not conflict with itself. | |
4958 | ||
4959 | When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with | |
4960 | reloads that load an address for the very reload we are considering. | |
4961 | ||
4962 | The caller has to make sure that there is no conflict with the return | |
4963 | register. */ | |
4964 | ||
4965 | static int | |
0c20a65f AJ |
4966 | free_for_value_p (int regno, enum machine_mode mode, int opnum, |
4967 | enum reload_type type, rtx value, rtx out, int reloadnum, | |
4968 | int ignore_address_reloads) | |
c02cad8f | 4969 | { |
66fd46b6 | 4970 | int nregs = hard_regno_nregs[regno][mode]; |
c02cad8f | 4971 | while (nregs-- > 0) |
304a22dd R |
4972 | if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type, |
4973 | value, out, reloadnum, | |
4974 | ignore_address_reloads)) | |
c02cad8f BS |
4975 | return 0; |
4976 | return 1; | |
4977 | } | |
4978 | ||
ff6534ad BS |
4979 | /* Determine whether the reload reg X overlaps any rtx'es used for |
4980 | overriding inheritance. Return nonzero if so. */ | |
4981 | ||
4982 | static int | |
0c20a65f | 4983 | conflicts_with_override (rtx x) |
ff6534ad BS |
4984 | { |
4985 | int i; | |
4986 | for (i = 0; i < n_reloads; i++) | |
4987 | if (reload_override_in[i] | |
4988 | && reg_overlap_mentioned_p (x, reload_override_in[i])) | |
4989 | return 1; | |
4990 | return 0; | |
4991 | } | |
4992 | \f | |
67e61fe7 BS |
4993 | /* Give an error message saying we failed to find a reload for INSN, |
4994 | and clear out reload R. */ | |
4995 | static void | |
0c20a65f | 4996 | failed_reload (rtx insn, int r) |
67e61fe7 BS |
4997 | { |
4998 | if (asm_noperands (PATTERN (insn)) < 0) | |
4999 | /* It's the compiler's fault. */ | |
1f978f5f | 5000 | fatal_insn ("could not find a spill register", insn); |
67e61fe7 BS |
5001 | |
5002 | /* It's the user's fault; the operand's mode and constraint | |
5003 | don't match. Disable this reload so we don't crash in final. */ | |
5004 | error_for_asm (insn, | |
5005 | "`asm' operand constraint incompatible with operand size"); | |
5006 | rld[r].in = 0; | |
5007 | rld[r].out = 0; | |
5008 | rld[r].reg_rtx = 0; | |
5009 | rld[r].optional = 1; | |
5010 | rld[r].secondary_p = 1; | |
5011 | } | |
5012 | ||
5013 | /* I is the index in SPILL_REG_RTX of the reload register we are to allocate | |
5014 | for reload R. If it's valid, get an rtx for it. Return nonzero if | |
5015 | successful. */ | |
5016 | static int | |
0c20a65f | 5017 | set_reload_reg (int i, int r) |
67e61fe7 BS |
5018 | { |
5019 | int regno; | |
5020 | rtx reg = spill_reg_rtx[i]; | |
5021 | ||
5022 | if (reg == 0 || GET_MODE (reg) != rld[r].mode) | |
5023 | spill_reg_rtx[i] = reg | |
5024 | = gen_rtx_REG (rld[r].mode, spill_regs[i]); | |
5025 | ||
5026 | regno = true_regnum (reg); | |
5027 | ||
5028 | /* Detect when the reload reg can't hold the reload mode. | |
5029 | This used to be one `if', but Sequent compiler can't handle that. */ | |
5030 | if (HARD_REGNO_MODE_OK (regno, rld[r].mode)) | |
5031 | { | |
5032 | enum machine_mode test_mode = VOIDmode; | |
5033 | if (rld[r].in) | |
5034 | test_mode = GET_MODE (rld[r].in); | |
5035 | /* If rld[r].in has VOIDmode, it means we will load it | |
5036 | in whatever mode the reload reg has: to wit, rld[r].mode. | |
5037 | We have already tested that for validity. */ | |
5038 | /* Aside from that, we need to test that the expressions | |
5039 | to reload from or into have modes which are valid for this | |
5040 | reload register. Otherwise the reload insns would be invalid. */ | |
5041 | if (! (rld[r].in != 0 && test_mode != VOIDmode | |
5042 | && ! HARD_REGNO_MODE_OK (regno, test_mode))) | |
5043 | if (! (rld[r].out != 0 | |
5044 | && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out)))) | |
5045 | { | |
5046 | /* The reg is OK. */ | |
5047 | last_spill_reg = i; | |
5048 | ||
5049 | /* Mark as in use for this insn the reload regs we use | |
5050 | for this. */ | |
5051 | mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, | |
5052 | rld[r].when_needed, rld[r].mode); | |
5053 | ||
5054 | rld[r].reg_rtx = reg; | |
5055 | reload_spill_index[r] = spill_regs[i]; | |
5056 | return 1; | |
5057 | } | |
5058 | } | |
5059 | return 0; | |
5060 | } | |
5061 | ||
32131a9c | 5062 | /* Find a spill register to use as a reload register for reload R. |
40f03658 | 5063 | LAST_RELOAD is nonzero if this is the last reload for the insn being |
32131a9c RK |
5064 | processed. |
5065 | ||
eceef4c9 | 5066 | Set rld[R].reg_rtx to the register allocated. |
32131a9c | 5067 | |
f5d8c9f4 BS |
5068 | We return 1 if successful, or 0 if we couldn't find a spill reg and |
5069 | we didn't change anything. */ | |
32131a9c RK |
5070 | |
5071 | static int | |
0c20a65f AJ |
5072 | allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r, |
5073 | int last_reload) | |
32131a9c | 5074 | { |
67e61fe7 | 5075 | int i, pass, count; |
32131a9c RK |
5076 | |
5077 | /* If we put this reload ahead, thinking it is a group, | |
5078 | then insist on finding a group. Otherwise we can grab a | |
a8fdc208 | 5079 | reg that some other reload needs. |
32131a9c RK |
5080 | (That can happen when we have a 68000 DATA_OR_FP_REG |
5081 | which is a group of data regs or one fp reg.) | |
5082 | We need not be so restrictive if there are no more reloads | |
5083 | for this insn. | |
5084 | ||
5085 | ??? Really it would be nicer to have smarter handling | |
5086 | for that kind of reg class, where a problem like this is normal. | |
5087 | Perhaps those classes should be avoided for reloading | |
5088 | by use of more alternatives. */ | |
5089 | ||
8ec450a4 | 5090 | int force_group = rld[r].nregs > 1 && ! last_reload; |
32131a9c RK |
5091 | |
5092 | /* If we want a single register and haven't yet found one, | |
5093 | take any reg in the right class and not in use. | |
5094 | If we want a consecutive group, here is where we look for it. | |
5095 | ||
5096 | We use two passes so we can first look for reload regs to | |
5097 | reuse, which are already in use for other reloads in this insn, | |
5098 | and only then use additional registers. | |
5099 | I think that maximizing reuse is needed to make sure we don't | |
5100 | run out of reload regs. Suppose we have three reloads, and | |
5101 | reloads A and B can share regs. These need two regs. | |
5102 | Suppose A and B are given different regs. | |
5103 | That leaves none for C. */ | |
5104 | for (pass = 0; pass < 2; pass++) | |
5105 | { | |
5106 | /* I is the index in spill_regs. | |
5107 | We advance it round-robin between insns to use all spill regs | |
5108 | equally, so that inherited reloads have a chance | |
f5d8c9f4 BS |
5109 | of leapfrogging each other. */ |
5110 | ||
5111 | i = last_spill_reg; | |
05d10675 | 5112 | |
a5339699 | 5113 | for (count = 0; count < n_spills; count++) |
32131a9c | 5114 | { |
eceef4c9 | 5115 | int class = (int) rld[r].class; |
03acd8f8 | 5116 | int regnum; |
32131a9c | 5117 | |
03acd8f8 BS |
5118 | i++; |
5119 | if (i >= n_spills) | |
5120 | i -= n_spills; | |
5121 | regnum = spill_regs[i]; | |
32131a9c | 5122 | |
eceef4c9 BS |
5123 | if ((reload_reg_free_p (regnum, rld[r].opnum, |
5124 | rld[r].when_needed) | |
5125 | || (rld[r].in | |
05d10675 BS |
5126 | /* We check reload_reg_used to make sure we |
5127 | don't clobber the return register. */ | |
03acd8f8 | 5128 | && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) |
c02cad8f BS |
5129 | && free_for_value_p (regnum, rld[r].mode, rld[r].opnum, |
5130 | rld[r].when_needed, rld[r].in, | |
5131 | rld[r].out, r, 1))) | |
03acd8f8 | 5132 | && TEST_HARD_REG_BIT (reg_class_contents[class], regnum) |
8ec450a4 | 5133 | && HARD_REGNO_MODE_OK (regnum, rld[r].mode) |
be7ae2a4 RK |
5134 | /* Look first for regs to share, then for unshared. But |
5135 | don't share regs used for inherited reloads; they are | |
5136 | the ones we want to preserve. */ | |
5137 | && (pass | |
5138 | || (TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
03acd8f8 | 5139 | regnum) |
be7ae2a4 | 5140 | && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, |
03acd8f8 | 5141 | regnum)))) |
32131a9c | 5142 | { |
66fd46b6 | 5143 | int nr = hard_regno_nregs[regnum][rld[r].mode]; |
32131a9c RK |
5144 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG |
5145 | (on 68000) got us two FP regs. If NR is 1, | |
5146 | we would reject both of them. */ | |
5147 | if (force_group) | |
67e61fe7 | 5148 | nr = rld[r].nregs; |
32131a9c RK |
5149 | /* If we need only one reg, we have already won. */ |
5150 | if (nr == 1) | |
5151 | { | |
5152 | /* But reject a single reg if we demand a group. */ | |
5153 | if (force_group) | |
5154 | continue; | |
5155 | break; | |
5156 | } | |
5157 | /* Otherwise check that as many consecutive regs as we need | |
f5d8c9f4 BS |
5158 | are available here. */ |
5159 | while (nr > 1) | |
5160 | { | |
5161 | int regno = regnum + nr - 1; | |
5162 | if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
5163 | && spill_reg_order[regno] >= 0 | |
5164 | && reload_reg_free_p (regno, rld[r].opnum, | |
5165 | rld[r].when_needed))) | |
5166 | break; | |
5167 | nr--; | |
5168 | } | |
32131a9c RK |
5169 | if (nr == 1) |
5170 | break; | |
5171 | } | |
5172 | } | |
5173 | ||
5174 | /* If we found something on pass 1, omit pass 2. */ | |
5175 | if (count < n_spills) | |
5176 | break; | |
5177 | } | |
1d7254c5 | 5178 | |
32131a9c | 5179 | /* We should have found a spill register by now. */ |
f5d8c9f4 | 5180 | if (count >= n_spills) |
32131a9c RK |
5181 | return 0; |
5182 | ||
f5d8c9f4 BS |
5183 | /* I is the index in SPILL_REG_RTX of the reload register we are to |
5184 | allocate. Get an rtx for it and find its register number. */ | |
32131a9c | 5185 | |
f5d8c9f4 | 5186 | return set_reload_reg (i, r); |
32131a9c RK |
5187 | } |
5188 | \f | |
67e61fe7 BS |
5189 | /* Initialize all the tables needed to allocate reload registers. |
5190 | CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX | |
5191 | is the array we use to restore the reg_rtx field for every reload. */ | |
efc9bd41 | 5192 | |
32131a9c | 5193 | static void |
0c20a65f | 5194 | choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx) |
32131a9c | 5195 | { |
67e61fe7 | 5196 | int i; |
32131a9c | 5197 | |
67e61fe7 BS |
5198 | for (i = 0; i < n_reloads; i++) |
5199 | rld[i].reg_rtx = save_reload_reg_rtx[i]; | |
32131a9c | 5200 | |
961192e1 | 5201 | memset (reload_inherited, 0, MAX_RELOADS); |
703ad42b KG |
5202 | memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx)); |
5203 | memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx)); | |
32131a9c RK |
5204 | |
5205 | CLEAR_HARD_REG_SET (reload_reg_used); | |
5206 | CLEAR_HARD_REG_SET (reload_reg_used_at_all); | |
32131a9c | 5207 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); |
893bc853 | 5208 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); |
546b63fb RK |
5209 | CLEAR_HARD_REG_SET (reload_reg_used_in_insn); |
5210 | CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); | |
32131a9c | 5211 | |
f1db3576 JL |
5212 | CLEAR_HARD_REG_SET (reg_used_in_insn); |
5213 | { | |
5214 | HARD_REG_SET tmp; | |
239a0f5b | 5215 | REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); |
f1db3576 | 5216 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b | 5217 | REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); |
f1db3576 | 5218 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b BS |
5219 | compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); |
5220 | compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); | |
f1db3576 | 5221 | } |
efc9bd41 | 5222 | |
546b63fb RK |
5223 | for (i = 0; i < reload_n_operands; i++) |
5224 | { | |
5225 | CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); | |
5226 | CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); | |
5227 | CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); | |
47c8cf91 | 5228 | CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); |
546b63fb | 5229 | CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); |
47c8cf91 | 5230 | CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); |
546b63fb | 5231 | } |
32131a9c | 5232 | |
9e3a9cf2 | 5233 | COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs); |
05d10675 | 5234 | |
67e61fe7 | 5235 | CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); |
32131a9c | 5236 | |
67e61fe7 BS |
5237 | for (i = 0; i < n_reloads; i++) |
5238 | /* If we have already decided to use a certain register, | |
5239 | don't use it in another way. */ | |
5240 | if (rld[i].reg_rtx) | |
5241 | mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, | |
5242 | rld[i].when_needed, rld[i].mode); | |
5243 | } | |
32131a9c | 5244 | |
67e61fe7 BS |
5245 | /* Assign hard reg targets for the pseudo-registers we must reload |
5246 | into hard regs for this insn. | |
5247 | Also output the instructions to copy them in and out of the hard regs. | |
5248 | ||
5249 | For machines with register classes, we are responsible for | |
5250 | finding a reload reg in the proper class. */ | |
5251 | ||
5252 | static void | |
0c20a65f | 5253 | choose_reload_regs (struct insn_chain *chain) |
67e61fe7 BS |
5254 | { |
5255 | rtx insn = chain->insn; | |
b3694847 | 5256 | int i, j; |
770ae6cc | 5257 | unsigned int max_group_size = 1; |
67e61fe7 | 5258 | enum reg_class group_class = NO_REGS; |
f5d8c9f4 | 5259 | int pass, win, inheritance; |
67e61fe7 BS |
5260 | |
5261 | rtx save_reload_reg_rtx[MAX_RELOADS]; | |
32131a9c | 5262 | |
32131a9c RK |
5263 | /* In order to be certain of getting the registers we need, |
5264 | we must sort the reloads into order of increasing register class. | |
5265 | Then our grabbing of reload registers will parallel the process | |
a8fdc208 | 5266 | that provided the reload registers. |
32131a9c RK |
5267 | |
5268 | Also note whether any of the reloads wants a consecutive group of regs. | |
5269 | If so, record the maximum size of the group desired and what | |
5270 | register class contains all the groups needed by this insn. */ | |
5271 | ||
5272 | for (j = 0; j < n_reloads; j++) | |
5273 | { | |
5274 | reload_order[j] = j; | |
5275 | reload_spill_index[j] = -1; | |
5276 | ||
8ec450a4 | 5277 | if (rld[j].nregs > 1) |
32131a9c | 5278 | { |
8ec450a4 | 5279 | max_group_size = MAX (rld[j].nregs, max_group_size); |
770ae6cc | 5280 | group_class |
8e2e89f7 | 5281 | = reg_class_superunion[(int) rld[j].class][(int) group_class]; |
32131a9c RK |
5282 | } |
5283 | ||
eceef4c9 | 5284 | save_reload_reg_rtx[j] = rld[j].reg_rtx; |
32131a9c RK |
5285 | } |
5286 | ||
5287 | if (n_reloads > 1) | |
5288 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
5289 | ||
58b1581b RS |
5290 | /* If -O, try first with inheritance, then turning it off. |
5291 | If not -O, don't do inheritance. | |
5292 | Using inheritance when not optimizing leads to paradoxes | |
5293 | with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves | |
5294 | because one side of the comparison might be inherited. */ | |
f5d8c9f4 | 5295 | win = 0; |
58b1581b | 5296 | for (inheritance = optimize > 0; inheritance >= 0; inheritance--) |
32131a9c | 5297 | { |
67e61fe7 BS |
5298 | choose_reload_regs_init (chain, save_reload_reg_rtx); |
5299 | ||
32131a9c RK |
5300 | /* Process the reloads in order of preference just found. |
5301 | Beyond this point, subregs can be found in reload_reg_rtx. | |
5302 | ||
770ae6cc RK |
5303 | This used to look for an existing reloaded home for all of the |
5304 | reloads, and only then perform any new reloads. But that could lose | |
5305 | if the reloads were done out of reg-class order because a later | |
5306 | reload with a looser constraint might have an old home in a register | |
5307 | needed by an earlier reload with a tighter constraint. | |
32131a9c RK |
5308 | |
5309 | To solve this, we make two passes over the reloads, in the order | |
5310 | described above. In the first pass we try to inherit a reload | |
5311 | from a previous insn. If there is a later reload that needs a | |
5312 | class that is a proper subset of the class being processed, we must | |
5313 | also allocate a spill register during the first pass. | |
5314 | ||
5315 | Then make a second pass over the reloads to allocate any reloads | |
5316 | that haven't been given registers yet. */ | |
5317 | ||
5318 | for (j = 0; j < n_reloads; j++) | |
5319 | { | |
b3694847 | 5320 | int r = reload_order[j]; |
8593b745 | 5321 | rtx search_equiv = NULL_RTX; |
32131a9c RK |
5322 | |
5323 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 BS |
5324 | if (rld[r].out == 0 && rld[r].in == 0 |
5325 | && ! rld[r].secondary_p) | |
32131a9c RK |
5326 | continue; |
5327 | ||
b29514ee | 5328 | /* If find_reloads chose to use reload_in or reload_out as a reload |
b080c137 RK |
5329 | register, we don't need to chose one. Otherwise, try even if it |
5330 | found one since we might save an insn if we find the value lying | |
b29514ee R |
5331 | around. |
5332 | Try also when reload_in is a pseudo without a hard reg. */ | |
eceef4c9 BS |
5333 | if (rld[r].in != 0 && rld[r].reg_rtx != 0 |
5334 | && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) | |
5335 | || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) | |
5336 | && GET_CODE (rld[r].in) != MEM | |
5337 | && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) | |
32131a9c RK |
5338 | continue; |
5339 | ||
5340 | #if 0 /* No longer needed for correct operation. | |
5341 | It might give better code, or might not; worth an experiment? */ | |
5342 | /* If this is an optional reload, we can't inherit from earlier insns | |
5343 | until we are sure that any non-optional reloads have been allocated. | |
5344 | The following code takes advantage of the fact that optional reloads | |
5345 | are at the end of reload_order. */ | |
eceef4c9 | 5346 | if (rld[r].optional != 0) |
32131a9c | 5347 | for (i = 0; i < j; i++) |
eceef4c9 BS |
5348 | if ((rld[reload_order[i]].out != 0 |
5349 | || rld[reload_order[i]].in != 0 | |
5350 | || rld[reload_order[i]].secondary_p) | |
5351 | && ! rld[reload_order[i]].optional | |
5352 | && rld[reload_order[i]].reg_rtx == 0) | |
f5d8c9f4 | 5353 | allocate_reload_reg (chain, reload_order[i], 0); |
32131a9c RK |
5354 | #endif |
5355 | ||
5356 | /* First see if this pseudo is already available as reloaded | |
5357 | for a previous insn. We cannot try to inherit for reloads | |
5358 | that are smaller than the maximum number of registers needed | |
5359 | for groups unless the register we would allocate cannot be used | |
5360 | for the groups. | |
5361 | ||
5362 | We could check here to see if this is a secondary reload for | |
5363 | an object that is already in a register of the desired class. | |
5364 | This would avoid the need for the secondary reload register. | |
5365 | But this is complex because we can't easily determine what | |
b080c137 RK |
5366 | objects might want to be loaded via this reload. So let a |
5367 | register be allocated here. In `emit_reload_insns' we suppress | |
5368 | one of the loads in the case described above. */ | |
32131a9c RK |
5369 | |
5370 | if (inheritance) | |
5371 | { | |
ddef6bc7 | 5372 | int byte = 0; |
b3694847 | 5373 | int regno = -1; |
6a651371 | 5374 | enum machine_mode mode = VOIDmode; |
32131a9c | 5375 | |
eceef4c9 | 5376 | if (rld[r].in == 0) |
32131a9c | 5377 | ; |
eceef4c9 | 5378 | else if (GET_CODE (rld[r].in) == REG) |
db660765 | 5379 | { |
eceef4c9 BS |
5380 | regno = REGNO (rld[r].in); |
5381 | mode = GET_MODE (rld[r].in); | |
db660765 | 5382 | } |
eceef4c9 | 5383 | else if (GET_CODE (rld[r].in_reg) == REG) |
db660765 | 5384 | { |
eceef4c9 BS |
5385 | regno = REGNO (rld[r].in_reg); |
5386 | mode = GET_MODE (rld[r].in_reg); | |
db660765 | 5387 | } |
eceef4c9 BS |
5388 | else if (GET_CODE (rld[r].in_reg) == SUBREG |
5389 | && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG) | |
b60a8416 | 5390 | { |
ddef6bc7 | 5391 | byte = SUBREG_BYTE (rld[r].in_reg); |
eceef4c9 | 5392 | regno = REGNO (SUBREG_REG (rld[r].in_reg)); |
cb2afeb3 | 5393 | if (regno < FIRST_PSEUDO_REGISTER) |
ddef6bc7 | 5394 | regno = subreg_regno (rld[r].in_reg); |
eceef4c9 | 5395 | mode = GET_MODE (rld[r].in_reg); |
cb2afeb3 R |
5396 | } |
5397 | #ifdef AUTO_INC_DEC | |
eceef4c9 BS |
5398 | else if ((GET_CODE (rld[r].in_reg) == PRE_INC |
5399 | || GET_CODE (rld[r].in_reg) == PRE_DEC | |
5400 | || GET_CODE (rld[r].in_reg) == POST_INC | |
5401 | || GET_CODE (rld[r].in_reg) == POST_DEC) | |
5402 | && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG) | |
cb2afeb3 | 5403 | { |
eceef4c9 BS |
5404 | regno = REGNO (XEXP (rld[r].in_reg, 0)); |
5405 | mode = GET_MODE (XEXP (rld[r].in_reg, 0)); | |
5406 | rld[r].out = rld[r].in; | |
b60a8416 | 5407 | } |
cb2afeb3 | 5408 | #endif |
32131a9c RK |
5409 | #if 0 |
5410 | /* This won't work, since REGNO can be a pseudo reg number. | |
5411 | Also, it takes much more hair to keep track of all the things | |
5412 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
eceef4c9 BS |
5413 | else if (GET_CODE (rld[r].in) == SUBREG |
5414 | && GET_CODE (SUBREG_REG (rld[r].in)) == REG) | |
ddef6bc7 | 5415 | regno = subreg_regno (rld[r].in); |
32131a9c RK |
5416 | #endif |
5417 | ||
5418 | if (regno >= 0 && reg_last_reload_reg[regno] != 0) | |
5419 | { | |
eceef4c9 | 5420 | enum reg_class class = rld[r].class, last_class; |
cb2afeb3 | 5421 | rtx last_reg = reg_last_reload_reg[regno]; |
02188693 | 5422 | enum machine_mode need_mode; |
05d10675 | 5423 | |
ddef6bc7 JJ |
5424 | i = REGNO (last_reg); |
5425 | i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode); | |
cb2afeb3 | 5426 | last_class = REGNO_REG_CLASS (i); |
02188693 | 5427 | |
ddef6bc7 | 5428 | if (byte == 0) |
ce701d1b BS |
5429 | need_mode = mode; |
5430 | else | |
5431 | need_mode | |
ddef6bc7 | 5432 | = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte, |
ce701d1b | 5433 | GET_MODE_CLASS (mode)); |
02188693 | 5434 | |
c9d8a813 | 5435 | if ( |
cff9f8d5 AH |
5436 | #ifdef CANNOT_CHANGE_MODE_CLASS |
5437 | (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg), | |
5438 | need_mode) | |
1fe668e5 | 5439 | && |
cff9f8d5 | 5440 | #endif |
c9d8a813 | 5441 | (GET_MODE_SIZE (GET_MODE (last_reg)) |
02188693 | 5442 | >= GET_MODE_SIZE (need_mode)) |
cff9f8d5 AH |
5443 | #ifdef CANNOT_CHANGE_MODE_CLASS |
5444 | ) | |
c9d8a813 | 5445 | #endif |
cb2afeb3 | 5446 | && reg_reloaded_contents[i] == regno |
e6e52be0 | 5447 | && TEST_HARD_REG_BIT (reg_reloaded_valid, i) |
8ec450a4 | 5448 | && HARD_REGNO_MODE_OK (i, rld[r].mode) |
cb2afeb3 R |
5449 | && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i) |
5450 | /* Even if we can't use this register as a reload | |
5451 | register, we might use it for reload_override_in, | |
5452 | if copying it to the desired class is cheap | |
5453 | enough. */ | |
e56b4594 | 5454 | || ((REGISTER_MOVE_COST (mode, last_class, class) |
cb2afeb3 R |
5455 | < MEMORY_MOVE_COST (mode, class, 1)) |
5456 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
5457 | && (SECONDARY_INPUT_RELOAD_CLASS (class, mode, | |
5458 | last_reg) | |
5459 | == NO_REGS) | |
5460 | #endif | |
5461 | #ifdef SECONDARY_MEMORY_NEEDED | |
5462 | && ! SECONDARY_MEMORY_NEEDED (last_class, class, | |
5463 | mode) | |
5464 | #endif | |
5465 | )) | |
5466 | ||
8ec450a4 | 5467 | && (rld[r].nregs == max_group_size |
32131a9c | 5468 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], |
e6e52be0 | 5469 | i)) |
c02cad8f BS |
5470 | && free_for_value_p (i, rld[r].mode, rld[r].opnum, |
5471 | rld[r].when_needed, rld[r].in, | |
5472 | const0_rtx, r, 1)) | |
32131a9c RK |
5473 | { |
5474 | /* If a group is needed, verify that all the subsequent | |
0f41302f | 5475 | registers still have their values intact. */ |
66fd46b6 | 5476 | int nr = hard_regno_nregs[i][rld[r].mode]; |
32131a9c RK |
5477 | int k; |
5478 | ||
5479 | for (k = 1; k < nr; k++) | |
e6e52be0 R |
5480 | if (reg_reloaded_contents[i + k] != regno |
5481 | || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) | |
32131a9c RK |
5482 | break; |
5483 | ||
5484 | if (k == nr) | |
5485 | { | |
c74fa651 | 5486 | int i1; |
eb4d554e | 5487 | int bad_for_class; |
c74fa651 | 5488 | |
cb2afeb3 R |
5489 | last_reg = (GET_MODE (last_reg) == mode |
5490 | ? last_reg : gen_rtx_REG (mode, i)); | |
5491 | ||
eb4d554e GK |
5492 | bad_for_class = 0; |
5493 | for (k = 0; k < nr; k++) | |
5494 | bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], | |
5495 | i+k); | |
5496 | ||
c74fa651 RS |
5497 | /* We found a register that contains the |
5498 | value we need. If this register is the | |
5499 | same as an `earlyclobber' operand of the | |
5500 | current insn, just mark it as a place to | |
5501 | reload from since we can't use it as the | |
5502 | reload register itself. */ | |
5503 | ||
5504 | for (i1 = 0; i1 < n_earlyclobbers; i1++) | |
5505 | if (reg_overlap_mentioned_for_reload_p | |
5506 | (reg_last_reload_reg[regno], | |
5507 | reload_earlyclobbers[i1])) | |
5508 | break; | |
5509 | ||
8908158d | 5510 | if (i1 != n_earlyclobbers |
c02cad8f BS |
5511 | || ! (free_for_value_p (i, rld[r].mode, |
5512 | rld[r].opnum, | |
5513 | rld[r].when_needed, rld[r].in, | |
5514 | rld[r].out, r, 1)) | |
e6e52be0 | 5515 | /* Don't use it if we'd clobber a pseudo reg. */ |
f1db3576 | 5516 | || (TEST_HARD_REG_BIT (reg_used_in_insn, i) |
eceef4c9 | 5517 | && rld[r].out |
e6e52be0 | 5518 | && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) |
0c7f2259 | 5519 | /* Don't clobber the frame pointer. */ |
1d7254c5 | 5520 | || (i == HARD_FRAME_POINTER_REGNUM |
2f460a0a | 5521 | && frame_pointer_needed |
1d7254c5 | 5522 | && rld[r].out) |
8908158d RS |
5523 | /* Don't really use the inherited spill reg |
5524 | if we need it wider than we've got it. */ | |
8ec450a4 | 5525 | || (GET_MODE_SIZE (rld[r].mode) |
b29514ee | 5526 | > GET_MODE_SIZE (mode)) |
eb4d554e | 5527 | || bad_for_class |
cb2afeb3 | 5528 | |
b29514ee R |
5529 | /* If find_reloads chose reload_out as reload |
5530 | register, stay with it - that leaves the | |
5531 | inherited register for subsequent reloads. */ | |
eceef4c9 | 5532 | || (rld[r].out && rld[r].reg_rtx |
67e61fe7 | 5533 | && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) |
cb2afeb3 | 5534 | { |
4c3a2649 BS |
5535 | if (! rld[r].optional) |
5536 | { | |
5537 | reload_override_in[r] = last_reg; | |
5538 | reload_inheritance_insn[r] | |
5539 | = reg_reloaded_insn[i]; | |
5540 | } | |
cb2afeb3 | 5541 | } |
c74fa651 RS |
5542 | else |
5543 | { | |
54c40e68 | 5544 | int k; |
c74fa651 RS |
5545 | /* We can use this as a reload reg. */ |
5546 | /* Mark the register as in use for this part of | |
5547 | the insn. */ | |
e6e52be0 | 5548 | mark_reload_reg_in_use (i, |
eceef4c9 BS |
5549 | rld[r].opnum, |
5550 | rld[r].when_needed, | |
8ec450a4 | 5551 | rld[r].mode); |
eceef4c9 | 5552 | rld[r].reg_rtx = last_reg; |
c74fa651 RS |
5553 | reload_inherited[r] = 1; |
5554 | reload_inheritance_insn[r] | |
5555 | = reg_reloaded_insn[i]; | |
5556 | reload_spill_index[r] = i; | |
54c40e68 RS |
5557 | for (k = 0; k < nr; k++) |
5558 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, | |
e6e52be0 | 5559 | i + k); |
c74fa651 | 5560 | } |
32131a9c RK |
5561 | } |
5562 | } | |
5563 | } | |
5564 | } | |
5565 | ||
5566 | /* Here's another way to see if the value is already lying around. */ | |
5567 | if (inheritance | |
eceef4c9 | 5568 | && rld[r].in != 0 |
32131a9c | 5569 | && ! reload_inherited[r] |
eceef4c9 BS |
5570 | && rld[r].out == 0 |
5571 | && (CONSTANT_P (rld[r].in) | |
5572 | || GET_CODE (rld[r].in) == PLUS | |
5573 | || GET_CODE (rld[r].in) == REG | |
5574 | || GET_CODE (rld[r].in) == MEM) | |
8ec450a4 | 5575 | && (rld[r].nregs == max_group_size |
eceef4c9 BS |
5576 | || ! reg_classes_intersect_p (rld[r].class, group_class))) |
5577 | search_equiv = rld[r].in; | |
8593b745 R |
5578 | /* If this is an output reload from a simple move insn, look |
5579 | if an equivalence for the input is available. */ | |
eceef4c9 | 5580 | else if (inheritance && rld[r].in == 0 && rld[r].out != 0) |
8593b745 R |
5581 | { |
5582 | rtx set = single_set (insn); | |
5583 | ||
5584 | if (set | |
eceef4c9 | 5585 | && rtx_equal_p (rld[r].out, SET_DEST (set)) |
8593b745 R |
5586 | && CONSTANT_P (SET_SRC (set))) |
5587 | search_equiv = SET_SRC (set); | |
5588 | } | |
5589 | ||
5590 | if (search_equiv) | |
32131a9c | 5591 | { |
b3694847 | 5592 | rtx equiv |
eceef4c9 | 5593 | = find_equiv_reg (search_equiv, insn, rld[r].class, |
9714cf43 | 5594 | -1, NULL, 0, rld[r].mode); |
f428f252 | 5595 | int regno = 0; |
32131a9c RK |
5596 | |
5597 | if (equiv != 0) | |
5598 | { | |
5599 | if (GET_CODE (equiv) == REG) | |
5600 | regno = REGNO (equiv); | |
5601 | else if (GET_CODE (equiv) == SUBREG) | |
5602 | { | |
f8a9e02b RK |
5603 | /* This must be a SUBREG of a hard register. |
5604 | Make a new REG since this might be used in an | |
5605 | address and not all machines support SUBREGs | |
5606 | there. */ | |
ddef6bc7 | 5607 | regno = subreg_regno (equiv); |
8ec450a4 | 5608 | equiv = gen_rtx_REG (rld[r].mode, regno); |
32131a9c RK |
5609 | } |
5610 | else | |
5611 | abort (); | |
5612 | } | |
5613 | ||
5614 | /* If we found a spill reg, reject it unless it is free | |
5615 | and of the desired class. */ | |
f58d8c95 JW |
5616 | if (equiv != 0) |
5617 | { | |
5618 | int regs_used = 0; | |
5619 | int bad_for_class = 0; | |
5620 | int max_regno = regno + rld[r].nregs; | |
5621 | ||
5622 | for (i = regno; i < max_regno; i++) | |
5623 | { | |
5624 | regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
5625 | i); | |
0c20a65f | 5626 | bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], |
f58d8c95 JW |
5627 | i); |
5628 | } | |
5629 | ||
5630 | if ((regs_used | |
c02cad8f BS |
5631 | && ! free_for_value_p (regno, rld[r].mode, |
5632 | rld[r].opnum, rld[r].when_needed, | |
5633 | rld[r].in, rld[r].out, r, 1)) | |
f58d8c95 JW |
5634 | || bad_for_class) |
5635 | equiv = 0; | |
5636 | } | |
32131a9c | 5637 | |
8ec450a4 | 5638 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) |
32131a9c RK |
5639 | equiv = 0; |
5640 | ||
5641 | /* We found a register that contains the value we need. | |
5642 | If this register is the same as an `earlyclobber' operand | |
5643 | of the current insn, just mark it as a place to reload from | |
5644 | since we can't use it as the reload register itself. */ | |
5645 | ||
5646 | if (equiv != 0) | |
5647 | for (i = 0; i < n_earlyclobbers; i++) | |
bfa30b22 RK |
5648 | if (reg_overlap_mentioned_for_reload_p (equiv, |
5649 | reload_earlyclobbers[i])) | |
32131a9c | 5650 | { |
4c3a2649 BS |
5651 | if (! rld[r].optional) |
5652 | reload_override_in[r] = equiv; | |
32131a9c RK |
5653 | equiv = 0; |
5654 | break; | |
5655 | } | |
5656 | ||
3c785e47 R |
5657 | /* If the equiv register we have found is explicitly clobbered |
5658 | in the current insn, it depends on the reload type if we | |
5659 | can use it, use it for reload_override_in, or not at all. | |
5660 | In particular, we then can't use EQUIV for a | |
5661 | RELOAD_FOR_OUTPUT_ADDRESS reload. */ | |
32131a9c | 5662 | |
9532e31f | 5663 | if (equiv != 0) |
174fa2c4 | 5664 | { |
9532e31f BS |
5665 | if (regno_clobbered_p (regno, insn, rld[r].mode, 0)) |
5666 | switch (rld[r].when_needed) | |
5667 | { | |
5668 | case RELOAD_FOR_OTHER_ADDRESS: | |
5669 | case RELOAD_FOR_INPADDR_ADDRESS: | |
5670 | case RELOAD_FOR_INPUT_ADDRESS: | |
5671 | case RELOAD_FOR_OPADDR_ADDR: | |
5672 | break; | |
5673 | case RELOAD_OTHER: | |
5674 | case RELOAD_FOR_INPUT: | |
5675 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5676 | if (! rld[r].optional) | |
5677 | reload_override_in[r] = equiv; | |
5678 | /* Fall through. */ | |
5679 | default: | |
5680 | equiv = 0; | |
5681 | break; | |
5682 | } | |
5683 | else if (regno_clobbered_p (regno, insn, rld[r].mode, 1)) | |
5684 | switch (rld[r].when_needed) | |
5685 | { | |
5686 | case RELOAD_FOR_OTHER_ADDRESS: | |
5687 | case RELOAD_FOR_INPADDR_ADDRESS: | |
5688 | case RELOAD_FOR_INPUT_ADDRESS: | |
5689 | case RELOAD_FOR_OPADDR_ADDR: | |
5690 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5691 | case RELOAD_FOR_INPUT: | |
5692 | break; | |
5693 | case RELOAD_OTHER: | |
5694 | if (! rld[r].optional) | |
5695 | reload_override_in[r] = equiv; | |
5696 | /* Fall through. */ | |
5697 | default: | |
5698 | equiv = 0; | |
5699 | break; | |
5700 | } | |
32131a9c RK |
5701 | } |
5702 | ||
5703 | /* If we found an equivalent reg, say no code need be generated | |
5704 | to load it, and use it as our reload reg. */ | |
a6a2274a KH |
5705 | if (equiv != 0 |
5706 | && (regno != HARD_FRAME_POINTER_REGNUM | |
2f460a0a | 5707 | || !frame_pointer_needed)) |
32131a9c | 5708 | { |
66fd46b6 | 5709 | int nr = hard_regno_nregs[regno][rld[r].mode]; |
100338df | 5710 | int k; |
eceef4c9 | 5711 | rld[r].reg_rtx = equiv; |
32131a9c | 5712 | reload_inherited[r] = 1; |
100338df | 5713 | |
91d7e7ac R |
5714 | /* If reg_reloaded_valid is not set for this register, |
5715 | there might be a stale spill_reg_store lying around. | |
5716 | We must clear it, since otherwise emit_reload_insns | |
5717 | might delete the store. */ | |
5718 | if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) | |
5719 | spill_reg_store[regno] = NULL_RTX; | |
100338df JL |
5720 | /* If any of the hard registers in EQUIV are spill |
5721 | registers, mark them as in use for this insn. */ | |
5722 | for (k = 0; k < nr; k++) | |
be7ae2a4 | 5723 | { |
100338df JL |
5724 | i = spill_reg_order[regno + k]; |
5725 | if (i >= 0) | |
5726 | { | |
eceef4c9 BS |
5727 | mark_reload_reg_in_use (regno, rld[r].opnum, |
5728 | rld[r].when_needed, | |
8ec450a4 | 5729 | rld[r].mode); |
100338df JL |
5730 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, |
5731 | regno + k); | |
5732 | } | |
be7ae2a4 | 5733 | } |
32131a9c RK |
5734 | } |
5735 | } | |
5736 | ||
5737 | /* If we found a register to use already, or if this is an optional | |
5738 | reload, we are done. */ | |
eceef4c9 | 5739 | if (rld[r].reg_rtx != 0 || rld[r].optional != 0) |
32131a9c RK |
5740 | continue; |
5741 | ||
1d7254c5 KH |
5742 | #if 0 |
5743 | /* No longer needed for correct operation. Might or might | |
5744 | not give better code on the average. Want to experiment? */ | |
32131a9c RK |
5745 | |
5746 | /* See if there is a later reload that has a class different from our | |
5747 | class that intersects our class or that requires less register | |
5748 | than our reload. If so, we must allocate a register to this | |
5749 | reload now, since that reload might inherit a previous reload | |
5750 | and take the only available register in our class. Don't do this | |
5751 | for optional reloads since they will force all previous reloads | |
5752 | to be allocated. Also don't do this for reloads that have been | |
5753 | turned off. */ | |
5754 | ||
5755 | for (i = j + 1; i < n_reloads; i++) | |
5756 | { | |
5757 | int s = reload_order[i]; | |
5758 | ||
eceef4c9 BS |
5759 | if ((rld[s].in == 0 && rld[s].out == 0 |
5760 | && ! rld[s].secondary_p) | |
5761 | || rld[s].optional) | |
32131a9c RK |
5762 | continue; |
5763 | ||
eceef4c9 BS |
5764 | if ((rld[s].class != rld[r].class |
5765 | && reg_classes_intersect_p (rld[r].class, | |
5766 | rld[s].class)) | |
8ec450a4 | 5767 | || rld[s].nregs < rld[r].nregs) |
05d10675 | 5768 | break; |
32131a9c RK |
5769 | } |
5770 | ||
5771 | if (i == n_reloads) | |
5772 | continue; | |
5773 | ||
f5d8c9f4 | 5774 | allocate_reload_reg (chain, r, j == n_reloads - 1); |
32131a9c RK |
5775 | #endif |
5776 | } | |
5777 | ||
5778 | /* Now allocate reload registers for anything non-optional that | |
5779 | didn't get one yet. */ | |
5780 | for (j = 0; j < n_reloads; j++) | |
5781 | { | |
b3694847 | 5782 | int r = reload_order[j]; |
32131a9c RK |
5783 | |
5784 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 | 5785 | if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) |
32131a9c RK |
5786 | continue; |
5787 | ||
5788 | /* Skip reloads that already have a register allocated or are | |
0f41302f | 5789 | optional. */ |
eceef4c9 | 5790 | if (rld[r].reg_rtx != 0 || rld[r].optional) |
32131a9c RK |
5791 | continue; |
5792 | ||
f5d8c9f4 | 5793 | if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) |
32131a9c RK |
5794 | break; |
5795 | } | |
5796 | ||
5797 | /* If that loop got all the way, we have won. */ | |
5798 | if (j == n_reloads) | |
f5d8c9f4 BS |
5799 | { |
5800 | win = 1; | |
5801 | break; | |
5802 | } | |
32131a9c | 5803 | |
32131a9c | 5804 | /* Loop around and try without any inheritance. */ |
32131a9c RK |
5805 | } |
5806 | ||
f5d8c9f4 BS |
5807 | if (! win) |
5808 | { | |
5809 | /* First undo everything done by the failed attempt | |
5810 | to allocate with inheritance. */ | |
5811 | choose_reload_regs_init (chain, save_reload_reg_rtx); | |
5812 | ||
5813 | /* Some sanity tests to verify that the reloads found in the first | |
5814 | pass are identical to the ones we have now. */ | |
5815 | if (chain->n_reloads != n_reloads) | |
5816 | abort (); | |
5817 | ||
5818 | for (i = 0; i < n_reloads; i++) | |
5819 | { | |
5820 | if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) | |
5821 | continue; | |
5822 | if (chain->rld[i].when_needed != rld[i].when_needed) | |
5823 | abort (); | |
5824 | for (j = 0; j < n_spills; j++) | |
5825 | if (spill_regs[j] == chain->rld[i].regno) | |
5826 | if (! set_reload_reg (j, i)) | |
5827 | failed_reload (chain->insn, i); | |
5828 | } | |
5829 | } | |
5830 | ||
32131a9c RK |
5831 | /* If we thought we could inherit a reload, because it seemed that |
5832 | nothing else wanted the same reload register earlier in the insn, | |
cb2afeb3 R |
5833 | verify that assumption, now that all reloads have been assigned. |
5834 | Likewise for reloads where reload_override_in has been set. */ | |
32131a9c | 5835 | |
cb2afeb3 R |
5836 | /* If doing expensive optimizations, do one preliminary pass that doesn't |
5837 | cancel any inheritance, but removes reloads that have been needed only | |
5838 | for reloads that we know can be inherited. */ | |
5839 | for (pass = flag_expensive_optimizations; pass >= 0; pass--) | |
32131a9c | 5840 | { |
cb2afeb3 | 5841 | for (j = 0; j < n_reloads; j++) |
029b38ff | 5842 | { |
b3694847 | 5843 | int r = reload_order[j]; |
cb2afeb3 | 5844 | rtx check_reg; |
eceef4c9 BS |
5845 | if (reload_inherited[r] && rld[r].reg_rtx) |
5846 | check_reg = rld[r].reg_rtx; | |
cb2afeb3 R |
5847 | else if (reload_override_in[r] |
5848 | && (GET_CODE (reload_override_in[r]) == REG | |
05d10675 | 5849 | || GET_CODE (reload_override_in[r]) == SUBREG)) |
cb2afeb3 R |
5850 | check_reg = reload_override_in[r]; |
5851 | else | |
5852 | continue; | |
c02cad8f BS |
5853 | if (! free_for_value_p (true_regnum (check_reg), rld[r].mode, |
5854 | rld[r].opnum, rld[r].when_needed, rld[r].in, | |
5855 | (reload_inherited[r] | |
5856 | ? rld[r].out : const0_rtx), | |
5857 | r, 1)) | |
029b38ff | 5858 | { |
cb2afeb3 R |
5859 | if (pass) |
5860 | continue; | |
5861 | reload_inherited[r] = 0; | |
5862 | reload_override_in[r] = 0; | |
029b38ff | 5863 | } |
cb2afeb3 R |
5864 | /* If we can inherit a RELOAD_FOR_INPUT, or can use a |
5865 | reload_override_in, then we do not need its related | |
5866 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; | |
5867 | likewise for other reload types. | |
5868 | We handle this by removing a reload when its only replacement | |
5869 | is mentioned in reload_in of the reload we are going to inherit. | |
5870 | A special case are auto_inc expressions; even if the input is | |
5871 | inherited, we still need the address for the output. We can | |
fe92fe26 | 5872 | recognize them because they have RELOAD_OUT set to RELOAD_IN. |
eaec9b3d | 5873 | If we succeeded removing some reload and we are doing a preliminary |
cb2afeb3 R |
5874 | pass just to remove such reloads, make another pass, since the |
5875 | removal of one reload might allow us to inherit another one. */ | |
eceef4c9 BS |
5876 | else if (rld[r].in |
5877 | && rld[r].out != rld[r].in | |
5878 | && remove_address_replacements (rld[r].in) && pass) | |
cb2afeb3 | 5879 | pass = 2; |
32131a9c RK |
5880 | } |
5881 | } | |
5882 | ||
5883 | /* Now that reload_override_in is known valid, | |
5884 | actually override reload_in. */ | |
5885 | for (j = 0; j < n_reloads; j++) | |
5886 | if (reload_override_in[j]) | |
eceef4c9 | 5887 | rld[j].in = reload_override_in[j]; |
32131a9c | 5888 | |
272d0bee | 5889 | /* If this reload won't be done because it has been canceled or is |
32131a9c RK |
5890 | optional and not inherited, clear reload_reg_rtx so other |
5891 | routines (such as subst_reloads) don't get confused. */ | |
5892 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
5893 | if (rld[j].reg_rtx != 0 |
5894 | && ((rld[j].optional && ! reload_inherited[j]) | |
5895 | || (rld[j].in == 0 && rld[j].out == 0 | |
5896 | && ! rld[j].secondary_p))) | |
be7ae2a4 | 5897 | { |
eceef4c9 | 5898 | int regno = true_regnum (rld[j].reg_rtx); |
be7ae2a4 RK |
5899 | |
5900 | if (spill_reg_order[regno] >= 0) | |
eceef4c9 | 5901 | clear_reload_reg_in_use (regno, rld[j].opnum, |
8ec450a4 | 5902 | rld[j].when_needed, rld[j].mode); |
eceef4c9 | 5903 | rld[j].reg_rtx = 0; |
c0029be5 | 5904 | reload_spill_index[j] = -1; |
be7ae2a4 | 5905 | } |
32131a9c RK |
5906 | |
5907 | /* Record which pseudos and which spill regs have output reloads. */ | |
5908 | for (j = 0; j < n_reloads; j++) | |
5909 | { | |
b3694847 | 5910 | int r = reload_order[j]; |
32131a9c RK |
5911 | |
5912 | i = reload_spill_index[r]; | |
5913 | ||
e6e52be0 | 5914 | /* I is nonneg if this reload uses a register. |
eceef4c9 | 5915 | If rld[r].reg_rtx is 0, this is an optional reload |
32131a9c | 5916 | that we opted to ignore. */ |
eceef4c9 BS |
5917 | if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG |
5918 | && rld[r].reg_rtx != 0) | |
32131a9c | 5919 | { |
b3694847 | 5920 | int nregno = REGNO (rld[r].out_reg); |
372e033b RS |
5921 | int nr = 1; |
5922 | ||
5923 | if (nregno < FIRST_PSEUDO_REGISTER) | |
66fd46b6 | 5924 | nr = hard_regno_nregs[nregno][rld[r].mode]; |
32131a9c RK |
5925 | |
5926 | while (--nr >= 0) | |
372e033b RS |
5927 | reg_has_output_reload[nregno + nr] = 1; |
5928 | ||
5929 | if (i >= 0) | |
32131a9c | 5930 | { |
66fd46b6 | 5931 | nr = hard_regno_nregs[i][rld[r].mode]; |
372e033b | 5932 | while (--nr >= 0) |
e6e52be0 | 5933 | SET_HARD_REG_BIT (reg_is_output_reload, i + nr); |
32131a9c RK |
5934 | } |
5935 | ||
eceef4c9 BS |
5936 | if (rld[r].when_needed != RELOAD_OTHER |
5937 | && rld[r].when_needed != RELOAD_FOR_OUTPUT | |
5938 | && rld[r].when_needed != RELOAD_FOR_INSN) | |
32131a9c RK |
5939 | abort (); |
5940 | } | |
5941 | } | |
5942 | } | |
cb2afeb3 R |
5943 | |
5944 | /* Deallocate the reload register for reload R. This is called from | |
5945 | remove_address_replacements. */ | |
1d813780 | 5946 | |
cb2afeb3 | 5947 | void |
0c20a65f | 5948 | deallocate_reload_reg (int r) |
cb2afeb3 R |
5949 | { |
5950 | int regno; | |
5951 | ||
eceef4c9 | 5952 | if (! rld[r].reg_rtx) |
cb2afeb3 | 5953 | return; |
eceef4c9 BS |
5954 | regno = true_regnum (rld[r].reg_rtx); |
5955 | rld[r].reg_rtx = 0; | |
cb2afeb3 | 5956 | if (spill_reg_order[regno] >= 0) |
eceef4c9 | 5957 | clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, |
8ec450a4 | 5958 | rld[r].mode); |
cb2afeb3 R |
5959 | reload_spill_index[r] = -1; |
5960 | } | |
32131a9c | 5961 | \f |
40f03658 | 5962 | /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two |
546b63fb RK |
5963 | reloads of the same item for fear that we might not have enough reload |
5964 | registers. However, normally they will get the same reload register | |
05d10675 | 5965 | and hence actually need not be loaded twice. |
546b63fb RK |
5966 | |
5967 | Here we check for the most common case of this phenomenon: when we have | |
5968 | a number of reloads for the same object, each of which were allocated | |
5969 | the same reload_reg_rtx, that reload_reg_rtx is not used for any other | |
5970 | reload, and is not modified in the insn itself. If we find such, | |
5971 | merge all the reloads and set the resulting reload to RELOAD_OTHER. | |
5972 | This will not increase the number of spill registers needed and will | |
5973 | prevent redundant code. */ | |
5974 | ||
546b63fb | 5975 | static void |
0c20a65f | 5976 | merge_assigned_reloads (rtx insn) |
546b63fb RK |
5977 | { |
5978 | int i, j; | |
5979 | ||
5980 | /* Scan all the reloads looking for ones that only load values and | |
5981 | are not already RELOAD_OTHER and ones whose reload_reg_rtx are | |
5982 | assigned and not modified by INSN. */ | |
5983 | ||
5984 | for (i = 0; i < n_reloads; i++) | |
5985 | { | |
d668e863 R |
5986 | int conflicting_input = 0; |
5987 | int max_input_address_opnum = -1; | |
5988 | int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; | |
5989 | ||
eceef4c9 BS |
5990 | if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER |
5991 | || rld[i].out != 0 || rld[i].reg_rtx == 0 | |
5992 | || reg_set_p (rld[i].reg_rtx, insn)) | |
546b63fb RK |
5993 | continue; |
5994 | ||
5995 | /* Look at all other reloads. Ensure that the only use of this | |
5996 | reload_reg_rtx is in a reload that just loads the same value | |
5997 | as we do. Note that any secondary reloads must be of the identical | |
5998 | class since the values, modes, and result registers are the | |
5999 | same, so we need not do anything with any secondary reloads. */ | |
6000 | ||
6001 | for (j = 0; j < n_reloads; j++) | |
6002 | { | |
eceef4c9 BS |
6003 | if (i == j || rld[j].reg_rtx == 0 |
6004 | || ! reg_overlap_mentioned_p (rld[j].reg_rtx, | |
6005 | rld[i].reg_rtx)) | |
546b63fb RK |
6006 | continue; |
6007 | ||
eceef4c9 BS |
6008 | if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6009 | && rld[j].opnum > max_input_address_opnum) | |
6010 | max_input_address_opnum = rld[j].opnum; | |
d668e863 | 6011 | |
546b63fb | 6012 | /* If the reload regs aren't exactly the same (e.g, different modes) |
d668e863 R |
6013 | or if the values are different, we can't merge this reload. |
6014 | But if it is an input reload, we might still merge | |
6015 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ | |
546b63fb | 6016 | |
eceef4c9 BS |
6017 | if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) |
6018 | || rld[j].out != 0 || rld[j].in == 0 | |
6019 | || ! rtx_equal_p (rld[i].in, rld[j].in)) | |
d668e863 | 6020 | { |
eceef4c9 BS |
6021 | if (rld[j].when_needed != RELOAD_FOR_INPUT |
6022 | || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS | |
6023 | || rld[i].opnum > rld[j].opnum) | |
6024 | && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS)) | |
d668e863 R |
6025 | break; |
6026 | conflicting_input = 1; | |
eceef4c9 BS |
6027 | if (min_conflicting_input_opnum > rld[j].opnum) |
6028 | min_conflicting_input_opnum = rld[j].opnum; | |
d668e863 | 6029 | } |
546b63fb RK |
6030 | } |
6031 | ||
6032 | /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if | |
6033 | we, in fact, found any matching reloads. */ | |
6034 | ||
d668e863 R |
6035 | if (j == n_reloads |
6036 | && max_input_address_opnum <= min_conflicting_input_opnum) | |
546b63fb RK |
6037 | { |
6038 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
6039 | if (i != j && rld[j].reg_rtx != 0 |
6040 | && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) | |
d668e863 | 6041 | && (! conflicting_input |
eceef4c9 BS |
6042 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6043 | || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
546b63fb | 6044 | { |
eceef4c9 BS |
6045 | rld[i].when_needed = RELOAD_OTHER; |
6046 | rld[j].in = 0; | |
efdb3590 | 6047 | reload_spill_index[j] = -1; |
546b63fb RK |
6048 | transfer_replacements (i, j); |
6049 | } | |
6050 | ||
6051 | /* If this is now RELOAD_OTHER, look for any reloads that load | |
6052 | parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS | |
6053 | if they were for inputs, RELOAD_OTHER for outputs. Note that | |
6054 | this test is equivalent to looking for reloads for this operand | |
6055 | number. */ | |
dec0798e R |
6056 | /* We must take special care when there are two or more reloads to |
6057 | be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the | |
6058 | same value or a part of it; we must not change its type if there | |
6059 | is a conflicting input. */ | |
546b63fb | 6060 | |
eceef4c9 | 6061 | if (rld[i].when_needed == RELOAD_OTHER) |
546b63fb | 6062 | for (j = 0; j < n_reloads; j++) |
eceef4c9 | 6063 | if (rld[j].in != 0 |
91667711 | 6064 | && rld[j].when_needed != RELOAD_OTHER |
dec0798e R |
6065 | && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS |
6066 | && (! conflicting_input | |
6067 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
6068 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
eceef4c9 BS |
6069 | && reg_overlap_mentioned_for_reload_p (rld[j].in, |
6070 | rld[i].in)) | |
c15c18c5 JW |
6071 | { |
6072 | int k; | |
6073 | ||
6074 | rld[j].when_needed | |
6075 | = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
6076 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
6077 | ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); | |
6078 | ||
6079 | /* Check to see if we accidentally converted two reloads | |
8a5db2b4 JW |
6080 | that use the same reload register with different inputs |
6081 | to the same type. If so, the resulting code won't work, | |
6082 | so abort. */ | |
c15c18c5 JW |
6083 | if (rld[j].reg_rtx) |
6084 | for (k = 0; k < j; k++) | |
6085 | if (rld[k].in != 0 && rld[k].reg_rtx != 0 | |
6086 | && rld[k].when_needed == rld[j].when_needed | |
8a5db2b4 JW |
6087 | && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx) |
6088 | && ! rtx_equal_p (rld[k].in, rld[j].in)) | |
c15c18c5 JW |
6089 | abort (); |
6090 | } | |
546b63fb RK |
6091 | } |
6092 | } | |
05d10675 | 6093 | } |
546b63fb | 6094 | \f |
367b1cf5 BS |
6095 | /* These arrays are filled by emit_reload_insns and its subroutines. */ |
6096 | static rtx input_reload_insns[MAX_RECOG_OPERANDS]; | |
6097 | static rtx other_input_address_reload_insns = 0; | |
6098 | static rtx other_input_reload_insns = 0; | |
6099 | static rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6100 | static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6101 | static rtx output_reload_insns[MAX_RECOG_OPERANDS]; | |
6102 | static rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6103 | static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6104 | static rtx operand_reload_insns = 0; | |
6105 | static rtx other_operand_reload_insns = 0; | |
6106 | static rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; | |
6107 | ||
6108 | /* Values to be put in spill_reg_store are put here first. */ | |
6109 | static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
6110 | static HARD_REG_SET reg_reloaded_died; | |
6111 | ||
6112 | /* Generate insns to perform reload RL, which is for the insn in CHAIN and | |
6113 | has the number J. OLD contains the value to be used as input. */ | |
770ae6cc | 6114 | |
32131a9c | 6115 | static void |
0c20a65f AJ |
6116 | emit_input_reload_insns (struct insn_chain *chain, struct reload *rl, |
6117 | rtx old, int j) | |
32131a9c | 6118 | { |
7609e720 | 6119 | rtx insn = chain->insn; |
b3694847 | 6120 | rtx reloadreg = rl->reg_rtx; |
367b1cf5 BS |
6121 | rtx oldequiv_reg = 0; |
6122 | rtx oldequiv = 0; | |
6123 | int special = 0; | |
6124 | enum machine_mode mode; | |
6125 | rtx *where; | |
6126 | ||
6127 | /* Determine the mode to reload in. | |
6128 | This is very tricky because we have three to choose from. | |
6129 | There is the mode the insn operand wants (rl->inmode). | |
6130 | There is the mode of the reload register RELOADREG. | |
6131 | There is the intrinsic mode of the operand, which we could find | |
6132 | by stripping some SUBREGs. | |
6133 | It turns out that RELOADREG's mode is irrelevant: | |
6134 | we can change that arbitrarily. | |
6135 | ||
6136 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
6137 | then the reload reg may not support QImode moves, so use SImode. | |
6138 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
6139 | because the QImode value is in the least significant part of a | |
6140 | slot big enough for a SImode. If foo is some other sort of | |
6141 | memory reference, then it is impossible to reload this case, | |
6142 | so previous passes had better make sure this never happens. | |
6143 | ||
6144 | Then consider a one-word union which has SImode and one of its | |
6145 | members is a float, being fetched as (SUBREG:SF union:SI). | |
6146 | We must fetch that as SFmode because we could be loading into | |
6147 | a float-only register. In this case OLD's mode is correct. | |
6148 | ||
6149 | Consider an immediate integer: it has VOIDmode. Here we need | |
6150 | to get a mode from something else. | |
6151 | ||
6152 | In some cases, there is a fourth mode, the operand's | |
6153 | containing mode. If the insn specifies a containing mode for | |
6154 | this operand, it overrides all others. | |
6155 | ||
6156 | I am not sure whether the algorithm here is always right, | |
6157 | but it does the right things in those cases. */ | |
6158 | ||
6159 | mode = GET_MODE (old); | |
6160 | if (mode == VOIDmode) | |
6161 | mode = rl->inmode; | |
7609e720 | 6162 | |
367b1cf5 BS |
6163 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
6164 | /* If we need a secondary register for this operation, see if | |
6165 | the value is already in a register in that class. Don't | |
6166 | do this if the secondary register will be used as a scratch | |
6167 | register. */ | |
6168 | ||
6169 | if (rl->secondary_in_reload >= 0 | |
6170 | && rl->secondary_in_icode == CODE_FOR_nothing | |
6171 | && optimize) | |
6172 | oldequiv | |
6173 | = find_equiv_reg (old, insn, | |
6174 | rld[rl->secondary_in_reload].class, | |
9714cf43 | 6175 | -1, NULL, 0, mode); |
367b1cf5 | 6176 | #endif |
e6e52be0 | 6177 | |
367b1cf5 BS |
6178 | /* If reloading from memory, see if there is a register |
6179 | that already holds the same value. If so, reload from there. | |
6180 | We can pass 0 as the reload_reg_p argument because | |
6181 | any other reload has either already been emitted, | |
6182 | in which case find_equiv_reg will see the reload-insn, | |
6183 | or has yet to be emitted, in which case it doesn't matter | |
6184 | because we will use this equiv reg right away. */ | |
6185 | ||
6186 | if (oldequiv == 0 && optimize | |
6187 | && (GET_CODE (old) == MEM | |
6188 | || (GET_CODE (old) == REG | |
6189 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
6190 | && reg_renumber[REGNO (old)] < 0))) | |
9714cf43 | 6191 | oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode); |
367b1cf5 BS |
6192 | |
6193 | if (oldequiv) | |
6194 | { | |
770ae6cc | 6195 | unsigned int regno = true_regnum (oldequiv); |
367b1cf5 BS |
6196 | |
6197 | /* Don't use OLDEQUIV if any other reload changes it at an | |
6198 | earlier stage of this insn or at this stage. */ | |
c02cad8f BS |
6199 | if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed, |
6200 | rl->in, const0_rtx, j, 0)) | |
367b1cf5 BS |
6201 | oldequiv = 0; |
6202 | ||
6203 | /* If it is no cheaper to copy from OLDEQUIV into the | |
6204 | reload register than it would be to move from memory, | |
6205 | don't use it. Likewise, if we need a secondary register | |
6d2f8887 | 6206 | or memory. */ |
367b1cf5 BS |
6207 | |
6208 | if (oldequiv != 0 | |
fc555370 | 6209 | && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class |
e56b4594 | 6210 | && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno), |
367b1cf5 BS |
6211 | rl->class) |
6212 | >= MEMORY_MOVE_COST (mode, rl->class, 1))) | |
6213 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
6214 | || (SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
6215 | mode, oldequiv) | |
6216 | != NO_REGS) | |
6217 | #endif | |
6218 | #ifdef SECONDARY_MEMORY_NEEDED | |
6219 | || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno), | |
6220 | rl->class, | |
6221 | mode) | |
6222 | #endif | |
6223 | )) | |
6224 | oldequiv = 0; | |
6225 | } | |
32131a9c | 6226 | |
367b1cf5 BS |
6227 | /* delete_output_reload is only invoked properly if old contains |
6228 | the original pseudo register. Since this is replaced with a | |
6229 | hard reg when RELOAD_OVERRIDE_IN is set, see if we can | |
6230 | find the pseudo in RELOAD_IN_REG. */ | |
6231 | if (oldequiv == 0 | |
6232 | && reload_override_in[j] | |
6233 | && GET_CODE (rl->in_reg) == REG) | |
6234 | { | |
6235 | oldequiv = old; | |
6236 | old = rl->in_reg; | |
6237 | } | |
6238 | if (oldequiv == 0) | |
6239 | oldequiv = old; | |
6240 | else if (GET_CODE (oldequiv) == REG) | |
6241 | oldequiv_reg = oldequiv; | |
6242 | else if (GET_CODE (oldequiv) == SUBREG) | |
6243 | oldequiv_reg = SUBREG_REG (oldequiv); | |
6244 | ||
6245 | /* If we are reloading from a register that was recently stored in | |
6246 | with an output-reload, see if we can prove there was | |
6247 | actually no need to store the old value in it. */ | |
6248 | ||
6249 | if (optimize && GET_CODE (oldequiv) == REG | |
6250 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6251 | && spill_reg_store[REGNO (oldequiv)] | |
6252 | && GET_CODE (old) == REG | |
6253 | && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) | |
6254 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6255 | rl->out_reg))) | |
6256 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6257 | ||
6258 | /* Encapsulate both RELOADREG and OLDEQUIV into that mode, | |
6259 | then load RELOADREG from OLDEQUIV. Note that we cannot use | |
6260 | gen_lowpart_common since it can do the wrong thing when | |
6261 | RELOADREG has a multi-word mode. Note that RELOADREG | |
6262 | must always be a REG here. */ | |
6263 | ||
6264 | if (GET_MODE (reloadreg) != mode) | |
f12448c8 | 6265 | reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); |
367b1cf5 BS |
6266 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) |
6267 | oldequiv = SUBREG_REG (oldequiv); | |
6268 | if (GET_MODE (oldequiv) != VOIDmode | |
6269 | && mode != GET_MODE (oldequiv)) | |
ddef6bc7 | 6270 | oldequiv = gen_lowpart_SUBREG (mode, oldequiv); |
367b1cf5 BS |
6271 | |
6272 | /* Switch to the right place to emit the reload insns. */ | |
6273 | switch (rl->when_needed) | |
6274 | { | |
6275 | case RELOAD_OTHER: | |
6276 | where = &other_input_reload_insns; | |
6277 | break; | |
6278 | case RELOAD_FOR_INPUT: | |
6279 | where = &input_reload_insns[rl->opnum]; | |
6280 | break; | |
6281 | case RELOAD_FOR_INPUT_ADDRESS: | |
6282 | where = &input_address_reload_insns[rl->opnum]; | |
6283 | break; | |
6284 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6285 | where = &inpaddr_address_reload_insns[rl->opnum]; | |
6286 | break; | |
6287 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
6288 | where = &output_address_reload_insns[rl->opnum]; | |
6289 | break; | |
6290 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
6291 | where = &outaddr_address_reload_insns[rl->opnum]; | |
6292 | break; | |
6293 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6294 | where = &operand_reload_insns; | |
6295 | break; | |
6296 | case RELOAD_FOR_OPADDR_ADDR: | |
6297 | where = &other_operand_reload_insns; | |
6298 | break; | |
6299 | case RELOAD_FOR_OTHER_ADDRESS: | |
6300 | where = &other_input_address_reload_insns; | |
6301 | break; | |
6302 | default: | |
6303 | abort (); | |
6304 | } | |
546b63fb | 6305 | |
367b1cf5 | 6306 | push_to_sequence (*where); |
32131a9c | 6307 | |
367b1cf5 BS |
6308 | /* Auto-increment addresses must be reloaded in a special way. */ |
6309 | if (rl->out && ! rl->out_reg) | |
32131a9c | 6310 | { |
367b1cf5 BS |
6311 | /* We are not going to bother supporting the case where a |
6312 | incremented register can't be copied directly from | |
6313 | OLDEQUIV since this seems highly unlikely. */ | |
6314 | if (rl->secondary_in_reload >= 0) | |
6315 | abort (); | |
32131a9c | 6316 | |
367b1cf5 BS |
6317 | if (reload_inherited[j]) |
6318 | oldequiv = reloadreg; | |
cb2afeb3 | 6319 | |
367b1cf5 | 6320 | old = XEXP (rl->in_reg, 0); |
32131a9c | 6321 | |
367b1cf5 BS |
6322 | if (optimize && GET_CODE (oldequiv) == REG |
6323 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6324 | && spill_reg_store[REGNO (oldequiv)] | |
6325 | && GET_CODE (old) == REG | |
6326 | && (dead_or_set_p (insn, | |
6327 | spill_reg_stored_to[REGNO (oldequiv)]) | |
6328 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6329 | old))) | |
6330 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6331 | ||
6332 | /* Prevent normal processing of this reload. */ | |
6333 | special = 1; | |
6334 | /* Output a special code sequence for this case. */ | |
6335 | new_spill_reg_store[REGNO (reloadreg)] | |
6336 | = inc_for_reload (reloadreg, oldequiv, rl->out, | |
6337 | rl->inc); | |
6338 | } | |
32131a9c | 6339 | |
367b1cf5 BS |
6340 | /* If we are reloading a pseudo-register that was set by the previous |
6341 | insn, see if we can get rid of that pseudo-register entirely | |
6342 | by redirecting the previous insn into our reload register. */ | |
6343 | ||
6344 | else if (optimize && GET_CODE (old) == REG | |
6345 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
6346 | && dead_or_set_p (insn, old) | |
6347 | /* This is unsafe if some other reload | |
6348 | uses the same reg first. */ | |
ff6534ad | 6349 | && ! conflicts_with_override (reloadreg) |
c02cad8f BS |
6350 | && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum, |
6351 | rl->when_needed, old, rl->out, j, 0)) | |
367b1cf5 BS |
6352 | { |
6353 | rtx temp = PREV_INSN (insn); | |
6354 | while (temp && GET_CODE (temp) == NOTE) | |
6355 | temp = PREV_INSN (temp); | |
6356 | if (temp | |
6357 | && GET_CODE (temp) == INSN | |
6358 | && GET_CODE (PATTERN (temp)) == SET | |
6359 | && SET_DEST (PATTERN (temp)) == old | |
6360 | /* Make sure we can access insn_operand_constraint. */ | |
6361 | && asm_noperands (PATTERN (temp)) < 0 | |
367b1cf5 BS |
6362 | /* This is unsafe if operand occurs more than once in current |
6363 | insn. Perhaps some occurrences aren't reloaded. */ | |
10d1bb36 | 6364 | && count_occurrences (PATTERN (insn), old, 0) == 1) |
367b1cf5 | 6365 | { |
10d1bb36 | 6366 | rtx old = SET_DEST (PATTERN (temp)); |
367b1cf5 BS |
6367 | /* Store into the reload register instead of the pseudo. */ |
6368 | SET_DEST (PATTERN (temp)) = reloadreg; | |
6369 | ||
10d1bb36 JH |
6370 | /* Verify that resulting insn is valid. */ |
6371 | extract_insn (temp); | |
6372 | if (constrain_operands (1)) | |
32131a9c | 6373 | { |
10d1bb36 JH |
6374 | /* If the previous insn is an output reload, the source is |
6375 | a reload register, and its spill_reg_store entry will | |
6376 | contain the previous destination. This is now | |
6377 | invalid. */ | |
6378 | if (GET_CODE (SET_SRC (PATTERN (temp))) == REG | |
6379 | && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) | |
6380 | { | |
6381 | spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
6382 | spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
6383 | } | |
32131a9c | 6384 | |
10d1bb36 JH |
6385 | /* If these are the only uses of the pseudo reg, |
6386 | pretend for GDB it lives in the reload reg we used. */ | |
6387 | if (REG_N_DEATHS (REGNO (old)) == 1 | |
6388 | && REG_N_SETS (REGNO (old)) == 1) | |
6389 | { | |
6390 | reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx); | |
6391 | alter_reg (REGNO (old), -1); | |
6392 | } | |
6393 | special = 1; | |
6394 | } | |
6395 | else | |
cb2afeb3 | 6396 | { |
10d1bb36 | 6397 | SET_DEST (PATTERN (temp)) = old; |
32131a9c | 6398 | } |
367b1cf5 BS |
6399 | } |
6400 | } | |
32131a9c | 6401 | |
367b1cf5 | 6402 | /* We can't do that, so output an insn to load RELOADREG. */ |
32131a9c | 6403 | |
367b1cf5 BS |
6404 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
6405 | /* If we have a secondary reload, pick up the secondary register | |
6406 | and icode, if any. If OLDEQUIV and OLD are different or | |
6407 | if this is an in-out reload, recompute whether or not we | |
6408 | still need a secondary register and what the icode should | |
6409 | be. If we still need a secondary register and the class or | |
6410 | icode is different, go back to reloading from OLD if using | |
6411 | OLDEQUIV means that we got the wrong type of register. We | |
6412 | cannot have different class or icode due to an in-out reload | |
6413 | because we don't make such reloads when both the input and | |
6414 | output need secondary reload registers. */ | |
6415 | ||
07875628 | 6416 | if (! special && rl->secondary_in_reload >= 0) |
367b1cf5 BS |
6417 | { |
6418 | rtx second_reload_reg = 0; | |
6419 | int secondary_reload = rl->secondary_in_reload; | |
6420 | rtx real_oldequiv = oldequiv; | |
6421 | rtx real_old = old; | |
6422 | rtx tmp; | |
6423 | enum insn_code icode; | |
6424 | ||
6425 | /* If OLDEQUIV is a pseudo with a MEM, get the real MEM | |
6426 | and similarly for OLD. | |
6427 | See comments in get_secondary_reload in reload.c. */ | |
6428 | /* If it is a pseudo that cannot be replaced with its | |
6429 | equivalent MEM, we must fall back to reload_in, which | |
6430 | will have all the necessary substitutions registered. | |
6431 | Likewise for a pseudo that can't be replaced with its | |
6432 | equivalent constant. | |
6433 | ||
6434 | Take extra care for subregs of such pseudos. Note that | |
6435 | we cannot use reg_equiv_mem in this case because it is | |
6436 | not in the right mode. */ | |
6437 | ||
6438 | tmp = oldequiv; | |
6439 | if (GET_CODE (tmp) == SUBREG) | |
6440 | tmp = SUBREG_REG (tmp); | |
6441 | if (GET_CODE (tmp) == REG | |
6442 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6443 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6444 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6445 | { | |
6446 | if (! reg_equiv_mem[REGNO (tmp)] | |
6447 | || num_not_at_initial_offset | |
6448 | || GET_CODE (oldequiv) == SUBREG) | |
6449 | real_oldequiv = rl->in; | |
6450 | else | |
6451 | real_oldequiv = reg_equiv_mem[REGNO (tmp)]; | |
6452 | } | |
32131a9c | 6453 | |
367b1cf5 BS |
6454 | tmp = old; |
6455 | if (GET_CODE (tmp) == SUBREG) | |
6456 | tmp = SUBREG_REG (tmp); | |
6457 | if (GET_CODE (tmp) == REG | |
6458 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6459 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6460 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6461 | { | |
6462 | if (! reg_equiv_mem[REGNO (tmp)] | |
6463 | || num_not_at_initial_offset | |
6464 | || GET_CODE (old) == SUBREG) | |
6465 | real_old = rl->in; | |
6466 | else | |
6467 | real_old = reg_equiv_mem[REGNO (tmp)]; | |
6468 | } | |
6469 | ||
6470 | second_reload_reg = rld[secondary_reload].reg_rtx; | |
6471 | icode = rl->secondary_in_icode; | |
6472 | ||
6473 | if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) | |
6474 | || (rl->in != 0 && rl->out != 0)) | |
6475 | { | |
6476 | enum reg_class new_class | |
6477 | = SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
6478 | mode, real_oldequiv); | |
6479 | ||
6480 | if (new_class == NO_REGS) | |
6481 | second_reload_reg = 0; | |
6482 | else | |
32131a9c | 6483 | { |
367b1cf5 BS |
6484 | enum insn_code new_icode; |
6485 | enum machine_mode new_mode; | |
6486 | ||
6487 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], | |
6488 | REGNO (second_reload_reg))) | |
6489 | oldequiv = old, real_oldequiv = real_old; | |
6490 | else | |
32131a9c | 6491 | { |
367b1cf5 BS |
6492 | new_icode = reload_in_optab[(int) mode]; |
6493 | if (new_icode != CODE_FOR_nothing | |
6494 | && ((insn_data[(int) new_icode].operand[0].predicate | |
6495 | && ! ((*insn_data[(int) new_icode].operand[0].predicate) | |
6496 | (reloadreg, mode))) | |
6497 | || (insn_data[(int) new_icode].operand[1].predicate | |
6498 | && ! ((*insn_data[(int) new_icode].operand[1].predicate) | |
6499 | (real_oldequiv, mode))))) | |
6500 | new_icode = CODE_FOR_nothing; | |
6501 | ||
6502 | if (new_icode == CODE_FOR_nothing) | |
6503 | new_mode = mode; | |
6504 | else | |
6505 | new_mode = insn_data[(int) new_icode].operand[2].mode; | |
d30e8ef0 | 6506 | |
367b1cf5 | 6507 | if (GET_MODE (second_reload_reg) != new_mode) |
32131a9c | 6508 | { |
367b1cf5 BS |
6509 | if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), |
6510 | new_mode)) | |
6511 | oldequiv = old, real_oldequiv = real_old; | |
6512 | else | |
6513 | second_reload_reg | |
f12448c8 AO |
6514 | = reload_adjust_reg_for_mode (second_reload_reg, |
6515 | new_mode); | |
32131a9c | 6516 | } |
32131a9c RK |
6517 | } |
6518 | } | |
367b1cf5 | 6519 | } |
32131a9c | 6520 | |
367b1cf5 BS |
6521 | /* If we still need a secondary reload register, check |
6522 | to see if it is being used as a scratch or intermediate | |
6523 | register and generate code appropriately. If we need | |
6524 | a scratch register, use REAL_OLDEQUIV since the form of | |
6525 | the insn may depend on the actual address if it is | |
6526 | a MEM. */ | |
546b63fb | 6527 | |
367b1cf5 BS |
6528 | if (second_reload_reg) |
6529 | { | |
6530 | if (icode != CODE_FOR_nothing) | |
32131a9c | 6531 | { |
367b1cf5 BS |
6532 | emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, |
6533 | second_reload_reg)); | |
07875628 | 6534 | special = 1; |
367b1cf5 BS |
6535 | } |
6536 | else | |
6537 | { | |
6538 | /* See if we need a scratch register to load the | |
6539 | intermediate register (a tertiary reload). */ | |
6540 | enum insn_code tertiary_icode | |
6541 | = rld[secondary_reload].secondary_in_icode; | |
1554c2c6 | 6542 | |
367b1cf5 BS |
6543 | if (tertiary_icode != CODE_FOR_nothing) |
6544 | { | |
6545 | rtx third_reload_reg | |
6546 | = rld[rld[secondary_reload].secondary_in_reload].reg_rtx; | |
1554c2c6 | 6547 | |
367b1cf5 BS |
6548 | emit_insn ((GEN_FCN (tertiary_icode) |
6549 | (second_reload_reg, real_oldequiv, | |
6550 | third_reload_reg))); | |
6551 | } | |
6552 | else | |
6553 | gen_reload (second_reload_reg, real_oldequiv, | |
6554 | rl->opnum, | |
6555 | rl->when_needed); | |
32131a9c | 6556 | |
367b1cf5 BS |
6557 | oldequiv = second_reload_reg; |
6558 | } | |
6559 | } | |
6560 | } | |
6561 | #endif | |
32131a9c | 6562 | |
07875628 | 6563 | if (! special && ! rtx_equal_p (reloadreg, oldequiv)) |
367b1cf5 BS |
6564 | { |
6565 | rtx real_oldequiv = oldequiv; | |
6566 | ||
6567 | if ((GET_CODE (oldequiv) == REG | |
6568 | && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER | |
6569 | && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 | |
6570 | || reg_equiv_constant[REGNO (oldequiv)] != 0)) | |
6571 | || (GET_CODE (oldequiv) == SUBREG | |
6572 | && GET_CODE (SUBREG_REG (oldequiv)) == REG | |
6573 | && (REGNO (SUBREG_REG (oldequiv)) | |
6574 | >= FIRST_PSEUDO_REGISTER) | |
6575 | && ((reg_equiv_memory_loc | |
6576 | [REGNO (SUBREG_REG (oldequiv))] != 0) | |
6577 | || (reg_equiv_constant | |
716120a7 JJ |
6578 | [REGNO (SUBREG_REG (oldequiv))] != 0))) |
6579 | || (CONSTANT_P (oldequiv) | |
019d2e99 AS |
6580 | && (PREFERRED_RELOAD_CLASS (oldequiv, |
6581 | REGNO_REG_CLASS (REGNO (reloadreg))) | |
6582 | == NO_REGS))) | |
367b1cf5 BS |
6583 | real_oldequiv = rl->in; |
6584 | gen_reload (reloadreg, real_oldequiv, rl->opnum, | |
6585 | rl->when_needed); | |
6586 | } | |
32131a9c | 6587 | |
94bd63e5 AH |
6588 | if (flag_non_call_exceptions) |
6589 | copy_eh_notes (insn, get_insns ()); | |
6590 | ||
367b1cf5 BS |
6591 | /* End this sequence. */ |
6592 | *where = get_insns (); | |
6593 | end_sequence (); | |
a6a2274a | 6594 | |
367b1cf5 BS |
6595 | /* Update reload_override_in so that delete_address_reloads_1 |
6596 | can see the actual register usage. */ | |
6597 | if (oldequiv_reg) | |
6598 | reload_override_in[j] = oldequiv; | |
6599 | } | |
32131a9c | 6600 | |
367b1cf5 BS |
6601 | /* Generate insns to for the output reload RL, which is for the insn described |
6602 | by CHAIN and has the number J. */ | |
6603 | static void | |
0c20a65f AJ |
6604 | emit_output_reload_insns (struct insn_chain *chain, struct reload *rl, |
6605 | int j) | |
367b1cf5 BS |
6606 | { |
6607 | rtx reloadreg = rl->reg_rtx; | |
6608 | rtx insn = chain->insn; | |
6609 | int special = 0; | |
6610 | rtx old = rl->out; | |
6611 | enum machine_mode mode = GET_MODE (old); | |
6612 | rtx p; | |
32131a9c | 6613 | |
367b1cf5 BS |
6614 | if (rl->when_needed == RELOAD_OTHER) |
6615 | start_sequence (); | |
6616 | else | |
6617 | push_to_sequence (output_reload_insns[rl->opnum]); | |
32131a9c | 6618 | |
367b1cf5 BS |
6619 | /* Determine the mode to reload in. |
6620 | See comments above (for input reloading). */ | |
32131a9c | 6621 | |
367b1cf5 BS |
6622 | if (mode == VOIDmode) |
6623 | { | |
6624 | /* VOIDmode should never happen for an output. */ | |
6625 | if (asm_noperands (PATTERN (insn)) < 0) | |
6626 | /* It's the compiler's fault. */ | |
6627 | fatal_insn ("VOIDmode on an output", insn); | |
6628 | error_for_asm (insn, "output operand is constant in `asm'"); | |
6629 | /* Prevent crash--use something we know is valid. */ | |
6630 | mode = word_mode; | |
6631 | old = gen_rtx_REG (mode, REGNO (reloadreg)); | |
6632 | } | |
546b63fb | 6633 | |
367b1cf5 | 6634 | if (GET_MODE (reloadreg) != mode) |
f12448c8 | 6635 | reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); |
32131a9c | 6636 | |
367b1cf5 | 6637 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
32131a9c | 6638 | |
367b1cf5 BS |
6639 | /* If we need two reload regs, set RELOADREG to the intermediate |
6640 | one, since it will be stored into OLD. We might need a secondary | |
6641 | register only for an input reload, so check again here. */ | |
32131a9c | 6642 | |
367b1cf5 BS |
6643 | if (rl->secondary_out_reload >= 0) |
6644 | { | |
6645 | rtx real_old = old; | |
cb2afeb3 | 6646 | |
367b1cf5 BS |
6647 | if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER |
6648 | && reg_equiv_mem[REGNO (old)] != 0) | |
6649 | real_old = reg_equiv_mem[REGNO (old)]; | |
32131a9c | 6650 | |
367b1cf5 BS |
6651 | if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class, |
6652 | mode, real_old) | |
6653 | != NO_REGS)) | |
b60a8416 | 6654 | { |
367b1cf5 BS |
6655 | rtx second_reloadreg = reloadreg; |
6656 | reloadreg = rld[rl->secondary_out_reload].reg_rtx; | |
32131a9c | 6657 | |
367b1cf5 BS |
6658 | /* See if RELOADREG is to be used as a scratch register |
6659 | or as an intermediate register. */ | |
6660 | if (rl->secondary_out_icode != CODE_FOR_nothing) | |
6661 | { | |
6662 | emit_insn ((GEN_FCN (rl->secondary_out_icode) | |
6663 | (real_old, second_reloadreg, reloadreg))); | |
6664 | special = 1; | |
6665 | } | |
6666 | else | |
6667 | { | |
6668 | /* See if we need both a scratch and intermediate reload | |
6669 | register. */ | |
32131a9c | 6670 | |
367b1cf5 BS |
6671 | int secondary_reload = rl->secondary_out_reload; |
6672 | enum insn_code tertiary_icode | |
6673 | = rld[secondary_reload].secondary_out_icode; | |
32131a9c | 6674 | |
367b1cf5 | 6675 | if (GET_MODE (reloadreg) != mode) |
f12448c8 | 6676 | reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); |
cb2afeb3 | 6677 | |
367b1cf5 BS |
6678 | if (tertiary_icode != CODE_FOR_nothing) |
6679 | { | |
6680 | rtx third_reloadreg | |
6681 | = rld[rld[secondary_reload].secondary_out_reload].reg_rtx; | |
6682 | rtx tem; | |
6683 | ||
6684 | /* Copy primary reload reg to secondary reload reg. | |
6685 | (Note that these have been swapped above, then | |
78adc5a0 | 6686 | secondary reload reg to OLD using our insn.) */ |
367b1cf5 BS |
6687 | |
6688 | /* If REAL_OLD is a paradoxical SUBREG, remove it | |
6689 | and try to put the opposite SUBREG on | |
6690 | RELOADREG. */ | |
6691 | if (GET_CODE (real_old) == SUBREG | |
6692 | && (GET_MODE_SIZE (GET_MODE (real_old)) | |
6693 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) | |
6694 | && 0 != (tem = gen_lowpart_common | |
6695 | (GET_MODE (SUBREG_REG (real_old)), | |
6696 | reloadreg))) | |
6697 | real_old = SUBREG_REG (real_old), reloadreg = tem; | |
6698 | ||
6699 | gen_reload (reloadreg, second_reloadreg, | |
6700 | rl->opnum, rl->when_needed); | |
6701 | emit_insn ((GEN_FCN (tertiary_icode) | |
6702 | (real_old, reloadreg, third_reloadreg))); | |
6703 | special = 1; | |
6704 | } | |
05d10675 | 6705 | |
367b1cf5 BS |
6706 | else |
6707 | /* Copy between the reload regs here and then to | |
6708 | OUT later. */ | |
cb2afeb3 | 6709 | |
367b1cf5 BS |
6710 | gen_reload (reloadreg, second_reloadreg, |
6711 | rl->opnum, rl->when_needed); | |
a7911cd2 | 6712 | } |
367b1cf5 BS |
6713 | } |
6714 | } | |
32131a9c RK |
6715 | #endif |
6716 | ||
367b1cf5 BS |
6717 | /* Output the last reload insn. */ |
6718 | if (! special) | |
6719 | { | |
6720 | rtx set; | |
6721 | ||
6722 | /* Don't output the last reload if OLD is not the dest of | |
1d7254c5 | 6723 | INSN and is in the src and is clobbered by INSN. */ |
367b1cf5 BS |
6724 | if (! flag_expensive_optimizations |
6725 | || GET_CODE (old) != REG | |
6726 | || !(set = single_set (insn)) | |
6727 | || rtx_equal_p (old, SET_DEST (set)) | |
6728 | || !reg_mentioned_p (old, SET_SRC (set)) | |
9532e31f | 6729 | || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0)) |
367b1cf5 BS |
6730 | gen_reload (old, reloadreg, rl->opnum, |
6731 | rl->when_needed); | |
6732 | } | |
32131a9c | 6733 | |
367b1cf5 BS |
6734 | /* Look at all insns we emitted, just to be safe. */ |
6735 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2c3c49de | 6736 | if (INSN_P (p)) |
367b1cf5 BS |
6737 | { |
6738 | rtx pat = PATTERN (p); | |
546b63fb | 6739 | |
367b1cf5 BS |
6740 | /* If this output reload doesn't come from a spill reg, |
6741 | clear any memory of reloaded copies of the pseudo reg. | |
6742 | If this output reload comes from a spill reg, | |
6743 | reg_has_output_reload will make this do nothing. */ | |
6744 | note_stores (pat, forget_old_reloads_1, NULL); | |
cb2afeb3 | 6745 | |
367b1cf5 BS |
6746 | if (reg_mentioned_p (rl->reg_rtx, pat)) |
6747 | { | |
6748 | rtx set = single_set (insn); | |
6749 | if (reload_spill_index[j] < 0 | |
6750 | && set | |
6751 | && SET_SRC (set) == rl->reg_rtx) | |
6752 | { | |
6753 | int src = REGNO (SET_SRC (set)); | |
32131a9c | 6754 | |
367b1cf5 BS |
6755 | reload_spill_index[j] = src; |
6756 | SET_HARD_REG_BIT (reg_is_output_reload, src); | |
6757 | if (find_regno_note (insn, REG_DEAD, src)) | |
6758 | SET_HARD_REG_BIT (reg_reloaded_died, src); | |
6759 | } | |
6760 | if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER) | |
6761 | { | |
6762 | int s = rl->secondary_out_reload; | |
6763 | set = single_set (p); | |
6764 | /* If this reload copies only to the secondary reload | |
6765 | register, the secondary reload does the actual | |
6766 | store. */ | |
6767 | if (s >= 0 && set == NULL_RTX) | |
1d7254c5 KH |
6768 | /* We can't tell what function the secondary reload |
6769 | has and where the actual store to the pseudo is | |
6770 | made; leave new_spill_reg_store alone. */ | |
6771 | ; | |
367b1cf5 BS |
6772 | else if (s >= 0 |
6773 | && SET_SRC (set) == rl->reg_rtx | |
6774 | && SET_DEST (set) == rld[s].reg_rtx) | |
6775 | { | |
6776 | /* Usually the next instruction will be the | |
6777 | secondary reload insn; if we can confirm | |
6778 | that it is, setting new_spill_reg_store to | |
6779 | that insn will allow an extra optimization. */ | |
6780 | rtx s_reg = rld[s].reg_rtx; | |
6781 | rtx next = NEXT_INSN (p); | |
6782 | rld[s].out = rl->out; | |
6783 | rld[s].out_reg = rl->out_reg; | |
6784 | set = single_set (next); | |
6785 | if (set && SET_SRC (set) == s_reg | |
6786 | && ! new_spill_reg_store[REGNO (s_reg)]) | |
6787 | { | |
6788 | SET_HARD_REG_BIT (reg_is_output_reload, | |
6789 | REGNO (s_reg)); | |
6790 | new_spill_reg_store[REGNO (s_reg)] = next; | |
6791 | } | |
6792 | } | |
6793 | else | |
6794 | new_spill_reg_store[REGNO (rl->reg_rtx)] = p; | |
6795 | } | |
6796 | } | |
6797 | } | |
32131a9c | 6798 | |
367b1cf5 BS |
6799 | if (rl->when_needed == RELOAD_OTHER) |
6800 | { | |
2f937369 | 6801 | emit_insn (other_output_reload_insns[rl->opnum]); |
367b1cf5 BS |
6802 | other_output_reload_insns[rl->opnum] = get_insns (); |
6803 | } | |
6804 | else | |
6805 | output_reload_insns[rl->opnum] = get_insns (); | |
32131a9c | 6806 | |
94bd63e5 AH |
6807 | if (flag_non_call_exceptions) |
6808 | copy_eh_notes (insn, get_insns ()); | |
6809 | ||
1d7254c5 | 6810 | end_sequence (); |
367b1cf5 | 6811 | } |
32131a9c | 6812 | |
367b1cf5 BS |
6813 | /* Do input reloading for reload RL, which is for the insn described by CHAIN |
6814 | and has the number J. */ | |
6815 | static void | |
0c20a65f | 6816 | do_input_reload (struct insn_chain *chain, struct reload *rl, int j) |
367b1cf5 | 6817 | { |
367b1cf5 BS |
6818 | rtx insn = chain->insn; |
6819 | rtx old = (rl->in && GET_CODE (rl->in) == MEM | |
6820 | ? rl->in_reg : rl->in); | |
6821 | ||
6822 | if (old != 0 | |
6823 | /* AUTO_INC reloads need to be handled even if inherited. We got an | |
6824 | AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ | |
6825 | && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) | |
6826 | && ! rtx_equal_p (rl->reg_rtx, old) | |
6827 | && rl->reg_rtx != 0) | |
1d813780 | 6828 | emit_input_reload_insns (chain, rld + j, old, j); |
32131a9c | 6829 | |
367b1cf5 BS |
6830 | /* When inheriting a wider reload, we have a MEM in rl->in, |
6831 | e.g. inheriting a SImode output reload for | |
6832 | (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ | |
6833 | if (optimize && reload_inherited[j] && rl->in | |
6834 | && GET_CODE (rl->in) == MEM | |
6835 | && GET_CODE (rl->in_reg) == MEM | |
6836 | && reload_spill_index[j] >= 0 | |
6837 | && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) | |
4977bab6 | 6838 | rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; |
32131a9c | 6839 | |
367b1cf5 BS |
6840 | /* If we are reloading a register that was recently stored in with an |
6841 | output-reload, see if we can prove there was | |
6842 | actually no need to store the old value in it. */ | |
32131a9c | 6843 | |
367b1cf5 BS |
6844 | if (optimize |
6845 | && (reload_inherited[j] || reload_override_in[j]) | |
6846 | && rl->reg_rtx | |
6847 | && GET_CODE (rl->reg_rtx) == REG | |
6848 | && spill_reg_store[REGNO (rl->reg_rtx)] != 0 | |
6849 | #if 0 | |
6850 | /* There doesn't seem to be any reason to restrict this to pseudos | |
6851 | and doing so loses in the case where we are copying from a | |
6852 | register of the wrong class. */ | |
6853 | && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6854 | >= FIRST_PSEUDO_REGISTER) | |
6855 | #endif | |
6856 | /* The insn might have already some references to stackslots | |
6857 | replaced by MEMs, while reload_out_reg still names the | |
6858 | original pseudo. */ | |
6859 | && (dead_or_set_p (insn, | |
6860 | spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6861 | || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], | |
6862 | rl->out_reg))) | |
6863 | delete_output_reload (insn, j, REGNO (rl->reg_rtx)); | |
6864 | } | |
32131a9c | 6865 | |
367b1cf5 BS |
6866 | /* Do output reloading for reload RL, which is for the insn described by |
6867 | CHAIN and has the number J. | |
6868 | ??? At some point we need to support handling output reloads of | |
6869 | JUMP_INSNs or insns that set cc0. */ | |
6870 | static void | |
0c20a65f | 6871 | do_output_reload (struct insn_chain *chain, struct reload *rl, int j) |
367b1cf5 BS |
6872 | { |
6873 | rtx note, old; | |
6874 | rtx insn = chain->insn; | |
6875 | /* If this is an output reload that stores something that is | |
6876 | not loaded in this same reload, see if we can eliminate a previous | |
6877 | store. */ | |
6878 | rtx pseudo = rl->out_reg; | |
6879 | ||
6880 | if (pseudo | |
159d5964 | 6881 | && optimize |
367b1cf5 BS |
6882 | && GET_CODE (pseudo) == REG |
6883 | && ! rtx_equal_p (rl->in_reg, pseudo) | |
6884 | && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER | |
6885 | && reg_last_reload_reg[REGNO (pseudo)]) | |
6886 | { | |
6887 | int pseudo_no = REGNO (pseudo); | |
6888 | int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); | |
6889 | ||
6890 | /* We don't need to test full validity of last_regno for | |
6891 | inherit here; we only want to know if the store actually | |
6892 | matches the pseudo. */ | |
60ef417d GK |
6893 | if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno) |
6894 | && reg_reloaded_contents[last_regno] == pseudo_no | |
367b1cf5 BS |
6895 | && spill_reg_store[last_regno] |
6896 | && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) | |
6897 | delete_output_reload (insn, j, last_regno); | |
6898 | } | |
5e03c156 | 6899 | |
367b1cf5 BS |
6900 | old = rl->out_reg; |
6901 | if (old == 0 | |
6902 | || rl->reg_rtx == old | |
6903 | || rl->reg_rtx == 0) | |
6904 | return; | |
32131a9c | 6905 | |
367b1cf5 BS |
6906 | /* An output operand that dies right away does need a reload, |
6907 | but need not be copied from it. Show the new location in the | |
6908 | REG_UNUSED note. */ | |
6909 | if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) | |
6910 | && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) | |
6911 | { | |
6912 | XEXP (note, 0) = rl->reg_rtx; | |
6913 | return; | |
6914 | } | |
6915 | /* Likewise for a SUBREG of an operand that dies. */ | |
6916 | else if (GET_CODE (old) == SUBREG | |
6917 | && GET_CODE (SUBREG_REG (old)) == REG | |
6918 | && 0 != (note = find_reg_note (insn, REG_UNUSED, | |
6919 | SUBREG_REG (old)))) | |
6920 | { | |
6921 | XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), | |
6922 | rl->reg_rtx); | |
6923 | return; | |
6924 | } | |
6925 | else if (GET_CODE (old) == SCRATCH) | |
6926 | /* If we aren't optimizing, there won't be a REG_UNUSED note, | |
6927 | but we don't want to make an output reload. */ | |
6928 | return; | |
1554c2c6 | 6929 | |
367b1cf5 BS |
6930 | /* If is a JUMP_INSN, we can't support output reloads yet. */ |
6931 | if (GET_CODE (insn) == JUMP_INSN) | |
6932 | abort (); | |
5e03c156 | 6933 | |
367b1cf5 BS |
6934 | emit_output_reload_insns (chain, rld + j, j); |
6935 | } | |
1554c2c6 | 6936 | |
367b1cf5 | 6937 | /* Output insns to reload values in and out of the chosen reload regs. */ |
32131a9c | 6938 | |
367b1cf5 | 6939 | static void |
0c20a65f | 6940 | emit_reload_insns (struct insn_chain *chain) |
367b1cf5 BS |
6941 | { |
6942 | rtx insn = chain->insn; | |
32131a9c | 6943 | |
b3694847 | 6944 | int j; |
e6e52be0 | 6945 | |
367b1cf5 | 6946 | CLEAR_HARD_REG_SET (reg_reloaded_died); |
e6e52be0 | 6947 | |
367b1cf5 BS |
6948 | for (j = 0; j < reload_n_operands; j++) |
6949 | input_reload_insns[j] = input_address_reload_insns[j] | |
6950 | = inpaddr_address_reload_insns[j] | |
6951 | = output_reload_insns[j] = output_address_reload_insns[j] | |
6952 | = outaddr_address_reload_insns[j] | |
6953 | = other_output_reload_insns[j] = 0; | |
6954 | other_input_address_reload_insns = 0; | |
6955 | other_input_reload_insns = 0; | |
6956 | operand_reload_insns = 0; | |
6957 | other_operand_reload_insns = 0; | |
32131a9c | 6958 | |
850aac53 | 6959 | /* Dump reloads into the dump file. */ |
c263766c | 6960 | if (dump_file) |
850aac53 | 6961 | { |
c263766c RH |
6962 | fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); |
6963 | debug_reload_to_stream (dump_file); | |
850aac53 JL |
6964 | } |
6965 | ||
367b1cf5 BS |
6966 | /* Now output the instructions to copy the data into and out of the |
6967 | reload registers. Do these in the order that the reloads were reported, | |
6968 | since reloads of base and index registers precede reloads of operands | |
6969 | and the operands may need the base and index registers reloaded. */ | |
32131a9c | 6970 | |
367b1cf5 BS |
6971 | for (j = 0; j < n_reloads; j++) |
6972 | { | |
6973 | if (rld[j].reg_rtx | |
6974 | && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER) | |
6975 | new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0; | |
d7e0324f | 6976 | |
367b1cf5 BS |
6977 | do_input_reload (chain, rld + j, j); |
6978 | do_output_reload (chain, rld + j, j); | |
32131a9c RK |
6979 | } |
6980 | ||
546b63fb RK |
6981 | /* Now write all the insns we made for reloads in the order expected by |
6982 | the allocation functions. Prior to the insn being reloaded, we write | |
6983 | the following reloads: | |
6984 | ||
6985 | RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. | |
6986 | ||
2edc8d65 | 6987 | RELOAD_OTHER reloads. |
546b63fb | 6988 | |
47c8cf91 ILT |
6989 | For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed |
6990 | by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the | |
6991 | RELOAD_FOR_INPUT reload for the operand. | |
546b63fb | 6992 | |
893bc853 RK |
6993 | RELOAD_FOR_OPADDR_ADDRS reloads. |
6994 | ||
546b63fb RK |
6995 | RELOAD_FOR_OPERAND_ADDRESS reloads. |
6996 | ||
6997 | After the insn being reloaded, we write the following: | |
6998 | ||
47c8cf91 ILT |
6999 | For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed |
7000 | by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the | |
7001 | RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output | |
7002 | reloads for the operand. The RELOAD_OTHER output reloads are | |
7003 | output in descending order by reload number. */ | |
546b63fb | 7004 | |
dd3adcf8 DJ |
7005 | emit_insn_before_sameloc (other_input_address_reload_insns, insn); |
7006 | emit_insn_before_sameloc (other_input_reload_insns, insn); | |
546b63fb RK |
7007 | |
7008 | for (j = 0; j < reload_n_operands; j++) | |
7009 | { | |
dd3adcf8 DJ |
7010 | emit_insn_before_sameloc (inpaddr_address_reload_insns[j], insn); |
7011 | emit_insn_before_sameloc (input_address_reload_insns[j], insn); | |
7012 | emit_insn_before_sameloc (input_reload_insns[j], insn); | |
546b63fb RK |
7013 | } |
7014 | ||
dd3adcf8 DJ |
7015 | emit_insn_before_sameloc (other_operand_reload_insns, insn); |
7016 | emit_insn_before_sameloc (operand_reload_insns, insn); | |
546b63fb RK |
7017 | |
7018 | for (j = 0; j < reload_n_operands; j++) | |
7019 | { | |
dd3adcf8 DJ |
7020 | rtx x = emit_insn_after_sameloc (outaddr_address_reload_insns[j], insn); |
7021 | x = emit_insn_after_sameloc (output_address_reload_insns[j], x); | |
7022 | x = emit_insn_after_sameloc (output_reload_insns[j], x); | |
7023 | emit_insn_after_sameloc (other_output_reload_insns[j], x); | |
546b63fb RK |
7024 | } |
7025 | ||
32131a9c RK |
7026 | /* For all the spill regs newly reloaded in this instruction, |
7027 | record what they were reloaded from, so subsequent instructions | |
d445b551 RK |
7028 | can inherit the reloads. |
7029 | ||
7030 | Update spill_reg_store for the reloads of this insn. | |
e9e79d69 | 7031 | Copy the elements that were updated in the loop above. */ |
32131a9c RK |
7032 | |
7033 | for (j = 0; j < n_reloads; j++) | |
7034 | { | |
b3694847 SS |
7035 | int r = reload_order[j]; |
7036 | int i = reload_spill_index[r]; | |
32131a9c | 7037 | |
78a2bc08 | 7038 | /* If this is a non-inherited input reload from a pseudo, we must |
05d10675 BS |
7039 | clear any memory of a previous store to the same pseudo. Only do |
7040 | something if there will not be an output reload for the pseudo | |
7041 | being reloaded. */ | |
eceef4c9 | 7042 | if (rld[r].in_reg != 0 |
05d10675 BS |
7043 | && ! (reload_inherited[r] || reload_override_in[r])) |
7044 | { | |
eceef4c9 | 7045 | rtx reg = rld[r].in_reg; |
78a2bc08 | 7046 | |
05d10675 | 7047 | if (GET_CODE (reg) == SUBREG) |
78a2bc08 | 7048 | reg = SUBREG_REG (reg); |
05d10675 BS |
7049 | |
7050 | if (GET_CODE (reg) == REG | |
78a2bc08 R |
7051 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER |
7052 | && ! reg_has_output_reload[REGNO (reg)]) | |
7053 | { | |
7054 | int nregno = REGNO (reg); | |
7055 | ||
7056 | if (reg_last_reload_reg[nregno]) | |
05d10675 BS |
7057 | { |
7058 | int last_regno = REGNO (reg_last_reload_reg[nregno]); | |
78a2bc08 | 7059 | |
05d10675 | 7060 | if (reg_reloaded_contents[last_regno] == nregno) |
78a2bc08 | 7061 | spill_reg_store[last_regno] = 0; |
05d10675 | 7062 | } |
78a2bc08 R |
7063 | } |
7064 | } | |
05d10675 | 7065 | |
e6e52be0 | 7066 | /* I is nonneg if this reload used a register. |
eceef4c9 | 7067 | If rld[r].reg_rtx is 0, this is an optional reload |
51f0c3b7 | 7068 | that we opted to ignore. */ |
d445b551 | 7069 | |
eceef4c9 | 7070 | if (i >= 0 && rld[r].reg_rtx != 0) |
32131a9c | 7071 | { |
66fd46b6 | 7072 | int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)]; |
32131a9c | 7073 | int k; |
51f0c3b7 JW |
7074 | int part_reaches_end = 0; |
7075 | int all_reaches_end = 1; | |
32131a9c | 7076 | |
51f0c3b7 JW |
7077 | /* For a multi register reload, we need to check if all or part |
7078 | of the value lives to the end. */ | |
32131a9c RK |
7079 | for (k = 0; k < nr; k++) |
7080 | { | |
eceef4c9 BS |
7081 | if (reload_reg_reaches_end_p (i + k, rld[r].opnum, |
7082 | rld[r].when_needed)) | |
51f0c3b7 JW |
7083 | part_reaches_end = 1; |
7084 | else | |
7085 | all_reaches_end = 0; | |
32131a9c RK |
7086 | } |
7087 | ||
51f0c3b7 JW |
7088 | /* Ignore reloads that don't reach the end of the insn in |
7089 | entirety. */ | |
7090 | if (all_reaches_end) | |
32131a9c | 7091 | { |
51f0c3b7 JW |
7092 | /* First, clear out memory of what used to be in this spill reg. |
7093 | If consecutive registers are used, clear them all. */ | |
d08ea79f | 7094 | |
32131a9c | 7095 | for (k = 0; k < nr; k++) |
e3e9336f | 7096 | { |
e6e52be0 | 7097 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
e3e9336f DJ |
7098 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k); |
7099 | } | |
d08ea79f | 7100 | |
51f0c3b7 | 7101 | /* Maybe the spill reg contains a copy of reload_out. */ |
eceef4c9 BS |
7102 | if (rld[r].out != 0 |
7103 | && (GET_CODE (rld[r].out) == REG | |
cb2afeb3 | 7104 | #ifdef AUTO_INC_DEC |
eceef4c9 | 7105 | || ! rld[r].out_reg |
cb2afeb3 | 7106 | #endif |
eceef4c9 | 7107 | || GET_CODE (rld[r].out_reg) == REG)) |
51f0c3b7 | 7108 | { |
eceef4c9 BS |
7109 | rtx out = (GET_CODE (rld[r].out) == REG |
7110 | ? rld[r].out | |
7111 | : rld[r].out_reg | |
7112 | ? rld[r].out_reg | |
7113 | /* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); | |
b3694847 | 7114 | int nregno = REGNO (out); |
51f0c3b7 | 7115 | int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
66fd46b6 JH |
7116 | : hard_regno_nregs[nregno] |
7117 | [GET_MODE (rld[r].reg_rtx)]); | |
51f0c3b7 JW |
7118 | |
7119 | spill_reg_store[i] = new_spill_reg_store[i]; | |
cb2afeb3 | 7120 | spill_reg_stored_to[i] = out; |
eceef4c9 | 7121 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
7122 | |
7123 | /* If NREGNO is a hard register, it may occupy more than | |
05d10675 | 7124 | one register. If it does, say what is in the |
51f0c3b7 JW |
7125 | rest of the registers assuming that both registers |
7126 | agree on how many words the object takes. If not, | |
7127 | invalidate the subsequent registers. */ | |
7128 | ||
7129 | if (nregno < FIRST_PSEUDO_REGISTER) | |
7130 | for (k = 1; k < nnr; k++) | |
7131 | reg_last_reload_reg[nregno + k] | |
7132 | = (nr == nnr | |
39d31de8 | 7133 | ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k] |
51f0c3b7 JW |
7134 | : 0); |
7135 | ||
7136 | /* Now do the inverse operation. */ | |
7137 | for (k = 0; k < nr; k++) | |
7138 | { | |
e6e52be0 R |
7139 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7140 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
7141 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
7142 | ? nregno | |
7143 | : nregno + k); | |
e6e52be0 R |
7144 | reg_reloaded_insn[i + k] = insn; |
7145 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
e3e9336f DJ |
7146 | if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out))) |
7147 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k); | |
51f0c3b7 JW |
7148 | } |
7149 | } | |
d08ea79f | 7150 | |
51f0c3b7 JW |
7151 | /* Maybe the spill reg contains a copy of reload_in. Only do |
7152 | something if there will not be an output reload for | |
7153 | the register being reloaded. */ | |
eceef4c9 BS |
7154 | else if (rld[r].out_reg == 0 |
7155 | && rld[r].in != 0 | |
7156 | && ((GET_CODE (rld[r].in) == REG | |
7157 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER | |
7158 | && ! reg_has_output_reload[REGNO (rld[r].in)]) | |
7159 | || (GET_CODE (rld[r].in_reg) == REG | |
7160 | && ! reg_has_output_reload[REGNO (rld[r].in_reg)])) | |
7161 | && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn))) | |
51f0c3b7 | 7162 | { |
b3694847 | 7163 | int nregno; |
51f0c3b7 | 7164 | int nnr; |
e3e9336f | 7165 | rtx in; |
d445b551 | 7166 | |
eceef4c9 BS |
7167 | if (GET_CODE (rld[r].in) == REG |
7168 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) | |
e3e9336f | 7169 | in = rld[r].in; |
eceef4c9 | 7170 | else if (GET_CODE (rld[r].in_reg) == REG) |
e3e9336f | 7171 | in = rld[r].in_reg; |
cb2afeb3 | 7172 | else |
e3e9336f DJ |
7173 | in = XEXP (rld[r].in_reg, 0); |
7174 | nregno = REGNO (in); | |
d08ea79f | 7175 | |
51f0c3b7 | 7176 | nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
66fd46b6 JH |
7177 | : hard_regno_nregs[nregno] |
7178 | [GET_MODE (rld[r].reg_rtx)]); | |
05d10675 | 7179 | |
eceef4c9 | 7180 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
7181 | |
7182 | if (nregno < FIRST_PSEUDO_REGISTER) | |
7183 | for (k = 1; k < nnr; k++) | |
7184 | reg_last_reload_reg[nregno + k] | |
7185 | = (nr == nnr | |
39d31de8 | 7186 | ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k] |
51f0c3b7 JW |
7187 | : 0); |
7188 | ||
7189 | /* Unless we inherited this reload, show we haven't | |
cb2afeb3 R |
7190 | recently done a store. |
7191 | Previous stores of inherited auto_inc expressions | |
7192 | also have to be discarded. */ | |
7193 | if (! reload_inherited[r] | |
eceef4c9 | 7194 | || (rld[r].out && ! rld[r].out_reg)) |
51f0c3b7 JW |
7195 | spill_reg_store[i] = 0; |
7196 | ||
7197 | for (k = 0; k < nr; k++) | |
7198 | { | |
e6e52be0 R |
7199 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7200 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
7201 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
7202 | ? nregno | |
7203 | : nregno + k); | |
e6e52be0 R |
7204 | reg_reloaded_insn[i + k] = insn; |
7205 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
e3e9336f DJ |
7206 | if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in))) |
7207 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k); | |
51f0c3b7 JW |
7208 | } |
7209 | } | |
7210 | } | |
d445b551 | 7211 | |
51f0c3b7 JW |
7212 | /* However, if part of the reload reaches the end, then we must |
7213 | invalidate the old info for the part that survives to the end. */ | |
7214 | else if (part_reaches_end) | |
7215 | { | |
546b63fb | 7216 | for (k = 0; k < nr; k++) |
e6e52be0 | 7217 | if (reload_reg_reaches_end_p (i + k, |
eceef4c9 BS |
7218 | rld[r].opnum, |
7219 | rld[r].when_needed)) | |
e6e52be0 | 7220 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
32131a9c RK |
7221 | } |
7222 | } | |
7223 | ||
7224 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
7225 | It's reenabled in 1.35 because supposedly nothing else | |
7226 | deals with this problem. */ | |
7227 | ||
7228 | /* If a register gets output-reloaded from a non-spill register, | |
7229 | that invalidates any previous reloaded copy of it. | |
7230 | But forget_old_reloads_1 won't get to see it, because | |
7231 | it thinks only about the original insn. So invalidate it here. */ | |
eceef4c9 BS |
7232 | if (i < 0 && rld[r].out != 0 |
7233 | && (GET_CODE (rld[r].out) == REG | |
7234 | || (GET_CODE (rld[r].out) == MEM | |
7235 | && GET_CODE (rld[r].out_reg) == REG))) | |
32131a9c | 7236 | { |
eceef4c9 BS |
7237 | rtx out = (GET_CODE (rld[r].out) == REG |
7238 | ? rld[r].out : rld[r].out_reg); | |
b3694847 | 7239 | int nregno = REGNO (out); |
c7093272 | 7240 | if (nregno >= FIRST_PSEUDO_REGISTER) |
cb2afeb3 | 7241 | { |
6a651371 | 7242 | rtx src_reg, store_insn = NULL_RTX; |
cb2afeb3 R |
7243 | |
7244 | reg_last_reload_reg[nregno] = 0; | |
7245 | ||
7246 | /* If we can find a hard register that is stored, record | |
7247 | the storing insn so that we may delete this insn with | |
7248 | delete_output_reload. */ | |
eceef4c9 | 7249 | src_reg = rld[r].reg_rtx; |
cb2afeb3 R |
7250 | |
7251 | /* If this is an optional reload, try to find the source reg | |
7252 | from an input reload. */ | |
7253 | if (! src_reg) | |
7254 | { | |
7255 | rtx set = single_set (insn); | |
eceef4c9 | 7256 | if (set && SET_DEST (set) == rld[r].out) |
cb2afeb3 R |
7257 | { |
7258 | int k; | |
7259 | ||
7260 | src_reg = SET_SRC (set); | |
7261 | store_insn = insn; | |
7262 | for (k = 0; k < n_reloads; k++) | |
7263 | { | |
eceef4c9 | 7264 | if (rld[k].in == src_reg) |
cb2afeb3 | 7265 | { |
eceef4c9 | 7266 | src_reg = rld[k].reg_rtx; |
cb2afeb3 R |
7267 | break; |
7268 | } | |
7269 | } | |
7270 | } | |
7271 | } | |
7272 | else | |
7273 | store_insn = new_spill_reg_store[REGNO (src_reg)]; | |
7274 | if (src_reg && GET_CODE (src_reg) == REG | |
7275 | && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) | |
7276 | { | |
7277 | int src_regno = REGNO (src_reg); | |
66fd46b6 | 7278 | int nr = hard_regno_nregs[src_regno][rld[r].mode]; |
cb2afeb3 R |
7279 | /* The place where to find a death note varies with |
7280 | PRESERVE_DEATH_INFO_REGNO_P . The condition is not | |
7281 | necessarily checked exactly in the code that moves | |
7282 | notes, so just check both locations. */ | |
7283 | rtx note = find_regno_note (insn, REG_DEAD, src_regno); | |
1558b970 | 7284 | if (! note && store_insn) |
cb2afeb3 R |
7285 | note = find_regno_note (store_insn, REG_DEAD, src_regno); |
7286 | while (nr-- > 0) | |
7287 | { | |
7288 | spill_reg_store[src_regno + nr] = store_insn; | |
7289 | spill_reg_stored_to[src_regno + nr] = out; | |
7290 | reg_reloaded_contents[src_regno + nr] = nregno; | |
7291 | reg_reloaded_insn[src_regno + nr] = store_insn; | |
00f9f1bc | 7292 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr); |
cb2afeb3 | 7293 | SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr); |
e3e9336f DJ |
7294 | if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr, |
7295 | GET_MODE (src_reg))) | |
7296 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, | |
7297 | src_regno + nr); | |
cb2afeb3 R |
7298 | SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr); |
7299 | if (note) | |
7300 | SET_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7301 | else | |
7302 | CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7303 | } | |
7304 | reg_last_reload_reg[nregno] = src_reg; | |
7305 | } | |
7306 | } | |
c7093272 RK |
7307 | else |
7308 | { | |
66fd46b6 | 7309 | int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)]; |
36281332 | 7310 | |
c7093272 RK |
7311 | while (num_regs-- > 0) |
7312 | reg_last_reload_reg[nregno + num_regs] = 0; | |
7313 | } | |
32131a9c RK |
7314 | } |
7315 | } | |
e6e52be0 | 7316 | IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); |
32131a9c RK |
7317 | } |
7318 | \f | |
5e03c156 RK |
7319 | /* Emit code to perform a reload from IN (which may be a reload register) to |
7320 | OUT (which may also be a reload register). IN or OUT is from operand | |
05d10675 | 7321 | OPNUM with reload type TYPE. |
546b63fb | 7322 | |
3c3eeea6 | 7323 | Returns first insn emitted. */ |
32131a9c RK |
7324 | |
7325 | rtx | |
0c20a65f | 7326 | gen_reload (rtx out, rtx in, int opnum, enum reload_type type) |
32131a9c | 7327 | { |
546b63fb | 7328 | rtx last = get_last_insn (); |
7a5b18b0 RK |
7329 | rtx tem; |
7330 | ||
7331 | /* If IN is a paradoxical SUBREG, remove it and try to put the | |
7332 | opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ | |
7333 | if (GET_CODE (in) == SUBREG | |
7334 | && (GET_MODE_SIZE (GET_MODE (in)) | |
7335 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
7336 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) | |
7337 | in = SUBREG_REG (in), out = tem; | |
7338 | else if (GET_CODE (out) == SUBREG | |
eceef4c9 BS |
7339 | && (GET_MODE_SIZE (GET_MODE (out)) |
7340 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
7341 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) | |
7a5b18b0 | 7342 | out = SUBREG_REG (out), in = tem; |
32131a9c | 7343 | |
a8fdc208 | 7344 | /* How to do this reload can get quite tricky. Normally, we are being |
32131a9c RK |
7345 | asked to reload a simple operand, such as a MEM, a constant, or a pseudo |
7346 | register that didn't get a hard register. In that case we can just | |
7347 | call emit_move_insn. | |
7348 | ||
a7fd196c JW |
7349 | We can also be asked to reload a PLUS that adds a register or a MEM to |
7350 | another register, constant or MEM. This can occur during frame pointer | |
7351 | elimination and while reloading addresses. This case is handled by | |
7352 | trying to emit a single insn to perform the add. If it is not valid, | |
7353 | we use a two insn sequence. | |
32131a9c RK |
7354 | |
7355 | Finally, we could be called to handle an 'o' constraint by putting | |
7356 | an address into a register. In that case, we first try to do this | |
7357 | with a named pattern of "reload_load_address". If no such pattern | |
7358 | exists, we just emit a SET insn and hope for the best (it will normally | |
7359 | be valid on machines that use 'o'). | |
7360 | ||
7361 | This entire process is made complex because reload will never | |
7362 | process the insns we generate here and so we must ensure that | |
7363 | they will fit their constraints and also by the fact that parts of | |
7364 | IN might be being reloaded separately and replaced with spill registers. | |
7365 | Because of this, we are, in some sense, just guessing the right approach | |
7366 | here. The one listed above seems to work. | |
7367 | ||
7368 | ??? At some point, this whole thing needs to be rethought. */ | |
7369 | ||
7370 | if (GET_CODE (in) == PLUS | |
a7fd196c | 7371 | && (GET_CODE (XEXP (in, 0)) == REG |
5c6b1bd2 | 7372 | || GET_CODE (XEXP (in, 0)) == SUBREG |
a7fd196c JW |
7373 | || GET_CODE (XEXP (in, 0)) == MEM) |
7374 | && (GET_CODE (XEXP (in, 1)) == REG | |
5c6b1bd2 | 7375 | || GET_CODE (XEXP (in, 1)) == SUBREG |
a7fd196c JW |
7376 | || CONSTANT_P (XEXP (in, 1)) |
7377 | || GET_CODE (XEXP (in, 1)) == MEM)) | |
32131a9c | 7378 | { |
a7fd196c JW |
7379 | /* We need to compute the sum of a register or a MEM and another |
7380 | register, constant, or MEM, and put it into the reload | |
3002e160 JW |
7381 | register. The best possible way of doing this is if the machine |
7382 | has a three-operand ADD insn that accepts the required operands. | |
32131a9c RK |
7383 | |
7384 | The simplest approach is to try to generate such an insn and see if it | |
7385 | is recognized and matches its constraints. If so, it can be used. | |
7386 | ||
7387 | It might be better not to actually emit the insn unless it is valid, | |
0009eff2 | 7388 | but we need to pass the insn as an operand to `recog' and |
0eadeb15 | 7389 | `extract_insn' and it is simpler to emit and then delete the insn if |
0009eff2 | 7390 | not valid than to dummy things up. */ |
a8fdc208 | 7391 | |
af929c62 | 7392 | rtx op0, op1, tem, insn; |
32131a9c | 7393 | int code; |
a8fdc208 | 7394 | |
af929c62 RK |
7395 | op0 = find_replacement (&XEXP (in, 0)); |
7396 | op1 = find_replacement (&XEXP (in, 1)); | |
7397 | ||
32131a9c RK |
7398 | /* Since constraint checking is strict, commutativity won't be |
7399 | checked, so we need to do that here to avoid spurious failure | |
7400 | if the add instruction is two-address and the second operand | |
7401 | of the add is the same as the reload reg, which is frequently | |
7402 | the case. If the insn would be A = B + A, rearrange it so | |
0f41302f | 7403 | it will be A = A + B as constrain_operands expects. */ |
a8fdc208 | 7404 | |
32131a9c | 7405 | if (GET_CODE (XEXP (in, 1)) == REG |
5e03c156 | 7406 | && REGNO (out) == REGNO (XEXP (in, 1))) |
af929c62 RK |
7407 | tem = op0, op0 = op1, op1 = tem; |
7408 | ||
7409 | if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) | |
38a448ca | 7410 | in = gen_rtx_PLUS (GET_MODE (in), op0, op1); |
32131a9c | 7411 | |
38a448ca | 7412 | insn = emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7413 | code = recog_memoized (insn); |
7414 | ||
7415 | if (code >= 0) | |
7416 | { | |
0eadeb15 | 7417 | extract_insn (insn); |
32131a9c RK |
7418 | /* We want constrain operands to treat this insn strictly in |
7419 | its validity determination, i.e., the way it would after reload | |
7420 | has completed. */ | |
0eadeb15 | 7421 | if (constrain_operands (1)) |
32131a9c RK |
7422 | return insn; |
7423 | } | |
7424 | ||
546b63fb | 7425 | delete_insns_since (last); |
32131a9c RK |
7426 | |
7427 | /* If that failed, we must use a conservative two-insn sequence. | |
09522f21 FS |
7428 | |
7429 | Use a move to copy one operand into the reload register. Prefer | |
7430 | to reload a constant, MEM or pseudo since the move patterns can | |
7431 | handle an arbitrary operand. If OP1 is not a constant, MEM or | |
7432 | pseudo and OP1 is not a valid operand for an add instruction, then | |
7433 | reload OP1. | |
7434 | ||
7435 | After reloading one of the operands into the reload register, add | |
7436 | the reload register to the output register. | |
32131a9c RK |
7437 | |
7438 | If there is another way to do this for a specific machine, a | |
7439 | DEFINE_PEEPHOLE should be specified that recognizes the sequence | |
7440 | we emit below. */ | |
7441 | ||
09522f21 FS |
7442 | code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code; |
7443 | ||
5c6b1bd2 | 7444 | if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG |
af929c62 | 7445 | || (GET_CODE (op1) == REG |
09522f21 FS |
7446 | && REGNO (op1) >= FIRST_PSEUDO_REGISTER) |
7447 | || (code != CODE_FOR_nothing | |
a995e389 RH |
7448 | && ! ((*insn_data[code].operand[2].predicate) |
7449 | (op1, insn_data[code].operand[2].mode)))) | |
af929c62 | 7450 | tem = op0, op0 = op1, op1 = tem; |
32131a9c | 7451 | |
5c6b1bd2 | 7452 | gen_reload (out, op0, opnum, type); |
39b56c2a | 7453 | |
5e03c156 | 7454 | /* If OP0 and OP1 are the same, we can use OUT for OP1. |
39b56c2a RK |
7455 | This fixes a problem on the 32K where the stack pointer cannot |
7456 | be used as an operand of an add insn. */ | |
7457 | ||
7458 | if (rtx_equal_p (op0, op1)) | |
5e03c156 | 7459 | op1 = out; |
39b56c2a | 7460 | |
5e03c156 | 7461 | insn = emit_insn (gen_add2_insn (out, op1)); |
c77c9766 RK |
7462 | |
7463 | /* If that failed, copy the address register to the reload register. | |
0f41302f | 7464 | Then add the constant to the reload register. */ |
c77c9766 RK |
7465 | |
7466 | code = recog_memoized (insn); | |
7467 | ||
7468 | if (code >= 0) | |
7469 | { | |
0eadeb15 | 7470 | extract_insn (insn); |
c77c9766 RK |
7471 | /* We want constrain operands to treat this insn strictly in |
7472 | its validity determination, i.e., the way it would after reload | |
7473 | has completed. */ | |
0eadeb15 | 7474 | if (constrain_operands (1)) |
4117a96b R |
7475 | { |
7476 | /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ | |
7477 | REG_NOTES (insn) | |
9e6a5703 | 7478 | = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
4117a96b R |
7479 | return insn; |
7480 | } | |
c77c9766 RK |
7481 | } |
7482 | ||
7483 | delete_insns_since (last); | |
7484 | ||
5c6b1bd2 | 7485 | gen_reload (out, op1, opnum, type); |
4117a96b | 7486 | insn = emit_insn (gen_add2_insn (out, op0)); |
9e6a5703 | 7487 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
32131a9c RK |
7488 | } |
7489 | ||
0dadecf6 RK |
7490 | #ifdef SECONDARY_MEMORY_NEEDED |
7491 | /* If we need a memory location to do the move, do it that way. */ | |
344b78b8 JH |
7492 | else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG) |
7493 | && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER | |
7494 | && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG) | |
7495 | && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER | |
7496 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)), | |
7497 | REGNO_REG_CLASS (reg_or_subregno (out)), | |
5e03c156 | 7498 | GET_MODE (out))) |
0dadecf6 RK |
7499 | { |
7500 | /* Get the memory to use and rewrite both registers to its mode. */ | |
5e03c156 | 7501 | rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); |
0dadecf6 | 7502 | |
5e03c156 | 7503 | if (GET_MODE (loc) != GET_MODE (out)) |
38a448ca | 7504 | out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); |
0dadecf6 RK |
7505 | |
7506 | if (GET_MODE (loc) != GET_MODE (in)) | |
38a448ca | 7507 | in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); |
0dadecf6 | 7508 | |
5c6b1bd2 RK |
7509 | gen_reload (loc, in, opnum, type); |
7510 | gen_reload (out, loc, opnum, type); | |
0dadecf6 RK |
7511 | } |
7512 | #endif | |
7513 | ||
32131a9c | 7514 | /* If IN is a simple operand, use gen_move_insn. */ |
ec8e098d | 7515 | else if (OBJECT_P (in) || GET_CODE (in) == SUBREG) |
5e03c156 | 7516 | emit_insn (gen_move_insn (out, in)); |
32131a9c RK |
7517 | |
7518 | #ifdef HAVE_reload_load_address | |
7519 | else if (HAVE_reload_load_address) | |
5e03c156 | 7520 | emit_insn (gen_reload_load_address (out, in)); |
32131a9c RK |
7521 | #endif |
7522 | ||
5e03c156 | 7523 | /* Otherwise, just write (set OUT IN) and hope for the best. */ |
32131a9c | 7524 | else |
38a448ca | 7525 | emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7526 | |
7527 | /* Return the first insn emitted. | |
546b63fb | 7528 | We can not just return get_last_insn, because there may have |
32131a9c RK |
7529 | been multiple instructions emitted. Also note that gen_move_insn may |
7530 | emit more than one insn itself, so we can not assume that there is one | |
7531 | insn emitted per emit_insn_before call. */ | |
7532 | ||
546b63fb | 7533 | return last ? NEXT_INSN (last) : get_insns (); |
32131a9c RK |
7534 | } |
7535 | \f | |
cda94cbb RH |
7536 | /* Delete a previously made output-reload whose result we now believe |
7537 | is not needed. First we double-check. | |
32131a9c RK |
7538 | |
7539 | INSN is the insn now being processed. | |
cb2afeb3 R |
7540 | LAST_RELOAD_REG is the hard register number for which we want to delete |
7541 | the last output reload. | |
7542 | J is the reload-number that originally used REG. The caller has made | |
7543 | certain that reload J doesn't use REG any longer for input. */ | |
32131a9c RK |
7544 | |
7545 | static void | |
0c20a65f | 7546 | delete_output_reload (rtx insn, int j, int last_reload_reg) |
32131a9c | 7547 | { |
cb2afeb3 R |
7548 | rtx output_reload_insn = spill_reg_store[last_reload_reg]; |
7549 | rtx reg = spill_reg_stored_to[last_reload_reg]; | |
7550 | int k; | |
7551 | int n_occurrences; | |
7552 | int n_inherited = 0; | |
b3694847 | 7553 | rtx i1; |
cb2afeb3 | 7554 | rtx substed; |
05d10675 | 7555 | |
068f5dea JH |
7556 | /* It is possible that this reload has been only used to set another reload |
7557 | we eliminated earlier and thus deleted this instruction too. */ | |
7558 | if (INSN_DELETED_P (output_reload_insn)) | |
7559 | return; | |
7560 | ||
32131a9c RK |
7561 | /* Get the raw pseudo-register referred to. */ |
7562 | ||
32131a9c RK |
7563 | while (GET_CODE (reg) == SUBREG) |
7564 | reg = SUBREG_REG (reg); | |
cb2afeb3 R |
7565 | substed = reg_equiv_memory_loc[REGNO (reg)]; |
7566 | ||
7567 | /* This is unsafe if the operand occurs more often in the current | |
7568 | insn than it is inherited. */ | |
7569 | for (k = n_reloads - 1; k >= 0; k--) | |
7570 | { | |
eceef4c9 | 7571 | rtx reg2 = rld[k].in; |
cb2afeb3 R |
7572 | if (! reg2) |
7573 | continue; | |
7574 | if (GET_CODE (reg2) == MEM || reload_override_in[k]) | |
eceef4c9 | 7575 | reg2 = rld[k].in_reg; |
cb2afeb3 | 7576 | #ifdef AUTO_INC_DEC |
eceef4c9 BS |
7577 | if (rld[k].out && ! rld[k].out_reg) |
7578 | reg2 = XEXP (rld[k].in_reg, 0); | |
cb2afeb3 R |
7579 | #endif |
7580 | while (GET_CODE (reg2) == SUBREG) | |
7581 | reg2 = SUBREG_REG (reg2); | |
7582 | if (rtx_equal_p (reg2, reg)) | |
2eb6dac7 AS |
7583 | { |
7584 | if (reload_inherited[k] || reload_override_in[k] || k == j) | |
7585 | { | |
cb2afeb3 | 7586 | n_inherited++; |
eceef4c9 | 7587 | reg2 = rld[k].out_reg; |
2eb6dac7 AS |
7588 | if (! reg2) |
7589 | continue; | |
7590 | while (GET_CODE (reg2) == SUBREG) | |
7591 | reg2 = XEXP (reg2, 0); | |
7592 | if (rtx_equal_p (reg2, reg)) | |
7593 | n_inherited++; | |
7594 | } | |
7595 | else | |
7596 | return; | |
7597 | } | |
cb2afeb3 | 7598 | } |
4b983fdc | 7599 | n_occurrences = count_occurrences (PATTERN (insn), reg, 0); |
cb2afeb3 | 7600 | if (substed) |
5d7ef82a BS |
7601 | n_occurrences += count_occurrences (PATTERN (insn), |
7602 | eliminate_regs (substed, 0, | |
7603 | NULL_RTX), 0); | |
cb2afeb3 R |
7604 | if (n_occurrences > n_inherited) |
7605 | return; | |
32131a9c RK |
7606 | |
7607 | /* If the pseudo-reg we are reloading is no longer referenced | |
7608 | anywhere between the store into it and here, | |
7609 | and no jumps or labels intervene, then the value can get | |
7610 | here through the reload reg alone. | |
7611 | Otherwise, give up--return. */ | |
7612 | for (i1 = NEXT_INSN (output_reload_insn); | |
7613 | i1 != insn; i1 = NEXT_INSN (i1)) | |
7614 | { | |
7615 | if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) | |
7616 | return; | |
7617 | if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) | |
7618 | && reg_mentioned_p (reg, PATTERN (i1))) | |
aa6498c2 | 7619 | { |
cb2afeb3 R |
7620 | /* If this is USE in front of INSN, we only have to check that |
7621 | there are no more references than accounted for by inheritance. */ | |
7622 | while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE) | |
aa6498c2 | 7623 | { |
cb2afeb3 | 7624 | n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; |
aa6498c2 R |
7625 | i1 = NEXT_INSN (i1); |
7626 | } | |
cb2afeb3 | 7627 | if (n_occurrences <= n_inherited && i1 == insn) |
aa6498c2 R |
7628 | break; |
7629 | return; | |
7630 | } | |
32131a9c RK |
7631 | } |
7632 | ||
cda94cbb | 7633 | /* We will be deleting the insn. Remove the spill reg information. */ |
66fd46b6 | 7634 | for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; ) |
cda94cbb RH |
7635 | { |
7636 | spill_reg_store[last_reload_reg + k] = 0; | |
7637 | spill_reg_stored_to[last_reload_reg + k] = 0; | |
7638 | } | |
7639 | ||
aa6498c2 | 7640 | /* The caller has already checked that REG dies or is set in INSN. |
cda94cbb | 7641 | It has also checked that we are optimizing, and thus some |
14b493d6 | 7642 | inaccuracies in the debugging information are acceptable. |
cda94cbb RH |
7643 | So we could just delete output_reload_insn. But in some cases |
7644 | we can improve the debugging information without sacrificing | |
7645 | optimization - maybe even improving the code: See if the pseudo | |
7646 | reg has been completely replaced with reload regs. If so, delete | |
7647 | the store insn and forget we had a stack slot for the pseudo. */ | |
eceef4c9 | 7648 | if (rld[j].out != rld[j].in |
aa6498c2 | 7649 | && REG_N_DEATHS (REGNO (reg)) == 1 |
a3a24aa6 | 7650 | && REG_N_SETS (REGNO (reg)) == 1 |
aa6498c2 R |
7651 | && REG_BASIC_BLOCK (REGNO (reg)) >= 0 |
7652 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) | |
32131a9c RK |
7653 | { |
7654 | rtx i2; | |
7655 | ||
cda94cbb RH |
7656 | /* We know that it was used only between here and the beginning of |
7657 | the current basic block. (We also know that the last use before | |
7658 | INSN was the output reload we are thinking of deleting, but never | |
7659 | mind that.) Search that range; see if any ref remains. */ | |
32131a9c RK |
7660 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) |
7661 | { | |
d445b551 RK |
7662 | rtx set = single_set (i2); |
7663 | ||
32131a9c RK |
7664 | /* Uses which just store in the pseudo don't count, |
7665 | since if they are the only uses, they are dead. */ | |
d445b551 | 7666 | if (set != 0 && SET_DEST (set) == reg) |
32131a9c RK |
7667 | continue; |
7668 | if (GET_CODE (i2) == CODE_LABEL | |
7669 | || GET_CODE (i2) == JUMP_INSN) | |
7670 | break; | |
7671 | if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) | |
7672 | && reg_mentioned_p (reg, PATTERN (i2))) | |
aa6498c2 R |
7673 | { |
7674 | /* Some other ref remains; just delete the output reload we | |
7675 | know to be dead. */ | |
cb2afeb3 | 7676 | delete_address_reloads (output_reload_insn, insn); |
ca6c03ca | 7677 | delete_insn (output_reload_insn); |
aa6498c2 R |
7678 | return; |
7679 | } | |
32131a9c RK |
7680 | } |
7681 | ||
cda94cbb RH |
7682 | /* Delete the now-dead stores into this pseudo. Note that this |
7683 | loop also takes care of deleting output_reload_insn. */ | |
32131a9c RK |
7684 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) |
7685 | { | |
d445b551 RK |
7686 | rtx set = single_set (i2); |
7687 | ||
7688 | if (set != 0 && SET_DEST (set) == reg) | |
5507b94b | 7689 | { |
cb2afeb3 | 7690 | delete_address_reloads (i2, insn); |
ca6c03ca | 7691 | delete_insn (i2); |
5507b94b | 7692 | } |
32131a9c RK |
7693 | if (GET_CODE (i2) == CODE_LABEL |
7694 | || GET_CODE (i2) == JUMP_INSN) | |
7695 | break; | |
7696 | } | |
7697 | ||
cda94cbb | 7698 | /* For the debugging info, say the pseudo lives in this reload reg. */ |
eceef4c9 | 7699 | reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx); |
32131a9c RK |
7700 | alter_reg (REGNO (reg), -1); |
7701 | } | |
cda94cbb RH |
7702 | else |
7703 | { | |
7704 | delete_address_reloads (output_reload_insn, insn); | |
7705 | delete_insn (output_reload_insn); | |
7706 | } | |
cb2afeb3 R |
7707 | } |
7708 | ||
7709 | /* We are going to delete DEAD_INSN. Recursively delete loads of | |
7710 | reload registers used in DEAD_INSN that are not used till CURRENT_INSN. | |
7711 | CURRENT_INSN is being reloaded, so we have to check its reloads too. */ | |
7712 | static void | |
0c20a65f | 7713 | delete_address_reloads (rtx dead_insn, rtx current_insn) |
cb2afeb3 R |
7714 | { |
7715 | rtx set = single_set (dead_insn); | |
7716 | rtx set2, dst, prev, next; | |
7717 | if (set) | |
7718 | { | |
7719 | rtx dst = SET_DEST (set); | |
7720 | if (GET_CODE (dst) == MEM) | |
7721 | delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); | |
7722 | } | |
7723 | /* If we deleted the store from a reloaded post_{in,de}c expression, | |
7724 | we can delete the matching adds. */ | |
7725 | prev = PREV_INSN (dead_insn); | |
7726 | next = NEXT_INSN (dead_insn); | |
7727 | if (! prev || ! next) | |
7728 | return; | |
7729 | set = single_set (next); | |
7730 | set2 = single_set (prev); | |
7731 | if (! set || ! set2 | |
7732 | || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS | |
7733 | || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT | |
7734 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT) | |
7735 | return; | |
7736 | dst = SET_DEST (set); | |
7737 | if (! rtx_equal_p (dst, SET_DEST (set2)) | |
7738 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) | |
7739 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) | |
7740 | || (INTVAL (XEXP (SET_SRC (set), 1)) | |
1d7254c5 | 7741 | != -INTVAL (XEXP (SET_SRC (set2), 1)))) |
cb2afeb3 | 7742 | return; |
53c17031 JH |
7743 | delete_related_insns (prev); |
7744 | delete_related_insns (next); | |
cb2afeb3 R |
7745 | } |
7746 | ||
7747 | /* Subfunction of delete_address_reloads: process registers found in X. */ | |
7748 | static void | |
0c20a65f | 7749 | delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn) |
cb2afeb3 R |
7750 | { |
7751 | rtx prev, set, dst, i2; | |
7752 | int i, j; | |
7753 | enum rtx_code code = GET_CODE (x); | |
7754 | ||
7755 | if (code != REG) | |
7756 | { | |
1d7254c5 | 7757 | const char *fmt = GET_RTX_FORMAT (code); |
cb2afeb3 R |
7758 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
7759 | { | |
7760 | if (fmt[i] == 'e') | |
7761 | delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); | |
7762 | else if (fmt[i] == 'E') | |
7763 | { | |
1d7254c5 | 7764 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
cb2afeb3 R |
7765 | delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), |
7766 | current_insn); | |
7767 | } | |
7768 | } | |
7769 | return; | |
7770 | } | |
7771 | ||
7772 | if (spill_reg_order[REGNO (x)] < 0) | |
7773 | return; | |
aa6498c2 | 7774 | |
cb2afeb3 R |
7775 | /* Scan backwards for the insn that sets x. This might be a way back due |
7776 | to inheritance. */ | |
7777 | for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) | |
7778 | { | |
7779 | code = GET_CODE (prev); | |
7780 | if (code == CODE_LABEL || code == JUMP_INSN) | |
7781 | return; | |
ec8e098d | 7782 | if (!INSN_P (prev)) |
cb2afeb3 R |
7783 | continue; |
7784 | if (reg_set_p (x, PATTERN (prev))) | |
7785 | break; | |
7786 | if (reg_referenced_p (x, PATTERN (prev))) | |
7787 | return; | |
7788 | } | |
7789 | if (! prev || INSN_UID (prev) < reload_first_uid) | |
7790 | return; | |
7791 | /* Check that PREV only sets the reload register. */ | |
7792 | set = single_set (prev); | |
7793 | if (! set) | |
7794 | return; | |
7795 | dst = SET_DEST (set); | |
7796 | if (GET_CODE (dst) != REG | |
7797 | || ! rtx_equal_p (dst, x)) | |
7798 | return; | |
7799 | if (! reg_set_p (dst, PATTERN (dead_insn))) | |
7800 | { | |
7801 | /* Check if DST was used in a later insn - | |
7802 | it might have been inherited. */ | |
7803 | for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) | |
7804 | { | |
7805 | if (GET_CODE (i2) == CODE_LABEL) | |
7806 | break; | |
2c3c49de | 7807 | if (! INSN_P (i2)) |
cb2afeb3 R |
7808 | continue; |
7809 | if (reg_referenced_p (dst, PATTERN (i2))) | |
7810 | { | |
7811 | /* If there is a reference to the register in the current insn, | |
7812 | it might be loaded in a non-inherited reload. If no other | |
7813 | reload uses it, that means the register is set before | |
7814 | referenced. */ | |
7815 | if (i2 == current_insn) | |
7816 | { | |
7817 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7818 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7819 | || reload_override_in[j] == dst) |
7820 | return; | |
7821 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7822 | if (rld[j].in && rld[j].reg_rtx == dst) |
cb2afeb3 R |
7823 | break; |
7824 | if (j >= 0) | |
7825 | break; | |
7826 | } | |
7827 | return; | |
7828 | } | |
7829 | if (GET_CODE (i2) == JUMP_INSN) | |
7830 | break; | |
cb2afeb3 | 7831 | /* If DST is still live at CURRENT_INSN, check if it is used for |
3900dc09 R |
7832 | any reload. Note that even if CURRENT_INSN sets DST, we still |
7833 | have to check the reloads. */ | |
cb2afeb3 R |
7834 | if (i2 == current_insn) |
7835 | { | |
7836 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7837 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7838 | || reload_override_in[j] == dst) |
7839 | return; | |
7840 | /* ??? We can't finish the loop here, because dst might be | |
7841 | allocated to a pseudo in this block if no reload in this | |
14b493d6 | 7842 | block needs any of the classes containing DST - see |
cb2afeb3 R |
7843 | spill_hard_reg. There is no easy way to tell this, so we |
7844 | have to scan till the end of the basic block. */ | |
7845 | } | |
3900dc09 R |
7846 | if (reg_set_p (dst, PATTERN (i2))) |
7847 | break; | |
cb2afeb3 R |
7848 | } |
7849 | } | |
7850 | delete_address_reloads_1 (prev, SET_SRC (set), current_insn); | |
7851 | reg_reloaded_contents[REGNO (dst)] = -1; | |
ca6c03ca | 7852 | delete_insn (prev); |
32131a9c | 7853 | } |
32131a9c | 7854 | \f |
a8fdc208 | 7855 | /* Output reload-insns to reload VALUE into RELOADREG. |
858a47b1 | 7856 | VALUE is an autoincrement or autodecrement RTX whose operand |
32131a9c RK |
7857 | is a register or memory location; |
7858 | so reloading involves incrementing that location. | |
cb2afeb3 | 7859 | IN is either identical to VALUE, or some cheaper place to reload from. |
32131a9c RK |
7860 | |
7861 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
cb2afeb3 | 7862 | This cannot be deduced from VALUE. |
32131a9c | 7863 | |
cb2afeb3 R |
7864 | Return the instruction that stores into RELOADREG. */ |
7865 | ||
7866 | static rtx | |
0c20a65f | 7867 | inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount) |
32131a9c RK |
7868 | { |
7869 | /* REG or MEM to be copied and incremented. */ | |
7870 | rtx incloc = XEXP (value, 0); | |
7871 | /* Nonzero if increment after copying. */ | |
7872 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); | |
546b63fb | 7873 | rtx last; |
0009eff2 RK |
7874 | rtx inc; |
7875 | rtx add_insn; | |
7876 | int code; | |
cb2afeb3 R |
7877 | rtx store; |
7878 | rtx real_in = in == value ? XEXP (in, 0) : in; | |
32131a9c RK |
7879 | |
7880 | /* No hard register is equivalent to this register after | |
40f03658 | 7881 | inc/dec operation. If REG_LAST_RELOAD_REG were nonzero, |
32131a9c RK |
7882 | we could inc/dec that register as well (maybe even using it for |
7883 | the source), but I'm not sure it's worth worrying about. */ | |
7884 | if (GET_CODE (incloc) == REG) | |
7885 | reg_last_reload_reg[REGNO (incloc)] = 0; | |
7886 | ||
7887 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
1d7254c5 | 7888 | inc_amount = -inc_amount; |
32131a9c | 7889 | |
fb3821f7 | 7890 | inc = GEN_INT (inc_amount); |
0009eff2 RK |
7891 | |
7892 | /* If this is post-increment, first copy the location to the reload reg. */ | |
cb2afeb3 R |
7893 | if (post && real_in != reloadreg) |
7894 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
0009eff2 | 7895 | |
cb2afeb3 R |
7896 | if (in == value) |
7897 | { | |
7898 | /* See if we can directly increment INCLOC. Use a method similar to | |
7899 | that in gen_reload. */ | |
0009eff2 | 7900 | |
cb2afeb3 R |
7901 | last = get_last_insn (); |
7902 | add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, | |
7903 | gen_rtx_PLUS (GET_MODE (incloc), | |
7904 | incloc, inc))); | |
05d10675 | 7905 | |
cb2afeb3 R |
7906 | code = recog_memoized (add_insn); |
7907 | if (code >= 0) | |
32131a9c | 7908 | { |
0eadeb15 BS |
7909 | extract_insn (add_insn); |
7910 | if (constrain_operands (1)) | |
cb2afeb3 R |
7911 | { |
7912 | /* If this is a pre-increment and we have incremented the value | |
7913 | where it lives, copy the incremented value to RELOADREG to | |
7914 | be used as an address. */ | |
0009eff2 | 7915 | |
cb2afeb3 R |
7916 | if (! post) |
7917 | emit_insn (gen_move_insn (reloadreg, incloc)); | |
546b63fb | 7918 | |
cb2afeb3 R |
7919 | return add_insn; |
7920 | } | |
32131a9c | 7921 | } |
cb2afeb3 | 7922 | delete_insns_since (last); |
32131a9c | 7923 | } |
0009eff2 | 7924 | |
0009eff2 RK |
7925 | /* If couldn't do the increment directly, must increment in RELOADREG. |
7926 | The way we do this depends on whether this is pre- or post-increment. | |
7927 | For pre-increment, copy INCLOC to the reload register, increment it | |
7928 | there, then save back. */ | |
7929 | ||
7930 | if (! post) | |
7931 | { | |
cb2afeb3 R |
7932 | if (in != reloadreg) |
7933 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
546b63fb | 7934 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7935 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
0009eff2 | 7936 | } |
32131a9c RK |
7937 | else |
7938 | { | |
0009eff2 RK |
7939 | /* Postincrement. |
7940 | Because this might be a jump insn or a compare, and because RELOADREG | |
7941 | may not be available after the insn in an input reload, we must do | |
7942 | the incrementation before the insn being reloaded for. | |
7943 | ||
cb2afeb3 | 7944 | We have already copied IN to RELOADREG. Increment the copy in |
0009eff2 RK |
7945 | RELOADREG, save that back, then decrement RELOADREG so it has |
7946 | the original value. */ | |
7947 | ||
546b63fb | 7948 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7949 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
546b63fb | 7950 | emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount))); |
32131a9c | 7951 | } |
0009eff2 | 7952 | |
cb2afeb3 | 7953 | return store; |
32131a9c RK |
7954 | } |
7955 | \f | |
2dfa9a87 MH |
7956 | #ifdef AUTO_INC_DEC |
7957 | static void | |
0c20a65f | 7958 | add_auto_inc_notes (rtx insn, rtx x) |
2dfa9a87 MH |
7959 | { |
7960 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 7961 | const char *fmt; |
2dfa9a87 MH |
7962 | int i, j; |
7963 | ||
7964 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
7965 | { | |
7966 | REG_NOTES (insn) | |
7967 | = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn)); | |
7968 | return; | |
7969 | } | |
7970 | ||
7971 | /* Scan all the operand sub-expressions. */ | |
7972 | fmt = GET_RTX_FORMAT (code); | |
7973 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7974 | { | |
7975 | if (fmt[i] == 'e') | |
7976 | add_auto_inc_notes (insn, XEXP (x, i)); | |
7977 | else if (fmt[i] == 'E') | |
7978 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
7979 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
7980 | } | |
7981 | } | |
7982 | #endif | |
94bd63e5 AH |
7983 | |
7984 | /* Copy EH notes from an insn to its reloads. */ | |
7985 | static void | |
0c20a65f | 7986 | copy_eh_notes (rtx insn, rtx x) |
94bd63e5 AH |
7987 | { |
7988 | rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
7989 | if (eh_note) | |
7990 | { | |
7991 | for (; x != 0; x = NEXT_INSN (x)) | |
7992 | { | |
7993 | if (may_trap_p (PATTERN (x))) | |
a6a2274a | 7994 | REG_NOTES (x) |
94bd63e5 AH |
7995 | = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0), |
7996 | REG_NOTES (x)); | |
7997 | } | |
7998 | } | |
7999 | } | |
8000 | ||
f1330226 JH |
8001 | /* This is used by reload pass, that does emit some instructions after |
8002 | abnormal calls moving basic block end, but in fact it wants to emit | |
8003 | them on the edge. Looks for abnormal call edges, find backward the | |
8004 | proper call and fix the damage. | |
a6a2274a | 8005 | |
f1330226 | 8006 | Similar handle instructions throwing exceptions internally. */ |
068473ec | 8007 | void |
0c20a65f | 8008 | fixup_abnormal_edges (void) |
f1330226 | 8009 | { |
f1330226 | 8010 | bool inserted = false; |
e0082a72 | 8011 | basic_block bb; |
f1330226 | 8012 | |
e0082a72 | 8013 | FOR_EACH_BB (bb) |
f1330226 | 8014 | { |
f1330226 JH |
8015 | edge e; |
8016 | ||
09da1532 | 8017 | /* Look for cases we are interested in - calls or instructions causing |
f1330226 JH |
8018 | exceptions. */ |
8019 | for (e = bb->succ; e; e = e->succ_next) | |
8020 | { | |
8021 | if (e->flags & EDGE_ABNORMAL_CALL) | |
8022 | break; | |
8023 | if ((e->flags & (EDGE_ABNORMAL | EDGE_EH)) | |
8024 | == (EDGE_ABNORMAL | EDGE_EH)) | |
8025 | break; | |
8026 | } | |
a813c111 SB |
8027 | if (e && GET_CODE (BB_END (bb)) != CALL_INSN |
8028 | && !can_throw_internal (BB_END (bb))) | |
f1330226 | 8029 | { |
a813c111 | 8030 | rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb)); |
f1330226 JH |
8031 | rtx next; |
8032 | for (e = bb->succ; e; e = e->succ_next) | |
8033 | if (e->flags & EDGE_FALLTHRU) | |
8034 | break; | |
39f95a2c JH |
8035 | /* Get past the new insns generated. Allow notes, as the insns may |
8036 | be already deleted. */ | |
8037 | while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE) | |
8038 | && !can_throw_internal (insn) | |
a813c111 | 8039 | && insn != BB_HEAD (bb)) |
f1330226 JH |
8040 | insn = PREV_INSN (insn); |
8041 | if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn)) | |
8042 | abort (); | |
a813c111 | 8043 | BB_END (bb) = insn; |
f1330226 JH |
8044 | inserted = true; |
8045 | insn = NEXT_INSN (insn); | |
0c4992b0 | 8046 | while (insn && insn != stop) |
f1330226 JH |
8047 | { |
8048 | next = NEXT_INSN (insn); | |
0c4992b0 JH |
8049 | if (INSN_P (insn)) |
8050 | { | |
53c17031 | 8051 | delete_insn (insn); |
f8ed1958 | 8052 | |
ed8d2920 MM |
8053 | /* Sometimes there's still the return value USE. |
8054 | If it's placed after a trapping call (i.e. that | |
8055 | call is the last insn anyway), we have no fallthru | |
8056 | edge. Simply delete this use and don't try to insert | |
14b493d6 | 8057 | on the non-existent edge. */ |
ed8d2920 MM |
8058 | if (GET_CODE (PATTERN (insn)) != USE) |
8059 | { | |
ed8d2920 MM |
8060 | /* We're not deleting it, we're moving it. */ |
8061 | INSN_DELETED_P (insn) = 0; | |
8062 | PREV_INSN (insn) = NULL_RTX; | |
8063 | NEXT_INSN (insn) = NULL_RTX; | |
f8ed1958 | 8064 | |
ed8d2920 MM |
8065 | insert_insn_on_edge (insn, e); |
8066 | } | |
0c4992b0 | 8067 | } |
f1330226 JH |
8068 | insn = next; |
8069 | } | |
8070 | } | |
8071 | } | |
83fd323c JH |
8072 | /* We've possibly turned single trapping insn into multiple ones. */ |
8073 | if (flag_non_call_exceptions) | |
8074 | { | |
8075 | sbitmap blocks; | |
8076 | blocks = sbitmap_alloc (last_basic_block); | |
8077 | sbitmap_ones (blocks); | |
8078 | find_many_sub_basic_blocks (blocks); | |
8079 | } | |
f1330226 JH |
8080 | if (inserted) |
8081 | commit_edge_insertions (); | |
8082 | } |