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6a73406e | 1 | /* Definitions for computing resource usage of specific insns. |
6fb5fa3c | 2 | Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
0c20a65f | 3 | Free Software Foundation, Inc. |
6a73406e | 4 | |
1322177d | 5 | This file is part of GCC. |
6a73406e | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 9 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 10 | version. |
6a73406e | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
6a73406e RH |
16 | |
17 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
6a73406e | 20 | |
ca545bb5 | 21 | #include "config.h" |
8ce25479 | 22 | #include "system.h" |
4977bab6 ZW |
23 | #include "coretypes.h" |
24 | #include "tm.h" | |
01198c2f | 25 | #include "toplev.h" |
ca545bb5 | 26 | #include "rtl.h" |
6baf1cc8 | 27 | #include "tm_p.h" |
ca545bb5 | 28 | #include "hard-reg-set.h" |
49ad7cfa | 29 | #include "function.h" |
ca545bb5 BM |
30 | #include "regs.h" |
31 | #include "flags.h" | |
32 | #include "output.h" | |
33 | #include "resource.h" | |
d80eb1e1 | 34 | #include "except.h" |
7bdb32b9 | 35 | #include "insn-attr.h" |
d5d063d7 | 36 | #include "params.h" |
6fb5fa3c | 37 | #include "df.h" |
ca545bb5 BM |
38 | |
39 | /* This structure is used to record liveness information at the targets or | |
40 | fallthrough insns of branches. We will most likely need the information | |
41 | at targets again, so save them in a hash table rather than recomputing them | |
42 | each time. */ | |
43 | ||
44 | struct target_info | |
45 | { | |
46 | int uid; /* INSN_UID of target. */ | |
47 | struct target_info *next; /* Next info for same hash bucket. */ | |
48 | HARD_REG_SET live_regs; /* Registers live at target. */ | |
49 | int block; /* Basic block number containing target. */ | |
50 | int bb_tick; /* Generation count of basic block info. */ | |
51 | }; | |
52 | ||
53 | #define TARGET_HASH_PRIME 257 | |
54 | ||
55 | /* Indicates what resources are required at the beginning of the epilogue. */ | |
56 | static struct resources start_of_epilogue_needs; | |
57 | ||
58 | /* Indicates what resources are required at function end. */ | |
59 | static struct resources end_of_function_needs; | |
60 | ||
61 | /* Define the hash table itself. */ | |
62 | static struct target_info **target_hash_table = NULL; | |
63 | ||
64 | /* For each basic block, we maintain a generation number of its basic | |
65 | block info, which is updated each time we move an insn from the | |
66 | target of a jump. This is the generation number indexed by block | |
67 | number. */ | |
68 | ||
69 | static int *bb_ticks; | |
70 | ||
71 | /* Marks registers possibly live at the current place being scanned by | |
d5d063d7 | 72 | mark_target_live_regs. Also used by update_live_status. */ |
ca545bb5 BM |
73 | |
74 | static HARD_REG_SET current_live_regs; | |
75 | ||
76 | /* Marks registers for which we have seen a REG_DEAD note but no assignment. | |
77 | Also only used by the next two functions. */ | |
78 | ||
79 | static HARD_REG_SET pending_dead_regs; | |
6a73406e | 80 | \f |
7bc980e1 | 81 | static void update_live_status (rtx, const_rtx, void *); |
0c20a65f AJ |
82 | static int find_basic_block (rtx, int); |
83 | static rtx next_insn_no_annul (rtx); | |
84 | static rtx find_dead_or_set_registers (rtx, struct resources*, | |
85 | rtx*, int, struct resources, | |
86 | struct resources); | |
6a73406e | 87 | \f |
ca545bb5 BM |
88 | /* Utility function called from mark_target_live_regs via note_stores. |
89 | It deadens any CLOBBERed registers and livens any SET registers. */ | |
90 | ||
91 | static void | |
7bc980e1 | 92 | update_live_status (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) |
ca545bb5 BM |
93 | { |
94 | int first_regno, last_regno; | |
95 | int i; | |
96 | ||
f8cfc6aa JQ |
97 | if (!REG_P (dest) |
98 | && (GET_CODE (dest) != SUBREG || !REG_P (SUBREG_REG (dest)))) | |
ca545bb5 BM |
99 | return; |
100 | ||
101 | if (GET_CODE (dest) == SUBREG) | |
f1f4e530 JM |
102 | { |
103 | first_regno = subreg_regno (dest); | |
104 | last_regno = first_regno + subreg_nregs (dest); | |
ca545bb5 | 105 | |
f1f4e530 JM |
106 | } |
107 | else | |
108 | { | |
109 | first_regno = REGNO (dest); | |
09e18274 | 110 | last_regno = END_HARD_REGNO (dest); |
f1f4e530 | 111 | } |
ca545bb5 BM |
112 | |
113 | if (GET_CODE (x) == CLOBBER) | |
114 | for (i = first_regno; i < last_regno; i++) | |
115 | CLEAR_HARD_REG_BIT (current_live_regs, i); | |
116 | else | |
117 | for (i = first_regno; i < last_regno; i++) | |
118 | { | |
119 | SET_HARD_REG_BIT (current_live_regs, i); | |
120 | CLEAR_HARD_REG_BIT (pending_dead_regs, i); | |
121 | } | |
122 | } | |
d5d063d7 JO |
123 | |
124 | /* Find the number of the basic block with correct live register | |
125 | information that starts closest to INSN. Return -1 if we couldn't | |
126 | find such a basic block or the beginning is more than | |
127 | SEARCH_LIMIT instructions before INSN. Use SEARCH_LIMIT = -1 for | |
128 | an unlimited search. | |
129 | ||
130 | The delay slot filling code destroys the control-flow graph so, | |
131 | instead of finding the basic block containing INSN, we search | |
132 | backwards toward a BARRIER where the live register information is | |
133 | correct. */ | |
925fa227 RH |
134 | |
135 | static int | |
0c20a65f | 136 | find_basic_block (rtx insn, int search_limit) |
925fa227 | 137 | { |
e0082a72 | 138 | basic_block bb; |
925fa227 RH |
139 | |
140 | /* Scan backwards to the previous BARRIER. Then see if we can find a | |
141 | label that starts a basic block. Return the basic block number. */ | |
925fa227 | 142 | for (insn = prev_nonnote_insn (insn); |
4b4bf941 | 143 | insn && !BARRIER_P (insn) && search_limit != 0; |
d5d063d7 | 144 | insn = prev_nonnote_insn (insn), --search_limit) |
925fa227 RH |
145 | ; |
146 | ||
d5d063d7 JO |
147 | /* The closest BARRIER is too far away. */ |
148 | if (search_limit == 0) | |
149 | return -1; | |
150 | ||
f6366fc7 | 151 | /* The start of the function. */ |
d5d063d7 | 152 | else if (insn == 0) |
f6366fc7 | 153 | return ENTRY_BLOCK_PTR->next_bb->index; |
925fa227 RH |
154 | |
155 | /* See if any of the upcoming CODE_LABELs start a basic block. If we reach | |
156 | anything other than a CODE_LABEL or note, we can't find this code. */ | |
157 | for (insn = next_nonnote_insn (insn); | |
4b4bf941 | 158 | insn && LABEL_P (insn); |
925fa227 RH |
159 | insn = next_nonnote_insn (insn)) |
160 | { | |
e0082a72 | 161 | FOR_EACH_BB (bb) |
a813c111 | 162 | if (insn == BB_HEAD (bb)) |
e0082a72 | 163 | return bb->index; |
925fa227 RH |
164 | } |
165 | ||
166 | return -1; | |
167 | } | |
ca545bb5 BM |
168 | \f |
169 | /* Similar to next_insn, but ignores insns in the delay slots of | |
170 | an annulled branch. */ | |
171 | ||
172 | static rtx | |
0c20a65f | 173 | next_insn_no_annul (rtx insn) |
ca545bb5 BM |
174 | { |
175 | if (insn) | |
176 | { | |
177 | /* If INSN is an annulled branch, skip any insns from the target | |
178 | of the branch. */ | |
4b4bf941 | 179 | if (INSN_P (insn) |
cf40ea15 | 180 | && INSN_ANNULLED_BRANCH_P (insn) |
ca545bb5 | 181 | && NEXT_INSN (PREV_INSN (insn)) != insn) |
cf40ea15 DM |
182 | { |
183 | rtx next = NEXT_INSN (insn); | |
184 | enum rtx_code code = GET_CODE (next); | |
185 | ||
186 | while ((code == INSN || code == JUMP_INSN || code == CALL_INSN) | |
187 | && INSN_FROM_TARGET_P (next)) | |
188 | { | |
189 | insn = next; | |
190 | next = NEXT_INSN (insn); | |
191 | code = GET_CODE (next); | |
192 | } | |
193 | } | |
ca545bb5 BM |
194 | |
195 | insn = NEXT_INSN (insn); | |
4b4bf941 | 196 | if (insn && NONJUMP_INSN_P (insn) |
ca545bb5 BM |
197 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
198 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
199 | } | |
200 | ||
201 | return insn; | |
202 | } | |
203 | \f | |
204 | /* Given X, some rtl, and RES, a pointer to a `struct resource', mark | |
f5df2e8c | 205 | which resources are referenced by the insn. If INCLUDE_DELAYED_EFFECTS |
ca545bb5 BM |
206 | is TRUE, resources used by the called routine will be included for |
207 | CALL_INSNs. */ | |
208 | ||
209 | void | |
0c20a65f AJ |
210 | mark_referenced_resources (rtx x, struct resources *res, |
211 | int include_delayed_effects) | |
ca545bb5 | 212 | { |
770ae6cc RK |
213 | enum rtx_code code = GET_CODE (x); |
214 | int i, j; | |
215 | unsigned int r; | |
b3694847 | 216 | const char *format_ptr; |
ca545bb5 BM |
217 | |
218 | /* Handle leaf items for which we set resource flags. Also, special-case | |
219 | CALL, SET and CLOBBER operators. */ | |
220 | switch (code) | |
221 | { | |
222 | case CONST: | |
223 | case CONST_INT: | |
224 | case CONST_DOUBLE: | |
69ef87e2 | 225 | case CONST_VECTOR: |
ca545bb5 BM |
226 | case PC: |
227 | case SYMBOL_REF: | |
228 | case LABEL_REF: | |
229 | return; | |
230 | ||
231 | case SUBREG: | |
f8cfc6aa | 232 | if (!REG_P (SUBREG_REG (x))) |
ca545bb5 BM |
233 | mark_referenced_resources (SUBREG_REG (x), res, 0); |
234 | else | |
235 | { | |
ddef6bc7 | 236 | unsigned int regno = subreg_regno (x); |
f1f4e530 | 237 | unsigned int last_regno = regno + subreg_nregs (x); |
770ae6cc | 238 | |
41374e13 | 239 | gcc_assert (last_regno <= FIRST_PSEUDO_REGISTER); |
770ae6cc RK |
240 | for (r = regno; r < last_regno; r++) |
241 | SET_HARD_REG_BIT (res->regs, r); | |
ca545bb5 BM |
242 | } |
243 | return; | |
244 | ||
245 | case REG: | |
09e18274 RS |
246 | gcc_assert (HARD_REGISTER_P (x)); |
247 | add_to_hard_reg_set (&res->regs, GET_MODE (x), REGNO (x)); | |
ca545bb5 BM |
248 | return; |
249 | ||
250 | case MEM: | |
251 | /* If this memory shouldn't change, it really isn't referencing | |
252 | memory. */ | |
389fdba0 | 253 | if (MEM_READONLY_P (x)) |
ca545bb5 BM |
254 | res->unch_memory = 1; |
255 | else | |
256 | res->memory = 1; | |
a5045352 | 257 | res->volatil |= MEM_VOLATILE_P (x); |
ca545bb5 BM |
258 | |
259 | /* Mark registers used to access memory. */ | |
260 | mark_referenced_resources (XEXP (x, 0), res, 0); | |
261 | return; | |
262 | ||
263 | case CC0: | |
264 | res->cc = 1; | |
265 | return; | |
266 | ||
267 | case UNSPEC_VOLATILE: | |
268 | case ASM_INPUT: | |
269 | /* Traditional asm's are always volatile. */ | |
270 | res->volatil = 1; | |
271 | return; | |
272 | ||
273 | case TRAP_IF: | |
274 | res->volatil = 1; | |
275 | break; | |
276 | ||
277 | case ASM_OPERANDS: | |
a5045352 | 278 | res->volatil |= MEM_VOLATILE_P (x); |
ca545bb5 BM |
279 | |
280 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
281 | We can not just fall through here since then we would be confused | |
282 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
283 | traditional asms unlike their normal usage. */ | |
a6a2274a | 284 | |
ca545bb5 BM |
285 | for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) |
286 | mark_referenced_resources (ASM_OPERANDS_INPUT (x, i), res, 0); | |
287 | return; | |
288 | ||
289 | case CALL: | |
290 | /* The first operand will be a (MEM (xxx)) but doesn't really reference | |
291 | memory. The second operand may be referenced, though. */ | |
292 | mark_referenced_resources (XEXP (XEXP (x, 0), 0), res, 0); | |
293 | mark_referenced_resources (XEXP (x, 1), res, 0); | |
294 | return; | |
295 | ||
296 | case SET: | |
297 | /* Usually, the first operand of SET is set, not referenced. But | |
298 | registers used to access memory are referenced. SET_DEST is | |
46d096a3 | 299 | also referenced if it is a ZERO_EXTRACT. */ |
ca545bb5 BM |
300 | |
301 | mark_referenced_resources (SET_SRC (x), res, 0); | |
302 | ||
303 | x = SET_DEST (x); | |
46d096a3 | 304 | if (GET_CODE (x) == ZERO_EXTRACT |
07570c39 | 305 | || GET_CODE (x) == STRICT_LOW_PART) |
ca545bb5 BM |
306 | mark_referenced_resources (x, res, 0); |
307 | else if (GET_CODE (x) == SUBREG) | |
308 | x = SUBREG_REG (x); | |
3c0cb5de | 309 | if (MEM_P (x)) |
ca545bb5 BM |
310 | mark_referenced_resources (XEXP (x, 0), res, 0); |
311 | return; | |
312 | ||
313 | case CLOBBER: | |
314 | return; | |
315 | ||
316 | case CALL_INSN: | |
317 | if (include_delayed_effects) | |
318 | { | |
319 | /* A CALL references memory, the frame pointer if it exists, the | |
320 | stack pointer, any global registers and any registers given in | |
321 | USE insns immediately in front of the CALL. | |
322 | ||
323 | However, we may have moved some of the parameter loading insns | |
324 | into the delay slot of this CALL. If so, the USE's for them | |
325 | don't count and should be skipped. */ | |
326 | rtx insn = PREV_INSN (x); | |
327 | rtx sequence = 0; | |
328 | int seq_size = 0; | |
ca545bb5 BM |
329 | int i; |
330 | ||
331 | /* If we are part of a delay slot sequence, point at the SEQUENCE. */ | |
332 | if (NEXT_INSN (insn) != x) | |
333 | { | |
ca545bb5 BM |
334 | sequence = PATTERN (NEXT_INSN (insn)); |
335 | seq_size = XVECLEN (sequence, 0); | |
41374e13 | 336 | gcc_assert (GET_CODE (sequence) == SEQUENCE); |
ca545bb5 BM |
337 | } |
338 | ||
339 | res->memory = 1; | |
340 | SET_HARD_REG_BIT (res->regs, STACK_POINTER_REGNUM); | |
341 | if (frame_pointer_needed) | |
342 | { | |
343 | SET_HARD_REG_BIT (res->regs, FRAME_POINTER_REGNUM); | |
344 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
345 | SET_HARD_REG_BIT (res->regs, HARD_FRAME_POINTER_REGNUM); | |
346 | #endif | |
347 | } | |
348 | ||
349 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
350 | if (global_regs[i]) | |
351 | SET_HARD_REG_BIT (res->regs, i); | |
352 | ||
570a98eb | 353 | /* Check for a REG_SETJMP. If it exists, then we must |
ca545bb5 BM |
354 | assume that this call can need any register. |
355 | ||
356 | This is done to be more conservative about how we handle setjmp. | |
357 | We assume that they both use and set all registers. Using all | |
358 | registers ensures that a register will not be considered dead | |
359 | just because it crosses a setjmp call. A register should be | |
40f03658 | 360 | considered dead only if the setjmp call returns nonzero. */ |
570a98eb | 361 | if (find_reg_note (x, REG_SETJMP, NULL)) |
ca545bb5 BM |
362 | SET_HARD_REG_SET (res->regs); |
363 | ||
364 | { | |
365 | rtx link; | |
366 | ||
367 | for (link = CALL_INSN_FUNCTION_USAGE (x); | |
368 | link; | |
369 | link = XEXP (link, 1)) | |
370 | if (GET_CODE (XEXP (link, 0)) == USE) | |
371 | { | |
372 | for (i = 1; i < seq_size; i++) | |
373 | { | |
374 | rtx slot_pat = PATTERN (XVECEXP (sequence, 0, i)); | |
375 | if (GET_CODE (slot_pat) == SET | |
376 | && rtx_equal_p (SET_DEST (slot_pat), | |
0cb5d81c | 377 | XEXP (XEXP (link, 0), 0))) |
ca545bb5 BM |
378 | break; |
379 | } | |
380 | if (i >= seq_size) | |
0cb5d81c | 381 | mark_referenced_resources (XEXP (XEXP (link, 0), 0), |
ca545bb5 BM |
382 | res, 0); |
383 | } | |
384 | } | |
385 | } | |
386 | ||
387 | /* ... fall through to other INSN processing ... */ | |
388 | ||
389 | case INSN: | |
390 | case JUMP_INSN: | |
391 | ||
392 | #ifdef INSN_REFERENCES_ARE_DELAYED | |
393 | if (! include_delayed_effects | |
394 | && INSN_REFERENCES_ARE_DELAYED (x)) | |
395 | return; | |
396 | #endif | |
397 | ||
398 | /* No special processing, just speed up. */ | |
399 | mark_referenced_resources (PATTERN (x), res, include_delayed_effects); | |
400 | return; | |
401 | ||
402 | default: | |
403 | break; | |
404 | } | |
405 | ||
406 | /* Process each sub-expression and flag what it needs. */ | |
407 | format_ptr = GET_RTX_FORMAT (code); | |
408 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
409 | switch (*format_ptr++) | |
410 | { | |
411 | case 'e': | |
412 | mark_referenced_resources (XEXP (x, i), res, include_delayed_effects); | |
413 | break; | |
414 | ||
415 | case 'E': | |
416 | for (j = 0; j < XVECLEN (x, i); j++) | |
417 | mark_referenced_resources (XVECEXP (x, i, j), res, | |
418 | include_delayed_effects); | |
419 | break; | |
420 | } | |
421 | } | |
422 | \f | |
423 | /* A subroutine of mark_target_live_regs. Search forward from TARGET | |
a6a2274a | 424 | looking for registers that are set before they are used. These are dead. |
ca545bb5 BM |
425 | Stop after passing a few conditional jumps, and/or a small |
426 | number of unconditional branches. */ | |
427 | ||
428 | static rtx | |
0c20a65f AJ |
429 | find_dead_or_set_registers (rtx target, struct resources *res, |
430 | rtx *jump_target, int jump_count, | |
431 | struct resources set, struct resources needed) | |
ca545bb5 BM |
432 | { |
433 | HARD_REG_SET scratch; | |
434 | rtx insn, next; | |
435 | rtx jump_insn = 0; | |
436 | int i; | |
437 | ||
438 | for (insn = target; insn; insn = next) | |
439 | { | |
440 | rtx this_jump_insn = insn; | |
441 | ||
442 | next = NEXT_INSN (insn); | |
0519ce30 MM |
443 | |
444 | /* If this instruction can throw an exception, then we don't | |
445 | know where we might end up next. That means that we have to | |
446 | assume that whatever we have already marked as live really is | |
447 | live. */ | |
54590688 | 448 | if (can_throw_internal (insn)) |
0519ce30 MM |
449 | break; |
450 | ||
ca545bb5 BM |
451 | switch (GET_CODE (insn)) |
452 | { | |
453 | case CODE_LABEL: | |
454 | /* After a label, any pending dead registers that weren't yet | |
455 | used can be made dead. */ | |
456 | AND_COMPL_HARD_REG_SET (pending_dead_regs, needed.regs); | |
457 | AND_COMPL_HARD_REG_SET (res->regs, pending_dead_regs); | |
458 | CLEAR_HARD_REG_SET (pending_dead_regs); | |
459 | ||
460 | continue; | |
461 | ||
462 | case BARRIER: | |
463 | case NOTE: | |
464 | continue; | |
465 | ||
466 | case INSN: | |
467 | if (GET_CODE (PATTERN (insn)) == USE) | |
468 | { | |
469 | /* If INSN is a USE made by update_block, we care about the | |
470 | underlying insn. Any registers set by the underlying insn | |
471 | are live since the insn is being done somewhere else. */ | |
2c3c49de | 472 | if (INSN_P (XEXP (PATTERN (insn), 0))) |
73780b74 SC |
473 | mark_set_resources (XEXP (PATTERN (insn), 0), res, 0, |
474 | MARK_SRC_DEST_CALL); | |
ca545bb5 BM |
475 | |
476 | /* All other USE insns are to be ignored. */ | |
477 | continue; | |
478 | } | |
479 | else if (GET_CODE (PATTERN (insn)) == CLOBBER) | |
480 | continue; | |
481 | else if (GET_CODE (PATTERN (insn)) == SEQUENCE) | |
482 | { | |
483 | /* An unconditional jump can be used to fill the delay slot | |
484 | of a call, so search for a JUMP_INSN in any position. */ | |
485 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
486 | { | |
487 | this_jump_insn = XVECEXP (PATTERN (insn), 0, i); | |
4b4bf941 | 488 | if (JUMP_P (this_jump_insn)) |
ca545bb5 BM |
489 | break; |
490 | } | |
491 | } | |
492 | ||
493 | default: | |
494 | break; | |
495 | } | |
496 | ||
4b4bf941 | 497 | if (JUMP_P (this_jump_insn)) |
ca545bb5 BM |
498 | { |
499 | if (jump_count++ < 10) | |
500 | { | |
7f1c097d | 501 | if (any_uncondjump_p (this_jump_insn) |
ca545bb5 BM |
502 | || GET_CODE (PATTERN (this_jump_insn)) == RETURN) |
503 | { | |
504 | next = JUMP_LABEL (this_jump_insn); | |
505 | if (jump_insn == 0) | |
506 | { | |
507 | jump_insn = insn; | |
508 | if (jump_target) | |
509 | *jump_target = JUMP_LABEL (this_jump_insn); | |
510 | } | |
511 | } | |
7f1c097d | 512 | else if (any_condjump_p (this_jump_insn)) |
ca545bb5 BM |
513 | { |
514 | struct resources target_set, target_res; | |
515 | struct resources fallthrough_res; | |
516 | ||
517 | /* We can handle conditional branches here by following | |
518 | both paths, and then IOR the results of the two paths | |
519 | together, which will give us registers that are dead | |
520 | on both paths. Since this is expensive, we give it | |
521 | a much higher cost than unconditional branches. The | |
522 | cost was chosen so that we will follow at most 1 | |
523 | conditional branch. */ | |
524 | ||
525 | jump_count += 4; | |
526 | if (jump_count >= 10) | |
527 | break; | |
528 | ||
529 | mark_referenced_resources (insn, &needed, 1); | |
530 | ||
531 | /* For an annulled branch, mark_set_resources ignores slots | |
532 | filled by instructions from the target. This is correct | |
533 | if the branch is not taken. Since we are following both | |
534 | paths from the branch, we must also compute correct info | |
535 | if the branch is taken. We do this by inverting all of | |
536 | the INSN_FROM_TARGET_P bits, calling mark_set_resources, | |
537 | and then inverting the INSN_FROM_TARGET_P bits again. */ | |
538 | ||
539 | if (GET_CODE (PATTERN (insn)) == SEQUENCE | |
540 | && INSN_ANNULLED_BRANCH_P (this_jump_insn)) | |
541 | { | |
542 | for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++) | |
543 | INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)) | |
544 | = ! INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)); | |
545 | ||
546 | target_set = set; | |
73780b74 SC |
547 | mark_set_resources (insn, &target_set, 0, |
548 | MARK_SRC_DEST_CALL); | |
ca545bb5 BM |
549 | |
550 | for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++) | |
551 | INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)) | |
552 | = ! INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)); | |
553 | ||
73780b74 | 554 | mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL); |
ca545bb5 BM |
555 | } |
556 | else | |
557 | { | |
73780b74 | 558 | mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL); |
ca545bb5 BM |
559 | target_set = set; |
560 | } | |
561 | ||
562 | target_res = *res; | |
563 | COPY_HARD_REG_SET (scratch, target_set.regs); | |
564 | AND_COMPL_HARD_REG_SET (scratch, needed.regs); | |
565 | AND_COMPL_HARD_REG_SET (target_res.regs, scratch); | |
566 | ||
567 | fallthrough_res = *res; | |
568 | COPY_HARD_REG_SET (scratch, set.regs); | |
569 | AND_COMPL_HARD_REG_SET (scratch, needed.regs); | |
570 | AND_COMPL_HARD_REG_SET (fallthrough_res.regs, scratch); | |
571 | ||
572 | find_dead_or_set_registers (JUMP_LABEL (this_jump_insn), | |
573 | &target_res, 0, jump_count, | |
574 | target_set, needed); | |
575 | find_dead_or_set_registers (next, | |
576 | &fallthrough_res, 0, jump_count, | |
577 | set, needed); | |
578 | IOR_HARD_REG_SET (fallthrough_res.regs, target_res.regs); | |
579 | AND_HARD_REG_SET (res->regs, fallthrough_res.regs); | |
580 | break; | |
581 | } | |
582 | else | |
583 | break; | |
584 | } | |
585 | else | |
586 | { | |
587 | /* Don't try this optimization if we expired our jump count | |
588 | above, since that would mean there may be an infinite loop | |
589 | in the function being compiled. */ | |
590 | jump_insn = 0; | |
591 | break; | |
592 | } | |
593 | } | |
594 | ||
595 | mark_referenced_resources (insn, &needed, 1); | |
73780b74 | 596 | mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL); |
ca545bb5 BM |
597 | |
598 | COPY_HARD_REG_SET (scratch, set.regs); | |
599 | AND_COMPL_HARD_REG_SET (scratch, needed.regs); | |
600 | AND_COMPL_HARD_REG_SET (res->regs, scratch); | |
601 | } | |
602 | ||
603 | return jump_insn; | |
604 | } | |
605 | \f | |
606 | /* Given X, a part of an insn, and a pointer to a `struct resource', | |
607 | RES, indicate which resources are modified by the insn. If | |
73780b74 | 608 | MARK_TYPE is MARK_SRC_DEST_CALL, also mark resources potentially |
73fb6466 | 609 | set by the called routine. |
ca545bb5 BM |
610 | |
611 | If IN_DEST is nonzero, it means we are inside a SET. Otherwise, | |
612 | objects are being referenced instead of set. | |
613 | ||
614 | We never mark the insn as modifying the condition code unless it explicitly | |
615 | SETs CC0 even though this is not totally correct. The reason for this is | |
616 | that we require a SET of CC0 to immediately precede the reference to CC0. | |
617 | So if some other insn sets CC0 as a side-effect, we know it cannot affect | |
6d2f8887 | 618 | our computation and thus may be placed in a delay slot. */ |
ca545bb5 BM |
619 | |
620 | void | |
0c20a65f AJ |
621 | mark_set_resources (rtx x, struct resources *res, int in_dest, |
622 | enum mark_resource_type mark_type) | |
ca545bb5 | 623 | { |
770ae6cc RK |
624 | enum rtx_code code; |
625 | int i, j; | |
626 | unsigned int r; | |
627 | const char *format_ptr; | |
ca545bb5 BM |
628 | |
629 | restart: | |
630 | ||
631 | code = GET_CODE (x); | |
632 | ||
633 | switch (code) | |
634 | { | |
635 | case NOTE: | |
636 | case BARRIER: | |
637 | case CODE_LABEL: | |
638 | case USE: | |
639 | case CONST_INT: | |
640 | case CONST_DOUBLE: | |
69ef87e2 | 641 | case CONST_VECTOR: |
ca545bb5 BM |
642 | case LABEL_REF: |
643 | case SYMBOL_REF: | |
644 | case CONST: | |
645 | case PC: | |
646 | /* These don't set any resources. */ | |
647 | return; | |
648 | ||
649 | case CC0: | |
650 | if (in_dest) | |
651 | res->cc = 1; | |
652 | return; | |
653 | ||
654 | case CALL_INSN: | |
655 | /* Called routine modifies the condition code, memory, any registers | |
656 | that aren't saved across calls, global registers and anything | |
657 | explicitly CLOBBERed immediately after the CALL_INSN. */ | |
658 | ||
73780b74 | 659 | if (mark_type == MARK_SRC_DEST_CALL) |
ca545bb5 | 660 | { |
ca545bb5 BM |
661 | rtx link; |
662 | ||
663 | res->cc = res->memory = 1; | |
770ae6cc RK |
664 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
665 | if (call_used_regs[r] || global_regs[r]) | |
666 | SET_HARD_REG_BIT (res->regs, r); | |
ca545bb5 | 667 | |
ca545bb5 BM |
668 | for (link = CALL_INSN_FUNCTION_USAGE (x); |
669 | link; link = XEXP (link, 1)) | |
670 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
73780b74 SC |
671 | mark_set_resources (SET_DEST (XEXP (link, 0)), res, 1, |
672 | MARK_SRC_DEST); | |
ca545bb5 | 673 | |
570a98eb | 674 | /* Check for a REG_SETJMP. If it exists, then we must |
ca545bb5 | 675 | assume that this call can clobber any register. */ |
570a98eb | 676 | if (find_reg_note (x, REG_SETJMP, NULL)) |
ca545bb5 BM |
677 | SET_HARD_REG_SET (res->regs); |
678 | } | |
679 | ||
680 | /* ... and also what its RTL says it modifies, if anything. */ | |
681 | ||
682 | case JUMP_INSN: | |
683 | case INSN: | |
684 | ||
685 | /* An insn consisting of just a CLOBBER (or USE) is just for flow | |
686 | and doesn't actually do anything, so we ignore it. */ | |
687 | ||
688 | #ifdef INSN_SETS_ARE_DELAYED | |
73780b74 | 689 | if (mark_type != MARK_SRC_DEST_CALL |
ca545bb5 BM |
690 | && INSN_SETS_ARE_DELAYED (x)) |
691 | return; | |
692 | #endif | |
693 | ||
694 | x = PATTERN (x); | |
695 | if (GET_CODE (x) != USE && GET_CODE (x) != CLOBBER) | |
696 | goto restart; | |
697 | return; | |
698 | ||
699 | case SET: | |
700 | /* If the source of a SET is a CALL, this is actually done by | |
701 | the called routine. So only include it if we are to include the | |
702 | effects of the calling routine. */ | |
703 | ||
704 | mark_set_resources (SET_DEST (x), res, | |
73780b74 | 705 | (mark_type == MARK_SRC_DEST_CALL |
ca545bb5 | 706 | || GET_CODE (SET_SRC (x)) != CALL), |
73780b74 | 707 | mark_type); |
ca545bb5 | 708 | |
73fb6466 | 709 | mark_set_resources (SET_SRC (x), res, 0, MARK_SRC_DEST); |
ca545bb5 BM |
710 | return; |
711 | ||
712 | case CLOBBER: | |
73780b74 | 713 | mark_set_resources (XEXP (x, 0), res, 1, MARK_SRC_DEST); |
ca545bb5 | 714 | return; |
a6a2274a | 715 | |
ca545bb5 BM |
716 | case SEQUENCE: |
717 | for (i = 0; i < XVECLEN (x, 0); i++) | |
718 | if (! (INSN_ANNULLED_BRANCH_P (XVECEXP (x, 0, 0)) | |
719 | && INSN_FROM_TARGET_P (XVECEXP (x, 0, i)))) | |
73780b74 | 720 | mark_set_resources (XVECEXP (x, 0, i), res, 0, mark_type); |
ca545bb5 BM |
721 | return; |
722 | ||
723 | case POST_INC: | |
724 | case PRE_INC: | |
725 | case POST_DEC: | |
726 | case PRE_DEC: | |
73780b74 | 727 | mark_set_resources (XEXP (x, 0), res, 1, MARK_SRC_DEST); |
ca545bb5 BM |
728 | return; |
729 | ||
4b983fdc RH |
730 | case PRE_MODIFY: |
731 | case POST_MODIFY: | |
1fb9c5cd MH |
732 | mark_set_resources (XEXP (x, 0), res, 1, MARK_SRC_DEST); |
733 | mark_set_resources (XEXP (XEXP (x, 1), 0), res, 0, MARK_SRC_DEST); | |
734 | mark_set_resources (XEXP (XEXP (x, 1), 1), res, 0, MARK_SRC_DEST); | |
4b983fdc RH |
735 | return; |
736 | ||
73780b74 | 737 | case SIGN_EXTRACT: |
ca545bb5 | 738 | case ZERO_EXTRACT: |
73fb6466 HPN |
739 | mark_set_resources (XEXP (x, 0), res, in_dest, MARK_SRC_DEST); |
740 | mark_set_resources (XEXP (x, 1), res, 0, MARK_SRC_DEST); | |
741 | mark_set_resources (XEXP (x, 2), res, 0, MARK_SRC_DEST); | |
ca545bb5 BM |
742 | return; |
743 | ||
744 | case MEM: | |
745 | if (in_dest) | |
746 | { | |
747 | res->memory = 1; | |
389fdba0 | 748 | res->unch_memory |= MEM_READONLY_P (x); |
a5045352 | 749 | res->volatil |= MEM_VOLATILE_P (x); |
ca545bb5 BM |
750 | } |
751 | ||
73780b74 | 752 | mark_set_resources (XEXP (x, 0), res, 0, MARK_SRC_DEST); |
ca545bb5 BM |
753 | return; |
754 | ||
755 | case SUBREG: | |
756 | if (in_dest) | |
757 | { | |
f8cfc6aa | 758 | if (!REG_P (SUBREG_REG (x))) |
73780b74 | 759 | mark_set_resources (SUBREG_REG (x), res, in_dest, mark_type); |
ca545bb5 BM |
760 | else |
761 | { | |
ddef6bc7 | 762 | unsigned int regno = subreg_regno (x); |
f1f4e530 | 763 | unsigned int last_regno = regno + subreg_nregs (x); |
770ae6cc | 764 | |
41374e13 | 765 | gcc_assert (last_regno <= FIRST_PSEUDO_REGISTER); |
770ae6cc RK |
766 | for (r = regno; r < last_regno; r++) |
767 | SET_HARD_REG_BIT (res->regs, r); | |
ca545bb5 BM |
768 | } |
769 | } | |
770 | return; | |
771 | ||
772 | case REG: | |
773 | if (in_dest) | |
1d2215fe | 774 | { |
09e18274 RS |
775 | gcc_assert (HARD_REGISTER_P (x)); |
776 | add_to_hard_reg_set (&res->regs, GET_MODE (x), REGNO (x)); | |
1d2215fe | 777 | } |
ca545bb5 BM |
778 | return; |
779 | ||
3d298f8f MM |
780 | case UNSPEC_VOLATILE: |
781 | case ASM_INPUT: | |
782 | /* Traditional asm's are always volatile. */ | |
783 | res->volatil = 1; | |
784 | return; | |
785 | ||
786 | case TRAP_IF: | |
787 | res->volatil = 1; | |
788 | break; | |
789 | ||
790 | case ASM_OPERANDS: | |
a5045352 | 791 | res->volatil |= MEM_VOLATILE_P (x); |
3d298f8f MM |
792 | |
793 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
794 | We can not just fall through here since then we would be confused | |
795 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
796 | traditional asms unlike their normal usage. */ | |
a6a2274a | 797 | |
3d298f8f | 798 | for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) |
73780b74 SC |
799 | mark_set_resources (ASM_OPERANDS_INPUT (x, i), res, in_dest, |
800 | MARK_SRC_DEST); | |
3d298f8f MM |
801 | return; |
802 | ||
ca545bb5 BM |
803 | default: |
804 | break; | |
805 | } | |
806 | ||
807 | /* Process each sub-expression and flag what it needs. */ | |
808 | format_ptr = GET_RTX_FORMAT (code); | |
809 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
810 | switch (*format_ptr++) | |
811 | { | |
812 | case 'e': | |
73780b74 | 813 | mark_set_resources (XEXP (x, i), res, in_dest, mark_type); |
ca545bb5 BM |
814 | break; |
815 | ||
816 | case 'E': | |
817 | for (j = 0; j < XVECLEN (x, i); j++) | |
73780b74 | 818 | mark_set_resources (XVECEXP (x, i, j), res, in_dest, mark_type); |
ca545bb5 BM |
819 | break; |
820 | } | |
821 | } | |
822 | \f | |
6e456a10 EB |
823 | /* Return TRUE if INSN is a return, possibly with a filled delay slot. */ |
824 | ||
825 | static bool | |
826 | return_insn_p (rtx insn) | |
827 | { | |
2ca202e7 | 828 | if (JUMP_P (insn) && GET_CODE (PATTERN (insn)) == RETURN) |
6e456a10 EB |
829 | return true; |
830 | ||
2ca202e7 | 831 | if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) |
6e456a10 EB |
832 | return return_insn_p (XVECEXP (PATTERN (insn), 0, 0)); |
833 | ||
834 | return false; | |
835 | } | |
836 | ||
ca545bb5 BM |
837 | /* Set the resources that are live at TARGET. |
838 | ||
839 | If TARGET is zero, we refer to the end of the current function and can | |
840 | return our precomputed value. | |
841 | ||
842 | Otherwise, we try to find out what is live by consulting the basic block | |
843 | information. This is tricky, because we must consider the actions of | |
844 | reload and jump optimization, which occur after the basic block information | |
845 | has been computed. | |
846 | ||
847 | Accordingly, we proceed as follows:: | |
848 | ||
849 | We find the previous BARRIER and look at all immediately following labels | |
850 | (with no intervening active insns) to see if any of them start a basic | |
851 | block. If we hit the start of the function first, we use block 0. | |
852 | ||
853 | Once we have found a basic block and a corresponding first insns, we can | |
854 | accurately compute the live status from basic_block_live_regs and | |
855 | reg_renumber. (By starting at a label following a BARRIER, we are immune | |
856 | to actions taken by reload and jump.) Then we scan all insns between | |
857 | that point and our target. For each CLOBBER (or for call-clobbered regs | |
858 | when we pass a CALL_INSN), mark the appropriate registers are dead. For | |
859 | a SET, mark them as live. | |
860 | ||
861 | We have to be careful when using REG_DEAD notes because they are not | |
862 | updated by such things as find_equiv_reg. So keep track of registers | |
863 | marked as dead that haven't been assigned to, and mark them dead at the | |
864 | next CODE_LABEL since reload and jump won't propagate values across labels. | |
865 | ||
866 | If we cannot find the start of a basic block (should be a very rare | |
867 | case, if it can happen at all), mark everything as potentially live. | |
868 | ||
869 | Next, scan forward from TARGET looking for things set or clobbered | |
870 | before they are used. These are not live. | |
871 | ||
872 | Because we can be called many times on the same target, save our results | |
873 | in a hash table indexed by INSN_UID. This is only done if the function | |
874 | init_resource_info () was invoked before we are called. */ | |
875 | ||
876 | void | |
0c20a65f | 877 | mark_target_live_regs (rtx insns, rtx target, struct resources *res) |
ca545bb5 BM |
878 | { |
879 | int b = -1; | |
5197bd50 | 880 | unsigned int i; |
ca545bb5 BM |
881 | struct target_info *tinfo = NULL; |
882 | rtx insn; | |
883 | rtx jump_insn = 0; | |
884 | rtx jump_target; | |
885 | HARD_REG_SET scratch; | |
886 | struct resources set, needed; | |
887 | ||
888 | /* Handle end of function. */ | |
889 | if (target == 0) | |
890 | { | |
891 | *res = end_of_function_needs; | |
892 | return; | |
893 | } | |
894 | ||
6e456a10 EB |
895 | /* Handle return insn. */ |
896 | else if (return_insn_p (target)) | |
897 | { | |
898 | *res = end_of_function_needs; | |
899 | mark_referenced_resources (target, res, 0); | |
900 | return; | |
901 | } | |
902 | ||
ca545bb5 BM |
903 | /* We have to assume memory is needed, but the CC isn't. */ |
904 | res->memory = 1; | |
905 | res->volatil = res->unch_memory = 0; | |
906 | res->cc = 0; | |
907 | ||
908 | /* See if we have computed this value already. */ | |
909 | if (target_hash_table != NULL) | |
910 | { | |
911 | for (tinfo = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME]; | |
912 | tinfo; tinfo = tinfo->next) | |
913 | if (tinfo->uid == INSN_UID (target)) | |
914 | break; | |
915 | ||
916 | /* Start by getting the basic block number. If we have saved | |
917 | information, we can get it from there unless the insn at the | |
918 | start of the basic block has been deleted. */ | |
919 | if (tinfo && tinfo->block != -1 | |
a813c111 | 920 | && ! INSN_DELETED_P (BB_HEAD (BASIC_BLOCK (tinfo->block)))) |
ca545bb5 BM |
921 | b = tinfo->block; |
922 | } | |
923 | ||
925fa227 | 924 | if (b == -1) |
d5d063d7 | 925 | b = find_basic_block (target, MAX_DELAY_SLOT_LIVE_SEARCH); |
ca545bb5 BM |
926 | |
927 | if (target_hash_table != NULL) | |
928 | { | |
929 | if (tinfo) | |
930 | { | |
931 | /* If the information is up-to-date, use it. Otherwise, we will | |
932 | update it below. */ | |
933 | if (b == tinfo->block && b != -1 && tinfo->bb_tick == bb_ticks[b]) | |
934 | { | |
935 | COPY_HARD_REG_SET (res->regs, tinfo->live_regs); | |
936 | return; | |
937 | } | |
938 | } | |
939 | else | |
940 | { | |
a6a2274a | 941 | /* Allocate a place to put our results and chain it into the |
ca545bb5 | 942 | hash table. */ |
5ed6ace5 | 943 | tinfo = XNEW (struct target_info); |
ca545bb5 BM |
944 | tinfo->uid = INSN_UID (target); |
945 | tinfo->block = b; | |
5197bd50 RK |
946 | tinfo->next |
947 | = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME]; | |
ca545bb5 BM |
948 | target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME] = tinfo; |
949 | } | |
950 | } | |
951 | ||
952 | CLEAR_HARD_REG_SET (pending_dead_regs); | |
953 | ||
954 | /* If we found a basic block, get the live registers from it and update | |
955 | them with anything set or killed between its start and the insn before | |
956 | TARGET. Otherwise, we must assume everything is live. */ | |
957 | if (b != -1) | |
958 | { | |
89a95777 | 959 | regset regs_live = df_get_live_in (BASIC_BLOCK (b)); |
ca545bb5 | 960 | rtx start_insn, stop_insn; |
a2041967 | 961 | reg_set_iterator rsi; |
ca545bb5 BM |
962 | |
963 | /* Compute hard regs live at start of block -- this is the real hard regs | |
964 | marked live, plus live pseudo regs that have been renumbered to | |
965 | hard regs. */ | |
966 | ||
967 | REG_SET_TO_HARD_REG_SET (current_live_regs, regs_live); | |
968 | ||
a2041967 KH |
969 | EXECUTE_IF_SET_IN_REG_SET (regs_live, FIRST_PSEUDO_REGISTER, i, rsi) |
970 | { | |
971 | if (reg_renumber[i] >= 0) | |
09e18274 RS |
972 | add_to_hard_reg_set (¤t_live_regs, PSEUDO_REGNO_MODE (i), |
973 | reg_renumber[i]); | |
a2041967 | 974 | } |
ca545bb5 BM |
975 | |
976 | /* Get starting and ending insn, handling the case where each might | |
977 | be a SEQUENCE. */ | |
6fb5fa3c DB |
978 | start_insn = (b == ENTRY_BLOCK_PTR->next_bb->index ? |
979 | insns : BB_HEAD (BASIC_BLOCK (b))); | |
ca545bb5 BM |
980 | stop_insn = target; |
981 | ||
4b4bf941 | 982 | if (NONJUMP_INSN_P (start_insn) |
ca545bb5 BM |
983 | && GET_CODE (PATTERN (start_insn)) == SEQUENCE) |
984 | start_insn = XVECEXP (PATTERN (start_insn), 0, 0); | |
985 | ||
4b4bf941 | 986 | if (NONJUMP_INSN_P (stop_insn) |
ca545bb5 BM |
987 | && GET_CODE (PATTERN (stop_insn)) == SEQUENCE) |
988 | stop_insn = next_insn (PREV_INSN (stop_insn)); | |
989 | ||
990 | for (insn = start_insn; insn != stop_insn; | |
991 | insn = next_insn_no_annul (insn)) | |
992 | { | |
993 | rtx link; | |
994 | rtx real_insn = insn; | |
cf40ea15 | 995 | enum rtx_code code = GET_CODE (insn); |
ca545bb5 BM |
996 | |
997 | /* If this insn is from the target of a branch, it isn't going to | |
998 | be used in the sequel. If it is used in both cases, this | |
999 | test will not be true. */ | |
cf40ea15 DM |
1000 | if ((code == INSN || code == JUMP_INSN || code == CALL_INSN) |
1001 | && INSN_FROM_TARGET_P (insn)) | |
ca545bb5 BM |
1002 | continue; |
1003 | ||
1004 | /* If this insn is a USE made by update_block, we care about the | |
1005 | underlying insn. */ | |
cf40ea15 | 1006 | if (code == INSN && GET_CODE (PATTERN (insn)) == USE |
2c3c49de | 1007 | && INSN_P (XEXP (PATTERN (insn), 0))) |
ca545bb5 BM |
1008 | real_insn = XEXP (PATTERN (insn), 0); |
1009 | ||
4b4bf941 | 1010 | if (CALL_P (real_insn)) |
ca545bb5 BM |
1011 | { |
1012 | /* CALL clobbers all call-used regs that aren't fixed except | |
1013 | sp, ap, and fp. Do this before setting the result of the | |
1014 | call live. */ | |
12beba6f RH |
1015 | AND_COMPL_HARD_REG_SET (current_live_regs, |
1016 | regs_invalidated_by_call); | |
ca545bb5 BM |
1017 | |
1018 | /* A CALL_INSN sets any global register live, since it may | |
1019 | have been modified by the call. */ | |
1020 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1021 | if (global_regs[i]) | |
1022 | SET_HARD_REG_BIT (current_live_regs, i); | |
1023 | } | |
1024 | ||
1025 | /* Mark anything killed in an insn to be deadened at the next | |
1026 | label. Ignore USE insns; the only REG_DEAD notes will be for | |
1027 | parameters. But they might be early. A CALL_INSN will usually | |
1028 | clobber registers used for parameters. It isn't worth bothering | |
1029 | with the unlikely case when it won't. */ | |
4b4bf941 | 1030 | if ((NONJUMP_INSN_P (real_insn) |
ca545bb5 BM |
1031 | && GET_CODE (PATTERN (real_insn)) != USE |
1032 | && GET_CODE (PATTERN (real_insn)) != CLOBBER) | |
4b4bf941 JQ |
1033 | || JUMP_P (real_insn) |
1034 | || CALL_P (real_insn)) | |
ca545bb5 BM |
1035 | { |
1036 | for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1)) | |
1037 | if (REG_NOTE_KIND (link) == REG_DEAD | |
f8cfc6aa | 1038 | && REG_P (XEXP (link, 0)) |
ca545bb5 | 1039 | && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER) |
09e18274 RS |
1040 | add_to_hard_reg_set (&pending_dead_regs, |
1041 | GET_MODE (XEXP (link, 0)), | |
1042 | REGNO (XEXP (link, 0))); | |
ca545bb5 | 1043 | |
84832317 | 1044 | note_stores (PATTERN (real_insn), update_live_status, NULL); |
ca545bb5 BM |
1045 | |
1046 | /* If any registers were unused after this insn, kill them. | |
1047 | These notes will always be accurate. */ | |
1048 | for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1)) | |
1049 | if (REG_NOTE_KIND (link) == REG_UNUSED | |
f8cfc6aa | 1050 | && REG_P (XEXP (link, 0)) |
ca545bb5 | 1051 | && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER) |
09e18274 RS |
1052 | remove_from_hard_reg_set (¤t_live_regs, |
1053 | GET_MODE (XEXP (link, 0)), | |
1054 | REGNO (XEXP (link, 0))); | |
ca545bb5 BM |
1055 | } |
1056 | ||
4b4bf941 | 1057 | else if (LABEL_P (real_insn)) |
ca545bb5 BM |
1058 | { |
1059 | /* A label clobbers the pending dead registers since neither | |
1060 | reload nor jump will propagate a value across a label. */ | |
1061 | AND_COMPL_HARD_REG_SET (current_live_regs, pending_dead_regs); | |
1062 | CLEAR_HARD_REG_SET (pending_dead_regs); | |
1063 | } | |
1064 | ||
1065 | /* The beginning of the epilogue corresponds to the end of the | |
1066 | RTL chain when there are no epilogue insns. Certain resources | |
1067 | are implicitly required at that point. */ | |
4b4bf941 | 1068 | else if (NOTE_P (real_insn) |
a38e7aa5 | 1069 | && NOTE_KIND (real_insn) == NOTE_INSN_EPILOGUE_BEG) |
ca545bb5 BM |
1070 | IOR_HARD_REG_SET (current_live_regs, start_of_epilogue_needs.regs); |
1071 | } | |
1072 | ||
1073 | COPY_HARD_REG_SET (res->regs, current_live_regs); | |
1074 | if (tinfo != NULL) | |
1075 | { | |
1076 | tinfo->block = b; | |
1077 | tinfo->bb_tick = bb_ticks[b]; | |
1078 | } | |
1079 | } | |
1080 | else | |
1081 | /* We didn't find the start of a basic block. Assume everything | |
1082 | in use. This should happen only extremely rarely. */ | |
1083 | SET_HARD_REG_SET (res->regs); | |
1084 | ||
1085 | CLEAR_RESOURCE (&set); | |
1086 | CLEAR_RESOURCE (&needed); | |
1087 | ||
1088 | jump_insn = find_dead_or_set_registers (target, res, &jump_target, 0, | |
1089 | set, needed); | |
1090 | ||
1091 | /* If we hit an unconditional branch, we have another way of finding out | |
1092 | what is live: we can see what is live at the branch target and include | |
96e9c98d | 1093 | anything used but not set before the branch. We add the live |
dc297297 | 1094 | resources found using the test below to those found until now. */ |
ca545bb5 BM |
1095 | |
1096 | if (jump_insn) | |
1097 | { | |
1098 | struct resources new_resources; | |
1099 | rtx stop_insn = next_active_insn (jump_insn); | |
1100 | ||
1101 | mark_target_live_regs (insns, next_active_insn (jump_target), | |
1102 | &new_resources); | |
1103 | CLEAR_RESOURCE (&set); | |
1104 | CLEAR_RESOURCE (&needed); | |
1105 | ||
1106 | /* Include JUMP_INSN in the needed registers. */ | |
1107 | for (insn = target; insn != stop_insn; insn = next_active_insn (insn)) | |
1108 | { | |
1109 | mark_referenced_resources (insn, &needed, 1); | |
1110 | ||
1111 | COPY_HARD_REG_SET (scratch, needed.regs); | |
1112 | AND_COMPL_HARD_REG_SET (scratch, set.regs); | |
1113 | IOR_HARD_REG_SET (new_resources.regs, scratch); | |
1114 | ||
73780b74 | 1115 | mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL); |
ca545bb5 BM |
1116 | } |
1117 | ||
96e9c98d | 1118 | IOR_HARD_REG_SET (res->regs, new_resources.regs); |
ca545bb5 BM |
1119 | } |
1120 | ||
1121 | if (tinfo != NULL) | |
1122 | { | |
1123 | COPY_HARD_REG_SET (tinfo->live_regs, res->regs); | |
1124 | } | |
1125 | } | |
1126 | \f | |
1127 | /* Initialize the resources required by mark_target_live_regs (). | |
1128 | This should be invoked before the first call to mark_target_live_regs. */ | |
1129 | ||
1130 | void | |
0c20a65f | 1131 | init_resource_info (rtx epilogue_insn) |
ca545bb5 BM |
1132 | { |
1133 | int i; | |
1134 | ||
1135 | /* Indicate what resources are required to be valid at the end of the current | |
1136 | function. The condition code never is and memory always is. If the | |
1137 | frame pointer is needed, it is and so is the stack pointer unless | |
40f03658 | 1138 | EXIT_IGNORE_STACK is nonzero. If the frame pointer is not needed, the |
ca545bb5 BM |
1139 | stack pointer is. Registers used to return the function value are |
1140 | needed. Registers holding global variables are needed. */ | |
1141 | ||
1142 | end_of_function_needs.cc = 0; | |
1143 | end_of_function_needs.memory = 1; | |
1144 | end_of_function_needs.unch_memory = 0; | |
1145 | CLEAR_HARD_REG_SET (end_of_function_needs.regs); | |
1146 | ||
1147 | if (frame_pointer_needed) | |
1148 | { | |
1149 | SET_HARD_REG_BIT (end_of_function_needs.regs, FRAME_POINTER_REGNUM); | |
1150 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
1151 | SET_HARD_REG_BIT (end_of_function_needs.regs, HARD_FRAME_POINTER_REGNUM); | |
1152 | #endif | |
ca545bb5 BM |
1153 | if (! EXIT_IGNORE_STACK |
1154 | || current_function_sp_is_unchanging) | |
ca545bb5 BM |
1155 | SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM); |
1156 | } | |
1157 | else | |
1158 | SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM); | |
1159 | ||
1160 | if (current_function_return_rtx != 0) | |
1161 | mark_referenced_resources (current_function_return_rtx, | |
1162 | &end_of_function_needs, 1); | |
1163 | ||
1164 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1165 | if (global_regs[i] | |
1166 | #ifdef EPILOGUE_USES | |
1167 | || EPILOGUE_USES (i) | |
1168 | #endif | |
1169 | ) | |
1170 | SET_HARD_REG_BIT (end_of_function_needs.regs, i); | |
1171 | ||
1172 | /* The registers required to be live at the end of the function are | |
1173 | represented in the flow information as being dead just prior to | |
1174 | reaching the end of the function. For example, the return of a value | |
1175 | might be represented by a USE of the return register immediately | |
1176 | followed by an unconditional jump to the return label where the | |
1177 | return label is the end of the RTL chain. The end of the RTL chain | |
1178 | is then taken to mean that the return register is live. | |
1179 | ||
1180 | This sequence is no longer maintained when epilogue instructions are | |
1181 | added to the RTL chain. To reconstruct the original meaning, the | |
1182 | start of the epilogue (NOTE_INSN_EPILOGUE_BEG) is regarded as the | |
1183 | point where these registers become live (start_of_epilogue_needs). | |
1184 | If epilogue instructions are present, the registers set by those | |
1185 | instructions won't have been processed by flow. Thus, those | |
1186 | registers are additionally required at the end of the RTL chain | |
1187 | (end_of_function_needs). */ | |
1188 | ||
1189 | start_of_epilogue_needs = end_of_function_needs; | |
1190 | ||
1191 | while ((epilogue_insn = next_nonnote_insn (epilogue_insn))) | |
6e456a10 EB |
1192 | { |
1193 | mark_set_resources (epilogue_insn, &end_of_function_needs, 0, | |
1194 | MARK_SRC_DEST_CALL); | |
1195 | if (return_insn_p (epilogue_insn)) | |
1196 | break; | |
1197 | } | |
ca545bb5 BM |
1198 | |
1199 | /* Allocate and initialize the tables used by mark_target_live_regs. */ | |
5ed6ace5 MD |
1200 | target_hash_table = XCNEWVEC (struct target_info *, TARGET_HASH_PRIME); |
1201 | bb_ticks = XCNEWVEC (int, last_basic_block); | |
ca545bb5 BM |
1202 | } |
1203 | \f | |
14b493d6 | 1204 | /* Free up the resources allocated to mark_target_live_regs (). This |
ca545bb5 BM |
1205 | should be invoked after the last call to mark_target_live_regs (). */ |
1206 | ||
1207 | void | |
0c20a65f | 1208 | free_resource_info (void) |
ca545bb5 BM |
1209 | { |
1210 | if (target_hash_table != NULL) | |
1211 | { | |
1f8f4a0b | 1212 | int i; |
a6a2274a KH |
1213 | |
1214 | for (i = 0; i < TARGET_HASH_PRIME; ++i) | |
1f8f4a0b MM |
1215 | { |
1216 | struct target_info *ti = target_hash_table[i]; | |
1217 | ||
a6a2274a | 1218 | while (ti) |
1f8f4a0b MM |
1219 | { |
1220 | struct target_info *next = ti->next; | |
1221 | free (ti); | |
1222 | ti = next; | |
1223 | } | |
1224 | } | |
1225 | ||
ca545bb5 BM |
1226 | free (target_hash_table); |
1227 | target_hash_table = NULL; | |
1228 | } | |
1229 | ||
1230 | if (bb_ticks != NULL) | |
1231 | { | |
1232 | free (bb_ticks); | |
1233 | bb_ticks = NULL; | |
1234 | } | |
1235 | } | |
1236 | \f | |
1237 | /* Clear any hashed information that we have stored for INSN. */ | |
1238 | ||
1239 | void | |
0c20a65f | 1240 | clear_hashed_info_for_insn (rtx insn) |
ca545bb5 BM |
1241 | { |
1242 | struct target_info *tinfo; | |
a6a2274a | 1243 | |
ca545bb5 BM |
1244 | if (target_hash_table != NULL) |
1245 | { | |
1246 | for (tinfo = target_hash_table[INSN_UID (insn) % TARGET_HASH_PRIME]; | |
1247 | tinfo; tinfo = tinfo->next) | |
1248 | if (tinfo->uid == INSN_UID (insn)) | |
1249 | break; | |
1250 | ||
1251 | if (tinfo) | |
1252 | tinfo->block = -1; | |
1253 | } | |
1254 | } | |
1255 | \f | |
1256 | /* Increment the tick count for the basic block that contains INSN. */ | |
1257 | ||
1258 | void | |
0c20a65f | 1259 | incr_ticks_for_insn (rtx insn) |
ca545bb5 | 1260 | { |
d5d063d7 | 1261 | int b = find_basic_block (insn, MAX_DELAY_SLOT_LIVE_SEARCH); |
ca545bb5 BM |
1262 | |
1263 | if (b != -1) | |
1264 | bb_ticks[b]++; | |
1265 | } | |
1266 | \f | |
1267 | /* Add TRIAL to the set of resources used at the end of the current | |
dc297297 | 1268 | function. */ |
ca545bb5 | 1269 | void |
0c20a65f | 1270 | mark_end_of_function_resources (rtx trial, int include_delayed_effects) |
ca545bb5 BM |
1271 | { |
1272 | mark_referenced_resources (trial, &end_of_function_needs, | |
1273 | include_delayed_effects); | |
1274 | } |