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6a73406e | 1 | /* Definitions for computing resource usage of specific insns. |
675f99c9 ILT |
2 | Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, |
3 | 2009 Free Software Foundation, Inc. | |
6a73406e | 4 | |
1322177d | 5 | This file is part of GCC. |
6a73406e | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 9 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 10 | version. |
6a73406e | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
6a73406e RH |
16 | |
17 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
6a73406e | 20 | |
ca545bb5 | 21 | #include "config.h" |
8ce25479 | 22 | #include "system.h" |
4977bab6 ZW |
23 | #include "coretypes.h" |
24 | #include "tm.h" | |
01198c2f | 25 | #include "toplev.h" |
ca545bb5 | 26 | #include "rtl.h" |
6baf1cc8 | 27 | #include "tm_p.h" |
ca545bb5 | 28 | #include "hard-reg-set.h" |
49ad7cfa | 29 | #include "function.h" |
ca545bb5 BM |
30 | #include "regs.h" |
31 | #include "flags.h" | |
32 | #include "output.h" | |
33 | #include "resource.h" | |
d80eb1e1 | 34 | #include "except.h" |
7bdb32b9 | 35 | #include "insn-attr.h" |
d5d063d7 | 36 | #include "params.h" |
6fb5fa3c | 37 | #include "df.h" |
ca545bb5 BM |
38 | |
39 | /* This structure is used to record liveness information at the targets or | |
40 | fallthrough insns of branches. We will most likely need the information | |
41 | at targets again, so save them in a hash table rather than recomputing them | |
42 | each time. */ | |
43 | ||
44 | struct target_info | |
45 | { | |
46 | int uid; /* INSN_UID of target. */ | |
47 | struct target_info *next; /* Next info for same hash bucket. */ | |
48 | HARD_REG_SET live_regs; /* Registers live at target. */ | |
49 | int block; /* Basic block number containing target. */ | |
50 | int bb_tick; /* Generation count of basic block info. */ | |
51 | }; | |
52 | ||
53 | #define TARGET_HASH_PRIME 257 | |
54 | ||
55 | /* Indicates what resources are required at the beginning of the epilogue. */ | |
56 | static struct resources start_of_epilogue_needs; | |
57 | ||
58 | /* Indicates what resources are required at function end. */ | |
59 | static struct resources end_of_function_needs; | |
60 | ||
61 | /* Define the hash table itself. */ | |
62 | static struct target_info **target_hash_table = NULL; | |
63 | ||
64 | /* For each basic block, we maintain a generation number of its basic | |
65 | block info, which is updated each time we move an insn from the | |
66 | target of a jump. This is the generation number indexed by block | |
67 | number. */ | |
68 | ||
69 | static int *bb_ticks; | |
70 | ||
71 | /* Marks registers possibly live at the current place being scanned by | |
d5d063d7 | 72 | mark_target_live_regs. Also used by update_live_status. */ |
ca545bb5 BM |
73 | |
74 | static HARD_REG_SET current_live_regs; | |
75 | ||
76 | /* Marks registers for which we have seen a REG_DEAD note but no assignment. | |
77 | Also only used by the next two functions. */ | |
78 | ||
79 | static HARD_REG_SET pending_dead_regs; | |
6a73406e | 80 | \f |
7bc980e1 | 81 | static void update_live_status (rtx, const_rtx, void *); |
0c20a65f AJ |
82 | static int find_basic_block (rtx, int); |
83 | static rtx next_insn_no_annul (rtx); | |
84 | static rtx find_dead_or_set_registers (rtx, struct resources*, | |
85 | rtx*, int, struct resources, | |
86 | struct resources); | |
6a73406e | 87 | \f |
ca545bb5 BM |
88 | /* Utility function called from mark_target_live_regs via note_stores. |
89 | It deadens any CLOBBERed registers and livens any SET registers. */ | |
90 | ||
91 | static void | |
7bc980e1 | 92 | update_live_status (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) |
ca545bb5 BM |
93 | { |
94 | int first_regno, last_regno; | |
95 | int i; | |
96 | ||
f8cfc6aa JQ |
97 | if (!REG_P (dest) |
98 | && (GET_CODE (dest) != SUBREG || !REG_P (SUBREG_REG (dest)))) | |
ca545bb5 BM |
99 | return; |
100 | ||
101 | if (GET_CODE (dest) == SUBREG) | |
f1f4e530 JM |
102 | { |
103 | first_regno = subreg_regno (dest); | |
104 | last_regno = first_regno + subreg_nregs (dest); | |
ca545bb5 | 105 | |
f1f4e530 JM |
106 | } |
107 | else | |
108 | { | |
109 | first_regno = REGNO (dest); | |
09e18274 | 110 | last_regno = END_HARD_REGNO (dest); |
f1f4e530 | 111 | } |
ca545bb5 BM |
112 | |
113 | if (GET_CODE (x) == CLOBBER) | |
114 | for (i = first_regno; i < last_regno; i++) | |
115 | CLEAR_HARD_REG_BIT (current_live_regs, i); | |
116 | else | |
117 | for (i = first_regno; i < last_regno; i++) | |
118 | { | |
119 | SET_HARD_REG_BIT (current_live_regs, i); | |
120 | CLEAR_HARD_REG_BIT (pending_dead_regs, i); | |
121 | } | |
122 | } | |
d5d063d7 JO |
123 | |
124 | /* Find the number of the basic block with correct live register | |
125 | information that starts closest to INSN. Return -1 if we couldn't | |
126 | find such a basic block or the beginning is more than | |
127 | SEARCH_LIMIT instructions before INSN. Use SEARCH_LIMIT = -1 for | |
128 | an unlimited search. | |
129 | ||
130 | The delay slot filling code destroys the control-flow graph so, | |
131 | instead of finding the basic block containing INSN, we search | |
132 | backwards toward a BARRIER where the live register information is | |
133 | correct. */ | |
925fa227 RH |
134 | |
135 | static int | |
0c20a65f | 136 | find_basic_block (rtx insn, int search_limit) |
925fa227 | 137 | { |
925fa227 RH |
138 | /* Scan backwards to the previous BARRIER. Then see if we can find a |
139 | label that starts a basic block. Return the basic block number. */ | |
925fa227 | 140 | for (insn = prev_nonnote_insn (insn); |
4b4bf941 | 141 | insn && !BARRIER_P (insn) && search_limit != 0; |
d5d063d7 | 142 | insn = prev_nonnote_insn (insn), --search_limit) |
925fa227 RH |
143 | ; |
144 | ||
d5d063d7 JO |
145 | /* The closest BARRIER is too far away. */ |
146 | if (search_limit == 0) | |
147 | return -1; | |
148 | ||
f6366fc7 | 149 | /* The start of the function. */ |
d5d063d7 | 150 | else if (insn == 0) |
f6366fc7 | 151 | return ENTRY_BLOCK_PTR->next_bb->index; |
925fa227 RH |
152 | |
153 | /* See if any of the upcoming CODE_LABELs start a basic block. If we reach | |
154 | anything other than a CODE_LABEL or note, we can't find this code. */ | |
155 | for (insn = next_nonnote_insn (insn); | |
4b4bf941 | 156 | insn && LABEL_P (insn); |
925fa227 | 157 | insn = next_nonnote_insn (insn)) |
a1fa3e79 EB |
158 | if (BLOCK_FOR_INSN (insn)) |
159 | return BLOCK_FOR_INSN (insn)->index; | |
925fa227 RH |
160 | |
161 | return -1; | |
162 | } | |
ca545bb5 BM |
163 | \f |
164 | /* Similar to next_insn, but ignores insns in the delay slots of | |
165 | an annulled branch. */ | |
166 | ||
167 | static rtx | |
0c20a65f | 168 | next_insn_no_annul (rtx insn) |
ca545bb5 BM |
169 | { |
170 | if (insn) | |
171 | { | |
172 | /* If INSN is an annulled branch, skip any insns from the target | |
173 | of the branch. */ | |
4b4bf941 | 174 | if (INSN_P (insn) |
cf40ea15 | 175 | && INSN_ANNULLED_BRANCH_P (insn) |
ca545bb5 | 176 | && NEXT_INSN (PREV_INSN (insn)) != insn) |
cf40ea15 DM |
177 | { |
178 | rtx next = NEXT_INSN (insn); | |
179 | enum rtx_code code = GET_CODE (next); | |
180 | ||
181 | while ((code == INSN || code == JUMP_INSN || code == CALL_INSN) | |
182 | && INSN_FROM_TARGET_P (next)) | |
183 | { | |
184 | insn = next; | |
185 | next = NEXT_INSN (insn); | |
186 | code = GET_CODE (next); | |
187 | } | |
188 | } | |
ca545bb5 BM |
189 | |
190 | insn = NEXT_INSN (insn); | |
4b4bf941 | 191 | if (insn && NONJUMP_INSN_P (insn) |
ca545bb5 BM |
192 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
193 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
194 | } | |
195 | ||
196 | return insn; | |
197 | } | |
198 | \f | |
199 | /* Given X, some rtl, and RES, a pointer to a `struct resource', mark | |
f5df2e8c | 200 | which resources are referenced by the insn. If INCLUDE_DELAYED_EFFECTS |
ca545bb5 BM |
201 | is TRUE, resources used by the called routine will be included for |
202 | CALL_INSNs. */ | |
203 | ||
204 | void | |
0c20a65f | 205 | mark_referenced_resources (rtx x, struct resources *res, |
675f99c9 | 206 | bool include_delayed_effects) |
ca545bb5 | 207 | { |
770ae6cc RK |
208 | enum rtx_code code = GET_CODE (x); |
209 | int i, j; | |
210 | unsigned int r; | |
b3694847 | 211 | const char *format_ptr; |
ca545bb5 BM |
212 | |
213 | /* Handle leaf items for which we set resource flags. Also, special-case | |
214 | CALL, SET and CLOBBER operators. */ | |
215 | switch (code) | |
216 | { | |
217 | case CONST: | |
218 | case CONST_INT: | |
219 | case CONST_DOUBLE: | |
091a3ac7 | 220 | case CONST_FIXED: |
69ef87e2 | 221 | case CONST_VECTOR: |
ca545bb5 BM |
222 | case PC: |
223 | case SYMBOL_REF: | |
224 | case LABEL_REF: | |
225 | return; | |
226 | ||
227 | case SUBREG: | |
f8cfc6aa | 228 | if (!REG_P (SUBREG_REG (x))) |
675f99c9 | 229 | mark_referenced_resources (SUBREG_REG (x), res, false); |
ca545bb5 BM |
230 | else |
231 | { | |
ddef6bc7 | 232 | unsigned int regno = subreg_regno (x); |
f1f4e530 | 233 | unsigned int last_regno = regno + subreg_nregs (x); |
770ae6cc | 234 | |
41374e13 | 235 | gcc_assert (last_regno <= FIRST_PSEUDO_REGISTER); |
770ae6cc RK |
236 | for (r = regno; r < last_regno; r++) |
237 | SET_HARD_REG_BIT (res->regs, r); | |
ca545bb5 BM |
238 | } |
239 | return; | |
240 | ||
241 | case REG: | |
09e18274 RS |
242 | gcc_assert (HARD_REGISTER_P (x)); |
243 | add_to_hard_reg_set (&res->regs, GET_MODE (x), REGNO (x)); | |
ca545bb5 BM |
244 | return; |
245 | ||
246 | case MEM: | |
247 | /* If this memory shouldn't change, it really isn't referencing | |
248 | memory. */ | |
389fdba0 | 249 | if (MEM_READONLY_P (x)) |
ca545bb5 BM |
250 | res->unch_memory = 1; |
251 | else | |
252 | res->memory = 1; | |
a5045352 | 253 | res->volatil |= MEM_VOLATILE_P (x); |
ca545bb5 BM |
254 | |
255 | /* Mark registers used to access memory. */ | |
675f99c9 | 256 | mark_referenced_resources (XEXP (x, 0), res, false); |
ca545bb5 BM |
257 | return; |
258 | ||
259 | case CC0: | |
260 | res->cc = 1; | |
261 | return; | |
262 | ||
263 | case UNSPEC_VOLATILE: | |
1b929c9a | 264 | case TRAP_IF: |
ca545bb5 BM |
265 | case ASM_INPUT: |
266 | /* Traditional asm's are always volatile. */ | |
ca545bb5 BM |
267 | res->volatil = 1; |
268 | break; | |
269 | ||
270 | case ASM_OPERANDS: | |
a5045352 | 271 | res->volatil |= MEM_VOLATILE_P (x); |
ca545bb5 BM |
272 | |
273 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
274 | We can not just fall through here since then we would be confused | |
275 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
276 | traditional asms unlike their normal usage. */ | |
a6a2274a | 277 | |
ca545bb5 | 278 | for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) |
675f99c9 | 279 | mark_referenced_resources (ASM_OPERANDS_INPUT (x, i), res, false); |
ca545bb5 BM |
280 | return; |
281 | ||
282 | case CALL: | |
283 | /* The first operand will be a (MEM (xxx)) but doesn't really reference | |
284 | memory. The second operand may be referenced, though. */ | |
675f99c9 ILT |
285 | mark_referenced_resources (XEXP (XEXP (x, 0), 0), res, false); |
286 | mark_referenced_resources (XEXP (x, 1), res, false); | |
ca545bb5 BM |
287 | return; |
288 | ||
289 | case SET: | |
290 | /* Usually, the first operand of SET is set, not referenced. But | |
291 | registers used to access memory are referenced. SET_DEST is | |
46d096a3 | 292 | also referenced if it is a ZERO_EXTRACT. */ |
ca545bb5 | 293 | |
675f99c9 | 294 | mark_referenced_resources (SET_SRC (x), res, false); |
ca545bb5 BM |
295 | |
296 | x = SET_DEST (x); | |
46d096a3 | 297 | if (GET_CODE (x) == ZERO_EXTRACT |
07570c39 | 298 | || GET_CODE (x) == STRICT_LOW_PART) |
675f99c9 | 299 | mark_referenced_resources (x, res, false); |
ca545bb5 BM |
300 | else if (GET_CODE (x) == SUBREG) |
301 | x = SUBREG_REG (x); | |
3c0cb5de | 302 | if (MEM_P (x)) |
675f99c9 | 303 | mark_referenced_resources (XEXP (x, 0), res, false); |
ca545bb5 BM |
304 | return; |
305 | ||
306 | case CLOBBER: | |
307 | return; | |
308 | ||
309 | case CALL_INSN: | |
310 | if (include_delayed_effects) | |
311 | { | |
312 | /* A CALL references memory, the frame pointer if it exists, the | |
313 | stack pointer, any global registers and any registers given in | |
314 | USE insns immediately in front of the CALL. | |
315 | ||
316 | However, we may have moved some of the parameter loading insns | |
317 | into the delay slot of this CALL. If so, the USE's for them | |
318 | don't count and should be skipped. */ | |
319 | rtx insn = PREV_INSN (x); | |
320 | rtx sequence = 0; | |
321 | int seq_size = 0; | |
ca545bb5 BM |
322 | int i; |
323 | ||
324 | /* If we are part of a delay slot sequence, point at the SEQUENCE. */ | |
325 | if (NEXT_INSN (insn) != x) | |
326 | { | |
ca545bb5 BM |
327 | sequence = PATTERN (NEXT_INSN (insn)); |
328 | seq_size = XVECLEN (sequence, 0); | |
41374e13 | 329 | gcc_assert (GET_CODE (sequence) == SEQUENCE); |
ca545bb5 BM |
330 | } |
331 | ||
332 | res->memory = 1; | |
333 | SET_HARD_REG_BIT (res->regs, STACK_POINTER_REGNUM); | |
334 | if (frame_pointer_needed) | |
335 | { | |
336 | SET_HARD_REG_BIT (res->regs, FRAME_POINTER_REGNUM); | |
337 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
338 | SET_HARD_REG_BIT (res->regs, HARD_FRAME_POINTER_REGNUM); | |
339 | #endif | |
340 | } | |
341 | ||
342 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
343 | if (global_regs[i]) | |
344 | SET_HARD_REG_BIT (res->regs, i); | |
345 | ||
570a98eb | 346 | /* Check for a REG_SETJMP. If it exists, then we must |
ca545bb5 BM |
347 | assume that this call can need any register. |
348 | ||
349 | This is done to be more conservative about how we handle setjmp. | |
350 | We assume that they both use and set all registers. Using all | |
351 | registers ensures that a register will not be considered dead | |
352 | just because it crosses a setjmp call. A register should be | |
40f03658 | 353 | considered dead only if the setjmp call returns nonzero. */ |
570a98eb | 354 | if (find_reg_note (x, REG_SETJMP, NULL)) |
ca545bb5 BM |
355 | SET_HARD_REG_SET (res->regs); |
356 | ||
357 | { | |
358 | rtx link; | |
359 | ||
360 | for (link = CALL_INSN_FUNCTION_USAGE (x); | |
361 | link; | |
362 | link = XEXP (link, 1)) | |
363 | if (GET_CODE (XEXP (link, 0)) == USE) | |
364 | { | |
365 | for (i = 1; i < seq_size; i++) | |
366 | { | |
367 | rtx slot_pat = PATTERN (XVECEXP (sequence, 0, i)); | |
368 | if (GET_CODE (slot_pat) == SET | |
369 | && rtx_equal_p (SET_DEST (slot_pat), | |
0cb5d81c | 370 | XEXP (XEXP (link, 0), 0))) |
ca545bb5 BM |
371 | break; |
372 | } | |
373 | if (i >= seq_size) | |
0cb5d81c | 374 | mark_referenced_resources (XEXP (XEXP (link, 0), 0), |
675f99c9 | 375 | res, false); |
ca545bb5 BM |
376 | } |
377 | } | |
378 | } | |
379 | ||
380 | /* ... fall through to other INSN processing ... */ | |
381 | ||
382 | case INSN: | |
383 | case JUMP_INSN: | |
384 | ||
385 | #ifdef INSN_REFERENCES_ARE_DELAYED | |
386 | if (! include_delayed_effects | |
387 | && INSN_REFERENCES_ARE_DELAYED (x)) | |
388 | return; | |
389 | #endif | |
390 | ||
391 | /* No special processing, just speed up. */ | |
392 | mark_referenced_resources (PATTERN (x), res, include_delayed_effects); | |
393 | return; | |
394 | ||
395 | default: | |
396 | break; | |
397 | } | |
398 | ||
399 | /* Process each sub-expression and flag what it needs. */ | |
400 | format_ptr = GET_RTX_FORMAT (code); | |
401 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
402 | switch (*format_ptr++) | |
403 | { | |
404 | case 'e': | |
405 | mark_referenced_resources (XEXP (x, i), res, include_delayed_effects); | |
406 | break; | |
407 | ||
408 | case 'E': | |
409 | for (j = 0; j < XVECLEN (x, i); j++) | |
410 | mark_referenced_resources (XVECEXP (x, i, j), res, | |
411 | include_delayed_effects); | |
412 | break; | |
413 | } | |
414 | } | |
415 | \f | |
416 | /* A subroutine of mark_target_live_regs. Search forward from TARGET | |
a6a2274a | 417 | looking for registers that are set before they are used. These are dead. |
ca545bb5 BM |
418 | Stop after passing a few conditional jumps, and/or a small |
419 | number of unconditional branches. */ | |
420 | ||
421 | static rtx | |
0c20a65f AJ |
422 | find_dead_or_set_registers (rtx target, struct resources *res, |
423 | rtx *jump_target, int jump_count, | |
424 | struct resources set, struct resources needed) | |
ca545bb5 BM |
425 | { |
426 | HARD_REG_SET scratch; | |
427 | rtx insn, next; | |
428 | rtx jump_insn = 0; | |
429 | int i; | |
430 | ||
431 | for (insn = target; insn; insn = next) | |
432 | { | |
433 | rtx this_jump_insn = insn; | |
434 | ||
435 | next = NEXT_INSN (insn); | |
0519ce30 MM |
436 | |
437 | /* If this instruction can throw an exception, then we don't | |
438 | know where we might end up next. That means that we have to | |
439 | assume that whatever we have already marked as live really is | |
440 | live. */ | |
54590688 | 441 | if (can_throw_internal (insn)) |
0519ce30 MM |
442 | break; |
443 | ||
ca545bb5 BM |
444 | switch (GET_CODE (insn)) |
445 | { | |
446 | case CODE_LABEL: | |
447 | /* After a label, any pending dead registers that weren't yet | |
448 | used can be made dead. */ | |
449 | AND_COMPL_HARD_REG_SET (pending_dead_regs, needed.regs); | |
450 | AND_COMPL_HARD_REG_SET (res->regs, pending_dead_regs); | |
451 | CLEAR_HARD_REG_SET (pending_dead_regs); | |
452 | ||
453 | continue; | |
454 | ||
455 | case BARRIER: | |
456 | case NOTE: | |
457 | continue; | |
458 | ||
459 | case INSN: | |
460 | if (GET_CODE (PATTERN (insn)) == USE) | |
461 | { | |
462 | /* If INSN is a USE made by update_block, we care about the | |
463 | underlying insn. Any registers set by the underlying insn | |
464 | are live since the insn is being done somewhere else. */ | |
2c3c49de | 465 | if (INSN_P (XEXP (PATTERN (insn), 0))) |
73780b74 SC |
466 | mark_set_resources (XEXP (PATTERN (insn), 0), res, 0, |
467 | MARK_SRC_DEST_CALL); | |
ca545bb5 BM |
468 | |
469 | /* All other USE insns are to be ignored. */ | |
470 | continue; | |
471 | } | |
472 | else if (GET_CODE (PATTERN (insn)) == CLOBBER) | |
473 | continue; | |
474 | else if (GET_CODE (PATTERN (insn)) == SEQUENCE) | |
475 | { | |
476 | /* An unconditional jump can be used to fill the delay slot | |
477 | of a call, so search for a JUMP_INSN in any position. */ | |
478 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
479 | { | |
480 | this_jump_insn = XVECEXP (PATTERN (insn), 0, i); | |
4b4bf941 | 481 | if (JUMP_P (this_jump_insn)) |
ca545bb5 BM |
482 | break; |
483 | } | |
484 | } | |
485 | ||
486 | default: | |
487 | break; | |
488 | } | |
489 | ||
4b4bf941 | 490 | if (JUMP_P (this_jump_insn)) |
ca545bb5 BM |
491 | { |
492 | if (jump_count++ < 10) | |
493 | { | |
7f1c097d | 494 | if (any_uncondjump_p (this_jump_insn) |
ca545bb5 BM |
495 | || GET_CODE (PATTERN (this_jump_insn)) == RETURN) |
496 | { | |
497 | next = JUMP_LABEL (this_jump_insn); | |
498 | if (jump_insn == 0) | |
499 | { | |
500 | jump_insn = insn; | |
501 | if (jump_target) | |
502 | *jump_target = JUMP_LABEL (this_jump_insn); | |
503 | } | |
504 | } | |
7f1c097d | 505 | else if (any_condjump_p (this_jump_insn)) |
ca545bb5 BM |
506 | { |
507 | struct resources target_set, target_res; | |
508 | struct resources fallthrough_res; | |
509 | ||
510 | /* We can handle conditional branches here by following | |
511 | both paths, and then IOR the results of the two paths | |
512 | together, which will give us registers that are dead | |
513 | on both paths. Since this is expensive, we give it | |
514 | a much higher cost than unconditional branches. The | |
515 | cost was chosen so that we will follow at most 1 | |
516 | conditional branch. */ | |
517 | ||
518 | jump_count += 4; | |
519 | if (jump_count >= 10) | |
520 | break; | |
521 | ||
675f99c9 | 522 | mark_referenced_resources (insn, &needed, true); |
ca545bb5 BM |
523 | |
524 | /* For an annulled branch, mark_set_resources ignores slots | |
525 | filled by instructions from the target. This is correct | |
526 | if the branch is not taken. Since we are following both | |
527 | paths from the branch, we must also compute correct info | |
528 | if the branch is taken. We do this by inverting all of | |
529 | the INSN_FROM_TARGET_P bits, calling mark_set_resources, | |
530 | and then inverting the INSN_FROM_TARGET_P bits again. */ | |
531 | ||
532 | if (GET_CODE (PATTERN (insn)) == SEQUENCE | |
533 | && INSN_ANNULLED_BRANCH_P (this_jump_insn)) | |
534 | { | |
535 | for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++) | |
536 | INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)) | |
537 | = ! INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)); | |
538 | ||
539 | target_set = set; | |
73780b74 SC |
540 | mark_set_resources (insn, &target_set, 0, |
541 | MARK_SRC_DEST_CALL); | |
ca545bb5 BM |
542 | |
543 | for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++) | |
544 | INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)) | |
545 | = ! INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)); | |
546 | ||
73780b74 | 547 | mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL); |
ca545bb5 BM |
548 | } |
549 | else | |
550 | { | |
73780b74 | 551 | mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL); |
ca545bb5 BM |
552 | target_set = set; |
553 | } | |
554 | ||
555 | target_res = *res; | |
556 | COPY_HARD_REG_SET (scratch, target_set.regs); | |
557 | AND_COMPL_HARD_REG_SET (scratch, needed.regs); | |
558 | AND_COMPL_HARD_REG_SET (target_res.regs, scratch); | |
559 | ||
560 | fallthrough_res = *res; | |
561 | COPY_HARD_REG_SET (scratch, set.regs); | |
562 | AND_COMPL_HARD_REG_SET (scratch, needed.regs); | |
563 | AND_COMPL_HARD_REG_SET (fallthrough_res.regs, scratch); | |
564 | ||
565 | find_dead_or_set_registers (JUMP_LABEL (this_jump_insn), | |
566 | &target_res, 0, jump_count, | |
567 | target_set, needed); | |
568 | find_dead_or_set_registers (next, | |
569 | &fallthrough_res, 0, jump_count, | |
570 | set, needed); | |
571 | IOR_HARD_REG_SET (fallthrough_res.regs, target_res.regs); | |
572 | AND_HARD_REG_SET (res->regs, fallthrough_res.regs); | |
573 | break; | |
574 | } | |
575 | else | |
576 | break; | |
577 | } | |
578 | else | |
579 | { | |
580 | /* Don't try this optimization if we expired our jump count | |
581 | above, since that would mean there may be an infinite loop | |
582 | in the function being compiled. */ | |
583 | jump_insn = 0; | |
584 | break; | |
585 | } | |
586 | } | |
587 | ||
675f99c9 | 588 | mark_referenced_resources (insn, &needed, true); |
73780b74 | 589 | mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL); |
ca545bb5 BM |
590 | |
591 | COPY_HARD_REG_SET (scratch, set.regs); | |
592 | AND_COMPL_HARD_REG_SET (scratch, needed.regs); | |
593 | AND_COMPL_HARD_REG_SET (res->regs, scratch); | |
594 | } | |
595 | ||
596 | return jump_insn; | |
597 | } | |
598 | \f | |
599 | /* Given X, a part of an insn, and a pointer to a `struct resource', | |
600 | RES, indicate which resources are modified by the insn. If | |
73780b74 | 601 | MARK_TYPE is MARK_SRC_DEST_CALL, also mark resources potentially |
73fb6466 | 602 | set by the called routine. |
ca545bb5 BM |
603 | |
604 | If IN_DEST is nonzero, it means we are inside a SET. Otherwise, | |
605 | objects are being referenced instead of set. | |
606 | ||
607 | We never mark the insn as modifying the condition code unless it explicitly | |
608 | SETs CC0 even though this is not totally correct. The reason for this is | |
609 | that we require a SET of CC0 to immediately precede the reference to CC0. | |
610 | So if some other insn sets CC0 as a side-effect, we know it cannot affect | |
6d2f8887 | 611 | our computation and thus may be placed in a delay slot. */ |
ca545bb5 BM |
612 | |
613 | void | |
0c20a65f AJ |
614 | mark_set_resources (rtx x, struct resources *res, int in_dest, |
615 | enum mark_resource_type mark_type) | |
ca545bb5 | 616 | { |
770ae6cc RK |
617 | enum rtx_code code; |
618 | int i, j; | |
619 | unsigned int r; | |
620 | const char *format_ptr; | |
ca545bb5 BM |
621 | |
622 | restart: | |
623 | ||
624 | code = GET_CODE (x); | |
625 | ||
626 | switch (code) | |
627 | { | |
628 | case NOTE: | |
629 | case BARRIER: | |
630 | case CODE_LABEL: | |
631 | case USE: | |
632 | case CONST_INT: | |
633 | case CONST_DOUBLE: | |
091a3ac7 | 634 | case CONST_FIXED: |
69ef87e2 | 635 | case CONST_VECTOR: |
ca545bb5 BM |
636 | case LABEL_REF: |
637 | case SYMBOL_REF: | |
638 | case CONST: | |
639 | case PC: | |
640 | /* These don't set any resources. */ | |
641 | return; | |
642 | ||
643 | case CC0: | |
644 | if (in_dest) | |
645 | res->cc = 1; | |
646 | return; | |
647 | ||
648 | case CALL_INSN: | |
649 | /* Called routine modifies the condition code, memory, any registers | |
650 | that aren't saved across calls, global registers and anything | |
651 | explicitly CLOBBERed immediately after the CALL_INSN. */ | |
652 | ||
73780b74 | 653 | if (mark_type == MARK_SRC_DEST_CALL) |
ca545bb5 | 654 | { |
ca545bb5 BM |
655 | rtx link; |
656 | ||
657 | res->cc = res->memory = 1; | |
eef75f5e RS |
658 | |
659 | IOR_HARD_REG_SET (res->regs, regs_invalidated_by_call); | |
ca545bb5 | 660 | |
ca545bb5 BM |
661 | for (link = CALL_INSN_FUNCTION_USAGE (x); |
662 | link; link = XEXP (link, 1)) | |
663 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
73780b74 SC |
664 | mark_set_resources (SET_DEST (XEXP (link, 0)), res, 1, |
665 | MARK_SRC_DEST); | |
ca545bb5 | 666 | |
570a98eb | 667 | /* Check for a REG_SETJMP. If it exists, then we must |
ca545bb5 | 668 | assume that this call can clobber any register. */ |
570a98eb | 669 | if (find_reg_note (x, REG_SETJMP, NULL)) |
ca545bb5 BM |
670 | SET_HARD_REG_SET (res->regs); |
671 | } | |
672 | ||
673 | /* ... and also what its RTL says it modifies, if anything. */ | |
674 | ||
675 | case JUMP_INSN: | |
676 | case INSN: | |
677 | ||
678 | /* An insn consisting of just a CLOBBER (or USE) is just for flow | |
679 | and doesn't actually do anything, so we ignore it. */ | |
680 | ||
681 | #ifdef INSN_SETS_ARE_DELAYED | |
73780b74 | 682 | if (mark_type != MARK_SRC_DEST_CALL |
ca545bb5 BM |
683 | && INSN_SETS_ARE_DELAYED (x)) |
684 | return; | |
685 | #endif | |
686 | ||
687 | x = PATTERN (x); | |
688 | if (GET_CODE (x) != USE && GET_CODE (x) != CLOBBER) | |
689 | goto restart; | |
690 | return; | |
691 | ||
692 | case SET: | |
693 | /* If the source of a SET is a CALL, this is actually done by | |
694 | the called routine. So only include it if we are to include the | |
695 | effects of the calling routine. */ | |
696 | ||
697 | mark_set_resources (SET_DEST (x), res, | |
73780b74 | 698 | (mark_type == MARK_SRC_DEST_CALL |
ca545bb5 | 699 | || GET_CODE (SET_SRC (x)) != CALL), |
73780b74 | 700 | mark_type); |
ca545bb5 | 701 | |
73fb6466 | 702 | mark_set_resources (SET_SRC (x), res, 0, MARK_SRC_DEST); |
ca545bb5 BM |
703 | return; |
704 | ||
705 | case CLOBBER: | |
73780b74 | 706 | mark_set_resources (XEXP (x, 0), res, 1, MARK_SRC_DEST); |
ca545bb5 | 707 | return; |
a6a2274a | 708 | |
ca545bb5 BM |
709 | case SEQUENCE: |
710 | for (i = 0; i < XVECLEN (x, 0); i++) | |
711 | if (! (INSN_ANNULLED_BRANCH_P (XVECEXP (x, 0, 0)) | |
712 | && INSN_FROM_TARGET_P (XVECEXP (x, 0, i)))) | |
73780b74 | 713 | mark_set_resources (XVECEXP (x, 0, i), res, 0, mark_type); |
ca545bb5 BM |
714 | return; |
715 | ||
716 | case POST_INC: | |
717 | case PRE_INC: | |
718 | case POST_DEC: | |
719 | case PRE_DEC: | |
73780b74 | 720 | mark_set_resources (XEXP (x, 0), res, 1, MARK_SRC_DEST); |
ca545bb5 BM |
721 | return; |
722 | ||
4b983fdc RH |
723 | case PRE_MODIFY: |
724 | case POST_MODIFY: | |
1fb9c5cd MH |
725 | mark_set_resources (XEXP (x, 0), res, 1, MARK_SRC_DEST); |
726 | mark_set_resources (XEXP (XEXP (x, 1), 0), res, 0, MARK_SRC_DEST); | |
727 | mark_set_resources (XEXP (XEXP (x, 1), 1), res, 0, MARK_SRC_DEST); | |
4b983fdc RH |
728 | return; |
729 | ||
73780b74 | 730 | case SIGN_EXTRACT: |
ca545bb5 | 731 | case ZERO_EXTRACT: |
73fb6466 HPN |
732 | mark_set_resources (XEXP (x, 0), res, in_dest, MARK_SRC_DEST); |
733 | mark_set_resources (XEXP (x, 1), res, 0, MARK_SRC_DEST); | |
734 | mark_set_resources (XEXP (x, 2), res, 0, MARK_SRC_DEST); | |
ca545bb5 BM |
735 | return; |
736 | ||
737 | case MEM: | |
738 | if (in_dest) | |
739 | { | |
740 | res->memory = 1; | |
389fdba0 | 741 | res->unch_memory |= MEM_READONLY_P (x); |
a5045352 | 742 | res->volatil |= MEM_VOLATILE_P (x); |
ca545bb5 BM |
743 | } |
744 | ||
73780b74 | 745 | mark_set_resources (XEXP (x, 0), res, 0, MARK_SRC_DEST); |
ca545bb5 BM |
746 | return; |
747 | ||
748 | case SUBREG: | |
749 | if (in_dest) | |
750 | { | |
f8cfc6aa | 751 | if (!REG_P (SUBREG_REG (x))) |
73780b74 | 752 | mark_set_resources (SUBREG_REG (x), res, in_dest, mark_type); |
ca545bb5 BM |
753 | else |
754 | { | |
ddef6bc7 | 755 | unsigned int regno = subreg_regno (x); |
f1f4e530 | 756 | unsigned int last_regno = regno + subreg_nregs (x); |
770ae6cc | 757 | |
41374e13 | 758 | gcc_assert (last_regno <= FIRST_PSEUDO_REGISTER); |
770ae6cc RK |
759 | for (r = regno; r < last_regno; r++) |
760 | SET_HARD_REG_BIT (res->regs, r); | |
ca545bb5 BM |
761 | } |
762 | } | |
763 | return; | |
764 | ||
765 | case REG: | |
766 | if (in_dest) | |
1d2215fe | 767 | { |
09e18274 RS |
768 | gcc_assert (HARD_REGISTER_P (x)); |
769 | add_to_hard_reg_set (&res->regs, GET_MODE (x), REGNO (x)); | |
1d2215fe | 770 | } |
ca545bb5 BM |
771 | return; |
772 | ||
3d298f8f MM |
773 | case UNSPEC_VOLATILE: |
774 | case ASM_INPUT: | |
775 | /* Traditional asm's are always volatile. */ | |
776 | res->volatil = 1; | |
777 | return; | |
778 | ||
779 | case TRAP_IF: | |
780 | res->volatil = 1; | |
781 | break; | |
782 | ||
783 | case ASM_OPERANDS: | |
a5045352 | 784 | res->volatil |= MEM_VOLATILE_P (x); |
3d298f8f MM |
785 | |
786 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
787 | We can not just fall through here since then we would be confused | |
788 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
789 | traditional asms unlike their normal usage. */ | |
a6a2274a | 790 | |
3d298f8f | 791 | for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) |
73780b74 SC |
792 | mark_set_resources (ASM_OPERANDS_INPUT (x, i), res, in_dest, |
793 | MARK_SRC_DEST); | |
3d298f8f MM |
794 | return; |
795 | ||
ca545bb5 BM |
796 | default: |
797 | break; | |
798 | } | |
799 | ||
800 | /* Process each sub-expression and flag what it needs. */ | |
801 | format_ptr = GET_RTX_FORMAT (code); | |
802 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
803 | switch (*format_ptr++) | |
804 | { | |
805 | case 'e': | |
73780b74 | 806 | mark_set_resources (XEXP (x, i), res, in_dest, mark_type); |
ca545bb5 BM |
807 | break; |
808 | ||
809 | case 'E': | |
810 | for (j = 0; j < XVECLEN (x, i); j++) | |
73780b74 | 811 | mark_set_resources (XVECEXP (x, i, j), res, in_dest, mark_type); |
ca545bb5 BM |
812 | break; |
813 | } | |
814 | } | |
815 | \f | |
6e456a10 EB |
816 | /* Return TRUE if INSN is a return, possibly with a filled delay slot. */ |
817 | ||
818 | static bool | |
ed7a4b4b | 819 | return_insn_p (const_rtx insn) |
6e456a10 | 820 | { |
2ca202e7 | 821 | if (JUMP_P (insn) && GET_CODE (PATTERN (insn)) == RETURN) |
6e456a10 EB |
822 | return true; |
823 | ||
2ca202e7 | 824 | if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) |
6e456a10 EB |
825 | return return_insn_p (XVECEXP (PATTERN (insn), 0, 0)); |
826 | ||
827 | return false; | |
828 | } | |
829 | ||
ca545bb5 BM |
830 | /* Set the resources that are live at TARGET. |
831 | ||
832 | If TARGET is zero, we refer to the end of the current function and can | |
833 | return our precomputed value. | |
834 | ||
835 | Otherwise, we try to find out what is live by consulting the basic block | |
836 | information. This is tricky, because we must consider the actions of | |
837 | reload and jump optimization, which occur after the basic block information | |
838 | has been computed. | |
839 | ||
840 | Accordingly, we proceed as follows:: | |
841 | ||
842 | We find the previous BARRIER and look at all immediately following labels | |
843 | (with no intervening active insns) to see if any of them start a basic | |
844 | block. If we hit the start of the function first, we use block 0. | |
845 | ||
a1fa3e79 EB |
846 | Once we have found a basic block and a corresponding first insn, we can |
847 | accurately compute the live status (by starting at a label following a | |
848 | BARRIER, we are immune to actions taken by reload and jump.) Then we | |
849 | scan all insns between that point and our target. For each CLOBBER (or | |
850 | for call-clobbered regs when we pass a CALL_INSN), mark the appropriate | |
851 | registers are dead. For a SET, mark them as live. | |
ca545bb5 BM |
852 | |
853 | We have to be careful when using REG_DEAD notes because they are not | |
854 | updated by such things as find_equiv_reg. So keep track of registers | |
855 | marked as dead that haven't been assigned to, and mark them dead at the | |
856 | next CODE_LABEL since reload and jump won't propagate values across labels. | |
857 | ||
858 | If we cannot find the start of a basic block (should be a very rare | |
859 | case, if it can happen at all), mark everything as potentially live. | |
860 | ||
861 | Next, scan forward from TARGET looking for things set or clobbered | |
862 | before they are used. These are not live. | |
863 | ||
864 | Because we can be called many times on the same target, save our results | |
865 | in a hash table indexed by INSN_UID. This is only done if the function | |
866 | init_resource_info () was invoked before we are called. */ | |
867 | ||
868 | void | |
0c20a65f | 869 | mark_target_live_regs (rtx insns, rtx target, struct resources *res) |
ca545bb5 BM |
870 | { |
871 | int b = -1; | |
5197bd50 | 872 | unsigned int i; |
ca545bb5 BM |
873 | struct target_info *tinfo = NULL; |
874 | rtx insn; | |
875 | rtx jump_insn = 0; | |
876 | rtx jump_target; | |
877 | HARD_REG_SET scratch; | |
878 | struct resources set, needed; | |
879 | ||
880 | /* Handle end of function. */ | |
881 | if (target == 0) | |
882 | { | |
883 | *res = end_of_function_needs; | |
884 | return; | |
885 | } | |
886 | ||
6e456a10 EB |
887 | /* Handle return insn. */ |
888 | else if (return_insn_p (target)) | |
889 | { | |
890 | *res = end_of_function_needs; | |
675f99c9 | 891 | mark_referenced_resources (target, res, false); |
6e456a10 EB |
892 | return; |
893 | } | |
894 | ||
ca545bb5 BM |
895 | /* We have to assume memory is needed, but the CC isn't. */ |
896 | res->memory = 1; | |
897 | res->volatil = res->unch_memory = 0; | |
898 | res->cc = 0; | |
899 | ||
900 | /* See if we have computed this value already. */ | |
901 | if (target_hash_table != NULL) | |
902 | { | |
903 | for (tinfo = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME]; | |
904 | tinfo; tinfo = tinfo->next) | |
905 | if (tinfo->uid == INSN_UID (target)) | |
906 | break; | |
907 | ||
908 | /* Start by getting the basic block number. If we have saved | |
909 | information, we can get it from there unless the insn at the | |
910 | start of the basic block has been deleted. */ | |
911 | if (tinfo && tinfo->block != -1 | |
a813c111 | 912 | && ! INSN_DELETED_P (BB_HEAD (BASIC_BLOCK (tinfo->block)))) |
ca545bb5 BM |
913 | b = tinfo->block; |
914 | } | |
915 | ||
925fa227 | 916 | if (b == -1) |
d5d063d7 | 917 | b = find_basic_block (target, MAX_DELAY_SLOT_LIVE_SEARCH); |
ca545bb5 BM |
918 | |
919 | if (target_hash_table != NULL) | |
920 | { | |
921 | if (tinfo) | |
922 | { | |
923 | /* If the information is up-to-date, use it. Otherwise, we will | |
924 | update it below. */ | |
925 | if (b == tinfo->block && b != -1 && tinfo->bb_tick == bb_ticks[b]) | |
926 | { | |
927 | COPY_HARD_REG_SET (res->regs, tinfo->live_regs); | |
928 | return; | |
929 | } | |
930 | } | |
931 | else | |
932 | { | |
a6a2274a | 933 | /* Allocate a place to put our results and chain it into the |
ca545bb5 | 934 | hash table. */ |
5ed6ace5 | 935 | tinfo = XNEW (struct target_info); |
ca545bb5 BM |
936 | tinfo->uid = INSN_UID (target); |
937 | tinfo->block = b; | |
5197bd50 RK |
938 | tinfo->next |
939 | = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME]; | |
ca545bb5 BM |
940 | target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME] = tinfo; |
941 | } | |
942 | } | |
943 | ||
944 | CLEAR_HARD_REG_SET (pending_dead_regs); | |
945 | ||
946 | /* If we found a basic block, get the live registers from it and update | |
947 | them with anything set or killed between its start and the insn before | |
9d2bb902 EB |
948 | TARGET; this custom life analysis is really about registers so we need |
949 | to use the LR problem. Otherwise, we must assume everything is live. */ | |
ca545bb5 BM |
950 | if (b != -1) |
951 | { | |
9d2bb902 | 952 | regset regs_live = DF_LR_IN (BASIC_BLOCK (b)); |
ca545bb5 BM |
953 | rtx start_insn, stop_insn; |
954 | ||
a1fa3e79 | 955 | /* Compute hard regs live at start of block. */ |
ca545bb5 BM |
956 | REG_SET_TO_HARD_REG_SET (current_live_regs, regs_live); |
957 | ||
ca545bb5 BM |
958 | /* Get starting and ending insn, handling the case where each might |
959 | be a SEQUENCE. */ | |
6fb5fa3c DB |
960 | start_insn = (b == ENTRY_BLOCK_PTR->next_bb->index ? |
961 | insns : BB_HEAD (BASIC_BLOCK (b))); | |
ca545bb5 BM |
962 | stop_insn = target; |
963 | ||
4b4bf941 | 964 | if (NONJUMP_INSN_P (start_insn) |
ca545bb5 BM |
965 | && GET_CODE (PATTERN (start_insn)) == SEQUENCE) |
966 | start_insn = XVECEXP (PATTERN (start_insn), 0, 0); | |
967 | ||
4b4bf941 | 968 | if (NONJUMP_INSN_P (stop_insn) |
ca545bb5 BM |
969 | && GET_CODE (PATTERN (stop_insn)) == SEQUENCE) |
970 | stop_insn = next_insn (PREV_INSN (stop_insn)); | |
971 | ||
972 | for (insn = start_insn; insn != stop_insn; | |
973 | insn = next_insn_no_annul (insn)) | |
974 | { | |
975 | rtx link; | |
976 | rtx real_insn = insn; | |
cf40ea15 | 977 | enum rtx_code code = GET_CODE (insn); |
ca545bb5 | 978 | |
b5b8b0ac AO |
979 | if (DEBUG_INSN_P (insn)) |
980 | continue; | |
981 | ||
ca545bb5 BM |
982 | /* If this insn is from the target of a branch, it isn't going to |
983 | be used in the sequel. If it is used in both cases, this | |
984 | test will not be true. */ | |
cf40ea15 DM |
985 | if ((code == INSN || code == JUMP_INSN || code == CALL_INSN) |
986 | && INSN_FROM_TARGET_P (insn)) | |
ca545bb5 BM |
987 | continue; |
988 | ||
989 | /* If this insn is a USE made by update_block, we care about the | |
990 | underlying insn. */ | |
cf40ea15 | 991 | if (code == INSN && GET_CODE (PATTERN (insn)) == USE |
2c3c49de | 992 | && INSN_P (XEXP (PATTERN (insn), 0))) |
ca545bb5 BM |
993 | real_insn = XEXP (PATTERN (insn), 0); |
994 | ||
4b4bf941 | 995 | if (CALL_P (real_insn)) |
ca545bb5 BM |
996 | { |
997 | /* CALL clobbers all call-used regs that aren't fixed except | |
998 | sp, ap, and fp. Do this before setting the result of the | |
999 | call live. */ | |
12beba6f RH |
1000 | AND_COMPL_HARD_REG_SET (current_live_regs, |
1001 | regs_invalidated_by_call); | |
ca545bb5 BM |
1002 | |
1003 | /* A CALL_INSN sets any global register live, since it may | |
1004 | have been modified by the call. */ | |
1005 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1006 | if (global_regs[i]) | |
1007 | SET_HARD_REG_BIT (current_live_regs, i); | |
1008 | } | |
1009 | ||
1010 | /* Mark anything killed in an insn to be deadened at the next | |
1011 | label. Ignore USE insns; the only REG_DEAD notes will be for | |
1012 | parameters. But they might be early. A CALL_INSN will usually | |
1013 | clobber registers used for parameters. It isn't worth bothering | |
1014 | with the unlikely case when it won't. */ | |
4b4bf941 | 1015 | if ((NONJUMP_INSN_P (real_insn) |
ca545bb5 BM |
1016 | && GET_CODE (PATTERN (real_insn)) != USE |
1017 | && GET_CODE (PATTERN (real_insn)) != CLOBBER) | |
4b4bf941 JQ |
1018 | || JUMP_P (real_insn) |
1019 | || CALL_P (real_insn)) | |
ca545bb5 BM |
1020 | { |
1021 | for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1)) | |
1022 | if (REG_NOTE_KIND (link) == REG_DEAD | |
f8cfc6aa | 1023 | && REG_P (XEXP (link, 0)) |
ca545bb5 | 1024 | && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER) |
09e18274 RS |
1025 | add_to_hard_reg_set (&pending_dead_regs, |
1026 | GET_MODE (XEXP (link, 0)), | |
1027 | REGNO (XEXP (link, 0))); | |
ca545bb5 | 1028 | |
84832317 | 1029 | note_stores (PATTERN (real_insn), update_live_status, NULL); |
ca545bb5 BM |
1030 | |
1031 | /* If any registers were unused after this insn, kill them. | |
1032 | These notes will always be accurate. */ | |
1033 | for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1)) | |
1034 | if (REG_NOTE_KIND (link) == REG_UNUSED | |
f8cfc6aa | 1035 | && REG_P (XEXP (link, 0)) |
ca545bb5 | 1036 | && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER) |
09e18274 RS |
1037 | remove_from_hard_reg_set (¤t_live_regs, |
1038 | GET_MODE (XEXP (link, 0)), | |
1039 | REGNO (XEXP (link, 0))); | |
ca545bb5 BM |
1040 | } |
1041 | ||
4b4bf941 | 1042 | else if (LABEL_P (real_insn)) |
ca545bb5 | 1043 | { |
a1fa3e79 EB |
1044 | basic_block bb; |
1045 | ||
ca545bb5 BM |
1046 | /* A label clobbers the pending dead registers since neither |
1047 | reload nor jump will propagate a value across a label. */ | |
1048 | AND_COMPL_HARD_REG_SET (current_live_regs, pending_dead_regs); | |
1049 | CLEAR_HARD_REG_SET (pending_dead_regs); | |
a1fa3e79 EB |
1050 | |
1051 | /* We must conservatively assume that all registers that used | |
1052 | to be live here still are. The fallthrough edge may have | |
1053 | left a live register uninitialized. */ | |
1054 | bb = BLOCK_FOR_INSN (real_insn); | |
1055 | if (bb) | |
1056 | { | |
1057 | HARD_REG_SET extra_live; | |
1058 | ||
9d2bb902 | 1059 | REG_SET_TO_HARD_REG_SET (extra_live, DF_LR_IN (bb)); |
a1fa3e79 EB |
1060 | IOR_HARD_REG_SET (current_live_regs, extra_live); |
1061 | } | |
ca545bb5 BM |
1062 | } |
1063 | ||
1064 | /* The beginning of the epilogue corresponds to the end of the | |
1065 | RTL chain when there are no epilogue insns. Certain resources | |
1066 | are implicitly required at that point. */ | |
4b4bf941 | 1067 | else if (NOTE_P (real_insn) |
a38e7aa5 | 1068 | && NOTE_KIND (real_insn) == NOTE_INSN_EPILOGUE_BEG) |
ca545bb5 BM |
1069 | IOR_HARD_REG_SET (current_live_regs, start_of_epilogue_needs.regs); |
1070 | } | |
1071 | ||
1072 | COPY_HARD_REG_SET (res->regs, current_live_regs); | |
1073 | if (tinfo != NULL) | |
1074 | { | |
1075 | tinfo->block = b; | |
1076 | tinfo->bb_tick = bb_ticks[b]; | |
1077 | } | |
1078 | } | |
1079 | else | |
1080 | /* We didn't find the start of a basic block. Assume everything | |
1081 | in use. This should happen only extremely rarely. */ | |
1082 | SET_HARD_REG_SET (res->regs); | |
1083 | ||
1084 | CLEAR_RESOURCE (&set); | |
1085 | CLEAR_RESOURCE (&needed); | |
1086 | ||
1087 | jump_insn = find_dead_or_set_registers (target, res, &jump_target, 0, | |
1088 | set, needed); | |
1089 | ||
1090 | /* If we hit an unconditional branch, we have another way of finding out | |
1091 | what is live: we can see what is live at the branch target and include | |
96e9c98d | 1092 | anything used but not set before the branch. We add the live |
dc297297 | 1093 | resources found using the test below to those found until now. */ |
ca545bb5 BM |
1094 | |
1095 | if (jump_insn) | |
1096 | { | |
1097 | struct resources new_resources; | |
1098 | rtx stop_insn = next_active_insn (jump_insn); | |
1099 | ||
1100 | mark_target_live_regs (insns, next_active_insn (jump_target), | |
1101 | &new_resources); | |
1102 | CLEAR_RESOURCE (&set); | |
1103 | CLEAR_RESOURCE (&needed); | |
1104 | ||
1105 | /* Include JUMP_INSN in the needed registers. */ | |
1106 | for (insn = target; insn != stop_insn; insn = next_active_insn (insn)) | |
1107 | { | |
675f99c9 | 1108 | mark_referenced_resources (insn, &needed, true); |
ca545bb5 BM |
1109 | |
1110 | COPY_HARD_REG_SET (scratch, needed.regs); | |
1111 | AND_COMPL_HARD_REG_SET (scratch, set.regs); | |
1112 | IOR_HARD_REG_SET (new_resources.regs, scratch); | |
1113 | ||
73780b74 | 1114 | mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL); |
ca545bb5 BM |
1115 | } |
1116 | ||
96e9c98d | 1117 | IOR_HARD_REG_SET (res->regs, new_resources.regs); |
ca545bb5 BM |
1118 | } |
1119 | ||
1120 | if (tinfo != NULL) | |
1121 | { | |
1122 | COPY_HARD_REG_SET (tinfo->live_regs, res->regs); | |
1123 | } | |
1124 | } | |
1125 | \f | |
1126 | /* Initialize the resources required by mark_target_live_regs (). | |
1127 | This should be invoked before the first call to mark_target_live_regs. */ | |
1128 | ||
1129 | void | |
0c20a65f | 1130 | init_resource_info (rtx epilogue_insn) |
ca545bb5 BM |
1131 | { |
1132 | int i; | |
a1fa3e79 | 1133 | basic_block bb; |
ca545bb5 BM |
1134 | |
1135 | /* Indicate what resources are required to be valid at the end of the current | |
1136 | function. The condition code never is and memory always is. If the | |
1137 | frame pointer is needed, it is and so is the stack pointer unless | |
40f03658 | 1138 | EXIT_IGNORE_STACK is nonzero. If the frame pointer is not needed, the |
ca545bb5 BM |
1139 | stack pointer is. Registers used to return the function value are |
1140 | needed. Registers holding global variables are needed. */ | |
1141 | ||
1142 | end_of_function_needs.cc = 0; | |
1143 | end_of_function_needs.memory = 1; | |
1144 | end_of_function_needs.unch_memory = 0; | |
1145 | CLEAR_HARD_REG_SET (end_of_function_needs.regs); | |
1146 | ||
1147 | if (frame_pointer_needed) | |
1148 | { | |
1149 | SET_HARD_REG_BIT (end_of_function_needs.regs, FRAME_POINTER_REGNUM); | |
1150 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
1151 | SET_HARD_REG_BIT (end_of_function_needs.regs, HARD_FRAME_POINTER_REGNUM); | |
1152 | #endif | |
ca545bb5 BM |
1153 | if (! EXIT_IGNORE_STACK |
1154 | || current_function_sp_is_unchanging) | |
ca545bb5 BM |
1155 | SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM); |
1156 | } | |
1157 | else | |
1158 | SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM); | |
1159 | ||
38173d38 JH |
1160 | if (crtl->return_rtx != 0) |
1161 | mark_referenced_resources (crtl->return_rtx, | |
675f99c9 | 1162 | &end_of_function_needs, true); |
ca545bb5 BM |
1163 | |
1164 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1165 | if (global_regs[i] | |
1166 | #ifdef EPILOGUE_USES | |
1167 | || EPILOGUE_USES (i) | |
1168 | #endif | |
1169 | ) | |
1170 | SET_HARD_REG_BIT (end_of_function_needs.regs, i); | |
1171 | ||
1172 | /* The registers required to be live at the end of the function are | |
1173 | represented in the flow information as being dead just prior to | |
1174 | reaching the end of the function. For example, the return of a value | |
1175 | might be represented by a USE of the return register immediately | |
1176 | followed by an unconditional jump to the return label where the | |
1177 | return label is the end of the RTL chain. The end of the RTL chain | |
1178 | is then taken to mean that the return register is live. | |
1179 | ||
1180 | This sequence is no longer maintained when epilogue instructions are | |
1181 | added to the RTL chain. To reconstruct the original meaning, the | |
1182 | start of the epilogue (NOTE_INSN_EPILOGUE_BEG) is regarded as the | |
1183 | point where these registers become live (start_of_epilogue_needs). | |
1184 | If epilogue instructions are present, the registers set by those | |
1185 | instructions won't have been processed by flow. Thus, those | |
1186 | registers are additionally required at the end of the RTL chain | |
1187 | (end_of_function_needs). */ | |
1188 | ||
1189 | start_of_epilogue_needs = end_of_function_needs; | |
1190 | ||
1191 | while ((epilogue_insn = next_nonnote_insn (epilogue_insn))) | |
6e456a10 EB |
1192 | { |
1193 | mark_set_resources (epilogue_insn, &end_of_function_needs, 0, | |
1194 | MARK_SRC_DEST_CALL); | |
1195 | if (return_insn_p (epilogue_insn)) | |
1196 | break; | |
1197 | } | |
ca545bb5 BM |
1198 | |
1199 | /* Allocate and initialize the tables used by mark_target_live_regs. */ | |
5ed6ace5 MD |
1200 | target_hash_table = XCNEWVEC (struct target_info *, TARGET_HASH_PRIME); |
1201 | bb_ticks = XCNEWVEC (int, last_basic_block); | |
a1fa3e79 EB |
1202 | |
1203 | /* Set the BLOCK_FOR_INSN of each label that starts a basic block. */ | |
1204 | FOR_EACH_BB (bb) | |
1205 | if (LABEL_P (BB_HEAD (bb))) | |
1206 | BLOCK_FOR_INSN (BB_HEAD (bb)) = bb; | |
ca545bb5 BM |
1207 | } |
1208 | \f | |
14b493d6 | 1209 | /* Free up the resources allocated to mark_target_live_regs (). This |
ca545bb5 BM |
1210 | should be invoked after the last call to mark_target_live_regs (). */ |
1211 | ||
1212 | void | |
0c20a65f | 1213 | free_resource_info (void) |
ca545bb5 | 1214 | { |
a1fa3e79 EB |
1215 | basic_block bb; |
1216 | ||
ca545bb5 BM |
1217 | if (target_hash_table != NULL) |
1218 | { | |
1f8f4a0b | 1219 | int i; |
a6a2274a KH |
1220 | |
1221 | for (i = 0; i < TARGET_HASH_PRIME; ++i) | |
1f8f4a0b MM |
1222 | { |
1223 | struct target_info *ti = target_hash_table[i]; | |
1224 | ||
a6a2274a | 1225 | while (ti) |
1f8f4a0b MM |
1226 | { |
1227 | struct target_info *next = ti->next; | |
1228 | free (ti); | |
1229 | ti = next; | |
1230 | } | |
1231 | } | |
1232 | ||
ca545bb5 BM |
1233 | free (target_hash_table); |
1234 | target_hash_table = NULL; | |
1235 | } | |
1236 | ||
1237 | if (bb_ticks != NULL) | |
1238 | { | |
1239 | free (bb_ticks); | |
1240 | bb_ticks = NULL; | |
1241 | } | |
a1fa3e79 EB |
1242 | |
1243 | FOR_EACH_BB (bb) | |
1244 | if (LABEL_P (BB_HEAD (bb))) | |
1245 | BLOCK_FOR_INSN (BB_HEAD (bb)) = NULL; | |
ca545bb5 BM |
1246 | } |
1247 | \f | |
1248 | /* Clear any hashed information that we have stored for INSN. */ | |
1249 | ||
1250 | void | |
0c20a65f | 1251 | clear_hashed_info_for_insn (rtx insn) |
ca545bb5 BM |
1252 | { |
1253 | struct target_info *tinfo; | |
a6a2274a | 1254 | |
ca545bb5 BM |
1255 | if (target_hash_table != NULL) |
1256 | { | |
1257 | for (tinfo = target_hash_table[INSN_UID (insn) % TARGET_HASH_PRIME]; | |
1258 | tinfo; tinfo = tinfo->next) | |
1259 | if (tinfo->uid == INSN_UID (insn)) | |
1260 | break; | |
1261 | ||
1262 | if (tinfo) | |
1263 | tinfo->block = -1; | |
1264 | } | |
1265 | } | |
1266 | \f | |
1267 | /* Increment the tick count for the basic block that contains INSN. */ | |
1268 | ||
1269 | void | |
0c20a65f | 1270 | incr_ticks_for_insn (rtx insn) |
ca545bb5 | 1271 | { |
d5d063d7 | 1272 | int b = find_basic_block (insn, MAX_DELAY_SLOT_LIVE_SEARCH); |
ca545bb5 BM |
1273 | |
1274 | if (b != -1) | |
1275 | bb_ticks[b]++; | |
1276 | } | |
1277 | \f | |
1278 | /* Add TRIAL to the set of resources used at the end of the current | |
dc297297 | 1279 | function. */ |
ca545bb5 | 1280 | void |
675f99c9 | 1281 | mark_end_of_function_resources (rtx trial, bool include_delayed_effects) |
ca545bb5 BM |
1282 | { |
1283 | mark_referenced_resources (trial, &end_of_function_needs, | |
1284 | include_delayed_effects); | |
1285 | } |