]>
Commit | Line | Data |
---|---|---|
73b75827 | 1 | // Implementation of instruction-related RTL SSA functions -*- C++ -*- |
7adcbafe | 2 | // Copyright (C) 2020-2022 Free Software Foundation, Inc. |
73b75827 RS |
3 | // |
4 | // This file is part of GCC. | |
5 | // | |
6 | // GCC is free software; you can redistribute it and/or modify it under | |
7 | // the terms of the GNU General Public License as published by the Free | |
8 | // Software Foundation; either version 3, or (at your option) any later | |
9 | // version. | |
10 | // | |
11 | // GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
12 | // WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | // for more details. | |
15 | // | |
16 | // You should have received a copy of the GNU General Public License | |
17 | // along with GCC; see the file COPYING3. If not see | |
18 | // <http://www.gnu.org/licenses/>. | |
19 | ||
20 | #define INCLUDE_ALGORITHM | |
21 | #define INCLUDE_FUNCTIONAL | |
22 | #include "config.h" | |
23 | #include "system.h" | |
24 | #include "coretypes.h" | |
25 | #include "backend.h" | |
26 | #include "rtl.h" | |
27 | #include "df.h" | |
28 | #include "rtl-ssa.h" | |
abe07a74 | 29 | #include "rtl-ssa/internals.h" |
73b75827 RS |
30 | #include "rtl-ssa/internals.inl" |
31 | #include "predict.h" | |
32 | #include "print-rtl.h" | |
33 | #include "rtl-iter.h" | |
34 | ||
35 | using namespace rtl_ssa; | |
36 | ||
37 | // The gap to leave between program points when building up the list | |
38 | // of instructions for the first time. Using 2 allows an instruction | |
39 | // to be inserted between two others without resorting to splay tree | |
40 | // ordering. Using 0 is useful as a debugging aid to stress the | |
41 | // splay tree code. | |
42 | static const unsigned int POINT_INCREASE = 2; | |
43 | ||
44 | // Calculate and record the cost of the instruction, based on the | |
45 | // form it had before any in-progress changes were made. | |
46 | void | |
47 | insn_info::calculate_cost () const | |
48 | { | |
49 | basic_block cfg_bb = BLOCK_FOR_INSN (m_rtl); | |
50 | temporarily_undo_changes (0); | |
51 | m_cost_or_uid = insn_cost (m_rtl, optimize_bb_for_speed_p (cfg_bb)); | |
52 | redo_changes (0); | |
53 | } | |
54 | ||
55 | // Add NOTE to the instruction's notes. | |
56 | void | |
57 | insn_info::add_note (insn_note *note) | |
58 | { | |
59 | insn_note **ptr = &m_first_note; | |
60 | // Always put the order node first, since it's the one that's likely | |
61 | // to be used most often. | |
62 | if (*ptr && (*ptr)->kind () == insn_note_kind::ORDER_NODE) | |
63 | ptr = &(*ptr)->m_next_note; | |
64 | note->m_next_note = *ptr; | |
65 | *ptr = note; | |
66 | } | |
67 | ||
68 | // Implement compare_with for the case in which this insn and OTHER | |
69 | // have the same program point. | |
70 | int | |
71 | insn_info::slow_compare_with (const insn_info &other) const | |
72 | { | |
73 | return order_splay_tree::compare_nodes (get_known_order_node (), | |
74 | other.get_known_order_node ()); | |
75 | } | |
76 | ||
77 | // Print insn uid UID to PP, where UID has the same form as insn_info::uid. | |
78 | void | |
79 | insn_info::print_uid (pretty_printer *pp, int uid) | |
80 | { | |
81 | char tmp[3 * sizeof (uid) + 2]; | |
82 | if (uid < 0) | |
83 | // An artificial instruction. | |
84 | snprintf (tmp, sizeof (tmp), "a%d", -uid); | |
85 | else | |
86 | // A real RTL instruction. | |
87 | snprintf (tmp, sizeof (tmp), "i%d", uid); | |
88 | pp_string (pp, tmp); | |
89 | } | |
90 | ||
91 | // See comment above declaration. | |
92 | void | |
93 | insn_info::print_identifier (pretty_printer *pp) const | |
94 | { | |
95 | print_uid (pp, uid ()); | |
96 | } | |
97 | ||
98 | // See comment above declaration. | |
99 | void | |
100 | insn_info::print_location (pretty_printer *pp) const | |
101 | { | |
102 | if (bb_info *bb = this->bb ()) | |
103 | { | |
104 | ebb_info *ebb = bb->ebb (); | |
105 | if (ebb && is_phi ()) | |
106 | ebb->print_identifier (pp); | |
107 | else | |
108 | bb->print_identifier (pp); | |
109 | pp_string (pp, " at point "); | |
110 | pp_decimal_int (pp, m_point); | |
111 | } | |
112 | else | |
113 | pp_string (pp, "<unknown location>"); | |
114 | } | |
115 | ||
116 | // See comment above declaration. | |
117 | void | |
118 | insn_info::print_identifier_and_location (pretty_printer *pp) const | |
119 | { | |
120 | if (m_is_asm) | |
121 | pp_string (pp, "asm "); | |
122 | if (m_is_debug_insn) | |
123 | pp_string (pp, "debug "); | |
124 | pp_string (pp, "insn "); | |
125 | print_identifier (pp); | |
126 | pp_string (pp, " in "); | |
127 | print_location (pp); | |
128 | } | |
129 | ||
130 | // See comment above declaration. | |
131 | void | |
132 | insn_info::print_full (pretty_printer *pp) const | |
133 | { | |
134 | print_identifier_and_location (pp); | |
135 | pp_colon (pp); | |
136 | if (is_real ()) | |
137 | { | |
138 | pp_newline_and_indent (pp, 2); | |
139 | if (has_been_deleted ()) | |
140 | pp_string (pp, "deleted"); | |
141 | else | |
142 | { | |
143 | // Print the insn pattern to a temporary printer. | |
144 | pretty_printer sub_pp; | |
145 | print_insn_with_notes (&sub_pp, rtl ()); | |
146 | const char *text = pp_formatted_text (&sub_pp); | |
147 | ||
148 | // Calculate the length of the maximum line in the pattern. | |
149 | unsigned int max_len = 0; | |
150 | const char *start = text; | |
151 | while (const char *end = strchr (start, '\n')) | |
152 | { | |
153 | max_len = MAX (max_len, (unsigned int) (end - start)); | |
154 | start = end + 1; | |
155 | } | |
156 | ||
157 | // Print a separator before or after the pattern. | |
158 | auto print_top_bottom = [&]() | |
159 | { | |
160 | pp_character (pp, '+'); | |
161 | for (unsigned int i = 0; i < max_len + 2; ++i) | |
162 | pp_character (pp, '-'); | |
163 | }; | |
164 | ||
165 | print_top_bottom (); | |
166 | start = text; | |
167 | while (const char *end = strchr (start, '\n')) | |
168 | { | |
169 | pp_newline_and_indent (pp, 0); | |
170 | pp_character (pp, '|'); | |
171 | // Each line of the pattern already starts with a space. | |
172 | // so we don't need to add another one here. | |
173 | pp_append_text (pp, start, end); | |
174 | start = end + 1; | |
175 | } | |
176 | pp_newline_and_indent (pp, 0); | |
177 | print_top_bottom (); | |
178 | ||
179 | if (m_cost_or_uid != UNKNOWN_COST) | |
180 | { | |
181 | pp_newline_and_indent (pp, 0); | |
182 | pp_string (pp, "cost: "); | |
183 | pp_decimal_int (pp, m_cost_or_uid); | |
184 | } | |
185 | if (m_has_pre_post_modify) | |
186 | { | |
187 | pp_newline_and_indent (pp, 0); | |
188 | pp_string (pp, "has pre/post-modify operations"); | |
189 | } | |
190 | if (m_has_volatile_refs) | |
191 | { | |
192 | pp_newline_and_indent (pp, 0); | |
193 | pp_string (pp, "has volatile refs"); | |
194 | } | |
195 | } | |
196 | pp_indentation (pp) -= 2; | |
197 | } | |
198 | ||
199 | auto print_accesses = [&](const char *heading, access_array accesses, | |
200 | unsigned int flags) | |
201 | { | |
202 | if (!accesses.empty ()) | |
203 | { | |
204 | pp_newline_and_indent (pp, 2); | |
205 | pp_string (pp, heading); | |
206 | pp_newline_and_indent (pp, 2); | |
207 | pp_accesses (pp, accesses, flags); | |
208 | pp_indentation (pp) -= 4; | |
209 | } | |
210 | }; | |
211 | ||
212 | print_accesses ("uses:", uses (), PP_ACCESS_USER); | |
213 | auto *call_clobbers_note = find_note<insn_call_clobbers_note> (); | |
214 | if (call_clobbers_note) | |
215 | { | |
216 | pp_newline_and_indent (pp, 2); | |
217 | pp_string (pp, "has call clobbers for ABI "); | |
218 | pp_decimal_int (pp, call_clobbers_note->abi_id ()); | |
219 | pp_indentation (pp) -= 2; | |
220 | } | |
221 | print_accesses ("defines:", defs (), PP_ACCESS_SETTER); | |
222 | if (num_uses () == 0 && !call_clobbers_note && num_defs () == 0) | |
223 | { | |
224 | pp_newline_and_indent (pp, 2); | |
225 | pp_string (pp, "has no uses or defs"); | |
226 | pp_indentation (pp) -= 2; | |
227 | } | |
228 | ||
229 | if (order_node *node = get_order_node ()) | |
230 | { | |
231 | while (node->m_parent) | |
232 | node = node->m_parent; | |
233 | ||
234 | pp_newline_and_indent (pp, 2); | |
235 | pp_string (pp, "insn order: "); | |
236 | pp_newline_and_indent (pp, 2); | |
237 | auto print_order = [](pretty_printer *pp, order_node *node) | |
238 | { | |
239 | print_uid (pp, node->uid ()); | |
240 | }; | |
241 | order_splay_tree::print (pp, node, print_order); | |
242 | pp_indentation (pp) -= 4; | |
243 | } | |
244 | } | |
245 | ||
246 | // Return an insn_info::order_node for INSN, creating one if necessary. | |
247 | insn_info::order_node * | |
248 | function_info::need_order_node (insn_info *insn) | |
249 | { | |
250 | insn_info::order_node *order = insn->get_order_node (); | |
251 | if (!order) | |
252 | { | |
253 | order = allocate<insn_info::order_node> (insn->uid ()); | |
254 | insn->add_note (order); | |
255 | } | |
256 | return order; | |
257 | } | |
258 | ||
259 | // Add instruction INSN immediately after AFTER in the reverse postorder list. | |
260 | // INSN is not currently in the list. | |
261 | void | |
262 | function_info::add_insn_after (insn_info *insn, insn_info *after) | |
263 | { | |
264 | gcc_checking_assert (!insn->has_insn_links ()); | |
265 | ||
266 | insn->copy_next_from (after); | |
267 | after->set_next_any_insn (insn); | |
268 | ||
269 | // The prev link is easy if AFTER and INSN are the same type. | |
270 | // Handle the other cases below. | |
271 | if (after->is_debug_insn () == insn->is_debug_insn ()) | |
272 | insn->set_prev_sametype_insn (after); | |
273 | ||
274 | if (insn_info *next = insn->next_any_insn ()) | |
275 | { | |
276 | if (insn->is_debug_insn () == next->is_debug_insn ()) | |
277 | { | |
278 | // INSN might now be the start of the subsequence of debug insns, | |
279 | // and so its prev pointer might point to the end of the subsequence | |
280 | // instead of AFTER. | |
281 | insn->copy_prev_from (next); | |
282 | next->set_prev_sametype_insn (insn); | |
283 | } | |
284 | else if (insn->is_debug_insn ()) // && !next->is_debug_insn () | |
285 | { | |
286 | // INSN ends a subsequence of debug instructions. Find the | |
287 | // first debug instruction in the subsequence, which might | |
288 | // be INSN itself. (If it isn't, then AFTER is also a debug | |
289 | // instruction and we updated INSN's prev link above.) | |
290 | insn_info *first = next->prev_nondebug_insn ()->next_any_insn (); | |
291 | first->set_last_debug_insn (insn); | |
292 | } | |
293 | else // !insn->is_debug_insn () && next->is_debug_insn () | |
294 | // At present we don't (need to) support inserting a nondebug | |
295 | // instruction between two existing debug instructions. | |
296 | gcc_assert (!after->is_debug_insn ()); | |
297 | ||
298 | // If AFTER and NEXT are separated by at least two points, we can | |
299 | // use a unique point number for INSN. Otherwise INSN will have | |
300 | // the same point number as AFTER. | |
301 | insn->set_point ((next->point () + after->point ()) / 2); | |
302 | } | |
303 | else | |
304 | { | |
305 | if (!insn->is_debug_insn ()) | |
306 | { | |
307 | insn->set_prev_sametype_insn (m_last_nondebug_insn); | |
308 | m_last_nondebug_insn = insn; | |
309 | } | |
310 | else | |
311 | // There is now at least one debug instruction after | |
312 | // m_last_nondebug_insn: either INSN itself, or the start of | |
313 | // a longer subsequence of debug insns that now ends with AFTER | |
314 | // followed by INSN. | |
315 | m_last_nondebug_insn->next_any_insn ()->set_last_debug_insn (insn); | |
316 | m_last_insn = insn; | |
317 | ||
318 | insn->set_point (after->point () + POINT_INCREASE); | |
319 | } | |
320 | ||
321 | // If INSN's program point is the same as AFTER's, we need to use the | |
322 | // splay tree to record their relative order. | |
323 | if (insn->point () == after->point ()) | |
324 | { | |
325 | insn_info::order_node *after_node = need_order_node (after); | |
326 | insn_info::order_node *insn_node = need_order_node (insn); | |
327 | insn_info::order_splay_tree::insert_child (after_node, 1, insn_node); | |
328 | } | |
329 | } | |
330 | ||
331 | // Remove INSN from the function's list of instructions. | |
332 | void | |
333 | function_info::remove_insn (insn_info *insn) | |
334 | { | |
335 | if (insn_info::order_node *order = insn->get_order_node ()) | |
336 | insn_info::order_splay_tree::remove_node (order); | |
337 | ||
338 | if (auto *note = insn->find_note<insn_call_clobbers_note> ()) | |
339 | { | |
340 | ebb_call_clobbers_info *ecc = insn->ebb ()->first_call_clobbers (); | |
341 | while (ecc->abi ()->id () != note->abi_id ()) | |
342 | ecc = ecc->next (); | |
343 | int comparison = lookup_call_clobbers (*ecc, insn); | |
344 | gcc_assert (comparison == 0); | |
345 | ecc->remove_root (); | |
346 | } | |
347 | ||
348 | insn_info *prev = insn->prev_any_insn (); | |
349 | insn_info *next = insn->next_any_insn (); | |
350 | insn_info *prev_nondebug = insn->prev_nondebug_insn (); | |
351 | insn_info *next_nondebug = insn->next_nondebug_insn (); | |
352 | ||
353 | // We should never remove the entry or exit block's instructions. | |
354 | // At present we also don't remove entire blocks, so should never | |
355 | // remove debug instructions. | |
356 | gcc_checking_assert (prev_nondebug | |
357 | && next_nondebug | |
358 | && !insn->is_debug_insn ()); | |
359 | ||
360 | if (prev->is_debug_insn () && next->is_debug_insn ()) | |
361 | { | |
362 | // We need to stitch together two subsequences of debug insns. | |
363 | insn_info *last = next->last_debug_insn (); | |
364 | next->set_prev_sametype_insn (prev); | |
365 | prev_nondebug->next_any_insn ()->set_last_debug_insn (last); | |
366 | } | |
367 | prev->set_next_any_insn (next); | |
368 | next_nondebug->set_prev_sametype_insn (prev_nondebug); | |
369 | ||
370 | insn->clear_insn_links (); | |
371 | } | |
372 | ||
373 | // Create an artificial instruction for BB, associating it with RTL (which can | |
374 | // be null). Add the new instruction to the end of the function's list and | |
375 | // return the new instruction. | |
376 | insn_info * | |
377 | function_info::append_artificial_insn (bb_info *bb, rtx_insn *rtl) | |
378 | { | |
379 | insn_info *insn = allocate<insn_info> (bb, rtl, m_next_artificial_uid); | |
380 | m_next_artificial_uid -= 1; | |
381 | append_insn (insn); | |
382 | return insn; | |
383 | } | |
384 | ||
385 | // Finish building a new list of uses and definitions for instruction INSN. | |
386 | void | |
387 | function_info::finish_insn_accesses (insn_info *insn) | |
388 | { | |
389 | unsigned int num_defs = m_temp_defs.length (); | |
390 | unsigned int num_uses = m_temp_uses.length (); | |
391 | obstack_make_room (&m_obstack, num_defs + num_uses); | |
392 | if (num_defs) | |
393 | { | |
394 | sort_accesses (m_temp_defs); | |
395 | obstack_grow (&m_obstack, m_temp_defs.address (), | |
396 | num_defs * sizeof (access_info *)); | |
397 | m_temp_defs.truncate (0); | |
398 | } | |
399 | if (num_uses) | |
400 | { | |
401 | sort_accesses (m_temp_uses); | |
402 | obstack_grow (&m_obstack, m_temp_uses.address (), | |
403 | num_uses * sizeof (access_info *)); | |
404 | m_temp_uses.truncate (0); | |
405 | } | |
406 | void *addr = obstack_finish (&m_obstack); | |
407 | insn->set_accesses (static_cast<access_info **> (addr), num_defs, num_uses); | |
408 | } | |
409 | ||
abe07a74 RS |
410 | // Called while building SSA form using BI. Create and return a use of |
411 | // register RESOURCE in INSN. Create a degenerate phi where necessary. | |
412 | use_info * | |
413 | function_info::create_reg_use (build_info &bi, insn_info *insn, | |
414 | resource_info resource) | |
415 | { | |
416 | set_info *value = bi.current_reg_value (resource.regno); | |
417 | if (value && value->ebb () != bi.current_ebb) | |
418 | { | |
419 | if (insn->is_debug_insn ()) | |
420 | value = look_through_degenerate_phi (value); | |
421 | else if (bitmap_bit_p (bi.potential_phi_regs, resource.regno)) | |
422 | { | |
423 | // VALUE is defined by a previous EBB and RESOURCE has multiple | |
424 | // definitions. Create a degenerate phi in the current EBB | |
425 | // so that all definitions and uses follow a linear RPO view; | |
426 | // see rtl.texi for details. | |
427 | access_info *inputs[] = { look_through_degenerate_phi (value) }; | |
428 | value = create_phi (bi.current_ebb, value->resource (), inputs, 1); | |
429 | bi.record_reg_def (value); | |
430 | } | |
431 | } | |
432 | auto *use = allocate<use_info> (insn, resource, value); | |
433 | add_use (use); | |
434 | return use; | |
435 | } | |
436 | ||
73b75827 RS |
437 | // Called while building SSA form using BI. Record that INSN contains |
438 | // read reference REF. If this requires new entries to be added to | |
439 | // INSN->uses (), add those entries to the list we're building in | |
440 | // m_temp_uses. | |
441 | void | |
442 | function_info::record_use (build_info &bi, insn_info *insn, | |
443 | rtx_obj_reference ref) | |
444 | { | |
445 | unsigned int regno = ref.regno; | |
446 | machine_mode mode = ref.is_reg () ? ref.mode : BLKmode; | |
447 | access_info *access = bi.last_access[ref.regno + 1]; | |
448 | use_info *use = safe_dyn_cast<use_info *> (access); | |
449 | if (!use) | |
450 | { | |
451 | set_info *value = safe_dyn_cast<set_info *> (access); | |
452 | // In order to ensure that -g doesn't affect codegen, uses in debug | |
453 | // instructions do not affect liveness, either in DF or here. | |
454 | // This means that there might be no correct definition of the resource | |
455 | // available (e.g. if it would require a phi node that the nondebug | |
456 | // code doesn't need). Perhaps we could have "debug phi nodes" as | |
457 | // well as "debug instructions", but that would require a method | |
458 | // of building phi nodes that didn't depend on DF liveness information, | |
459 | // and so might be significantly more expensive. | |
460 | // | |
461 | // Therefore, the only value we try to attach to a use by a debug | |
462 | // instruction is VALUE itself (as we would for nondebug instructions). | |
463 | // We then need to make a conservative check for whether VALUE is | |
464 | // actually correct. | |
465 | auto value_is_valid = [&]() | |
466 | { | |
467 | // Memmory always has a valid definition. | |
468 | if (ref.is_mem ()) | |
469 | return true; | |
470 | ||
471 | // If VALUE would lead to an uninitialized use anyway, there's | |
472 | // nothing to check. | |
473 | if (!value) | |
474 | return false; | |
475 | ||
476 | // If the previous definition occurs in the same EBB then it | |
477 | // is certainly correct. | |
478 | if (value->ebb () == bi.current_ebb) | |
479 | return true; | |
480 | ||
abe07a74 RS |
481 | // Check if VALUE is the function's only definition of REGNO. |
482 | // (We already know that it dominates the use.) | |
483 | if (!bitmap_bit_p (bi.potential_phi_regs, regno)) | |
484 | return true; | |
485 | ||
73b75827 RS |
486 | // If the register is live on entry to the EBB but not used |
487 | // within it, VALUE is the correct live-in value. | |
abe07a74 RS |
488 | if (!bi.ebb_live_in_for_debug) |
489 | calculate_ebb_live_in_for_debug (bi); | |
73b75827 RS |
490 | if (bitmap_bit_p (bi.ebb_live_in_for_debug, regno)) |
491 | return true; | |
492 | ||
73b75827 RS |
493 | // Punt for other cases. |
494 | return false; | |
495 | }; | |
496 | if (insn->is_debug_insn () && !value_is_valid ()) | |
497 | value = nullptr; | |
498 | ||
abe07a74 | 499 | use = create_reg_use (bi, insn, { mode, regno }); |
73b75827 RS |
500 | m_temp_uses.safe_push (use); |
501 | bi.last_access[ref.regno + 1] = use; | |
502 | use->record_reference (ref, true); | |
503 | } | |
504 | else | |
505 | { | |
506 | // Record the mode of the largest use. The choice is arbitrary if | |
507 | // the instruction (unusually) references the same register in two | |
508 | // different but equal-sized modes. | |
509 | gcc_checking_assert (use->insn () == insn); | |
510 | if (HARD_REGISTER_NUM_P (regno) | |
511 | && partial_subreg_p (use->mode (), mode)) | |
512 | use->set_mode (mode); | |
513 | use->record_reference (ref, false); | |
514 | } | |
515 | } | |
516 | ||
517 | // Called while building SSA form for INSN using BI. Record the effect | |
518 | // of call clobbers in RTL. We have already added the explicit sets and | |
519 | // clobbers for RTL, which have priority over any call clobbers. | |
520 | void | |
521 | function_info::record_call_clobbers (build_info &bi, insn_info *insn, | |
522 | rtx_call_insn *rtl) | |
523 | { | |
524 | // See whether we should record this call in the EBB's list of | |
525 | // call clobbers. Three things affect this choice: | |
526 | // | |
527 | // (1) The list is the only way we have of recording partial clobbers. | |
528 | // All calls that only partially clobber registers must therefore | |
529 | // be in the list. | |
530 | // | |
531 | // (2) Adding calls to the list is much more memory-efficient than | |
532 | // creating a long list of clobber_infos. | |
533 | // | |
534 | // (3) Adding calls to the list limits the ability to move definitions | |
535 | // of registers that are normally fully or partially clobbered | |
536 | // by the associated predefined ABI. So adding calls to the list | |
537 | // can hamper optimization if (thanks to -fipa-ra) the number of | |
538 | // clobbers is much smaller than the usual set. | |
539 | // | |
540 | // The trade-off that we currently take is to use the list if there | |
541 | // are some registers that the call only partially clobbers or if | |
542 | // the set of clobbers is the standard set. | |
543 | function_abi abi = insn_callee_abi (rtl); | |
544 | if (abi.base_abi ().full_reg_clobbers () == abi.full_reg_clobbers () | |
545 | || abi.full_and_partial_reg_clobbers () != abi.full_reg_clobbers ()) | |
546 | { | |
547 | // Find an entry for this predefined ABI, creating one if necessary. | |
548 | ebb_call_clobbers_info *ecc = bi.current_ebb->first_call_clobbers (); | |
549 | while (ecc && ecc->abi () != &abi.base_abi ()) | |
550 | ecc = ecc->next (); | |
551 | if (!ecc) | |
552 | { | |
553 | ecc = allocate<ebb_call_clobbers_info> (&abi.base_abi ()); | |
554 | ecc->m_next = bi.current_ebb->first_call_clobbers (); | |
555 | bi.current_ebb->set_first_call_clobbers (ecc); | |
556 | } | |
557 | ||
558 | auto abi_id = abi.base_abi ().id (); | |
559 | auto *insn_clobbers = allocate<insn_call_clobbers_note> (abi_id, insn); | |
560 | insn->add_note (insn_clobbers); | |
561 | ||
562 | ecc->insert_max_node (insn_clobbers); | |
563 | } | |
564 | else | |
565 | for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno) | |
566 | if (TEST_HARD_REG_BIT (abi.full_reg_clobbers (), regno)) | |
567 | { | |
568 | def_info *def = m_defs[regno + 1]; | |
569 | if (!def || def->last_def ()->insn () != insn) | |
570 | { | |
571 | def = allocate<clobber_info> (insn, regno); | |
572 | def->m_is_call_clobber = true; | |
573 | append_def (def); | |
574 | m_temp_defs.safe_push (def); | |
abe07a74 | 575 | bi.record_reg_def (def); |
73b75827 RS |
576 | } |
577 | } | |
578 | } | |
579 | ||
580 | // Called while building SSA form using BI. Record that INSN contains | |
581 | // write reference REF. Add associated def_infos to the list of accesses | |
582 | // that we're building in m_temp_defs. Record the register's new live | |
583 | // value in BI. | |
584 | void | |
585 | function_info::record_def (build_info &bi, insn_info *insn, | |
586 | rtx_obj_reference ref) | |
587 | { | |
588 | // Punt if we see multiple definitions of the same resource. | |
589 | // This can happen for several reasons: | |
590 | // | |
591 | // - An instruction might store two values to memory at once, giving two | |
592 | // distinct memory references. | |
593 | // | |
594 | // - An instruction might assign to multiple pieces of a wide pseudo | |
595 | // register. For example, on 32-bit targets, an instruction might | |
596 | // assign to both the upper and lower halves of a 64-bit pseudo register. | |
597 | // | |
598 | // - It's possible for the same register to be clobbered by the | |
599 | // CALL_INSN_FUNCTION_USAGE and to be set by the main instruction | |
600 | // pattern as well. In that case, the clobber conceptually happens | |
601 | // before the set and can essentially be ignored. | |
602 | // | |
603 | // - Similarly, global registers are implicitly set by a call but can | |
604 | // be explicitly set or clobbered as well. In that situation, the sets | |
605 | // are listed first and should win over a clobber. | |
606 | unsigned int regno = ref.regno; | |
607 | machine_mode mode = ref.is_reg () ? ref.mode : BLKmode; | |
608 | def_info *def = safe_dyn_cast<def_info *> (bi.last_access[ref.regno + 1]); | |
609 | if (def && def->insn () == insn) | |
610 | { | |
611 | if (!ref.is_clobber ()) | |
612 | { | |
613 | gcc_checking_assert (!is_a<clobber_info *> (def)); | |
614 | def->record_reference (ref, false); | |
615 | } | |
616 | return; | |
617 | } | |
618 | ||
619 | // Memory is always well-defined, so only use clobber_infos for registers. | |
620 | if (ref.is_reg () && ref.is_clobber ()) | |
621 | def = allocate<clobber_info> (insn, regno); | |
622 | else | |
623 | def = allocate<set_info> (insn, resource_info { mode, regno }); | |
624 | def->record_reference (ref, true); | |
625 | append_def (def); | |
626 | m_temp_defs.safe_push (def); | |
abe07a74 | 627 | bi.record_reg_def (def); |
73b75827 RS |
628 | } |
629 | ||
630 | // Called while building SSA form using BI. Add an insn_info for RTL | |
631 | // to the block that we're current building. | |
632 | void | |
633 | function_info::add_insn_to_block (build_info &bi, rtx_insn *rtl) | |
634 | { | |
635 | insn_info *insn = allocate<insn_info> (bi.current_bb, rtl, UNKNOWN_COST); | |
636 | append_insn (insn); | |
637 | ||
638 | vec_rtx_properties properties; | |
639 | properties.add_insn (rtl, true); | |
640 | insn->set_properties (properties); | |
641 | ||
642 | start_insn_accesses (); | |
643 | ||
644 | // Record the uses. | |
645 | for (rtx_obj_reference ref : properties.refs ()) | |
646 | if (ref.is_read ()) | |
647 | record_use (bi, insn, ref); | |
648 | ||
649 | // Restore the contents of bi.last_access, which we used as a cache | |
650 | // when assembling the uses. | |
651 | for (access_info *access : m_temp_uses) | |
652 | { | |
653 | unsigned int regno = access->regno (); | |
654 | gcc_checking_assert (bi.last_access[regno + 1] == access); | |
655 | bi.last_access[regno + 1] = as_a<use_info *> (access)->def (); | |
656 | } | |
657 | ||
658 | // Record the definitions. | |
659 | for (rtx_obj_reference ref : properties.refs ()) | |
660 | if (ref.is_write ()) | |
661 | record_def (bi, insn, ref); | |
662 | ||
663 | // Logically these happen before the explicit definitions, but if the | |
664 | // explicit definitions and call clobbers reference the same register, | |
665 | // the explicit definition should win. | |
666 | if (auto *call_rtl = dyn_cast<rtx_call_insn *> (rtl)) | |
667 | record_call_clobbers (bi, insn, call_rtl); | |
668 | ||
669 | finish_insn_accesses (insn); | |
670 | } | |
671 | ||
672 | // Check whether INSN sets any registers that are never subsequently used. | |
673 | // If so, add REG_UNUSED notes for them. The caller has already removed | |
674 | // any previous REG_UNUSED notes. | |
675 | void | |
676 | function_info::add_reg_unused_notes (insn_info *insn) | |
677 | { | |
678 | rtx_insn *rtl = insn->rtl (); | |
679 | ||
680 | auto handle_potential_set = [&](rtx pattern) | |
681 | { | |
682 | if (GET_CODE (pattern) != SET) | |
683 | return; | |
684 | ||
685 | rtx dest = SET_DEST (pattern); | |
686 | if (!REG_P (dest)) | |
687 | return; | |
688 | ||
689 | def_array defs = insn->defs (); | |
690 | unsigned int index = find_access_index (defs, REGNO (dest)); | |
691 | for (unsigned int i = 0; i < REG_NREGS (dest); ++i) | |
692 | { | |
693 | def_info *def = defs[index + i]; | |
694 | gcc_checking_assert (def->regno () == REGNO (dest) + i); | |
695 | set_info *set = dyn_cast<set_info *> (def); | |
696 | if (set && set->has_nondebug_uses ()) | |
697 | return; | |
698 | } | |
699 | add_reg_note (rtl, REG_UNUSED, dest); | |
700 | }; | |
701 | ||
702 | rtx pattern = PATTERN (rtl); | |
703 | if (GET_CODE (pattern) == PARALLEL) | |
704 | for (int i = 0; i < XVECLEN (pattern, 0); ++i) | |
705 | handle_potential_set (XVECEXP (pattern, 0, i)); | |
706 | else | |
707 | handle_potential_set (pattern); | |
708 | } | |
709 | ||
710 | // Search TREE for call clobbers at INSN. Return: | |
711 | // | |
712 | // - less than zero if INSN occurs before the root of TREE | |
713 | // - 0 if INSN is the root of TREE | |
714 | // - greater than zero if INSN occurs after the root of TREE | |
715 | int | |
716 | rtl_ssa::lookup_call_clobbers (insn_call_clobbers_tree &tree, insn_info *insn) | |
717 | { | |
718 | auto compare = [&](insn_call_clobbers_note *clobbers) | |
719 | { | |
720 | return insn->compare_with (clobbers->insn ()); | |
721 | }; | |
722 | return tree.lookup (compare); | |
723 | } | |
724 | ||
725 | // Print a description of INSN to PP. | |
726 | void | |
727 | rtl_ssa::pp_insn (pretty_printer *pp, const insn_info *insn) | |
728 | { | |
729 | if (!insn) | |
730 | pp_string (pp, "<null>"); | |
731 | else | |
732 | insn->print_full (pp); | |
733 | } | |
734 | ||
735 | // Print a description of INSN to FILE. | |
736 | void | |
737 | dump (FILE *file, const insn_info *insn) | |
738 | { | |
739 | dump_using (file, pp_insn, insn); | |
740 | } | |
741 | ||
742 | // Debug interface to the dump routine above. | |
743 | void debug (const insn_info *x) { dump (stderr, x); } |