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16f6ece6 BS |
1 | /* Instruction scheduling pass. This file computes dependencies between |
2 | instructions. | |
23a5b65a | 3 | Copyright (C) 1992-2014 Free Software Foundation, Inc. |
16f6ece6 BS |
4 | Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by, |
5 | and currently maintained by, Jim Wilson (wilson@cygnus.com) | |
6 | ||
1322177d | 7 | This file is part of GCC. |
16f6ece6 | 8 | |
1322177d LB |
9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 11 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 12 | version. |
16f6ece6 | 13 | |
1322177d LB |
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16f6ece6 BS |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
17 | for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
16f6ece6 BS |
22 | \f |
23 | #include "config.h" | |
24 | #include "system.h" | |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
718f9c0f | 27 | #include "diagnostic-core.h" |
16f6ece6 | 28 | #include "rtl.h" |
532aafad | 29 | #include "tree.h" /* FIXME: Used by call_may_noreturn_p. */ |
16f6ece6 BS |
30 | #include "tm_p.h" |
31 | #include "hard-reg-set.h" | |
16f6ece6 | 32 | #include "regs.h" |
83685514 AM |
33 | #include "hashtab.h" |
34 | #include "hash-set.h" | |
35 | #include "vec.h" | |
36 | #include "machmode.h" | |
37 | #include "input.h" | |
16f6ece6 BS |
38 | #include "function.h" |
39 | #include "flags.h" | |
40 | #include "insn-config.h" | |
41 | #include "insn-attr.h" | |
42 | #include "except.h" | |
16f6ece6 | 43 | #include "recog.h" |
1a83e602 | 44 | #include "emit-rtl.h" |
60393bbc AM |
45 | #include "dominance.h" |
46 | #include "cfg.h" | |
47 | #include "cfgbuild.h" | |
48 | #include "predict.h" | |
49 | #include "basic-block.h" | |
16f6ece6 | 50 | #include "sched-int.h" |
4a121cc3 | 51 | #include "params.h" |
4b6c5340 | 52 | #include "cselib.h" |
ce18efcb | 53 | #include "ira.h" |
d4ebfa65 | 54 | #include "target.h" |
16f6ece6 | 55 | |
a750daa2 MK |
56 | #ifdef INSN_SCHEDULING |
57 | ||
b198261f MK |
58 | #ifdef ENABLE_CHECKING |
59 | #define CHECK (true) | |
60 | #else | |
61 | #define CHECK (false) | |
62 | #endif | |
63 | ||
e855c69d AB |
64 | /* Holds current parameters for the dependency analyzer. */ |
65 | struct sched_deps_info_def *sched_deps_info; | |
66 | ||
67 | /* The data is specific to the Haifa scheduler. */ | |
9771b263 | 68 | vec<haifa_deps_insn_data_def> |
6e1aa848 | 69 | h_d_i_d = vNULL; |
e855c69d | 70 | |
b198261f MK |
71 | /* Return the major type present in the DS. */ |
72 | enum reg_note | |
73 | ds_to_dk (ds_t ds) | |
74 | { | |
75 | if (ds & DEP_TRUE) | |
76 | return REG_DEP_TRUE; | |
77 | ||
78 | if (ds & DEP_OUTPUT) | |
79 | return REG_DEP_OUTPUT; | |
80 | ||
e2724e63 BS |
81 | if (ds & DEP_CONTROL) |
82 | return REG_DEP_CONTROL; | |
83 | ||
b198261f MK |
84 | gcc_assert (ds & DEP_ANTI); |
85 | ||
86 | return REG_DEP_ANTI; | |
87 | } | |
88 | ||
89 | /* Return equivalent dep_status. */ | |
90 | ds_t | |
91 | dk_to_ds (enum reg_note dk) | |
92 | { | |
93 | switch (dk) | |
94 | { | |
95 | case REG_DEP_TRUE: | |
96 | return DEP_TRUE; | |
97 | ||
98 | case REG_DEP_OUTPUT: | |
99 | return DEP_OUTPUT; | |
100 | ||
e2724e63 BS |
101 | case REG_DEP_CONTROL: |
102 | return DEP_CONTROL; | |
103 | ||
b198261f MK |
104 | default: |
105 | gcc_assert (dk == REG_DEP_ANTI); | |
106 | return DEP_ANTI; | |
107 | } | |
108 | } | |
109 | ||
110 | /* Functions to operate with dependence information container - dep_t. */ | |
111 | ||
112 | /* Init DEP with the arguments. */ | |
e2f6ff94 | 113 | void |
0e0ce50d | 114 | init_dep_1 (dep_t dep, rtx_insn *pro, rtx_insn *con, enum reg_note type, ds_t ds) |
b198261f | 115 | { |
0e0ce50d DM |
116 | DEP_PRO (dep) = pro; |
117 | DEP_CON (dep) = con; | |
e2f6ff94 | 118 | DEP_TYPE (dep) = type; |
b198261f | 119 | DEP_STATUS (dep) = ds; |
a19af9c4 | 120 | DEP_COST (dep) = UNKNOWN_DEP_COST; |
1a83e602 BS |
121 | DEP_NONREG (dep) = 0; |
122 | DEP_MULTIPLE (dep) = 0; | |
123 | DEP_REPLACE (dep) = NULL; | |
b198261f MK |
124 | } |
125 | ||
126 | /* Init DEP with the arguments. | |
127 | While most of the scheduler (including targets) only need the major type | |
9f5ed61a | 128 | of the dependency, it is convenient to hide full dep_status from them. */ |
b198261f | 129 | void |
0e0ce50d | 130 | init_dep (dep_t dep, rtx_insn *pro, rtx_insn *con, enum reg_note kind) |
b198261f MK |
131 | { |
132 | ds_t ds; | |
133 | ||
e2f6ff94 | 134 | if ((current_sched_info->flags & USE_DEPS_LIST)) |
b198261f MK |
135 | ds = dk_to_ds (kind); |
136 | else | |
b953c2b8 | 137 | ds = 0; |
b198261f MK |
138 | |
139 | init_dep_1 (dep, pro, con, kind, ds); | |
140 | } | |
141 | ||
142 | /* Make a copy of FROM in TO. */ | |
143 | static void | |
144 | copy_dep (dep_t to, dep_t from) | |
145 | { | |
146 | memcpy (to, from, sizeof (*to)); | |
147 | } | |
148 | ||
e2f6ff94 | 149 | static void dump_ds (FILE *, ds_t); |
b198261f | 150 | |
e2f6ff94 MK |
151 | /* Define flags for dump_dep (). */ |
152 | ||
153 | /* Dump producer of the dependence. */ | |
154 | #define DUMP_DEP_PRO (2) | |
155 | ||
156 | /* Dump consumer of the dependence. */ | |
157 | #define DUMP_DEP_CON (4) | |
158 | ||
159 | /* Dump type of the dependence. */ | |
160 | #define DUMP_DEP_TYPE (8) | |
161 | ||
162 | /* Dump status of the dependence. */ | |
163 | #define DUMP_DEP_STATUS (16) | |
164 | ||
165 | /* Dump all information about the dependence. */ | |
166 | #define DUMP_DEP_ALL (DUMP_DEP_PRO | DUMP_DEP_CON | DUMP_DEP_TYPE \ | |
167 | |DUMP_DEP_STATUS) | |
168 | ||
169 | /* Dump DEP to DUMP. | |
170 | FLAGS is a bit mask specifying what information about DEP needs | |
171 | to be printed. | |
172 | If FLAGS has the very first bit set, then dump all information about DEP | |
173 | and propagate this bit into the callee dump functions. */ | |
174 | static void | |
175 | dump_dep (FILE *dump, dep_t dep, int flags) | |
b198261f | 176 | { |
e2f6ff94 MK |
177 | if (flags & 1) |
178 | flags |= DUMP_DEP_ALL; | |
179 | ||
180 | fprintf (dump, "<"); | |
181 | ||
182 | if (flags & DUMP_DEP_PRO) | |
183 | fprintf (dump, "%d; ", INSN_UID (DEP_PRO (dep))); | |
184 | ||
185 | if (flags & DUMP_DEP_CON) | |
186 | fprintf (dump, "%d; ", INSN_UID (DEP_CON (dep))); | |
187 | ||
188 | if (flags & DUMP_DEP_TYPE) | |
189 | { | |
190 | char t; | |
191 | enum reg_note type = DEP_TYPE (dep); | |
192 | ||
193 | switch (type) | |
194 | { | |
195 | case REG_DEP_TRUE: | |
196 | t = 't'; | |
197 | break; | |
198 | ||
199 | case REG_DEP_OUTPUT: | |
200 | t = 'o'; | |
201 | break; | |
b198261f | 202 | |
e2724e63 BS |
203 | case REG_DEP_CONTROL: |
204 | t = 'c'; | |
205 | break; | |
206 | ||
e2f6ff94 MK |
207 | case REG_DEP_ANTI: |
208 | t = 'a'; | |
209 | break; | |
210 | ||
211 | default: | |
212 | gcc_unreachable (); | |
213 | break; | |
214 | } | |
215 | ||
216 | fprintf (dump, "%c; ", t); | |
217 | } | |
218 | ||
219 | if (flags & DUMP_DEP_STATUS) | |
220 | { | |
221 | if (current_sched_info->flags & USE_DEPS_LIST) | |
222 | dump_ds (dump, DEP_STATUS (dep)); | |
223 | } | |
224 | ||
225 | fprintf (dump, ">"); | |
226 | } | |
227 | ||
228 | /* Default flags for dump_dep (). */ | |
229 | static int dump_dep_flags = (DUMP_DEP_PRO | DUMP_DEP_CON); | |
230 | ||
231 | /* Dump all fields of DEP to STDERR. */ | |
232 | void | |
233 | sd_debug_dep (dep_t dep) | |
234 | { | |
235 | dump_dep (stderr, dep, 1); | |
236 | fprintf (stderr, "\n"); | |
b198261f MK |
237 | } |
238 | ||
f49b295a AO |
239 | /* Determine whether DEP is a dependency link of a non-debug insn on a |
240 | debug insn. */ | |
241 | ||
242 | static inline bool | |
243 | depl_on_debug_p (dep_link_t dep) | |
244 | { | |
245 | return (DEBUG_INSN_P (DEP_LINK_PRO (dep)) | |
246 | && !DEBUG_INSN_P (DEP_LINK_CON (dep))); | |
247 | } | |
248 | ||
e2f6ff94 MK |
249 | /* Functions to operate with a single link from the dependencies lists - |
250 | dep_link_t. */ | |
251 | ||
b198261f MK |
252 | /* Attach L to appear after link X whose &DEP_LINK_NEXT (X) is given by |
253 | PREV_NEXT_P. */ | |
254 | static void | |
255 | attach_dep_link (dep_link_t l, dep_link_t *prev_nextp) | |
256 | { | |
257 | dep_link_t next = *prev_nextp; | |
258 | ||
259 | gcc_assert (DEP_LINK_PREV_NEXTP (l) == NULL | |
260 | && DEP_LINK_NEXT (l) == NULL); | |
261 | ||
262 | /* Init node being inserted. */ | |
263 | DEP_LINK_PREV_NEXTP (l) = prev_nextp; | |
264 | DEP_LINK_NEXT (l) = next; | |
265 | ||
266 | /* Fix next node. */ | |
267 | if (next != NULL) | |
268 | { | |
269 | gcc_assert (DEP_LINK_PREV_NEXTP (next) == prev_nextp); | |
270 | ||
271 | DEP_LINK_PREV_NEXTP (next) = &DEP_LINK_NEXT (l); | |
272 | } | |
273 | ||
274 | /* Fix prev node. */ | |
275 | *prev_nextp = l; | |
276 | } | |
277 | ||
278 | /* Add dep_link LINK to deps_list L. */ | |
279 | static void | |
280 | add_to_deps_list (dep_link_t link, deps_list_t l) | |
281 | { | |
282 | attach_dep_link (link, &DEPS_LIST_FIRST (l)); | |
e2f6ff94 | 283 | |
f49b295a AO |
284 | /* Don't count debug deps. */ |
285 | if (!depl_on_debug_p (link)) | |
286 | ++DEPS_LIST_N_LINKS (l); | |
b198261f MK |
287 | } |
288 | ||
289 | /* Detach dep_link L from the list. */ | |
290 | static void | |
291 | detach_dep_link (dep_link_t l) | |
292 | { | |
293 | dep_link_t *prev_nextp = DEP_LINK_PREV_NEXTP (l); | |
294 | dep_link_t next = DEP_LINK_NEXT (l); | |
295 | ||
296 | *prev_nextp = next; | |
297 | ||
298 | if (next != NULL) | |
299 | DEP_LINK_PREV_NEXTP (next) = prev_nextp; | |
300 | ||
b198261f MK |
301 | DEP_LINK_PREV_NEXTP (l) = NULL; |
302 | DEP_LINK_NEXT (l) = NULL; | |
303 | } | |
304 | ||
e2f6ff94 MK |
305 | /* Remove link LINK from list LIST. */ |
306 | static void | |
307 | remove_from_deps_list (dep_link_t link, deps_list_t list) | |
b198261f MK |
308 | { |
309 | detach_dep_link (link); | |
b198261f | 310 | |
f49b295a AO |
311 | /* Don't count debug deps. */ |
312 | if (!depl_on_debug_p (link)) | |
313 | --DEPS_LIST_N_LINKS (list); | |
b198261f MK |
314 | } |
315 | ||
e2f6ff94 | 316 | /* Move link LINK from list FROM to list TO. */ |
b198261f | 317 | static void |
e2f6ff94 | 318 | move_dep_link (dep_link_t link, deps_list_t from, deps_list_t to) |
b198261f | 319 | { |
e2f6ff94 MK |
320 | remove_from_deps_list (link, from); |
321 | add_to_deps_list (link, to); | |
b198261f MK |
322 | } |
323 | ||
e2f6ff94 MK |
324 | /* Return true of LINK is not attached to any list. */ |
325 | static bool | |
326 | dep_link_is_detached_p (dep_link_t link) | |
b198261f | 327 | { |
e2f6ff94 | 328 | return DEP_LINK_PREV_NEXTP (link) == NULL; |
b198261f MK |
329 | } |
330 | ||
e2f6ff94 MK |
331 | /* Pool to hold all dependency nodes (dep_node_t). */ |
332 | static alloc_pool dn_pool; | |
b198261f | 333 | |
e2f6ff94 MK |
334 | /* Number of dep_nodes out there. */ |
335 | static int dn_pool_diff = 0; | |
b198261f | 336 | |
e2f6ff94 MK |
337 | /* Create a dep_node. */ |
338 | static dep_node_t | |
339 | create_dep_node (void) | |
340 | { | |
341 | dep_node_t n = (dep_node_t) pool_alloc (dn_pool); | |
342 | dep_link_t back = DEP_NODE_BACK (n); | |
343 | dep_link_t forw = DEP_NODE_FORW (n); | |
b198261f | 344 | |
e2f6ff94 MK |
345 | DEP_LINK_NODE (back) = n; |
346 | DEP_LINK_NEXT (back) = NULL; | |
347 | DEP_LINK_PREV_NEXTP (back) = NULL; | |
b198261f | 348 | |
e2f6ff94 MK |
349 | DEP_LINK_NODE (forw) = n; |
350 | DEP_LINK_NEXT (forw) = NULL; | |
351 | DEP_LINK_PREV_NEXTP (forw) = NULL; | |
b198261f | 352 | |
e2f6ff94 | 353 | ++dn_pool_diff; |
b198261f | 354 | |
e2f6ff94 | 355 | return n; |
b198261f MK |
356 | } |
357 | ||
e2f6ff94 | 358 | /* Delete dep_node N. N must not be connected to any deps_list. */ |
b198261f | 359 | static void |
e2f6ff94 | 360 | delete_dep_node (dep_node_t n) |
b198261f | 361 | { |
e2f6ff94 MK |
362 | gcc_assert (dep_link_is_detached_p (DEP_NODE_BACK (n)) |
363 | && dep_link_is_detached_p (DEP_NODE_FORW (n))); | |
b198261f | 364 | |
334e71e8 JJ |
365 | XDELETE (DEP_REPLACE (DEP_NODE_DEP (n))); |
366 | ||
e2f6ff94 | 367 | --dn_pool_diff; |
b198261f | 368 | |
e2f6ff94 | 369 | pool_free (dn_pool, n); |
b198261f MK |
370 | } |
371 | ||
e2f6ff94 MK |
372 | /* Pool to hold dependencies lists (deps_list_t). */ |
373 | static alloc_pool dl_pool; | |
b198261f | 374 | |
e2f6ff94 MK |
375 | /* Number of deps_lists out there. */ |
376 | static int dl_pool_diff = 0; | |
b198261f | 377 | |
e2f6ff94 | 378 | /* Functions to operate with dependences lists - deps_list_t. */ |
b198261f | 379 | |
e2f6ff94 | 380 | /* Return true if list L is empty. */ |
b198261f | 381 | static bool |
e2f6ff94 | 382 | deps_list_empty_p (deps_list_t l) |
b198261f | 383 | { |
e2f6ff94 | 384 | return DEPS_LIST_N_LINKS (l) == 0; |
b198261f MK |
385 | } |
386 | ||
e2f6ff94 MK |
387 | /* Create a new deps_list. */ |
388 | static deps_list_t | |
389 | create_deps_list (void) | |
b198261f | 390 | { |
e2f6ff94 | 391 | deps_list_t l = (deps_list_t) pool_alloc (dl_pool); |
b198261f | 392 | |
e2f6ff94 MK |
393 | DEPS_LIST_FIRST (l) = NULL; |
394 | DEPS_LIST_N_LINKS (l) = 0; | |
b198261f | 395 | |
e2f6ff94 MK |
396 | ++dl_pool_diff; |
397 | return l; | |
b198261f MK |
398 | } |
399 | ||
e2f6ff94 MK |
400 | /* Free deps_list L. */ |
401 | static void | |
402 | free_deps_list (deps_list_t l) | |
b198261f | 403 | { |
e2f6ff94 | 404 | gcc_assert (deps_list_empty_p (l)); |
b198261f | 405 | |
e2f6ff94 | 406 | --dl_pool_diff; |
b198261f | 407 | |
e2f6ff94 | 408 | pool_free (dl_pool, l); |
b198261f MK |
409 | } |
410 | ||
e2f6ff94 | 411 | /* Return true if there is no dep_nodes and deps_lists out there. |
15dc95cb | 412 | After the region is scheduled all the dependency nodes and lists |
e2f6ff94 MK |
413 | should [generally] be returned to pool. */ |
414 | bool | |
415 | deps_pools_are_empty_p (void) | |
b198261f | 416 | { |
e2f6ff94 | 417 | return dn_pool_diff == 0 && dl_pool_diff == 0; |
b198261f MK |
418 | } |
419 | ||
e2f6ff94 MK |
420 | /* Remove all elements from L. */ |
421 | static void | |
422 | clear_deps_list (deps_list_t l) | |
b198261f | 423 | { |
e2f6ff94 MK |
424 | do |
425 | { | |
426 | dep_link_t link = DEPS_LIST_FIRST (l); | |
b198261f | 427 | |
e2f6ff94 MK |
428 | if (link == NULL) |
429 | break; | |
b198261f | 430 | |
e2f6ff94 | 431 | remove_from_deps_list (link, l); |
b198261f | 432 | } |
e2f6ff94 | 433 | while (1); |
b198261f | 434 | } |
16f6ece6 | 435 | |
b953c2b8 BS |
436 | /* Decide whether a dependency should be treated as a hard or a speculative |
437 | dependency. */ | |
438 | static bool | |
439 | dep_spec_p (dep_t dep) | |
440 | { | |
441 | if (current_sched_info->flags & DO_SPECULATION) | |
e2724e63 BS |
442 | { |
443 | if (DEP_STATUS (dep) & SPECULATIVE) | |
444 | return true; | |
445 | } | |
446 | if (current_sched_info->flags & DO_PREDICATION) | |
447 | { | |
448 | if (DEP_TYPE (dep) == REG_DEP_CONTROL) | |
449 | return true; | |
450 | } | |
1a83e602 BS |
451 | if (DEP_REPLACE (dep) != NULL) |
452 | return true; | |
b953c2b8 BS |
453 | return false; |
454 | } | |
455 | ||
16f6ece6 BS |
456 | static regset reg_pending_sets; |
457 | static regset reg_pending_clobbers; | |
37a0f8a5 | 458 | static regset reg_pending_uses; |
e2724e63 | 459 | static regset reg_pending_control_uses; |
d1c9693e | 460 | static enum reg_pending_barrier_mode reg_pending_barrier; |
16f6ece6 | 461 | |
ce18efcb VM |
462 | /* Hard registers implicitly clobbered or used (or may be implicitly |
463 | clobbered or used) by the currently analyzed insn. For example, | |
464 | insn in its constraint has one register class. Even if there is | |
465 | currently no hard register in the insn, the particular hard | |
466 | register will be in the insn after reload pass because the | |
467 | constraint requires it. */ | |
468 | static HARD_REG_SET implicit_reg_pending_clobbers; | |
469 | static HARD_REG_SET implicit_reg_pending_uses; | |
470 | ||
16f6ece6 BS |
471 | /* To speed up the test for duplicate dependency links we keep a |
472 | record of dependencies created by add_dependence when the average | |
473 | number of instructions in a basic block is very large. | |
474 | ||
475 | Studies have shown that there is typically around 5 instructions between | |
476 | branches for typical C code. So we can make a guess that the average | |
477 | basic block is approximately 5 instructions long; we will choose 100X | |
478 | the average size as a very large basic block. | |
479 | ||
480 | Each insn has associated bitmaps for its dependencies. Each bitmap | |
481 | has enough entries to represent a dependency on any other insn in | |
482 | the insn chain. All bitmap for true dependencies cache is | |
2d76cb1a | 483 | allocated then the rest two ones are also allocated. */ |
e855c69d AB |
484 | static bitmap_head *true_dependency_cache = NULL; |
485 | static bitmap_head *output_dependency_cache = NULL; | |
486 | static bitmap_head *anti_dependency_cache = NULL; | |
e2724e63 | 487 | static bitmap_head *control_dependency_cache = NULL; |
e855c69d | 488 | static bitmap_head *spec_dependency_cache = NULL; |
392c64a0 | 489 | static int cache_size; |
16f6ece6 | 490 | |
1a83e602 BS |
491 | /* True if we should mark added dependencies as a non-register deps. */ |
492 | static bool mark_as_hard; | |
493 | ||
9678086d | 494 | static int deps_may_trap_p (const_rtx); |
ce1ce33a | 495 | static void add_dependence_1 (rtx_insn *, rtx_insn *, enum reg_note); |
3dc99c19 DM |
496 | static void add_dependence_list (rtx_insn *, rtx_insn_list *, int, |
497 | enum reg_note, bool); | |
ce1ce33a | 498 | static void add_dependence_list_and_free (struct deps_desc *, rtx_insn *, |
3dc99c19 DM |
499 | rtx_insn_list **, int, enum reg_note, |
500 | bool); | |
4c2b2906 | 501 | static void delete_all_dependences (rtx); |
ce1ce33a | 502 | static void chain_to_prev_insn (rtx_insn *); |
16f6ece6 | 503 | |
ce1ce33a DM |
504 | static void flush_pending_lists (struct deps_desc *, rtx_insn *, int, int); |
505 | static void sched_analyze_1 (struct deps_desc *, rtx, rtx_insn *); | |
506 | static void sched_analyze_2 (struct deps_desc *, rtx, rtx_insn *); | |
507 | static void sched_analyze_insn (struct deps_desc *, rtx, rtx_insn *); | |
0a1bb917 | 508 | |
c838c402 | 509 | static bool sched_has_condition_p (const rtx_insn *); |
e855c69d | 510 | static int conditions_mutex_p (const_rtx, const_rtx, bool, bool); |
ddbd5439 | 511 | |
e2f6ff94 MK |
512 | static enum DEPS_ADJUST_RESULT maybe_add_or_update_dep_1 (dep_t, bool, |
513 | rtx, rtx); | |
514 | static enum DEPS_ADJUST_RESULT add_or_update_dep_1 (dep_t, bool, rtx, rtx); | |
ddbd5439 | 515 | |
ddbd5439 | 516 | #ifdef ENABLE_CHECKING |
e2f6ff94 | 517 | static void check_dep (dep_t, bool); |
ddbd5439 | 518 | #endif |
16f6ece6 | 519 | \f |
713f41f9 BS |
520 | /* Return nonzero if a load of the memory reference MEM can cause a trap. */ |
521 | ||
522 | static int | |
9678086d | 523 | deps_may_trap_p (const_rtx mem) |
713f41f9 | 524 | { |
9678086d | 525 | const_rtx addr = XEXP (mem, 0); |
713f41f9 | 526 | |
bb1acb3e RH |
527 | if (REG_P (addr) && REGNO (addr) >= FIRST_PSEUDO_REGISTER) |
528 | { | |
9678086d | 529 | const_rtx t = get_reg_known_value (REGNO (addr)); |
bb1acb3e RH |
530 | if (t) |
531 | addr = t; | |
532 | } | |
713f41f9 BS |
533 | return rtx_addr_can_trap_p (addr); |
534 | } | |
535 | \f | |
0a1bb917 | 536 | |
e855c69d AB |
537 | /* Find the condition under which INSN is executed. If REV is not NULL, |
538 | it is set to TRUE when the returned comparison should be reversed | |
f0898307 | 539 | to get the actual condition. */ |
0a1bb917 | 540 | static rtx |
c838c402 | 541 | sched_get_condition_with_rev_uncached (const rtx_insn *insn, bool *rev) |
0a1bb917 BS |
542 | { |
543 | rtx pat = PATTERN (insn); | |
adf968c7 | 544 | rtx src; |
0a1bb917 | 545 | |
e855c69d AB |
546 | if (rev) |
547 | *rev = false; | |
548 | ||
0a1bb917 | 549 | if (GET_CODE (pat) == COND_EXEC) |
f0898307 | 550 | return COND_EXEC_TEST (pat); |
6903ecd4 RE |
551 | |
552 | if (!any_condjump_p (insn) || !onlyjump_p (insn)) | |
0a1bb917 | 553 | return 0; |
6903ecd4 | 554 | |
adf968c7 | 555 | src = SET_SRC (pc_set (insn)); |
2bd1e239 | 556 | |
adf968c7 | 557 | if (XEXP (src, 2) == pc_rtx) |
f0898307 | 558 | return XEXP (src, 0); |
adf968c7 | 559 | else if (XEXP (src, 1) == pc_rtx) |
6903ecd4 | 560 | { |
adf968c7 | 561 | rtx cond = XEXP (src, 0); |
6903ecd4 RE |
562 | enum rtx_code revcode = reversed_comparison_code (cond, insn); |
563 | ||
564 | if (revcode == UNKNOWN) | |
565 | return 0; | |
e855c69d AB |
566 | |
567 | if (rev) | |
568 | *rev = true; | |
569 | return cond; | |
6903ecd4 | 570 | } |
a8b3643c RE |
571 | |
572 | return 0; | |
0a1bb917 BS |
573 | } |
574 | ||
e2724e63 BS |
575 | /* Return the condition under which INSN does not execute (i.e. the |
576 | not-taken condition for a conditional branch), or NULL if we cannot | |
577 | find such a condition. The caller should make a copy of the condition | |
578 | before using it. */ | |
579 | rtx | |
c838c402 | 580 | sched_get_reverse_condition_uncached (const rtx_insn *insn) |
e2724e63 BS |
581 | { |
582 | bool rev; | |
583 | rtx cond = sched_get_condition_with_rev_uncached (insn, &rev); | |
584 | if (cond == NULL_RTX) | |
585 | return cond; | |
586 | if (!rev) | |
587 | { | |
588 | enum rtx_code revcode = reversed_comparison_code (cond, insn); | |
589 | cond = gen_rtx_fmt_ee (revcode, GET_MODE (cond), | |
590 | XEXP (cond, 0), | |
591 | XEXP (cond, 1)); | |
592 | } | |
593 | return cond; | |
594 | } | |
595 | ||
f0898307 SG |
596 | /* Caching variant of sched_get_condition_with_rev_uncached. |
597 | We only do actual work the first time we come here for an insn; the | |
598 | results are cached in INSN_CACHED_COND and INSN_REVERSE_COND. */ | |
599 | static rtx | |
c838c402 | 600 | sched_get_condition_with_rev (const rtx_insn *insn, bool *rev) |
f0898307 SG |
601 | { |
602 | bool tmp; | |
603 | ||
604 | if (INSN_LUID (insn) == 0) | |
605 | return sched_get_condition_with_rev_uncached (insn, rev); | |
606 | ||
607 | if (INSN_CACHED_COND (insn) == const_true_rtx) | |
608 | return NULL_RTX; | |
609 | ||
610 | if (INSN_CACHED_COND (insn) != NULL_RTX) | |
611 | { | |
612 | if (rev) | |
613 | *rev = INSN_REVERSE_COND (insn); | |
614 | return INSN_CACHED_COND (insn); | |
615 | } | |
616 | ||
617 | INSN_CACHED_COND (insn) = sched_get_condition_with_rev_uncached (insn, &tmp); | |
618 | INSN_REVERSE_COND (insn) = tmp; | |
619 | ||
620 | if (INSN_CACHED_COND (insn) == NULL_RTX) | |
621 | { | |
622 | INSN_CACHED_COND (insn) = const_true_rtx; | |
623 | return NULL_RTX; | |
624 | } | |
625 | ||
626 | if (rev) | |
627 | *rev = INSN_REVERSE_COND (insn); | |
628 | return INSN_CACHED_COND (insn); | |
629 | } | |
630 | ||
e855c69d AB |
631 | /* True when we can find a condition under which INSN is executed. */ |
632 | static bool | |
c838c402 | 633 | sched_has_condition_p (const rtx_insn *insn) |
e855c69d AB |
634 | { |
635 | return !! sched_get_condition_with_rev (insn, NULL); | |
636 | } | |
637 | ||
2bd1e239 | 638 | \f |
0a1bb917 | 639 | |
e855c69d | 640 | /* Return nonzero if conditions COND1 and COND2 can never be both true. */ |
0a1bb917 | 641 | static int |
e855c69d | 642 | conditions_mutex_p (const_rtx cond1, const_rtx cond2, bool rev1, bool rev2) |
0a1bb917 | 643 | { |
ec8e098d PB |
644 | if (COMPARISON_P (cond1) |
645 | && COMPARISON_P (cond2) | |
e855c69d AB |
646 | && GET_CODE (cond1) == |
647 | (rev1==rev2 | |
648 | ? reversed_comparison_code (cond2, NULL) | |
649 | : GET_CODE (cond2)) | |
aef0e7a8 | 650 | && rtx_equal_p (XEXP (cond1, 0), XEXP (cond2, 0)) |
0a1bb917 BS |
651 | && XEXP (cond1, 1) == XEXP (cond2, 1)) |
652 | return 1; | |
653 | return 0; | |
654 | } | |
2bd1e239 SB |
655 | |
656 | /* Return true if insn1 and insn2 can never depend on one another because | |
657 | the conditions under which they are executed are mutually exclusive. */ | |
658 | bool | |
c838c402 | 659 | sched_insns_conditions_mutex_p (const rtx_insn *insn1, const rtx_insn *insn2) |
2bd1e239 SB |
660 | { |
661 | rtx cond1, cond2; | |
99e395c7 | 662 | bool rev1 = false, rev2 = false; |
2bd1e239 | 663 | |
6fb5fa3c | 664 | /* df doesn't handle conditional lifetimes entirely correctly; |
2bd1e239 SB |
665 | calls mess up the conditional lifetimes. */ |
666 | if (!CALL_P (insn1) && !CALL_P (insn2)) | |
667 | { | |
e855c69d AB |
668 | cond1 = sched_get_condition_with_rev (insn1, &rev1); |
669 | cond2 = sched_get_condition_with_rev (insn2, &rev2); | |
2bd1e239 | 670 | if (cond1 && cond2 |
e855c69d | 671 | && conditions_mutex_p (cond1, cond2, rev1, rev2) |
2bd1e239 SB |
672 | /* Make sure first instruction doesn't affect condition of second |
673 | instruction if switched. */ | |
674 | && !modified_in_p (cond1, insn2) | |
675 | /* Make sure second instruction doesn't affect condition of first | |
676 | instruction if switched. */ | |
677 | && !modified_in_p (cond2, insn1)) | |
678 | return true; | |
679 | } | |
680 | return false; | |
681 | } | |
0a1bb917 | 682 | \f |
ddbd5439 | 683 | |
c275297b MK |
684 | /* Return true if INSN can potentially be speculated with type DS. */ |
685 | bool | |
c838c402 | 686 | sched_insn_is_legitimate_for_speculation_p (const rtx_insn *insn, ds_t ds) |
c275297b MK |
687 | { |
688 | if (HAS_INTERNAL_DEP (insn)) | |
689 | return false; | |
690 | ||
691 | if (!NONJUMP_INSN_P (insn)) | |
692 | return false; | |
693 | ||
694 | if (SCHED_GROUP_P (insn)) | |
695 | return false; | |
696 | ||
c838c402 | 697 | if (IS_SPECULATION_CHECK_P (CONST_CAST_RTX_INSN (insn))) |
c275297b MK |
698 | return false; |
699 | ||
700 | if (side_effects_p (PATTERN (insn))) | |
701 | return false; | |
702 | ||
703 | if (ds & BE_IN_SPEC) | |
704 | /* The following instructions, which depend on a speculatively scheduled | |
705 | instruction, cannot be speculatively scheduled along. */ | |
706 | { | |
a61c3633 EB |
707 | if (may_trap_or_fault_p (PATTERN (insn))) |
708 | /* If instruction might fault, it cannot be speculatively scheduled. | |
c275297b MK |
709 | For control speculation it's obvious why and for data speculation |
710 | it's because the insn might get wrong input if speculation | |
711 | wasn't successful. */ | |
712 | return false; | |
713 | ||
714 | if ((ds & BE_IN_DATA) | |
e855c69d | 715 | && sched_has_condition_p (insn)) |
c275297b MK |
716 | /* If this is a predicated instruction, then it cannot be |
717 | speculatively scheduled. See PR35659. */ | |
718 | return false; | |
719 | } | |
720 | ||
721 | return true; | |
722 | } | |
723 | ||
e2f6ff94 MK |
724 | /* Initialize LIST_PTR to point to one of the lists present in TYPES_PTR, |
725 | initialize RESOLVED_P_PTR with true if that list consists of resolved deps, | |
726 | and remove the type of returned [through LIST_PTR] list from TYPES_PTR. | |
727 | This function is used to switch sd_iterator to the next list. | |
728 | !!! For internal use only. Might consider moving it to sched-int.h. */ | |
729 | void | |
9678086d | 730 | sd_next_list (const_rtx insn, sd_list_types_def *types_ptr, |
e2f6ff94 MK |
731 | deps_list_t *list_ptr, bool *resolved_p_ptr) |
732 | { | |
733 | sd_list_types_def types = *types_ptr; | |
734 | ||
735 | if (types & SD_LIST_HARD_BACK) | |
736 | { | |
737 | *list_ptr = INSN_HARD_BACK_DEPS (insn); | |
738 | *resolved_p_ptr = false; | |
739 | *types_ptr = types & ~SD_LIST_HARD_BACK; | |
740 | } | |
741 | else if (types & SD_LIST_SPEC_BACK) | |
742 | { | |
743 | *list_ptr = INSN_SPEC_BACK_DEPS (insn); | |
744 | *resolved_p_ptr = false; | |
745 | *types_ptr = types & ~SD_LIST_SPEC_BACK; | |
746 | } | |
747 | else if (types & SD_LIST_FORW) | |
748 | { | |
749 | *list_ptr = INSN_FORW_DEPS (insn); | |
750 | *resolved_p_ptr = false; | |
751 | *types_ptr = types & ~SD_LIST_FORW; | |
752 | } | |
753 | else if (types & SD_LIST_RES_BACK) | |
754 | { | |
755 | *list_ptr = INSN_RESOLVED_BACK_DEPS (insn); | |
756 | *resolved_p_ptr = true; | |
757 | *types_ptr = types & ~SD_LIST_RES_BACK; | |
758 | } | |
759 | else if (types & SD_LIST_RES_FORW) | |
760 | { | |
761 | *list_ptr = INSN_RESOLVED_FORW_DEPS (insn); | |
762 | *resolved_p_ptr = true; | |
763 | *types_ptr = types & ~SD_LIST_RES_FORW; | |
764 | } | |
765 | else | |
766 | { | |
767 | *list_ptr = NULL; | |
768 | *resolved_p_ptr = false; | |
769 | *types_ptr = SD_LIST_NONE; | |
770 | } | |
771 | } | |
772 | ||
773 | /* Return the summary size of INSN's lists defined by LIST_TYPES. */ | |
774 | int | |
9678086d | 775 | sd_lists_size (const_rtx insn, sd_list_types_def list_types) |
e2f6ff94 MK |
776 | { |
777 | int size = 0; | |
778 | ||
779 | while (list_types != SD_LIST_NONE) | |
780 | { | |
781 | deps_list_t list; | |
782 | bool resolved_p; | |
783 | ||
784 | sd_next_list (insn, &list_types, &list, &resolved_p); | |
b5b8b0ac AO |
785 | if (list) |
786 | size += DEPS_LIST_N_LINKS (list); | |
e2f6ff94 MK |
787 | } |
788 | ||
789 | return size; | |
790 | } | |
791 | ||
792 | /* Return true if INSN's lists defined by LIST_TYPES are all empty. */ | |
f49b295a | 793 | |
e2f6ff94 | 794 | bool |
9678086d | 795 | sd_lists_empty_p (const_rtx insn, sd_list_types_def list_types) |
e2f6ff94 | 796 | { |
f49b295a AO |
797 | while (list_types != SD_LIST_NONE) |
798 | { | |
799 | deps_list_t list; | |
800 | bool resolved_p; | |
801 | ||
802 | sd_next_list (insn, &list_types, &list, &resolved_p); | |
803 | if (!deps_list_empty_p (list)) | |
804 | return false; | |
805 | } | |
806 | ||
807 | return true; | |
e2f6ff94 MK |
808 | } |
809 | ||
810 | /* Initialize data for INSN. */ | |
811 | void | |
812 | sd_init_insn (rtx insn) | |
813 | { | |
814 | INSN_HARD_BACK_DEPS (insn) = create_deps_list (); | |
815 | INSN_SPEC_BACK_DEPS (insn) = create_deps_list (); | |
816 | INSN_RESOLVED_BACK_DEPS (insn) = create_deps_list (); | |
817 | INSN_FORW_DEPS (insn) = create_deps_list (); | |
818 | INSN_RESOLVED_FORW_DEPS (insn) = create_deps_list (); | |
819 | ||
820 | /* ??? It would be nice to allocate dependency caches here. */ | |
821 | } | |
822 | ||
823 | /* Free data for INSN. */ | |
824 | void | |
825 | sd_finish_insn (rtx insn) | |
826 | { | |
827 | /* ??? It would be nice to deallocate dependency caches here. */ | |
828 | ||
829 | free_deps_list (INSN_HARD_BACK_DEPS (insn)); | |
830 | INSN_HARD_BACK_DEPS (insn) = NULL; | |
831 | ||
832 | free_deps_list (INSN_SPEC_BACK_DEPS (insn)); | |
833 | INSN_SPEC_BACK_DEPS (insn) = NULL; | |
834 | ||
835 | free_deps_list (INSN_RESOLVED_BACK_DEPS (insn)); | |
836 | INSN_RESOLVED_BACK_DEPS (insn) = NULL; | |
837 | ||
838 | free_deps_list (INSN_FORW_DEPS (insn)); | |
839 | INSN_FORW_DEPS (insn) = NULL; | |
840 | ||
841 | free_deps_list (INSN_RESOLVED_FORW_DEPS (insn)); | |
842 | INSN_RESOLVED_FORW_DEPS (insn) = NULL; | |
843 | } | |
844 | ||
845 | /* Find a dependency between producer PRO and consumer CON. | |
846 | Search through resolved dependency lists if RESOLVED_P is true. | |
847 | If no such dependency is found return NULL, | |
15dc95cb | 848 | otherwise return the dependency and initialize SD_IT_PTR [if it is nonnull] |
e2f6ff94 MK |
849 | with an iterator pointing to it. */ |
850 | static dep_t | |
851 | sd_find_dep_between_no_cache (rtx pro, rtx con, bool resolved_p, | |
852 | sd_iterator_def *sd_it_ptr) | |
853 | { | |
854 | sd_list_types_def pro_list_type; | |
855 | sd_list_types_def con_list_type; | |
856 | sd_iterator_def sd_it; | |
857 | dep_t dep; | |
858 | bool found_p = false; | |
859 | ||
860 | if (resolved_p) | |
861 | { | |
862 | pro_list_type = SD_LIST_RES_FORW; | |
863 | con_list_type = SD_LIST_RES_BACK; | |
864 | } | |
865 | else | |
866 | { | |
867 | pro_list_type = SD_LIST_FORW; | |
868 | con_list_type = SD_LIST_BACK; | |
869 | } | |
870 | ||
871 | /* Walk through either back list of INSN or forw list of ELEM | |
872 | depending on which one is shorter. */ | |
873 | if (sd_lists_size (con, con_list_type) < sd_lists_size (pro, pro_list_type)) | |
874 | { | |
875 | /* Find the dep_link with producer PRO in consumer's back_deps. */ | |
876 | FOR_EACH_DEP (con, con_list_type, sd_it, dep) | |
877 | if (DEP_PRO (dep) == pro) | |
878 | { | |
879 | found_p = true; | |
880 | break; | |
881 | } | |
882 | } | |
883 | else | |
884 | { | |
885 | /* Find the dep_link with consumer CON in producer's forw_deps. */ | |
886 | FOR_EACH_DEP (pro, pro_list_type, sd_it, dep) | |
887 | if (DEP_CON (dep) == con) | |
888 | { | |
889 | found_p = true; | |
890 | break; | |
891 | } | |
892 | } | |
893 | ||
894 | if (found_p) | |
895 | { | |
896 | if (sd_it_ptr != NULL) | |
897 | *sd_it_ptr = sd_it; | |
898 | ||
899 | return dep; | |
900 | } | |
901 | ||
902 | return NULL; | |
903 | } | |
904 | ||
905 | /* Find a dependency between producer PRO and consumer CON. | |
906 | Use dependency [if available] to check if dependency is present at all. | |
907 | Search through resolved dependency lists if RESOLVED_P is true. | |
908 | If the dependency or NULL if none found. */ | |
909 | dep_t | |
910 | sd_find_dep_between (rtx pro, rtx con, bool resolved_p) | |
911 | { | |
912 | if (true_dependency_cache != NULL) | |
913 | /* Avoiding the list walk below can cut compile times dramatically | |
914 | for some code. */ | |
915 | { | |
916 | int elem_luid = INSN_LUID (pro); | |
917 | int insn_luid = INSN_LUID (con); | |
918 | ||
e2f6ff94 MK |
919 | if (!bitmap_bit_p (&true_dependency_cache[insn_luid], elem_luid) |
920 | && !bitmap_bit_p (&output_dependency_cache[insn_luid], elem_luid) | |
e2724e63 BS |
921 | && !bitmap_bit_p (&anti_dependency_cache[insn_luid], elem_luid) |
922 | && !bitmap_bit_p (&control_dependency_cache[insn_luid], elem_luid)) | |
e2f6ff94 MK |
923 | return NULL; |
924 | } | |
925 | ||
926 | return sd_find_dep_between_no_cache (pro, con, resolved_p, NULL); | |
927 | } | |
928 | ||
929 | /* Add or update a dependence described by DEP. | |
930 | MEM1 and MEM2, if non-null, correspond to memory locations in case of | |
931 | data speculation. | |
932 | ||
933 | The function returns a value indicating if an old entry has been changed | |
934 | or a new entry has been added to insn's backward deps. | |
935 | ||
936 | This function merely checks if producer and consumer is the same insn | |
937 | and doesn't create a dep in this case. Actual manipulation of | |
938 | dependence data structures is performed in add_or_update_dep_1. */ | |
ddbd5439 | 939 | static enum DEPS_ADJUST_RESULT |
e2f6ff94 | 940 | maybe_add_or_update_dep_1 (dep_t dep, bool resolved_p, rtx mem1, rtx mem2) |
16f6ece6 | 941 | { |
974c43e9 DM |
942 | rtx_insn *elem = DEP_PRO (dep); |
943 | rtx_insn *insn = DEP_CON (dep); | |
e2f6ff94 | 944 | |
ddbd5439 | 945 | gcc_assert (INSN_P (insn) && INSN_P (elem)); |
16f6ece6 BS |
946 | |
947 | /* Don't depend an insn on itself. */ | |
948 | if (insn == elem) | |
ddbd5439 | 949 | { |
e855c69d | 950 | if (sched_deps_info->generate_spec_deps) |
ddbd5439 MK |
951 | /* INSN has an internal dependence, which we can't overcome. */ |
952 | HAS_INTERNAL_DEP (insn) = 1; | |
e2f6ff94 MK |
953 | |
954 | return DEP_NODEP; | |
ddbd5439 | 955 | } |
16f6ece6 | 956 | |
e2f6ff94 | 957 | return add_or_update_dep_1 (dep, resolved_p, mem1, mem2); |
ddbd5439 | 958 | } |
16f6ece6 | 959 | |
e2f6ff94 MK |
960 | /* Ask dependency caches what needs to be done for dependence DEP. |
961 | Return DEP_CREATED if new dependence should be created and there is no | |
962 | need to try to find one searching the dependencies lists. | |
963 | Return DEP_PRESENT if there already is a dependence described by DEP and | |
964 | hence nothing is to be done. | |
965 | Return DEP_CHANGED if there already is a dependence, but it should be | |
966 | updated to incorporate additional information from DEP. */ | |
ddbd5439 | 967 | static enum DEPS_ADJUST_RESULT |
e2f6ff94 | 968 | ask_dependency_caches (dep_t dep) |
ddbd5439 | 969 | { |
e2f6ff94 MK |
970 | int elem_luid = INSN_LUID (DEP_PRO (dep)); |
971 | int insn_luid = INSN_LUID (DEP_CON (dep)); | |
ddbd5439 | 972 | |
e2f6ff94 MK |
973 | gcc_assert (true_dependency_cache != NULL |
974 | && output_dependency_cache != NULL | |
e2724e63 BS |
975 | && anti_dependency_cache != NULL |
976 | && control_dependency_cache != NULL); | |
ddbd5439 | 977 | |
e2f6ff94 | 978 | if (!(current_sched_info->flags & USE_DEPS_LIST)) |
b8698a0f | 979 | { |
e2f6ff94 MK |
980 | enum reg_note present_dep_type; |
981 | ||
982 | if (bitmap_bit_p (&true_dependency_cache[insn_luid], elem_luid)) | |
983 | present_dep_type = REG_DEP_TRUE; | |
984 | else if (bitmap_bit_p (&output_dependency_cache[insn_luid], elem_luid)) | |
985 | present_dep_type = REG_DEP_OUTPUT; | |
986 | else if (bitmap_bit_p (&anti_dependency_cache[insn_luid], elem_luid)) | |
987 | present_dep_type = REG_DEP_ANTI; | |
e2724e63 BS |
988 | else if (bitmap_bit_p (&control_dependency_cache[insn_luid], elem_luid)) |
989 | present_dep_type = REG_DEP_CONTROL; | |
e2f6ff94 MK |
990 | else |
991 | /* There is no existing dep so it should be created. */ | |
992 | return DEP_CREATED; | |
993 | ||
994 | if ((int) DEP_TYPE (dep) >= (int) present_dep_type) | |
995 | /* DEP does not add anything to the existing dependence. */ | |
996 | return DEP_PRESENT; | |
997 | } | |
998 | else | |
b8698a0f | 999 | { |
e2f6ff94 | 1000 | ds_t present_dep_types = 0; |
b8698a0f | 1001 | |
e2f6ff94 MK |
1002 | if (bitmap_bit_p (&true_dependency_cache[insn_luid], elem_luid)) |
1003 | present_dep_types |= DEP_TRUE; | |
1004 | if (bitmap_bit_p (&output_dependency_cache[insn_luid], elem_luid)) | |
1005 | present_dep_types |= DEP_OUTPUT; | |
1006 | if (bitmap_bit_p (&anti_dependency_cache[insn_luid], elem_luid)) | |
1007 | present_dep_types |= DEP_ANTI; | |
e2724e63 BS |
1008 | if (bitmap_bit_p (&control_dependency_cache[insn_luid], elem_luid)) |
1009 | present_dep_types |= DEP_CONTROL; | |
e2f6ff94 MK |
1010 | |
1011 | if (present_dep_types == 0) | |
1012 | /* There is no existing dep so it should be created. */ | |
1013 | return DEP_CREATED; | |
1014 | ||
1015 | if (!(current_sched_info->flags & DO_SPECULATION) | |
1016 | || !bitmap_bit_p (&spec_dependency_cache[insn_luid], elem_luid)) | |
1017 | { | |
1018 | if ((present_dep_types | (DEP_STATUS (dep) & DEP_TYPES)) | |
1019 | == present_dep_types) | |
1020 | /* DEP does not add anything to the existing dependence. */ | |
1021 | return DEP_PRESENT; | |
1022 | } | |
1023 | else | |
1024 | { | |
1025 | /* Only true dependencies can be data speculative and | |
1026 | only anti dependencies can be control speculative. */ | |
1027 | gcc_assert ((present_dep_types & (DEP_TRUE | DEP_ANTI)) | |
1028 | == present_dep_types); | |
1029 | ||
1030 | /* if (DEP is SPECULATIVE) then | |
1031 | ..we should update DEP_STATUS | |
1032 | else | |
1033 | ..we should reset existing dep to non-speculative. */ | |
1034 | } | |
1035 | } | |
1036 | ||
1037 | return DEP_CHANGED; | |
1038 | } | |
1039 | ||
1040 | /* Set dependency caches according to DEP. */ | |
1041 | static void | |
1042 | set_dependency_caches (dep_t dep) | |
1043 | { | |
1044 | int elem_luid = INSN_LUID (DEP_PRO (dep)); | |
1045 | int insn_luid = INSN_LUID (DEP_CON (dep)); | |
1046 | ||
1047 | if (!(current_sched_info->flags & USE_DEPS_LIST)) | |
1048 | { | |
1049 | switch (DEP_TYPE (dep)) | |
1050 | { | |
1051 | case REG_DEP_TRUE: | |
1052 | bitmap_set_bit (&true_dependency_cache[insn_luid], elem_luid); | |
1053 | break; | |
1054 | ||
1055 | case REG_DEP_OUTPUT: | |
1056 | bitmap_set_bit (&output_dependency_cache[insn_luid], elem_luid); | |
1057 | break; | |
1058 | ||
1059 | case REG_DEP_ANTI: | |
1060 | bitmap_set_bit (&anti_dependency_cache[insn_luid], elem_luid); | |
1061 | break; | |
1062 | ||
e2724e63 BS |
1063 | case REG_DEP_CONTROL: |
1064 | bitmap_set_bit (&control_dependency_cache[insn_luid], elem_luid); | |
1065 | break; | |
1066 | ||
e2f6ff94 MK |
1067 | default: |
1068 | gcc_unreachable (); | |
1069 | } | |
1070 | } | |
1071 | else | |
1072 | { | |
1073 | ds_t ds = DEP_STATUS (dep); | |
1074 | ||
1075 | if (ds & DEP_TRUE) | |
1076 | bitmap_set_bit (&true_dependency_cache[insn_luid], elem_luid); | |
1077 | if (ds & DEP_OUTPUT) | |
1078 | bitmap_set_bit (&output_dependency_cache[insn_luid], elem_luid); | |
1079 | if (ds & DEP_ANTI) | |
1080 | bitmap_set_bit (&anti_dependency_cache[insn_luid], elem_luid); | |
e2724e63 BS |
1081 | if (ds & DEP_CONTROL) |
1082 | bitmap_set_bit (&control_dependency_cache[insn_luid], elem_luid); | |
e2f6ff94 MK |
1083 | |
1084 | if (ds & SPECULATIVE) | |
1085 | { | |
1086 | gcc_assert (current_sched_info->flags & DO_SPECULATION); | |
1087 | bitmap_set_bit (&spec_dependency_cache[insn_luid], elem_luid); | |
1088 | } | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | /* Type of dependence DEP have changed from OLD_TYPE. Update dependency | |
1093 | caches accordingly. */ | |
1094 | static void | |
1095 | update_dependency_caches (dep_t dep, enum reg_note old_type) | |
1096 | { | |
1097 | int elem_luid = INSN_LUID (DEP_PRO (dep)); | |
1098 | int insn_luid = INSN_LUID (DEP_CON (dep)); | |
1099 | ||
1100 | /* Clear corresponding cache entry because type of the link | |
1101 | may have changed. Keep them if we use_deps_list. */ | |
1102 | if (!(current_sched_info->flags & USE_DEPS_LIST)) | |
1103 | { | |
1104 | switch (old_type) | |
1105 | { | |
1106 | case REG_DEP_OUTPUT: | |
1107 | bitmap_clear_bit (&output_dependency_cache[insn_luid], elem_luid); | |
1108 | break; | |
1109 | ||
1110 | case REG_DEP_ANTI: | |
1111 | bitmap_clear_bit (&anti_dependency_cache[insn_luid], elem_luid); | |
1112 | break; | |
1113 | ||
e2724e63 BS |
1114 | case REG_DEP_CONTROL: |
1115 | bitmap_clear_bit (&control_dependency_cache[insn_luid], elem_luid); | |
1116 | break; | |
1117 | ||
e2f6ff94 | 1118 | default: |
b8698a0f | 1119 | gcc_unreachable (); |
e2f6ff94 MK |
1120 | } |
1121 | } | |
1122 | ||
1123 | set_dependency_caches (dep); | |
1124 | } | |
1125 | ||
1126 | /* Convert a dependence pointed to by SD_IT to be non-speculative. */ | |
1127 | static void | |
1128 | change_spec_dep_to_hard (sd_iterator_def sd_it) | |
1129 | { | |
1130 | dep_node_t node = DEP_LINK_NODE (*sd_it.linkp); | |
1131 | dep_link_t link = DEP_NODE_BACK (node); | |
1132 | dep_t dep = DEP_NODE_DEP (node); | |
974c43e9 DM |
1133 | rtx_insn *elem = DEP_PRO (dep); |
1134 | rtx_insn *insn = DEP_CON (dep); | |
e2f6ff94 MK |
1135 | |
1136 | move_dep_link (link, INSN_SPEC_BACK_DEPS (insn), INSN_HARD_BACK_DEPS (insn)); | |
1137 | ||
1138 | DEP_STATUS (dep) &= ~SPECULATIVE; | |
16f6ece6 | 1139 | |
16f6ece6 | 1140 | if (true_dependency_cache != NULL) |
e2f6ff94 MK |
1141 | /* Clear the cache entry. */ |
1142 | bitmap_clear_bit (&spec_dependency_cache[INSN_LUID (insn)], | |
1143 | INSN_LUID (elem)); | |
1144 | } | |
e2f6ff94 MK |
1145 | |
1146 | /* Update DEP to incorporate information from NEW_DEP. | |
1147 | SD_IT points to DEP in case it should be moved to another list. | |
1148 | MEM1 and MEM2, if nonnull, correspond to memory locations in case if | |
1149 | data-speculative dependence should be updated. */ | |
1150 | static enum DEPS_ADJUST_RESULT | |
1151 | update_dep (dep_t dep, dep_t new_dep, | |
a34ef915 MK |
1152 | sd_iterator_def sd_it ATTRIBUTE_UNUSED, |
1153 | rtx mem1 ATTRIBUTE_UNUSED, | |
1154 | rtx mem2 ATTRIBUTE_UNUSED) | |
e2f6ff94 MK |
1155 | { |
1156 | enum DEPS_ADJUST_RESULT res = DEP_PRESENT; | |
1157 | enum reg_note old_type = DEP_TYPE (dep); | |
b953c2b8 | 1158 | bool was_spec = dep_spec_p (dep); |
e2f6ff94 | 1159 | |
1a83e602 BS |
1160 | DEP_NONREG (dep) |= DEP_NONREG (new_dep); |
1161 | DEP_MULTIPLE (dep) = 1; | |
1162 | ||
e2f6ff94 MK |
1163 | /* If this is a more restrictive type of dependence than the |
1164 | existing one, then change the existing dependence to this | |
1165 | type. */ | |
1166 | if ((int) DEP_TYPE (new_dep) < (int) old_type) | |
16f6ece6 | 1167 | { |
e2f6ff94 MK |
1168 | DEP_TYPE (dep) = DEP_TYPE (new_dep); |
1169 | res = DEP_CHANGED; | |
1170 | } | |
1171 | ||
e2f6ff94 MK |
1172 | if (current_sched_info->flags & USE_DEPS_LIST) |
1173 | /* Update DEP_STATUS. */ | |
1174 | { | |
1175 | ds_t dep_status = DEP_STATUS (dep); | |
1176 | ds_t ds = DEP_STATUS (new_dep); | |
1177 | ds_t new_status = ds | dep_status; | |
1178 | ||
1179 | if (new_status & SPECULATIVE) | |
e2f6ff94 | 1180 | { |
b953c2b8 BS |
1181 | /* Either existing dep or a dep we're adding or both are |
1182 | speculative. */ | |
e2f6ff94 MK |
1183 | if (!(ds & SPECULATIVE) |
1184 | || !(dep_status & SPECULATIVE)) | |
1185 | /* The new dep can't be speculative. */ | |
b953c2b8 | 1186 | new_status &= ~SPECULATIVE; |
e2f6ff94 | 1187 | else |
ddbd5439 | 1188 | { |
e2f6ff94 MK |
1189 | /* Both are speculative. Merge probabilities. */ |
1190 | if (mem1 != NULL) | |
ddbd5439 | 1191 | { |
e2f6ff94 MK |
1192 | dw_t dw; |
1193 | ||
1194 | dw = estimate_dep_weak (mem1, mem2); | |
1195 | ds = set_dep_weak (ds, BEGIN_DATA, dw); | |
ddbd5439 | 1196 | } |
b8698a0f | 1197 | |
e2f6ff94 | 1198 | new_status = ds_merge (dep_status, ds); |
ddbd5439 | 1199 | } |
e2f6ff94 MK |
1200 | } |
1201 | ||
1202 | ds = new_status; | |
1203 | ||
1204 | if (dep_status != ds) | |
1205 | { | |
1206 | DEP_STATUS (dep) = ds; | |
1207 | res = DEP_CHANGED; | |
1208 | } | |
1209 | } | |
1210 | ||
b953c2b8 BS |
1211 | if (was_spec && !dep_spec_p (dep)) |
1212 | /* The old dep was speculative, but now it isn't. */ | |
1213 | change_spec_dep_to_hard (sd_it); | |
1214 | ||
e2f6ff94 MK |
1215 | if (true_dependency_cache != NULL |
1216 | && res == DEP_CHANGED) | |
1217 | update_dependency_caches (dep, old_type); | |
e2f6ff94 MK |
1218 | |
1219 | return res; | |
1220 | } | |
1221 | ||
1222 | /* Add or update a dependence described by DEP. | |
1223 | MEM1 and MEM2, if non-null, correspond to memory locations in case of | |
1224 | data speculation. | |
1225 | ||
1226 | The function returns a value indicating if an old entry has been changed | |
1227 | or a new entry has been added to insn's backward deps or nothing has | |
1228 | been updated at all. */ | |
1229 | static enum DEPS_ADJUST_RESULT | |
1230 | add_or_update_dep_1 (dep_t new_dep, bool resolved_p, | |
1231 | rtx mem1 ATTRIBUTE_UNUSED, rtx mem2 ATTRIBUTE_UNUSED) | |
1232 | { | |
1233 | bool maybe_present_p = true; | |
1234 | bool present_p = false; | |
1235 | ||
1236 | gcc_assert (INSN_P (DEP_PRO (new_dep)) && INSN_P (DEP_CON (new_dep)) | |
1237 | && DEP_PRO (new_dep) != DEP_CON (new_dep)); | |
b8698a0f | 1238 | |
e2f6ff94 MK |
1239 | #ifdef ENABLE_CHECKING |
1240 | check_dep (new_dep, mem1 != NULL); | |
1241 | #endif | |
1242 | ||
1243 | if (true_dependency_cache != NULL) | |
1244 | { | |
1245 | switch (ask_dependency_caches (new_dep)) | |
1246 | { | |
1247 | case DEP_PRESENT: | |
a0107bd0 JJ |
1248 | dep_t present_dep; |
1249 | sd_iterator_def sd_it; | |
1250 | ||
1251 | present_dep = sd_find_dep_between_no_cache (DEP_PRO (new_dep), | |
1252 | DEP_CON (new_dep), | |
1253 | resolved_p, &sd_it); | |
1254 | DEP_MULTIPLE (present_dep) = 1; | |
e2f6ff94 MK |
1255 | return DEP_PRESENT; |
1256 | ||
1257 | case DEP_CHANGED: | |
1258 | maybe_present_p = true; | |
1259 | present_p = true; | |
1260 | break; | |
1261 | ||
1262 | case DEP_CREATED: | |
1263 | maybe_present_p = false; | |
1264 | present_p = false; | |
1265 | break; | |
1266 | ||
1267 | default: | |
1268 | gcc_unreachable (); | |
1269 | break; | |
1270 | } | |
16f6ece6 | 1271 | } |
16f6ece6 BS |
1272 | |
1273 | /* Check that we don't already have this dependence. */ | |
ddbd5439 MK |
1274 | if (maybe_present_p) |
1275 | { | |
e2f6ff94 MK |
1276 | dep_t present_dep; |
1277 | sd_iterator_def sd_it; | |
ddbd5439 | 1278 | |
e2f6ff94 | 1279 | gcc_assert (true_dependency_cache == NULL || present_p); |
46c5ad27 | 1280 | |
e2f6ff94 MK |
1281 | present_dep = sd_find_dep_between_no_cache (DEP_PRO (new_dep), |
1282 | DEP_CON (new_dep), | |
1283 | resolved_p, &sd_it); | |
786de7eb | 1284 | |
e2f6ff94 MK |
1285 | if (present_dep != NULL) |
1286 | /* We found an existing dependency between ELEM and INSN. */ | |
1287 | return update_dep (present_dep, new_dep, sd_it, mem1, mem2); | |
1288 | else | |
1289 | /* We didn't find a dep, it shouldn't present in the cache. */ | |
1290 | gcc_assert (!present_p); | |
ddbd5439 | 1291 | } |
16f6ece6 | 1292 | |
ddbd5439 | 1293 | /* Might want to check one level of transitivity to save conses. |
e2f6ff94 MK |
1294 | This check should be done in maybe_add_or_update_dep_1. |
1295 | Since we made it to add_or_update_dep_1, we must create | |
ddbd5439 | 1296 | (or update) a link. */ |
16f6ece6 | 1297 | |
e2f6ff94 | 1298 | if (mem1 != NULL_RTX) |
ddbd5439 | 1299 | { |
e855c69d | 1300 | gcc_assert (sched_deps_info->generate_spec_deps); |
e2f6ff94 MK |
1301 | DEP_STATUS (new_dep) = set_dep_weak (DEP_STATUS (new_dep), BEGIN_DATA, |
1302 | estimate_dep_weak (mem1, mem2)); | |
ddbd5439 | 1303 | } |
e2f6ff94 MK |
1304 | |
1305 | sd_add_dep (new_dep, resolved_p); | |
b8698a0f | 1306 | |
ddbd5439 MK |
1307 | return DEP_CREATED; |
1308 | } | |
16f6ece6 | 1309 | |
e2f6ff94 MK |
1310 | /* Initialize BACK_LIST_PTR with consumer's backward list and |
1311 | FORW_LIST_PTR with producer's forward list. If RESOLVED_P is true | |
1312 | initialize with lists that hold resolved deps. */ | |
ddbd5439 | 1313 | static void |
e2f6ff94 MK |
1314 | get_back_and_forw_lists (dep_t dep, bool resolved_p, |
1315 | deps_list_t *back_list_ptr, | |
1316 | deps_list_t *forw_list_ptr) | |
ddbd5439 | 1317 | { |
974c43e9 | 1318 | rtx_insn *con = DEP_CON (dep); |
b198261f | 1319 | |
e2f6ff94 MK |
1320 | if (!resolved_p) |
1321 | { | |
b953c2b8 | 1322 | if (dep_spec_p (dep)) |
e2f6ff94 MK |
1323 | *back_list_ptr = INSN_SPEC_BACK_DEPS (con); |
1324 | else | |
1325 | *back_list_ptr = INSN_HARD_BACK_DEPS (con); | |
ddbd5439 | 1326 | |
e2f6ff94 MK |
1327 | *forw_list_ptr = INSN_FORW_DEPS (DEP_PRO (dep)); |
1328 | } | |
ddbd5439 | 1329 | else |
e2f6ff94 MK |
1330 | { |
1331 | *back_list_ptr = INSN_RESOLVED_BACK_DEPS (con); | |
1332 | *forw_list_ptr = INSN_RESOLVED_FORW_DEPS (DEP_PRO (dep)); | |
1333 | } | |
1334 | } | |
1335 | ||
1336 | /* Add dependence described by DEP. | |
1337 | If RESOLVED_P is true treat the dependence as a resolved one. */ | |
1338 | void | |
1339 | sd_add_dep (dep_t dep, bool resolved_p) | |
1340 | { | |
1341 | dep_node_t n = create_dep_node (); | |
1342 | deps_list_t con_back_deps; | |
1343 | deps_list_t pro_forw_deps; | |
974c43e9 DM |
1344 | rtx_insn *elem = DEP_PRO (dep); |
1345 | rtx_insn *insn = DEP_CON (dep); | |
e2f6ff94 MK |
1346 | |
1347 | gcc_assert (INSN_P (insn) && INSN_P (elem) && insn != elem); | |
1348 | ||
b953c2b8 BS |
1349 | if ((current_sched_info->flags & DO_SPECULATION) == 0 |
1350 | || !sched_insn_is_legitimate_for_speculation_p (insn, DEP_STATUS (dep))) | |
e2f6ff94 MK |
1351 | DEP_STATUS (dep) &= ~SPECULATIVE; |
1352 | ||
1353 | copy_dep (DEP_NODE_DEP (n), dep); | |
1354 | ||
1355 | get_back_and_forw_lists (dep, resolved_p, &con_back_deps, &pro_forw_deps); | |
b198261f | 1356 | |
e2f6ff94 | 1357 | add_to_deps_list (DEP_NODE_BACK (n), con_back_deps); |
b198261f | 1358 | |
ddbd5439 | 1359 | #ifdef ENABLE_CHECKING |
e2f6ff94 | 1360 | check_dep (dep, false); |
ddbd5439 MK |
1361 | #endif |
1362 | ||
e2f6ff94 MK |
1363 | add_to_deps_list (DEP_NODE_FORW (n), pro_forw_deps); |
1364 | ||
16f6ece6 | 1365 | /* If we are adding a dependency to INSN's LOG_LINKs, then note that |
2d76cb1a | 1366 | in the bitmap caches of dependency information. */ |
16f6ece6 | 1367 | if (true_dependency_cache != NULL) |
e2f6ff94 | 1368 | set_dependency_caches (dep); |
e2f6ff94 MK |
1369 | } |
1370 | ||
1371 | /* Add or update backward dependence between INSN and ELEM | |
1372 | with given type DEP_TYPE and dep_status DS. | |
1373 | This function is a convenience wrapper. */ | |
1374 | enum DEPS_ADJUST_RESULT | |
1375 | sd_add_or_update_dep (dep_t dep, bool resolved_p) | |
1376 | { | |
1377 | return add_or_update_dep_1 (dep, resolved_p, NULL_RTX, NULL_RTX); | |
1378 | } | |
1379 | ||
1380 | /* Resolved dependence pointed to by SD_IT. | |
1381 | SD_IT will advance to the next element. */ | |
1382 | void | |
1383 | sd_resolve_dep (sd_iterator_def sd_it) | |
1384 | { | |
1385 | dep_node_t node = DEP_LINK_NODE (*sd_it.linkp); | |
1386 | dep_t dep = DEP_NODE_DEP (node); | |
974c43e9 DM |
1387 | rtx_insn *pro = DEP_PRO (dep); |
1388 | rtx_insn *con = DEP_CON (dep); | |
e2f6ff94 | 1389 | |
b953c2b8 | 1390 | if (dep_spec_p (dep)) |
e2f6ff94 MK |
1391 | move_dep_link (DEP_NODE_BACK (node), INSN_SPEC_BACK_DEPS (con), |
1392 | INSN_RESOLVED_BACK_DEPS (con)); | |
1393 | else | |
1394 | move_dep_link (DEP_NODE_BACK (node), INSN_HARD_BACK_DEPS (con), | |
1395 | INSN_RESOLVED_BACK_DEPS (con)); | |
1396 | ||
1397 | move_dep_link (DEP_NODE_FORW (node), INSN_FORW_DEPS (pro), | |
1398 | INSN_RESOLVED_FORW_DEPS (pro)); | |
1399 | } | |
1400 | ||
26965010 BS |
1401 | /* Perform the inverse operation of sd_resolve_dep. Restore the dependence |
1402 | pointed to by SD_IT to unresolved state. */ | |
1403 | void | |
1404 | sd_unresolve_dep (sd_iterator_def sd_it) | |
1405 | { | |
1406 | dep_node_t node = DEP_LINK_NODE (*sd_it.linkp); | |
1407 | dep_t dep = DEP_NODE_DEP (node); | |
974c43e9 DM |
1408 | rtx_insn *pro = DEP_PRO (dep); |
1409 | rtx_insn *con = DEP_CON (dep); | |
26965010 | 1410 | |
e2724e63 | 1411 | if (dep_spec_p (dep)) |
26965010 BS |
1412 | move_dep_link (DEP_NODE_BACK (node), INSN_RESOLVED_BACK_DEPS (con), |
1413 | INSN_SPEC_BACK_DEPS (con)); | |
1414 | else | |
1415 | move_dep_link (DEP_NODE_BACK (node), INSN_RESOLVED_BACK_DEPS (con), | |
1416 | INSN_HARD_BACK_DEPS (con)); | |
1417 | ||
1418 | move_dep_link (DEP_NODE_FORW (node), INSN_RESOLVED_FORW_DEPS (pro), | |
1419 | INSN_FORW_DEPS (pro)); | |
1420 | } | |
1421 | ||
e2f6ff94 MK |
1422 | /* Make TO depend on all the FROM's producers. |
1423 | If RESOLVED_P is true add dependencies to the resolved lists. */ | |
1424 | void | |
0e0ce50d | 1425 | sd_copy_back_deps (rtx_insn *to, rtx_insn *from, bool resolved_p) |
e2f6ff94 MK |
1426 | { |
1427 | sd_list_types_def list_type; | |
1428 | sd_iterator_def sd_it; | |
1429 | dep_t dep; | |
1430 | ||
1431 | list_type = resolved_p ? SD_LIST_RES_BACK : SD_LIST_BACK; | |
1432 | ||
1433 | FOR_EACH_DEP (from, list_type, sd_it, dep) | |
16f6ece6 | 1434 | { |
e2f6ff94 MK |
1435 | dep_def _new_dep, *new_dep = &_new_dep; |
1436 | ||
1437 | copy_dep (new_dep, dep); | |
0e0ce50d | 1438 | DEP_CON (new_dep) = to; |
e2f6ff94 | 1439 | sd_add_dep (new_dep, resolved_p); |
16f6ece6 | 1440 | } |
e2f6ff94 MK |
1441 | } |
1442 | ||
1443 | /* Remove a dependency referred to by SD_IT. | |
1444 | SD_IT will point to the next dependence after removal. */ | |
1445 | void | |
1446 | sd_delete_dep (sd_iterator_def sd_it) | |
1447 | { | |
1448 | dep_node_t n = DEP_LINK_NODE (*sd_it.linkp); | |
1449 | dep_t dep = DEP_NODE_DEP (n); | |
974c43e9 DM |
1450 | rtx_insn *pro = DEP_PRO (dep); |
1451 | rtx_insn *con = DEP_CON (dep); | |
e2f6ff94 MK |
1452 | deps_list_t con_back_deps; |
1453 | deps_list_t pro_forw_deps; | |
1454 | ||
1455 | if (true_dependency_cache != NULL) | |
1456 | { | |
1457 | int elem_luid = INSN_LUID (pro); | |
1458 | int insn_luid = INSN_LUID (con); | |
1459 | ||
1460 | bitmap_clear_bit (&true_dependency_cache[insn_luid], elem_luid); | |
1461 | bitmap_clear_bit (&anti_dependency_cache[insn_luid], elem_luid); | |
e2724e63 | 1462 | bitmap_clear_bit (&control_dependency_cache[insn_luid], elem_luid); |
e2f6ff94 MK |
1463 | bitmap_clear_bit (&output_dependency_cache[insn_luid], elem_luid); |
1464 | ||
1465 | if (current_sched_info->flags & DO_SPECULATION) | |
1466 | bitmap_clear_bit (&spec_dependency_cache[insn_luid], elem_luid); | |
1467 | } | |
1468 | ||
1469 | get_back_and_forw_lists (dep, sd_it.resolved_p, | |
1470 | &con_back_deps, &pro_forw_deps); | |
1471 | ||
1472 | remove_from_deps_list (DEP_NODE_BACK (n), con_back_deps); | |
1473 | remove_from_deps_list (DEP_NODE_FORW (n), pro_forw_deps); | |
1474 | ||
1475 | delete_dep_node (n); | |
1476 | } | |
1477 | ||
1478 | /* Dump size of the lists. */ | |
1479 | #define DUMP_LISTS_SIZE (2) | |
1480 | ||
1481 | /* Dump dependencies of the lists. */ | |
1482 | #define DUMP_LISTS_DEPS (4) | |
1483 | ||
1484 | /* Dump all information about the lists. */ | |
1485 | #define DUMP_LISTS_ALL (DUMP_LISTS_SIZE | DUMP_LISTS_DEPS) | |
1486 | ||
1487 | /* Dump deps_lists of INSN specified by TYPES to DUMP. | |
1488 | FLAGS is a bit mask specifying what information about the lists needs | |
1489 | to be printed. | |
1490 | If FLAGS has the very first bit set, then dump all information about | |
1491 | the lists and propagate this bit into the callee dump functions. */ | |
1492 | static void | |
1493 | dump_lists (FILE *dump, rtx insn, sd_list_types_def types, int flags) | |
1494 | { | |
1495 | sd_iterator_def sd_it; | |
1496 | dep_t dep; | |
1497 | int all; | |
1498 | ||
1499 | all = (flags & 1); | |
1500 | ||
1501 | if (all) | |
1502 | flags |= DUMP_LISTS_ALL; | |
1503 | ||
1504 | fprintf (dump, "["); | |
1505 | ||
1506 | if (flags & DUMP_LISTS_SIZE) | |
1507 | fprintf (dump, "%d; ", sd_lists_size (insn, types)); | |
1508 | ||
1509 | if (flags & DUMP_LISTS_DEPS) | |
1510 | { | |
1511 | FOR_EACH_DEP (insn, types, sd_it, dep) | |
1512 | { | |
1513 | dump_dep (dump, dep, dump_dep_flags | all); | |
1514 | fprintf (dump, " "); | |
1515 | } | |
1516 | } | |
1517 | } | |
1518 | ||
1519 | /* Dump all information about deps_lists of INSN specified by TYPES | |
1520 | to STDERR. */ | |
1521 | void | |
1522 | sd_debug_lists (rtx insn, sd_list_types_def types) | |
1523 | { | |
1524 | dump_lists (stderr, insn, types, 1); | |
1525 | fprintf (stderr, "\n"); | |
16f6ece6 BS |
1526 | } |
1527 | ||
e2724e63 BS |
1528 | /* A wrapper around add_dependence_1, to add a dependence of CON on |
1529 | PRO, with type DEP_TYPE. This function implements special handling | |
1530 | for REG_DEP_CONTROL dependencies. For these, we optionally promote | |
1531 | the type to REG_DEP_ANTI if we can determine that predication is | |
1532 | impossible; otherwise we add additional true dependencies on the | |
1533 | INSN_COND_DEPS list of the jump (which PRO must be). */ | |
1534 | void | |
ce1ce33a | 1535 | add_dependence (rtx_insn *con, rtx_insn *pro, enum reg_note dep_type) |
e2724e63 | 1536 | { |
f561ef0f BS |
1537 | if (dep_type == REG_DEP_CONTROL |
1538 | && !(current_sched_info->flags & DO_PREDICATION)) | |
1539 | dep_type = REG_DEP_ANTI; | |
1540 | ||
e2724e63 BS |
1541 | /* A REG_DEP_CONTROL dependence may be eliminated through predication, |
1542 | so we must also make the insn dependent on the setter of the | |
1543 | condition. */ | |
1544 | if (dep_type == REG_DEP_CONTROL) | |
1545 | { | |
f57aa6b0 DM |
1546 | rtx_insn *real_pro = pro; |
1547 | rtx_insn *other = real_insn_for_shadow (real_pro); | |
e2724e63 BS |
1548 | rtx cond; |
1549 | ||
1550 | if (other != NULL_RTX) | |
1551 | real_pro = other; | |
1552 | cond = sched_get_reverse_condition_uncached (real_pro); | |
1553 | /* Verify that the insn does not use a different value in | |
1554 | the condition register than the one that was present at | |
1555 | the jump. */ | |
1556 | if (cond == NULL_RTX) | |
1557 | dep_type = REG_DEP_ANTI; | |
1558 | else if (INSN_CACHED_COND (real_pro) == const_true_rtx) | |
1559 | { | |
1560 | HARD_REG_SET uses; | |
1561 | CLEAR_HARD_REG_SET (uses); | |
1562 | note_uses (&PATTERN (con), record_hard_reg_uses, &uses); | |
1563 | if (TEST_HARD_REG_BIT (uses, REGNO (XEXP (cond, 0)))) | |
1564 | dep_type = REG_DEP_ANTI; | |
1565 | } | |
1566 | if (dep_type == REG_DEP_CONTROL) | |
1567 | { | |
1568 | if (sched_verbose >= 5) | |
1569 | fprintf (sched_dump, "making DEP_CONTROL for %d\n", | |
1570 | INSN_UID (real_pro)); | |
1571 | add_dependence_list (con, INSN_COND_DEPS (real_pro), 0, | |
1a83e602 | 1572 | REG_DEP_TRUE, false); |
e2724e63 BS |
1573 | } |
1574 | } | |
1575 | ||
1576 | add_dependence_1 (con, pro, dep_type); | |
1577 | } | |
1578 | ||
1a83e602 BS |
1579 | /* A convenience wrapper to operate on an entire list. HARD should be |
1580 | true if DEP_NONREG should be set on newly created dependencies. */ | |
37a0f8a5 RH |
1581 | |
1582 | static void | |
3dc99c19 DM |
1583 | add_dependence_list (rtx_insn *insn, rtx_insn_list *list, int uncond, |
1584 | enum reg_note dep_type, bool hard) | |
37a0f8a5 | 1585 | { |
1a83e602 | 1586 | mark_as_hard = hard; |
3dc99c19 | 1587 | for (; list; list = list->next ()) |
2bd1e239 | 1588 | { |
3dc99c19 DM |
1589 | if (uncond || ! sched_insns_conditions_mutex_p (insn, list->insn ())) |
1590 | add_dependence (insn, list->insn (), dep_type); | |
2bd1e239 | 1591 | } |
1a83e602 | 1592 | mark_as_hard = false; |
37a0f8a5 RH |
1593 | } |
1594 | ||
b8698a0f | 1595 | /* Similar, but free *LISTP at the same time, when the context |
1a83e602 BS |
1596 | is not readonly. HARD should be true if DEP_NONREG should be set on |
1597 | newly created dependencies. */ | |
37a0f8a5 RH |
1598 | |
1599 | static void | |
3dc99c19 DM |
1600 | add_dependence_list_and_free (struct deps_desc *deps, rtx_insn *insn, |
1601 | rtx_insn_list **listp, | |
1a83e602 | 1602 | int uncond, enum reg_note dep_type, bool hard) |
37a0f8a5 | 1603 | { |
1a83e602 | 1604 | add_dependence_list (insn, *listp, uncond, dep_type, hard); |
e855c69d | 1605 | |
39e7207a AO |
1606 | /* We don't want to short-circuit dependencies involving debug |
1607 | insns, because they may cause actual dependencies to be | |
1608 | disregarded. */ | |
1609 | if (deps->readonly || DEBUG_INSN_P (insn)) | |
8febe3fa | 1610 | return; |
e855c69d | 1611 | |
8febe3fa | 1612 | free_INSN_LIST_list (listp); |
37a0f8a5 RH |
1613 | } |
1614 | ||
073a8998 JM |
1615 | /* Remove all occurrences of INSN from LIST. Return the number of |
1616 | occurrences removed. */ | |
e855c69d AB |
1617 | |
1618 | static int | |
3dc99c19 | 1619 | remove_from_dependence_list (rtx insn, rtx_insn_list **listp) |
e855c69d AB |
1620 | { |
1621 | int removed = 0; | |
b8698a0f | 1622 | |
e855c69d AB |
1623 | while (*listp) |
1624 | { | |
3dc99c19 | 1625 | if ((*listp)->insn () == insn) |
e855c69d AB |
1626 | { |
1627 | remove_free_INSN_LIST_node (listp); | |
1628 | removed++; | |
1629 | continue; | |
1630 | } | |
b8698a0f | 1631 | |
3dc99c19 | 1632 | listp = (rtx_insn_list **)&XEXP (*listp, 1); |
e855c69d | 1633 | } |
b8698a0f | 1634 | |
e855c69d AB |
1635 | return removed; |
1636 | } | |
1637 | ||
1638 | /* Same as above, but process two lists at once. */ | |
b8698a0f | 1639 | static int |
3dc99c19 DM |
1640 | remove_from_both_dependence_lists (rtx insn, |
1641 | rtx_insn_list **listp, | |
2f33ff0a | 1642 | rtx_expr_list **exprp) |
e855c69d AB |
1643 | { |
1644 | int removed = 0; | |
b8698a0f | 1645 | |
e855c69d AB |
1646 | while (*listp) |
1647 | { | |
1648 | if (XEXP (*listp, 0) == insn) | |
1649 | { | |
1650 | remove_free_INSN_LIST_node (listp); | |
1651 | remove_free_EXPR_LIST_node (exprp); | |
1652 | removed++; | |
1653 | continue; | |
1654 | } | |
b8698a0f | 1655 | |
3dc99c19 | 1656 | listp = (rtx_insn_list **)&XEXP (*listp, 1); |
2f33ff0a | 1657 | exprp = (rtx_expr_list **)&XEXP (*exprp, 1); |
e855c69d | 1658 | } |
b8698a0f | 1659 | |
e855c69d AB |
1660 | return removed; |
1661 | } | |
1662 | ||
4c2b2906 | 1663 | /* Clear all dependencies for an insn. */ |
16f6ece6 | 1664 | static void |
4c2b2906 | 1665 | delete_all_dependences (rtx insn) |
16f6ece6 | 1666 | { |
e2f6ff94 MK |
1667 | sd_iterator_def sd_it; |
1668 | dep_t dep; | |
16f6ece6 | 1669 | |
e2f6ff94 MK |
1670 | /* The below cycle can be optimized to clear the caches and back_deps |
1671 | in one call but that would provoke duplication of code from | |
1672 | delete_dep (). */ | |
16f6ece6 | 1673 | |
e2f6ff94 MK |
1674 | for (sd_it = sd_iterator_start (insn, SD_LIST_BACK); |
1675 | sd_iterator_cond (&sd_it, &dep);) | |
1676 | sd_delete_dep (sd_it); | |
4c2b2906 EC |
1677 | } |
1678 | ||
1679 | /* All insns in a scheduling group except the first should only have | |
1680 | dependencies on the previous insn in the group. So we find the | |
1681 | first instruction in the scheduling group by walking the dependence | |
1682 | chains backwards. Then we add the dependencies for the group to | |
1683 | the previous nonnote insn. */ | |
1684 | ||
1685 | static void | |
ce1ce33a | 1686 | chain_to_prev_insn (rtx_insn *insn) |
4c2b2906 | 1687 | { |
e2f6ff94 MK |
1688 | sd_iterator_def sd_it; |
1689 | dep_t dep; | |
ce1ce33a | 1690 | rtx_insn *prev_nonnote; |
4c2b2906 | 1691 | |
e2f6ff94 | 1692 | FOR_EACH_DEP (insn, SD_LIST_BACK, sd_it, dep) |
4c2b2906 | 1693 | { |
ce1ce33a | 1694 | rtx_insn *i = insn; |
974c43e9 | 1695 | rtx_insn *pro = DEP_PRO (dep); |
b198261f | 1696 | |
4c2b2906 EC |
1697 | do |
1698 | { | |
1699 | i = prev_nonnote_insn (i); | |
1700 | ||
b198261f | 1701 | if (pro == i) |
4c2b2906 | 1702 | goto next_link; |
b5b8b0ac | 1703 | } while (SCHED_GROUP_P (i) || DEBUG_INSN_P (i)); |
b198261f MK |
1704 | |
1705 | if (! sched_insns_conditions_mutex_p (i, pro)) | |
e2f6ff94 | 1706 | add_dependence (i, pro, DEP_TYPE (dep)); |
4c2b2906 EC |
1707 | next_link:; |
1708 | } | |
1709 | ||
1710 | delete_all_dependences (insn); | |
1711 | ||
f0fc0803 | 1712 | prev_nonnote = prev_nonnote_nondebug_insn (insn); |
2bd1e239 SB |
1713 | if (BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (prev_nonnote) |
1714 | && ! sched_insns_conditions_mutex_p (insn, prev_nonnote)) | |
1715 | add_dependence (insn, prev_nonnote, REG_DEP_ANTI); | |
16f6ece6 BS |
1716 | } |
1717 | \f | |
1718 | /* Process an insn's memory dependencies. There are four kinds of | |
1719 | dependencies: | |
1720 | ||
1721 | (0) read dependence: read follows read | |
1722 | (1) true dependence: read follows write | |
ddbd5439 MK |
1723 | (2) output dependence: write follows write |
1724 | (3) anti dependence: write follows read | |
16f6ece6 BS |
1725 | |
1726 | We are careful to build only dependencies which actually exist, and | |
1727 | use transitivity to avoid building too many links. */ | |
1728 | ||
1729 | /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST. | |
1730 | The MEM is a memory reference contained within INSN, which we are saving | |
1731 | so that we can do memory aliasing on it. */ | |
1732 | ||
c66a4368 | 1733 | static void |
88302d54 | 1734 | add_insn_mem_dependence (struct deps_desc *deps, bool read_p, |
12ea1b95 | 1735 | rtx_insn *insn, rtx mem) |
16f6ece6 | 1736 | { |
3dc99c19 DM |
1737 | rtx_insn_list **insn_list; |
1738 | rtx_insn_list *insn_node; | |
2f33ff0a DM |
1739 | rtx_expr_list **mem_list; |
1740 | rtx_expr_list *mem_node; | |
16f6ece6 | 1741 | |
e855c69d | 1742 | gcc_assert (!deps->readonly); |
bdbf40a5 MK |
1743 | if (read_p) |
1744 | { | |
1745 | insn_list = &deps->pending_read_insns; | |
1746 | mem_list = &deps->pending_read_mems; | |
f49b295a AO |
1747 | if (!DEBUG_INSN_P (insn)) |
1748 | deps->pending_read_list_length++; | |
bdbf40a5 MK |
1749 | } |
1750 | else | |
1751 | { | |
1752 | insn_list = &deps->pending_write_insns; | |
1753 | mem_list = &deps->pending_write_mems; | |
1754 | deps->pending_write_list_length++; | |
1755 | } | |
1756 | ||
3dc99c19 DM |
1757 | insn_node = alloc_INSN_LIST (insn, *insn_list); |
1758 | *insn_list = insn_node; | |
16f6ece6 | 1759 | |
e855c69d | 1760 | if (sched_deps_info->use_cselib) |
4b6c5340 BS |
1761 | { |
1762 | mem = shallow_copy_rtx (mem); | |
9a76e83d JJ |
1763 | XEXP (mem, 0) = cselib_subst_to_values_from_insn (XEXP (mem, 0), |
1764 | GET_MODE (mem), insn); | |
4b6c5340 | 1765 | } |
3dc99c19 DM |
1766 | mem_node = alloc_EXPR_LIST (VOIDmode, canon_rtx (mem), *mem_list); |
1767 | *mem_list = mem_node; | |
16f6ece6 BS |
1768 | } |
1769 | ||
1770 | /* Make a dependency between every memory reference on the pending lists | |
37a0f8a5 RH |
1771 | and INSN, thus flushing the pending lists. FOR_READ is true if emitting |
1772 | dependencies for a read operation, similarly with FOR_WRITE. */ | |
16f6ece6 BS |
1773 | |
1774 | static void | |
ce1ce33a | 1775 | flush_pending_lists (struct deps_desc *deps, rtx_insn *insn, int for_read, |
46c5ad27 | 1776 | int for_write) |
16f6ece6 | 1777 | { |
37a0f8a5 | 1778 | if (for_write) |
16f6ece6 | 1779 | { |
b8698a0f | 1780 | add_dependence_list_and_free (deps, insn, &deps->pending_read_insns, |
1a83e602 | 1781 | 1, REG_DEP_ANTI, true); |
e855c69d AB |
1782 | if (!deps->readonly) |
1783 | { | |
1784 | free_EXPR_LIST_list (&deps->pending_read_mems); | |
1785 | deps->pending_read_list_length = 0; | |
1786 | } | |
16f6ece6 | 1787 | } |
16f6ece6 | 1788 | |
e855c69d | 1789 | add_dependence_list_and_free (deps, insn, &deps->pending_write_insns, 1, |
1a83e602 BS |
1790 | for_read ? REG_DEP_ANTI : REG_DEP_OUTPUT, |
1791 | true); | |
16f6ece6 | 1792 | |
b8698a0f | 1793 | add_dependence_list_and_free (deps, insn, |
e855c69d | 1794 | &deps->last_pending_memory_flush, 1, |
1a83e602 BS |
1795 | for_read ? REG_DEP_ANTI : REG_DEP_OUTPUT, |
1796 | true); | |
e2724e63 BS |
1797 | |
1798 | add_dependence_list_and_free (deps, insn, &deps->pending_jump_insns, 1, | |
1a83e602 | 1799 | REG_DEP_ANTI, true); |
e2724e63 | 1800 | |
8febe3fa MK |
1801 | if (DEBUG_INSN_P (insn)) |
1802 | { | |
1803 | if (for_write) | |
1804 | free_INSN_LIST_list (&deps->pending_read_insns); | |
1805 | free_INSN_LIST_list (&deps->pending_write_insns); | |
1806 | free_INSN_LIST_list (&deps->last_pending_memory_flush); | |
1807 | free_INSN_LIST_list (&deps->pending_jump_insns); | |
1808 | } | |
1809 | ||
e855c69d AB |
1810 | if (!deps->readonly) |
1811 | { | |
1812 | free_EXPR_LIST_list (&deps->pending_write_mems); | |
1813 | deps->pending_write_list_length = 0; | |
1814 | ||
1815 | deps->last_pending_memory_flush = alloc_INSN_LIST (insn, NULL_RTX); | |
1816 | deps->pending_flush_length = 1; | |
1817 | } | |
1a83e602 | 1818 | mark_as_hard = false; |
e855c69d AB |
1819 | } |
1820 | \f | |
1821 | /* Instruction which dependencies we are analyzing. */ | |
ce1ce33a | 1822 | static rtx_insn *cur_insn = NULL; |
e855c69d AB |
1823 | |
1824 | /* Implement hooks for haifa scheduler. */ | |
1825 | ||
1826 | static void | |
6144a836 | 1827 | haifa_start_insn (rtx_insn *insn) |
e855c69d AB |
1828 | { |
1829 | gcc_assert (insn && !cur_insn); | |
1830 | ||
6144a836 | 1831 | cur_insn = insn; |
e855c69d AB |
1832 | } |
1833 | ||
1834 | static void | |
1835 | haifa_finish_insn (void) | |
1836 | { | |
1837 | cur_insn = NULL; | |
1838 | } | |
1839 | ||
1840 | void | |
1841 | haifa_note_reg_set (int regno) | |
1842 | { | |
1843 | SET_REGNO_REG_SET (reg_pending_sets, regno); | |
1844 | } | |
1845 | ||
1846 | void | |
1847 | haifa_note_reg_clobber (int regno) | |
1848 | { | |
1849 | SET_REGNO_REG_SET (reg_pending_clobbers, regno); | |
1850 | } | |
1851 | ||
1852 | void | |
1853 | haifa_note_reg_use (int regno) | |
1854 | { | |
1855 | SET_REGNO_REG_SET (reg_pending_uses, regno); | |
1856 | } | |
1857 | ||
1858 | static void | |
6144a836 | 1859 | haifa_note_mem_dep (rtx mem, rtx pending_mem, rtx_insn *pending_insn, ds_t ds) |
e855c69d AB |
1860 | { |
1861 | if (!(ds & SPECULATIVE)) | |
1862 | { | |
1863 | mem = NULL_RTX; | |
1864 | pending_mem = NULL_RTX; | |
1865 | } | |
1866 | else | |
1867 | gcc_assert (ds & BEGIN_DATA); | |
1868 | ||
1869 | { | |
1870 | dep_def _dep, *dep = &_dep; | |
b8698a0f | 1871 | |
ce18efcb | 1872 | init_dep_1 (dep, pending_insn, cur_insn, ds_to_dt (ds), |
b953c2b8 | 1873 | current_sched_info->flags & USE_DEPS_LIST ? ds : 0); |
1a83e602 | 1874 | DEP_NONREG (dep) = 1; |
e855c69d AB |
1875 | maybe_add_or_update_dep_1 (dep, false, pending_mem, mem); |
1876 | } | |
1877 | ||
1878 | } | |
1879 | ||
1880 | static void | |
6144a836 | 1881 | haifa_note_dep (rtx_insn *elem, ds_t ds) |
e855c69d AB |
1882 | { |
1883 | dep_def _dep; | |
1884 | dep_t dep = &_dep; | |
1885 | ||
1886 | init_dep (dep, elem, cur_insn, ds_to_dt (ds)); | |
1a83e602 BS |
1887 | if (mark_as_hard) |
1888 | DEP_NONREG (dep) = 1; | |
e855c69d AB |
1889 | maybe_add_or_update_dep_1 (dep, false, NULL_RTX, NULL_RTX); |
1890 | } | |
1891 | ||
1892 | static void | |
1893 | note_reg_use (int r) | |
1894 | { | |
1895 | if (sched_deps_info->note_reg_use) | |
1896 | sched_deps_info->note_reg_use (r); | |
1897 | } | |
1898 | ||
1899 | static void | |
1900 | note_reg_set (int r) | |
1901 | { | |
1902 | if (sched_deps_info->note_reg_set) | |
1903 | sched_deps_info->note_reg_set (r); | |
1904 | } | |
1905 | ||
1906 | static void | |
1907 | note_reg_clobber (int r) | |
1908 | { | |
1909 | if (sched_deps_info->note_reg_clobber) | |
1910 | sched_deps_info->note_reg_clobber (r); | |
1911 | } | |
1912 | ||
1913 | static void | |
6144a836 | 1914 | note_mem_dep (rtx m1, rtx m2, rtx_insn *e, ds_t ds) |
e855c69d AB |
1915 | { |
1916 | if (sched_deps_info->note_mem_dep) | |
1917 | sched_deps_info->note_mem_dep (m1, m2, e, ds); | |
1918 | } | |
1919 | ||
1920 | static void | |
ce1ce33a | 1921 | note_dep (rtx_insn *e, ds_t ds) |
e855c69d AB |
1922 | { |
1923 | if (sched_deps_info->note_dep) | |
1924 | sched_deps_info->note_dep (e, ds); | |
1925 | } | |
1926 | ||
1927 | /* Return corresponding to DS reg_note. */ | |
1928 | enum reg_note | |
1929 | ds_to_dt (ds_t ds) | |
1930 | { | |
1931 | if (ds & DEP_TRUE) | |
1932 | return REG_DEP_TRUE; | |
1933 | else if (ds & DEP_OUTPUT) | |
1934 | return REG_DEP_OUTPUT; | |
e2724e63 BS |
1935 | else if (ds & DEP_ANTI) |
1936 | return REG_DEP_ANTI; | |
e855c69d AB |
1937 | else |
1938 | { | |
e2724e63 BS |
1939 | gcc_assert (ds & DEP_CONTROL); |
1940 | return REG_DEP_CONTROL; | |
e855c69d | 1941 | } |
16f6ece6 | 1942 | } |
ce18efcb VM |
1943 | |
1944 | \f | |
1945 | ||
1946 | /* Functions for computation of info needed for register pressure | |
1947 | sensitive insn scheduling. */ | |
1948 | ||
1949 | ||
1950 | /* Allocate and return reg_use_data structure for REGNO and INSN. */ | |
1951 | static struct reg_use_data * | |
f57aa6b0 | 1952 | create_insn_reg_use (int regno, rtx_insn *insn) |
ce18efcb VM |
1953 | { |
1954 | struct reg_use_data *use; | |
1955 | ||
1956 | use = (struct reg_use_data *) xmalloc (sizeof (struct reg_use_data)); | |
1957 | use->regno = regno; | |
1958 | use->insn = insn; | |
1959 | use->next_insn_use = INSN_REG_USE_LIST (insn); | |
1960 | INSN_REG_USE_LIST (insn) = use; | |
1961 | return use; | |
1962 | } | |
1963 | ||
f20f2613 VM |
1964 | /* Allocate reg_set_data structure for REGNO and INSN. */ |
1965 | static void | |
ce18efcb VM |
1966 | create_insn_reg_set (int regno, rtx insn) |
1967 | { | |
1968 | struct reg_set_data *set; | |
1969 | ||
1970 | set = (struct reg_set_data *) xmalloc (sizeof (struct reg_set_data)); | |
1971 | set->regno = regno; | |
1972 | set->insn = insn; | |
1973 | set->next_insn_set = INSN_REG_SET_LIST (insn); | |
1974 | INSN_REG_SET_LIST (insn) = set; | |
ce18efcb VM |
1975 | } |
1976 | ||
1977 | /* Set up insn register uses for INSN and dependency context DEPS. */ | |
1978 | static void | |
f57aa6b0 | 1979 | setup_insn_reg_uses (struct deps_desc *deps, rtx_insn *insn) |
ce18efcb VM |
1980 | { |
1981 | unsigned i; | |
1982 | reg_set_iterator rsi; | |
ce18efcb VM |
1983 | struct reg_use_data *use, *use2, *next; |
1984 | struct deps_reg *reg_last; | |
1985 | ||
1986 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_uses, 0, i, rsi) | |
1987 | { | |
1988 | if (i < FIRST_PSEUDO_REGISTER | |
1989 | && TEST_HARD_REG_BIT (ira_no_alloc_regs, i)) | |
1990 | continue; | |
1991 | ||
1992 | if (find_regno_note (insn, REG_DEAD, i) == NULL_RTX | |
1993 | && ! REGNO_REG_SET_P (reg_pending_sets, i) | |
1994 | && ! REGNO_REG_SET_P (reg_pending_clobbers, i)) | |
1995 | /* Ignore use which is not dying. */ | |
1996 | continue; | |
1997 | ||
1998 | use = create_insn_reg_use (i, insn); | |
1999 | use->next_regno_use = use; | |
2000 | reg_last = &deps->reg_last[i]; | |
b8698a0f | 2001 | |
ce18efcb | 2002 | /* Create the cycle list of uses. */ |
c838c402 | 2003 | for (rtx_insn_list *list = reg_last->uses; list; list = list->next ()) |
ce18efcb | 2004 | { |
c838c402 | 2005 | use2 = create_insn_reg_use (i, list->insn ()); |
ce18efcb VM |
2006 | next = use->next_regno_use; |
2007 | use->next_regno_use = use2; | |
2008 | use2->next_regno_use = next; | |
2009 | } | |
2010 | } | |
2011 | } | |
2012 | ||
2013 | /* Register pressure info for the currently processed insn. */ | |
2014 | static struct reg_pressure_data reg_pressure_info[N_REG_CLASSES]; | |
2015 | ||
2016 | /* Return TRUE if INSN has the use structure for REGNO. */ | |
2017 | static bool | |
2018 | insn_use_p (rtx insn, int regno) | |
2019 | { | |
2020 | struct reg_use_data *use; | |
2021 | ||
2022 | for (use = INSN_REG_USE_LIST (insn); use != NULL; use = use->next_insn_use) | |
2023 | if (use->regno == regno) | |
2024 | return true; | |
2025 | return false; | |
2026 | } | |
2027 | ||
2028 | /* Update the register pressure info after birth of pseudo register REGNO | |
2029 | in INSN. Arguments CLOBBER_P and UNUSED_P say correspondingly that | |
2030 | the register is in clobber or unused after the insn. */ | |
2031 | static void | |
2032 | mark_insn_pseudo_birth (rtx insn, int regno, bool clobber_p, bool unused_p) | |
2033 | { | |
2034 | int incr, new_incr; | |
2035 | enum reg_class cl; | |
2036 | ||
2037 | gcc_assert (regno >= FIRST_PSEUDO_REGISTER); | |
1756cb66 | 2038 | cl = sched_regno_pressure_class[regno]; |
ce18efcb VM |
2039 | if (cl != NO_REGS) |
2040 | { | |
1756cb66 | 2041 | incr = ira_reg_class_max_nregs[cl][PSEUDO_REGNO_MODE (regno)]; |
ce18efcb VM |
2042 | if (clobber_p) |
2043 | { | |
2044 | new_incr = reg_pressure_info[cl].clobber_increase + incr; | |
2045 | reg_pressure_info[cl].clobber_increase = new_incr; | |
2046 | } | |
2047 | else if (unused_p) | |
2048 | { | |
2049 | new_incr = reg_pressure_info[cl].unused_set_increase + incr; | |
2050 | reg_pressure_info[cl].unused_set_increase = new_incr; | |
2051 | } | |
2052 | else | |
2053 | { | |
2054 | new_incr = reg_pressure_info[cl].set_increase + incr; | |
2055 | reg_pressure_info[cl].set_increase = new_incr; | |
2056 | if (! insn_use_p (insn, regno)) | |
2057 | reg_pressure_info[cl].change += incr; | |
2058 | create_insn_reg_set (regno, insn); | |
2059 | } | |
2060 | gcc_assert (new_incr < (1 << INCREASE_BITS)); | |
2061 | } | |
2062 | } | |
2063 | ||
2064 | /* Like mark_insn_pseudo_regno_birth except that NREGS saying how many | |
2065 | hard registers involved in the birth. */ | |
2066 | static void | |
2067 | mark_insn_hard_regno_birth (rtx insn, int regno, int nregs, | |
2068 | bool clobber_p, bool unused_p) | |
2069 | { | |
2070 | enum reg_class cl; | |
2071 | int new_incr, last = regno + nregs; | |
b8698a0f | 2072 | |
ce18efcb VM |
2073 | while (regno < last) |
2074 | { | |
2075 | gcc_assert (regno < FIRST_PSEUDO_REGISTER); | |
2076 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
2077 | { | |
1756cb66 | 2078 | cl = sched_regno_pressure_class[regno]; |
ce18efcb VM |
2079 | if (cl != NO_REGS) |
2080 | { | |
2081 | if (clobber_p) | |
2082 | { | |
2083 | new_incr = reg_pressure_info[cl].clobber_increase + 1; | |
2084 | reg_pressure_info[cl].clobber_increase = new_incr; | |
2085 | } | |
2086 | else if (unused_p) | |
2087 | { | |
2088 | new_incr = reg_pressure_info[cl].unused_set_increase + 1; | |
2089 | reg_pressure_info[cl].unused_set_increase = new_incr; | |
2090 | } | |
2091 | else | |
2092 | { | |
2093 | new_incr = reg_pressure_info[cl].set_increase + 1; | |
2094 | reg_pressure_info[cl].set_increase = new_incr; | |
2095 | if (! insn_use_p (insn, regno)) | |
2096 | reg_pressure_info[cl].change += 1; | |
2097 | create_insn_reg_set (regno, insn); | |
2098 | } | |
2099 | gcc_assert (new_incr < (1 << INCREASE_BITS)); | |
2100 | } | |
2101 | } | |
2102 | regno++; | |
2103 | } | |
2104 | } | |
2105 | ||
2106 | /* Update the register pressure info after birth of pseudo or hard | |
2107 | register REG in INSN. Arguments CLOBBER_P and UNUSED_P say | |
2108 | correspondingly that the register is in clobber or unused after the | |
2109 | insn. */ | |
2110 | static void | |
2111 | mark_insn_reg_birth (rtx insn, rtx reg, bool clobber_p, bool unused_p) | |
2112 | { | |
2113 | int regno; | |
2114 | ||
2115 | if (GET_CODE (reg) == SUBREG) | |
2116 | reg = SUBREG_REG (reg); | |
2117 | ||
2118 | if (! REG_P (reg)) | |
2119 | return; | |
2120 | ||
2121 | regno = REGNO (reg); | |
2122 | if (regno < FIRST_PSEUDO_REGISTER) | |
2123 | mark_insn_hard_regno_birth (insn, regno, | |
2124 | hard_regno_nregs[regno][GET_MODE (reg)], | |
2125 | clobber_p, unused_p); | |
2126 | else | |
2127 | mark_insn_pseudo_birth (insn, regno, clobber_p, unused_p); | |
2128 | } | |
2129 | ||
2130 | /* Update the register pressure info after death of pseudo register | |
2131 | REGNO. */ | |
2132 | static void | |
2133 | mark_pseudo_death (int regno) | |
2134 | { | |
2135 | int incr; | |
2136 | enum reg_class cl; | |
2137 | ||
2138 | gcc_assert (regno >= FIRST_PSEUDO_REGISTER); | |
1756cb66 | 2139 | cl = sched_regno_pressure_class[regno]; |
ce18efcb VM |
2140 | if (cl != NO_REGS) |
2141 | { | |
1756cb66 | 2142 | incr = ira_reg_class_max_nregs[cl][PSEUDO_REGNO_MODE (regno)]; |
ce18efcb VM |
2143 | reg_pressure_info[cl].change -= incr; |
2144 | } | |
2145 | } | |
2146 | ||
2147 | /* Like mark_pseudo_death except that NREGS saying how many hard | |
2148 | registers involved in the death. */ | |
2149 | static void | |
2150 | mark_hard_regno_death (int regno, int nregs) | |
2151 | { | |
2152 | enum reg_class cl; | |
2153 | int last = regno + nregs; | |
b8698a0f | 2154 | |
ce18efcb VM |
2155 | while (regno < last) |
2156 | { | |
2157 | gcc_assert (regno < FIRST_PSEUDO_REGISTER); | |
2158 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
2159 | { | |
1756cb66 | 2160 | cl = sched_regno_pressure_class[regno]; |
ce18efcb VM |
2161 | if (cl != NO_REGS) |
2162 | reg_pressure_info[cl].change -= 1; | |
2163 | } | |
2164 | regno++; | |
2165 | } | |
2166 | } | |
2167 | ||
2168 | /* Update the register pressure info after death of pseudo or hard | |
2169 | register REG. */ | |
2170 | static void | |
2171 | mark_reg_death (rtx reg) | |
2172 | { | |
2173 | int regno; | |
2174 | ||
2175 | if (GET_CODE (reg) == SUBREG) | |
2176 | reg = SUBREG_REG (reg); | |
2177 | ||
2178 | if (! REG_P (reg)) | |
2179 | return; | |
2180 | ||
2181 | regno = REGNO (reg); | |
2182 | if (regno < FIRST_PSEUDO_REGISTER) | |
2183 | mark_hard_regno_death (regno, hard_regno_nregs[regno][GET_MODE (reg)]); | |
2184 | else | |
2185 | mark_pseudo_death (regno); | |
2186 | } | |
2187 | ||
2188 | /* Process SETTER of REG. DATA is an insn containing the setter. */ | |
2189 | static void | |
2190 | mark_insn_reg_store (rtx reg, const_rtx setter, void *data) | |
2191 | { | |
2192 | if (setter != NULL_RTX && GET_CODE (setter) != SET) | |
2193 | return; | |
2194 | mark_insn_reg_birth | |
2195 | ((rtx) data, reg, false, | |
2196 | find_reg_note ((const_rtx) data, REG_UNUSED, reg) != NULL_RTX); | |
2197 | } | |
2198 | ||
2199 | /* Like mark_insn_reg_store except notice just CLOBBERs; ignore SETs. */ | |
2200 | static void | |
2201 | mark_insn_reg_clobber (rtx reg, const_rtx setter, void *data) | |
2202 | { | |
2203 | if (GET_CODE (setter) == CLOBBER) | |
2204 | mark_insn_reg_birth ((rtx) data, reg, true, false); | |
2205 | } | |
2206 | ||
2207 | /* Set up reg pressure info related to INSN. */ | |
19ac7892 AB |
2208 | void |
2209 | init_insn_reg_pressure_info (rtx insn) | |
ce18efcb VM |
2210 | { |
2211 | int i, len; | |
2212 | enum reg_class cl; | |
2213 | static struct reg_pressure_data *pressure_info; | |
2214 | rtx link; | |
2215 | ||
7a1aca9c | 2216 | gcc_assert (sched_pressure != SCHED_PRESSURE_NONE); |
ce18efcb VM |
2217 | |
2218 | if (! INSN_P (insn)) | |
2219 | return; | |
2220 | ||
1756cb66 | 2221 | for (i = 0; i < ira_pressure_classes_num; i++) |
ce18efcb | 2222 | { |
1756cb66 | 2223 | cl = ira_pressure_classes[i]; |
ce18efcb VM |
2224 | reg_pressure_info[cl].clobber_increase = 0; |
2225 | reg_pressure_info[cl].set_increase = 0; | |
2226 | reg_pressure_info[cl].unused_set_increase = 0; | |
2227 | reg_pressure_info[cl].change = 0; | |
2228 | } | |
b8698a0f | 2229 | |
ce18efcb | 2230 | note_stores (PATTERN (insn), mark_insn_reg_clobber, insn); |
b8698a0f | 2231 | |
ce18efcb | 2232 | note_stores (PATTERN (insn), mark_insn_reg_store, insn); |
b8698a0f | 2233 | |
ce18efcb VM |
2234 | #ifdef AUTO_INC_DEC |
2235 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
2236 | if (REG_NOTE_KIND (link) == REG_INC) | |
2237 | mark_insn_reg_store (XEXP (link, 0), NULL_RTX, insn); | |
2238 | #endif | |
2239 | ||
2240 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
2241 | if (REG_NOTE_KIND (link) == REG_DEAD) | |
2242 | mark_reg_death (XEXP (link, 0)); | |
b8698a0f | 2243 | |
1756cb66 | 2244 | len = sizeof (struct reg_pressure_data) * ira_pressure_classes_num; |
ce18efcb VM |
2245 | pressure_info |
2246 | = INSN_REG_PRESSURE (insn) = (struct reg_pressure_data *) xmalloc (len); | |
7a1aca9c RS |
2247 | if (sched_pressure == SCHED_PRESSURE_WEIGHTED) |
2248 | INSN_MAX_REG_PRESSURE (insn) = (int *) xcalloc (ira_pressure_classes_num | |
2249 | * sizeof (int), 1); | |
1756cb66 | 2250 | for (i = 0; i < ira_pressure_classes_num; i++) |
ce18efcb | 2251 | { |
1756cb66 | 2252 | cl = ira_pressure_classes[i]; |
ce18efcb VM |
2253 | pressure_info[i].clobber_increase |
2254 | = reg_pressure_info[cl].clobber_increase; | |
2255 | pressure_info[i].set_increase = reg_pressure_info[cl].set_increase; | |
2256 | pressure_info[i].unused_set_increase | |
2257 | = reg_pressure_info[cl].unused_set_increase; | |
2258 | pressure_info[i].change = reg_pressure_info[cl].change; | |
2259 | } | |
2260 | } | |
2261 | ||
2262 | ||
16f6ece6 | 2263 | \f |
e855c69d AB |
2264 | |
2265 | /* Internal variable for sched_analyze_[12] () functions. | |
2266 | If it is nonzero, this means that sched_analyze_[12] looks | |
2267 | at the most toplevel SET. */ | |
2268 | static bool can_start_lhs_rhs_p; | |
2269 | ||
b8698a0f | 2270 | /* Extend reg info for the deps context DEPS given that |
e855c69d AB |
2271 | we have just generated a register numbered REGNO. */ |
2272 | static void | |
88302d54 | 2273 | extend_deps_reg_info (struct deps_desc *deps, int regno) |
e855c69d AB |
2274 | { |
2275 | int max_regno = regno + 1; | |
2276 | ||
2277 | gcc_assert (!reload_completed); | |
2278 | ||
2279 | /* In a readonly context, it would not hurt to extend info, | |
2280 | but it should not be needed. */ | |
2281 | if (reload_completed && deps->readonly) | |
2282 | { | |
2283 | deps->max_reg = max_regno; | |
2284 | return; | |
2285 | } | |
2286 | ||
2287 | if (max_regno > deps->max_reg) | |
2288 | { | |
b8698a0f | 2289 | deps->reg_last = XRESIZEVEC (struct deps_reg, deps->reg_last, |
e855c69d AB |
2290 | max_regno); |
2291 | memset (&deps->reg_last[deps->max_reg], | |
b8698a0f | 2292 | 0, (max_regno - deps->max_reg) |
e855c69d AB |
2293 | * sizeof (struct deps_reg)); |
2294 | deps->max_reg = max_regno; | |
2295 | } | |
2296 | } | |
2297 | ||
2298 | /* Extends REG_INFO_P if needed. */ | |
2299 | void | |
2300 | maybe_extend_reg_info_p (void) | |
2301 | { | |
2302 | /* Extend REG_INFO_P, if needed. */ | |
2303 | if ((unsigned int)max_regno - 1 >= reg_info_p_size) | |
2304 | { | |
2305 | size_t new_reg_info_p_size = max_regno + 128; | |
2306 | ||
2307 | gcc_assert (!reload_completed && sel_sched_p ()); | |
2308 | ||
2309 | reg_info_p = (struct reg_info_t *) xrecalloc (reg_info_p, | |
2310 | new_reg_info_p_size, | |
2311 | reg_info_p_size, | |
2312 | sizeof (*reg_info_p)); | |
2313 | reg_info_p_size = new_reg_info_p_size; | |
2314 | } | |
2315 | } | |
2316 | ||
2e9182fd EB |
2317 | /* Analyze a single reference to register (reg:MODE REGNO) in INSN. |
2318 | The type of the reference is specified by REF and can be SET, | |
2319 | CLOBBER, PRE_DEC, POST_DEC, PRE_INC, POST_INC or USE. */ | |
2320 | ||
2321 | static void | |
ef4bddc2 | 2322 | sched_analyze_reg (struct deps_desc *deps, int regno, machine_mode mode, |
ce1ce33a | 2323 | enum rtx_code ref, rtx_insn *insn) |
2e9182fd | 2324 | { |
e855c69d AB |
2325 | /* We could emit new pseudos in renaming. Extend the reg structures. */ |
2326 | if (!reload_completed && sel_sched_p () | |
2327 | && (regno >= max_reg_num () - 1 || regno >= deps->max_reg)) | |
2328 | extend_deps_reg_info (deps, regno); | |
2329 | ||
2330 | maybe_extend_reg_info_p (); | |
2331 | ||
2e9182fd EB |
2332 | /* A hard reg in a wide mode may really be multiple registers. |
2333 | If so, mark all of them just like the first. */ | |
2334 | if (regno < FIRST_PSEUDO_REGISTER) | |
2335 | { | |
2336 | int i = hard_regno_nregs[regno][mode]; | |
2337 | if (ref == SET) | |
2338 | { | |
2339 | while (--i >= 0) | |
e855c69d | 2340 | note_reg_set (regno + i); |
2e9182fd EB |
2341 | } |
2342 | else if (ref == USE) | |
2343 | { | |
2344 | while (--i >= 0) | |
e855c69d | 2345 | note_reg_use (regno + i); |
2e9182fd EB |
2346 | } |
2347 | else | |
2348 | { | |
2349 | while (--i >= 0) | |
e855c69d | 2350 | note_reg_clobber (regno + i); |
2e9182fd EB |
2351 | } |
2352 | } | |
2353 | ||
2354 | /* ??? Reload sometimes emits USEs and CLOBBERs of pseudos that | |
2355 | it does not reload. Ignore these as they have served their | |
2356 | purpose already. */ | |
2357 | else if (regno >= deps->max_reg) | |
2358 | { | |
2359 | enum rtx_code code = GET_CODE (PATTERN (insn)); | |
2360 | gcc_assert (code == USE || code == CLOBBER); | |
2361 | } | |
2362 | ||
2363 | else | |
2364 | { | |
2365 | if (ref == SET) | |
e855c69d | 2366 | note_reg_set (regno); |
2e9182fd | 2367 | else if (ref == USE) |
e855c69d | 2368 | note_reg_use (regno); |
2e9182fd | 2369 | else |
e855c69d | 2370 | note_reg_clobber (regno); |
2e9182fd EB |
2371 | |
2372 | /* Pseudos that are REG_EQUIV to something may be replaced | |
2373 | by that during reloading. We need only add dependencies for | |
2374 | the address in the REG_EQUIV note. */ | |
2375 | if (!reload_completed && get_reg_known_equiv_p (regno)) | |
2376 | { | |
2377 | rtx t = get_reg_known_value (regno); | |
2378 | if (MEM_P (t)) | |
2379 | sched_analyze_2 (deps, XEXP (t, 0), insn); | |
2380 | } | |
2381 | ||
2382 | /* Don't let it cross a call after scheduling if it doesn't | |
2383 | already cross one. */ | |
2384 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
2385 | { | |
b5b8b0ac | 2386 | if (!deps->readonly && ref == USE && !DEBUG_INSN_P (insn)) |
2e9182fd EB |
2387 | deps->sched_before_next_call |
2388 | = alloc_INSN_LIST (insn, deps->sched_before_next_call); | |
2389 | else | |
2390 | add_dependence_list (insn, deps->last_function_call, 1, | |
1a83e602 | 2391 | REG_DEP_ANTI, false); |
2e9182fd EB |
2392 | } |
2393 | } | |
2394 | } | |
2395 | ||
16f6ece6 BS |
2396 | /* Analyze a single SET, CLOBBER, PRE_DEC, POST_DEC, PRE_INC or POST_INC |
2397 | rtx, X, creating all dependencies generated by the write to the | |
2398 | destination of X, and reads of everything mentioned. */ | |
2399 | ||
2400 | static void | |
ce1ce33a | 2401 | sched_analyze_1 (struct deps_desc *deps, rtx x, rtx_insn *insn) |
16f6ece6 | 2402 | { |
b3694847 | 2403 | rtx dest = XEXP (x, 0); |
16f6ece6 | 2404 | enum rtx_code code = GET_CODE (x); |
e855c69d | 2405 | bool cslr_p = can_start_lhs_rhs_p; |
16f6ece6 | 2406 | |
e855c69d AB |
2407 | can_start_lhs_rhs_p = false; |
2408 | ||
2409 | gcc_assert (dest); | |
16f6ece6 BS |
2410 | if (dest == 0) |
2411 | return; | |
2412 | ||
e855c69d AB |
2413 | if (cslr_p && sched_deps_info->start_lhs) |
2414 | sched_deps_info->start_lhs (dest); | |
2415 | ||
7193d1dc | 2416 | if (GET_CODE (dest) == PARALLEL) |
16f6ece6 | 2417 | { |
b3694847 | 2418 | int i; |
90d036a0 | 2419 | |
16f6ece6 | 2420 | for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) |
7193d1dc RK |
2421 | if (XEXP (XVECEXP (dest, 0, i), 0) != 0) |
2422 | sched_analyze_1 (deps, | |
2423 | gen_rtx_CLOBBER (VOIDmode, | |
2424 | XEXP (XVECEXP (dest, 0, i), 0)), | |
2425 | insn); | |
90d036a0 | 2426 | |
e855c69d AB |
2427 | if (cslr_p && sched_deps_info->finish_lhs) |
2428 | sched_deps_info->finish_lhs (); | |
2429 | ||
2430 | if (code == SET) | |
2431 | { | |
2432 | can_start_lhs_rhs_p = cslr_p; | |
2433 | ||
2434 | sched_analyze_2 (deps, SET_SRC (x), insn); | |
2435 | ||
2436 | can_start_lhs_rhs_p = false; | |
2437 | } | |
2438 | ||
16f6ece6 BS |
2439 | return; |
2440 | } | |
2441 | ||
2442 | while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG | |
46d096a3 | 2443 | || GET_CODE (dest) == ZERO_EXTRACT) |
16f6ece6 | 2444 | { |
37bd08f8 HP |
2445 | if (GET_CODE (dest) == STRICT_LOW_PART |
2446 | || GET_CODE (dest) == ZERO_EXTRACT | |
4d779342 | 2447 | || df_read_modify_subreg_p (dest)) |
37bd08f8 | 2448 | { |
46c5ad27 | 2449 | /* These both read and modify the result. We must handle |
37bd08f8 HP |
2450 | them as writes to get proper dependencies for following |
2451 | instructions. We must handle them as reads to get proper | |
2452 | dependencies from this to previous instructions. | |
71c0e7fc | 2453 | Thus we need to call sched_analyze_2. */ |
37bd08f8 | 2454 | |
46c5ad27 | 2455 | sched_analyze_2 (deps, XEXP (dest, 0), insn); |
37bd08f8 | 2456 | } |
46d096a3 | 2457 | if (GET_CODE (dest) == ZERO_EXTRACT) |
16f6ece6 BS |
2458 | { |
2459 | /* The second and third arguments are values read by this insn. */ | |
2460 | sched_analyze_2 (deps, XEXP (dest, 1), insn); | |
2461 | sched_analyze_2 (deps, XEXP (dest, 2), insn); | |
2462 | } | |
2463 | dest = XEXP (dest, 0); | |
2464 | } | |
2465 | ||
f8cfc6aa | 2466 | if (REG_P (dest)) |
16f6ece6 | 2467 | { |
2e9182fd | 2468 | int regno = REGNO (dest); |
ef4bddc2 | 2469 | machine_mode mode = GET_MODE (dest); |
2e9182fd EB |
2470 | |
2471 | sched_analyze_reg (deps, regno, mode, code, insn); | |
16f6ece6 | 2472 | |
c3bdeea8 RS |
2473 | #ifdef STACK_REGS |
2474 | /* Treat all writes to a stack register as modifying the TOS. */ | |
2475 | if (regno >= FIRST_STACK_REG && regno <= LAST_STACK_REG) | |
2476 | { | |
2e9182fd EB |
2477 | /* Avoid analyzing the same register twice. */ |
2478 | if (regno != FIRST_STACK_REG) | |
2479 | sched_analyze_reg (deps, FIRST_STACK_REG, mode, code, insn); | |
ce18efcb | 2480 | |
d108e679 AS |
2481 | add_to_hard_reg_set (&implicit_reg_pending_uses, mode, |
2482 | FIRST_STACK_REG); | |
c3bdeea8 RS |
2483 | } |
2484 | #endif | |
16f6ece6 | 2485 | } |
3c0cb5de | 2486 | else if (MEM_P (dest)) |
16f6ece6 BS |
2487 | { |
2488 | /* Writing memory. */ | |
4b6c5340 BS |
2489 | rtx t = dest; |
2490 | ||
e855c69d | 2491 | if (sched_deps_info->use_cselib) |
4b6c5340 | 2492 | { |
ef4bddc2 | 2493 | machine_mode address_mode = get_address_mode (dest); |
d4ebfa65 | 2494 | |
4b6c5340 | 2495 | t = shallow_copy_rtx (dest); |
4deef538 AO |
2496 | cselib_lookup_from_insn (XEXP (t, 0), address_mode, 1, |
2497 | GET_MODE (t), insn); | |
9a76e83d JJ |
2498 | XEXP (t, 0) |
2499 | = cselib_subst_to_values_from_insn (XEXP (t, 0), GET_MODE (t), | |
2500 | insn); | |
4b6c5340 | 2501 | } |
c7866154 | 2502 | t = canon_rtx (t); |
16f6ece6 | 2503 | |
e855c69d AB |
2504 | /* Pending lists can't get larger with a readonly context. */ |
2505 | if (!deps->readonly | |
2506 | && ((deps->pending_read_list_length + deps->pending_write_list_length) | |
2507 | > MAX_PENDING_LIST_LENGTH)) | |
16f6ece6 BS |
2508 | { |
2509 | /* Flush all pending reads and writes to prevent the pending lists | |
2510 | from getting any larger. Insn scheduling runs too slowly when | |
4a121cc3 | 2511 | these lists get long. When compiling GCC with itself, |
16f6ece6 | 2512 | this flush occurs 8 times for sparc, and 10 times for m88k using |
4a121cc3 | 2513 | the default value of 32. */ |
37a0f8a5 | 2514 | flush_pending_lists (deps, insn, false, true); |
16f6ece6 BS |
2515 | } |
2516 | else | |
2517 | { | |
c838c402 DM |
2518 | rtx_insn_list *pending; |
2519 | rtx_expr_list *pending_mem; | |
16f6ece6 BS |
2520 | |
2521 | pending = deps->pending_read_insns; | |
2522 | pending_mem = deps->pending_read_mems; | |
2523 | while (pending) | |
2524 | { | |
c838c402 DM |
2525 | if (anti_dependence (pending_mem->element (), t) |
2526 | && ! sched_insns_conditions_mutex_p (insn, pending->insn ())) | |
2527 | note_mem_dep (t, pending_mem->element (), pending->insn (), | |
e855c69d | 2528 | DEP_ANTI); |
16f6ece6 | 2529 | |
c838c402 DM |
2530 | pending = pending->next (); |
2531 | pending_mem = pending_mem->next (); | |
16f6ece6 BS |
2532 | } |
2533 | ||
2534 | pending = deps->pending_write_insns; | |
2535 | pending_mem = deps->pending_write_mems; | |
2536 | while (pending) | |
2537 | { | |
c838c402 DM |
2538 | if (output_dependence (pending_mem->element (), t) |
2539 | && ! sched_insns_conditions_mutex_p (insn, pending->insn ())) | |
2540 | note_mem_dep (t, pending_mem->element (), | |
2541 | pending->insn (), | |
e855c69d | 2542 | DEP_OUTPUT); |
16f6ece6 | 2543 | |
c838c402 DM |
2544 | pending = pending->next (); |
2545 | pending_mem = pending_mem-> next (); | |
16f6ece6 BS |
2546 | } |
2547 | ||
b27cedc6 | 2548 | add_dependence_list (insn, deps->last_pending_memory_flush, 1, |
1a83e602 | 2549 | REG_DEP_ANTI, true); |
e2724e63 | 2550 | add_dependence_list (insn, deps->pending_jump_insns, 1, |
1a83e602 | 2551 | REG_DEP_CONTROL, true); |
16f6ece6 | 2552 | |
e855c69d AB |
2553 | if (!deps->readonly) |
2554 | add_insn_mem_dependence (deps, false, insn, dest); | |
16f6ece6 BS |
2555 | } |
2556 | sched_analyze_2 (deps, XEXP (dest, 0), insn); | |
2557 | } | |
2558 | ||
e855c69d AB |
2559 | if (cslr_p && sched_deps_info->finish_lhs) |
2560 | sched_deps_info->finish_lhs (); | |
2561 | ||
16f6ece6 BS |
2562 | /* Analyze reads. */ |
2563 | if (GET_CODE (x) == SET) | |
e855c69d AB |
2564 | { |
2565 | can_start_lhs_rhs_p = cslr_p; | |
2566 | ||
2567 | sched_analyze_2 (deps, SET_SRC (x), insn); | |
2568 | ||
2569 | can_start_lhs_rhs_p = false; | |
2570 | } | |
16f6ece6 BS |
2571 | } |
2572 | ||
2573 | /* Analyze the uses of memory and registers in rtx X in INSN. */ | |
16f6ece6 | 2574 | static void |
ce1ce33a | 2575 | sched_analyze_2 (struct deps_desc *deps, rtx x, rtx_insn *insn) |
16f6ece6 | 2576 | { |
b3694847 SS |
2577 | int i; |
2578 | int j; | |
2579 | enum rtx_code code; | |
2580 | const char *fmt; | |
e855c69d AB |
2581 | bool cslr_p = can_start_lhs_rhs_p; |
2582 | ||
2583 | can_start_lhs_rhs_p = false; | |
16f6ece6 | 2584 | |
e855c69d | 2585 | gcc_assert (x); |
16f6ece6 BS |
2586 | if (x == 0) |
2587 | return; | |
2588 | ||
e855c69d AB |
2589 | if (cslr_p && sched_deps_info->start_rhs) |
2590 | sched_deps_info->start_rhs (x); | |
2591 | ||
16f6ece6 BS |
2592 | code = GET_CODE (x); |
2593 | ||
2594 | switch (code) | |
2595 | { | |
d8116890 | 2596 | CASE_CONST_ANY: |
16f6ece6 BS |
2597 | case SYMBOL_REF: |
2598 | case CONST: | |
2599 | case LABEL_REF: | |
bf520698 | 2600 | /* Ignore constants. */ |
e855c69d AB |
2601 | if (cslr_p && sched_deps_info->finish_rhs) |
2602 | sched_deps_info->finish_rhs (); | |
2603 | ||
16f6ece6 BS |
2604 | return; |
2605 | ||
2606 | #ifdef HAVE_cc0 | |
2607 | case CC0: | |
2608 | /* User of CC0 depends on immediately preceding insn. */ | |
4c2b2906 | 2609 | SCHED_GROUP_P (insn) = 1; |
caf819ae VM |
2610 | /* Don't move CC0 setter to another block (it can set up the |
2611 | same flag for previous CC0 users which is safe). */ | |
2612 | CANT_MOVE (prev_nonnote_insn (insn)) = 1; | |
e855c69d AB |
2613 | |
2614 | if (cslr_p && sched_deps_info->finish_rhs) | |
2615 | sched_deps_info->finish_rhs (); | |
2616 | ||
16f6ece6 BS |
2617 | return; |
2618 | #endif | |
2619 | ||
2620 | case REG: | |
2621 | { | |
16f6ece6 | 2622 | int regno = REGNO (x); |
ef4bddc2 | 2623 | machine_mode mode = GET_MODE (x); |
2e9182fd EB |
2624 | |
2625 | sched_analyze_reg (deps, regno, mode, USE, insn); | |
c3bdeea8 RS |
2626 | |
2627 | #ifdef STACK_REGS | |
2628 | /* Treat all reads of a stack register as modifying the TOS. */ | |
2629 | if (regno >= FIRST_STACK_REG && regno <= LAST_STACK_REG) | |
2630 | { | |
2e9182fd EB |
2631 | /* Avoid analyzing the same register twice. */ |
2632 | if (regno != FIRST_STACK_REG) | |
2633 | sched_analyze_reg (deps, FIRST_STACK_REG, mode, USE, insn); | |
2634 | sched_analyze_reg (deps, FIRST_STACK_REG, mode, SET, insn); | |
c3bdeea8 RS |
2635 | } |
2636 | #endif | |
e855c69d AB |
2637 | |
2638 | if (cslr_p && sched_deps_info->finish_rhs) | |
2639 | sched_deps_info->finish_rhs (); | |
2640 | ||
16f6ece6 BS |
2641 | return; |
2642 | } | |
2643 | ||
2644 | case MEM: | |
2645 | { | |
2646 | /* Reading memory. */ | |
2647 | rtx u; | |
c838c402 DM |
2648 | rtx_insn_list *pending; |
2649 | rtx_expr_list *pending_mem; | |
4b6c5340 | 2650 | rtx t = x; |
16f6ece6 | 2651 | |
e855c69d | 2652 | if (sched_deps_info->use_cselib) |
4b6c5340 | 2653 | { |
ef4bddc2 | 2654 | machine_mode address_mode = get_address_mode (t); |
d4ebfa65 | 2655 | |
4b6c5340 | 2656 | t = shallow_copy_rtx (t); |
4deef538 AO |
2657 | cselib_lookup_from_insn (XEXP (t, 0), address_mode, 1, |
2658 | GET_MODE (t), insn); | |
9a76e83d JJ |
2659 | XEXP (t, 0) |
2660 | = cselib_subst_to_values_from_insn (XEXP (t, 0), GET_MODE (t), | |
2661 | insn); | |
4b6c5340 | 2662 | } |
16f6ece6 | 2663 | |
f49b295a | 2664 | if (!DEBUG_INSN_P (insn)) |
16f6ece6 | 2665 | { |
f49b295a AO |
2666 | t = canon_rtx (t); |
2667 | pending = deps->pending_read_insns; | |
2668 | pending_mem = deps->pending_read_mems; | |
2669 | while (pending) | |
2670 | { | |
c838c402 | 2671 | if (read_dependence (pending_mem->element (), t) |
f49b295a | 2672 | && ! sched_insns_conditions_mutex_p (insn, |
c838c402 DM |
2673 | pending->insn ())) |
2674 | note_mem_dep (t, pending_mem->element (), | |
2675 | pending->insn (), | |
f49b295a AO |
2676 | DEP_ANTI); |
2677 | ||
c838c402 DM |
2678 | pending = pending->next (); |
2679 | pending_mem = pending_mem->next (); | |
f49b295a | 2680 | } |
16f6ece6 | 2681 | |
f49b295a AO |
2682 | pending = deps->pending_write_insns; |
2683 | pending_mem = deps->pending_write_mems; | |
2684 | while (pending) | |
e855c69d | 2685 | { |
c838c402 | 2686 | if (true_dependence (pending_mem->element (), VOIDmode, t) |
f49b295a | 2687 | && ! sched_insns_conditions_mutex_p (insn, |
c838c402 DM |
2688 | pending->insn ())) |
2689 | note_mem_dep (t, pending_mem->element (), | |
2690 | pending->insn (), | |
f49b295a AO |
2691 | sched_deps_info->generate_spec_deps |
2692 | ? BEGIN_DATA | DEP_TRUE : DEP_TRUE); | |
2693 | ||
c838c402 DM |
2694 | pending = pending->next (); |
2695 | pending_mem = pending_mem->next (); | |
f49b295a | 2696 | } |
e855c69d | 2697 | |
f49b295a | 2698 | for (u = deps->last_pending_memory_flush; u; u = XEXP (u, 1)) |
ce1ce33a DM |
2699 | add_dependence (insn, as_a <rtx_insn *> (XEXP (u, 0)), |
2700 | REG_DEP_ANTI); | |
e2724e63 BS |
2701 | |
2702 | for (u = deps->pending_jump_insns; u; u = XEXP (u, 1)) | |
2703 | if (deps_may_trap_p (x)) | |
2704 | { | |
2705 | if ((sched_deps_info->generate_spec_deps) | |
2706 | && sel_sched_p () && (spec_info->mask & BEGIN_CONTROL)) | |
2707 | { | |
2708 | ds_t ds = set_dep_weak (DEP_ANTI, BEGIN_CONTROL, | |
2709 | MAX_DEP_WEAK); | |
2710 | ||
ce1ce33a | 2711 | note_dep (as_a <rtx_insn *> (XEXP (u, 0)), ds); |
e2724e63 BS |
2712 | } |
2713 | else | |
ce1ce33a DM |
2714 | add_dependence (insn, as_a <rtx_insn *> (XEXP (u, 0)), |
2715 | REG_DEP_CONTROL); | |
e2724e63 | 2716 | } |
e855c69d | 2717 | } |
16f6ece6 BS |
2718 | |
2719 | /* Always add these dependencies to pending_reads, since | |
2720 | this insn may be followed by a write. */ | |
1baf9159 JJ |
2721 | if (!deps->readonly) |
2722 | { | |
2723 | if ((deps->pending_read_list_length | |
2724 | + deps->pending_write_list_length) | |
2725 | > MAX_PENDING_LIST_LENGTH | |
2726 | && !DEBUG_INSN_P (insn)) | |
2727 | flush_pending_lists (deps, insn, true, true); | |
2728 | add_insn_mem_dependence (deps, true, insn, x); | |
2729 | } | |
16f6ece6 | 2730 | |
16f6ece6 | 2731 | sched_analyze_2 (deps, XEXP (x, 0), insn); |
e855c69d AB |
2732 | |
2733 | if (cslr_p && sched_deps_info->finish_rhs) | |
2734 | sched_deps_info->finish_rhs (); | |
2735 | ||
16f6ece6 BS |
2736 | return; |
2737 | } | |
2738 | ||
2739 | /* Force pending stores to memory in case a trap handler needs them. */ | |
2740 | case TRAP_IF: | |
37a0f8a5 | 2741 | flush_pending_lists (deps, insn, true, false); |
16f6ece6 BS |
2742 | break; |
2743 | ||
3fce100b AK |
2744 | case PREFETCH: |
2745 | if (PREFETCH_SCHEDULE_BARRIER_P (x)) | |
2746 | reg_pending_barrier = TRUE_BARRIER; | |
0e80383f VM |
2747 | /* Prefetch insn contains addresses only. So if the prefetch |
2748 | address has no registers, there will be no dependencies on | |
2749 | the prefetch insn. This is wrong with result code | |
2750 | correctness point of view as such prefetch can be moved below | |
2751 | a jump insn which usually generates MOVE_BARRIER preventing | |
2752 | to move insns containing registers or memories through the | |
2753 | barrier. It is also wrong with generated code performance | |
2754 | point of view as prefetch withouth dependecies will have a | |
2755 | tendency to be issued later instead of earlier. It is hard | |
2756 | to generate accurate dependencies for prefetch insns as | |
2757 | prefetch has only the start address but it is better to have | |
2758 | something than nothing. */ | |
79f01c76 | 2759 | if (!deps->readonly) |
db1fb332 JJ |
2760 | { |
2761 | rtx x = gen_rtx_MEM (Pmode, XEXP (PATTERN (insn), 0)); | |
2762 | if (sched_deps_info->use_cselib) | |
2763 | cselib_lookup_from_insn (x, Pmode, true, VOIDmode, insn); | |
2764 | add_insn_mem_dependence (deps, true, insn, x); | |
2765 | } | |
3fce100b AK |
2766 | break; |
2767 | ||
a11fe699 UB |
2768 | case UNSPEC_VOLATILE: |
2769 | flush_pending_lists (deps, insn, true, true); | |
2770 | /* FALLTHRU */ | |
2771 | ||
16f6ece6 BS |
2772 | case ASM_OPERANDS: |
2773 | case ASM_INPUT: | |
16f6ece6 | 2774 | { |
16f6ece6 BS |
2775 | /* Traditional and volatile asm instructions must be considered to use |
2776 | and clobber all hard registers, all pseudo-registers and all of | |
2777 | memory. So must TRAP_IF and UNSPEC_VOLATILE operations. | |
2778 | ||
2779 | Consider for instance a volatile asm that changes the fpu rounding | |
2780 | mode. An insn should not be moved across this even if it only uses | |
2781 | pseudo-regs because it might give an incorrectly rounded result. */ | |
bf95b629 RB |
2782 | if ((code != ASM_OPERANDS || MEM_VOLATILE_P (x)) |
2783 | && !DEBUG_INSN_P (insn)) | |
d1c9693e | 2784 | reg_pending_barrier = TRUE_BARRIER; |
16f6ece6 BS |
2785 | |
2786 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
2787 | We can not just fall through here since then we would be confused | |
2788 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
2789 | traditional asms unlike their normal usage. */ | |
2790 | ||
2791 | if (code == ASM_OPERANDS) | |
2792 | { | |
2793 | for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++) | |
2794 | sched_analyze_2 (deps, ASM_OPERANDS_INPUT (x, j), insn); | |
e855c69d AB |
2795 | |
2796 | if (cslr_p && sched_deps_info->finish_rhs) | |
2797 | sched_deps_info->finish_rhs (); | |
2798 | ||
16f6ece6 BS |
2799 | return; |
2800 | } | |
2801 | break; | |
2802 | } | |
2803 | ||
2804 | case PRE_DEC: | |
2805 | case POST_DEC: | |
2806 | case PRE_INC: | |
2807 | case POST_INC: | |
2808 | /* These both read and modify the result. We must handle them as writes | |
2809 | to get proper dependencies for following instructions. We must handle | |
2810 | them as reads to get proper dependencies from this to previous | |
2811 | instructions. Thus we need to pass them to both sched_analyze_1 | |
2812 | and sched_analyze_2. We must call sched_analyze_2 first in order | |
2813 | to get the proper antecedent for the read. */ | |
2814 | sched_analyze_2 (deps, XEXP (x, 0), insn); | |
2815 | sched_analyze_1 (deps, x, insn); | |
e855c69d AB |
2816 | |
2817 | if (cslr_p && sched_deps_info->finish_rhs) | |
2818 | sched_deps_info->finish_rhs (); | |
2819 | ||
16f6ece6 BS |
2820 | return; |
2821 | ||
2822 | case POST_MODIFY: | |
2823 | case PRE_MODIFY: | |
2824 | /* op0 = op0 + op1 */ | |
2825 | sched_analyze_2 (deps, XEXP (x, 0), insn); | |
2826 | sched_analyze_2 (deps, XEXP (x, 1), insn); | |
2827 | sched_analyze_1 (deps, x, insn); | |
e855c69d AB |
2828 | |
2829 | if (cslr_p && sched_deps_info->finish_rhs) | |
2830 | sched_deps_info->finish_rhs (); | |
2831 | ||
16f6ece6 BS |
2832 | return; |
2833 | ||
2834 | default: | |
2835 | break; | |
2836 | } | |
2837 | ||
2838 | /* Other cases: walk the insn. */ | |
2839 | fmt = GET_RTX_FORMAT (code); | |
2840 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2841 | { | |
2842 | if (fmt[i] == 'e') | |
2843 | sched_analyze_2 (deps, XEXP (x, i), insn); | |
2844 | else if (fmt[i] == 'E') | |
2845 | for (j = 0; j < XVECLEN (x, i); j++) | |
2846 | sched_analyze_2 (deps, XVECEXP (x, i, j), insn); | |
2847 | } | |
e855c69d AB |
2848 | |
2849 | if (cslr_p && sched_deps_info->finish_rhs) | |
2850 | sched_deps_info->finish_rhs (); | |
16f6ece6 BS |
2851 | } |
2852 | ||
dc549f34 RR |
2853 | /* Try to group two fuseable insns together to prevent scheduler |
2854 | from scheduling them apart. */ | |
ba4fa581 WM |
2855 | |
2856 | static void | |
ac44248e | 2857 | sched_macro_fuse_insns (rtx_insn *insn) |
ba4fa581 | 2858 | { |
ac44248e | 2859 | rtx_insn *prev; |
ba4fa581 | 2860 | |
dc549f34 RR |
2861 | if (any_condjump_p (insn)) |
2862 | { | |
2863 | unsigned int condreg1, condreg2; | |
2864 | rtx cc_reg_1; | |
2865 | targetm.fixed_condition_code_regs (&condreg1, &condreg2); | |
2866 | cc_reg_1 = gen_rtx_REG (CCmode, condreg1); | |
2867 | prev = prev_nonnote_nondebug_insn (insn); | |
2868 | if (!reg_referenced_p (cc_reg_1, PATTERN (insn)) | |
2869 | || !prev | |
2870 | || !modified_in_p (cc_reg_1, prev)) | |
2871 | return; | |
2872 | } | |
2873 | else | |
2874 | { | |
2875 | rtx insn_set = single_set (insn); | |
ba4fa581 | 2876 | |
dc549f34 RR |
2877 | prev = prev_nonnote_nondebug_insn (insn); |
2878 | if (!prev | |
2879 | || !insn_set | |
2880 | || !single_set (prev) | |
2881 | || !modified_in_p (SET_DEST (insn_set), prev)) | |
2882 | return; | |
ba4fa581 | 2883 | |
dc549f34 RR |
2884 | } |
2885 | ||
2886 | if (targetm.sched.macro_fusion_pair_p (prev, insn)) | |
2887 | SCHED_GROUP_P (insn) = 1; | |
ba4fa581 | 2888 | |
ba4fa581 WM |
2889 | } |
2890 | ||
16f6ece6 | 2891 | /* Analyze an INSN with pattern X to find all dependencies. */ |
16f6ece6 | 2892 | static void |
ce1ce33a | 2893 | sched_analyze_insn (struct deps_desc *deps, rtx x, rtx_insn *insn) |
16f6ece6 | 2894 | { |
b3694847 | 2895 | RTX_CODE code = GET_CODE (x); |
16f6ece6 | 2896 | rtx link; |
3cd8c58a | 2897 | unsigned i; |
a2041967 | 2898 | reg_set_iterator rsi; |
16f6ece6 | 2899 | |
ce18efcb VM |
2900 | if (! reload_completed) |
2901 | { | |
2902 | HARD_REG_SET temp; | |
2903 | ||
2904 | extract_insn (insn); | |
1145837d | 2905 | preprocess_constraints (insn); |
ce18efcb | 2906 | ira_implicitly_set_insn_hard_regs (&temp); |
6eeea7a7 | 2907 | AND_COMPL_HARD_REG_SET (temp, ira_no_alloc_regs); |
ce18efcb VM |
2908 | IOR_HARD_REG_SET (implicit_reg_pending_clobbers, temp); |
2909 | } | |
2910 | ||
e855c69d AB |
2911 | can_start_lhs_rhs_p = (NONJUMP_INSN_P (insn) |
2912 | && code == SET); | |
2913 | ||
ba4fa581 WM |
2914 | /* Group compare and branch insns for macro-fusion. */ |
2915 | if (targetm.sched.macro_fusion_p | |
2916 | && targetm.sched.macro_fusion_p ()) | |
dc549f34 | 2917 | sched_macro_fuse_insns (insn); |
ba4fa581 | 2918 | |
1098d3a5 | 2919 | if (may_trap_p (x)) |
073a8998 | 2920 | /* Avoid moving trapping instructions across function calls that might |
1098d3a5 JJ |
2921 | not always return. */ |
2922 | add_dependence_list (insn, deps->last_function_call_may_noreturn, | |
1a83e602 | 2923 | 1, REG_DEP_ANTI, true); |
1098d3a5 | 2924 | |
7b4ef662 RH |
2925 | /* We must avoid creating a situation in which two successors of the |
2926 | current block have different unwind info after scheduling. If at any | |
2927 | point the two paths re-join this leads to incorrect unwind info. */ | |
2928 | /* ??? There are certain situations involving a forced frame pointer in | |
2929 | which, with extra effort, we could fix up the unwind info at a later | |
2930 | CFG join. However, it seems better to notice these cases earlier | |
2931 | during prologue generation and avoid marking the frame pointer setup | |
2932 | as frame-related at all. */ | |
2933 | if (RTX_FRAME_RELATED_P (insn)) | |
2db036a7 TV |
2934 | { |
2935 | /* Make sure prologue insn is scheduled before next jump. */ | |
2936 | deps->sched_before_next_jump | |
2937 | = alloc_INSN_LIST (insn, deps->sched_before_next_jump); | |
2938 | ||
2939 | /* Make sure epilogue insn is scheduled after preceding jumps. */ | |
1a83e602 BS |
2940 | add_dependence_list (insn, deps->pending_jump_insns, 1, REG_DEP_ANTI, |
2941 | true); | |
2db036a7 | 2942 | } |
7b4ef662 | 2943 | |
16f6ece6 BS |
2944 | if (code == COND_EXEC) |
2945 | { | |
2946 | sched_analyze_2 (deps, COND_EXEC_TEST (x), insn); | |
2947 | ||
2948 | /* ??? Should be recording conditions so we reduce the number of | |
ff7cc307 | 2949 | false dependencies. */ |
16f6ece6 BS |
2950 | x = COND_EXEC_CODE (x); |
2951 | code = GET_CODE (x); | |
2952 | } | |
2953 | if (code == SET || code == CLOBBER) | |
c2310f51 RH |
2954 | { |
2955 | sched_analyze_1 (deps, x, insn); | |
2956 | ||
2957 | /* Bare clobber insns are used for letting life analysis, reg-stack | |
2958 | and others know that a value is dead. Depend on the last call | |
2959 | instruction so that reg-stack won't get confused. */ | |
2960 | if (code == CLOBBER) | |
ce18efcb | 2961 | add_dependence_list (insn, deps->last_function_call, 1, |
1a83e602 | 2962 | REG_DEP_OUTPUT, true); |
c2310f51 | 2963 | } |
16f6ece6 BS |
2964 | else if (code == PARALLEL) |
2965 | { | |
3cd8c58a | 2966 | for (i = XVECLEN (x, 0); i--;) |
16f6ece6 BS |
2967 | { |
2968 | rtx sub = XVECEXP (x, 0, i); | |
2969 | code = GET_CODE (sub); | |
2970 | ||
2971 | if (code == COND_EXEC) | |
2972 | { | |
2973 | sched_analyze_2 (deps, COND_EXEC_TEST (sub), insn); | |
2974 | sub = COND_EXEC_CODE (sub); | |
2975 | code = GET_CODE (sub); | |
2976 | } | |
2977 | if (code == SET || code == CLOBBER) | |
2978 | sched_analyze_1 (deps, sub, insn); | |
2979 | else | |
2980 | sched_analyze_2 (deps, sub, insn); | |
2981 | } | |
2982 | } | |
2983 | else | |
2984 | sched_analyze_2 (deps, x, insn); | |
2985 | ||
2986 | /* Mark registers CLOBBERED or used by called function. */ | |
4b4bf941 | 2987 | if (CALL_P (insn)) |
570a98eb JH |
2988 | { |
2989 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) | |
2990 | { | |
2991 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
2992 | sched_analyze_1 (deps, XEXP (link, 0), insn); | |
e384e6b5 | 2993 | else if (GET_CODE (XEXP (link, 0)) != SET) |
570a98eb JH |
2994 | sched_analyze_2 (deps, XEXP (link, 0), insn); |
2995 | } | |
9790c19e JJ |
2996 | /* Don't schedule anything after a tail call, tail call needs |
2997 | to use at least all call-saved registers. */ | |
2998 | if (SIBLING_CALL_P (insn)) | |
2999 | reg_pending_barrier = TRUE_BARRIER; | |
3000 | else if (find_reg_note (insn, REG_SETJMP, NULL)) | |
d1c9693e | 3001 | reg_pending_barrier = MOVE_BARRIER; |
570a98eb | 3002 | } |
16f6ece6 | 3003 | |
4b4bf941 | 3004 | if (JUMP_P (insn)) |
18e720b3 | 3005 | { |
79ba58ef | 3006 | rtx next; |
f0fc0803 | 3007 | next = next_nonnote_nondebug_insn (insn); |
4b4bf941 | 3008 | if (next && BARRIER_P (next)) |
0a1766b2 | 3009 | reg_pending_barrier = MOVE_BARRIER; |
18e720b3 BS |
3010 | else |
3011 | { | |
c838c402 DM |
3012 | rtx_insn_list *pending; |
3013 | rtx_expr_list *pending_mem; | |
5a257872 | 3014 | |
e855c69d AB |
3015 | if (sched_deps_info->compute_jump_reg_dependencies) |
3016 | { | |
e2724e63 BS |
3017 | (*sched_deps_info->compute_jump_reg_dependencies) |
3018 | (insn, reg_pending_control_uses); | |
e855c69d | 3019 | |
e855c69d | 3020 | /* Make latency of jump equal to 0 by using anti-dependence. */ |
e2724e63 | 3021 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_control_uses, 0, i, rsi) |
e855c69d AB |
3022 | { |
3023 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
1a83e602 BS |
3024 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_ANTI, |
3025 | false); | |
ce18efcb | 3026 | add_dependence_list (insn, reg_last->implicit_sets, |
1a83e602 | 3027 | 0, REG_DEP_ANTI, false); |
e855c69d | 3028 | add_dependence_list (insn, reg_last->clobbers, 0, |
1a83e602 | 3029 | REG_DEP_ANTI, false); |
e855c69d | 3030 | } |
e855c69d | 3031 | } |
79ba58ef | 3032 | |
d9214e53 RH |
3033 | /* All memory writes and volatile reads must happen before the |
3034 | jump. Non-volatile reads must happen before the jump iff | |
3035 | the result is needed by the above register used mask. */ | |
3036 | ||
79ba58ef BS |
3037 | pending = deps->pending_write_insns; |
3038 | pending_mem = deps->pending_write_mems; | |
3039 | while (pending) | |
3040 | { | |
c838c402 DM |
3041 | if (! sched_insns_conditions_mutex_p (insn, pending->insn ())) |
3042 | add_dependence (insn, pending->insn (), | |
ce1ce33a | 3043 | REG_DEP_OUTPUT); |
c838c402 DM |
3044 | pending = pending->next (); |
3045 | pending_mem = pending_mem->next (); | |
d9214e53 | 3046 | } |
79ba58ef | 3047 | |
d9214e53 RH |
3048 | pending = deps->pending_read_insns; |
3049 | pending_mem = deps->pending_read_mems; | |
3050 | while (pending) | |
3051 | { | |
c838c402 DM |
3052 | if (MEM_VOLATILE_P (pending_mem->element ()) |
3053 | && ! sched_insns_conditions_mutex_p (insn, pending->insn ())) | |
3054 | add_dependence (insn, pending->insn (), | |
ce1ce33a | 3055 | REG_DEP_OUTPUT); |
c838c402 DM |
3056 | pending = pending->next (); |
3057 | pending_mem = pending_mem->next (); | |
79ba58ef BS |
3058 | } |
3059 | ||
b27cedc6 | 3060 | add_dependence_list (insn, deps->last_pending_memory_flush, 1, |
1a83e602 | 3061 | REG_DEP_ANTI, true); |
e2724e63 | 3062 | add_dependence_list (insn, deps->pending_jump_insns, 1, |
1a83e602 | 3063 | REG_DEP_ANTI, true); |
18e720b3 | 3064 | } |
18e720b3 BS |
3065 | } |
3066 | ||
ca3c1028 | 3067 | /* If this instruction can throw an exception, then moving it changes |
786de7eb | 3068 | where block boundaries fall. This is mighty confusing elsewhere. |
d47a8b83 EB |
3069 | Therefore, prevent such an instruction from being moved. Same for |
3070 | non-jump instructions that define block boundaries. | |
3071 | ??? Unclear whether this is still necessary in EBB mode. If not, | |
3072 | add_branch_dependences should be adjusted for RGN mode instead. */ | |
3073 | if (((CALL_P (insn) || JUMP_P (insn)) && can_throw_internal (insn)) | |
3074 | || (NONJUMP_INSN_P (insn) && control_flow_insn_p (insn))) | |
d1c9693e | 3075 | reg_pending_barrier = MOVE_BARRIER; |
ca3c1028 | 3076 | |
7a1aca9c | 3077 | if (sched_pressure != SCHED_PRESSURE_NONE) |
ce18efcb VM |
3078 | { |
3079 | setup_insn_reg_uses (deps, insn); | |
19ac7892 | 3080 | init_insn_reg_pressure_info (insn); |
ce18efcb VM |
3081 | } |
3082 | ||
b5b8b0ac AO |
3083 | /* Add register dependencies for insn. */ |
3084 | if (DEBUG_INSN_P (insn)) | |
3085 | { | |
ce1ce33a | 3086 | rtx_insn *prev = deps->last_debug_insn; |
b5b8b0ac AO |
3087 | rtx u; |
3088 | ||
3089 | if (!deps->readonly) | |
3090 | deps->last_debug_insn = insn; | |
3091 | ||
3092 | if (prev) | |
3093 | add_dependence (insn, prev, REG_DEP_ANTI); | |
3094 | ||
3095 | add_dependence_list (insn, deps->last_function_call, 1, | |
1a83e602 | 3096 | REG_DEP_ANTI, false); |
b5b8b0ac | 3097 | |
1a83e602 BS |
3098 | if (!sel_sched_p ()) |
3099 | for (u = deps->last_pending_memory_flush; u; u = XEXP (u, 1)) | |
ce1ce33a | 3100 | add_dependence (insn, as_a <rtx_insn *> (XEXP (u, 0)), REG_DEP_ANTI); |
b5b8b0ac AO |
3101 | |
3102 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_uses, 0, i, rsi) | |
3103 | { | |
3104 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
1a83e602 | 3105 | add_dependence_list (insn, reg_last->sets, 1, REG_DEP_ANTI, false); |
e2724e63 BS |
3106 | /* There's no point in making REG_DEP_CONTROL dependencies for |
3107 | debug insns. */ | |
1a83e602 BS |
3108 | add_dependence_list (insn, reg_last->clobbers, 1, REG_DEP_ANTI, |
3109 | false); | |
f49b295a AO |
3110 | |
3111 | if (!deps->readonly) | |
3112 | reg_last->uses = alloc_INSN_LIST (insn, reg_last->uses); | |
b5b8b0ac AO |
3113 | } |
3114 | CLEAR_REG_SET (reg_pending_uses); | |
3115 | ||
3116 | /* Quite often, a debug insn will refer to stuff in the | |
3117 | previous instruction, but the reason we want this | |
3118 | dependency here is to make sure the scheduler doesn't | |
3119 | gratuitously move a debug insn ahead. This could dirty | |
3120 | DF flags and cause additional analysis that wouldn't have | |
3121 | occurred in compilation without debug insns, and such | |
3122 | additional analysis can modify the generated code. */ | |
3123 | prev = PREV_INSN (insn); | |
3124 | ||
3125 | if (prev && NONDEBUG_INSN_P (prev)) | |
3126 | add_dependence (insn, prev, REG_DEP_ANTI); | |
3127 | } | |
0a1766b2 AM |
3128 | else |
3129 | { | |
b0bd15f7 BS |
3130 | regset_head set_or_clobbered; |
3131 | ||
0a1766b2 | 3132 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_uses, 0, i, rsi) |
ce18efcb VM |
3133 | { |
3134 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
1a83e602 BS |
3135 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_TRUE, false); |
3136 | add_dependence_list (insn, reg_last->implicit_sets, 0, REG_DEP_ANTI, | |
3137 | false); | |
3138 | add_dependence_list (insn, reg_last->clobbers, 0, REG_DEP_TRUE, | |
3139 | false); | |
b8698a0f | 3140 | |
ce18efcb VM |
3141 | if (!deps->readonly) |
3142 | { | |
3143 | reg_last->uses = alloc_INSN_LIST (insn, reg_last->uses); | |
3144 | reg_last->uses_length++; | |
3145 | } | |
3146 | } | |
b8698a0f | 3147 | |
ce18efcb VM |
3148 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
3149 | if (TEST_HARD_REG_BIT (implicit_reg_pending_uses, i)) | |
3150 | { | |
3151 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
1a83e602 | 3152 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_TRUE, false); |
ce18efcb | 3153 | add_dependence_list (insn, reg_last->implicit_sets, 0, |
1a83e602 BS |
3154 | REG_DEP_ANTI, false); |
3155 | add_dependence_list (insn, reg_last->clobbers, 0, REG_DEP_TRUE, | |
3156 | false); | |
b8698a0f | 3157 | |
ce18efcb VM |
3158 | if (!deps->readonly) |
3159 | { | |
3160 | reg_last->uses = alloc_INSN_LIST (insn, reg_last->uses); | |
3161 | reg_last->uses_length++; | |
3162 | } | |
3163 | } | |
e855c69d | 3164 | |
b0bd15f7 BS |
3165 | if (targetm.sched.exposed_pipeline) |
3166 | { | |
3167 | INIT_REG_SET (&set_or_clobbered); | |
3168 | bitmap_ior (&set_or_clobbered, reg_pending_clobbers, | |
3169 | reg_pending_sets); | |
3170 | EXECUTE_IF_SET_IN_REG_SET (&set_or_clobbered, 0, i, rsi) | |
3171 | { | |
3172 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
3173 | rtx list; | |
3174 | for (list = reg_last->uses; list; list = XEXP (list, 1)) | |
3175 | { | |
3176 | rtx other = XEXP (list, 0); | |
f0898307 SG |
3177 | if (INSN_CACHED_COND (other) != const_true_rtx |
3178 | && refers_to_regno_p (i, i + 1, INSN_CACHED_COND (other), NULL)) | |
3179 | INSN_CACHED_COND (other) = const_true_rtx; | |
b0bd15f7 BS |
3180 | } |
3181 | } | |
3182 | } | |
3183 | ||
ce18efcb VM |
3184 | /* If the current insn is conditional, we can't free any |
3185 | of the lists. */ | |
3186 | if (sched_has_condition_p (insn)) | |
3187 | { | |
3188 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_clobbers, 0, i, rsi) | |
3189 | { | |
3190 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
1a83e602 BS |
3191 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_OUTPUT, |
3192 | false); | |
ce18efcb | 3193 | add_dependence_list (insn, reg_last->implicit_sets, 0, |
1a83e602 BS |
3194 | REG_DEP_ANTI, false); |
3195 | add_dependence_list (insn, reg_last->uses, 0, REG_DEP_ANTI, | |
3196 | false); | |
e2724e63 | 3197 | add_dependence_list (insn, reg_last->control_uses, 0, |
1a83e602 | 3198 | REG_DEP_CONTROL, false); |
b8698a0f | 3199 | |
ce18efcb VM |
3200 | if (!deps->readonly) |
3201 | { | |
3202 | reg_last->clobbers | |
3203 | = alloc_INSN_LIST (insn, reg_last->clobbers); | |
3204 | reg_last->clobbers_length++; | |
3205 | } | |
3206 | } | |
3207 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_sets, 0, i, rsi) | |
3208 | { | |
3209 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
1a83e602 BS |
3210 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_OUTPUT, |
3211 | false); | |
ce18efcb | 3212 | add_dependence_list (insn, reg_last->implicit_sets, 0, |
1a83e602 BS |
3213 | REG_DEP_ANTI, false); |
3214 | add_dependence_list (insn, reg_last->clobbers, 0, REG_DEP_OUTPUT, | |
3215 | false); | |
3216 | add_dependence_list (insn, reg_last->uses, 0, REG_DEP_ANTI, | |
3217 | false); | |
e2724e63 | 3218 | add_dependence_list (insn, reg_last->control_uses, 0, |
1a83e602 | 3219 | REG_DEP_CONTROL, false); |
b8698a0f | 3220 | |
ce18efcb | 3221 | if (!deps->readonly) |
aef0e7a8 | 3222 | reg_last->sets = alloc_INSN_LIST (insn, reg_last->sets); |
ce18efcb VM |
3223 | } |
3224 | } | |
3225 | else | |
3226 | { | |
3227 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_clobbers, 0, i, rsi) | |
3228 | { | |
3229 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
3230 | if (reg_last->uses_length > MAX_PENDING_LIST_LENGTH | |
3231 | || reg_last->clobbers_length > MAX_PENDING_LIST_LENGTH) | |
3232 | { | |
3233 | add_dependence_list_and_free (deps, insn, ®_last->sets, 0, | |
1a83e602 | 3234 | REG_DEP_OUTPUT, false); |
ce18efcb VM |
3235 | add_dependence_list_and_free (deps, insn, |
3236 | ®_last->implicit_sets, 0, | |
1a83e602 | 3237 | REG_DEP_ANTI, false); |
ce18efcb | 3238 | add_dependence_list_and_free (deps, insn, ®_last->uses, 0, |
1a83e602 | 3239 | REG_DEP_ANTI, false); |
e2724e63 BS |
3240 | add_dependence_list_and_free (deps, insn, |
3241 | ®_last->control_uses, 0, | |
1a83e602 BS |
3242 | REG_DEP_ANTI, false); |
3243 | add_dependence_list_and_free (deps, insn, | |
3244 | ®_last->clobbers, 0, | |
3245 | REG_DEP_OUTPUT, false); | |
b8698a0f | 3246 | |
ce18efcb VM |
3247 | if (!deps->readonly) |
3248 | { | |
3249 | reg_last->sets = alloc_INSN_LIST (insn, reg_last->sets); | |
3250 | reg_last->clobbers_length = 0; | |
3251 | reg_last->uses_length = 0; | |
3252 | } | |
3253 | } | |
3254 | else | |
3255 | { | |
1a83e602 BS |
3256 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_OUTPUT, |
3257 | false); | |
ce18efcb | 3258 | add_dependence_list (insn, reg_last->implicit_sets, 0, |
1a83e602 BS |
3259 | REG_DEP_ANTI, false); |
3260 | add_dependence_list (insn, reg_last->uses, 0, REG_DEP_ANTI, | |
3261 | false); | |
e2724e63 | 3262 | add_dependence_list (insn, reg_last->control_uses, 0, |
1a83e602 | 3263 | REG_DEP_CONTROL, false); |
ce18efcb | 3264 | } |
b8698a0f | 3265 | |
ce18efcb VM |
3266 | if (!deps->readonly) |
3267 | { | |
3268 | reg_last->clobbers_length++; | |
3269 | reg_last->clobbers | |
3270 | = alloc_INSN_LIST (insn, reg_last->clobbers); | |
3271 | } | |
3272 | } | |
3273 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_sets, 0, i, rsi) | |
3274 | { | |
3275 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
b8698a0f | 3276 | |
ce18efcb | 3277 | add_dependence_list_and_free (deps, insn, ®_last->sets, 0, |
1a83e602 | 3278 | REG_DEP_OUTPUT, false); |
ce18efcb VM |
3279 | add_dependence_list_and_free (deps, insn, |
3280 | ®_last->implicit_sets, | |
1a83e602 | 3281 | 0, REG_DEP_ANTI, false); |
ce18efcb | 3282 | add_dependence_list_and_free (deps, insn, ®_last->clobbers, 0, |
1a83e602 | 3283 | REG_DEP_OUTPUT, false); |
ce18efcb | 3284 | add_dependence_list_and_free (deps, insn, ®_last->uses, 0, |
1a83e602 | 3285 | REG_DEP_ANTI, false); |
e2724e63 | 3286 | add_dependence_list (insn, reg_last->control_uses, 0, |
1a83e602 | 3287 | REG_DEP_CONTROL, false); |
b8698a0f | 3288 | |
ce18efcb VM |
3289 | if (!deps->readonly) |
3290 | { | |
3291 | reg_last->sets = alloc_INSN_LIST (insn, reg_last->sets); | |
3292 | reg_last->uses_length = 0; | |
3293 | reg_last->clobbers_length = 0; | |
ce18efcb VM |
3294 | } |
3295 | } | |
3296 | } | |
e2724e63 BS |
3297 | if (!deps->readonly) |
3298 | { | |
3299 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_control_uses, 0, i, rsi) | |
3300 | { | |
3301 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
3302 | reg_last->control_uses | |
3303 | = alloc_INSN_LIST (insn, reg_last->control_uses); | |
3304 | } | |
3305 | } | |
0a1766b2 AM |
3306 | } |
3307 | ||
ce18efcb VM |
3308 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
3309 | if (TEST_HARD_REG_BIT (implicit_reg_pending_clobbers, i)) | |
3310 | { | |
3311 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
1a83e602 BS |
3312 | add_dependence_list (insn, reg_last->sets, 0, REG_DEP_ANTI, false); |
3313 | add_dependence_list (insn, reg_last->clobbers, 0, REG_DEP_ANTI, false); | |
3314 | add_dependence_list (insn, reg_last->uses, 0, REG_DEP_ANTI, false); | |
3315 | add_dependence_list (insn, reg_last->control_uses, 0, REG_DEP_ANTI, | |
3316 | false); | |
b8698a0f | 3317 | |
ce18efcb VM |
3318 | if (!deps->readonly) |
3319 | reg_last->implicit_sets | |
3320 | = alloc_INSN_LIST (insn, reg_last->implicit_sets); | |
3321 | } | |
3322 | ||
e855c69d AB |
3323 | if (!deps->readonly) |
3324 | { | |
3325 | IOR_REG_SET (&deps->reg_last_in_use, reg_pending_uses); | |
3326 | IOR_REG_SET (&deps->reg_last_in_use, reg_pending_clobbers); | |
3327 | IOR_REG_SET (&deps->reg_last_in_use, reg_pending_sets); | |
ce18efcb VM |
3328 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
3329 | if (TEST_HARD_REG_BIT (implicit_reg_pending_uses, i) | |
3330 | || TEST_HARD_REG_BIT (implicit_reg_pending_clobbers, i)) | |
3331 | SET_REGNO_REG_SET (&deps->reg_last_in_use, i); | |
e855c69d AB |
3332 | |
3333 | /* Set up the pending barrier found. */ | |
3334 | deps->last_reg_pending_barrier = reg_pending_barrier; | |
3335 | } | |
0a1766b2 AM |
3336 | |
3337 | CLEAR_REG_SET (reg_pending_uses); | |
3338 | CLEAR_REG_SET (reg_pending_clobbers); | |
3339 | CLEAR_REG_SET (reg_pending_sets); | |
e2724e63 | 3340 | CLEAR_REG_SET (reg_pending_control_uses); |
ce18efcb VM |
3341 | CLEAR_HARD_REG_SET (implicit_reg_pending_clobbers); |
3342 | CLEAR_HARD_REG_SET (implicit_reg_pending_uses); | |
0a1766b2 | 3343 | |
ca3c1028 | 3344 | /* Add dependencies if a scheduling barrier was found. */ |
37a0f8a5 | 3345 | if (reg_pending_barrier) |
ca3c1028 | 3346 | { |
30028c85 VM |
3347 | /* In the case of barrier the most added dependencies are not |
3348 | real, so we use anti-dependence here. */ | |
e855c69d | 3349 | if (sched_has_condition_p (insn)) |
16f6ece6 | 3350 | { |
a2041967 | 3351 | EXECUTE_IF_SET_IN_REG_SET (&deps->reg_last_in_use, 0, i, rsi) |
37a0f8a5 RH |
3352 | { |
3353 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
1a83e602 BS |
3354 | add_dependence_list (insn, reg_last->uses, 0, REG_DEP_ANTI, |
3355 | true); | |
ce18efcb VM |
3356 | add_dependence_list (insn, reg_last->sets, 0, |
3357 | reg_pending_barrier == TRUE_BARRIER | |
1a83e602 | 3358 | ? REG_DEP_TRUE : REG_DEP_ANTI, true); |
ce18efcb | 3359 | add_dependence_list (insn, reg_last->implicit_sets, 0, |
1a83e602 | 3360 | REG_DEP_ANTI, true); |
ce18efcb VM |
3361 | add_dependence_list (insn, reg_last->clobbers, 0, |
3362 | reg_pending_barrier == TRUE_BARRIER | |
1a83e602 | 3363 | ? REG_DEP_TRUE : REG_DEP_ANTI, true); |
a2041967 | 3364 | } |
37a0f8a5 RH |
3365 | } |
3366 | else | |
3367 | { | |
a2041967 | 3368 | EXECUTE_IF_SET_IN_REG_SET (&deps->reg_last_in_use, 0, i, rsi) |
37a0f8a5 RH |
3369 | { |
3370 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
e855c69d | 3371 | add_dependence_list_and_free (deps, insn, ®_last->uses, 0, |
1a83e602 | 3372 | REG_DEP_ANTI, true); |
e2724e63 BS |
3373 | add_dependence_list_and_free (deps, insn, |
3374 | ®_last->control_uses, 0, | |
1a83e602 | 3375 | REG_DEP_CONTROL, true); |
ce18efcb VM |
3376 | add_dependence_list_and_free (deps, insn, ®_last->sets, 0, |
3377 | reg_pending_barrier == TRUE_BARRIER | |
1a83e602 BS |
3378 | ? REG_DEP_TRUE : REG_DEP_ANTI, |
3379 | true); | |
ce18efcb VM |
3380 | add_dependence_list_and_free (deps, insn, |
3381 | ®_last->implicit_sets, 0, | |
1a83e602 | 3382 | REG_DEP_ANTI, true); |
ce18efcb VM |
3383 | add_dependence_list_and_free (deps, insn, ®_last->clobbers, 0, |
3384 | reg_pending_barrier == TRUE_BARRIER | |
1a83e602 BS |
3385 | ? REG_DEP_TRUE : REG_DEP_ANTI, |
3386 | true); | |
16f6ece6 | 3387 | |
e855c69d AB |
3388 | if (!deps->readonly) |
3389 | { | |
3390 | reg_last->uses_length = 0; | |
3391 | reg_last->clobbers_length = 0; | |
3392 | } | |
3393 | } | |
0a1bb917 | 3394 | } |
37a0f8a5 | 3395 | |
e855c69d AB |
3396 | if (!deps->readonly) |
3397 | for (i = 0; i < (unsigned)deps->max_reg; i++) | |
3398 | { | |
3399 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
3400 | reg_last->sets = alloc_INSN_LIST (insn, reg_last->sets); | |
3401 | SET_REGNO_REG_SET (&deps->reg_last_in_use, i); | |
3402 | } | |
3403 | ||
ed358aea | 3404 | /* Don't flush pending lists on speculative checks for |
f45e9053 AB |
3405 | selective scheduling. */ |
3406 | if (!sel_sched_p () || !sel_insn_is_speculation_check (insn)) | |
e855c69d | 3407 | flush_pending_lists (deps, insn, true, true); |
b8698a0f | 3408 | |
d1c9693e | 3409 | reg_pending_barrier = NOT_A_BARRIER; |
4ba478b8 | 3410 | } |
16f6ece6 BS |
3411 | |
3412 | /* If a post-call group is still open, see if it should remain so. | |
3413 | This insn must be a simple move of a hard reg to a pseudo or | |
3414 | vice-versa. | |
3415 | ||
42db504c SB |
3416 | We must avoid moving these insns for correctness on targets |
3417 | with small register classes, and for special registers like | |
16f6ece6 BS |
3418 | PIC_OFFSET_TABLE_REGNUM. For simplicity, extend this to all |
3419 | hard regs for all targets. */ | |
3420 | ||
3421 | if (deps->in_post_call_group_p) | |
3422 | { | |
3423 | rtx tmp, set = single_set (insn); | |
3424 | int src_regno, dest_regno; | |
3425 | ||
3426 | if (set == NULL) | |
b5b8b0ac AO |
3427 | { |
3428 | if (DEBUG_INSN_P (insn)) | |
3429 | /* We don't want to mark debug insns as part of the same | |
3430 | sched group. We know they really aren't, but if we use | |
3431 | debug insns to tell that a call group is over, we'll | |
3432 | get different code if debug insns are not there and | |
3433 | instructions that follow seem like they should be part | |
3434 | of the call group. | |
3435 | ||
fd59643c | 3436 | Also, if we did, chain_to_prev_insn would move the |
b5b8b0ac AO |
3437 | deps of the debug insn to the call insn, modifying |
3438 | non-debug post-dependency counts of the debug insn | |
3439 | dependencies and otherwise messing with the scheduling | |
3440 | order. | |
3441 | ||
3442 | Instead, let such debug insns be scheduled freely, but | |
3443 | keep the call group open in case there are insns that | |
3444 | should be part of it afterwards. Since we grant debug | |
3445 | insns higher priority than even sched group insns, it | |
3446 | will all turn out all right. */ | |
3447 | goto debug_dont_end_call_group; | |
3448 | else | |
3449 | goto end_call_group; | |
3450 | } | |
16f6ece6 BS |
3451 | |
3452 | tmp = SET_DEST (set); | |
3453 | if (GET_CODE (tmp) == SUBREG) | |
3454 | tmp = SUBREG_REG (tmp); | |
f8cfc6aa | 3455 | if (REG_P (tmp)) |
16f6ece6 BS |
3456 | dest_regno = REGNO (tmp); |
3457 | else | |
3458 | goto end_call_group; | |
3459 | ||
3460 | tmp = SET_SRC (set); | |
3461 | if (GET_CODE (tmp) == SUBREG) | |
3462 | tmp = SUBREG_REG (tmp); | |
58f206d6 DD |
3463 | if ((GET_CODE (tmp) == PLUS |
3464 | || GET_CODE (tmp) == MINUS) | |
f8cfc6aa | 3465 | && REG_P (XEXP (tmp, 0)) |
58f206d6 DD |
3466 | && REGNO (XEXP (tmp, 0)) == STACK_POINTER_REGNUM |
3467 | && dest_regno == STACK_POINTER_REGNUM) | |
3468 | src_regno = STACK_POINTER_REGNUM; | |
f8cfc6aa | 3469 | else if (REG_P (tmp)) |
16f6ece6 BS |
3470 | src_regno = REGNO (tmp); |
3471 | else | |
3472 | goto end_call_group; | |
3473 | ||
3474 | if (src_regno < FIRST_PSEUDO_REGISTER | |
3475 | || dest_regno < FIRST_PSEUDO_REGISTER) | |
3476 | { | |
e855c69d AB |
3477 | if (!deps->readonly |
3478 | && deps->in_post_call_group_p == post_call_initial) | |
4c2b2906 EC |
3479 | deps->in_post_call_group_p = post_call; |
3480 | ||
b8698a0f | 3481 | if (!sel_sched_p () || sched_emulate_haifa_p) |
e855c69d AB |
3482 | { |
3483 | SCHED_GROUP_P (insn) = 1; | |
3484 | CANT_MOVE (insn) = 1; | |
3485 | } | |
16f6ece6 BS |
3486 | } |
3487 | else | |
3488 | { | |
3489 | end_call_group: | |
e855c69d AB |
3490 | if (!deps->readonly) |
3491 | deps->in_post_call_group_p = not_post_call; | |
16f6ece6 BS |
3492 | } |
3493 | } | |
4c2b2906 | 3494 | |
b5b8b0ac | 3495 | debug_dont_end_call_group: |
e2f6ff94 MK |
3496 | if ((current_sched_info->flags & DO_SPECULATION) |
3497 | && !sched_insn_is_legitimate_for_speculation_p (insn, 0)) | |
3498 | /* INSN has an internal dependency (e.g. r14 = [r14]) and thus cannot | |
3499 | be speculated. */ | |
3500 | { | |
e855c69d AB |
3501 | if (sel_sched_p ()) |
3502 | sel_mark_hard_insn (insn); | |
3503 | else | |
3504 | { | |
3505 | sd_iterator_def sd_it; | |
3506 | dep_t dep; | |
b8698a0f | 3507 | |
e855c69d AB |
3508 | for (sd_it = sd_iterator_start (insn, SD_LIST_SPEC_BACK); |
3509 | sd_iterator_cond (&sd_it, &dep);) | |
3510 | change_spec_dep_to_hard (sd_it); | |
3511 | } | |
e2f6ff94 | 3512 | } |
76df831f RH |
3513 | |
3514 | /* We do not yet have code to adjust REG_ARGS_SIZE, therefore we must | |
3515 | honor their original ordering. */ | |
3516 | if (find_reg_note (insn, REG_ARGS_SIZE, NULL)) | |
3517 | { | |
3518 | if (deps->last_args_size) | |
3519 | add_dependence (insn, deps->last_args_size, REG_DEP_OUTPUT); | |
3520 | deps->last_args_size = insn; | |
3521 | } | |
16f6ece6 BS |
3522 | } |
3523 | ||
1098d3a5 JJ |
3524 | /* Return TRUE if INSN might not always return normally (e.g. call exit, |
3525 | longjmp, loop forever, ...). */ | |
532aafad SB |
3526 | /* FIXME: Why can't this function just use flags_from_decl_or_type and |
3527 | test for ECF_NORETURN? */ | |
1098d3a5 JJ |
3528 | static bool |
3529 | call_may_noreturn_p (rtx insn) | |
3530 | { | |
3531 | rtx call; | |
3532 | ||
3533 | /* const or pure calls that aren't looping will always return. */ | |
3534 | if (RTL_CONST_OR_PURE_CALL_P (insn) | |
3535 | && !RTL_LOOPING_CONST_OR_PURE_CALL_P (insn)) | |
3536 | return false; | |
3537 | ||
da4fdf2d SB |
3538 | call = get_call_rtx_from (insn); |
3539 | if (call && GET_CODE (XEXP (XEXP (call, 0), 0)) == SYMBOL_REF) | |
1098d3a5 JJ |
3540 | { |
3541 | rtx symbol = XEXP (XEXP (call, 0), 0); | |
3542 | if (SYMBOL_REF_DECL (symbol) | |
3543 | && TREE_CODE (SYMBOL_REF_DECL (symbol)) == FUNCTION_DECL) | |
3544 | { | |
3545 | if (DECL_BUILT_IN_CLASS (SYMBOL_REF_DECL (symbol)) | |
3546 | == BUILT_IN_NORMAL) | |
3547 | switch (DECL_FUNCTION_CODE (SYMBOL_REF_DECL (symbol))) | |
3548 | { | |
3549 | case BUILT_IN_BCMP: | |
3550 | case BUILT_IN_BCOPY: | |
3551 | case BUILT_IN_BZERO: | |
3552 | case BUILT_IN_INDEX: | |
3553 | case BUILT_IN_MEMCHR: | |
3554 | case BUILT_IN_MEMCMP: | |
3555 | case BUILT_IN_MEMCPY: | |
3556 | case BUILT_IN_MEMMOVE: | |
3557 | case BUILT_IN_MEMPCPY: | |
3558 | case BUILT_IN_MEMSET: | |
3559 | case BUILT_IN_RINDEX: | |
3560 | case BUILT_IN_STPCPY: | |
3561 | case BUILT_IN_STPNCPY: | |
3562 | case BUILT_IN_STRCAT: | |
3563 | case BUILT_IN_STRCHR: | |
3564 | case BUILT_IN_STRCMP: | |
3565 | case BUILT_IN_STRCPY: | |
3566 | case BUILT_IN_STRCSPN: | |
3567 | case BUILT_IN_STRLEN: | |
3568 | case BUILT_IN_STRNCAT: | |
3569 | case BUILT_IN_STRNCMP: | |
3570 | case BUILT_IN_STRNCPY: | |
3571 | case BUILT_IN_STRPBRK: | |
3572 | case BUILT_IN_STRRCHR: | |
3573 | case BUILT_IN_STRSPN: | |
3574 | case BUILT_IN_STRSTR: | |
3575 | /* Assume certain string/memory builtins always return. */ | |
3576 | return false; | |
3577 | default: | |
3578 | break; | |
3579 | } | |
3580 | } | |
3581 | } | |
3582 | ||
3583 | /* For all other calls assume that they might not always return. */ | |
3584 | return true; | |
3585 | } | |
3586 | ||
fd59643c RS |
3587 | /* Return true if INSN should be made dependent on the previous instruction |
3588 | group, and if all INSN's dependencies should be moved to the first | |
3589 | instruction of that group. */ | |
3590 | ||
3591 | static bool | |
3592 | chain_to_prev_insn_p (rtx insn) | |
3593 | { | |
3594 | rtx prev, x; | |
3595 | ||
3596 | /* INSN forms a group with the previous instruction. */ | |
3597 | if (SCHED_GROUP_P (insn)) | |
3598 | return true; | |
3599 | ||
3600 | /* If the previous instruction clobbers a register R and this one sets | |
3601 | part of R, the clobber was added specifically to help us track the | |
3602 | liveness of R. There's no point scheduling the clobber and leaving | |
3603 | INSN behind, especially if we move the clobber to another block. */ | |
3604 | prev = prev_nonnote_nondebug_insn (insn); | |
3605 | if (prev | |
3606 | && INSN_P (prev) | |
3607 | && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn) | |
3608 | && GET_CODE (PATTERN (prev)) == CLOBBER) | |
3609 | { | |
3610 | x = XEXP (PATTERN (prev), 0); | |
3611 | if (set_of (x, insn)) | |
3612 | return true; | |
3613 | } | |
3614 | ||
3615 | return false; | |
3616 | } | |
3617 | ||
e855c69d | 3618 | /* Analyze INSN with DEPS as a context. */ |
16f6ece6 | 3619 | void |
ce1ce33a | 3620 | deps_analyze_insn (struct deps_desc *deps, rtx_insn *insn) |
16f6ece6 | 3621 | { |
e855c69d AB |
3622 | if (sched_deps_info->start_insn) |
3623 | sched_deps_info->start_insn (insn); | |
16f6ece6 | 3624 | |
b0bd15f7 BS |
3625 | /* Record the condition for this insn. */ |
3626 | if (NONDEBUG_INSN_P (insn)) | |
e2724e63 BS |
3627 | { |
3628 | rtx t; | |
3629 | sched_get_condition_with_rev (insn, NULL); | |
3630 | t = INSN_CACHED_COND (insn); | |
3dc99c19 | 3631 | INSN_COND_DEPS (insn) = NULL; |
e2724e63 BS |
3632 | if (reload_completed |
3633 | && (current_sched_info->flags & DO_PREDICATION) | |
3634 | && COMPARISON_P (t) | |
3635 | && REG_P (XEXP (t, 0)) | |
3636 | && CONSTANT_P (XEXP (t, 1))) | |
3637 | { | |
3638 | unsigned int regno; | |
3639 | int nregs; | |
3dc99c19 | 3640 | rtx_insn_list *cond_deps = NULL; |
e2724e63 BS |
3641 | t = XEXP (t, 0); |
3642 | regno = REGNO (t); | |
3643 | nregs = hard_regno_nregs[regno][GET_MODE (t)]; | |
e2724e63 BS |
3644 | while (nregs-- > 0) |
3645 | { | |
3646 | struct deps_reg *reg_last = &deps->reg_last[regno + nregs]; | |
3dc99c19 DM |
3647 | cond_deps = concat_INSN_LIST (reg_last->sets, cond_deps); |
3648 | cond_deps = concat_INSN_LIST (reg_last->clobbers, cond_deps); | |
3649 | cond_deps = concat_INSN_LIST (reg_last->implicit_sets, cond_deps); | |
e2724e63 | 3650 | } |
3dc99c19 | 3651 | INSN_COND_DEPS (insn) = cond_deps; |
e2724e63 BS |
3652 | } |
3653 | } | |
b0bd15f7 | 3654 | |
7b4ef662 | 3655 | if (JUMP_P (insn)) |
e855c69d | 3656 | { |
b8698a0f | 3657 | /* Make each JUMP_INSN (but not a speculative check) |
e855c69d AB |
3658 | a scheduling barrier for memory references. */ |
3659 | if (!deps->readonly | |
b8698a0f | 3660 | && !(sel_sched_p () |
e855c69d AB |
3661 | && sel_insn_is_speculation_check (insn))) |
3662 | { | |
3663 | /* Keep the list a reasonable size. */ | |
3664 | if (deps->pending_flush_length++ > MAX_PENDING_LIST_LENGTH) | |
3665 | flush_pending_lists (deps, insn, true, true); | |
3666 | else | |
e2724e63 BS |
3667 | deps->pending_jump_insns |
3668 | = alloc_INSN_LIST (insn, deps->pending_jump_insns); | |
e855c69d AB |
3669 | } |
3670 | ||
7b4ef662 RH |
3671 | /* For each insn which shouldn't cross a jump, add a dependence. */ |
3672 | add_dependence_list_and_free (deps, insn, | |
3673 | &deps->sched_before_next_jump, 1, | |
1a83e602 | 3674 | REG_DEP_ANTI, true); |
7b4ef662 RH |
3675 | |
3676 | sched_analyze_insn (deps, PATTERN (insn), insn); | |
3677 | } | |
3678 | else if (NONJUMP_INSN_P (insn) || DEBUG_INSN_P (insn)) | |
3679 | { | |
e855c69d AB |
3680 | sched_analyze_insn (deps, PATTERN (insn), insn); |
3681 | } | |
3682 | else if (CALL_P (insn)) | |
3683 | { | |
3684 | int i; | |
3685 | ||
3686 | CANT_MOVE (insn) = 1; | |
3687 | ||
3688 | if (find_reg_note (insn, REG_SETJMP, NULL)) | |
3689 | { | |
3690 | /* This is setjmp. Assume that all registers, not just | |
3691 | hard registers, may be clobbered by this call. */ | |
3692 | reg_pending_barrier = MOVE_BARRIER; | |
3693 | } | |
3694 | else | |
3695 | { | |
3696 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3697 | /* A call may read and modify global register variables. */ | |
3698 | if (global_regs[i]) | |
3699 | { | |
3700 | SET_REGNO_REG_SET (reg_pending_sets, i); | |
ce18efcb | 3701 | SET_HARD_REG_BIT (implicit_reg_pending_uses, i); |
e855c69d AB |
3702 | } |
3703 | /* Other call-clobbered hard regs may be clobbered. | |
3704 | Since we only have a choice between 'might be clobbered' | |
3705 | and 'definitely not clobbered', we must include all | |
3706 | partly call-clobbered registers here. */ | |
3707 | else if (HARD_REGNO_CALL_PART_CLOBBERED (i, reg_raw_mode[i]) | |
3708 | || TEST_HARD_REG_BIT (regs_invalidated_by_call, i)) | |
3709 | SET_REGNO_REG_SET (reg_pending_clobbers, i); | |
3710 | /* We don't know what set of fixed registers might be used | |
3711 | by the function, but it is certain that the stack pointer | |
3712 | is among them, but be conservative. */ | |
3713 | else if (fixed_regs[i]) | |
ce18efcb | 3714 | SET_HARD_REG_BIT (implicit_reg_pending_uses, i); |
e855c69d AB |
3715 | /* The frame pointer is normally not used by the function |
3716 | itself, but by the debugger. */ | |
3717 | /* ??? MIPS o32 is an exception. It uses the frame pointer | |
3718 | in the macro expansion of jal but does not represent this | |
3719 | fact in the call_insn rtl. */ | |
3720 | else if (i == FRAME_POINTER_REGNUM | |
3721 | || (i == HARD_FRAME_POINTER_REGNUM | |
3722 | && (! reload_completed || frame_pointer_needed))) | |
ce18efcb | 3723 | SET_HARD_REG_BIT (implicit_reg_pending_uses, i); |
e855c69d AB |
3724 | } |
3725 | ||
3726 | /* For each insn which shouldn't cross a call, add a dependence | |
3727 | between that insn and this call insn. */ | |
b8698a0f | 3728 | add_dependence_list_and_free (deps, insn, |
e855c69d | 3729 | &deps->sched_before_next_call, 1, |
1a83e602 | 3730 | REG_DEP_ANTI, true); |
e855c69d AB |
3731 | |
3732 | sched_analyze_insn (deps, PATTERN (insn), insn); | |
3733 | ||
3734 | /* If CALL would be in a sched group, then this will violate | |
3735 | convention that sched group insns have dependencies only on the | |
3736 | previous instruction. | |
3737 | ||
3738 | Of course one can say: "Hey! What about head of the sched group?" | |
3739 | And I will answer: "Basic principles (one dep per insn) are always | |
3740 | the same." */ | |
3741 | gcc_assert (!SCHED_GROUP_P (insn)); | |
3742 | ||
3743 | /* In the absence of interprocedural alias analysis, we must flush | |
3744 | all pending reads and writes, and start new dependencies starting | |
3745 | from here. But only flush writes for constant calls (which may | |
3746 | be passed a pointer to something we haven't written yet). */ | |
3747 | flush_pending_lists (deps, insn, true, ! RTL_CONST_OR_PURE_CALL_P (insn)); | |
3748 | ||
3749 | if (!deps->readonly) | |
3750 | { | |
3751 | /* Remember the last function call for limiting lifetimes. */ | |
3752 | free_INSN_LIST_list (&deps->last_function_call); | |
3753 | deps->last_function_call = alloc_INSN_LIST (insn, NULL_RTX); | |
1098d3a5 JJ |
3754 | |
3755 | if (call_may_noreturn_p (insn)) | |
3756 | { | |
3757 | /* Remember the last function call that might not always return | |
3758 | normally for limiting moves of trapping insns. */ | |
3759 | free_INSN_LIST_list (&deps->last_function_call_may_noreturn); | |
3760 | deps->last_function_call_may_noreturn | |
3761 | = alloc_INSN_LIST (insn, NULL_RTX); | |
3762 | } | |
3763 | ||
e855c69d AB |
3764 | /* Before reload, begin a post-call group, so as to keep the |
3765 | lifetimes of hard registers correct. */ | |
3766 | if (! reload_completed) | |
3767 | deps->in_post_call_group_p = post_call; | |
3768 | } | |
3769 | } | |
3770 | ||
3771 | if (sched_deps_info->use_cselib) | |
3772 | cselib_process_insn (insn); | |
3773 | ||
e855c69d AB |
3774 | if (sched_deps_info->finish_insn) |
3775 | sched_deps_info->finish_insn (); | |
3776 | ||
3777 | /* Fixup the dependencies in the sched group. */ | |
b8698a0f | 3778 | if ((NONJUMP_INSN_P (insn) || JUMP_P (insn)) |
fd59643c RS |
3779 | && chain_to_prev_insn_p (insn) |
3780 | && !sel_sched_p ()) | |
3781 | chain_to_prev_insn (insn); | |
e855c69d AB |
3782 | } |
3783 | ||
3784 | /* Initialize DEPS for the new block beginning with HEAD. */ | |
3785 | void | |
99de8612 | 3786 | deps_start_bb (struct deps_desc *deps, rtx_insn *head) |
e855c69d AB |
3787 | { |
3788 | gcc_assert (!deps->readonly); | |
4b6c5340 | 3789 | |
b40742a5 R |
3790 | /* Before reload, if the previous block ended in a call, show that |
3791 | we are inside a post-call group, so as to keep the lifetimes of | |
3792 | hard registers correct. */ | |
4b4bf941 | 3793 | if (! reload_completed && !LABEL_P (head)) |
b40742a5 | 3794 | { |
99de8612 | 3795 | rtx_insn *insn = prev_nonnote_nondebug_insn (head); |
e855c69d | 3796 | |
4b4bf941 | 3797 | if (insn && CALL_P (insn)) |
b40742a5 R |
3798 | deps->in_post_call_group_p = post_call_initial; |
3799 | } | |
e855c69d AB |
3800 | } |
3801 | ||
3802 | /* Analyze every insn between HEAD and TAIL inclusive, creating backward | |
3803 | dependencies for each insn. */ | |
3804 | void | |
ce1ce33a | 3805 | sched_analyze (struct deps_desc *deps, rtx_insn *head, rtx_insn *tail) |
e855c69d | 3806 | { |
ce1ce33a | 3807 | rtx_insn *insn; |
e855c69d AB |
3808 | |
3809 | if (sched_deps_info->use_cselib) | |
457eeaae | 3810 | cselib_init (CSELIB_RECORD_MEMORY); |
e855c69d AB |
3811 | |
3812 | deps_start_bb (deps, head); | |
3813 | ||
16f6ece6 BS |
3814 | for (insn = head;; insn = NEXT_INSN (insn)) |
3815 | { | |
e855c69d | 3816 | |
b198261f | 3817 | if (INSN_P (insn)) |
16f6ece6 | 3818 | { |
e2f6ff94 MK |
3819 | /* And initialize deps_lists. */ |
3820 | sd_init_insn (insn); | |
ba4fa581 WM |
3821 | /* Clean up SCHED_GROUP_P which may be set by last |
3822 | scheduler pass. */ | |
3823 | if (SCHED_GROUP_P (insn)) | |
3824 | SCHED_GROUP_P (insn) = 0; | |
b198261f MK |
3825 | } |
3826 | ||
e855c69d | 3827 | deps_analyze_insn (deps, insn); |
85d69216 | 3828 | |
16f6ece6 | 3829 | if (insn == tail) |
4b6c5340 | 3830 | { |
e855c69d | 3831 | if (sched_deps_info->use_cselib) |
4b6c5340 BS |
3832 | cselib_finish (); |
3833 | return; | |
3834 | } | |
16f6ece6 | 3835 | } |
41374e13 | 3836 | gcc_unreachable (); |
16f6ece6 | 3837 | } |
15aab9c0 | 3838 | |
e2f6ff94 MK |
3839 | /* Helper for sched_free_deps (). |
3840 | Delete INSN's (RESOLVED_P) backward dependencies. */ | |
3841 | static void | |
3842 | delete_dep_nodes_in_back_deps (rtx insn, bool resolved_p) | |
15aab9c0 | 3843 | { |
e2f6ff94 MK |
3844 | sd_iterator_def sd_it; |
3845 | dep_t dep; | |
3846 | sd_list_types_def types; | |
15aab9c0 | 3847 | |
e2f6ff94 MK |
3848 | if (resolved_p) |
3849 | types = SD_LIST_RES_BACK; | |
3850 | else | |
3851 | types = SD_LIST_BACK; | |
3852 | ||
3853 | for (sd_it = sd_iterator_start (insn, types); | |
3854 | sd_iterator_cond (&sd_it, &dep);) | |
ddbd5439 | 3855 | { |
e2f6ff94 MK |
3856 | dep_link_t link = *sd_it.linkp; |
3857 | dep_node_t node = DEP_LINK_NODE (link); | |
3858 | deps_list_t back_list; | |
3859 | deps_list_t forw_list; | |
3860 | ||
3861 | get_back_and_forw_lists (dep, resolved_p, &back_list, &forw_list); | |
3862 | remove_from_deps_list (link, back_list); | |
3863 | delete_dep_node (node); | |
ddbd5439 | 3864 | } |
15aab9c0 VM |
3865 | } |
3866 | ||
e2f6ff94 MK |
3867 | /* Delete (RESOLVED_P) dependencies between HEAD and TAIL together with |
3868 | deps_lists. */ | |
16f6ece6 | 3869 | void |
dc01c3d1 | 3870 | sched_free_deps (rtx_insn *head, rtx_insn *tail, bool resolved_p) |
16f6ece6 | 3871 | { |
dc01c3d1 DM |
3872 | rtx_insn *insn; |
3873 | rtx_insn *next_tail = NEXT_INSN (tail); | |
16f6ece6 | 3874 | |
b953c2b8 BS |
3875 | /* We make two passes since some insns may be scheduled before their |
3876 | dependencies are resolved. */ | |
16f6ece6 | 3877 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) |
e2f6ff94 MK |
3878 | if (INSN_P (insn) && INSN_LUID (insn) > 0) |
3879 | { | |
e2f6ff94 MK |
3880 | /* Clear forward deps and leave the dep_nodes to the |
3881 | corresponding back_deps list. */ | |
3882 | if (resolved_p) | |
3883 | clear_deps_list (INSN_RESOLVED_FORW_DEPS (insn)); | |
3884 | else | |
3885 | clear_deps_list (INSN_FORW_DEPS (insn)); | |
b953c2b8 BS |
3886 | } |
3887 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
3888 | if (INSN_P (insn) && INSN_LUID (insn) > 0) | |
3889 | { | |
3890 | /* Clear resolved back deps together with its dep_nodes. */ | |
3891 | delete_dep_nodes_in_back_deps (insn, resolved_p); | |
16f6ece6 | 3892 | |
e2f6ff94 MK |
3893 | sd_finish_insn (insn); |
3894 | } | |
16f6ece6 BS |
3895 | } |
3896 | \f | |
3897 | /* Initialize variables for region data dependence analysis. | |
b8698a0f | 3898 | When LAZY_REG_LAST is true, do not allocate reg_last array |
88302d54 | 3899 | of struct deps_desc immediately. */ |
16f6ece6 BS |
3900 | |
3901 | void | |
88302d54 | 3902 | init_deps (struct deps_desc *deps, bool lazy_reg_last) |
16f6ece6 | 3903 | { |
4ba478b8 RH |
3904 | int max_reg = (reload_completed ? FIRST_PSEUDO_REGISTER : max_reg_num ()); |
3905 | ||
3906 | deps->max_reg = max_reg; | |
bcf33775 AB |
3907 | if (lazy_reg_last) |
3908 | deps->reg_last = NULL; | |
3909 | else | |
3910 | deps->reg_last = XCNEWVEC (struct deps_reg, max_reg); | |
4ba478b8 | 3911 | INIT_REG_SET (&deps->reg_last_in_use); |
16f6ece6 BS |
3912 | |
3913 | deps->pending_read_insns = 0; | |
3914 | deps->pending_read_mems = 0; | |
3915 | deps->pending_write_insns = 0; | |
3916 | deps->pending_write_mems = 0; | |
e2724e63 | 3917 | deps->pending_jump_insns = 0; |
bdbf40a5 MK |
3918 | deps->pending_read_list_length = 0; |
3919 | deps->pending_write_list_length = 0; | |
4a121cc3 | 3920 | deps->pending_flush_length = 0; |
16f6ece6 BS |
3921 | deps->last_pending_memory_flush = 0; |
3922 | deps->last_function_call = 0; | |
1098d3a5 | 3923 | deps->last_function_call_may_noreturn = 0; |
37a0f8a5 | 3924 | deps->sched_before_next_call = 0; |
7b4ef662 | 3925 | deps->sched_before_next_jump = 0; |
b40742a5 | 3926 | deps->in_post_call_group_p = not_post_call; |
b5b8b0ac | 3927 | deps->last_debug_insn = 0; |
76df831f | 3928 | deps->last_args_size = 0; |
e855c69d AB |
3929 | deps->last_reg_pending_barrier = NOT_A_BARRIER; |
3930 | deps->readonly = 0; | |
16f6ece6 BS |
3931 | } |
3932 | ||
b8698a0f | 3933 | /* Init only reg_last field of DEPS, which was not allocated before as |
bcf33775 AB |
3934 | we inited DEPS lazily. */ |
3935 | void | |
88302d54 | 3936 | init_deps_reg_last (struct deps_desc *deps) |
bcf33775 AB |
3937 | { |
3938 | gcc_assert (deps && deps->max_reg > 0); | |
3939 | gcc_assert (deps->reg_last == NULL); | |
3940 | ||
3941 | deps->reg_last = XCNEWVEC (struct deps_reg, deps->max_reg); | |
3942 | } | |
3943 | ||
3944 | ||
16f6ece6 BS |
3945 | /* Free insn lists found in DEPS. */ |
3946 | ||
3947 | void | |
88302d54 | 3948 | free_deps (struct deps_desc *deps) |
16f6ece6 | 3949 | { |
3cd8c58a | 3950 | unsigned i; |
a2041967 | 3951 | reg_set_iterator rsi; |
16f6ece6 | 3952 | |
bcf33775 AB |
3953 | /* We set max_reg to 0 when this context was already freed. */ |
3954 | if (deps->max_reg == 0) | |
3955 | { | |
3956 | gcc_assert (deps->reg_last == NULL); | |
3957 | return; | |
3958 | } | |
3959 | deps->max_reg = 0; | |
b8698a0f | 3960 | |
37a0f8a5 RH |
3961 | free_INSN_LIST_list (&deps->pending_read_insns); |
3962 | free_EXPR_LIST_list (&deps->pending_read_mems); | |
3963 | free_INSN_LIST_list (&deps->pending_write_insns); | |
3964 | free_EXPR_LIST_list (&deps->pending_write_mems); | |
3965 | free_INSN_LIST_list (&deps->last_pending_memory_flush); | |
3966 | ||
4ba478b8 | 3967 | /* Without the EXECUTE_IF_SET, this loop is executed max_reg * nr_regions |
7ef0daad | 3968 | times. For a testcase with 42000 regs and 8000 small basic blocks, |
4ba478b8 | 3969 | this loop accounted for nearly 60% (84 sec) of the total -O2 runtime. */ |
a2041967 | 3970 | EXECUTE_IF_SET_IN_REG_SET (&deps->reg_last_in_use, 0, i, rsi) |
16f6ece6 | 3971 | { |
4ba478b8 | 3972 | struct deps_reg *reg_last = &deps->reg_last[i]; |
f2846820 JL |
3973 | if (reg_last->uses) |
3974 | free_INSN_LIST_list (®_last->uses); | |
3975 | if (reg_last->sets) | |
3976 | free_INSN_LIST_list (®_last->sets); | |
ce18efcb VM |
3977 | if (reg_last->implicit_sets) |
3978 | free_INSN_LIST_list (®_last->implicit_sets); | |
e2724e63 BS |
3979 | if (reg_last->control_uses) |
3980 | free_INSN_LIST_list (®_last->control_uses); | |
f2846820 JL |
3981 | if (reg_last->clobbers) |
3982 | free_INSN_LIST_list (®_last->clobbers); | |
a2041967 | 3983 | } |
4ba478b8 RH |
3984 | CLEAR_REG_SET (&deps->reg_last_in_use); |
3985 | ||
b8698a0f | 3986 | /* As we initialize reg_last lazily, it is possible that we didn't allocate |
bcf33775 | 3987 | it at all. */ |
04695783 | 3988 | free (deps->reg_last); |
e855c69d AB |
3989 | deps->reg_last = NULL; |
3990 | ||
3991 | deps = NULL; | |
16f6ece6 BS |
3992 | } |
3993 | ||
aef0e7a8 | 3994 | /* Remove INSN from dependence contexts DEPS. */ |
e855c69d | 3995 | void |
3dc99c19 | 3996 | remove_from_deps (struct deps_desc *deps, rtx_insn *insn) |
e855c69d AB |
3997 | { |
3998 | int removed; | |
3999 | unsigned i; | |
4000 | reg_set_iterator rsi; | |
b8698a0f | 4001 | |
e855c69d AB |
4002 | removed = remove_from_both_dependence_lists (insn, &deps->pending_read_insns, |
4003 | &deps->pending_read_mems); | |
f49b295a AO |
4004 | if (!DEBUG_INSN_P (insn)) |
4005 | deps->pending_read_list_length -= removed; | |
e855c69d AB |
4006 | removed = remove_from_both_dependence_lists (insn, &deps->pending_write_insns, |
4007 | &deps->pending_write_mems); | |
4008 | deps->pending_write_list_length -= removed; | |
e2724e63 BS |
4009 | |
4010 | removed = remove_from_dependence_list (insn, &deps->pending_jump_insns); | |
4011 | deps->pending_flush_length -= removed; | |
e855c69d AB |
4012 | removed = remove_from_dependence_list (insn, &deps->last_pending_memory_flush); |
4013 | deps->pending_flush_length -= removed; | |
16f6ece6 | 4014 | |
e855c69d AB |
4015 | EXECUTE_IF_SET_IN_REG_SET (&deps->reg_last_in_use, 0, i, rsi) |
4016 | { | |
4017 | struct deps_reg *reg_last = &deps->reg_last[i]; | |
4018 | if (reg_last->uses) | |
4019 | remove_from_dependence_list (insn, ®_last->uses); | |
4020 | if (reg_last->sets) | |
4021 | remove_from_dependence_list (insn, ®_last->sets); | |
ce18efcb VM |
4022 | if (reg_last->implicit_sets) |
4023 | remove_from_dependence_list (insn, ®_last->implicit_sets); | |
e855c69d AB |
4024 | if (reg_last->clobbers) |
4025 | remove_from_dependence_list (insn, ®_last->clobbers); | |
ce18efcb VM |
4026 | if (!reg_last->uses && !reg_last->sets && !reg_last->implicit_sets |
4027 | && !reg_last->clobbers) | |
e855c69d AB |
4028 | CLEAR_REGNO_REG_SET (&deps->reg_last_in_use, i); |
4029 | } | |
4030 | ||
4031 | if (CALL_P (insn)) | |
1098d3a5 JJ |
4032 | { |
4033 | remove_from_dependence_list (insn, &deps->last_function_call); | |
b8698a0f | 4034 | remove_from_dependence_list (insn, |
1098d3a5 JJ |
4035 | &deps->last_function_call_may_noreturn); |
4036 | } | |
e855c69d AB |
4037 | remove_from_dependence_list (insn, &deps->sched_before_next_call); |
4038 | } | |
4039 | ||
4040 | /* Init deps data vector. */ | |
4041 | static void | |
4042 | init_deps_data_vector (void) | |
4043 | { | |
9771b263 DN |
4044 | int reserve = (sched_max_luid + 1 - h_d_i_d.length ()); |
4045 | if (reserve > 0 && ! h_d_i_d.space (reserve)) | |
4046 | h_d_i_d.safe_grow_cleared (3 * sched_max_luid / 2); | |
e855c69d AB |
4047 | } |
4048 | ||
4049 | /* If it is profitable to use them, initialize or extend (depending on | |
4050 | GLOBAL_P) dependency data. */ | |
16f6ece6 | 4051 | void |
e855c69d | 4052 | sched_deps_init (bool global_p) |
16f6ece6 | 4053 | { |
e2f6ff94 MK |
4054 | /* Average number of insns in the basic block. |
4055 | '+ 1' is used to make it nonzero. */ | |
0cae8d31 | 4056 | int insns_in_block = sched_max_luid / n_basic_blocks_for_fn (cfun) + 1; |
e2f6ff94 | 4057 | |
e855c69d | 4058 | init_deps_data_vector (); |
b8698a0f L |
4059 | |
4060 | /* We use another caching mechanism for selective scheduling, so | |
e855c69d AB |
4061 | we don't use this one. */ |
4062 | if (!sel_sched_p () && global_p && insns_in_block > 100 * 5) | |
4063 | { | |
4064 | /* ?!? We could save some memory by computing a per-region luid mapping | |
4065 | which could reduce both the number of vectors in the cache and the | |
4066 | size of each vector. Instead we just avoid the cache entirely unless | |
4067 | the average number of instructions in a basic block is very high. See | |
4068 | the comment before the declaration of true_dependency_cache for | |
4069 | what we consider "very high". */ | |
496d7bb0 | 4070 | cache_size = 0; |
e855c69d | 4071 | extend_dependency_caches (sched_max_luid, true); |
496d7bb0 | 4072 | } |
b198261f | 4073 | |
b8698a0f | 4074 | if (global_p) |
e855c69d AB |
4075 | { |
4076 | dl_pool = create_alloc_pool ("deps_list", sizeof (struct _deps_list), | |
4077 | /* Allocate lists for one block at a time. */ | |
4078 | insns_in_block); | |
4079 | dn_pool = create_alloc_pool ("dep_node", sizeof (struct _dep_node), | |
4080 | /* Allocate nodes for one block at a time. | |
4081 | We assume that average insn has | |
4082 | 5 producers. */ | |
4083 | 5 * insns_in_block); | |
4084 | } | |
496d7bb0 | 4085 | } |
ddbd5439 | 4086 | |
e855c69d | 4087 | |
496d7bb0 MK |
4088 | /* Create or extend (depending on CREATE_P) dependency caches to |
4089 | size N. */ | |
4090 | void | |
4091 | extend_dependency_caches (int n, bool create_p) | |
4092 | { | |
4093 | if (create_p || true_dependency_cache) | |
4094 | { | |
4095 | int i, luid = cache_size + n; | |
4096 | ||
4097 | true_dependency_cache = XRESIZEVEC (bitmap_head, true_dependency_cache, | |
4098 | luid); | |
4099 | output_dependency_cache = XRESIZEVEC (bitmap_head, | |
4100 | output_dependency_cache, luid); | |
4101 | anti_dependency_cache = XRESIZEVEC (bitmap_head, anti_dependency_cache, | |
4102 | luid); | |
e2724e63 BS |
4103 | control_dependency_cache = XRESIZEVEC (bitmap_head, control_dependency_cache, |
4104 | luid); | |
e2f6ff94 | 4105 | |
ddbd5439 MK |
4106 | if (current_sched_info->flags & DO_SPECULATION) |
4107 | spec_dependency_cache = XRESIZEVEC (bitmap_head, spec_dependency_cache, | |
4108 | luid); | |
4109 | ||
496d7bb0 | 4110 | for (i = cache_size; i < luid; i++) |
84568e14 JH |
4111 | { |
4112 | bitmap_initialize (&true_dependency_cache[i], 0); | |
84568e14 | 4113 | bitmap_initialize (&output_dependency_cache[i], 0); |
ddbd5439 | 4114 | bitmap_initialize (&anti_dependency_cache[i], 0); |
e2724e63 | 4115 | bitmap_initialize (&control_dependency_cache[i], 0); |
e2f6ff94 | 4116 | |
ddbd5439 MK |
4117 | if (current_sched_info->flags & DO_SPECULATION) |
4118 | bitmap_initialize (&spec_dependency_cache[i], 0); | |
84568e14 JH |
4119 | } |
4120 | cache_size = luid; | |
16f6ece6 BS |
4121 | } |
4122 | } | |
4123 | ||
e855c69d | 4124 | /* Finalize dependency information for the whole function. */ |
16f6ece6 | 4125 | void |
e855c69d | 4126 | sched_deps_finish (void) |
16f6ece6 | 4127 | { |
e2f6ff94 MK |
4128 | gcc_assert (deps_pools_are_empty_p ()); |
4129 | free_alloc_pool_if_empty (&dn_pool); | |
4130 | free_alloc_pool_if_empty (&dl_pool); | |
4131 | gcc_assert (dn_pool == NULL && dl_pool == NULL); | |
b198261f | 4132 | |
9771b263 | 4133 | h_d_i_d.release (); |
e855c69d | 4134 | cache_size = 0; |
b8698a0f | 4135 | |
16f6ece6 BS |
4136 | if (true_dependency_cache) |
4137 | { | |
84568e14 JH |
4138 | int i; |
4139 | ||
4140 | for (i = 0; i < cache_size; i++) | |
4141 | { | |
4142 | bitmap_clear (&true_dependency_cache[i]); | |
84568e14 | 4143 | bitmap_clear (&output_dependency_cache[i]); |
ddbd5439 | 4144 | bitmap_clear (&anti_dependency_cache[i]); |
e2724e63 | 4145 | bitmap_clear (&control_dependency_cache[i]); |
e2f6ff94 | 4146 | |
e855c69d | 4147 | if (sched_deps_info->generate_spec_deps) |
ddbd5439 | 4148 | bitmap_clear (&spec_dependency_cache[i]); |
84568e14 JH |
4149 | } |
4150 | free (true_dependency_cache); | |
16f6ece6 | 4151 | true_dependency_cache = NULL; |
84568e14 | 4152 | free (output_dependency_cache); |
16f6ece6 | 4153 | output_dependency_cache = NULL; |
ddbd5439 MK |
4154 | free (anti_dependency_cache); |
4155 | anti_dependency_cache = NULL; | |
e2724e63 BS |
4156 | free (control_dependency_cache); |
4157 | control_dependency_cache = NULL; | |
e2f6ff94 | 4158 | |
e855c69d | 4159 | if (sched_deps_info->generate_spec_deps) |
ddbd5439 MK |
4160 | { |
4161 | free (spec_dependency_cache); | |
4162 | spec_dependency_cache = NULL; | |
4163 | } | |
e855c69d | 4164 | |
16f6ece6 BS |
4165 | } |
4166 | } | |
4167 | ||
4168 | /* Initialize some global variables needed by the dependency analysis | |
4169 | code. */ | |
4170 | ||
4171 | void | |
46c5ad27 | 4172 | init_deps_global (void) |
16f6ece6 | 4173 | { |
ce18efcb VM |
4174 | CLEAR_HARD_REG_SET (implicit_reg_pending_clobbers); |
4175 | CLEAR_HARD_REG_SET (implicit_reg_pending_uses); | |
04389919 NS |
4176 | reg_pending_sets = ALLOC_REG_SET (®_obstack); |
4177 | reg_pending_clobbers = ALLOC_REG_SET (®_obstack); | |
4178 | reg_pending_uses = ALLOC_REG_SET (®_obstack); | |
e2724e63 | 4179 | reg_pending_control_uses = ALLOC_REG_SET (®_obstack); |
d1c9693e | 4180 | reg_pending_barrier = NOT_A_BARRIER; |
e855c69d AB |
4181 | |
4182 | if (!sel_sched_p () || sched_emulate_haifa_p) | |
4183 | { | |
4184 | sched_deps_info->start_insn = haifa_start_insn; | |
4185 | sched_deps_info->finish_insn = haifa_finish_insn; | |
4186 | ||
4187 | sched_deps_info->note_reg_set = haifa_note_reg_set; | |
4188 | sched_deps_info->note_reg_clobber = haifa_note_reg_clobber; | |
4189 | sched_deps_info->note_reg_use = haifa_note_reg_use; | |
4190 | ||
4191 | sched_deps_info->note_mem_dep = haifa_note_mem_dep; | |
4192 | sched_deps_info->note_dep = haifa_note_dep; | |
4193 | } | |
16f6ece6 BS |
4194 | } |
4195 | ||
4196 | /* Free everything used by the dependency analysis code. */ | |
4197 | ||
4198 | void | |
46c5ad27 | 4199 | finish_deps_global (void) |
16f6ece6 BS |
4200 | { |
4201 | FREE_REG_SET (reg_pending_sets); | |
4202 | FREE_REG_SET (reg_pending_clobbers); | |
37a0f8a5 | 4203 | FREE_REG_SET (reg_pending_uses); |
e2724e63 | 4204 | FREE_REG_SET (reg_pending_control_uses); |
16f6ece6 | 4205 | } |
ddbd5439 | 4206 | |
ddbd5439 | 4207 | /* Estimate the weakness of dependence between MEM1 and MEM2. */ |
e855c69d | 4208 | dw_t |
ddbd5439 MK |
4209 | estimate_dep_weak (rtx mem1, rtx mem2) |
4210 | { | |
4211 | rtx r1, r2; | |
4212 | ||
4213 | if (mem1 == mem2) | |
4214 | /* MEMs are the same - don't speculate. */ | |
4215 | return MIN_DEP_WEAK; | |
4216 | ||
4217 | r1 = XEXP (mem1, 0); | |
4218 | r2 = XEXP (mem2, 0); | |
4219 | ||
4220 | if (r1 == r2 | |
4221 | || (REG_P (r1) && REG_P (r2) | |
4222 | && REGNO (r1) == REGNO (r2))) | |
4223 | /* Again, MEMs are the same. */ | |
4224 | return MIN_DEP_WEAK; | |
4225 | else if ((REG_P (r1) && !REG_P (r2)) | |
4226 | || (!REG_P (r1) && REG_P (r2))) | |
4227 | /* Different addressing modes - reason to be more speculative, | |
4228 | than usual. */ | |
4229 | return NO_DEP_WEAK - (NO_DEP_WEAK - UNCERTAIN_DEP_WEAK) / 2; | |
4230 | else | |
4231 | /* We can't say anything about the dependence. */ | |
4232 | return UNCERTAIN_DEP_WEAK; | |
4233 | } | |
4234 | ||
4235 | /* Add or update backward dependence between INSN and ELEM with type DEP_TYPE. | |
4236 | This function can handle same INSN and ELEM (INSN == ELEM). | |
4237 | It is a convenience wrapper. */ | |
e2724e63 | 4238 | static void |
ce1ce33a | 4239 | add_dependence_1 (rtx_insn *insn, rtx_insn *elem, enum reg_note dep_type) |
ddbd5439 | 4240 | { |
e855c69d AB |
4241 | ds_t ds; |
4242 | bool internal; | |
ddbd5439 | 4243 | |
e855c69d AB |
4244 | if (dep_type == REG_DEP_TRUE) |
4245 | ds = DEP_TRUE; | |
4246 | else if (dep_type == REG_DEP_OUTPUT) | |
4247 | ds = DEP_OUTPUT; | |
e2724e63 BS |
4248 | else if (dep_type == REG_DEP_CONTROL) |
4249 | ds = DEP_CONTROL; | |
e855c69d AB |
4250 | else |
4251 | { | |
4252 | gcc_assert (dep_type == REG_DEP_ANTI); | |
4253 | ds = DEP_ANTI; | |
4254 | } | |
4255 | ||
4256 | /* When add_dependence is called from inside sched-deps.c, we expect | |
4257 | cur_insn to be non-null. */ | |
4258 | internal = cur_insn != NULL; | |
4259 | if (internal) | |
4260 | gcc_assert (insn == cur_insn); | |
4261 | else | |
4262 | cur_insn = insn; | |
b8698a0f | 4263 | |
e855c69d AB |
4264 | note_dep (elem, ds); |
4265 | if (!internal) | |
4266 | cur_insn = NULL; | |
ddbd5439 MK |
4267 | } |
4268 | ||
8e90de43 SB |
4269 | /* Return weakness of speculative type TYPE in the dep_status DS, |
4270 | without checking to prevent ICEs on malformed input. */ | |
4271 | static dw_t | |
e2f6ff94 | 4272 | get_dep_weak_1 (ds_t ds, ds_t type) |
ddbd5439 MK |
4273 | { |
4274 | ds = ds & type; | |
e855c69d | 4275 | |
ddbd5439 MK |
4276 | switch (type) |
4277 | { | |
4278 | case BEGIN_DATA: ds >>= BEGIN_DATA_BITS_OFFSET; break; | |
4279 | case BE_IN_DATA: ds >>= BE_IN_DATA_BITS_OFFSET; break; | |
4280 | case BEGIN_CONTROL: ds >>= BEGIN_CONTROL_BITS_OFFSET; break; | |
4281 | case BE_IN_CONTROL: ds >>= BE_IN_CONTROL_BITS_OFFSET; break; | |
4282 | default: gcc_unreachable (); | |
4283 | } | |
4284 | ||
ddbd5439 MK |
4285 | return (dw_t) ds; |
4286 | } | |
4287 | ||
8e90de43 | 4288 | /* Return weakness of speculative type TYPE in the dep_status DS. */ |
e2f6ff94 MK |
4289 | dw_t |
4290 | get_dep_weak (ds_t ds, ds_t type) | |
4291 | { | |
4292 | dw_t dw = get_dep_weak_1 (ds, type); | |
4293 | ||
4294 | gcc_assert (MIN_DEP_WEAK <= dw && dw <= MAX_DEP_WEAK); | |
e2f6ff94 MK |
4295 | return dw; |
4296 | } | |
4297 | ||
ddbd5439 MK |
4298 | /* Return the dep_status, which has the same parameters as DS, except for |
4299 | speculative type TYPE, that will have weakness DW. */ | |
4300 | ds_t | |
4301 | set_dep_weak (ds_t ds, ds_t type, dw_t dw) | |
4302 | { | |
4303 | gcc_assert (MIN_DEP_WEAK <= dw && dw <= MAX_DEP_WEAK); | |
4304 | ||
4305 | ds &= ~type; | |
4306 | switch (type) | |
4307 | { | |
4308 | case BEGIN_DATA: ds |= ((ds_t) dw) << BEGIN_DATA_BITS_OFFSET; break; | |
4309 | case BE_IN_DATA: ds |= ((ds_t) dw) << BE_IN_DATA_BITS_OFFSET; break; | |
4310 | case BEGIN_CONTROL: ds |= ((ds_t) dw) << BEGIN_CONTROL_BITS_OFFSET; break; | |
4311 | case BE_IN_CONTROL: ds |= ((ds_t) dw) << BE_IN_CONTROL_BITS_OFFSET; break; | |
4312 | default: gcc_unreachable (); | |
4313 | } | |
4314 | return ds; | |
4315 | } | |
4316 | ||
e855c69d AB |
4317 | /* Return the join of two dep_statuses DS1 and DS2. |
4318 | If MAX_P is true then choose the greater probability, | |
4319 | otherwise multiply probabilities. | |
4320 | This function assumes that both DS1 and DS2 contain speculative bits. */ | |
4321 | static ds_t | |
4322 | ds_merge_1 (ds_t ds1, ds_t ds2, bool max_p) | |
ddbd5439 MK |
4323 | { |
4324 | ds_t ds, t; | |
4325 | ||
4326 | gcc_assert ((ds1 & SPECULATIVE) && (ds2 & SPECULATIVE)); | |
4327 | ||
4328 | ds = (ds1 & DEP_TYPES) | (ds2 & DEP_TYPES); | |
4329 | ||
4330 | t = FIRST_SPEC_TYPE; | |
4331 | do | |
4332 | { | |
4333 | if ((ds1 & t) && !(ds2 & t)) | |
4334 | ds |= ds1 & t; | |
4335 | else if (!(ds1 & t) && (ds2 & t)) | |
4336 | ds |= ds2 & t; | |
4337 | else if ((ds1 & t) && (ds2 & t)) | |
4338 | { | |
e855c69d AB |
4339 | dw_t dw1 = get_dep_weak (ds1, t); |
4340 | dw_t dw2 = get_dep_weak (ds2, t); | |
ddbd5439 MK |
4341 | ds_t dw; |
4342 | ||
e855c69d AB |
4343 | if (!max_p) |
4344 | { | |
4345 | dw = ((ds_t) dw1) * ((ds_t) dw2); | |
4346 | dw /= MAX_DEP_WEAK; | |
4347 | if (dw < MIN_DEP_WEAK) | |
4348 | dw = MIN_DEP_WEAK; | |
4349 | } | |
4350 | else | |
4351 | { | |
4352 | if (dw1 >= dw2) | |
4353 | dw = dw1; | |
4354 | else | |
4355 | dw = dw2; | |
4356 | } | |
ddbd5439 MK |
4357 | |
4358 | ds = set_dep_weak (ds, t, (dw_t) dw); | |
4359 | } | |
4360 | ||
4361 | if (t == LAST_SPEC_TYPE) | |
4362 | break; | |
4363 | t <<= SPEC_TYPE_SHIFT; | |
4364 | } | |
4365 | while (1); | |
4366 | ||
4367 | return ds; | |
4368 | } | |
4369 | ||
e855c69d AB |
4370 | /* Return the join of two dep_statuses DS1 and DS2. |
4371 | This function assumes that both DS1 and DS2 contain speculative bits. */ | |
4372 | ds_t | |
4373 | ds_merge (ds_t ds1, ds_t ds2) | |
4374 | { | |
4375 | return ds_merge_1 (ds1, ds2, false); | |
4376 | } | |
4377 | ||
4378 | /* Return the join of two dep_statuses DS1 and DS2. */ | |
4379 | ds_t | |
4380 | ds_full_merge (ds_t ds, ds_t ds2, rtx mem1, rtx mem2) | |
4381 | { | |
4382 | ds_t new_status = ds | ds2; | |
4383 | ||
4384 | if (new_status & SPECULATIVE) | |
4385 | { | |
4386 | if ((ds && !(ds & SPECULATIVE)) | |
4387 | || (ds2 && !(ds2 & SPECULATIVE))) | |
4388 | /* Then this dep can't be speculative. */ | |
4389 | new_status &= ~SPECULATIVE; | |
4390 | else | |
4391 | { | |
4392 | /* Both are speculative. Merging probabilities. */ | |
4393 | if (mem1) | |
4394 | { | |
4395 | dw_t dw; | |
4396 | ||
4397 | dw = estimate_dep_weak (mem1, mem2); | |
4398 | ds = set_dep_weak (ds, BEGIN_DATA, dw); | |
4399 | } | |
4400 | ||
4401 | if (!ds) | |
4402 | new_status = ds2; | |
4403 | else if (!ds2) | |
4404 | new_status = ds; | |
4405 | else | |
4406 | new_status = ds_merge (ds2, ds); | |
4407 | } | |
4408 | } | |
4409 | ||
4410 | return new_status; | |
4411 | } | |
4412 | ||
4413 | /* Return the join of DS1 and DS2. Use maximum instead of multiplying | |
4414 | probabilities. */ | |
4415 | ds_t | |
4416 | ds_max_merge (ds_t ds1, ds_t ds2) | |
4417 | { | |
4418 | if (ds1 == 0 && ds2 == 0) | |
4419 | return 0; | |
4420 | ||
4421 | if (ds1 == 0 && ds2 != 0) | |
4422 | return ds2; | |
4423 | ||
4424 | if (ds1 != 0 && ds2 == 0) | |
4425 | return ds1; | |
4426 | ||
4427 | return ds_merge_1 (ds1, ds2, true); | |
4428 | } | |
4429 | ||
4430 | /* Return the probability of speculation success for the speculation | |
4431 | status DS. */ | |
4432 | dw_t | |
4433 | ds_weak (ds_t ds) | |
4434 | { | |
4435 | ds_t res = 1, dt; | |
4436 | int n = 0; | |
4437 | ||
4438 | dt = FIRST_SPEC_TYPE; | |
4439 | do | |
4440 | { | |
4441 | if (ds & dt) | |
4442 | { | |
4443 | res *= (ds_t) get_dep_weak (ds, dt); | |
4444 | n++; | |
4445 | } | |
4446 | ||
4447 | if (dt == LAST_SPEC_TYPE) | |
4448 | break; | |
4449 | dt <<= SPEC_TYPE_SHIFT; | |
4450 | } | |
4451 | while (1); | |
4452 | ||
4453 | gcc_assert (n); | |
4454 | while (--n) | |
4455 | res /= MAX_DEP_WEAK; | |
4456 | ||
4457 | if (res < MIN_DEP_WEAK) | |
4458 | res = MIN_DEP_WEAK; | |
4459 | ||
4460 | gcc_assert (res <= MAX_DEP_WEAK); | |
4461 | ||
4462 | return (dw_t) res; | |
4463 | } | |
4464 | ||
4465 | /* Return a dep status that contains all speculation types of DS. */ | |
4466 | ds_t | |
4467 | ds_get_speculation_types (ds_t ds) | |
4468 | { | |
4469 | if (ds & BEGIN_DATA) | |
4470 | ds |= BEGIN_DATA; | |
4471 | if (ds & BE_IN_DATA) | |
4472 | ds |= BE_IN_DATA; | |
4473 | if (ds & BEGIN_CONTROL) | |
4474 | ds |= BEGIN_CONTROL; | |
4475 | if (ds & BE_IN_CONTROL) | |
4476 | ds |= BE_IN_CONTROL; | |
4477 | ||
4478 | return ds & SPECULATIVE; | |
4479 | } | |
4480 | ||
4481 | /* Return a dep status that contains maximal weakness for each speculation | |
4482 | type present in DS. */ | |
4483 | ds_t | |
4484 | ds_get_max_dep_weak (ds_t ds) | |
4485 | { | |
4486 | if (ds & BEGIN_DATA) | |
4487 | ds = set_dep_weak (ds, BEGIN_DATA, MAX_DEP_WEAK); | |
4488 | if (ds & BE_IN_DATA) | |
4489 | ds = set_dep_weak (ds, BE_IN_DATA, MAX_DEP_WEAK); | |
4490 | if (ds & BEGIN_CONTROL) | |
4491 | ds = set_dep_weak (ds, BEGIN_CONTROL, MAX_DEP_WEAK); | |
4492 | if (ds & BE_IN_CONTROL) | |
4493 | ds = set_dep_weak (ds, BE_IN_CONTROL, MAX_DEP_WEAK); | |
4494 | ||
4495 | return ds; | |
4496 | } | |
4497 | ||
e2f6ff94 MK |
4498 | /* Dump information about the dependence status S. */ |
4499 | static void | |
4500 | dump_ds (FILE *f, ds_t s) | |
4501 | { | |
4502 | fprintf (f, "{"); | |
4503 | ||
4504 | if (s & BEGIN_DATA) | |
4505 | fprintf (f, "BEGIN_DATA: %d; ", get_dep_weak_1 (s, BEGIN_DATA)); | |
4506 | if (s & BE_IN_DATA) | |
4507 | fprintf (f, "BE_IN_DATA: %d; ", get_dep_weak_1 (s, BE_IN_DATA)); | |
4508 | if (s & BEGIN_CONTROL) | |
4509 | fprintf (f, "BEGIN_CONTROL: %d; ", get_dep_weak_1 (s, BEGIN_CONTROL)); | |
4510 | if (s & BE_IN_CONTROL) | |
4511 | fprintf (f, "BE_IN_CONTROL: %d; ", get_dep_weak_1 (s, BE_IN_CONTROL)); | |
4512 | ||
4513 | if (s & HARD_DEP) | |
4514 | fprintf (f, "HARD_DEP; "); | |
4515 | ||
4516 | if (s & DEP_TRUE) | |
4517 | fprintf (f, "DEP_TRUE; "); | |
e2f6ff94 MK |
4518 | if (s & DEP_OUTPUT) |
4519 | fprintf (f, "DEP_OUTPUT; "); | |
e2724e63 BS |
4520 | if (s & DEP_ANTI) |
4521 | fprintf (f, "DEP_ANTI; "); | |
4522 | if (s & DEP_CONTROL) | |
4523 | fprintf (f, "DEP_CONTROL; "); | |
e2f6ff94 MK |
4524 | |
4525 | fprintf (f, "}"); | |
4526 | } | |
4527 | ||
24e47c76 | 4528 | DEBUG_FUNCTION void |
e2f6ff94 MK |
4529 | debug_ds (ds_t s) |
4530 | { | |
4531 | dump_ds (stderr, s); | |
4532 | fprintf (stderr, "\n"); | |
4533 | } | |
4534 | ||
ddbd5439 MK |
4535 | #ifdef ENABLE_CHECKING |
4536 | /* Verify that dependence type and status are consistent. | |
4537 | If RELAXED_P is true, then skip dep_weakness checks. */ | |
4538 | static void | |
e2f6ff94 | 4539 | check_dep (dep_t dep, bool relaxed_p) |
ddbd5439 | 4540 | { |
e2f6ff94 MK |
4541 | enum reg_note dt = DEP_TYPE (dep); |
4542 | ds_t ds = DEP_STATUS (dep); | |
4543 | ||
4544 | gcc_assert (DEP_PRO (dep) != DEP_CON (dep)); | |
4545 | ||
4546 | if (!(current_sched_info->flags & USE_DEPS_LIST)) | |
4547 | { | |
b953c2b8 | 4548 | gcc_assert (ds == 0); |
e2f6ff94 MK |
4549 | return; |
4550 | } | |
4551 | ||
ddbd5439 MK |
4552 | /* Check that dependence type contains the same bits as the status. */ |
4553 | if (dt == REG_DEP_TRUE) | |
4554 | gcc_assert (ds & DEP_TRUE); | |
4555 | else if (dt == REG_DEP_OUTPUT) | |
4556 | gcc_assert ((ds & DEP_OUTPUT) | |
b8698a0f | 4557 | && !(ds & DEP_TRUE)); |
e2724e63 BS |
4558 | else if (dt == REG_DEP_ANTI) |
4559 | gcc_assert ((ds & DEP_ANTI) | |
ddbd5439 | 4560 | && !(ds & (DEP_OUTPUT | DEP_TRUE))); |
e2724e63 BS |
4561 | else |
4562 | gcc_assert (dt == REG_DEP_CONTROL | |
4563 | && (ds & DEP_CONTROL) | |
4564 | && !(ds & (DEP_OUTPUT | DEP_ANTI | DEP_TRUE))); | |
ddbd5439 MK |
4565 | |
4566 | /* HARD_DEP can not appear in dep_status of a link. */ | |
b8698a0f | 4567 | gcc_assert (!(ds & HARD_DEP)); |
ddbd5439 MK |
4568 | |
4569 | /* Check that dependence status is set correctly when speculation is not | |
4570 | supported. */ | |
e855c69d | 4571 | if (!sched_deps_info->generate_spec_deps) |
ddbd5439 MK |
4572 | gcc_assert (!(ds & SPECULATIVE)); |
4573 | else if (ds & SPECULATIVE) | |
4574 | { | |
4575 | if (!relaxed_p) | |
4576 | { | |
4577 | ds_t type = FIRST_SPEC_TYPE; | |
4578 | ||
4579 | /* Check that dependence weakness is in proper range. */ | |
4580 | do | |
4581 | { | |
4582 | if (ds & type) | |
4583 | get_dep_weak (ds, type); | |
4584 | ||
4585 | if (type == LAST_SPEC_TYPE) | |
4586 | break; | |
4587 | type <<= SPEC_TYPE_SHIFT; | |
4588 | } | |
4589 | while (1); | |
4590 | } | |
4591 | ||
4592 | if (ds & BEGIN_SPEC) | |
4593 | { | |
4594 | /* Only true dependence can be data speculative. */ | |
4595 | if (ds & BEGIN_DATA) | |
4596 | gcc_assert (ds & DEP_TRUE); | |
4597 | ||
4598 | /* Control dependencies in the insn scheduler are represented by | |
4599 | anti-dependencies, therefore only anti dependence can be | |
4600 | control speculative. */ | |
4601 | if (ds & BEGIN_CONTROL) | |
4602 | gcc_assert (ds & DEP_ANTI); | |
4603 | } | |
4604 | else | |
4605 | { | |
4606 | /* Subsequent speculations should resolve true dependencies. */ | |
4607 | gcc_assert ((ds & DEP_TYPES) == DEP_TRUE); | |
4608 | } | |
b8698a0f L |
4609 | |
4610 | /* Check that true and anti dependencies can't have other speculative | |
ddbd5439 MK |
4611 | statuses. */ |
4612 | if (ds & DEP_TRUE) | |
4613 | gcc_assert (ds & (BEGIN_DATA | BE_IN_SPEC)); | |
4614 | /* An output dependence can't be speculative at all. */ | |
4615 | gcc_assert (!(ds & DEP_OUTPUT)); | |
4616 | if (ds & DEP_ANTI) | |
4617 | gcc_assert (ds & BEGIN_CONTROL); | |
4618 | } | |
4619 | } | |
a750daa2 MK |
4620 | #endif /* ENABLE_CHECKING */ |
4621 | ||
1a83e602 BS |
4622 | /* The following code discovers opportunities to switch a memory reference |
4623 | and an increment by modifying the address. We ensure that this is done | |
4624 | only for dependencies that are only used to show a single register | |
4625 | dependence (using DEP_NONREG and DEP_MULTIPLE), and so that every memory | |
4626 | instruction involved is subject to only one dep that can cause a pattern | |
4627 | change. | |
4628 | ||
4629 | When we discover a suitable dependency, we fill in the dep_replacement | |
4630 | structure to show how to modify the memory reference. */ | |
4631 | ||
4632 | /* Holds information about a pair of memory reference and register increment | |
4633 | insns which depend on each other, but could possibly be interchanged. */ | |
4634 | struct mem_inc_info | |
4635 | { | |
ce1ce33a DM |
4636 | rtx_insn *inc_insn; |
4637 | rtx_insn *mem_insn; | |
1a83e602 BS |
4638 | |
4639 | rtx *mem_loc; | |
4640 | /* A register occurring in the memory address for which we wish to break | |
4641 | the dependence. This must be identical to the destination register of | |
4642 | the increment. */ | |
4643 | rtx mem_reg0; | |
4644 | /* Any kind of index that is added to that register. */ | |
4645 | rtx mem_index; | |
4646 | /* The constant offset used in the memory address. */ | |
4647 | HOST_WIDE_INT mem_constant; | |
4648 | /* The constant added in the increment insn. Negated if the increment is | |
4649 | after the memory address. */ | |
4650 | HOST_WIDE_INT inc_constant; | |
4651 | /* The source register used in the increment. May be different from mem_reg0 | |
4652 | if the increment occurs before the memory address. */ | |
4653 | rtx inc_input; | |
4654 | }; | |
4655 | ||
4656 | /* Verify that the memory location described in MII can be replaced with | |
4657 | one using NEW_ADDR. Return the new memory reference or NULL_RTX. The | |
4658 | insn remains unchanged by this function. */ | |
4659 | ||
4660 | static rtx | |
4661 | attempt_change (struct mem_inc_info *mii, rtx new_addr) | |
4662 | { | |
4663 | rtx mem = *mii->mem_loc; | |
4664 | rtx new_mem; | |
4665 | ||
1aa95df7 | 4666 | /* Jump through a lot of hoops to keep the attributes up to date. We |
1a83e602 BS |
4667 | do not want to call one of the change address variants that take |
4668 | an offset even though we know the offset in many cases. These | |
4669 | assume you are changing where the address is pointing by the | |
4670 | offset. */ | |
4671 | new_mem = replace_equiv_address_nv (mem, new_addr); | |
4672 | if (! validate_change (mii->mem_insn, mii->mem_loc, new_mem, 0)) | |
4673 | { | |
4674 | if (sched_verbose >= 5) | |
4675 | fprintf (sched_dump, "validation failure\n"); | |
4676 | return NULL_RTX; | |
4677 | } | |
4678 | ||
4679 | /* Put back the old one. */ | |
4680 | validate_change (mii->mem_insn, mii->mem_loc, mem, 0); | |
4681 | ||
4682 | return new_mem; | |
4683 | } | |
4684 | ||
4685 | /* Return true if INSN is of a form "a = b op c" where a and b are | |
4686 | regs. op is + if c is a reg and +|- if c is a const. Fill in | |
4687 | informantion in MII about what is found. | |
4688 | BEFORE_MEM indicates whether the increment is found before or after | |
4689 | a corresponding memory reference. */ | |
4690 | ||
4691 | static bool | |
ce1ce33a | 4692 | parse_add_or_inc (struct mem_inc_info *mii, rtx_insn *insn, bool before_mem) |
1a83e602 BS |
4693 | { |
4694 | rtx pat = single_set (insn); | |
4695 | rtx src, cst; | |
4696 | bool regs_equal; | |
4697 | ||
4698 | if (RTX_FRAME_RELATED_P (insn) || !pat) | |
4699 | return false; | |
4700 | ||
4701 | /* Result must be single reg. */ | |
4702 | if (!REG_P (SET_DEST (pat))) | |
4703 | return false; | |
4704 | ||
0380c51f | 4705 | if (GET_CODE (SET_SRC (pat)) != PLUS) |
1a83e602 BS |
4706 | return false; |
4707 | ||
4708 | mii->inc_insn = insn; | |
4709 | src = SET_SRC (pat); | |
4710 | mii->inc_input = XEXP (src, 0); | |
4711 | ||
4712 | if (!REG_P (XEXP (src, 0))) | |
4713 | return false; | |
4714 | ||
4715 | if (!rtx_equal_p (SET_DEST (pat), mii->mem_reg0)) | |
4716 | return false; | |
4717 | ||
4718 | cst = XEXP (src, 1); | |
4719 | if (!CONST_INT_P (cst)) | |
4720 | return false; | |
4721 | mii->inc_constant = INTVAL (cst); | |
4722 | ||
4723 | regs_equal = rtx_equal_p (mii->inc_input, mii->mem_reg0); | |
4724 | ||
4725 | if (!before_mem) | |
4726 | { | |
4727 | mii->inc_constant = -mii->inc_constant; | |
4728 | if (!regs_equal) | |
4729 | return false; | |
4730 | } | |
4731 | ||
4732 | if (regs_equal && REGNO (SET_DEST (pat)) == STACK_POINTER_REGNUM) | |
0380c51f BS |
4733 | { |
4734 | /* Note that the sign has already been reversed for !before_mem. */ | |
4735 | #ifdef STACK_GROWS_DOWNWARD | |
4736 | return mii->inc_constant > 0; | |
4737 | #else | |
4738 | return mii->inc_constant < 0; | |
4739 | #endif | |
4740 | } | |
1a83e602 BS |
4741 | return true; |
4742 | } | |
4743 | ||
4744 | /* Once a suitable mem reference has been found and the corresponding data | |
4745 | in MII has been filled in, this function is called to find a suitable | |
4746 | add or inc insn involving the register we found in the memory | |
4747 | reference. */ | |
4748 | ||
4749 | static bool | |
4750 | find_inc (struct mem_inc_info *mii, bool backwards) | |
4751 | { | |
4752 | sd_iterator_def sd_it; | |
4753 | dep_t dep; | |
4754 | ||
4755 | sd_it = sd_iterator_start (mii->mem_insn, | |
4756 | backwards ? SD_LIST_HARD_BACK : SD_LIST_FORW); | |
4757 | while (sd_iterator_cond (&sd_it, &dep)) | |
4758 | { | |
4759 | dep_node_t node = DEP_LINK_NODE (*sd_it.linkp); | |
974c43e9 DM |
4760 | rtx_insn *pro = DEP_PRO (dep); |
4761 | rtx_insn *con = DEP_CON (dep); | |
ce1ce33a | 4762 | rtx_insn *inc_cand = backwards ? pro : con; |
1a83e602 BS |
4763 | if (DEP_NONREG (dep) || DEP_MULTIPLE (dep)) |
4764 | goto next; | |
4765 | if (parse_add_or_inc (mii, inc_cand, backwards)) | |
4766 | { | |
4767 | struct dep_replacement *desc; | |
bfac633a | 4768 | df_ref def; |
1a83e602 BS |
4769 | rtx newaddr, newmem; |
4770 | ||
4771 | if (sched_verbose >= 5) | |
4772 | fprintf (sched_dump, "candidate mem/inc pair: %d %d\n", | |
4773 | INSN_UID (mii->mem_insn), INSN_UID (inc_cand)); | |
4774 | ||
4775 | /* Need to assure that none of the operands of the inc | |
4776 | instruction are assigned to by the mem insn. */ | |
bfac633a RS |
4777 | FOR_EACH_INSN_DEF (def, mii->mem_insn) |
4778 | if (reg_overlap_mentioned_p (DF_REF_REG (def), mii->inc_input) | |
4779 | || reg_overlap_mentioned_p (DF_REF_REG (def), mii->mem_reg0)) | |
4780 | { | |
4781 | if (sched_verbose >= 5) | |
4782 | fprintf (sched_dump, | |
4783 | "inc conflicts with store failure.\n"); | |
4784 | goto next; | |
4785 | } | |
c7cf969c | 4786 | |
1a83e602 BS |
4787 | newaddr = mii->inc_input; |
4788 | if (mii->mem_index != NULL_RTX) | |
4789 | newaddr = gen_rtx_PLUS (GET_MODE (newaddr), newaddr, | |
4790 | mii->mem_index); | |
4791 | newaddr = plus_constant (GET_MODE (newaddr), newaddr, | |
4792 | mii->mem_constant + mii->inc_constant); | |
4793 | newmem = attempt_change (mii, newaddr); | |
4794 | if (newmem == NULL_RTX) | |
4795 | goto next; | |
4796 | if (sched_verbose >= 5) | |
4797 | fprintf (sched_dump, "successful address replacement\n"); | |
4798 | desc = XCNEW (struct dep_replacement); | |
4799 | DEP_REPLACE (dep) = desc; | |
4800 | desc->loc = mii->mem_loc; | |
4801 | desc->newval = newmem; | |
4802 | desc->orig = *desc->loc; | |
4803 | desc->insn = mii->mem_insn; | |
4804 | move_dep_link (DEP_NODE_BACK (node), INSN_HARD_BACK_DEPS (con), | |
4805 | INSN_SPEC_BACK_DEPS (con)); | |
4806 | if (backwards) | |
4807 | { | |
4808 | FOR_EACH_DEP (mii->inc_insn, SD_LIST_BACK, sd_it, dep) | |
28d1688d BS |
4809 | add_dependence_1 (mii->mem_insn, DEP_PRO (dep), |
4810 | REG_DEP_TRUE); | |
1a83e602 BS |
4811 | } |
4812 | else | |
4813 | { | |
4814 | FOR_EACH_DEP (mii->inc_insn, SD_LIST_FORW, sd_it, dep) | |
28d1688d BS |
4815 | add_dependence_1 (DEP_CON (dep), mii->mem_insn, |
4816 | REG_DEP_ANTI); | |
1a83e602 BS |
4817 | } |
4818 | return true; | |
4819 | } | |
4820 | next: | |
4821 | sd_iterator_next (&sd_it); | |
4822 | } | |
4823 | return false; | |
4824 | } | |
4825 | ||
4826 | /* A recursive function that walks ADDRESS_OF_X to find memory references | |
4827 | which could be modified during scheduling. We call find_inc for each | |
4828 | one we find that has a recognizable form. MII holds information about | |
4829 | the pair of memory/increment instructions. | |
4830 | We ensure that every instruction with a memory reference (which will be | |
4831 | the location of the replacement) is assigned at most one breakable | |
4832 | dependency. */ | |
4833 | ||
4834 | static bool | |
4835 | find_mem (struct mem_inc_info *mii, rtx *address_of_x) | |
4836 | { | |
4837 | rtx x = *address_of_x; | |
4838 | enum rtx_code code = GET_CODE (x); | |
4839 | const char *const fmt = GET_RTX_FORMAT (code); | |
4840 | int i; | |
4841 | ||
4842 | if (code == MEM) | |
4843 | { | |
4844 | rtx reg0 = XEXP (x, 0); | |
4845 | ||
4846 | mii->mem_loc = address_of_x; | |
4847 | mii->mem_index = NULL_RTX; | |
4848 | mii->mem_constant = 0; | |
4849 | if (GET_CODE (reg0) == PLUS && CONST_INT_P (XEXP (reg0, 1))) | |
4850 | { | |
4851 | mii->mem_constant = INTVAL (XEXP (reg0, 1)); | |
4852 | reg0 = XEXP (reg0, 0); | |
4853 | } | |
4854 | if (GET_CODE (reg0) == PLUS) | |
4855 | { | |
4856 | mii->mem_index = XEXP (reg0, 1); | |
4857 | reg0 = XEXP (reg0, 0); | |
4858 | } | |
4859 | if (REG_P (reg0)) | |
4860 | { | |
bfac633a | 4861 | df_ref use; |
1a83e602 BS |
4862 | int occurrences = 0; |
4863 | ||
4864 | /* Make sure this reg appears only once in this insn. Can't use | |
4865 | count_occurrences since that only works for pseudos. */ | |
bfac633a RS |
4866 | FOR_EACH_INSN_USE (use, mii->mem_insn) |
4867 | if (reg_overlap_mentioned_p (reg0, DF_REF_REG (use))) | |
4868 | if (++occurrences > 1) | |
4869 | { | |
4870 | if (sched_verbose >= 5) | |
4871 | fprintf (sched_dump, "mem count failure\n"); | |
4872 | return false; | |
4873 | } | |
1a83e602 BS |
4874 | |
4875 | mii->mem_reg0 = reg0; | |
4876 | return find_inc (mii, true) || find_inc (mii, false); | |
4877 | } | |
4878 | return false; | |
4879 | } | |
4880 | ||
4881 | if (code == SIGN_EXTRACT || code == ZERO_EXTRACT) | |
4882 | { | |
4883 | /* If REG occurs inside a MEM used in a bit-field reference, | |
4884 | that is unacceptable. */ | |
4885 | return false; | |
4886 | } | |
4887 | ||
4888 | /* Time for some deep diving. */ | |
4889 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4890 | { | |
4891 | if (fmt[i] == 'e') | |
4892 | { | |
4893 | if (find_mem (mii, &XEXP (x, i))) | |
4894 | return true; | |
4895 | } | |
4896 | else if (fmt[i] == 'E') | |
4897 | { | |
4898 | int j; | |
4899 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4900 | if (find_mem (mii, &XVECEXP (x, i, j))) | |
4901 | return true; | |
4902 | } | |
4903 | } | |
4904 | return false; | |
4905 | } | |
4906 | ||
4907 | ||
4908 | /* Examine the instructions between HEAD and TAIL and try to find | |
4909 | dependencies that can be broken by modifying one of the patterns. */ | |
4910 | ||
4911 | void | |
ce1ce33a | 4912 | find_modifiable_mems (rtx_insn *head, rtx_insn *tail) |
1a83e602 | 4913 | { |
ce1ce33a | 4914 | rtx_insn *insn, *next_tail = NEXT_INSN (tail); |
1a83e602 BS |
4915 | int success_in_block = 0; |
4916 | ||
8b8de8b6 | 4917 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) |
1a83e602 BS |
4918 | { |
4919 | struct mem_inc_info mii; | |
4920 | ||
4921 | if (!NONDEBUG_INSN_P (insn) || RTX_FRAME_RELATED_P (insn)) | |
4922 | continue; | |
4923 | ||
4924 | mii.mem_insn = insn; | |
4925 | if (find_mem (&mii, &PATTERN (insn))) | |
4926 | success_in_block++; | |
4927 | } | |
4928 | if (success_in_block && sched_verbose >= 5) | |
4929 | fprintf (sched_dump, "%d candidates for address modification found.\n", | |
4930 | success_in_block); | |
4931 | } | |
4932 | ||
a750daa2 | 4933 | #endif /* INSN_SCHEDULING */ |