]>
Commit | Line | Data |
---|---|---|
e855c69d | 1 | /* Instruction scheduling pass. Selective scheduler and pipeliner. |
9b0f04e7 AB |
2 | Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011 |
3 | Free Software Foundation, Inc. | |
e855c69d AB |
4 | |
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
24 | #include "tm.h" | |
0cbd9993 | 25 | #include "rtl-error.h" |
e855c69d AB |
26 | #include "tm_p.h" |
27 | #include "hard-reg-set.h" | |
28 | #include "regs.h" | |
29 | #include "function.h" | |
30 | #include "flags.h" | |
31 | #include "insn-config.h" | |
32 | #include "insn-attr.h" | |
33 | #include "except.h" | |
e855c69d AB |
34 | #include "recog.h" |
35 | #include "params.h" | |
36 | #include "target.h" | |
37 | #include "output.h" | |
38 | #include "timevar.h" | |
39 | #include "tree-pass.h" | |
40 | #include "sched-int.h" | |
41 | #include "ggc.h" | |
42 | #include "tree.h" | |
43 | #include "vec.h" | |
44 | #include "langhooks.h" | |
45 | #include "rtlhooks-def.h" | |
46 | #include "output.h" | |
5936d944 | 47 | #include "emit-rtl.h" |
e855c69d AB |
48 | |
49 | #ifdef INSN_SCHEDULING | |
50 | #include "sel-sched-ir.h" | |
51 | #include "sel-sched-dump.h" | |
52 | #include "sel-sched.h" | |
53 | #include "dbgcnt.h" | |
54 | ||
55 | /* Implementation of selective scheduling approach. | |
56 | The below implementation follows the original approach with the following | |
57 | changes: | |
58 | ||
b8698a0f | 59 | o the scheduler works after register allocation (but can be also tuned |
e855c69d AB |
60 | to work before RA); |
61 | o some instructions are not copied or register renamed; | |
62 | o conditional jumps are not moved with code duplication; | |
63 | o several jumps in one parallel group are not supported; | |
64 | o when pipelining outer loops, code motion through inner loops | |
65 | is not supported; | |
66 | o control and data speculation are supported; | |
67 | o some improvements for better compile time/performance were made. | |
68 | ||
69 | Terminology | |
70 | =========== | |
71 | ||
b8698a0f L |
72 | A vinsn, or virtual insn, is an insn with additional data characterizing |
73 | insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc. | |
74 | Vinsns also act as smart pointers to save memory by reusing them in | |
e855c69d AB |
75 | different expressions. A vinsn is described by vinsn_t type. |
76 | ||
77 | An expression is a vinsn with additional data characterizing its properties | |
b8698a0f | 78 | at some point in the control flow graph. The data may be its usefulness, |
e855c69d AB |
79 | priority, speculative status, whether it was renamed/subsituted, etc. |
80 | An expression is described by expr_t type. | |
81 | ||
b8698a0f | 82 | Availability set (av_set) is a set of expressions at a given control flow |
e855c69d | 83 | point. It is represented as av_set_t. The expressions in av sets are kept |
b8698a0f | 84 | sorted in the terms of expr_greater_p function. It allows to truncate |
e855c69d | 85 | the set while leaving the best expressions. |
b8698a0f | 86 | |
e855c69d AB |
87 | A fence is a point through which code motion is prohibited. On each step, |
88 | we gather a parallel group of insns at a fence. It is possible to have | |
89 | multiple fences. A fence is represented via fence_t. | |
90 | ||
91 | A boundary is the border between the fence group and the rest of the code. | |
92 | Currently, we never have more than one boundary per fence, as we finalize | |
b8698a0f | 93 | the fence group when a jump is scheduled. A boundary is represented |
e855c69d AB |
94 | via bnd_t. |
95 | ||
96 | High-level overview | |
97 | =================== | |
98 | ||
99 | The scheduler finds regions to schedule, schedules each one, and finalizes. | |
b8698a0f | 100 | The regions are formed starting from innermost loops, so that when the inner |
e855c69d | 101 | loop is pipelined, its prologue can be scheduled together with yet unprocessed |
b8698a0f | 102 | outer loop. The rest of acyclic regions are found using extend_rgns: |
e855c69d | 103 | the blocks that are not yet allocated to any regions are traversed in top-down |
b8698a0f | 104 | order, and a block is added to a region to which all its predecessors belong; |
e855c69d AB |
105 | otherwise, the block starts its own region. |
106 | ||
107 | The main scheduling loop (sel_sched_region_2) consists of just | |
108 | scheduling on each fence and updating fences. For each fence, | |
109 | we fill a parallel group of insns (fill_insns) until some insns can be added. | |
b8698a0f L |
110 | First, we compute available exprs (av-set) at the boundary of the current |
111 | group. Second, we choose the best expression from it. If the stall is | |
e855c69d | 112 | required to schedule any of the expressions, we advance the current cycle |
b8698a0f | 113 | appropriately. So, the final group does not exactly correspond to a VLIW |
e855c69d AB |
114 | word. Third, we move the chosen expression to the boundary (move_op) |
115 | and update the intermediate av sets and liveness sets. We quit fill_insns | |
116 | when either no insns left for scheduling or we have scheduled enough insns | |
b8698a0f | 117 | so we feel like advancing a scheduling point. |
e855c69d AB |
118 | |
119 | Computing available expressions | |
120 | =============================== | |
121 | ||
122 | The computation (compute_av_set) is a bottom-up traversal. At each insn, | |
b8698a0f L |
123 | we're moving the union of its successors' sets through it via |
124 | moveup_expr_set. The dependent expressions are removed. Local | |
125 | transformations (substitution, speculation) are applied to move more | |
e855c69d AB |
126 | exprs. Then the expr corresponding to the current insn is added. |
127 | The result is saved on each basic block header. | |
128 | ||
129 | When traversing the CFG, we're moving down for no more than max_ws insns. | |
130 | Also, we do not move down to ineligible successors (is_ineligible_successor), | |
131 | which include moving along a back-edge, moving to already scheduled code, | |
b8698a0f | 132 | and moving to another fence. The first two restrictions are lifted during |
e855c69d AB |
133 | pipelining, which allows us to move insns along a back-edge. We always have |
134 | an acyclic region for scheduling because we forbid motion through fences. | |
135 | ||
136 | Choosing the best expression | |
137 | ============================ | |
138 | ||
139 | We sort the final availability set via sel_rank_for_schedule, then we remove | |
140 | expressions which are not yet ready (tick_check_p) or which dest registers | |
b8698a0f L |
141 | cannot be used. For some of them, we choose another register via |
142 | find_best_reg. To do this, we run find_used_regs to calculate the set of | |
e855c69d AB |
143 | registers which cannot be used. The find_used_regs function performs |
144 | a traversal of code motion paths for an expr. We consider for renaming | |
b8698a0f | 145 | only registers which are from the same regclass as the original one and |
e855c69d AB |
146 | using which does not interfere with any live ranges. Finally, we convert |
147 | the resulting set to the ready list format and use max_issue and reorder* | |
148 | hooks similarly to the Haifa scheduler. | |
149 | ||
150 | Scheduling the best expression | |
151 | ============================== | |
152 | ||
b8698a0f | 153 | We run the move_op routine to perform the same type of code motion paths |
e855c69d AB |
154 | traversal as in find_used_regs. (These are working via the same driver, |
155 | code_motion_path_driver.) When moving down the CFG, we look for original | |
b8698a0f | 156 | instruction that gave birth to a chosen expression. We undo |
e855c69d | 157 | the transformations performed on an expression via the history saved in it. |
b8698a0f L |
158 | When found, we remove the instruction or leave a reg-reg copy/speculation |
159 | check if needed. On a way up, we insert bookkeeping copies at each join | |
160 | point. If a copy is not needed, it will be removed later during this | |
e855c69d AB |
161 | traversal. We update the saved av sets and liveness sets on the way up, too. |
162 | ||
163 | Finalizing the schedule | |
164 | ======================= | |
165 | ||
b8698a0f L |
166 | When pipelining, we reschedule the blocks from which insns were pipelined |
167 | to get a tighter schedule. On Itanium, we also perform bundling via | |
168 | the same routine from ia64.c. | |
e855c69d AB |
169 | |
170 | Dependence analysis changes | |
171 | =========================== | |
172 | ||
173 | We augmented the sched-deps.c with hooks that get called when a particular | |
174 | dependence is found in a particular part of an insn. Using these hooks, we | |
175 | can do several actions such as: determine whether an insn can be moved through | |
b8698a0f L |
176 | another (has_dependence_p, moveup_expr); find out whether an insn can be |
177 | scheduled on the current cycle (tick_check_p); find out registers that | |
178 | are set/used/clobbered by an insn and find out all the strange stuff that | |
179 | restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in | |
e855c69d AB |
180 | init_global_and_expr_for_insn). |
181 | ||
182 | Initialization changes | |
183 | ====================== | |
184 | ||
b8698a0f | 185 | There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are |
e855c69d | 186 | reused in all of the schedulers. We have split up the initialization of data |
b8698a0f | 187 | of such parts into different functions prefixed with scheduler type and |
e855c69d AB |
188 | postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish}, |
189 | sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc. | |
b8698a0f L |
190 | The same splitting is done with current_sched_info structure: |
191 | dependence-related parts are in sched_deps_info, common part is in | |
e855c69d | 192 | common_sched_info, and haifa/sel/etc part is in current_sched_info. |
b8698a0f | 193 | |
e855c69d AB |
194 | Target contexts |
195 | =============== | |
196 | ||
197 | As we now have multiple-point scheduling, this would not work with backends | |
b8698a0f L |
198 | which save some of the scheduler state to use it in the target hooks. |
199 | For this purpose, we introduce a concept of target contexts, which | |
e855c69d AB |
200 | encapsulate such information. The backend should implement simple routines |
201 | of allocating/freeing/setting such a context. The scheduler calls these | |
202 | as target hooks and handles the target context as an opaque pointer (similar | |
203 | to the DFA state type, state_t). | |
204 | ||
205 | Various speedups | |
206 | ================ | |
207 | ||
208 | As the correct data dependence graph is not supported during scheduling (which | |
b8698a0f L |
209 | is to be changed in mid-term), we cache as much of the dependence analysis |
210 | results as possible to avoid reanalyzing. This includes: bitmap caches on | |
211 | each insn in stream of the region saying yes/no for a query with a pair of | |
e855c69d AB |
212 | UIDs; hashtables with the previously done transformations on each insn in |
213 | stream; a vector keeping a history of transformations on each expr. | |
214 | ||
215 | Also, we try to minimize the dependence context used on each fence to check | |
216 | whether the given expression is ready for scheduling by removing from it | |
b8698a0f | 217 | insns that are definitely completed the execution. The results of |
e855c69d AB |
218 | tick_check_p checks are also cached in a vector on each fence. |
219 | ||
b8698a0f | 220 | We keep a valid liveness set on each insn in a region to avoid the high |
e855c69d AB |
221 | cost of recomputation on large basic blocks. |
222 | ||
223 | Finally, we try to minimize the number of needed updates to the availability | |
b8698a0f | 224 | sets. The updates happen in two cases: when fill_insns terminates, |
e855c69d AB |
225 | we advance all fences and increase the stage number to show that the region |
226 | has changed and the sets are to be recomputed; and when the next iteration | |
227 | of a loop in fill_insns happens (but this one reuses the saved av sets | |
228 | on bb headers.) Thus, we try to break the fill_insns loop only when | |
229 | "significant" number of insns from the current scheduling window was | |
230 | scheduled. This should be made a target param. | |
b8698a0f | 231 | |
e855c69d AB |
232 | |
233 | TODO: correctly support the data dependence graph at all stages and get rid | |
234 | of all caches. This should speed up the scheduler. | |
235 | TODO: implement moving cond jumps with bookkeeping copies on both targets. | |
236 | TODO: tune the scheduler before RA so it does not create too much pseudos. | |
237 | ||
238 | ||
239 | References: | |
240 | S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with | |
b8698a0f L |
241 | selective scheduling and software pipelining. |
242 | ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997. | |
e855c69d | 243 | |
b8698a0f L |
244 | Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik, |
245 | and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler | |
e855c69d AB |
246 | for GCC. In Proceedings of GCC Developers' Summit 2006. |
247 | ||
b8698a0f | 248 | Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction |
e855c69d AB |
249 | Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop. |
250 | http://rogue.colorado.edu/EPIC7/. | |
b8698a0f | 251 | |
e855c69d AB |
252 | */ |
253 | ||
254 | /* True when pipelining is enabled. */ | |
255 | bool pipelining_p; | |
256 | ||
257 | /* True if bookkeeping is enabled. */ | |
258 | bool bookkeeping_p; | |
259 | ||
260 | /* Maximum number of insns that are eligible for renaming. */ | |
261 | int max_insns_to_rename; | |
262 | \f | |
263 | ||
264 | /* Definitions of local types and macros. */ | |
265 | ||
266 | /* Represents possible outcomes of moving an expression through an insn. */ | |
b8698a0f L |
267 | enum MOVEUP_EXPR_CODE |
268 | { | |
e855c69d | 269 | /* The expression is not changed. */ |
b8698a0f | 270 | MOVEUP_EXPR_SAME, |
e855c69d AB |
271 | |
272 | /* Not changed, but requires a new destination register. */ | |
b8698a0f | 273 | MOVEUP_EXPR_AS_RHS, |
e855c69d AB |
274 | |
275 | /* Cannot be moved. */ | |
b8698a0f | 276 | MOVEUP_EXPR_NULL, |
e855c69d AB |
277 | |
278 | /* Changed (substituted or speculated). */ | |
b8698a0f | 279 | MOVEUP_EXPR_CHANGED |
e855c69d AB |
280 | }; |
281 | ||
282 | /* The container to be passed into rtx search & replace functions. */ | |
283 | struct rtx_search_arg | |
284 | { | |
285 | /* What we are searching for. */ | |
286 | rtx x; | |
287 | ||
288 | /* The occurence counter. */ | |
289 | int n; | |
290 | }; | |
291 | ||
292 | typedef struct rtx_search_arg *rtx_search_arg_p; | |
293 | ||
b8698a0f | 294 | /* This struct contains precomputed hard reg sets that are needed when |
e855c69d | 295 | computing registers available for renaming. */ |
b8698a0f | 296 | struct hard_regs_data |
e855c69d | 297 | { |
b8698a0f | 298 | /* For every mode, this stores registers available for use with |
e855c69d AB |
299 | that mode. */ |
300 | HARD_REG_SET regs_for_mode[NUM_MACHINE_MODES]; | |
301 | ||
302 | /* True when regs_for_mode[mode] is initialized. */ | |
303 | bool regs_for_mode_ok[NUM_MACHINE_MODES]; | |
304 | ||
305 | /* For every register, it has regs that are ok to rename into it. | |
306 | The register in question is always set. If not, this means | |
307 | that the whole set is not computed yet. */ | |
308 | HARD_REG_SET regs_for_rename[FIRST_PSEUDO_REGISTER]; | |
309 | ||
b8698a0f | 310 | /* For every mode, this stores registers not available due to |
e855c69d AB |
311 | call clobbering. */ |
312 | HARD_REG_SET regs_for_call_clobbered[NUM_MACHINE_MODES]; | |
313 | ||
314 | /* All registers that are used or call used. */ | |
315 | HARD_REG_SET regs_ever_used; | |
316 | ||
317 | #ifdef STACK_REGS | |
318 | /* Stack registers. */ | |
319 | HARD_REG_SET stack_regs; | |
320 | #endif | |
321 | }; | |
322 | ||
323 | /* Holds the results of computation of available for renaming and | |
324 | unavailable hard registers. */ | |
325 | struct reg_rename | |
326 | { | |
327 | /* These are unavailable due to calls crossing, globalness, etc. */ | |
328 | HARD_REG_SET unavailable_hard_regs; | |
329 | ||
330 | /* These are *available* for renaming. */ | |
331 | HARD_REG_SET available_for_renaming; | |
332 | ||
333 | /* Whether this code motion path crosses a call. */ | |
334 | bool crosses_call; | |
335 | }; | |
336 | ||
b8698a0f | 337 | /* A global structure that contains the needed information about harg |
e855c69d AB |
338 | regs. */ |
339 | static struct hard_regs_data sel_hrd; | |
340 | \f | |
341 | ||
b8698a0f L |
342 | /* This structure holds local data used in code_motion_path_driver hooks on |
343 | the same or adjacent levels of recursion. Here we keep those parameters | |
344 | that are not used in code_motion_path_driver routine itself, but only in | |
345 | its hooks. Moreover, all parameters that can be modified in hooks are | |
346 | in this structure, so all other parameters passed explicitly to hooks are | |
e855c69d AB |
347 | read-only. */ |
348 | struct cmpd_local_params | |
349 | { | |
350 | /* Local params used in move_op_* functions. */ | |
351 | ||
352 | /* Edges for bookkeeping generation. */ | |
353 | edge e1, e2; | |
354 | ||
355 | /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */ | |
356 | expr_t c_expr_merged, c_expr_local; | |
357 | ||
358 | /* Local params used in fur_* functions. */ | |
359 | /* Copy of the ORIGINAL_INSN list, stores the original insns already | |
360 | found before entering the current level of code_motion_path_driver. */ | |
361 | def_list_t old_original_insns; | |
362 | ||
363 | /* Local params used in move_op_* functions. */ | |
b8698a0f | 364 | /* True when we have removed last insn in the block which was |
e855c69d AB |
365 | also a boundary. Do not update anything or create bookkeeping copies. */ |
366 | BOOL_BITFIELD removed_last_insn : 1; | |
367 | }; | |
368 | ||
369 | /* Stores the static parameters for move_op_* calls. */ | |
370 | struct moveop_static_params | |
371 | { | |
372 | /* Destination register. */ | |
373 | rtx dest; | |
374 | ||
375 | /* Current C_EXPR. */ | |
376 | expr_t c_expr; | |
377 | ||
378 | /* An UID of expr_vliw which is to be moved up. If we find other exprs, | |
379 | they are to be removed. */ | |
380 | int uid; | |
381 | ||
382 | #ifdef ENABLE_CHECKING | |
383 | /* This is initialized to the insn on which the driver stopped its traversal. */ | |
384 | insn_t failed_insn; | |
385 | #endif | |
386 | ||
387 | /* True if we scheduled an insn with different register. */ | |
388 | bool was_renamed; | |
389 | }; | |
390 | ||
391 | /* Stores the static parameters for fur_* calls. */ | |
392 | struct fur_static_params | |
393 | { | |
394 | /* Set of registers unavailable on the code motion path. */ | |
395 | regset used_regs; | |
396 | ||
397 | /* Pointer to the list of original insns definitions. */ | |
398 | def_list_t *original_insns; | |
399 | ||
400 | /* True if a code motion path contains a CALL insn. */ | |
401 | bool crosses_call; | |
402 | }; | |
403 | ||
404 | typedef struct fur_static_params *fur_static_params_p; | |
405 | typedef struct cmpd_local_params *cmpd_local_params_p; | |
406 | typedef struct moveop_static_params *moveop_static_params_p; | |
407 | ||
408 | /* Set of hooks and parameters that determine behaviour specific to | |
409 | move_op or find_used_regs functions. */ | |
410 | struct code_motion_path_driver_info_def | |
411 | { | |
412 | /* Called on enter to the basic block. */ | |
413 | int (*on_enter) (insn_t, cmpd_local_params_p, void *, bool); | |
414 | ||
415 | /* Called when original expr is found. */ | |
416 | void (*orig_expr_found) (insn_t, expr_t, cmpd_local_params_p, void *); | |
417 | ||
418 | /* Called while descending current basic block if current insn is not | |
419 | the original EXPR we're searching for. */ | |
420 | bool (*orig_expr_not_found) (insn_t, av_set_t, void *); | |
421 | ||
422 | /* Function to merge C_EXPRes from different successors. */ | |
423 | void (*merge_succs) (insn_t, insn_t, int, cmpd_local_params_p, void *); | |
424 | ||
425 | /* Function to finalize merge from different successors and possibly | |
426 | deallocate temporary data structures used for merging. */ | |
427 | void (*after_merge_succs) (cmpd_local_params_p, void *); | |
428 | ||
429 | /* Called on the backward stage of recursion to do moveup_expr. | |
430 | Used only with move_op_*. */ | |
431 | void (*ascend) (insn_t, void *); | |
432 | ||
b8698a0f | 433 | /* Called on the ascending pass, before returning from the current basic |
e855c69d AB |
434 | block or from the whole traversal. */ |
435 | void (*at_first_insn) (insn_t, cmpd_local_params_p, void *); | |
436 | ||
b8698a0f | 437 | /* When processing successors in move_op we need only descend into |
e855c69d AB |
438 | SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */ |
439 | int succ_flags; | |
440 | ||
441 | /* The routine name to print in dumps ("move_op" of "find_used_regs"). */ | |
442 | const char *routine_name; | |
443 | }; | |
444 | ||
445 | /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or | |
446 | FUR_HOOKS. */ | |
447 | struct code_motion_path_driver_info_def *code_motion_path_driver_info; | |
448 | ||
449 | /* Set of hooks for performing move_op and find_used_regs routines with | |
450 | code_motion_path_driver. */ | |
c32e2175 | 451 | extern struct code_motion_path_driver_info_def move_op_hooks, fur_hooks; |
e855c69d | 452 | |
b8698a0f L |
453 | /* True if/when we want to emulate Haifa scheduler in the common code. |
454 | This is used in sched_rgn_local_init and in various places in | |
e855c69d AB |
455 | sched-deps.c. */ |
456 | int sched_emulate_haifa_p; | |
457 | ||
458 | /* GLOBAL_LEVEL is used to discard information stored in basic block headers | |
459 | av_sets. Av_set of bb header is valid if its (bb header's) level is equal | |
460 | to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance | |
461 | scheduling window. */ | |
462 | int global_level; | |
463 | ||
464 | /* Current fences. */ | |
465 | flist_t fences; | |
466 | ||
467 | /* True when separable insns should be scheduled as RHSes. */ | |
468 | static bool enable_schedule_as_rhs_p; | |
469 | ||
470 | /* Used in verify_target_availability to assert that target reg is reported | |
471 | unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if | |
b8698a0f | 472 | we haven't scheduled anything on the previous fence. |
e855c69d | 473 | if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can |
b8698a0f | 474 | have more conservative value than the one returned by the |
e855c69d AB |
475 | find_used_regs, thus we shouldn't assert that these values are equal. */ |
476 | static bool scheduled_something_on_previous_fence; | |
477 | ||
478 | /* All newly emitted insns will have their uids greater than this value. */ | |
479 | static int first_emitted_uid; | |
480 | ||
481 | /* Set of basic blocks that are forced to start new ebbs. This is a subset | |
482 | of all the ebb heads. */ | |
483 | static bitmap_head _forced_ebb_heads; | |
484 | bitmap_head *forced_ebb_heads = &_forced_ebb_heads; | |
485 | ||
486 | /* Blocks that need to be rescheduled after pipelining. */ | |
487 | bitmap blocks_to_reschedule = NULL; | |
488 | ||
489 | /* True when the first lv set should be ignored when updating liveness. */ | |
490 | static bool ignore_first = false; | |
491 | ||
492 | /* Number of insns max_issue has initialized data structures for. */ | |
493 | static int max_issue_size = 0; | |
494 | ||
495 | /* Whether we can issue more instructions. */ | |
496 | static int can_issue_more; | |
497 | ||
498 | /* Maximum software lookahead window size, reduced when rescheduling after | |
499 | pipelining. */ | |
500 | static int max_ws; | |
501 | ||
502 | /* Number of insns scheduled in current region. */ | |
503 | static int num_insns_scheduled; | |
504 | ||
505 | /* A vector of expressions is used to be able to sort them. */ | |
506 | DEF_VEC_P(expr_t); | |
507 | DEF_VEC_ALLOC_P(expr_t,heap); | |
508 | static VEC(expr_t, heap) *vec_av_set = NULL; | |
509 | ||
510 | /* A vector of vinsns is used to hold temporary lists of vinsns. */ | |
511 | DEF_VEC_P(vinsn_t); | |
512 | DEF_VEC_ALLOC_P(vinsn_t,heap); | |
513 | typedef VEC(vinsn_t, heap) *vinsn_vec_t; | |
514 | ||
515 | /* This vector has the exprs which may still present in av_sets, but actually | |
516 | can't be moved up due to bookkeeping created during code motion to another | |
517 | fence. See comment near the call to update_and_record_unavailable_insns | |
518 | for the detailed explanations. */ | |
519 | static vinsn_vec_t vec_bookkeeping_blocked_vinsns = NULL; | |
520 | ||
b8698a0f | 521 | /* This vector has vinsns which are scheduled with renaming on the first fence |
e855c69d AB |
522 | and then seen on the second. For expressions with such vinsns, target |
523 | availability information may be wrong. */ | |
524 | static vinsn_vec_t vec_target_unavailable_vinsns = NULL; | |
525 | ||
526 | /* Vector to store temporary nops inserted in move_op to prevent removal | |
527 | of empty bbs. */ | |
528 | DEF_VEC_P(insn_t); | |
529 | DEF_VEC_ALLOC_P(insn_t,heap); | |
530 | static VEC(insn_t, heap) *vec_temp_moveop_nops = NULL; | |
531 | ||
b8698a0f L |
532 | /* These bitmaps record original instructions scheduled on the current |
533 | iteration and bookkeeping copies created by them. */ | |
e855c69d AB |
534 | static bitmap current_originators = NULL; |
535 | static bitmap current_copies = NULL; | |
536 | ||
537 | /* This bitmap marks the blocks visited by code_motion_path_driver so we don't | |
538 | visit them afterwards. */ | |
539 | static bitmap code_motion_visited_blocks = NULL; | |
540 | ||
541 | /* Variables to accumulate different statistics. */ | |
542 | ||
543 | /* The number of bookkeeping copies created. */ | |
544 | static int stat_bookkeeping_copies; | |
545 | ||
546 | /* The number of insns that required bookkeeiping for their scheduling. */ | |
547 | static int stat_insns_needed_bookkeeping; | |
548 | ||
549 | /* The number of insns that got renamed. */ | |
550 | static int stat_renamed_scheduled; | |
551 | ||
552 | /* The number of substitutions made during scheduling. */ | |
553 | static int stat_substitutions_total; | |
554 | \f | |
555 | ||
556 | /* Forward declarations of static functions. */ | |
557 | static bool rtx_ok_for_substitution_p (rtx, rtx); | |
558 | static int sel_rank_for_schedule (const void *, const void *); | |
559 | static av_set_t find_sequential_best_exprs (bnd_t, expr_t, bool); | |
b5b8b0ac | 560 | static basic_block find_block_for_bookkeeping (edge e1, edge e2, bool lax); |
e855c69d AB |
561 | |
562 | static rtx get_dest_from_orig_ops (av_set_t); | |
563 | static basic_block generate_bookkeeping_insn (expr_t, edge, edge); | |
b8698a0f | 564 | static bool find_used_regs (insn_t, av_set_t, regset, struct reg_rename *, |
e855c69d | 565 | def_list_t *); |
72a54528 AM |
566 | static bool move_op (insn_t, av_set_t, expr_t, rtx, expr_t, bool*); |
567 | static int code_motion_path_driver (insn_t, av_set_t, ilist_t, | |
568 | cmpd_local_params_p, void *); | |
e855c69d AB |
569 | static void sel_sched_region_1 (void); |
570 | static void sel_sched_region_2 (int); | |
571 | static av_set_t compute_av_set_inside_bb (insn_t, ilist_t, int, bool); | |
572 | ||
573 | static void debug_state (state_t); | |
574 | \f | |
575 | ||
576 | /* Functions that work with fences. */ | |
577 | ||
578 | /* Advance one cycle on FENCE. */ | |
579 | static void | |
580 | advance_one_cycle (fence_t fence) | |
581 | { | |
582 | unsigned i; | |
583 | int cycle; | |
584 | rtx insn; | |
b8698a0f | 585 | |
e855c69d AB |
586 | advance_state (FENCE_STATE (fence)); |
587 | cycle = ++FENCE_CYCLE (fence); | |
588 | FENCE_ISSUED_INSNS (fence) = 0; | |
589 | FENCE_STARTS_CYCLE_P (fence) = 1; | |
590 | can_issue_more = issue_rate; | |
136e01a3 | 591 | FENCE_ISSUE_MORE (fence) = can_issue_more; |
e855c69d AB |
592 | |
593 | for (i = 0; VEC_iterate (rtx, FENCE_EXECUTING_INSNS (fence), i, insn); ) | |
594 | { | |
595 | if (INSN_READY_CYCLE (insn) < cycle) | |
596 | { | |
597 | remove_from_deps (FENCE_DC (fence), insn); | |
598 | VEC_unordered_remove (rtx, FENCE_EXECUTING_INSNS (fence), i); | |
599 | continue; | |
600 | } | |
601 | i++; | |
602 | } | |
603 | if (sched_verbose >= 2) | |
604 | { | |
605 | sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence)); | |
606 | debug_state (FENCE_STATE (fence)); | |
607 | } | |
608 | } | |
609 | ||
610 | /* Returns true when SUCC in a fallthru bb of INSN, possibly | |
611 | skipping empty basic blocks. */ | |
612 | static bool | |
613 | in_fallthru_bb_p (rtx insn, rtx succ) | |
614 | { | |
615 | basic_block bb = BLOCK_FOR_INSN (insn); | |
0fd4b31d | 616 | edge e; |
e855c69d AB |
617 | |
618 | if (bb == BLOCK_FOR_INSN (succ)) | |
619 | return true; | |
620 | ||
0fd4b31d NF |
621 | e = find_fallthru_edge_from (bb); |
622 | if (e) | |
623 | bb = e->dest; | |
e855c69d AB |
624 | else |
625 | return false; | |
626 | ||
627 | while (sel_bb_empty_p (bb)) | |
628 | bb = bb->next_bb; | |
629 | ||
630 | return bb == BLOCK_FOR_INSN (succ); | |
631 | } | |
632 | ||
b8698a0f | 633 | /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES. |
e855c69d AB |
634 | When a successor will continue a ebb, transfer all parameters of a fence |
635 | to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round | |
636 | of scheduling helping to distinguish between the old and the new code. */ | |
637 | static void | |
638 | extract_new_fences_from (flist_t old_fences, flist_tail_t new_fences, | |
639 | int orig_max_seqno) | |
640 | { | |
641 | bool was_here_p = false; | |
642 | insn_t insn = NULL_RTX; | |
643 | insn_t succ; | |
644 | succ_iterator si; | |
645 | ilist_iterator ii; | |
646 | fence_t fence = FLIST_FENCE (old_fences); | |
647 | basic_block bb; | |
648 | ||
649 | /* Get the only element of FENCE_BNDS (fence). */ | |
650 | FOR_EACH_INSN (insn, ii, FENCE_BNDS (fence)) | |
651 | { | |
652 | gcc_assert (!was_here_p); | |
653 | was_here_p = true; | |
654 | } | |
655 | gcc_assert (was_here_p && insn != NULL_RTX); | |
656 | ||
b8698a0f | 657 | /* When in the "middle" of the block, just move this fence |
e855c69d AB |
658 | to the new list. */ |
659 | bb = BLOCK_FOR_INSN (insn); | |
660 | if (! sel_bb_end_p (insn) | |
b8698a0f | 661 | || (single_succ_p (bb) |
e855c69d AB |
662 | && single_pred_p (single_succ (bb)))) |
663 | { | |
664 | insn_t succ; | |
665 | ||
b8698a0f | 666 | succ = (sel_bb_end_p (insn) |
e855c69d AB |
667 | ? sel_bb_head (single_succ (bb)) |
668 | : NEXT_INSN (insn)); | |
669 | ||
b8698a0f | 670 | if (INSN_SEQNO (succ) > 0 |
e855c69d AB |
671 | && INSN_SEQNO (succ) <= orig_max_seqno |
672 | && INSN_SCHED_TIMES (succ) <= 0) | |
673 | { | |
674 | FENCE_INSN (fence) = succ; | |
675 | move_fence_to_fences (old_fences, new_fences); | |
676 | ||
677 | if (sched_verbose >= 1) | |
b8698a0f | 678 | sel_print ("Fence %d continues as %d[%d] (state continue)\n", |
e855c69d AB |
679 | INSN_UID (insn), INSN_UID (succ), BLOCK_NUM (succ)); |
680 | } | |
681 | return; | |
682 | } | |
683 | ||
684 | /* Otherwise copy fence's structures to (possibly) multiple successors. */ | |
685 | FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS) | |
686 | { | |
687 | int seqno = INSN_SEQNO (succ); | |
688 | ||
689 | if (0 < seqno && seqno <= orig_max_seqno | |
690 | && (pipelining_p || INSN_SCHED_TIMES (succ) <= 0)) | |
691 | { | |
692 | bool b = (in_same_ebb_p (insn, succ) | |
b8698a0f | 693 | || in_fallthru_bb_p (insn, succ)); |
e855c69d AB |
694 | |
695 | if (sched_verbose >= 1) | |
b8698a0f L |
696 | sel_print ("Fence %d continues as %d[%d] (state %s)\n", |
697 | INSN_UID (insn), INSN_UID (succ), | |
e855c69d AB |
698 | BLOCK_NUM (succ), b ? "continue" : "reset"); |
699 | ||
700 | if (b) | |
701 | add_dirty_fence_to_fences (new_fences, succ, fence); | |
702 | else | |
703 | { | |
704 | /* Mark block of the SUCC as head of the new ebb. */ | |
705 | bitmap_set_bit (forced_ebb_heads, BLOCK_NUM (succ)); | |
706 | add_clean_fence_to_fences (new_fences, succ, fence); | |
707 | } | |
708 | } | |
709 | } | |
710 | } | |
711 | \f | |
712 | ||
713 | /* Functions to support substitution. */ | |
714 | ||
b8698a0f L |
715 | /* Returns whether INSN with dependence status DS is eligible for |
716 | substitution, i.e. it's a copy operation x := y, and RHS that is | |
e855c69d AB |
717 | moved up through this insn should be substituted. */ |
718 | static bool | |
719 | can_substitute_through_p (insn_t insn, ds_t ds) | |
720 | { | |
721 | /* We can substitute only true dependencies. */ | |
722 | if ((ds & DEP_OUTPUT) | |
723 | || (ds & DEP_ANTI) | |
724 | || ! INSN_RHS (insn) | |
725 | || ! INSN_LHS (insn)) | |
726 | return false; | |
727 | ||
b8698a0f | 728 | /* Now we just need to make sure the INSN_RHS consists of only one |
e855c69d | 729 | simple REG rtx. */ |
b8698a0f | 730 | if (REG_P (INSN_LHS (insn)) |
e855c69d | 731 | && REG_P (INSN_RHS (insn))) |
b8698a0f | 732 | return true; |
e855c69d AB |
733 | return false; |
734 | } | |
735 | ||
b8698a0f | 736 | /* Substitute all occurences of INSN's destination in EXPR' vinsn with INSN's |
e855c69d AB |
737 | source (if INSN is eligible for substitution). Returns TRUE if |
738 | substitution was actually performed, FALSE otherwise. Substitution might | |
739 | be not performed because it's either EXPR' vinsn doesn't contain INSN's | |
b8698a0f | 740 | destination or the resulting insn is invalid for the target machine. |
e855c69d AB |
741 | When UNDO is true, perform unsubstitution instead (the difference is in |
742 | the part of rtx on which validate_replace_rtx is called). */ | |
743 | static bool | |
744 | substitute_reg_in_expr (expr_t expr, insn_t insn, bool undo) | |
745 | { | |
746 | rtx *where; | |
747 | bool new_insn_valid; | |
748 | vinsn_t *vi = &EXPR_VINSN (expr); | |
749 | bool has_rhs = VINSN_RHS (*vi) != NULL; | |
750 | rtx old, new_rtx; | |
751 | ||
752 | /* Do not try to replace in SET_DEST. Although we'll choose new | |
b8698a0f | 753 | register for the RHS, we don't want to change RHS' original reg. |
e855c69d | 754 | If the insn is not SET, we may still be able to substitute something |
b8698a0f | 755 | in it, and if we're here (don't have deps), it doesn't write INSN's |
e855c69d AB |
756 | dest. */ |
757 | where = (has_rhs | |
758 | ? &VINSN_RHS (*vi) | |
759 | : &PATTERN (VINSN_INSN_RTX (*vi))); | |
760 | old = undo ? INSN_RHS (insn) : INSN_LHS (insn); | |
761 | ||
762 | /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */ | |
763 | if (rtx_ok_for_substitution_p (old, *where)) | |
764 | { | |
765 | rtx new_insn; | |
766 | rtx *where_replace; | |
767 | ||
768 | /* We should copy these rtxes before substitution. */ | |
769 | new_rtx = copy_rtx (undo ? INSN_LHS (insn) : INSN_RHS (insn)); | |
770 | new_insn = create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi)); | |
771 | ||
b8698a0f | 772 | /* Where we'll replace. |
e855c69d AB |
773 | WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be |
774 | used instead of SET_SRC. */ | |
775 | where_replace = (has_rhs | |
776 | ? &SET_SRC (PATTERN (new_insn)) | |
777 | : &PATTERN (new_insn)); | |
778 | ||
b8698a0f L |
779 | new_insn_valid |
780 | = validate_replace_rtx_part_nosimplify (old, new_rtx, where_replace, | |
e855c69d AB |
781 | new_insn); |
782 | ||
783 | /* ??? Actually, constrain_operands result depends upon choice of | |
784 | destination register. E.g. if we allow single register to be an rhs, | |
b8698a0f | 785 | and if we try to move dx=ax(as rhs) through ax=dx, we'll result |
e855c69d AB |
786 | in invalid insn dx=dx, so we'll loose this rhs here. |
787 | Just can't come up with significant testcase for this, so just | |
788 | leaving it for now. */ | |
789 | if (new_insn_valid) | |
790 | { | |
b8698a0f | 791 | change_vinsn_in_expr (expr, |
e855c69d AB |
792 | create_vinsn_from_insn_rtx (new_insn, false)); |
793 | ||
b8698a0f | 794 | /* Do not allow clobbering the address register of speculative |
e855c69d AB |
795 | insns. */ |
796 | if ((EXPR_SPEC_DONE_DS (expr) & SPECULATIVE) | |
b8698a0f | 797 | && bitmap_bit_p (VINSN_REG_USES (EXPR_VINSN (expr)), |
e855c69d AB |
798 | expr_dest_regno (expr))) |
799 | EXPR_TARGET_AVAILABLE (expr) = false; | |
800 | ||
801 | return true; | |
802 | } | |
803 | else | |
804 | return false; | |
805 | } | |
806 | else | |
807 | return false; | |
808 | } | |
809 | ||
810 | /* Helper function for count_occurences_equiv. */ | |
b8698a0f | 811 | static int |
e855c69d AB |
812 | count_occurrences_1 (rtx *cur_rtx, void *arg) |
813 | { | |
814 | rtx_search_arg_p p = (rtx_search_arg_p) arg; | |
815 | ||
816 | /* The last param FOR_GCSE is true, because otherwise it performs excessive | |
817 | substitutions like | |
818 | r8 = r33 | |
819 | r16 = r33 | |
820 | for the last insn it presumes r33 equivalent to r8, so it changes it to | |
821 | r33. Actually, there's no change, but it spoils debugging. */ | |
822 | if (exp_equiv_p (*cur_rtx, p->x, 0, true)) | |
823 | { | |
824 | /* Bail out if we occupy more than one register. */ | |
825 | if (REG_P (*cur_rtx) | |
72a54528 | 826 | && HARD_REGISTER_P (*cur_rtx) |
e855c69d AB |
827 | && hard_regno_nregs[REGNO(*cur_rtx)][GET_MODE (*cur_rtx)] > 1) |
828 | { | |
829 | p->n = 0; | |
830 | return 1; | |
831 | } | |
832 | ||
833 | p->n++; | |
834 | ||
835 | /* Do not traverse subexprs. */ | |
836 | return -1; | |
837 | } | |
838 | ||
839 | if (GET_CODE (*cur_rtx) == SUBREG | |
840 | && REG_P (p->x) | |
5e841c82 AB |
841 | && (!REG_P (SUBREG_REG (*cur_rtx)) |
842 | || REGNO (SUBREG_REG (*cur_rtx)) == REGNO (p->x))) | |
e855c69d AB |
843 | { |
844 | /* ??? Do not support substituting regs inside subregs. In that case, | |
b8698a0f | 845 | simplify_subreg will be called by validate_replace_rtx, and |
e855c69d AB |
846 | unsubstitution will fail later. */ |
847 | p->n = 0; | |
848 | return 1; | |
849 | } | |
850 | ||
851 | /* Continue search. */ | |
852 | return 0; | |
853 | } | |
854 | ||
b8698a0f | 855 | /* Return the number of places WHAT appears within WHERE. |
e855c69d | 856 | Bail out when we found a reference occupying several hard registers. */ |
b8698a0f | 857 | static int |
e855c69d AB |
858 | count_occurrences_equiv (rtx what, rtx where) |
859 | { | |
860 | struct rtx_search_arg arg; | |
861 | ||
862 | arg.x = what; | |
863 | arg.n = 0; | |
864 | ||
865 | for_each_rtx (&where, &count_occurrences_1, (void *) &arg); | |
866 | ||
867 | return arg.n; | |
868 | } | |
869 | ||
870 | /* Returns TRUE if WHAT is found in WHERE rtx tree. */ | |
871 | static bool | |
872 | rtx_ok_for_substitution_p (rtx what, rtx where) | |
873 | { | |
874 | return (count_occurrences_equiv (what, where) > 0); | |
875 | } | |
876 | \f | |
877 | ||
878 | /* Functions to support register renaming. */ | |
879 | ||
880 | /* Substitute VI's set source with REGNO. Returns newly created pattern | |
881 | that has REGNO as its source. */ | |
882 | static rtx | |
883 | create_insn_rtx_with_rhs (vinsn_t vi, rtx rhs_rtx) | |
884 | { | |
885 | rtx lhs_rtx; | |
886 | rtx pattern; | |
887 | rtx insn_rtx; | |
888 | ||
889 | lhs_rtx = copy_rtx (VINSN_LHS (vi)); | |
890 | ||
891 | pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx); | |
892 | insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX); | |
893 | ||
894 | return insn_rtx; | |
895 | } | |
896 | ||
b8698a0f | 897 | /* Returns whether INSN's src can be replaced with register number |
e855c69d AB |
898 | NEW_SRC_REG. E.g. the following insn is valid for i386: |
899 | ||
b8698a0f | 900 | (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337 |
e855c69d AB |
901 | (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp) |
902 | (reg:SI 0 ax [orig:770 c1 ] [770])) | |
903 | (const_int 288 [0x120])) [0 str S1 A8]) | |
904 | (const_int 0 [0x0])) 43 {*movqi_1} (nil) | |
905 | (nil)) | |
906 | ||
907 | But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid | |
b8698a0f | 908 | because of operand constraints: |
e855c69d AB |
909 | |
910 | (define_insn "*movqi_1" | |
911 | [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m") | |
912 | (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn") | |
913 | )] | |
b8698a0f L |
914 | |
915 | So do constrain_operands here, before choosing NEW_SRC_REG as best | |
e855c69d AB |
916 | reg for rhs. */ |
917 | ||
918 | static bool | |
919 | replace_src_with_reg_ok_p (insn_t insn, rtx new_src_reg) | |
920 | { | |
921 | vinsn_t vi = INSN_VINSN (insn); | |
922 | enum machine_mode mode; | |
923 | rtx dst_loc; | |
924 | bool res; | |
925 | ||
926 | gcc_assert (VINSN_SEPARABLE_P (vi)); | |
927 | ||
928 | get_dest_and_mode (insn, &dst_loc, &mode); | |
929 | gcc_assert (mode == GET_MODE (new_src_reg)); | |
930 | ||
931 | if (REG_P (dst_loc) && REGNO (new_src_reg) == REGNO (dst_loc)) | |
932 | return true; | |
933 | ||
934 | /* See whether SET_SRC can be replaced with this register. */ | |
935 | validate_change (insn, &SET_SRC (PATTERN (insn)), new_src_reg, 1); | |
936 | res = verify_changes (0); | |
937 | cancel_changes (0); | |
938 | ||
939 | return res; | |
940 | } | |
941 | ||
942 | /* Returns whether INSN still be valid after replacing it's DEST with | |
943 | register NEW_REG. */ | |
944 | static bool | |
945 | replace_dest_with_reg_ok_p (insn_t insn, rtx new_reg) | |
946 | { | |
947 | vinsn_t vi = INSN_VINSN (insn); | |
948 | bool res; | |
949 | ||
950 | /* We should deal here only with separable insns. */ | |
951 | gcc_assert (VINSN_SEPARABLE_P (vi)); | |
952 | gcc_assert (GET_MODE (VINSN_LHS (vi)) == GET_MODE (new_reg)); | |
953 | ||
954 | /* See whether SET_DEST can be replaced with this register. */ | |
955 | validate_change (insn, &SET_DEST (PATTERN (insn)), new_reg, 1); | |
956 | res = verify_changes (0); | |
957 | cancel_changes (0); | |
958 | ||
959 | return res; | |
960 | } | |
961 | ||
962 | /* Create a pattern with rhs of VI and lhs of LHS_RTX. */ | |
963 | static rtx | |
964 | create_insn_rtx_with_lhs (vinsn_t vi, rtx lhs_rtx) | |
965 | { | |
966 | rtx rhs_rtx; | |
967 | rtx pattern; | |
968 | rtx insn_rtx; | |
969 | ||
970 | rhs_rtx = copy_rtx (VINSN_RHS (vi)); | |
971 | ||
972 | pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx); | |
973 | insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX); | |
974 | ||
975 | return insn_rtx; | |
976 | } | |
977 | ||
b8698a0f | 978 | /* Substitute lhs in the given expression EXPR for the register with number |
e855c69d AB |
979 | NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */ |
980 | static void | |
981 | replace_dest_with_reg_in_expr (expr_t expr, rtx new_reg) | |
982 | { | |
983 | rtx insn_rtx; | |
984 | vinsn_t vinsn; | |
985 | ||
986 | insn_rtx = create_insn_rtx_with_lhs (EXPR_VINSN (expr), new_reg); | |
987 | vinsn = create_vinsn_from_insn_rtx (insn_rtx, false); | |
988 | ||
989 | change_vinsn_in_expr (expr, vinsn); | |
990 | EXPR_WAS_RENAMED (expr) = 1; | |
991 | EXPR_TARGET_AVAILABLE (expr) = 1; | |
992 | } | |
993 | ||
994 | /* Returns whether VI writes either one of the USED_REGS registers or, | |
995 | if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */ | |
996 | static bool | |
b8698a0f | 997 | vinsn_writes_one_of_regs_p (vinsn_t vi, regset used_regs, |
e855c69d AB |
998 | HARD_REG_SET unavailable_hard_regs) |
999 | { | |
1000 | unsigned regno; | |
1001 | reg_set_iterator rsi; | |
1002 | ||
1003 | EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi), 0, regno, rsi) | |
1004 | { | |
1005 | if (REGNO_REG_SET_P (used_regs, regno)) | |
1006 | return true; | |
1007 | if (HARD_REGISTER_NUM_P (regno) | |
1008 | && TEST_HARD_REG_BIT (unavailable_hard_regs, regno)) | |
1009 | return true; | |
1010 | } | |
1011 | ||
1012 | EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi), 0, regno, rsi) | |
1013 | { | |
1014 | if (REGNO_REG_SET_P (used_regs, regno)) | |
1015 | return true; | |
1016 | if (HARD_REGISTER_NUM_P (regno) | |
1017 | && TEST_HARD_REG_BIT (unavailable_hard_regs, regno)) | |
1018 | return true; | |
1019 | } | |
1020 | ||
1021 | return false; | |
1022 | } | |
1023 | ||
b8698a0f | 1024 | /* Returns register class of the output register in INSN. |
e855c69d AB |
1025 | Returns NO_REGS for call insns because some targets have constraints on |
1026 | destination register of a call insn. | |
b8698a0f | 1027 | |
e855c69d AB |
1028 | Code adopted from regrename.c::build_def_use. */ |
1029 | static enum reg_class | |
1030 | get_reg_class (rtx insn) | |
1031 | { | |
1032 | int alt, i, n_ops; | |
1033 | ||
1034 | extract_insn (insn); | |
1035 | if (! constrain_operands (1)) | |
1036 | fatal_insn_not_found (insn); | |
1037 | preprocess_constraints (); | |
1038 | alt = which_alternative; | |
1039 | n_ops = recog_data.n_operands; | |
1040 | ||
1041 | for (i = 0; i < n_ops; ++i) | |
1042 | { | |
1043 | int matches = recog_op_alt[i][alt].matches; | |
1044 | if (matches >= 0) | |
1045 | recog_op_alt[i][alt].cl = recog_op_alt[matches][alt].cl; | |
1046 | } | |
1047 | ||
1048 | if (asm_noperands (PATTERN (insn)) > 0) | |
1049 | { | |
1050 | for (i = 0; i < n_ops; i++) | |
1051 | if (recog_data.operand_type[i] == OP_OUT) | |
1052 | { | |
1053 | rtx *loc = recog_data.operand_loc[i]; | |
1054 | rtx op = *loc; | |
1055 | enum reg_class cl = recog_op_alt[i][alt].cl; | |
1056 | ||
1057 | if (REG_P (op) | |
1058 | && REGNO (op) == ORIGINAL_REGNO (op)) | |
1059 | continue; | |
1060 | ||
1061 | return cl; | |
1062 | } | |
1063 | } | |
1064 | else if (!CALL_P (insn)) | |
1065 | { | |
1066 | for (i = 0; i < n_ops + recog_data.n_dups; i++) | |
1067 | { | |
1068 | int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops]; | |
1069 | enum reg_class cl = recog_op_alt[opn][alt].cl; | |
b8698a0f | 1070 | |
e855c69d AB |
1071 | if (recog_data.operand_type[opn] == OP_OUT || |
1072 | recog_data.operand_type[opn] == OP_INOUT) | |
1073 | return cl; | |
1074 | } | |
1075 | } | |
1076 | ||
1077 | /* Insns like | |
1078 | (insn (set (reg:CCZ 17 flags) (compare:CCZ ...))) | |
1079 | may result in returning NO_REGS, cause flags is written implicitly through | |
1080 | CMP insn, which has no OP_OUT | OP_INOUT operands. */ | |
1081 | return NO_REGS; | |
1082 | } | |
1083 | ||
1084 | #ifdef HARD_REGNO_RENAME_OK | |
1085 | /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */ | |
1086 | static void | |
1087 | init_hard_regno_rename (int regno) | |
1088 | { | |
1089 | int cur_reg; | |
1090 | ||
1091 | SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], regno); | |
1092 | ||
1093 | for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++) | |
1094 | { | |
1095 | /* We are not interested in renaming in other regs. */ | |
1096 | if (!TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg)) | |
1097 | continue; | |
1098 | ||
1099 | if (HARD_REGNO_RENAME_OK (regno, cur_reg)) | |
1100 | SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], cur_reg); | |
1101 | } | |
1102 | } | |
1103 | #endif | |
1104 | ||
b8698a0f | 1105 | /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs |
e855c69d AB |
1106 | data first. */ |
1107 | static inline bool | |
a20d7130 | 1108 | sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED, int to ATTRIBUTE_UNUSED) |
e855c69d AB |
1109 | { |
1110 | #ifdef HARD_REGNO_RENAME_OK | |
1111 | /* Check whether this is all calculated. */ | |
1112 | if (TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], from)) | |
1113 | return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to); | |
1114 | ||
1115 | init_hard_regno_rename (from); | |
1116 | ||
1117 | return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to); | |
1118 | #else | |
1119 | return true; | |
1120 | #endif | |
1121 | } | |
1122 | ||
1123 | /* Calculate set of registers that are capable of holding MODE. */ | |
1124 | static void | |
1125 | init_regs_for_mode (enum machine_mode mode) | |
1126 | { | |
1127 | int cur_reg; | |
b8698a0f | 1128 | |
e855c69d AB |
1129 | CLEAR_HARD_REG_SET (sel_hrd.regs_for_mode[mode]); |
1130 | CLEAR_HARD_REG_SET (sel_hrd.regs_for_call_clobbered[mode]); | |
1131 | ||
1132 | for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++) | |
1133 | { | |
1134 | int nregs = hard_regno_nregs[cur_reg][mode]; | |
1135 | int i; | |
b8698a0f | 1136 | |
e855c69d AB |
1137 | for (i = nregs - 1; i >= 0; --i) |
1138 | if (fixed_regs[cur_reg + i] | |
1139 | || global_regs[cur_reg + i] | |
b8698a0f | 1140 | /* Can't use regs which aren't saved by |
e855c69d AB |
1141 | the prologue. */ |
1142 | || !TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg + i) | |
8fd0a474 AM |
1143 | /* Can't use regs with non-null REG_BASE_VALUE, because adjusting |
1144 | it affects aliasing globally and invalidates all AV sets. */ | |
1145 | || get_reg_base_value (cur_reg + i) | |
e855c69d AB |
1146 | #ifdef LEAF_REGISTERS |
1147 | /* We can't use a non-leaf register if we're in a | |
1148 | leaf function. */ | |
1149 | || (current_function_is_leaf | |
1150 | && !LEAF_REGISTERS[cur_reg + i]) | |
1151 | #endif | |
1152 | ) | |
1153 | break; | |
b8698a0f L |
1154 | |
1155 | if (i >= 0) | |
e855c69d | 1156 | continue; |
b8698a0f | 1157 | |
e855c69d AB |
1158 | /* See whether it accepts all modes that occur in |
1159 | original insns. */ | |
1160 | if (! HARD_REGNO_MODE_OK (cur_reg, mode)) | |
1161 | continue; | |
b8698a0f | 1162 | |
e855c69d | 1163 | if (HARD_REGNO_CALL_PART_CLOBBERED (cur_reg, mode)) |
b8698a0f | 1164 | SET_HARD_REG_BIT (sel_hrd.regs_for_call_clobbered[mode], |
e855c69d | 1165 | cur_reg); |
b8698a0f L |
1166 | |
1167 | /* If the CUR_REG passed all the checks above, | |
e855c69d AB |
1168 | then it's ok. */ |
1169 | SET_HARD_REG_BIT (sel_hrd.regs_for_mode[mode], cur_reg); | |
1170 | } | |
1171 | ||
1172 | sel_hrd.regs_for_mode_ok[mode] = true; | |
1173 | } | |
1174 | ||
1175 | /* Init all register sets gathered in HRD. */ | |
1176 | static void | |
1177 | init_hard_regs_data (void) | |
1178 | { | |
1179 | int cur_reg = 0; | |
32e8bb8e | 1180 | int cur_mode = 0; |
e855c69d AB |
1181 | |
1182 | CLEAR_HARD_REG_SET (sel_hrd.regs_ever_used); | |
1183 | for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++) | |
1184 | if (df_regs_ever_live_p (cur_reg) || call_used_regs[cur_reg]) | |
1185 | SET_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg); | |
b8698a0f L |
1186 | |
1187 | /* Initialize registers that are valid based on mode when this is | |
e855c69d AB |
1188 | really needed. */ |
1189 | for (cur_mode = 0; cur_mode < NUM_MACHINE_MODES; cur_mode++) | |
1190 | sel_hrd.regs_for_mode_ok[cur_mode] = false; | |
b8698a0f | 1191 | |
e855c69d AB |
1192 | /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */ |
1193 | for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++) | |
1194 | CLEAR_HARD_REG_SET (sel_hrd.regs_for_rename[cur_reg]); | |
1195 | ||
1196 | #ifdef STACK_REGS | |
1197 | CLEAR_HARD_REG_SET (sel_hrd.stack_regs); | |
1198 | ||
1199 | for (cur_reg = FIRST_STACK_REG; cur_reg <= LAST_STACK_REG; cur_reg++) | |
1200 | SET_HARD_REG_BIT (sel_hrd.stack_regs, cur_reg); | |
1201 | #endif | |
b8698a0f | 1202 | } |
e855c69d | 1203 | |
b8698a0f | 1204 | /* Mark hardware regs in REG_RENAME_P that are not suitable |
e855c69d AB |
1205 | for renaming rhs in INSN due to hardware restrictions (register class, |
1206 | modes compatibility etc). This doesn't affect original insn's dest reg, | |
1207 | if it isn't in USED_REGS. DEF is a definition insn of rhs for which the | |
1208 | destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM. | |
1209 | Registers that are in used_regs are always marked in | |
1210 | unavailable_hard_regs as well. */ | |
1211 | ||
1212 | static void | |
1213 | mark_unavailable_hard_regs (def_t def, struct reg_rename *reg_rename_p, | |
1214 | regset used_regs ATTRIBUTE_UNUSED) | |
1215 | { | |
1216 | enum machine_mode mode; | |
1217 | enum reg_class cl = NO_REGS; | |
1218 | rtx orig_dest; | |
1219 | unsigned cur_reg, regno; | |
1220 | hard_reg_set_iterator hrsi; | |
1221 | ||
1222 | gcc_assert (GET_CODE (PATTERN (def->orig_insn)) == SET); | |
1223 | gcc_assert (reg_rename_p); | |
1224 | ||
1225 | orig_dest = SET_DEST (PATTERN (def->orig_insn)); | |
b8698a0f | 1226 | |
e855c69d AB |
1227 | /* We have decided not to rename 'mem = something;' insns, as 'something' |
1228 | is usually a register. */ | |
1229 | if (!REG_P (orig_dest)) | |
1230 | return; | |
1231 | ||
1232 | regno = REGNO (orig_dest); | |
1233 | ||
1234 | /* If before reload, don't try to work with pseudos. */ | |
1235 | if (!reload_completed && !HARD_REGISTER_NUM_P (regno)) | |
1236 | return; | |
1237 | ||
0c94f956 AM |
1238 | if (reload_completed) |
1239 | cl = get_reg_class (def->orig_insn); | |
e855c69d | 1240 | |
0c94f956 AM |
1241 | /* Stop if the original register is one of the fixed_regs, global_regs or |
1242 | frame pointer, or we could not discover its class. */ | |
b8698a0f | 1243 | if (fixed_regs[regno] |
e855c69d | 1244 | || global_regs[regno] |
e3339d0f | 1245 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER |
0c94f956 | 1246 | || (frame_pointer_needed && regno == HARD_FRAME_POINTER_REGNUM) |
e855c69d | 1247 | #else |
0c94f956 | 1248 | || (frame_pointer_needed && regno == FRAME_POINTER_REGNUM) |
e855c69d | 1249 | #endif |
0c94f956 | 1250 | || (reload_completed && cl == NO_REGS)) |
e855c69d AB |
1251 | { |
1252 | SET_HARD_REG_SET (reg_rename_p->unavailable_hard_regs); | |
1253 | ||
1254 | /* Give a chance for original register, if it isn't in used_regs. */ | |
1255 | if (!def->crosses_call) | |
1256 | CLEAR_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno); | |
1257 | ||
1258 | return; | |
1259 | } | |
1260 | ||
1261 | /* If something allocated on stack in this function, mark frame pointer | |
b8698a0f | 1262 | register unavailable, considering also modes. |
e855c69d AB |
1263 | FIXME: it is enough to do this once per all original defs. */ |
1264 | if (frame_pointer_needed) | |
1265 | { | |
d108e679 AS |
1266 | add_to_hard_reg_set (®_rename_p->unavailable_hard_regs, |
1267 | Pmode, FRAME_POINTER_REGNUM); | |
e855c69d | 1268 | |
d108e679 AS |
1269 | if (!HARD_FRAME_POINTER_IS_FRAME_POINTER) |
1270 | add_to_hard_reg_set (®_rename_p->unavailable_hard_regs, | |
1271 | Pmode, HARD_FRAME_POINTER_IS_FRAME_POINTER); | |
e855c69d AB |
1272 | } |
1273 | ||
1274 | #ifdef STACK_REGS | |
1275 | /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS | |
1276 | is equivalent to as if all stack regs were in this set. | |
1277 | I.e. no stack register can be renamed, and even if it's an original | |
b8698a0f L |
1278 | register here we make sure it won't be lifted over it's previous def |
1279 | (it's previous def will appear as if it's a FIRST_STACK_REG def. | |
e855c69d AB |
1280 | The HARD_REGNO_RENAME_OK covers other cases in condition below. */ |
1281 | if (IN_RANGE (REGNO (orig_dest), FIRST_STACK_REG, LAST_STACK_REG) | |
b8698a0f L |
1282 | && REGNO_REG_SET_P (used_regs, FIRST_STACK_REG)) |
1283 | IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs, | |
e855c69d | 1284 | sel_hrd.stack_regs); |
b8698a0f | 1285 | #endif |
e855c69d | 1286 | |
b8698a0f | 1287 | /* If there's a call on this path, make regs from call_used_reg_set |
e855c69d AB |
1288 | unavailable. */ |
1289 | if (def->crosses_call) | |
b8698a0f | 1290 | IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs, |
e855c69d AB |
1291 | call_used_reg_set); |
1292 | ||
b8698a0f | 1293 | /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call, |
e855c69d AB |
1294 | but not register classes. */ |
1295 | if (!reload_completed) | |
1296 | return; | |
1297 | ||
b8698a0f | 1298 | /* Leave regs as 'available' only from the current |
e855c69d | 1299 | register class. */ |
e855c69d AB |
1300 | COPY_HARD_REG_SET (reg_rename_p->available_for_renaming, |
1301 | reg_class_contents[cl]); | |
1302 | ||
0c94f956 AM |
1303 | mode = GET_MODE (orig_dest); |
1304 | ||
e855c69d AB |
1305 | /* Leave only registers available for this mode. */ |
1306 | if (!sel_hrd.regs_for_mode_ok[mode]) | |
1307 | init_regs_for_mode (mode); | |
b8698a0f | 1308 | AND_HARD_REG_SET (reg_rename_p->available_for_renaming, |
e855c69d AB |
1309 | sel_hrd.regs_for_mode[mode]); |
1310 | ||
1311 | /* Exclude registers that are partially call clobbered. */ | |
1312 | if (def->crosses_call | |
1313 | && ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)) | |
b8698a0f | 1314 | AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming, |
e855c69d AB |
1315 | sel_hrd.regs_for_call_clobbered[mode]); |
1316 | ||
1317 | /* Leave only those that are ok to rename. */ | |
1318 | EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming, | |
1319 | 0, cur_reg, hrsi) | |
1320 | { | |
1321 | int nregs; | |
1322 | int i; | |
1323 | ||
1324 | nregs = hard_regno_nregs[cur_reg][mode]; | |
1325 | gcc_assert (nregs > 0); | |
1326 | ||
1327 | for (i = nregs - 1; i >= 0; --i) | |
1328 | if (! sel_hard_regno_rename_ok (regno + i, cur_reg + i)) | |
1329 | break; | |
1330 | ||
b8698a0f L |
1331 | if (i >= 0) |
1332 | CLEAR_HARD_REG_BIT (reg_rename_p->available_for_renaming, | |
e855c69d AB |
1333 | cur_reg); |
1334 | } | |
1335 | ||
b8698a0f | 1336 | AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming, |
e855c69d AB |
1337 | reg_rename_p->unavailable_hard_regs); |
1338 | ||
1339 | /* Regno is always ok from the renaming part of view, but it really | |
1340 | could be in *unavailable_hard_regs already, so set it here instead | |
1341 | of there. */ | |
1342 | SET_HARD_REG_BIT (reg_rename_p->available_for_renaming, regno); | |
1343 | } | |
1344 | ||
1345 | /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the | |
1346 | best register more recently than REG2. */ | |
1347 | static int reg_rename_tick[FIRST_PSEUDO_REGISTER]; | |
1348 | ||
1349 | /* Indicates the number of times renaming happened before the current one. */ | |
1350 | static int reg_rename_this_tick; | |
1351 | ||
b8698a0f | 1352 | /* Choose the register among free, that is suitable for storing |
e855c69d AB |
1353 | the rhs value. |
1354 | ||
1355 | ORIGINAL_INSNS is the list of insns where the operation (rhs) | |
b8698a0f L |
1356 | originally appears. There could be multiple original operations |
1357 | for single rhs since we moving it up and merging along different | |
e855c69d AB |
1358 | paths. |
1359 | ||
1360 | Some code is adapted from regrename.c (regrename_optimize). | |
1361 | If original register is available, function returns it. | |
1362 | Otherwise it performs the checks, so the new register should | |
1363 | comply with the following: | |
b8698a0f | 1364 | - it should not violate any live ranges (such registers are in |
e855c69d AB |
1365 | REG_RENAME_P->available_for_renaming set); |
1366 | - it should not be in the HARD_REGS_USED regset; | |
1367 | - it should be in the class compatible with original uses; | |
1368 | - it should not be clobbered through reference with different mode; | |
b8698a0f | 1369 | - if we're in the leaf function, then the new register should |
e855c69d AB |
1370 | not be in the LEAF_REGISTERS; |
1371 | - etc. | |
1372 | ||
1373 | If several registers meet the conditions, the register with smallest | |
1374 | tick is returned to achieve more even register allocation. | |
1375 | ||
1376 | If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true. | |
1377 | ||
1378 | If no register satisfies the above conditions, NULL_RTX is returned. */ | |
1379 | static rtx | |
b8698a0f L |
1380 | choose_best_reg_1 (HARD_REG_SET hard_regs_used, |
1381 | struct reg_rename *reg_rename_p, | |
e855c69d AB |
1382 | def_list_t original_insns, bool *is_orig_reg_p_ptr) |
1383 | { | |
1384 | int best_new_reg; | |
1385 | unsigned cur_reg; | |
1386 | enum machine_mode mode = VOIDmode; | |
1387 | unsigned regno, i, n; | |
1388 | hard_reg_set_iterator hrsi; | |
1389 | def_list_iterator di; | |
1390 | def_t def; | |
1391 | ||
1392 | /* If original register is available, return it. */ | |
1393 | *is_orig_reg_p_ptr = true; | |
1394 | ||
1395 | FOR_EACH_DEF (def, di, original_insns) | |
1396 | { | |
1397 | rtx orig_dest = SET_DEST (PATTERN (def->orig_insn)); | |
1398 | ||
1399 | gcc_assert (REG_P (orig_dest)); | |
1400 | ||
b8698a0f | 1401 | /* Check that all original operations have the same mode. |
e855c69d | 1402 | This is done for the next loop; if we'd return from this |
b8698a0f | 1403 | loop, we'd check only part of them, but in this case |
e855c69d AB |
1404 | it doesn't matter. */ |
1405 | if (mode == VOIDmode) | |
1406 | mode = GET_MODE (orig_dest); | |
1407 | gcc_assert (mode == GET_MODE (orig_dest)); | |
1408 | ||
1409 | regno = REGNO (orig_dest); | |
1410 | for (i = 0, n = hard_regno_nregs[regno][mode]; i < n; i++) | |
1411 | if (TEST_HARD_REG_BIT (hard_regs_used, regno + i)) | |
1412 | break; | |
1413 | ||
1414 | /* All hard registers are available. */ | |
1415 | if (i == n) | |
1416 | { | |
1417 | gcc_assert (mode != VOIDmode); | |
b8698a0f | 1418 | |
e855c69d AB |
1419 | /* Hard registers should not be shared. */ |
1420 | return gen_rtx_REG (mode, regno); | |
1421 | } | |
1422 | } | |
b8698a0f | 1423 | |
e855c69d AB |
1424 | *is_orig_reg_p_ptr = false; |
1425 | best_new_reg = -1; | |
b8698a0f L |
1426 | |
1427 | /* Among all available regs choose the register that was | |
e855c69d AB |
1428 | allocated earliest. */ |
1429 | EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming, | |
1430 | 0, cur_reg, hrsi) | |
1431 | if (! TEST_HARD_REG_BIT (hard_regs_used, cur_reg)) | |
1432 | { | |
a9ced68b AM |
1433 | /* Check that all hard regs for mode are available. */ |
1434 | for (i = 1, n = hard_regno_nregs[cur_reg][mode]; i < n; i++) | |
1435 | if (TEST_HARD_REG_BIT (hard_regs_used, cur_reg + i) | |
1436 | || !TEST_HARD_REG_BIT (reg_rename_p->available_for_renaming, | |
1437 | cur_reg + i)) | |
1438 | break; | |
1439 | ||
1440 | if (i < n) | |
1441 | continue; | |
1442 | ||
e855c69d AB |
1443 | /* All hard registers are available. */ |
1444 | if (best_new_reg < 0 | |
1445 | || reg_rename_tick[cur_reg] < reg_rename_tick[best_new_reg]) | |
1446 | { | |
1447 | best_new_reg = cur_reg; | |
b8698a0f | 1448 | |
e855c69d AB |
1449 | /* Return immediately when we know there's no better reg. */ |
1450 | if (! reg_rename_tick[best_new_reg]) | |
1451 | break; | |
1452 | } | |
1453 | } | |
1454 | ||
1455 | if (best_new_reg >= 0) | |
1456 | { | |
1457 | /* Use the check from the above loop. */ | |
1458 | gcc_assert (mode != VOIDmode); | |
1459 | return gen_rtx_REG (mode, best_new_reg); | |
1460 | } | |
1461 | ||
1462 | return NULL_RTX; | |
1463 | } | |
1464 | ||
1465 | /* A wrapper around choose_best_reg_1 () to verify that we make correct | |
1466 | assumptions about available registers in the function. */ | |
1467 | static rtx | |
b8698a0f | 1468 | choose_best_reg (HARD_REG_SET hard_regs_used, struct reg_rename *reg_rename_p, |
e855c69d AB |
1469 | def_list_t original_insns, bool *is_orig_reg_p_ptr) |
1470 | { | |
b8698a0f | 1471 | rtx best_reg = choose_best_reg_1 (hard_regs_used, reg_rename_p, |
e855c69d AB |
1472 | original_insns, is_orig_reg_p_ptr); |
1473 | ||
a9ced68b | 1474 | /* FIXME loop over hard_regno_nregs here. */ |
e855c69d AB |
1475 | gcc_assert (best_reg == NULL_RTX |
1476 | || TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, REGNO (best_reg))); | |
1477 | ||
1478 | return best_reg; | |
1479 | } | |
1480 | ||
b8698a0f | 1481 | /* Choose the pseudo register for storing rhs value. As this is supposed |
e855c69d | 1482 | to work before reload, we return either the original register or make |
b8698a0f L |
1483 | the new one. The parameters are the same that in choose_nest_reg_1 |
1484 | functions, except that USED_REGS may contain pseudos. | |
e855c69d AB |
1485 | If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS. |
1486 | ||
b8698a0f L |
1487 | TODO: take into account register pressure while doing this. Up to this |
1488 | moment, this function would never return NULL for pseudos, but we should | |
e855c69d AB |
1489 | not rely on this. */ |
1490 | static rtx | |
b8698a0f L |
1491 | choose_best_pseudo_reg (regset used_regs, |
1492 | struct reg_rename *reg_rename_p, | |
e855c69d AB |
1493 | def_list_t original_insns, bool *is_orig_reg_p_ptr) |
1494 | { | |
1495 | def_list_iterator i; | |
1496 | def_t def; | |
1497 | enum machine_mode mode = VOIDmode; | |
1498 | bool bad_hard_regs = false; | |
b8698a0f | 1499 | |
e855c69d AB |
1500 | /* We should not use this after reload. */ |
1501 | gcc_assert (!reload_completed); | |
1502 | ||
1503 | /* If original register is available, return it. */ | |
1504 | *is_orig_reg_p_ptr = true; | |
1505 | ||
1506 | FOR_EACH_DEF (def, i, original_insns) | |
1507 | { | |
1508 | rtx dest = SET_DEST (PATTERN (def->orig_insn)); | |
1509 | int orig_regno; | |
b8698a0f | 1510 | |
e855c69d | 1511 | gcc_assert (REG_P (dest)); |
b8698a0f | 1512 | |
e855c69d AB |
1513 | /* Check that all original operations have the same mode. */ |
1514 | if (mode == VOIDmode) | |
1515 | mode = GET_MODE (dest); | |
1516 | else | |
1517 | gcc_assert (mode == GET_MODE (dest)); | |
1518 | orig_regno = REGNO (dest); | |
b8698a0f | 1519 | |
e855c69d AB |
1520 | if (!REGNO_REG_SET_P (used_regs, orig_regno)) |
1521 | { | |
1522 | if (orig_regno < FIRST_PSEUDO_REGISTER) | |
1523 | { | |
1524 | gcc_assert (df_regs_ever_live_p (orig_regno)); | |
b8698a0f L |
1525 | |
1526 | /* For hard registers, we have to check hardware imposed | |
e855c69d | 1527 | limitations (frame/stack registers, calls crossed). */ |
b8698a0f | 1528 | if (!TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, |
e855c69d AB |
1529 | orig_regno)) |
1530 | { | |
b8698a0f L |
1531 | /* Don't let register cross a call if it doesn't already |
1532 | cross one. This condition is written in accordance with | |
e855c69d | 1533 | that in sched-deps.c sched_analyze_reg(). */ |
b8698a0f | 1534 | if (!reg_rename_p->crosses_call |
e855c69d | 1535 | || REG_N_CALLS_CROSSED (orig_regno) > 0) |
b8698a0f | 1536 | return gen_rtx_REG (mode, orig_regno); |
e855c69d | 1537 | } |
b8698a0f | 1538 | |
e855c69d AB |
1539 | bad_hard_regs = true; |
1540 | } | |
1541 | else | |
1542 | return dest; | |
1543 | } | |
1544 | } | |
1545 | ||
1546 | *is_orig_reg_p_ptr = false; | |
b8698a0f | 1547 | |
e855c69d AB |
1548 | /* We had some original hard registers that couldn't be used. |
1549 | Those were likely special. Don't try to create a pseudo. */ | |
1550 | if (bad_hard_regs) | |
1551 | return NULL_RTX; | |
b8698a0f L |
1552 | |
1553 | /* We haven't found a register from original operations. Get a new one. | |
e855c69d AB |
1554 | FIXME: control register pressure somehow. */ |
1555 | { | |
1556 | rtx new_reg = gen_reg_rtx (mode); | |
1557 | ||
1558 | gcc_assert (mode != VOIDmode); | |
1559 | ||
1560 | max_regno = max_reg_num (); | |
1561 | maybe_extend_reg_info_p (); | |
1562 | REG_N_CALLS_CROSSED (REGNO (new_reg)) = reg_rename_p->crosses_call ? 1 : 0; | |
1563 | ||
1564 | return new_reg; | |
1565 | } | |
1566 | } | |
1567 | ||
1568 | /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE, | |
1569 | USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */ | |
1570 | static void | |
b8698a0f | 1571 | verify_target_availability (expr_t expr, regset used_regs, |
e855c69d AB |
1572 | struct reg_rename *reg_rename_p) |
1573 | { | |
1574 | unsigned n, i, regno; | |
1575 | enum machine_mode mode; | |
1576 | bool target_available, live_available, hard_available; | |
1577 | ||
1578 | if (!REG_P (EXPR_LHS (expr)) || EXPR_TARGET_AVAILABLE (expr) < 0) | |
1579 | return; | |
b8698a0f | 1580 | |
e855c69d AB |
1581 | regno = expr_dest_regno (expr); |
1582 | mode = GET_MODE (EXPR_LHS (expr)); | |
1583 | target_available = EXPR_TARGET_AVAILABLE (expr) == 1; | |
1584 | n = reload_completed ? hard_regno_nregs[regno][mode] : 1; | |
1585 | ||
1586 | live_available = hard_available = true; | |
1587 | for (i = 0; i < n; i++) | |
1588 | { | |
1589 | if (bitmap_bit_p (used_regs, regno + i)) | |
1590 | live_available = false; | |
1591 | if (TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno + i)) | |
1592 | hard_available = false; | |
1593 | } | |
1594 | ||
b8698a0f | 1595 | /* When target is not available, it may be due to hard register |
e855c69d AB |
1596 | restrictions, e.g. crosses calls, so we check hard_available too. */ |
1597 | if (target_available) | |
1598 | gcc_assert (live_available); | |
1599 | else | |
b8698a0f | 1600 | /* Check only if we haven't scheduled something on the previous fence, |
e855c69d AB |
1601 | cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues |
1602 | and having more than one fence, we may end having targ_un in a block | |
b8698a0f | 1603 | in which successors target register is actually available. |
e855c69d AB |
1604 | |
1605 | The last condition handles the case when a dependence from a call insn | |
b8698a0f L |
1606 | was created in sched-deps.c for insns with destination registers that |
1607 | never crossed a call before, but do cross one after our code motion. | |
e855c69d | 1608 | |
b8698a0f L |
1609 | FIXME: in the latter case, we just uselessly called find_used_regs, |
1610 | because we can't move this expression with any other register | |
e855c69d | 1611 | as well. */ |
b8698a0f L |
1612 | gcc_assert (scheduled_something_on_previous_fence || !live_available |
1613 | || !hard_available | |
1614 | || (!reload_completed && reg_rename_p->crosses_call | |
e855c69d AB |
1615 | && REG_N_CALLS_CROSSED (regno) == 0)); |
1616 | } | |
1617 | ||
b8698a0f L |
1618 | /* Collect unavailable registers due to liveness for EXPR from BNDS |
1619 | into USED_REGS. Save additional information about available | |
e855c69d AB |
1620 | registers and unavailable due to hardware restriction registers |
1621 | into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS | |
1622 | list. */ | |
1623 | static void | |
1624 | collect_unavailable_regs_from_bnds (expr_t expr, blist_t bnds, regset used_regs, | |
1625 | struct reg_rename *reg_rename_p, | |
1626 | def_list_t *original_insns) | |
1627 | { | |
1628 | for (; bnds; bnds = BLIST_NEXT (bnds)) | |
1629 | { | |
1630 | bool res; | |
1631 | av_set_t orig_ops = NULL; | |
1632 | bnd_t bnd = BLIST_BND (bnds); | |
1633 | ||
1634 | /* If the chosen best expr doesn't belong to current boundary, | |
1635 | skip it. */ | |
1636 | if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr))) | |
1637 | continue; | |
1638 | ||
1639 | /* Put in ORIG_OPS all exprs from this boundary that became | |
1640 | RES on top. */ | |
1641 | orig_ops = find_sequential_best_exprs (bnd, expr, false); | |
1642 | ||
1643 | /* Compute used regs and OR it into the USED_REGS. */ | |
1644 | res = find_used_regs (BND_TO (bnd), orig_ops, used_regs, | |
1645 | reg_rename_p, original_insns); | |
1646 | ||
1647 | /* FIXME: the assert is true until we'd have several boundaries. */ | |
1648 | gcc_assert (res); | |
1649 | av_set_clear (&orig_ops); | |
1650 | } | |
1651 | } | |
1652 | ||
1653 | /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG. | |
1654 | If BEST_REG is valid, replace LHS of EXPR with it. */ | |
1655 | static bool | |
1656 | try_replace_dest_reg (ilist_t orig_insns, rtx best_reg, expr_t expr) | |
1657 | { | |
e855c69d AB |
1658 | /* Try whether we'll be able to generate the insn |
1659 | 'dest := best_reg' at the place of the original operation. */ | |
1660 | for (; orig_insns; orig_insns = ILIST_NEXT (orig_insns)) | |
1661 | { | |
1662 | insn_t orig_insn = DEF_LIST_DEF (orig_insns)->orig_insn; | |
1663 | ||
1664 | gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn))); | |
1665 | ||
0666ff4e AB |
1666 | if (REGNO (best_reg) != REGNO (INSN_LHS (orig_insn)) |
1667 | && (! replace_src_with_reg_ok_p (orig_insn, best_reg) | |
1668 | || ! replace_dest_with_reg_ok_p (orig_insn, best_reg))) | |
e855c69d AB |
1669 | return false; |
1670 | } | |
1671 | ||
1672 | /* Make sure that EXPR has the right destination | |
1673 | register. */ | |
0666ff4e AB |
1674 | if (expr_dest_regno (expr) != REGNO (best_reg)) |
1675 | replace_dest_with_reg_in_expr (expr, best_reg); | |
1676 | else | |
1677 | EXPR_TARGET_AVAILABLE (expr) = 1; | |
1678 | ||
e855c69d AB |
1679 | return true; |
1680 | } | |
1681 | ||
b8698a0f L |
1682 | /* Select and assign best register to EXPR searching from BNDS. |
1683 | Set *IS_ORIG_REG_P to TRUE if original register was selected. | |
e855c69d AB |
1684 | Return FALSE if no register can be chosen, which could happen when: |
1685 | * EXPR_SEPARABLE_P is true but we were unable to find suitable register; | |
1686 | * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers | |
1687 | that are used on the moving path. */ | |
1688 | static bool | |
1689 | find_best_reg_for_expr (expr_t expr, blist_t bnds, bool *is_orig_reg_p) | |
1690 | { | |
1691 | static struct reg_rename reg_rename_data; | |
1692 | ||
1693 | regset used_regs; | |
1694 | def_list_t original_insns = NULL; | |
1695 | bool reg_ok; | |
1696 | ||
1697 | *is_orig_reg_p = false; | |
1698 | ||
1699 | /* Don't bother to do anything if this insn doesn't set any registers. */ | |
1700 | if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr))) | |
1701 | && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr)))) | |
1702 | return true; | |
1703 | ||
1704 | used_regs = get_clear_regset_from_pool (); | |
1705 | CLEAR_HARD_REG_SET (reg_rename_data.unavailable_hard_regs); | |
1706 | ||
1707 | collect_unavailable_regs_from_bnds (expr, bnds, used_regs, ®_rename_data, | |
1708 | &original_insns); | |
1709 | ||
1710 | #ifdef ENABLE_CHECKING | |
1711 | /* If after reload, make sure we're working with hard regs here. */ | |
b8698a0f | 1712 | if (reload_completed) |
e855c69d AB |
1713 | { |
1714 | reg_set_iterator rsi; | |
1715 | unsigned i; | |
b8698a0f | 1716 | |
e855c69d AB |
1717 | EXECUTE_IF_SET_IN_REG_SET (used_regs, FIRST_PSEUDO_REGISTER, i, rsi) |
1718 | gcc_unreachable (); | |
1719 | } | |
1720 | #endif | |
1721 | ||
1722 | if (EXPR_SEPARABLE_P (expr)) | |
1723 | { | |
1724 | rtx best_reg = NULL_RTX; | |
1725 | /* Check that we have computed availability of a target register | |
1726 | correctly. */ | |
1727 | verify_target_availability (expr, used_regs, ®_rename_data); | |
1728 | ||
1729 | /* Turn everything in hard regs after reload. */ | |
1730 | if (reload_completed) | |
1731 | { | |
1732 | HARD_REG_SET hard_regs_used; | |
1733 | REG_SET_TO_HARD_REG_SET (hard_regs_used, used_regs); | |
1734 | ||
1735 | /* Join hard registers unavailable due to register class | |
1736 | restrictions and live range intersection. */ | |
1737 | IOR_HARD_REG_SET (hard_regs_used, | |
1738 | reg_rename_data.unavailable_hard_regs); | |
1739 | ||
1740 | best_reg = choose_best_reg (hard_regs_used, ®_rename_data, | |
1741 | original_insns, is_orig_reg_p); | |
1742 | } | |
1743 | else | |
1744 | best_reg = choose_best_pseudo_reg (used_regs, ®_rename_data, | |
1745 | original_insns, is_orig_reg_p); | |
1746 | ||
1747 | if (!best_reg) | |
1748 | reg_ok = false; | |
1749 | else if (*is_orig_reg_p) | |
1750 | { | |
1751 | /* In case of unification BEST_REG may be different from EXPR's LHS | |
1752 | when EXPR's LHS is unavailable, and there is another LHS among | |
1753 | ORIGINAL_INSNS. */ | |
1754 | reg_ok = try_replace_dest_reg (original_insns, best_reg, expr); | |
1755 | } | |
1756 | else | |
1757 | { | |
1758 | /* Forbid renaming of low-cost insns. */ | |
1759 | if (sel_vinsn_cost (EXPR_VINSN (expr)) < 2) | |
1760 | reg_ok = false; | |
1761 | else | |
1762 | reg_ok = try_replace_dest_reg (original_insns, best_reg, expr); | |
1763 | } | |
1764 | } | |
1765 | else | |
1766 | { | |
1767 | /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set | |
1768 | any of the HARD_REGS_USED set. */ | |
1769 | if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr), used_regs, | |
1770 | reg_rename_data.unavailable_hard_regs)) | |
1771 | { | |
1772 | reg_ok = false; | |
1773 | gcc_assert (EXPR_TARGET_AVAILABLE (expr) <= 0); | |
1774 | } | |
1775 | else | |
1776 | { | |
1777 | reg_ok = true; | |
1778 | gcc_assert (EXPR_TARGET_AVAILABLE (expr) != 0); | |
1779 | } | |
1780 | } | |
1781 | ||
1782 | ilist_clear (&original_insns); | |
1783 | return_regset_to_pool (used_regs); | |
1784 | ||
1785 | return reg_ok; | |
1786 | } | |
1787 | \f | |
1788 | ||
1789 | /* Return true if dependence described by DS can be overcomed. */ | |
1790 | static bool | |
1791 | can_speculate_dep_p (ds_t ds) | |
1792 | { | |
1793 | if (spec_info == NULL) | |
1794 | return false; | |
1795 | ||
1796 | /* Leave only speculative data. */ | |
1797 | ds &= SPECULATIVE; | |
1798 | ||
1799 | if (ds == 0) | |
1800 | return false; | |
1801 | ||
1802 | { | |
1803 | /* FIXME: make sched-deps.c produce only those non-hard dependencies, | |
1804 | that we can overcome. */ | |
1805 | ds_t spec_mask = spec_info->mask; | |
1806 | ||
1807 | if ((ds & spec_mask) != ds) | |
1808 | return false; | |
1809 | } | |
1810 | ||
1811 | if (ds_weak (ds) < spec_info->data_weakness_cutoff) | |
1812 | return false; | |
1813 | ||
1814 | return true; | |
1815 | } | |
1816 | ||
1817 | /* Get a speculation check instruction. | |
1818 | C_EXPR is a speculative expression, | |
1819 | CHECK_DS describes speculations that should be checked, | |
1820 | ORIG_INSN is the original non-speculative insn in the stream. */ | |
1821 | static insn_t | |
1822 | create_speculation_check (expr_t c_expr, ds_t check_ds, insn_t orig_insn) | |
1823 | { | |
1824 | rtx check_pattern; | |
1825 | rtx insn_rtx; | |
1826 | insn_t insn; | |
1827 | basic_block recovery_block; | |
1828 | rtx label; | |
1829 | ||
1830 | /* Create a recovery block if target is going to emit branchy check, or if | |
1831 | ORIG_INSN was speculative already. */ | |
388092d5 | 1832 | if (targetm.sched.needs_block_p (check_ds) |
e855c69d AB |
1833 | || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn)) != 0) |
1834 | { | |
1835 | recovery_block = sel_create_recovery_block (orig_insn); | |
1836 | label = BB_HEAD (recovery_block); | |
1837 | } | |
1838 | else | |
1839 | { | |
1840 | recovery_block = NULL; | |
1841 | label = NULL_RTX; | |
1842 | } | |
1843 | ||
1844 | /* Get pattern of the check. */ | |
1845 | check_pattern = targetm.sched.gen_spec_check (EXPR_INSN_RTX (c_expr), label, | |
1846 | check_ds); | |
1847 | ||
1848 | gcc_assert (check_pattern != NULL); | |
1849 | ||
1850 | /* Emit check. */ | |
1851 | insn_rtx = create_insn_rtx_from_pattern (check_pattern, label); | |
1852 | ||
1853 | insn = sel_gen_insn_from_rtx_after (insn_rtx, INSN_EXPR (orig_insn), | |
1854 | INSN_SEQNO (orig_insn), orig_insn); | |
1855 | ||
1856 | /* Make check to be non-speculative. */ | |
1857 | EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0; | |
1858 | INSN_SPEC_CHECKED_DS (insn) = check_ds; | |
1859 | ||
1860 | /* Decrease priority of check by difference of load/check instruction | |
1861 | latencies. */ | |
1862 | EXPR_PRIORITY (INSN_EXPR (insn)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn)) | |
1863 | - sel_vinsn_cost (INSN_VINSN (insn))); | |
1864 | ||
1865 | /* Emit copy of original insn (though with replaced target register, | |
1866 | if needed) to the recovery block. */ | |
1867 | if (recovery_block != NULL) | |
1868 | { | |
1869 | rtx twin_rtx; | |
e855c69d AB |
1870 | |
1871 | twin_rtx = copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr))); | |
1872 | twin_rtx = create_insn_rtx_from_pattern (twin_rtx, NULL_RTX); | |
1124098b JJ |
1873 | sel_gen_recovery_insn_from_rtx_after (twin_rtx, |
1874 | INSN_EXPR (orig_insn), | |
1875 | INSN_SEQNO (insn), | |
1876 | bb_note (recovery_block)); | |
e855c69d AB |
1877 | } |
1878 | ||
1879 | /* If we've generated a data speculation check, make sure | |
1880 | that all the bookkeeping instruction we'll create during | |
1881 | this move_op () will allocate an ALAT entry so that the | |
1882 | check won't fail. | |
1883 | In case of control speculation we must convert C_EXPR to control | |
1884 | speculative mode, because failing to do so will bring us an exception | |
1885 | thrown by the non-control-speculative load. */ | |
1886 | check_ds = ds_get_max_dep_weak (check_ds); | |
1887 | speculate_expr (c_expr, check_ds); | |
b8698a0f | 1888 | |
e855c69d AB |
1889 | return insn; |
1890 | } | |
1891 | ||
1892 | /* True when INSN is a "regN = regN" copy. */ | |
1893 | static bool | |
1894 | identical_copy_p (rtx insn) | |
1895 | { | |
1896 | rtx lhs, rhs, pat; | |
1897 | ||
1898 | pat = PATTERN (insn); | |
1899 | ||
1900 | if (GET_CODE (pat) != SET) | |
1901 | return false; | |
1902 | ||
1903 | lhs = SET_DEST (pat); | |
1904 | if (!REG_P (lhs)) | |
1905 | return false; | |
1906 | ||
1907 | rhs = SET_SRC (pat); | |
1908 | if (!REG_P (rhs)) | |
1909 | return false; | |
1910 | ||
1911 | return REGNO (lhs) == REGNO (rhs); | |
1912 | } | |
1913 | ||
b8698a0f | 1914 | /* Undo all transformations on *AV_PTR that were done when |
e855c69d AB |
1915 | moving through INSN. */ |
1916 | static void | |
1917 | undo_transformations (av_set_t *av_ptr, rtx insn) | |
1918 | { | |
1919 | av_set_iterator av_iter; | |
1920 | expr_t expr; | |
1921 | av_set_t new_set = NULL; | |
1922 | ||
b8698a0f | 1923 | /* First, kill any EXPR that uses registers set by an insn. This is |
e855c69d AB |
1924 | required for correctness. */ |
1925 | FOR_EACH_EXPR_1 (expr, av_iter, av_ptr) | |
1926 | if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (expr)) | |
b8698a0f | 1927 | && bitmap_intersect_p (INSN_REG_SETS (insn), |
e855c69d AB |
1928 | VINSN_REG_USES (EXPR_VINSN (expr))) |
1929 | /* When an insn looks like 'r1 = r1', we could substitute through | |
1930 | it, but the above condition will still hold. This happened with | |
b8698a0f | 1931 | gcc.c-torture/execute/961125-1.c. */ |
e855c69d AB |
1932 | && !identical_copy_p (insn)) |
1933 | { | |
1934 | if (sched_verbose >= 6) | |
b8698a0f | 1935 | sel_print ("Expr %d removed due to use/set conflict\n", |
e855c69d AB |
1936 | INSN_UID (EXPR_INSN_RTX (expr))); |
1937 | av_set_iter_remove (&av_iter); | |
1938 | } | |
1939 | ||
1940 | /* Undo transformations looking at the history vector. */ | |
1941 | FOR_EACH_EXPR (expr, av_iter, *av_ptr) | |
1942 | { | |
1943 | int index = find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr), | |
1944 | insn, EXPR_VINSN (expr), true); | |
1945 | ||
1946 | if (index >= 0) | |
1947 | { | |
1948 | expr_history_def *phist; | |
1949 | ||
b8698a0f | 1950 | phist = VEC_index (expr_history_def, |
e855c69d AB |
1951 | EXPR_HISTORY_OF_CHANGES (expr), |
1952 | index); | |
1953 | ||
b8698a0f | 1954 | switch (phist->type) |
e855c69d AB |
1955 | { |
1956 | case TRANS_SPECULATION: | |
1957 | { | |
1958 | ds_t old_ds, new_ds; | |
b8698a0f | 1959 | |
e855c69d | 1960 | /* Compute the difference between old and new speculative |
b8698a0f | 1961 | statuses: that's what we need to check. |
e855c69d AB |
1962 | Earlier we used to assert that the status will really |
1963 | change. This no longer works because only the probability | |
1964 | bits in the status may have changed during compute_av_set, | |
b8698a0f L |
1965 | and in the case of merging different probabilities of the |
1966 | same speculative status along different paths we do not | |
e855c69d AB |
1967 | record this in the history vector. */ |
1968 | old_ds = phist->spec_ds; | |
1969 | new_ds = EXPR_SPEC_DONE_DS (expr); | |
1970 | ||
1971 | old_ds &= SPECULATIVE; | |
1972 | new_ds &= SPECULATIVE; | |
1973 | new_ds &= ~old_ds; | |
b8698a0f | 1974 | |
e855c69d AB |
1975 | EXPR_SPEC_TO_CHECK_DS (expr) |= new_ds; |
1976 | break; | |
1977 | } | |
1978 | case TRANS_SUBSTITUTION: | |
1979 | { | |
1980 | expr_def _tmp_expr, *tmp_expr = &_tmp_expr; | |
1981 | vinsn_t new_vi; | |
1982 | bool add = true; | |
b8698a0f | 1983 | |
e855c69d | 1984 | new_vi = phist->old_expr_vinsn; |
b8698a0f L |
1985 | |
1986 | gcc_assert (VINSN_SEPARABLE_P (new_vi) | |
e855c69d AB |
1987 | == EXPR_SEPARABLE_P (expr)); |
1988 | copy_expr (tmp_expr, expr); | |
1989 | ||
b8698a0f | 1990 | if (vinsn_equal_p (phist->new_expr_vinsn, |
e855c69d AB |
1991 | EXPR_VINSN (tmp_expr))) |
1992 | change_vinsn_in_expr (tmp_expr, new_vi); | |
1993 | else | |
1994 | /* This happens when we're unsubstituting on a bookkeeping | |
1995 | copy, which was in turn substituted. The history is wrong | |
1996 | in this case. Do it the hard way. */ | |
1997 | add = substitute_reg_in_expr (tmp_expr, insn, true); | |
1998 | if (add) | |
1999 | av_set_add (&new_set, tmp_expr); | |
2000 | clear_expr (tmp_expr); | |
2001 | break; | |
2002 | } | |
2003 | default: | |
2004 | gcc_unreachable (); | |
2005 | } | |
2006 | } | |
b8698a0f | 2007 | |
e855c69d AB |
2008 | } |
2009 | ||
2010 | av_set_union_and_clear (av_ptr, &new_set, NULL); | |
2011 | } | |
2012 | \f | |
2013 | ||
2014 | /* Moveup_* helpers for code motion and computing av sets. */ | |
2015 | ||
2016 | /* Propagates EXPR inside an insn group through THROUGH_INSN. | |
b8698a0f | 2017 | The difference from the below function is that only substitution is |
e855c69d AB |
2018 | performed. */ |
2019 | static enum MOVEUP_EXPR_CODE | |
2020 | moveup_expr_inside_insn_group (expr_t expr, insn_t through_insn) | |
2021 | { | |
2022 | vinsn_t vi = EXPR_VINSN (expr); | |
2023 | ds_t *has_dep_p; | |
2024 | ds_t full_ds; | |
2025 | ||
2026 | /* Do this only inside insn group. */ | |
2027 | gcc_assert (INSN_SCHED_CYCLE (through_insn) > 0); | |
2028 | ||
2029 | full_ds = has_dependence_p (expr, through_insn, &has_dep_p); | |
2030 | if (full_ds == 0) | |
2031 | return MOVEUP_EXPR_SAME; | |
2032 | ||
2033 | /* Substitution is the possible choice in this case. */ | |
2034 | if (has_dep_p[DEPS_IN_RHS]) | |
2035 | { | |
2036 | /* Can't substitute UNIQUE VINSNs. */ | |
2037 | gcc_assert (!VINSN_UNIQUE_P (vi)); | |
b8698a0f L |
2038 | |
2039 | if (can_substitute_through_p (through_insn, | |
e855c69d AB |
2040 | has_dep_p[DEPS_IN_RHS]) |
2041 | && substitute_reg_in_expr (expr, through_insn, false)) | |
2042 | { | |
2043 | EXPR_WAS_SUBSTITUTED (expr) = true; | |
2044 | return MOVEUP_EXPR_CHANGED; | |
2045 | } | |
2046 | ||
2047 | /* Don't care about this, as even true dependencies may be allowed | |
2048 | in an insn group. */ | |
2049 | return MOVEUP_EXPR_SAME; | |
2050 | } | |
2051 | ||
2052 | /* This can catch output dependencies in COND_EXECs. */ | |
2053 | if (has_dep_p[DEPS_IN_INSN]) | |
2054 | return MOVEUP_EXPR_NULL; | |
b8698a0f | 2055 | |
e855c69d AB |
2056 | /* This is either an output or an anti dependence, which usually have |
2057 | a zero latency. Allow this here, if we'd be wrong, tick_check_p | |
2058 | will fix this. */ | |
2059 | gcc_assert (has_dep_p[DEPS_IN_LHS]); | |
2060 | return MOVEUP_EXPR_AS_RHS; | |
2061 | } | |
2062 | ||
2063 | /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */ | |
2064 | #define CANT_MOVE_TRAPPING(expr, through_insn) \ | |
2065 | (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \ | |
2066 | && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \ | |
2067 | && !sel_insn_is_speculation_check (through_insn)) | |
2068 | ||
2069 | /* True when a conflict on a target register was found during moveup_expr. */ | |
2070 | static bool was_target_conflict = false; | |
2071 | ||
b5b8b0ac AO |
2072 | /* Return true when moving a debug INSN across THROUGH_INSN will |
2073 | create a bookkeeping block. We don't want to create such blocks, | |
2074 | for they would cause codegen differences between compilations with | |
2075 | and without debug info. */ | |
2076 | ||
2077 | static bool | |
2078 | moving_insn_creates_bookkeeping_block_p (insn_t insn, | |
2079 | insn_t through_insn) | |
2080 | { | |
2081 | basic_block bbi, bbt; | |
2082 | edge e1, e2; | |
2083 | edge_iterator ei1, ei2; | |
2084 | ||
2085 | if (!bookkeeping_can_be_created_if_moved_through_p (through_insn)) | |
2086 | { | |
2087 | if (sched_verbose >= 9) | |
2088 | sel_print ("no bookkeeping required: "); | |
2089 | return FALSE; | |
2090 | } | |
2091 | ||
2092 | bbi = BLOCK_FOR_INSN (insn); | |
2093 | ||
2094 | if (EDGE_COUNT (bbi->preds) == 1) | |
2095 | { | |
2096 | if (sched_verbose >= 9) | |
2097 | sel_print ("only one pred edge: "); | |
2098 | return TRUE; | |
2099 | } | |
2100 | ||
2101 | bbt = BLOCK_FOR_INSN (through_insn); | |
2102 | ||
2103 | FOR_EACH_EDGE (e1, ei1, bbt->succs) | |
2104 | { | |
2105 | FOR_EACH_EDGE (e2, ei2, bbi->preds) | |
2106 | { | |
2107 | if (find_block_for_bookkeeping (e1, e2, TRUE)) | |
2108 | { | |
2109 | if (sched_verbose >= 9) | |
2110 | sel_print ("found existing block: "); | |
2111 | return FALSE; | |
2112 | } | |
2113 | } | |
2114 | } | |
2115 | ||
2116 | if (sched_verbose >= 9) | |
2117 | sel_print ("would create bookkeeping block: "); | |
2118 | ||
2119 | return TRUE; | |
2120 | } | |
2121 | ||
e855c69d | 2122 | /* Modifies EXPR so it can be moved through the THROUGH_INSN, |
b8698a0f L |
2123 | performing necessary transformations. Record the type of transformation |
2124 | made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP, | |
e855c69d | 2125 | permit all dependencies except true ones, and try to remove those |
b8698a0f L |
2126 | too via forward substitution. All cases when a non-eliminable |
2127 | non-zero cost dependency exists inside an insn group will be fixed | |
e855c69d AB |
2128 | in tick_check_p instead. */ |
2129 | static enum MOVEUP_EXPR_CODE | |
2130 | moveup_expr (expr_t expr, insn_t through_insn, bool inside_insn_group, | |
2131 | enum local_trans_type *ptrans_type) | |
2132 | { | |
2133 | vinsn_t vi = EXPR_VINSN (expr); | |
2134 | insn_t insn = VINSN_INSN_RTX (vi); | |
2135 | bool was_changed = false; | |
2136 | bool as_rhs = false; | |
2137 | ds_t *has_dep_p; | |
2138 | ds_t full_ds; | |
2139 | ||
48bb58b1 AO |
2140 | /* ??? We use dependencies of non-debug insns on debug insns to |
2141 | indicate that the debug insns need to be reset if the non-debug | |
2142 | insn is pulled ahead of it. It's hard to figure out how to | |
2143 | introduce such a notion in sel-sched, but it already fails to | |
2144 | support debug insns in other ways, so we just go ahead and | |
2145 | let the deug insns go corrupt for now. */ | |
2146 | if (DEBUG_INSN_P (through_insn) && !DEBUG_INSN_P (insn)) | |
2147 | return MOVEUP_EXPR_SAME; | |
2148 | ||
e855c69d AB |
2149 | /* When inside_insn_group, delegate to the helper. */ |
2150 | if (inside_insn_group) | |
2151 | return moveup_expr_inside_insn_group (expr, through_insn); | |
2152 | ||
2153 | /* Deal with unique insns and control dependencies. */ | |
2154 | if (VINSN_UNIQUE_P (vi)) | |
2155 | { | |
2156 | /* We can move jumps without side-effects or jumps that are | |
2157 | mutually exclusive with instruction THROUGH_INSN (all in cases | |
2158 | dependencies allow to do so and jump is not speculative). */ | |
2159 | if (control_flow_insn_p (insn)) | |
2160 | { | |
2161 | basic_block fallthru_bb; | |
2162 | ||
b8698a0f | 2163 | /* Do not move checks and do not move jumps through other |
e855c69d AB |
2164 | jumps. */ |
2165 | if (control_flow_insn_p (through_insn) | |
2166 | || sel_insn_is_speculation_check (insn)) | |
2167 | return MOVEUP_EXPR_NULL; | |
2168 | ||
2169 | /* Don't move jumps through CFG joins. */ | |
2170 | if (bookkeeping_can_be_created_if_moved_through_p (through_insn)) | |
2171 | return MOVEUP_EXPR_NULL; | |
2172 | ||
b8698a0f | 2173 | /* The jump should have a clear fallthru block, and |
e855c69d AB |
2174 | this block should be in the current region. */ |
2175 | if ((fallthru_bb = fallthru_bb_of_jump (insn)) == NULL | |
2176 | || ! in_current_region_p (fallthru_bb)) | |
2177 | return MOVEUP_EXPR_NULL; | |
b8698a0f | 2178 | |
eb277bf1 AM |
2179 | /* And it should be mutually exclusive with through_insn. */ |
2180 | if (! sched_insns_conditions_mutex_p (insn, through_insn) | |
b5b8b0ac | 2181 | && ! DEBUG_INSN_P (through_insn)) |
e855c69d AB |
2182 | return MOVEUP_EXPR_NULL; |
2183 | } | |
2184 | ||
2185 | /* Don't move what we can't move. */ | |
2186 | if (EXPR_CANT_MOVE (expr) | |
2187 | && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn)) | |
2188 | return MOVEUP_EXPR_NULL; | |
2189 | ||
2190 | /* Don't move SCHED_GROUP instruction through anything. | |
2191 | If we don't force this, then it will be possible to start | |
2192 | scheduling a sched_group before all its dependencies are | |
2193 | resolved. | |
2194 | ??? Haifa deals with this issue by delaying the SCHED_GROUP | |
2195 | as late as possible through rank_for_schedule. */ | |
2196 | if (SCHED_GROUP_P (insn)) | |
2197 | return MOVEUP_EXPR_NULL; | |
2198 | } | |
2199 | else | |
2200 | gcc_assert (!control_flow_insn_p (insn)); | |
2201 | ||
b5b8b0ac AO |
2202 | /* Don't move debug insns if this would require bookkeeping. */ |
2203 | if (DEBUG_INSN_P (insn) | |
2204 | && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn) | |
2205 | && moving_insn_creates_bookkeeping_block_p (insn, through_insn)) | |
2206 | return MOVEUP_EXPR_NULL; | |
2207 | ||
e855c69d AB |
2208 | /* Deal with data dependencies. */ |
2209 | was_target_conflict = false; | |
2210 | full_ds = has_dependence_p (expr, through_insn, &has_dep_p); | |
2211 | if (full_ds == 0) | |
2212 | { | |
2213 | if (!CANT_MOVE_TRAPPING (expr, through_insn)) | |
2214 | return MOVEUP_EXPR_SAME; | |
2215 | } | |
2216 | else | |
2217 | { | |
b8698a0f | 2218 | /* We can move UNIQUE insn up only as a whole and unchanged, |
e855c69d AB |
2219 | so it shouldn't have any dependencies. */ |
2220 | if (VINSN_UNIQUE_P (vi)) | |
2221 | return MOVEUP_EXPR_NULL; | |
2222 | } | |
2223 | ||
2224 | if (full_ds != 0 && can_speculate_dep_p (full_ds)) | |
2225 | { | |
2226 | int res; | |
2227 | ||
2228 | res = speculate_expr (expr, full_ds); | |
2229 | if (res >= 0) | |
2230 | { | |
2231 | /* Speculation was successful. */ | |
2232 | full_ds = 0; | |
2233 | was_changed = (res > 0); | |
2234 | if (res == 2) | |
2235 | was_target_conflict = true; | |
2236 | if (ptrans_type) | |
2237 | *ptrans_type = TRANS_SPECULATION; | |
2238 | sel_clear_has_dependence (); | |
2239 | } | |
2240 | } | |
2241 | ||
2242 | if (has_dep_p[DEPS_IN_INSN]) | |
2243 | /* We have some dependency that cannot be discarded. */ | |
2244 | return MOVEUP_EXPR_NULL; | |
2245 | ||
2246 | if (has_dep_p[DEPS_IN_LHS]) | |
b8698a0f | 2247 | { |
e855c69d | 2248 | /* Only separable insns can be moved up with the new register. |
b8698a0f | 2249 | Anyways, we should mark that the original register is |
e855c69d AB |
2250 | unavailable. */ |
2251 | if (!enable_schedule_as_rhs_p || !EXPR_SEPARABLE_P (expr)) | |
2252 | return MOVEUP_EXPR_NULL; | |
2253 | ||
2254 | EXPR_TARGET_AVAILABLE (expr) = false; | |
2255 | was_target_conflict = true; | |
2256 | as_rhs = true; | |
2257 | } | |
2258 | ||
2259 | /* At this point we have either separable insns, that will be lifted | |
2260 | up only as RHSes, or non-separable insns with no dependency in lhs. | |
2261 | If dependency is in RHS, then try to perform substitution and move up | |
2262 | substituted RHS: | |
2263 | ||
2264 | Ex. 1: Ex.2 | |
2265 | y = x; y = x; | |
2266 | z = y*2; y = y*2; | |
2267 | ||
b8698a0f | 2268 | In Ex.1 y*2 can be substituted for x*2 and the whole operation can be |
e855c69d AB |
2269 | moved above y=x assignment as z=x*2. |
2270 | ||
b8698a0f | 2271 | In Ex.2 y*2 also can be substituted for x*2, but only the right hand |
e855c69d AB |
2272 | side can be moved because of the output dependency. The operation was |
2273 | cropped to its rhs above. */ | |
2274 | if (has_dep_p[DEPS_IN_RHS]) | |
2275 | { | |
2276 | ds_t *rhs_dsp = &has_dep_p[DEPS_IN_RHS]; | |
2277 | ||
2278 | /* Can't substitute UNIQUE VINSNs. */ | |
2279 | gcc_assert (!VINSN_UNIQUE_P (vi)); | |
2280 | ||
2281 | if (can_speculate_dep_p (*rhs_dsp)) | |
2282 | { | |
2283 | int res; | |
b8698a0f | 2284 | |
e855c69d AB |
2285 | res = speculate_expr (expr, *rhs_dsp); |
2286 | if (res >= 0) | |
2287 | { | |
2288 | /* Speculation was successful. */ | |
2289 | *rhs_dsp = 0; | |
2290 | was_changed = (res > 0); | |
2291 | if (res == 2) | |
2292 | was_target_conflict = true; | |
2293 | if (ptrans_type) | |
2294 | *ptrans_type = TRANS_SPECULATION; | |
2295 | } | |
2296 | else | |
2297 | return MOVEUP_EXPR_NULL; | |
2298 | } | |
2299 | else if (can_substitute_through_p (through_insn, | |
2300 | *rhs_dsp) | |
2301 | && substitute_reg_in_expr (expr, through_insn, false)) | |
2302 | { | |
2303 | /* ??? We cannot perform substitution AND speculation on the same | |
2304 | insn. */ | |
2305 | gcc_assert (!was_changed); | |
2306 | was_changed = true; | |
2307 | if (ptrans_type) | |
2308 | *ptrans_type = TRANS_SUBSTITUTION; | |
2309 | EXPR_WAS_SUBSTITUTED (expr) = true; | |
2310 | } | |
2311 | else | |
2312 | return MOVEUP_EXPR_NULL; | |
2313 | } | |
2314 | ||
2315 | /* Don't move trapping insns through jumps. | |
2316 | This check should be at the end to give a chance to control speculation | |
2317 | to perform its duties. */ | |
2318 | if (CANT_MOVE_TRAPPING (expr, through_insn)) | |
2319 | return MOVEUP_EXPR_NULL; | |
2320 | ||
b8698a0f L |
2321 | return (was_changed |
2322 | ? MOVEUP_EXPR_CHANGED | |
2323 | : (as_rhs | |
e855c69d AB |
2324 | ? MOVEUP_EXPR_AS_RHS |
2325 | : MOVEUP_EXPR_SAME)); | |
2326 | } | |
2327 | ||
b8698a0f | 2328 | /* Try to look at bitmap caches for EXPR and INSN pair, return true |
e855c69d AB |
2329 | if successful. When INSIDE_INSN_GROUP, also try ignore dependencies |
2330 | that can exist within a parallel group. Write to RES the resulting | |
2331 | code for moveup_expr. */ | |
b8698a0f | 2332 | static bool |
e855c69d AB |
2333 | try_bitmap_cache (expr_t expr, insn_t insn, |
2334 | bool inside_insn_group, | |
2335 | enum MOVEUP_EXPR_CODE *res) | |
2336 | { | |
2337 | int expr_uid = INSN_UID (EXPR_INSN_RTX (expr)); | |
b8698a0f | 2338 | |
e855c69d AB |
2339 | /* First check whether we've analyzed this situation already. */ |
2340 | if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn), expr_uid)) | |
2341 | { | |
2342 | if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid)) | |
2343 | { | |
2344 | if (sched_verbose >= 6) | |
2345 | sel_print ("removed (cached)\n"); | |
2346 | *res = MOVEUP_EXPR_NULL; | |
2347 | return true; | |
2348 | } | |
2349 | else | |
2350 | { | |
2351 | if (sched_verbose >= 6) | |
2352 | sel_print ("unchanged (cached)\n"); | |
2353 | *res = MOVEUP_EXPR_SAME; | |
2354 | return true; | |
2355 | } | |
2356 | } | |
2357 | else if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid)) | |
2358 | { | |
2359 | if (inside_insn_group) | |
2360 | { | |
2361 | if (sched_verbose >= 6) | |
2362 | sel_print ("unchanged (as RHS, cached, inside insn group)\n"); | |
2363 | *res = MOVEUP_EXPR_SAME; | |
2364 | return true; | |
b8698a0f | 2365 | |
e855c69d AB |
2366 | } |
2367 | else | |
2368 | EXPR_TARGET_AVAILABLE (expr) = false; | |
2369 | ||
b8698a0f L |
2370 | /* This is the only case when propagation result can change over time, |
2371 | as we can dynamically switch off scheduling as RHS. In this case, | |
e855c69d AB |
2372 | just check the flag to reach the correct decision. */ |
2373 | if (enable_schedule_as_rhs_p) | |
2374 | { | |
2375 | if (sched_verbose >= 6) | |
2376 | sel_print ("unchanged (as RHS, cached)\n"); | |
2377 | *res = MOVEUP_EXPR_AS_RHS; | |
2378 | return true; | |
2379 | } | |
2380 | else | |
2381 | { | |
2382 | if (sched_verbose >= 6) | |
2383 | sel_print ("removed (cached as RHS, but renaming" | |
2384 | " is now disabled)\n"); | |
2385 | *res = MOVEUP_EXPR_NULL; | |
2386 | return true; | |
2387 | } | |
2388 | } | |
2389 | ||
2390 | return false; | |
2391 | } | |
2392 | ||
b8698a0f | 2393 | /* Try to look at bitmap caches for EXPR and INSN pair, return true |
e855c69d | 2394 | if successful. Write to RES the resulting code for moveup_expr. */ |
b8698a0f | 2395 | static bool |
e855c69d AB |
2396 | try_transformation_cache (expr_t expr, insn_t insn, |
2397 | enum MOVEUP_EXPR_CODE *res) | |
2398 | { | |
b8698a0f | 2399 | struct transformed_insns *pti |
e855c69d AB |
2400 | = (struct transformed_insns *) |
2401 | htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn), | |
b8698a0f | 2402 | &EXPR_VINSN (expr), |
e855c69d AB |
2403 | VINSN_HASH_RTX (EXPR_VINSN (expr))); |
2404 | if (pti) | |
2405 | { | |
b8698a0f L |
2406 | /* This EXPR was already moved through this insn and was |
2407 | changed as a result. Fetch the proper data from | |
e855c69d | 2408 | the hashtable. */ |
b8698a0f L |
2409 | insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr), |
2410 | INSN_UID (insn), pti->type, | |
2411 | pti->vinsn_old, pti->vinsn_new, | |
e855c69d | 2412 | EXPR_SPEC_DONE_DS (expr)); |
b8698a0f | 2413 | |
e855c69d AB |
2414 | if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti->vinsn_new))) |
2415 | pti->vinsn_new = vinsn_copy (pti->vinsn_new, true); | |
2416 | change_vinsn_in_expr (expr, pti->vinsn_new); | |
2417 | if (pti->was_target_conflict) | |
2418 | EXPR_TARGET_AVAILABLE (expr) = false; | |
2419 | if (pti->type == TRANS_SPECULATION) | |
2420 | { | |
e855c69d AB |
2421 | EXPR_SPEC_DONE_DS (expr) = pti->ds; |
2422 | EXPR_NEEDS_SPEC_CHECK_P (expr) |= pti->needs_check; | |
2423 | } | |
2424 | ||
2425 | if (sched_verbose >= 6) | |
2426 | { | |
2427 | sel_print ("changed (cached): "); | |
2428 | dump_expr (expr); | |
2429 | sel_print ("\n"); | |
2430 | } | |
2431 | ||
2432 | *res = MOVEUP_EXPR_CHANGED; | |
2433 | return true; | |
2434 | } | |
2435 | ||
2436 | return false; | |
2437 | } | |
2438 | ||
2439 | /* Update bitmap caches on INSN with result RES of propagating EXPR. */ | |
2440 | static void | |
b8698a0f | 2441 | update_bitmap_cache (expr_t expr, insn_t insn, bool inside_insn_group, |
e855c69d AB |
2442 | enum MOVEUP_EXPR_CODE res) |
2443 | { | |
2444 | int expr_uid = INSN_UID (EXPR_INSN_RTX (expr)); | |
2445 | ||
b8698a0f | 2446 | /* Do not cache result of propagating jumps through an insn group, |
e855c69d AB |
2447 | as it is always true, which is not useful outside the group. */ |
2448 | if (inside_insn_group) | |
2449 | return; | |
b8698a0f | 2450 | |
e855c69d AB |
2451 | if (res == MOVEUP_EXPR_NULL) |
2452 | { | |
2453 | bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid); | |
2454 | bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid); | |
2455 | } | |
2456 | else if (res == MOVEUP_EXPR_SAME) | |
2457 | { | |
2458 | bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid); | |
2459 | bitmap_clear_bit (INSN_FOUND_DEPS (insn), expr_uid); | |
2460 | } | |
2461 | else if (res == MOVEUP_EXPR_AS_RHS) | |
2462 | { | |
2463 | bitmap_clear_bit (INSN_ANALYZED_DEPS (insn), expr_uid); | |
2464 | bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid); | |
2465 | } | |
2466 | else | |
2467 | gcc_unreachable (); | |
2468 | } | |
2469 | ||
2470 | /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN | |
2471 | and transformation type TRANS_TYPE. */ | |
2472 | static void | |
b8698a0f | 2473 | update_transformation_cache (expr_t expr, insn_t insn, |
e855c69d | 2474 | bool inside_insn_group, |
b8698a0f | 2475 | enum local_trans_type trans_type, |
e855c69d AB |
2476 | vinsn_t expr_old_vinsn) |
2477 | { | |
2478 | struct transformed_insns *pti; | |
2479 | ||
2480 | if (inside_insn_group) | |
2481 | return; | |
b8698a0f | 2482 | |
e855c69d AB |
2483 | pti = XNEW (struct transformed_insns); |
2484 | pti->vinsn_old = expr_old_vinsn; | |
2485 | pti->vinsn_new = EXPR_VINSN (expr); | |
2486 | pti->type = trans_type; | |
2487 | pti->was_target_conflict = was_target_conflict; | |
2488 | pti->ds = EXPR_SPEC_DONE_DS (expr); | |
2489 | pti->needs_check = EXPR_NEEDS_SPEC_CHECK_P (expr); | |
2490 | vinsn_attach (pti->vinsn_old); | |
2491 | vinsn_attach (pti->vinsn_new); | |
b8698a0f | 2492 | *((struct transformed_insns **) |
e855c69d AB |
2493 | htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn), |
2494 | pti, VINSN_HASH_RTX (expr_old_vinsn), | |
2495 | INSERT)) = pti; | |
2496 | } | |
2497 | ||
b8698a0f | 2498 | /* Same as moveup_expr, but first looks up the result of |
e855c69d AB |
2499 | transformation in caches. */ |
2500 | static enum MOVEUP_EXPR_CODE | |
2501 | moveup_expr_cached (expr_t expr, insn_t insn, bool inside_insn_group) | |
2502 | { | |
2503 | enum MOVEUP_EXPR_CODE res; | |
2504 | bool got_answer = false; | |
2505 | ||
2506 | if (sched_verbose >= 6) | |
2507 | { | |
b8698a0f | 2508 | sel_print ("Moving "); |
e855c69d AB |
2509 | dump_expr (expr); |
2510 | sel_print (" through %d: ", INSN_UID (insn)); | |
2511 | } | |
2512 | ||
b5b8b0ac AO |
2513 | if (DEBUG_INSN_P (EXPR_INSN_RTX (expr)) |
2514 | && (sel_bb_head (BLOCK_FOR_INSN (EXPR_INSN_RTX (expr))) | |
2515 | == EXPR_INSN_RTX (expr))) | |
2516 | /* Don't use cached information for debug insns that are heads of | |
2517 | basic blocks. */; | |
2518 | else if (try_bitmap_cache (expr, insn, inside_insn_group, &res)) | |
e855c69d AB |
2519 | /* When inside insn group, we do not want remove stores conflicting |
2520 | with previosly issued loads. */ | |
2521 | got_answer = ! inside_insn_group || res != MOVEUP_EXPR_NULL; | |
2522 | else if (try_transformation_cache (expr, insn, &res)) | |
2523 | got_answer = true; | |
2524 | ||
2525 | if (! got_answer) | |
2526 | { | |
2527 | /* Invoke moveup_expr and record the results. */ | |
2528 | vinsn_t expr_old_vinsn = EXPR_VINSN (expr); | |
2529 | ds_t expr_old_spec_ds = EXPR_SPEC_DONE_DS (expr); | |
2530 | int expr_uid = INSN_UID (VINSN_INSN_RTX (expr_old_vinsn)); | |
2531 | bool unique_p = VINSN_UNIQUE_P (expr_old_vinsn); | |
2532 | enum local_trans_type trans_type = TRANS_SUBSTITUTION; | |
2533 | ||
b8698a0f | 2534 | /* ??? Invent something better than this. We can't allow old_vinsn |
e855c69d AB |
2535 | to go, we need it for the history vector. */ |
2536 | vinsn_attach (expr_old_vinsn); | |
2537 | ||
2538 | res = moveup_expr (expr, insn, inside_insn_group, | |
2539 | &trans_type); | |
2540 | switch (res) | |
2541 | { | |
2542 | case MOVEUP_EXPR_NULL: | |
2543 | update_bitmap_cache (expr, insn, inside_insn_group, res); | |
2544 | if (sched_verbose >= 6) | |
2545 | sel_print ("removed\n"); | |
2546 | break; | |
2547 | ||
2548 | case MOVEUP_EXPR_SAME: | |
2549 | update_bitmap_cache (expr, insn, inside_insn_group, res); | |
2550 | if (sched_verbose >= 6) | |
2551 | sel_print ("unchanged\n"); | |
2552 | break; | |
2553 | ||
2554 | case MOVEUP_EXPR_AS_RHS: | |
2555 | gcc_assert (!unique_p || inside_insn_group); | |
2556 | update_bitmap_cache (expr, insn, inside_insn_group, res); | |
2557 | if (sched_verbose >= 6) | |
2558 | sel_print ("unchanged (as RHS)\n"); | |
2559 | break; | |
2560 | ||
2561 | case MOVEUP_EXPR_CHANGED: | |
2562 | gcc_assert (INSN_UID (EXPR_INSN_RTX (expr)) != expr_uid | |
2563 | || EXPR_SPEC_DONE_DS (expr) != expr_old_spec_ds); | |
b8698a0f L |
2564 | insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr), |
2565 | INSN_UID (insn), trans_type, | |
2566 | expr_old_vinsn, EXPR_VINSN (expr), | |
e855c69d AB |
2567 | expr_old_spec_ds); |
2568 | update_transformation_cache (expr, insn, inside_insn_group, | |
2569 | trans_type, expr_old_vinsn); | |
2570 | if (sched_verbose >= 6) | |
2571 | { | |
2572 | sel_print ("changed: "); | |
2573 | dump_expr (expr); | |
2574 | sel_print ("\n"); | |
2575 | } | |
2576 | break; | |
2577 | default: | |
2578 | gcc_unreachable (); | |
2579 | } | |
2580 | ||
2581 | vinsn_detach (expr_old_vinsn); | |
2582 | } | |
2583 | ||
2584 | return res; | |
2585 | } | |
2586 | ||
b8698a0f | 2587 | /* Moves an av set AVP up through INSN, performing necessary |
e855c69d AB |
2588 | transformations. */ |
2589 | static void | |
2590 | moveup_set_expr (av_set_t *avp, insn_t insn, bool inside_insn_group) | |
2591 | { | |
2592 | av_set_iterator i; | |
2593 | expr_t expr; | |
2594 | ||
b8698a0f L |
2595 | FOR_EACH_EXPR_1 (expr, i, avp) |
2596 | { | |
2597 | ||
e855c69d AB |
2598 | switch (moveup_expr_cached (expr, insn, inside_insn_group)) |
2599 | { | |
2600 | case MOVEUP_EXPR_SAME: | |
2601 | case MOVEUP_EXPR_AS_RHS: | |
2602 | break; | |
2603 | ||
2604 | case MOVEUP_EXPR_NULL: | |
2605 | av_set_iter_remove (&i); | |
2606 | break; | |
2607 | ||
2608 | case MOVEUP_EXPR_CHANGED: | |
2609 | expr = merge_with_other_exprs (avp, &i, expr); | |
2610 | break; | |
b8698a0f | 2611 | |
e855c69d AB |
2612 | default: |
2613 | gcc_unreachable (); | |
2614 | } | |
2615 | } | |
2616 | } | |
2617 | ||
2618 | /* Moves AVP set along PATH. */ | |
2619 | static void | |
2620 | moveup_set_inside_insn_group (av_set_t *avp, ilist_t path) | |
2621 | { | |
2622 | int last_cycle; | |
b8698a0f | 2623 | |
e855c69d AB |
2624 | if (sched_verbose >= 6) |
2625 | sel_print ("Moving expressions up in the insn group...\n"); | |
2626 | if (! path) | |
2627 | return; | |
2628 | last_cycle = INSN_SCHED_CYCLE (ILIST_INSN (path)); | |
b8698a0f | 2629 | while (path |
e855c69d AB |
2630 | && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle) |
2631 | { | |
2632 | moveup_set_expr (avp, ILIST_INSN (path), true); | |
2633 | path = ILIST_NEXT (path); | |
2634 | } | |
2635 | } | |
2636 | ||
2637 | /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */ | |
2638 | static bool | |
2639 | equal_after_moveup_path_p (expr_t expr, ilist_t path, expr_t expr_vliw) | |
2640 | { | |
2641 | expr_def _tmp, *tmp = &_tmp; | |
2642 | int last_cycle; | |
2643 | bool res = true; | |
2644 | ||
2645 | copy_expr_onside (tmp, expr); | |
2646 | last_cycle = path ? INSN_SCHED_CYCLE (ILIST_INSN (path)) : 0; | |
b8698a0f | 2647 | while (path |
e855c69d AB |
2648 | && res |
2649 | && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle) | |
2650 | { | |
b8698a0f | 2651 | res = (moveup_expr_cached (tmp, ILIST_INSN (path), true) |
e855c69d AB |
2652 | != MOVEUP_EXPR_NULL); |
2653 | path = ILIST_NEXT (path); | |
2654 | } | |
2655 | ||
2656 | if (res) | |
2657 | { | |
2658 | vinsn_t tmp_vinsn = EXPR_VINSN (tmp); | |
2659 | vinsn_t expr_vliw_vinsn = EXPR_VINSN (expr_vliw); | |
2660 | ||
2661 | if (tmp_vinsn != expr_vliw_vinsn) | |
2662 | res = vinsn_equal_p (tmp_vinsn, expr_vliw_vinsn); | |
2663 | } | |
2664 | ||
2665 | clear_expr (tmp); | |
2666 | return res; | |
2667 | } | |
2668 | \f | |
2669 | ||
2670 | /* Functions that compute av and lv sets. */ | |
2671 | ||
b8698a0f | 2672 | /* Returns true if INSN is not a downward continuation of the given path P in |
e855c69d AB |
2673 | the current stage. */ |
2674 | static bool | |
2675 | is_ineligible_successor (insn_t insn, ilist_t p) | |
2676 | { | |
2677 | insn_t prev_insn; | |
2678 | ||
2679 | /* Check if insn is not deleted. */ | |
2680 | if (PREV_INSN (insn) && NEXT_INSN (PREV_INSN (insn)) != insn) | |
2681 | gcc_unreachable (); | |
2682 | else if (NEXT_INSN (insn) && PREV_INSN (NEXT_INSN (insn)) != insn) | |
2683 | gcc_unreachable (); | |
2684 | ||
2685 | /* If it's the first insn visited, then the successor is ok. */ | |
2686 | if (!p) | |
2687 | return false; | |
2688 | ||
2689 | prev_insn = ILIST_INSN (p); | |
2690 | ||
2691 | if (/* a backward edge. */ | |
2692 | INSN_SEQNO (insn) < INSN_SEQNO (prev_insn) | |
2693 | /* is already visited. */ | |
2694 | || (INSN_SEQNO (insn) == INSN_SEQNO (prev_insn) | |
2695 | && (ilist_is_in_p (p, insn) | |
b8698a0f L |
2696 | /* We can reach another fence here and still seqno of insn |
2697 | would be equal to seqno of prev_insn. This is possible | |
e855c69d AB |
2698 | when prev_insn is a previously created bookkeeping copy. |
2699 | In that case it'd get a seqno of insn. Thus, check here | |
2700 | whether insn is in current fence too. */ | |
2701 | || IN_CURRENT_FENCE_P (insn))) | |
2702 | /* Was already scheduled on this round. */ | |
2703 | || (INSN_SEQNO (insn) > INSN_SEQNO (prev_insn) | |
2704 | && IN_CURRENT_FENCE_P (insn)) | |
b8698a0f L |
2705 | /* An insn from another fence could also be |
2706 | scheduled earlier even if this insn is not in | |
e855c69d AB |
2707 | a fence list right now. Check INSN_SCHED_CYCLE instead. */ |
2708 | || (!pipelining_p | |
2709 | && INSN_SCHED_TIMES (insn) > 0)) | |
2710 | return true; | |
2711 | else | |
2712 | return false; | |
2713 | } | |
2714 | ||
b8698a0f L |
2715 | /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work' |
2716 | of handling multiple successors and properly merging its av_sets. P is | |
2717 | the current path traversed. WS is the size of lookahead window. | |
e855c69d AB |
2718 | Return the av set computed. */ |
2719 | static av_set_t | |
2720 | compute_av_set_at_bb_end (insn_t insn, ilist_t p, int ws) | |
2721 | { | |
2722 | struct succs_info *sinfo; | |
2723 | av_set_t expr_in_all_succ_branches = NULL; | |
2724 | int is; | |
2725 | insn_t succ, zero_succ = NULL; | |
2726 | av_set_t av1 = NULL; | |
2727 | ||
2728 | gcc_assert (sel_bb_end_p (insn)); | |
2729 | ||
b8698a0f | 2730 | /* Find different kind of successors needed for correct computing of |
e855c69d AB |
2731 | SPEC and TARGET_AVAILABLE attributes. */ |
2732 | sinfo = compute_succs_info (insn, SUCCS_NORMAL); | |
2733 | ||
2734 | /* Debug output. */ | |
2735 | if (sched_verbose >= 6) | |
2736 | { | |
2737 | sel_print ("successors of bb end (%d): ", INSN_UID (insn)); | |
2738 | dump_insn_vector (sinfo->succs_ok); | |
2739 | sel_print ("\n"); | |
2740 | if (sinfo->succs_ok_n != sinfo->all_succs_n) | |
2741 | sel_print ("real successors num: %d\n", sinfo->all_succs_n); | |
2742 | } | |
2743 | ||
dd5a833e | 2744 | /* Add insn to the tail of current path. */ |
e855c69d AB |
2745 | ilist_add (&p, insn); |
2746 | ||
ac47786e | 2747 | FOR_EACH_VEC_ELT (rtx, sinfo->succs_ok, is, succ) |
e855c69d AB |
2748 | { |
2749 | av_set_t succ_set; | |
2750 | ||
2751 | /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */ | |
2752 | succ_set = compute_av_set_inside_bb (succ, p, ws, true); | |
2753 | ||
b8698a0f L |
2754 | av_set_split_usefulness (succ_set, |
2755 | VEC_index (int, sinfo->probs_ok, is), | |
e855c69d AB |
2756 | sinfo->all_prob); |
2757 | ||
c6486552 | 2758 | if (sinfo->all_succs_n > 1) |
e855c69d | 2759 | { |
b8698a0f | 2760 | /* Find EXPR'es that came from *all* successors and save them |
e855c69d AB |
2761 | into expr_in_all_succ_branches. This set will be used later |
2762 | for calculating speculation attributes of EXPR'es. */ | |
2763 | if (is == 0) | |
2764 | { | |
2765 | expr_in_all_succ_branches = av_set_copy (succ_set); | |
2766 | ||
2767 | /* Remember the first successor for later. */ | |
2768 | zero_succ = succ; | |
2769 | } | |
2770 | else | |
2771 | { | |
2772 | av_set_iterator i; | |
2773 | expr_t expr; | |
b8698a0f | 2774 | |
e855c69d AB |
2775 | FOR_EACH_EXPR_1 (expr, i, &expr_in_all_succ_branches) |
2776 | if (!av_set_is_in_p (succ_set, EXPR_VINSN (expr))) | |
2777 | av_set_iter_remove (&i); | |
2778 | } | |
2779 | } | |
2780 | ||
2781 | /* Union the av_sets. Check liveness restrictions on target registers | |
2782 | in special case of two successors. */ | |
2783 | if (sinfo->succs_ok_n == 2 && is == 1) | |
2784 | { | |
2785 | basic_block bb0 = BLOCK_FOR_INSN (zero_succ); | |
2786 | basic_block bb1 = BLOCK_FOR_INSN (succ); | |
2787 | ||
2788 | gcc_assert (BB_LV_SET_VALID_P (bb0) && BB_LV_SET_VALID_P (bb1)); | |
b8698a0f | 2789 | av_set_union_and_live (&av1, &succ_set, |
e855c69d AB |
2790 | BB_LV_SET (bb0), |
2791 | BB_LV_SET (bb1), | |
2792 | insn); | |
2793 | } | |
2794 | else | |
2795 | av_set_union_and_clear (&av1, &succ_set, insn); | |
2796 | } | |
2797 | ||
b8698a0f | 2798 | /* Check liveness restrictions via hard way when there are more than |
e855c69d AB |
2799 | two successors. */ |
2800 | if (sinfo->succs_ok_n > 2) | |
ac47786e | 2801 | FOR_EACH_VEC_ELT (rtx, sinfo->succs_ok, is, succ) |
e855c69d AB |
2802 | { |
2803 | basic_block succ_bb = BLOCK_FOR_INSN (succ); | |
b8698a0f | 2804 | |
e855c69d | 2805 | gcc_assert (BB_LV_SET_VALID_P (succ_bb)); |
b8698a0f | 2806 | mark_unavailable_targets (av1, BB_AV_SET (succ_bb), |
e855c69d AB |
2807 | BB_LV_SET (succ_bb)); |
2808 | } | |
b8698a0f L |
2809 | |
2810 | /* Finally, check liveness restrictions on paths leaving the region. */ | |
e855c69d | 2811 | if (sinfo->all_succs_n > sinfo->succs_ok_n) |
ac47786e | 2812 | FOR_EACH_VEC_ELT (rtx, sinfo->succs_other, is, succ) |
b8698a0f | 2813 | mark_unavailable_targets |
e855c69d AB |
2814 | (av1, NULL, BB_LV_SET (BLOCK_FOR_INSN (succ))); |
2815 | ||
2816 | if (sinfo->all_succs_n > 1) | |
2817 | { | |
2818 | av_set_iterator i; | |
2819 | expr_t expr; | |
2820 | ||
b8698a0f | 2821 | /* Increase the spec attribute of all EXPR'es that didn't come |
e855c69d AB |
2822 | from all successors. */ |
2823 | FOR_EACH_EXPR (expr, i, av1) | |
2824 | if (!av_set_is_in_p (expr_in_all_succ_branches, EXPR_VINSN (expr))) | |
2825 | EXPR_SPEC (expr)++; | |
2826 | ||
2827 | av_set_clear (&expr_in_all_succ_branches); | |
b8698a0f L |
2828 | |
2829 | /* Do not move conditional branches through other | |
2830 | conditional branches. So, remove all conditional | |
e855c69d AB |
2831 | branches from av_set if current operator is a conditional |
2832 | branch. */ | |
2833 | av_set_substract_cond_branches (&av1); | |
2834 | } | |
b8698a0f | 2835 | |
e855c69d AB |
2836 | ilist_remove (&p); |
2837 | free_succs_info (sinfo); | |
2838 | ||
2839 | if (sched_verbose >= 6) | |
2840 | { | |
2841 | sel_print ("av_succs (%d): ", INSN_UID (insn)); | |
2842 | dump_av_set (av1); | |
2843 | sel_print ("\n"); | |
2844 | } | |
2845 | ||
2846 | return av1; | |
2847 | } | |
2848 | ||
b8698a0f L |
2849 | /* This function computes av_set for the FIRST_INSN by dragging valid |
2850 | av_set through all basic block insns either from the end of basic block | |
2851 | (computed using compute_av_set_at_bb_end) or from the insn on which | |
e855c69d AB |
2852 | MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set |
2853 | below the basic block and handling conditional branches. | |
2854 | FIRST_INSN - the basic block head, P - path consisting of the insns | |
2855 | traversed on the way to the FIRST_INSN (the path is sparse, only bb heads | |
2856 | and bb ends are added to the path), WS - current window size, | |
2857 | NEED_COPY_P - true if we'll make a copy of av_set before returning it. */ | |
2858 | static av_set_t | |
b8698a0f | 2859 | compute_av_set_inside_bb (insn_t first_insn, ilist_t p, int ws, |
e855c69d AB |
2860 | bool need_copy_p) |
2861 | { | |
2862 | insn_t cur_insn; | |
2863 | int end_ws = ws; | |
2864 | insn_t bb_end = sel_bb_end (BLOCK_FOR_INSN (first_insn)); | |
2865 | insn_t after_bb_end = NEXT_INSN (bb_end); | |
2866 | insn_t last_insn; | |
2867 | av_set_t av = NULL; | |
2868 | basic_block cur_bb = BLOCK_FOR_INSN (first_insn); | |
2869 | ||
2870 | /* Return NULL if insn is not on the legitimate downward path. */ | |
2871 | if (is_ineligible_successor (first_insn, p)) | |
2872 | { | |
2873 | if (sched_verbose >= 6) | |
2874 | sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn)); | |
2875 | ||
2876 | return NULL; | |
2877 | } | |
2878 | ||
b8698a0f | 2879 | /* If insn already has valid av(insn) computed, just return it. */ |
e855c69d AB |
2880 | if (AV_SET_VALID_P (first_insn)) |
2881 | { | |
2882 | av_set_t av_set; | |
2883 | ||
2884 | if (sel_bb_head_p (first_insn)) | |
2885 | av_set = BB_AV_SET (BLOCK_FOR_INSN (first_insn)); | |
2886 | else | |
2887 | av_set = NULL; | |
2888 | ||
2889 | if (sched_verbose >= 6) | |
2890 | { | |
2891 | sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn)); | |
2892 | dump_av_set (av_set); | |
2893 | sel_print ("\n"); | |
2894 | } | |
2895 | ||
2896 | return need_copy_p ? av_set_copy (av_set) : av_set; | |
2897 | } | |
2898 | ||
2899 | ilist_add (&p, first_insn); | |
2900 | ||
2901 | /* As the result after this loop have completed, in LAST_INSN we'll | |
b8698a0f L |
2902 | have the insn which has valid av_set to start backward computation |
2903 | from: it either will be NULL because on it the window size was exceeded | |
2904 | or other valid av_set as returned by compute_av_set for the last insn | |
e855c69d AB |
2905 | of the basic block. */ |
2906 | for (last_insn = first_insn; last_insn != after_bb_end; | |
2907 | last_insn = NEXT_INSN (last_insn)) | |
2908 | { | |
2909 | /* We may encounter valid av_set not only on bb_head, but also on | |
2910 | those insns on which previously MAX_WS was exceeded. */ | |
2911 | if (AV_SET_VALID_P (last_insn)) | |
2912 | { | |
2913 | if (sched_verbose >= 6) | |
2914 | sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn)); | |
2915 | break; | |
2916 | } | |
2917 | ||
2918 | /* The special case: the last insn of the BB may be an | |
2919 | ineligible_successor due to its SEQ_NO that was set on | |
2920 | it as a bookkeeping. */ | |
b8698a0f | 2921 | if (last_insn != first_insn |
e855c69d AB |
2922 | && is_ineligible_successor (last_insn, p)) |
2923 | { | |
2924 | if (sched_verbose >= 6) | |
2925 | sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn)); | |
b8698a0f | 2926 | break; |
e855c69d AB |
2927 | } |
2928 | ||
b5b8b0ac AO |
2929 | if (DEBUG_INSN_P (last_insn)) |
2930 | continue; | |
2931 | ||
e855c69d AB |
2932 | if (end_ws > max_ws) |
2933 | { | |
b8698a0f | 2934 | /* We can reach max lookahead size at bb_header, so clean av_set |
e855c69d AB |
2935 | first. */ |
2936 | INSN_WS_LEVEL (last_insn) = global_level; | |
2937 | ||
2938 | if (sched_verbose >= 6) | |
2939 | sel_print ("Insn %d is beyond the software lookahead window size\n", | |
2940 | INSN_UID (last_insn)); | |
2941 | break; | |
2942 | } | |
2943 | ||
2944 | end_ws++; | |
2945 | } | |
2946 | ||
2947 | /* Get the valid av_set into AV above the LAST_INSN to start backward | |
2948 | computation from. It either will be empty av_set or av_set computed from | |
2949 | the successors on the last insn of the current bb. */ | |
2950 | if (last_insn != after_bb_end) | |
2951 | { | |
2952 | av = NULL; | |
2953 | ||
b8698a0f | 2954 | /* This is needed only to obtain av_sets that are identical to |
e855c69d AB |
2955 | those computed by the old compute_av_set version. */ |
2956 | if (last_insn == first_insn && !INSN_NOP_P (last_insn)) | |
2957 | av_set_add (&av, INSN_EXPR (last_insn)); | |
2958 | } | |
2959 | else | |
2960 | /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */ | |
2961 | av = compute_av_set_at_bb_end (bb_end, p, end_ws); | |
2962 | ||
2963 | /* Compute av_set in AV starting from below the LAST_INSN up to | |
2964 | location above the FIRST_INSN. */ | |
2965 | for (cur_insn = PREV_INSN (last_insn); cur_insn != PREV_INSN (first_insn); | |
b8698a0f | 2966 | cur_insn = PREV_INSN (cur_insn)) |
e855c69d AB |
2967 | if (!INSN_NOP_P (cur_insn)) |
2968 | { | |
2969 | expr_t expr; | |
b8698a0f | 2970 | |
e855c69d | 2971 | moveup_set_expr (&av, cur_insn, false); |
b8698a0f L |
2972 | |
2973 | /* If the expression for CUR_INSN is already in the set, | |
e855c69d | 2974 | replace it by the new one. */ |
b8698a0f | 2975 | expr = av_set_lookup (av, INSN_VINSN (cur_insn)); |
e855c69d AB |
2976 | if (expr != NULL) |
2977 | { | |
2978 | clear_expr (expr); | |
2979 | copy_expr (expr, INSN_EXPR (cur_insn)); | |
2980 | } | |
2981 | else | |
2982 | av_set_add (&av, INSN_EXPR (cur_insn)); | |
2983 | } | |
2984 | ||
2985 | /* Clear stale bb_av_set. */ | |
2986 | if (sel_bb_head_p (first_insn)) | |
2987 | { | |
2988 | av_set_clear (&BB_AV_SET (cur_bb)); | |
2989 | BB_AV_SET (cur_bb) = need_copy_p ? av_set_copy (av) : av; | |
2990 | BB_AV_LEVEL (cur_bb) = global_level; | |
2991 | } | |
2992 | ||
2993 | if (sched_verbose >= 6) | |
2994 | { | |
2995 | sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn)); | |
2996 | dump_av_set (av); | |
2997 | sel_print ("\n"); | |
2998 | } | |
2999 | ||
3000 | ilist_remove (&p); | |
3001 | return av; | |
3002 | } | |
3003 | ||
3004 | /* Compute av set before INSN. | |
3005 | INSN - the current operation (actual rtx INSN) | |
3006 | P - the current path, which is list of insns visited so far | |
3007 | WS - software lookahead window size. | |
3008 | UNIQUE_P - TRUE, if returned av_set will be changed, hence | |
3009 | if we want to save computed av_set in s_i_d, we should make a copy of it. | |
3010 | ||
3011 | In the resulting set we will have only expressions that don't have delay | |
3012 | stalls and nonsubstitutable dependences. */ | |
3013 | static av_set_t | |
3014 | compute_av_set (insn_t insn, ilist_t p, int ws, bool unique_p) | |
3015 | { | |
3016 | return compute_av_set_inside_bb (insn, p, ws, unique_p); | |
3017 | } | |
3018 | ||
3019 | /* Propagate a liveness set LV through INSN. */ | |
3020 | static void | |
3021 | propagate_lv_set (regset lv, insn_t insn) | |
3022 | { | |
3023 | gcc_assert (INSN_P (insn)); | |
3024 | ||
3025 | if (INSN_NOP_P (insn)) | |
3026 | return; | |
3027 | ||
02b47899 | 3028 | df_simulate_one_insn_backwards (BLOCK_FOR_INSN (insn), insn, lv); |
e855c69d AB |
3029 | } |
3030 | ||
3031 | /* Return livness set at the end of BB. */ | |
3032 | static regset | |
3033 | compute_live_after_bb (basic_block bb) | |
3034 | { | |
3035 | edge e; | |
3036 | edge_iterator ei; | |
3037 | regset lv = get_clear_regset_from_pool (); | |
3038 | ||
3039 | gcc_assert (!ignore_first); | |
3040 | ||
3041 | FOR_EACH_EDGE (e, ei, bb->succs) | |
3042 | if (sel_bb_empty_p (e->dest)) | |
3043 | { | |
3044 | if (! BB_LV_SET_VALID_P (e->dest)) | |
3045 | { | |
3046 | gcc_unreachable (); | |
3047 | gcc_assert (BB_LV_SET (e->dest) == NULL); | |
3048 | BB_LV_SET (e->dest) = compute_live_after_bb (e->dest); | |
3049 | BB_LV_SET_VALID_P (e->dest) = true; | |
3050 | } | |
3051 | IOR_REG_SET (lv, BB_LV_SET (e->dest)); | |
3052 | } | |
3053 | else | |
3054 | IOR_REG_SET (lv, compute_live (sel_bb_head (e->dest))); | |
3055 | ||
3056 | return lv; | |
3057 | } | |
3058 | ||
3059 | /* Compute the set of all live registers at the point before INSN and save | |
3060 | it at INSN if INSN is bb header. */ | |
3061 | regset | |
3062 | compute_live (insn_t insn) | |
3063 | { | |
3064 | basic_block bb = BLOCK_FOR_INSN (insn); | |
3065 | insn_t final, temp; | |
3066 | regset lv; | |
3067 | ||
3068 | /* Return the valid set if we're already on it. */ | |
3069 | if (!ignore_first) | |
3070 | { | |
3071 | regset src = NULL; | |
b8698a0f | 3072 | |
e855c69d AB |
3073 | if (sel_bb_head_p (insn) && BB_LV_SET_VALID_P (bb)) |
3074 | src = BB_LV_SET (bb); | |
b8698a0f | 3075 | else |
e855c69d AB |
3076 | { |
3077 | gcc_assert (in_current_region_p (bb)); | |
3078 | if (INSN_LIVE_VALID_P (insn)) | |
3079 | src = INSN_LIVE (insn); | |
3080 | } | |
b8698a0f | 3081 | |
e855c69d AB |
3082 | if (src) |
3083 | { | |
3084 | lv = get_regset_from_pool (); | |
3085 | COPY_REG_SET (lv, src); | |
3086 | ||
3087 | if (sel_bb_head_p (insn) && ! BB_LV_SET_VALID_P (bb)) | |
3088 | { | |
3089 | COPY_REG_SET (BB_LV_SET (bb), lv); | |
3090 | BB_LV_SET_VALID_P (bb) = true; | |
3091 | } | |
b8698a0f | 3092 | |
e855c69d AB |
3093 | return_regset_to_pool (lv); |
3094 | return lv; | |
3095 | } | |
3096 | } | |
3097 | ||
3098 | /* We've skipped the wrong lv_set. Don't skip the right one. */ | |
3099 | ignore_first = false; | |
3100 | gcc_assert (in_current_region_p (bb)); | |
3101 | ||
b8698a0f L |
3102 | /* Find a valid LV set in this block or below, if needed. |
3103 | Start searching from the next insn: either ignore_first is true, or | |
e855c69d AB |
3104 | INSN doesn't have a correct live set. */ |
3105 | temp = NEXT_INSN (insn); | |
3106 | final = NEXT_INSN (BB_END (bb)); | |
3107 | while (temp != final && ! INSN_LIVE_VALID_P (temp)) | |
3108 | temp = NEXT_INSN (temp); | |
3109 | if (temp == final) | |
3110 | { | |
3111 | lv = compute_live_after_bb (bb); | |
3112 | temp = PREV_INSN (temp); | |
3113 | } | |
3114 | else | |
3115 | { | |
3116 | lv = get_regset_from_pool (); | |
3117 | COPY_REG_SET (lv, INSN_LIVE (temp)); | |
3118 | } | |
3119 | ||
3120 | /* Put correct lv sets on the insns which have bad sets. */ | |
3121 | final = PREV_INSN (insn); | |
3122 | while (temp != final) | |
3123 | { | |
3124 | propagate_lv_set (lv, temp); | |
3125 | COPY_REG_SET (INSN_LIVE (temp), lv); | |
3126 | INSN_LIVE_VALID_P (temp) = true; | |
3127 | temp = PREV_INSN (temp); | |
3128 | } | |
3129 | ||
3130 | /* Also put it in a BB. */ | |
3131 | if (sel_bb_head_p (insn)) | |
3132 | { | |
3133 | basic_block bb = BLOCK_FOR_INSN (insn); | |
b8698a0f | 3134 | |
e855c69d AB |
3135 | COPY_REG_SET (BB_LV_SET (bb), lv); |
3136 | BB_LV_SET_VALID_P (bb) = true; | |
3137 | } | |
b8698a0f | 3138 | |
e855c69d AB |
3139 | /* We return LV to the pool, but will not clear it there. Thus we can |
3140 | legimatelly use LV till the next use of regset_pool_get (). */ | |
3141 | return_regset_to_pool (lv); | |
3142 | return lv; | |
3143 | } | |
3144 | ||
3145 | /* Update liveness sets for INSN. */ | |
3146 | static inline void | |
3147 | update_liveness_on_insn (rtx insn) | |
3148 | { | |
3149 | ignore_first = true; | |
3150 | compute_live (insn); | |
3151 | } | |
3152 | ||
3153 | /* Compute liveness below INSN and write it into REGS. */ | |
3154 | static inline void | |
3155 | compute_live_below_insn (rtx insn, regset regs) | |
3156 | { | |
3157 | rtx succ; | |
3158 | succ_iterator si; | |
b8698a0f L |
3159 | |
3160 | FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_ALL) | |
e855c69d AB |
3161 | IOR_REG_SET (regs, compute_live (succ)); |
3162 | } | |
3163 | ||
3164 | /* Update the data gathered in av and lv sets starting from INSN. */ | |
3165 | static void | |
3166 | update_data_sets (rtx insn) | |
3167 | { | |
3168 | update_liveness_on_insn (insn); | |
3169 | if (sel_bb_head_p (insn)) | |
3170 | { | |
3171 | gcc_assert (AV_LEVEL (insn) != 0); | |
3172 | BB_AV_LEVEL (BLOCK_FOR_INSN (insn)) = -1; | |
3173 | compute_av_set (insn, NULL, 0, 0); | |
3174 | } | |
3175 | } | |
3176 | \f | |
3177 | ||
3178 | /* Helper for move_op () and find_used_regs (). | |
3179 | Return speculation type for which a check should be created on the place | |
3180 | of INSN. EXPR is one of the original ops we are searching for. */ | |
3181 | static ds_t | |
3182 | get_spec_check_type_for_insn (insn_t insn, expr_t expr) | |
3183 | { | |
3184 | ds_t to_check_ds; | |
3185 | ds_t already_checked_ds = EXPR_SPEC_DONE_DS (INSN_EXPR (insn)); | |
3186 | ||
3187 | to_check_ds = EXPR_SPEC_TO_CHECK_DS (expr); | |
3188 | ||
3189 | if (targetm.sched.get_insn_checked_ds) | |
3190 | already_checked_ds |= targetm.sched.get_insn_checked_ds (insn); | |
3191 | ||
3192 | if (spec_info != NULL | |
3193 | && (spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL)) | |
3194 | already_checked_ds |= BEGIN_CONTROL; | |
3195 | ||
3196 | already_checked_ds = ds_get_speculation_types (already_checked_ds); | |
3197 | ||
3198 | to_check_ds &= ~already_checked_ds; | |
3199 | ||
3200 | return to_check_ds; | |
3201 | } | |
3202 | ||
b8698a0f | 3203 | /* Find the set of registers that are unavailable for storing expres |
e855c69d AB |
3204 | while moving ORIG_OPS up on the path starting from INSN due to |
3205 | liveness (USED_REGS) or hardware restrictions (REG_RENAME_P). | |
3206 | ||
3207 | All the original operations found during the traversal are saved in the | |
3208 | ORIGINAL_INSNS list. | |
3209 | ||
3210 | REG_RENAME_P denotes the set of hardware registers that | |
3211 | can not be used with renaming due to the register class restrictions, | |
b8698a0f | 3212 | mode restrictions and other (the register we'll choose should be |
e855c69d AB |
3213 | compatible class with the original uses, shouldn't be in call_used_regs, |
3214 | should be HARD_REGNO_RENAME_OK etc). | |
3215 | ||
3216 | Returns TRUE if we've found all original insns, FALSE otherwise. | |
3217 | ||
3218 | This function utilizes code_motion_path_driver (formerly find_used_regs_1) | |
b8698a0f L |
3219 | to traverse the code motion paths. This helper function finds registers |
3220 | that are not available for storing expres while moving ORIG_OPS up on the | |
e855c69d AB |
3221 | path starting from INSN. A register considered as used on the moving path, |
3222 | if one of the following conditions is not satisfied: | |
3223 | ||
b8698a0f L |
3224 | (1) a register not set or read on any path from xi to an instance of |
3225 | the original operation, | |
3226 | (2) not among the live registers of the point immediately following the | |
e855c69d AB |
3227 | first original operation on a given downward path, except for the |
3228 | original target register of the operation, | |
b8698a0f | 3229 | (3) not live on the other path of any conditional branch that is passed |
e855c69d AB |
3230 | by the operation, in case original operations are not present on |
3231 | both paths of the conditional branch. | |
3232 | ||
3233 | All the original operations found during the traversal are saved in the | |
3234 | ORIGINAL_INSNS list. | |
3235 | ||
b8698a0f L |
3236 | REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path |
3237 | from INSN to original insn. In this case CALL_USED_REG_SET will be added | |
e855c69d AB |
3238 | to unavailable hard regs at the point original operation is found. */ |
3239 | ||
3240 | static bool | |
3241 | find_used_regs (insn_t insn, av_set_t orig_ops, regset used_regs, | |
3242 | struct reg_rename *reg_rename_p, def_list_t *original_insns) | |
3243 | { | |
3244 | def_list_iterator i; | |
3245 | def_t def; | |
3246 | int res; | |
3247 | bool needs_spec_check_p = false; | |
3248 | expr_t expr; | |
3249 | av_set_iterator expr_iter; | |
3250 | struct fur_static_params sparams; | |
3251 | struct cmpd_local_params lparams; | |
3252 | ||
3253 | /* We haven't visited any blocks yet. */ | |
3254 | bitmap_clear (code_motion_visited_blocks); | |
3255 | ||
3256 | /* Init parameters for code_motion_path_driver. */ | |
3257 | sparams.crosses_call = false; | |
3258 | sparams.original_insns = original_insns; | |
3259 | sparams.used_regs = used_regs; | |
b8698a0f | 3260 | |
e855c69d AB |
3261 | /* Set the appropriate hooks and data. */ |
3262 | code_motion_path_driver_info = &fur_hooks; | |
b8698a0f | 3263 | |
e855c69d AB |
3264 | res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams); |
3265 | ||
3266 | reg_rename_p->crosses_call |= sparams.crosses_call; | |
3267 | ||
3268 | gcc_assert (res == 1); | |
3269 | gcc_assert (original_insns && *original_insns); | |
3270 | ||
3271 | /* ??? We calculate whether an expression needs a check when computing | |
3272 | av sets. This information is not as precise as it could be due to | |
3273 | merging this bit in merge_expr. We can do better in find_used_regs, | |
b8698a0f | 3274 | but we want to avoid multiple traversals of the same code motion |
e855c69d AB |
3275 | paths. */ |
3276 | FOR_EACH_EXPR (expr, expr_iter, orig_ops) | |
3277 | needs_spec_check_p |= EXPR_NEEDS_SPEC_CHECK_P (expr); | |
3278 | ||
b8698a0f | 3279 | /* Mark hardware regs in REG_RENAME_P that are not suitable |
e855c69d AB |
3280 | for renaming expr in INSN due to hardware restrictions (register class, |
3281 | modes compatibility etc). */ | |
3282 | FOR_EACH_DEF (def, i, *original_insns) | |
3283 | { | |
3284 | vinsn_t vinsn = INSN_VINSN (def->orig_insn); | |
3285 | ||
3286 | if (VINSN_SEPARABLE_P (vinsn)) | |
3287 | mark_unavailable_hard_regs (def, reg_rename_p, used_regs); | |
3288 | ||
b8698a0f | 3289 | /* Do not allow clobbering of ld.[sa] address in case some of the |
e855c69d AB |
3290 | original operations need a check. */ |
3291 | if (needs_spec_check_p) | |
3292 | IOR_REG_SET (used_regs, VINSN_REG_USES (vinsn)); | |
3293 | } | |
3294 | ||
3295 | return true; | |
3296 | } | |
3297 | \f | |
3298 | ||
3299 | /* Functions to choose the best insn from available ones. */ | |
3300 | ||
3301 | /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */ | |
3302 | static int | |
3303 | sel_target_adjust_priority (expr_t expr) | |
3304 | { | |
3305 | int priority = EXPR_PRIORITY (expr); | |
3306 | int new_priority; | |
3307 | ||
3308 | if (targetm.sched.adjust_priority) | |
3309 | new_priority = targetm.sched.adjust_priority (EXPR_INSN_RTX (expr), priority); | |
3310 | else | |
3311 | new_priority = priority; | |
3312 | ||
3313 | /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */ | |
3314 | EXPR_PRIORITY_ADJ (expr) = new_priority - EXPR_PRIORITY (expr); | |
3315 | ||
3316 | gcc_assert (EXPR_PRIORITY_ADJ (expr) >= 0); | |
3317 | ||
136e01a3 AB |
3318 | if (sched_verbose >= 4) |
3319 | sel_print ("sel_target_adjust_priority: insn %d, %d+%d = %d.\n", | |
b8698a0f | 3320 | INSN_UID (EXPR_INSN_RTX (expr)), EXPR_PRIORITY (expr), |
e855c69d AB |
3321 | EXPR_PRIORITY_ADJ (expr), new_priority); |
3322 | ||
3323 | return new_priority; | |
3324 | } | |
3325 | ||
3326 | /* Rank two available exprs for schedule. Never return 0 here. */ | |
b8698a0f | 3327 | static int |
e855c69d AB |
3328 | sel_rank_for_schedule (const void *x, const void *y) |
3329 | { | |
3330 | expr_t tmp = *(const expr_t *) y; | |
3331 | expr_t tmp2 = *(const expr_t *) x; | |
3332 | insn_t tmp_insn, tmp2_insn; | |
3333 | vinsn_t tmp_vinsn, tmp2_vinsn; | |
3334 | int val; | |
3335 | ||
3336 | tmp_vinsn = EXPR_VINSN (tmp); | |
3337 | tmp2_vinsn = EXPR_VINSN (tmp2); | |
3338 | tmp_insn = EXPR_INSN_RTX (tmp); | |
3339 | tmp2_insn = EXPR_INSN_RTX (tmp2); | |
b8698a0f | 3340 | |
b5b8b0ac AO |
3341 | /* Schedule debug insns as early as possible. */ |
3342 | if (DEBUG_INSN_P (tmp_insn) && !DEBUG_INSN_P (tmp2_insn)) | |
3343 | return -1; | |
3344 | else if (DEBUG_INSN_P (tmp2_insn)) | |
3345 | return 1; | |
3346 | ||
e855c69d AB |
3347 | /* Prefer SCHED_GROUP_P insns to any others. */ |
3348 | if (SCHED_GROUP_P (tmp_insn) != SCHED_GROUP_P (tmp2_insn)) | |
3349 | { | |
b8698a0f | 3350 | if (VINSN_UNIQUE_P (tmp_vinsn) && VINSN_UNIQUE_P (tmp2_vinsn)) |
e855c69d AB |
3351 | return SCHED_GROUP_P (tmp2_insn) ? 1 : -1; |
3352 | ||
3353 | /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups | |
3354 | cannot be cloned. */ | |
3355 | if (VINSN_UNIQUE_P (tmp2_vinsn)) | |
3356 | return 1; | |
3357 | return -1; | |
3358 | } | |
3359 | ||
3360 | /* Discourage scheduling of speculative checks. */ | |
3361 | val = (sel_insn_is_speculation_check (tmp_insn) | |
3362 | - sel_insn_is_speculation_check (tmp2_insn)); | |
3363 | if (val) | |
3364 | return val; | |
3365 | ||
3366 | /* Prefer not scheduled insn over scheduled one. */ | |
3367 | if (EXPR_SCHED_TIMES (tmp) > 0 || EXPR_SCHED_TIMES (tmp2) > 0) | |
3368 | { | |
3369 | val = EXPR_SCHED_TIMES (tmp) - EXPR_SCHED_TIMES (tmp2); | |
3370 | if (val) | |
3371 | return val; | |
3372 | } | |
3373 | ||
3374 | /* Prefer jump over non-jump instruction. */ | |
3375 | if (control_flow_insn_p (tmp_insn) && !control_flow_insn_p (tmp2_insn)) | |
3376 | return -1; | |
3377 | else if (control_flow_insn_p (tmp2_insn) && !control_flow_insn_p (tmp_insn)) | |
3378 | return 1; | |
3379 | ||
3380 | /* Prefer an expr with greater priority. */ | |
3381 | if (EXPR_USEFULNESS (tmp) != 0 && EXPR_USEFULNESS (tmp2) != 0) | |
3382 | { | |
3383 | int p2 = EXPR_PRIORITY (tmp2) + EXPR_PRIORITY_ADJ (tmp2), | |
3384 | p1 = EXPR_PRIORITY (tmp) + EXPR_PRIORITY_ADJ (tmp); | |
3385 | ||
3386 | val = p2 * EXPR_USEFULNESS (tmp2) - p1 * EXPR_USEFULNESS (tmp); | |
3387 | } | |
3388 | else | |
b8698a0f | 3389 | val = EXPR_PRIORITY (tmp2) - EXPR_PRIORITY (tmp) |
e855c69d AB |
3390 | + EXPR_PRIORITY_ADJ (tmp2) - EXPR_PRIORITY_ADJ (tmp); |
3391 | if (val) | |
3392 | return val; | |
3393 | ||
3394 | if (spec_info != NULL && spec_info->mask != 0) | |
3395 | /* This code was taken from haifa-sched.c: rank_for_schedule (). */ | |
3396 | { | |
3397 | ds_t ds1, ds2; | |
3398 | dw_t dw1, dw2; | |
3399 | int dw; | |
3400 | ||
3401 | ds1 = EXPR_SPEC_DONE_DS (tmp); | |
3402 | if (ds1) | |
3403 | dw1 = ds_weak (ds1); | |
3404 | else | |
3405 | dw1 = NO_DEP_WEAK; | |
3406 | ||
3407 | ds2 = EXPR_SPEC_DONE_DS (tmp2); | |
3408 | if (ds2) | |
3409 | dw2 = ds_weak (ds2); | |
3410 | else | |
3411 | dw2 = NO_DEP_WEAK; | |
3412 | ||
3413 | dw = dw2 - dw1; | |
3414 | if (dw > (NO_DEP_WEAK / 8) || dw < -(NO_DEP_WEAK / 8)) | |
3415 | return dw; | |
3416 | } | |
3417 | ||
e855c69d | 3418 | /* Prefer an old insn to a bookkeeping insn. */ |
b8698a0f | 3419 | if (INSN_UID (tmp_insn) < first_emitted_uid |
e855c69d AB |
3420 | && INSN_UID (tmp2_insn) >= first_emitted_uid) |
3421 | return -1; | |
b8698a0f | 3422 | if (INSN_UID (tmp_insn) >= first_emitted_uid |
e855c69d AB |
3423 | && INSN_UID (tmp2_insn) < first_emitted_uid) |
3424 | return 1; | |
3425 | ||
b8698a0f | 3426 | /* Prefer an insn with smaller UID, as a last resort. |
e855c69d AB |
3427 | We can't safely use INSN_LUID as it is defined only for those insns |
3428 | that are in the stream. */ | |
3429 | return INSN_UID (tmp_insn) - INSN_UID (tmp2_insn); | |
3430 | } | |
3431 | ||
b8698a0f | 3432 | /* Filter out expressions from av set pointed to by AV_PTR |
e855c69d AB |
3433 | that are pipelined too many times. */ |
3434 | static void | |
3435 | process_pipelined_exprs (av_set_t *av_ptr) | |
3436 | { | |
3437 | expr_t expr; | |
3438 | av_set_iterator si; | |
3439 | ||
3440 | /* Don't pipeline already pipelined code as that would increase | |
b8698a0f | 3441 | number of unnecessary register moves. */ |
e855c69d AB |
3442 | FOR_EACH_EXPR_1 (expr, si, av_ptr) |
3443 | { | |
3444 | if (EXPR_SCHED_TIMES (expr) | |
3445 | >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES)) | |
3446 | av_set_iter_remove (&si); | |
3447 | } | |
3448 | } | |
3449 | ||
3450 | /* Filter speculative insns from AV_PTR if we don't want them. */ | |
3451 | static void | |
3452 | process_spec_exprs (av_set_t *av_ptr) | |
3453 | { | |
3454 | bool try_data_p = true; | |
3455 | bool try_control_p = true; | |
3456 | expr_t expr; | |
3457 | av_set_iterator si; | |
3458 | ||
3459 | if (spec_info == NULL) | |
3460 | return; | |
3461 | ||
3462 | /* Scan *AV_PTR to find out if we want to consider speculative | |
3463 | instructions for scheduling. */ | |
3464 | FOR_EACH_EXPR_1 (expr, si, av_ptr) | |
3465 | { | |
3466 | ds_t ds; | |
3467 | ||
3468 | ds = EXPR_SPEC_DONE_DS (expr); | |
3469 | ||
3470 | /* The probability of a success is too low - don't speculate. */ | |
3471 | if ((ds & SPECULATIVE) | |
3472 | && (ds_weak (ds) < spec_info->data_weakness_cutoff | |
3473 | || EXPR_USEFULNESS (expr) < spec_info->control_weakness_cutoff | |
3474 | || (pipelining_p && false | |
3475 | && (ds & DATA_SPEC) | |
3476 | && (ds & CONTROL_SPEC)))) | |
3477 | { | |
3478 | av_set_iter_remove (&si); | |
3479 | continue; | |
3480 | } | |
3481 | ||
3482 | if ((spec_info->flags & PREFER_NON_DATA_SPEC) | |
3483 | && !(ds & BEGIN_DATA)) | |
3484 | try_data_p = false; | |
3485 | ||
3486 | if ((spec_info->flags & PREFER_NON_CONTROL_SPEC) | |
3487 | && !(ds & BEGIN_CONTROL)) | |
3488 | try_control_p = false; | |
3489 | } | |
3490 | ||
3491 | FOR_EACH_EXPR_1 (expr, si, av_ptr) | |
3492 | { | |
3493 | ds_t ds; | |
3494 | ||
3495 | ds = EXPR_SPEC_DONE_DS (expr); | |
3496 | ||
3497 | if (ds & SPECULATIVE) | |
3498 | { | |
3499 | if ((ds & BEGIN_DATA) && !try_data_p) | |
3500 | /* We don't want any data speculative instructions right | |
3501 | now. */ | |
3502 | av_set_iter_remove (&si); | |
3503 | ||
3504 | if ((ds & BEGIN_CONTROL) && !try_control_p) | |
3505 | /* We don't want any control speculative instructions right | |
3506 | now. */ | |
3507 | av_set_iter_remove (&si); | |
3508 | } | |
3509 | } | |
3510 | } | |
3511 | ||
b8698a0f L |
3512 | /* Search for any use-like insns in AV_PTR and decide on scheduling |
3513 | them. Return one when found, and NULL otherwise. | |
e855c69d AB |
3514 | Note that we check here whether a USE could be scheduled to avoid |
3515 | an infinite loop later. */ | |
3516 | static expr_t | |
3517 | process_use_exprs (av_set_t *av_ptr) | |
3518 | { | |
3519 | expr_t expr; | |
3520 | av_set_iterator si; | |
3521 | bool uses_present_p = false; | |
3522 | bool try_uses_p = true; | |
3523 | ||
3524 | FOR_EACH_EXPR_1 (expr, si, av_ptr) | |
3525 | { | |
3526 | /* This will also initialize INSN_CODE for later use. */ | |
3527 | if (recog_memoized (EXPR_INSN_RTX (expr)) < 0) | |
3528 | { | |
3529 | /* If we have a USE in *AV_PTR that was not scheduled yet, | |
3530 | do so because it will do good only. */ | |
3531 | if (EXPR_SCHED_TIMES (expr) <= 0) | |
3532 | { | |
3533 | if (EXPR_TARGET_AVAILABLE (expr) == 1) | |
3534 | return expr; | |
3535 | ||
3536 | av_set_iter_remove (&si); | |
3537 | } | |
3538 | else | |
3539 | { | |
3540 | gcc_assert (pipelining_p); | |
3541 | ||
3542 | uses_present_p = true; | |
3543 | } | |
3544 | } | |
3545 | else | |
3546 | try_uses_p = false; | |
3547 | } | |
3548 | ||
3549 | if (uses_present_p) | |
3550 | { | |
3551 | /* If we don't want to schedule any USEs right now and we have some | |
3552 | in *AV_PTR, remove them, else just return the first one found. */ | |
3553 | if (!try_uses_p) | |
3554 | { | |
3555 | FOR_EACH_EXPR_1 (expr, si, av_ptr) | |
3556 | if (INSN_CODE (EXPR_INSN_RTX (expr)) < 0) | |
3557 | av_set_iter_remove (&si); | |
3558 | } | |
3559 | else | |
3560 | { | |
3561 | FOR_EACH_EXPR_1 (expr, si, av_ptr) | |
3562 | { | |
3563 | gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr)) < 0); | |
3564 | ||
3565 | if (EXPR_TARGET_AVAILABLE (expr) == 1) | |
3566 | return expr; | |
3567 | ||
3568 | av_set_iter_remove (&si); | |
3569 | } | |
3570 | } | |
3571 | } | |
3572 | ||
3573 | return NULL; | |
3574 | } | |
3575 | ||
3576 | /* Lookup EXPR in VINSN_VEC and return TRUE if found. */ | |
3577 | static bool | |
3578 | vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec, expr_t expr) | |
3579 | { | |
3580 | vinsn_t vinsn; | |
3581 | int n; | |
3582 | ||
ac47786e | 3583 | FOR_EACH_VEC_ELT (vinsn_t, vinsn_vec, n, vinsn) |
e855c69d AB |
3584 | if (VINSN_SEPARABLE_P (vinsn)) |
3585 | { | |
3586 | if (vinsn_equal_p (vinsn, EXPR_VINSN (expr))) | |
3587 | return true; | |
3588 | } | |
3589 | else | |
3590 | { | |
3591 | /* For non-separable instructions, the blocking insn can have | |
3592 | another pattern due to substitution, and we can't choose | |
3593 | different register as in the above case. Check all registers | |
3594 | being written instead. */ | |
b8698a0f | 3595 | if (bitmap_intersect_p (VINSN_REG_SETS (vinsn), |
e855c69d AB |
3596 | VINSN_REG_SETS (EXPR_VINSN (expr)))) |
3597 | return true; | |
3598 | } | |
3599 | ||
3600 | return false; | |
3601 | } | |
3602 | ||
3603 | #ifdef ENABLE_CHECKING | |
3604 | /* Return true if either of expressions from ORIG_OPS can be blocked | |
3605 | by previously created bookkeeping code. STATIC_PARAMS points to static | |
3606 | parameters of move_op. */ | |
3607 | static bool | |
3608 | av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops, void *static_params) | |
3609 | { | |
3610 | expr_t expr; | |
3611 | av_set_iterator iter; | |
3612 | moveop_static_params_p sparams; | |
3613 | ||
3614 | /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping | |
3615 | created while scheduling on another fence. */ | |
3616 | FOR_EACH_EXPR (expr, iter, orig_ops) | |
3617 | if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr)) | |
3618 | return true; | |
3619 | ||
3620 | gcc_assert (code_motion_path_driver_info == &move_op_hooks); | |
3621 | sparams = (moveop_static_params_p) static_params; | |
3622 | ||
3623 | /* Expressions can be also blocked by bookkeeping created during current | |
3624 | move_op. */ | |
3625 | if (bitmap_bit_p (current_copies, INSN_UID (sparams->failed_insn))) | |
3626 | FOR_EACH_EXPR (expr, iter, orig_ops) | |
3627 | if (moveup_expr_cached (expr, sparams->failed_insn, false) != MOVEUP_EXPR_NULL) | |
3628 | return true; | |
3629 | ||
3630 | /* Expressions in ORIG_OPS may have wrong destination register due to | |
3631 | renaming. Check with the right register instead. */ | |
3632 | if (sparams->dest && REG_P (sparams->dest)) | |
3633 | { | |
3634 | unsigned regno = REGNO (sparams->dest); | |
3635 | vinsn_t failed_vinsn = INSN_VINSN (sparams->failed_insn); | |
3636 | ||
3637 | if (bitmap_bit_p (VINSN_REG_SETS (failed_vinsn), regno) | |
3638 | || bitmap_bit_p (VINSN_REG_USES (failed_vinsn), regno) | |
3639 | || bitmap_bit_p (VINSN_REG_CLOBBERS (failed_vinsn), regno)) | |
3640 | return true; | |
3641 | } | |
3642 | ||
3643 | return false; | |
3644 | } | |
3645 | #endif | |
3646 | ||
3647 | /* Clear VINSN_VEC and detach vinsns. */ | |
3648 | static void | |
3649 | vinsn_vec_clear (vinsn_vec_t *vinsn_vec) | |
3650 | { | |
3651 | unsigned len = VEC_length (vinsn_t, *vinsn_vec); | |
3652 | if (len > 0) | |
3653 | { | |
3654 | vinsn_t vinsn; | |
3655 | int n; | |
b8698a0f | 3656 | |
ac47786e | 3657 | FOR_EACH_VEC_ELT (vinsn_t, *vinsn_vec, n, vinsn) |
e855c69d AB |
3658 | vinsn_detach (vinsn); |
3659 | VEC_block_remove (vinsn_t, *vinsn_vec, 0, len); | |
3660 | } | |
3661 | } | |
3662 | ||
3663 | /* Add the vinsn of EXPR to the VINSN_VEC. */ | |
3664 | static void | |
3665 | vinsn_vec_add (vinsn_vec_t *vinsn_vec, expr_t expr) | |
3666 | { | |
3667 | vinsn_attach (EXPR_VINSN (expr)); | |
3668 | VEC_safe_push (vinsn_t, heap, *vinsn_vec, EXPR_VINSN (expr)); | |
3669 | } | |
3670 | ||
b8698a0f | 3671 | /* Free the vector representing blocked expressions. */ |
e855c69d AB |
3672 | static void |
3673 | vinsn_vec_free (vinsn_vec_t *vinsn_vec) | |
3674 | { | |
3675 | if (*vinsn_vec) | |
3676 | VEC_free (vinsn_t, heap, *vinsn_vec); | |
3677 | } | |
3678 | ||
3679 | /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */ | |
3680 | ||
3681 | void sel_add_to_insn_priority (rtx insn, int amount) | |
3682 | { | |
3683 | EXPR_PRIORITY_ADJ (INSN_EXPR (insn)) += amount; | |
3684 | ||
3685 | if (sched_verbose >= 2) | |
b8698a0f | 3686 | sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n", |
e855c69d AB |
3687 | INSN_UID (insn), amount, EXPR_PRIORITY (INSN_EXPR (insn)), |
3688 | EXPR_PRIORITY_ADJ (INSN_EXPR (insn))); | |
3689 | } | |
3690 | ||
b8698a0f | 3691 | /* Turn AV into a vector, filter inappropriate insns and sort it. Return |
e855c69d AB |
3692 | true if there is something to schedule. BNDS and FENCE are current |
3693 | boundaries and fence, respectively. If we need to stall for some cycles | |
b8698a0f | 3694 | before an expr from AV would become available, write this number to |
e855c69d AB |
3695 | *PNEED_STALL. */ |
3696 | static bool | |
3697 | fill_vec_av_set (av_set_t av, blist_t bnds, fence_t fence, | |
3698 | int *pneed_stall) | |
3699 | { | |
3700 | av_set_iterator si; | |
3701 | expr_t expr; | |
3702 | int sched_next_worked = 0, stalled, n; | |
3703 | static int av_max_prio, est_ticks_till_branch; | |
3704 | int min_need_stall = -1; | |
3705 | deps_t dc = BND_DC (BLIST_BND (bnds)); | |
3706 | ||
3707 | /* Bail out early when the ready list contained only USEs/CLOBBERs that are | |
3708 | already scheduled. */ | |
3709 | if (av == NULL) | |
3710 | return false; | |
3711 | ||
3712 | /* Empty vector from the previous stuff. */ | |
3713 | if (VEC_length (expr_t, vec_av_set) > 0) | |
3714 | VEC_block_remove (expr_t, vec_av_set, 0, VEC_length (expr_t, vec_av_set)); | |
3715 | ||
3716 | /* Turn the set into a vector for sorting and call sel_target_adjust_priority | |
3717 | for each insn. */ | |
3718 | gcc_assert (VEC_empty (expr_t, vec_av_set)); | |
3719 | FOR_EACH_EXPR (expr, si, av) | |
b8698a0f | 3720 | { |
e855c69d AB |
3721 | VEC_safe_push (expr_t, heap, vec_av_set, expr); |
3722 | ||
3723 | gcc_assert (EXPR_PRIORITY_ADJ (expr) == 0 || *pneed_stall); | |
3724 | ||
3725 | /* Adjust priority using target backend hook. */ | |
3726 | sel_target_adjust_priority (expr); | |
3727 | } | |
3728 | ||
3729 | /* Sort the vector. */ | |
5095da95 | 3730 | VEC_qsort (expr_t, vec_av_set, sel_rank_for_schedule); |
e855c69d AB |
3731 | |
3732 | /* We record maximal priority of insns in av set for current instruction | |
3733 | group. */ | |
3734 | if (FENCE_STARTS_CYCLE_P (fence)) | |
3735 | av_max_prio = est_ticks_till_branch = INT_MIN; | |
3736 | ||
3737 | /* Filter out inappropriate expressions. Loop's direction is reversed to | |
3738 | visit "best" instructions first. We assume that VEC_unordered_remove | |
3739 | moves last element in place of one being deleted. */ | |
3740 | for (n = VEC_length (expr_t, vec_av_set) - 1, stalled = 0; n >= 0; n--) | |
3741 | { | |
3742 | expr_t expr = VEC_index (expr_t, vec_av_set, n); | |
3743 | insn_t insn = EXPR_INSN_RTX (expr); | |
f3764768 | 3744 | signed char target_available; |
e855c69d AB |
3745 | bool is_orig_reg_p = true; |
3746 | int need_cycles, new_prio; | |
3747 | ||
3748 | /* Don't allow any insns other than from SCHED_GROUP if we have one. */ | |
3749 | if (FENCE_SCHED_NEXT (fence) && insn != FENCE_SCHED_NEXT (fence)) | |
3750 | { | |
3751 | VEC_unordered_remove (expr_t, vec_av_set, n); | |
3752 | continue; | |
3753 | } | |
3754 | ||
b8698a0f | 3755 | /* Set number of sched_next insns (just in case there |
e855c69d AB |
3756 | could be several). */ |
3757 | if (FENCE_SCHED_NEXT (fence)) | |
3758 | sched_next_worked++; | |
b8698a0f L |
3759 | |
3760 | /* Check all liveness requirements and try renaming. | |
e855c69d AB |
3761 | FIXME: try to minimize calls to this. */ |
3762 | target_available = EXPR_TARGET_AVAILABLE (expr); | |
3763 | ||
3764 | /* If insn was already scheduled on the current fence, | |
3765 | set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */ | |
3766 | if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns, expr)) | |
3767 | target_available = -1; | |
3768 | ||
3769 | /* If the availability of the EXPR is invalidated by the insertion of | |
3770 | bookkeeping earlier, make sure that we won't choose this expr for | |
3771 | scheduling if it's not separable, and if it is separable, then | |
3772 | we have to recompute the set of available registers for it. */ | |
3773 | if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr)) | |
3774 | { | |
3775 | VEC_unordered_remove (expr_t, vec_av_set, n); | |
3776 | if (sched_verbose >= 4) | |
3777 | sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n", | |
3778 | INSN_UID (insn)); | |
3779 | continue; | |
3780 | } | |
b8698a0f | 3781 | |
e855c69d AB |
3782 | if (target_available == true) |
3783 | { | |
3784 | /* Do nothing -- we can use an existing register. */ | |
3785 | is_orig_reg_p = EXPR_SEPARABLE_P (expr); | |
3786 | } | |
b8698a0f | 3787 | else if (/* Non-separable instruction will never |
e855c69d AB |
3788 | get another register. */ |
3789 | (target_available == false | |
3790 | && !EXPR_SEPARABLE_P (expr)) | |
3791 | /* Don't try to find a register for low-priority expression. */ | |
3792 | || (int) VEC_length (expr_t, vec_av_set) - 1 - n >= max_insns_to_rename | |
3793 | /* ??? FIXME: Don't try to rename data speculation. */ | |
3794 | || (EXPR_SPEC_DONE_DS (expr) & BEGIN_DATA) | |
3795 | || ! find_best_reg_for_expr (expr, bnds, &is_orig_reg_p)) | |
3796 | { | |
3797 | VEC_unordered_remove (expr_t, vec_av_set, n); | |
3798 | if (sched_verbose >= 4) | |
b8698a0f | 3799 | sel_print ("Expr %d has no suitable target register\n", |
e855c69d AB |
3800 | INSN_UID (insn)); |
3801 | continue; | |
3802 | } | |
3803 | ||
3804 | /* Filter expressions that need to be renamed or speculated when | |
3805 | pipelining, because compensating register copies or speculation | |
3806 | checks are likely to be placed near the beginning of the loop, | |
3807 | causing a stall. */ | |
3808 | if (pipelining_p && EXPR_ORIG_SCHED_CYCLE (expr) > 0 | |
3809 | && (!is_orig_reg_p || EXPR_SPEC_DONE_DS (expr) != 0)) | |
3810 | { | |
3811 | /* Estimation of number of cycles until loop branch for | |
3812 | renaming/speculation to be successful. */ | |
3813 | int need_n_ticks_till_branch = sel_vinsn_cost (EXPR_VINSN (expr)); | |
3814 | ||
3815 | if ((int) current_loop_nest->ninsns < 9) | |
3816 | { | |
3817 | VEC_unordered_remove (expr_t, vec_av_set, n); | |
3818 | if (sched_verbose >= 4) | |
3819 | sel_print ("Pipelining expr %d will likely cause stall\n", | |
3820 | INSN_UID (insn)); | |
3821 | continue; | |
3822 | } | |
3823 | ||
3824 | if ((int) current_loop_nest->ninsns - num_insns_scheduled | |
3825 | < need_n_ticks_till_branch * issue_rate / 2 | |
3826 | && est_ticks_till_branch < need_n_ticks_till_branch) | |
3827 | { | |
3828 | VEC_unordered_remove (expr_t, vec_av_set, n); | |
3829 | if (sched_verbose >= 4) | |
3830 | sel_print ("Pipelining expr %d will likely cause stall\n", | |
3831 | INSN_UID (insn)); | |
3832 | continue; | |
3833 | } | |
3834 | } | |
3835 | ||
3836 | /* We want to schedule speculation checks as late as possible. Discard | |
3837 | them from av set if there are instructions with higher priority. */ | |
3838 | if (sel_insn_is_speculation_check (insn) | |
3839 | && EXPR_PRIORITY (expr) < av_max_prio) | |
3840 | { | |
3841 | stalled++; | |
3842 | min_need_stall = min_need_stall < 0 ? 1 : MIN (min_need_stall, 1); | |
3843 | VEC_unordered_remove (expr_t, vec_av_set, n); | |
3844 | if (sched_verbose >= 4) | |
3845 | sel_print ("Delaying speculation check %d until its first use\n", | |
3846 | INSN_UID (insn)); | |
3847 | continue; | |
3848 | } | |
3849 | ||
3850 | /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */ | |
3851 | if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0) | |
3852 | av_max_prio = MAX (av_max_prio, EXPR_PRIORITY (expr)); | |
3853 | ||
3854 | /* Don't allow any insns whose data is not yet ready. | |
3855 | Check first whether we've already tried them and failed. */ | |
3856 | if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence)) | |
3857 | { | |
3858 | need_cycles = (FENCE_READY_TICKS (fence)[INSN_UID (insn)] | |
3859 | - FENCE_CYCLE (fence)); | |
3860 | if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0) | |
3861 | est_ticks_till_branch = MAX (est_ticks_till_branch, | |
3862 | EXPR_PRIORITY (expr) + need_cycles); | |
3863 | ||
3864 | if (need_cycles > 0) | |
3865 | { | |
3866 | stalled++; | |
b8698a0f | 3867 | min_need_stall = (min_need_stall < 0 |
e855c69d AB |
3868 | ? need_cycles |
3869 | : MIN (min_need_stall, need_cycles)); | |
3870 | VEC_unordered_remove (expr_t, vec_av_set, n); | |
3871 | ||
3872 | if (sched_verbose >= 4) | |
b8698a0f | 3873 | sel_print ("Expr %d is not ready until cycle %d (cached)\n", |
e855c69d AB |
3874 | INSN_UID (insn), |
3875 | FENCE_READY_TICKS (fence)[INSN_UID (insn)]); | |
3876 | continue; | |
3877 | } | |
3878 | } | |
3879 | ||
b8698a0f | 3880 | /* Now resort to dependence analysis to find whether EXPR might be |
e855c69d AB |
3881 | stalled due to dependencies from FENCE's context. */ |
3882 | need_cycles = tick_check_p (expr, dc, fence); | |
3883 | new_prio = EXPR_PRIORITY (expr) + EXPR_PRIORITY_ADJ (expr) + need_cycles; | |
3884 | ||
3885 | if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0) | |
3886 | est_ticks_till_branch = MAX (est_ticks_till_branch, | |
3887 | new_prio); | |
3888 | ||
3889 | if (need_cycles > 0) | |
3890 | { | |
3891 | if (INSN_UID (insn) >= FENCE_READY_TICKS_SIZE (fence)) | |
3892 | { | |
3893 | int new_size = INSN_UID (insn) * 3 / 2; | |
b8698a0f L |
3894 | |
3895 | FENCE_READY_TICKS (fence) | |
e855c69d AB |
3896 | = (int *) xrecalloc (FENCE_READY_TICKS (fence), |
3897 | new_size, FENCE_READY_TICKS_SIZE (fence), | |
3898 | sizeof (int)); | |
3899 | } | |
b8698a0f L |
3900 | FENCE_READY_TICKS (fence)[INSN_UID (insn)] |
3901 | = FENCE_CYCLE (fence) + need_cycles; | |
3902 | ||
e855c69d | 3903 | stalled++; |
b8698a0f | 3904 | min_need_stall = (min_need_stall < 0 |
e855c69d AB |
3905 | ? need_cycles |
3906 | : MIN (min_need_stall, need_cycles)); | |
3907 | ||
3908 | VEC_unordered_remove (expr_t, vec_av_set, n); | |
b8698a0f | 3909 | |
e855c69d | 3910 | if (sched_verbose >= 4) |
b8698a0f | 3911 | sel_print ("Expr %d is not ready yet until cycle %d\n", |
e855c69d AB |
3912 | INSN_UID (insn), |
3913 | FENCE_READY_TICKS (fence)[INSN_UID (insn)]); | |
3914 | continue; | |
3915 | } | |
3916 | ||
3917 | if (sched_verbose >= 4) | |
3918 | sel_print ("Expr %d is ok\n", INSN_UID (insn)); | |
3919 | min_need_stall = 0; | |
3920 | } | |
3921 | ||
3922 | /* Clear SCHED_NEXT. */ | |
3923 | if (FENCE_SCHED_NEXT (fence)) | |
3924 | { | |
3925 | gcc_assert (sched_next_worked == 1); | |
3926 | FENCE_SCHED_NEXT (fence) = NULL_RTX; | |
3927 | } | |
3928 | ||
3929 | /* No need to stall if this variable was not initialized. */ | |
3930 | if (min_need_stall < 0) | |
3931 | min_need_stall = 0; | |
3932 | ||
3933 | if (VEC_empty (expr_t, vec_av_set)) | |
3934 | { | |
3935 | /* We need to set *pneed_stall here, because later we skip this code | |
3936 | when ready list is empty. */ | |
3937 | *pneed_stall = min_need_stall; | |
3938 | return false; | |
3939 | } | |
3940 | else | |
3941 | gcc_assert (min_need_stall == 0); | |
3942 | ||
3943 | /* Sort the vector. */ | |
5095da95 | 3944 | VEC_qsort (expr_t, vec_av_set, sel_rank_for_schedule); |
b8698a0f | 3945 | |
e855c69d AB |
3946 | if (sched_verbose >= 4) |
3947 | { | |
b8698a0f | 3948 | sel_print ("Total ready exprs: %d, stalled: %d\n", |
e855c69d AB |
3949 | VEC_length (expr_t, vec_av_set), stalled); |
3950 | sel_print ("Sorted av set (%d): ", VEC_length (expr_t, vec_av_set)); | |
ac47786e | 3951 | FOR_EACH_VEC_ELT (expr_t, vec_av_set, n, expr) |
e855c69d AB |
3952 | dump_expr (expr); |
3953 | sel_print ("\n"); | |
3954 | } | |
3955 | ||
3956 | *pneed_stall = 0; | |
3957 | return true; | |
3958 | } | |
3959 | ||
3960 | /* Convert a vectored and sorted av set to the ready list that | |
3961 | the rest of the backend wants to see. */ | |
3962 | static void | |
3963 | convert_vec_av_set_to_ready (void) | |
3964 | { | |
3965 | int n; | |
3966 | expr_t expr; | |
3967 | ||
3968 | /* Allocate and fill the ready list from the sorted vector. */ | |
3969 | ready.n_ready = VEC_length (expr_t, vec_av_set); | |
3970 | ready.first = ready.n_ready - 1; | |
b8698a0f | 3971 | |
e855c69d AB |
3972 | gcc_assert (ready.n_ready > 0); |
3973 | ||
3974 | if (ready.n_ready > max_issue_size) | |
3975 | { | |
3976 | max_issue_size = ready.n_ready; | |
3977 | sched_extend_ready_list (ready.n_ready); | |
3978 | } | |
b8698a0f | 3979 | |
ac47786e | 3980 | FOR_EACH_VEC_ELT (expr_t, vec_av_set, n, expr) |
e855c69d AB |
3981 | { |
3982 | vinsn_t vi = EXPR_VINSN (expr); | |
3983 | insn_t insn = VINSN_INSN_RTX (vi); | |
3984 | ||
3985 | ready_try[n] = 0; | |
3986 | ready.vec[n] = insn; | |
3987 | } | |
3988 | } | |
3989 | ||
3990 | /* Initialize ready list from *AV_PTR for the max_issue () call. | |
3991 | If any unrecognizable insn found in *AV_PTR, return it (and skip | |
b8698a0f L |
3992 | max_issue). BND and FENCE are current boundary and fence, |
3993 | respectively. If we need to stall for some cycles before an expr | |
e855c69d AB |
3994 | from *AV_PTR would become available, write this number to *PNEED_STALL. */ |
3995 | static expr_t | |
3996 | fill_ready_list (av_set_t *av_ptr, blist_t bnds, fence_t fence, | |
3997 | int *pneed_stall) | |
3998 | { | |
3999 | expr_t expr; | |
4000 | ||
4001 | /* We do not support multiple boundaries per fence. */ | |
4002 | gcc_assert (BLIST_NEXT (bnds) == NULL); | |
4003 | ||
b8698a0f | 4004 | /* Process expressions required special handling, i.e. pipelined, |
e855c69d AB |
4005 | speculative and recog() < 0 expressions first. */ |
4006 | process_pipelined_exprs (av_ptr); | |
4007 | process_spec_exprs (av_ptr); | |
4008 | ||
4009 | /* A USE could be scheduled immediately. */ | |
4010 | expr = process_use_exprs (av_ptr); | |
4011 | if (expr) | |
4012 | { | |
4013 | *pneed_stall = 0; | |
4014 | return expr; | |
4015 | } | |
4016 | ||
4017 | /* Turn the av set to a vector for sorting. */ | |
4018 | if (! fill_vec_av_set (*av_ptr, bnds, fence, pneed_stall)) | |
4019 | { | |
4020 | ready.n_ready = 0; | |
4021 | return NULL; | |
4022 | } | |
4023 | ||
4024 | /* Build the final ready list. */ | |
4025 | convert_vec_av_set_to_ready (); | |
4026 | return NULL; | |
4027 | } | |
4028 | ||
4029 | /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */ | |
4030 | static bool | |
4031 | sel_dfa_new_cycle (insn_t insn, fence_t fence) | |
4032 | { | |
b8698a0f L |
4033 | int last_scheduled_cycle = FENCE_LAST_SCHEDULED_INSN (fence) |
4034 | ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence)) | |
e855c69d AB |
4035 | : FENCE_CYCLE (fence) - 1; |
4036 | bool res = false; | |
4037 | int sort_p = 0; | |
4038 | ||
4039 | if (!targetm.sched.dfa_new_cycle) | |
4040 | return false; | |
4041 | ||
4042 | memcpy (curr_state, FENCE_STATE (fence), dfa_state_size); | |
4043 | ||
4044 | while (!sort_p && targetm.sched.dfa_new_cycle (sched_dump, sched_verbose, | |
4045 | insn, last_scheduled_cycle, | |
4046 | FENCE_CYCLE (fence), &sort_p)) | |
4047 | { | |
4048 | memcpy (FENCE_STATE (fence), curr_state, dfa_state_size); | |
4049 | advance_one_cycle (fence); | |
4050 | memcpy (curr_state, FENCE_STATE (fence), dfa_state_size); | |
4051 | res = true; | |
4052 | } | |
4053 | ||
4054 | return res; | |
4055 | } | |
4056 | ||
4057 | /* Invoke reorder* target hooks on the ready list. Return the number of insns | |
4058 | we can issue. FENCE is the current fence. */ | |
4059 | static int | |
4060 | invoke_reorder_hooks (fence_t fence) | |
4061 | { | |
4062 | int issue_more; | |
4063 | bool ran_hook = false; | |
4064 | ||
4065 | /* Call the reorder hook at the beginning of the cycle, and call | |
4066 | the reorder2 hook in the middle of the cycle. */ | |
4067 | if (FENCE_ISSUED_INSNS (fence) == 0) | |
4068 | { | |
4069 | if (targetm.sched.reorder | |
4070 | && !SCHED_GROUP_P (ready_element (&ready, 0)) | |
4071 | && ready.n_ready > 1) | |
4072 | { | |
4073 | /* Don't give reorder the most prioritized insn as it can break | |
4074 | pipelining. */ | |
4075 | if (pipelining_p) | |
4076 | --ready.n_ready; | |
4077 | ||
4078 | issue_more | |
4079 | = targetm.sched.reorder (sched_dump, sched_verbose, | |
4080 | ready_lastpos (&ready), | |
4081 | &ready.n_ready, FENCE_CYCLE (fence)); | |
4082 | ||
4083 | if (pipelining_p) | |
4084 | ++ready.n_ready; | |
4085 | ||
4086 | ran_hook = true; | |
4087 | } | |
4088 | else | |
4089 | /* Initialize can_issue_more for variable_issue. */ | |
4090 | issue_more = issue_rate; | |
4091 | } | |
4092 | else if (targetm.sched.reorder2 | |
4093 | && !SCHED_GROUP_P (ready_element (&ready, 0))) | |
4094 | { | |
4095 | if (ready.n_ready == 1) | |
b8698a0f | 4096 | issue_more = |
e855c69d AB |
4097 | targetm.sched.reorder2 (sched_dump, sched_verbose, |
4098 | ready_lastpos (&ready), | |
4099 | &ready.n_ready, FENCE_CYCLE (fence)); | |
4100 | else | |
4101 | { | |
4102 | if (pipelining_p) | |
4103 | --ready.n_ready; | |
4104 | ||
4105 | issue_more = | |
4106 | targetm.sched.reorder2 (sched_dump, sched_verbose, | |
4107 | ready.n_ready | |
4108 | ? ready_lastpos (&ready) : NULL, | |
4109 | &ready.n_ready, FENCE_CYCLE (fence)); | |
4110 | ||
4111 | if (pipelining_p) | |
4112 | ++ready.n_ready; | |
4113 | } | |
4114 | ||
4115 | ran_hook = true; | |
4116 | } | |
b8698a0f | 4117 | else |
136e01a3 | 4118 | issue_more = FENCE_ISSUE_MORE (fence); |
e855c69d AB |
4119 | |
4120 | /* Ensure that ready list and vec_av_set are in line with each other, | |
4121 | i.e. vec_av_set[i] == ready_element (&ready, i). */ | |
4122 | if (issue_more && ran_hook) | |
4123 | { | |
4124 | int i, j, n; | |
4125 | rtx *arr = ready.vec; | |
4126 | expr_t *vec = VEC_address (expr_t, vec_av_set); | |
4127 | ||
4128 | for (i = 0, n = ready.n_ready; i < n; i++) | |
4129 | if (EXPR_INSN_RTX (vec[i]) != arr[i]) | |
4130 | { | |
4131 | expr_t tmp; | |
4132 | ||
4133 | for (j = i; j < n; j++) | |
4134 | if (EXPR_INSN_RTX (vec[j]) == arr[i]) | |
4135 | break; | |
4136 | gcc_assert (j < n); | |
4137 | ||
b8698a0f | 4138 | tmp = vec[i]; |
e855c69d AB |
4139 | vec[i] = vec[j]; |
4140 | vec[j] = tmp; | |
4141 | } | |
4142 | } | |
4143 | ||
4144 | return issue_more; | |
4145 | } | |
4146 | ||
b8698a0f L |
4147 | /* Return an EXPR correponding to INDEX element of ready list, if |
4148 | FOLLOW_READY_ELEMENT is true (i.e., an expr of | |
4149 | ready_element (&ready, INDEX) will be returned), and to INDEX element of | |
e855c69d AB |
4150 | ready.vec otherwise. */ |
4151 | static inline expr_t | |
4152 | find_expr_for_ready (int index, bool follow_ready_element) | |
4153 | { | |
4154 | expr_t expr; | |
4155 | int real_index; | |
4156 | ||
4157 | real_index = follow_ready_element ? ready.first - index : index; | |
4158 | ||
4159 | expr = VEC_index (expr_t, vec_av_set, real_index); | |
4160 | gcc_assert (ready.vec[real_index] == EXPR_INSN_RTX (expr)); | |
4161 | ||
4162 | return expr; | |
4163 | } | |
4164 | ||
4165 | /* Calculate insns worth trying via lookahead_guard hook. Return a number | |
4166 | of such insns found. */ | |
4167 | static int | |
4168 | invoke_dfa_lookahead_guard (void) | |
4169 | { | |
4170 | int i, n; | |
b8698a0f | 4171 | bool have_hook |
e855c69d AB |
4172 | = targetm.sched.first_cycle_multipass_dfa_lookahead_guard != NULL; |
4173 | ||
4174 | if (sched_verbose >= 2) | |
4175 | sel_print ("ready after reorder: "); | |
4176 | ||
4177 | for (i = 0, n = 0; i < ready.n_ready; i++) | |
4178 | { | |
4179 | expr_t expr; | |
4180 | insn_t insn; | |
4181 | int r; | |
4182 | ||
b8698a0f | 4183 | /* In this loop insn is Ith element of the ready list given by |
e855c69d AB |
4184 | ready_element, not Ith element of ready.vec. */ |
4185 | insn = ready_element (&ready, i); | |
b8698a0f | 4186 | |
e855c69d AB |
4187 | if (! have_hook || i == 0) |
4188 | r = 0; | |
4189 | else | |
4190 | r = !targetm.sched.first_cycle_multipass_dfa_lookahead_guard (insn); | |
b8698a0f | 4191 | |
e855c69d | 4192 | gcc_assert (INSN_CODE (insn) >= 0); |
b8698a0f L |
4193 | |
4194 | /* Only insns with ready_try = 0 can get here | |
e855c69d AB |
4195 | from fill_ready_list. */ |
4196 | gcc_assert (ready_try [i] == 0); | |
4197 | ready_try[i] = r; | |
4198 | if (!r) | |
4199 | n++; | |
4200 | ||
4201 | expr = find_expr_for_ready (i, true); | |
b8698a0f | 4202 | |
e855c69d AB |
4203 | if (sched_verbose >= 2) |
4204 | { | |
4205 | dump_vinsn (EXPR_VINSN (expr)); | |
4206 | sel_print (":%d; ", ready_try[i]); | |
4207 | } | |
4208 | } | |
4209 | ||
4210 | if (sched_verbose >= 2) | |
4211 | sel_print ("\n"); | |
4212 | return n; | |
4213 | } | |
4214 | ||
4215 | /* Calculate the number of privileged insns and return it. */ | |
4216 | static int | |
4217 | calculate_privileged_insns (void) | |
4218 | { | |
4219 | expr_t cur_expr, min_spec_expr = NULL; | |
e855c69d AB |
4220 | int privileged_n = 0, i; |
4221 | ||
4222 | for (i = 0; i < ready.n_ready; i++) | |
4223 | { | |
4224 | if (ready_try[i]) | |
4225 | continue; | |
4226 | ||
4227 | if (! min_spec_expr) | |
1124098b | 4228 | min_spec_expr = find_expr_for_ready (i, true); |
b8698a0f | 4229 | |
e855c69d AB |
4230 | cur_expr = find_expr_for_ready (i, true); |
4231 | ||
4232 | if (EXPR_SPEC (cur_expr) > EXPR_SPEC (min_spec_expr)) | |
4233 | break; | |
4234 | ||
4235 | ++privileged_n; | |
4236 | } | |
4237 | ||
4238 | if (i == ready.n_ready) | |
4239 | privileged_n = 0; | |
4240 | ||
4241 | if (sched_verbose >= 2) | |
4242 | sel_print ("privileged_n: %d insns with SPEC %d\n", | |
4243 | privileged_n, privileged_n ? EXPR_SPEC (min_spec_expr) : -1); | |
4244 | return privileged_n; | |
4245 | } | |
4246 | ||
b8698a0f | 4247 | /* Call the rest of the hooks after the choice was made. Return |
e855c69d AB |
4248 | the number of insns that still can be issued given that the current |
4249 | number is ISSUE_MORE. FENCE and BEST_INSN are the current fence | |
4250 | and the insn chosen for scheduling, respectively. */ | |
4251 | static int | |
4252 | invoke_aftermath_hooks (fence_t fence, rtx best_insn, int issue_more) | |
4253 | { | |
4254 | gcc_assert (INSN_P (best_insn)); | |
4255 | ||
4256 | /* First, call dfa_new_cycle, and then variable_issue, if available. */ | |
4257 | sel_dfa_new_cycle (best_insn, fence); | |
b8698a0f | 4258 | |
e855c69d AB |
4259 | if (targetm.sched.variable_issue) |
4260 | { | |
4261 | memcpy (curr_state, FENCE_STATE (fence), dfa_state_size); | |
b8698a0f | 4262 | issue_more = |
e855c69d AB |
4263 | targetm.sched.variable_issue (sched_dump, sched_verbose, best_insn, |
4264 | issue_more); | |
4265 | memcpy (FENCE_STATE (fence), curr_state, dfa_state_size); | |
4266 | } | |
4267 | else if (GET_CODE (PATTERN (best_insn)) != USE | |
4268 | && GET_CODE (PATTERN (best_insn)) != CLOBBER) | |
4269 | issue_more--; | |
4270 | ||
4271 | return issue_more; | |
4272 | } | |
4273 | ||
4274 | /* Estimate the cost of issuing INSN on DFA state STATE. */ | |
4275 | static int | |
4276 | estimate_insn_cost (rtx insn, state_t state) | |
4277 | { | |
4278 | static state_t temp = NULL; | |
4279 | int cost; | |
4280 | ||
4281 | if (!temp) | |
4282 | temp = xmalloc (dfa_state_size); | |
4283 | ||
4284 | memcpy (temp, state, dfa_state_size); | |
4285 | cost = state_transition (temp, insn); | |
4286 | ||
4287 | if (cost < 0) | |
4288 | return 0; | |
4289 | else if (cost == 0) | |
4290 | return 1; | |
4291 | return cost; | |
4292 | } | |
4293 | ||
b8698a0f | 4294 | /* Return the cost of issuing EXPR on the FENCE as estimated by DFA. |
e855c69d AB |
4295 | This function properly handles ASMs, USEs etc. */ |
4296 | static int | |
4297 | get_expr_cost (expr_t expr, fence_t fence) | |
4298 | { | |
4299 | rtx insn = EXPR_INSN_RTX (expr); | |
4300 | ||
4301 | if (recog_memoized (insn) < 0) | |
4302 | { | |
b8698a0f | 4303 | if (!FENCE_STARTS_CYCLE_P (fence) |
e855c69d AB |
4304 | && INSN_ASM_P (insn)) |
4305 | /* This is asm insn which is tryed to be issued on the | |
4306 | cycle not first. Issue it on the next cycle. */ | |
4307 | return 1; | |
4308 | else | |
4309 | /* A USE insn, or something else we don't need to | |
4310 | understand. We can't pass these directly to | |
4311 | state_transition because it will trigger a | |
4312 | fatal error for unrecognizable insns. */ | |
4313 | return 0; | |
4314 | } | |
4315 | else | |
4316 | return estimate_insn_cost (insn, FENCE_STATE (fence)); | |
4317 | } | |
4318 | ||
b8698a0f | 4319 | /* Find the best insn for scheduling, either via max_issue or just take |
e855c69d AB |
4320 | the most prioritized available. */ |
4321 | static int | |
4322 | choose_best_insn (fence_t fence, int privileged_n, int *index) | |
4323 | { | |
4324 | int can_issue = 0; | |
4325 | ||
4326 | if (dfa_lookahead > 0) | |
4327 | { | |
4328 | cycle_issued_insns = FENCE_ISSUED_INSNS (fence); | |
894fd6f2 | 4329 | /* TODO: pass equivalent of first_cycle_insn_p to max_issue (). */ |
e855c69d | 4330 | can_issue = max_issue (&ready, privileged_n, |
894fd6f2 | 4331 | FENCE_STATE (fence), true, index); |
e855c69d AB |
4332 | if (sched_verbose >= 2) |
4333 | sel_print ("max_issue: we can issue %d insns, already did %d insns\n", | |
4334 | can_issue, FENCE_ISSUED_INSNS (fence)); | |
4335 | } | |
4336 | else | |
4337 | { | |
4338 | /* We can't use max_issue; just return the first available element. */ | |
4339 | int i; | |
4340 | ||
4341 | for (i = 0; i < ready.n_ready; i++) | |
4342 | { | |
4343 | expr_t expr = find_expr_for_ready (i, true); | |
4344 | ||
4345 | if (get_expr_cost (expr, fence) < 1) | |
4346 | { | |
4347 | can_issue = can_issue_more; | |
4348 | *index = i; | |
4349 | ||
4350 | if (sched_verbose >= 2) | |
4351 | sel_print ("using %dth insn from the ready list\n", i + 1); | |
4352 | ||
4353 | break; | |
4354 | } | |
4355 | } | |
4356 | ||
4357 | if (i == ready.n_ready) | |
4358 | { | |
4359 | can_issue = 0; | |
4360 | *index = -1; | |
4361 | } | |
4362 | } | |
4363 | ||
4364 | return can_issue; | |
4365 | } | |
4366 | ||
b8698a0f L |
4367 | /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it. |
4368 | BNDS and FENCE are current boundaries and scheduling fence respectively. | |
4369 | Return the expr found and NULL if nothing can be issued atm. | |
4370 | Write to PNEED_STALL the number of cycles to stall if no expr was found. */ | |
e855c69d AB |
4371 | static expr_t |
4372 | find_best_expr (av_set_t *av_vliw_ptr, blist_t bnds, fence_t fence, | |
4373 | int *pneed_stall) | |
4374 | { | |
4375 | expr_t best; | |
b8698a0f | 4376 | |
e855c69d AB |
4377 | /* Choose the best insn for scheduling via: |
4378 | 1) sorting the ready list based on priority; | |
4379 | 2) calling the reorder hook; | |
4380 | 3) calling max_issue. */ | |
4381 | best = fill_ready_list (av_vliw_ptr, bnds, fence, pneed_stall); | |
4382 | if (best == NULL && ready.n_ready > 0) | |
4383 | { | |
1124098b | 4384 | int privileged_n, index; |
e855c69d AB |
4385 | |
4386 | can_issue_more = invoke_reorder_hooks (fence); | |
4387 | if (can_issue_more > 0) | |
4388 | { | |
b8698a0f | 4389 | /* Try choosing the best insn until we find one that is could be |
e855c69d AB |
4390 | scheduled due to liveness restrictions on its destination register. |
4391 | In the future, we'd like to choose once and then just probe insns | |
4392 | in the order of their priority. */ | |
1124098b | 4393 | invoke_dfa_lookahead_guard (); |
e855c69d AB |
4394 | privileged_n = calculate_privileged_insns (); |
4395 | can_issue_more = choose_best_insn (fence, privileged_n, &index); | |
4396 | if (can_issue_more) | |
4397 | best = find_expr_for_ready (index, true); | |
4398 | } | |
b8698a0f | 4399 | /* We had some available insns, so if we can't issue them, |
e855c69d AB |
4400 | we have a stall. */ |
4401 | if (can_issue_more == 0) | |
4402 | { | |
4403 | best = NULL; | |
4404 | *pneed_stall = 1; | |
4405 | } | |
4406 | } | |
4407 | ||
4408 | if (best != NULL) | |
4409 | { | |
4410 | can_issue_more = invoke_aftermath_hooks (fence, EXPR_INSN_RTX (best), | |
4411 | can_issue_more); | |
06f0c25f AB |
4412 | if (targetm.sched.variable_issue |
4413 | && can_issue_more == 0) | |
e855c69d AB |
4414 | *pneed_stall = 1; |
4415 | } | |
b8698a0f | 4416 | |
e855c69d AB |
4417 | if (sched_verbose >= 2) |
4418 | { | |
4419 | if (best != NULL) | |
4420 | { | |
4421 | sel_print ("Best expression (vliw form): "); | |
4422 | dump_expr (best); | |
4423 | sel_print ("; cycle %d\n", FENCE_CYCLE (fence)); | |
4424 | } | |
4425 | else | |
4426 | sel_print ("No best expr found!\n"); | |
4427 | } | |
4428 | ||
4429 | return best; | |
4430 | } | |
4431 | \f | |
4432 | ||
4433 | /* Functions that implement the core of the scheduler. */ | |
4434 | ||
4435 | ||
b8698a0f | 4436 | /* Emit an instruction from EXPR with SEQNO and VINSN after |
e855c69d AB |
4437 | PLACE_TO_INSERT. */ |
4438 | static insn_t | |
b8698a0f | 4439 | emit_insn_from_expr_after (expr_t expr, vinsn_t vinsn, int seqno, |
e855c69d AB |
4440 | insn_t place_to_insert) |
4441 | { | |
4442 | /* This assert fails when we have identical instructions | |
4443 | one of which dominates the other. In this case move_op () | |
4444 | finds the first instruction and doesn't search for second one. | |
4445 | The solution would be to compute av_set after the first found | |
4446 | insn and, if insn present in that set, continue searching. | |
4447 | For now we workaround this issue in move_op. */ | |
4448 | gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr))); | |
4449 | ||
4450 | if (EXPR_WAS_RENAMED (expr)) | |
4451 | { | |
4452 | unsigned regno = expr_dest_regno (expr); | |
b8698a0f | 4453 | |
e855c69d AB |
4454 | if (HARD_REGISTER_NUM_P (regno)) |
4455 | { | |
4456 | df_set_regs_ever_live (regno, true); | |
4457 | reg_rename_tick[regno] = ++reg_rename_this_tick; | |
4458 | } | |
4459 | } | |
b8698a0f L |
4460 | |
4461 | return sel_gen_insn_from_expr_after (expr, vinsn, seqno, | |
e855c69d AB |
4462 | place_to_insert); |
4463 | } | |
4464 | ||
4465 | /* Return TRUE if BB can hold bookkeeping code. */ | |
4466 | static bool | |
4467 | block_valid_for_bookkeeping_p (basic_block bb) | |
4468 | { | |
4469 | insn_t bb_end = BB_END (bb); | |
4470 | ||
4471 | if (!in_current_region_p (bb) || EDGE_COUNT (bb->succs) > 1) | |
4472 | return false; | |
4473 | ||
4474 | if (INSN_P (bb_end)) | |
4475 | { | |
4476 | if (INSN_SCHED_TIMES (bb_end) > 0) | |
4477 | return false; | |
4478 | } | |
4479 | else | |
4480 | gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end)); | |
4481 | ||
4482 | return true; | |
4483 | } | |
4484 | ||
4485 | /* Attempt to find a block that can hold bookkeeping code for path(s) incoming | |
4486 | into E2->dest, except from E1->src (there may be a sequence of empty basic | |
4487 | blocks between E1->src and E2->dest). Return found block, or NULL if new | |
b5b8b0ac AO |
4488 | one must be created. If LAX holds, don't assume there is a simple path |
4489 | from E1->src to E2->dest. */ | |
e855c69d | 4490 | static basic_block |
b5b8b0ac | 4491 | find_block_for_bookkeeping (edge e1, edge e2, bool lax) |
e855c69d AB |
4492 | { |
4493 | basic_block candidate_block = NULL; | |
4494 | edge e; | |
4495 | ||
4496 | /* Loop over edges from E1 to E2, inclusive. */ | |
b5b8b0ac | 4497 | for (e = e1; !lax || e->dest != EXIT_BLOCK_PTR; e = EDGE_SUCC (e->dest, 0)) |
e855c69d AB |
4498 | { |
4499 | if (EDGE_COUNT (e->dest->preds) == 2) | |
4500 | { | |
4501 | if (candidate_block == NULL) | |
4502 | candidate_block = (EDGE_PRED (e->dest, 0) == e | |
4503 | ? EDGE_PRED (e->dest, 1)->src | |
4504 | : EDGE_PRED (e->dest, 0)->src); | |
4505 | else | |
4506 | /* Found additional edge leading to path from e1 to e2 | |
4507 | from aside. */ | |
4508 | return NULL; | |
4509 | } | |
4510 | else if (EDGE_COUNT (e->dest->preds) > 2) | |
4511 | /* Several edges leading to path from e1 to e2 from aside. */ | |
4512 | return NULL; | |
4513 | ||
4514 | if (e == e2) | |
b5b8b0ac AO |
4515 | return ((!lax || candidate_block) |
4516 | && block_valid_for_bookkeeping_p (candidate_block) | |
e855c69d AB |
4517 | ? candidate_block |
4518 | : NULL); | |
b5b8b0ac AO |
4519 | |
4520 | if (lax && EDGE_COUNT (e->dest->succs) != 1) | |
4521 | return NULL; | |
e855c69d | 4522 | } |
b5b8b0ac AO |
4523 | |
4524 | if (lax) | |
4525 | return NULL; | |
4526 | ||
e855c69d AB |
4527 | gcc_unreachable (); |
4528 | } | |
4529 | ||
4530 | /* Create new basic block for bookkeeping code for path(s) incoming into | |
4531 | E2->dest, except from E1->src. Return created block. */ | |
4532 | static basic_block | |
4533 | create_block_for_bookkeeping (edge e1, edge e2) | |
4534 | { | |
4535 | basic_block new_bb, bb = e2->dest; | |
4536 | ||
4537 | /* Check that we don't spoil the loop structure. */ | |
4538 | if (current_loop_nest) | |
4539 | { | |
4540 | basic_block latch = current_loop_nest->latch; | |
4541 | ||
4542 | /* We do not split header. */ | |
4543 | gcc_assert (e2->dest != current_loop_nest->header); | |
4544 | ||
4545 | /* We do not redirect the only edge to the latch block. */ | |
4546 | gcc_assert (e1->dest != latch | |
4547 | || !single_pred_p (latch) | |
4548 | || e1 != single_pred_edge (latch)); | |
4549 | } | |
4550 | ||
4551 | /* Split BB to insert BOOK_INSN there. */ | |
4552 | new_bb = sched_split_block (bb, NULL); | |
4553 | ||
4554 | /* Move note_list from the upper bb. */ | |
4555 | gcc_assert (BB_NOTE_LIST (new_bb) == NULL_RTX); | |
4556 | BB_NOTE_LIST (new_bb) = BB_NOTE_LIST (bb); | |
4557 | BB_NOTE_LIST (bb) = NULL_RTX; | |
4558 | ||
4559 | gcc_assert (e2->dest == bb); | |
4560 | ||
4561 | /* Skip block for bookkeeping copy when leaving E1->src. */ | |
4562 | if (e1->flags & EDGE_FALLTHRU) | |
4563 | sel_redirect_edge_and_branch_force (e1, new_bb); | |
4564 | else | |
4565 | sel_redirect_edge_and_branch (e1, new_bb); | |
4566 | ||
4567 | gcc_assert (e1->dest == new_bb); | |
4568 | gcc_assert (sel_bb_empty_p (bb)); | |
4569 | ||
b5b8b0ac AO |
4570 | /* To keep basic block numbers in sync between debug and non-debug |
4571 | compilations, we have to rotate blocks here. Consider that we | |
4572 | started from (a,b)->d, (c,d)->e, and d contained only debug | |
4573 | insns. It would have been removed before if the debug insns | |
4574 | weren't there, so we'd have split e rather than d. So what we do | |
4575 | now is to swap the block numbers of new_bb and | |
4576 | single_succ(new_bb) == e, so that the insns that were in e before | |
4577 | get the new block number. */ | |
4578 | ||
4579 | if (MAY_HAVE_DEBUG_INSNS) | |
4580 | { | |
4581 | basic_block succ; | |
4582 | insn_t insn = sel_bb_head (new_bb); | |
4583 | insn_t last; | |
4584 | ||
4585 | if (DEBUG_INSN_P (insn) | |
4586 | && single_succ_p (new_bb) | |
4587 | && (succ = single_succ (new_bb)) | |
4588 | && succ != EXIT_BLOCK_PTR | |
4589 | && DEBUG_INSN_P ((last = sel_bb_end (new_bb)))) | |
4590 | { | |
4591 | while (insn != last && (DEBUG_INSN_P (insn) || NOTE_P (insn))) | |
4592 | insn = NEXT_INSN (insn); | |
4593 | ||
4594 | if (insn == last) | |
4595 | { | |
4596 | sel_global_bb_info_def gbi; | |
4597 | sel_region_bb_info_def rbi; | |
4598 | int i; | |
4599 | ||
4600 | if (sched_verbose >= 2) | |
4601 | sel_print ("Swapping block ids %i and %i\n", | |
4602 | new_bb->index, succ->index); | |
4603 | ||
4604 | i = new_bb->index; | |
4605 | new_bb->index = succ->index; | |
4606 | succ->index = i; | |
4607 | ||
4608 | SET_BASIC_BLOCK (new_bb->index, new_bb); | |
4609 | SET_BASIC_BLOCK (succ->index, succ); | |
4610 | ||
4611 | memcpy (&gbi, SEL_GLOBAL_BB_INFO (new_bb), sizeof (gbi)); | |
4612 | memcpy (SEL_GLOBAL_BB_INFO (new_bb), SEL_GLOBAL_BB_INFO (succ), | |
4613 | sizeof (gbi)); | |
4614 | memcpy (SEL_GLOBAL_BB_INFO (succ), &gbi, sizeof (gbi)); | |
4615 | ||
4616 | memcpy (&rbi, SEL_REGION_BB_INFO (new_bb), sizeof (rbi)); | |
4617 | memcpy (SEL_REGION_BB_INFO (new_bb), SEL_REGION_BB_INFO (succ), | |
4618 | sizeof (rbi)); | |
4619 | memcpy (SEL_REGION_BB_INFO (succ), &rbi, sizeof (rbi)); | |
4620 | ||
4621 | i = BLOCK_TO_BB (new_bb->index); | |
4622 | BLOCK_TO_BB (new_bb->index) = BLOCK_TO_BB (succ->index); | |
4623 | BLOCK_TO_BB (succ->index) = i; | |
4624 | ||
4625 | i = CONTAINING_RGN (new_bb->index); | |
4626 | CONTAINING_RGN (new_bb->index) = CONTAINING_RGN (succ->index); | |
4627 | CONTAINING_RGN (succ->index) = i; | |
4628 | ||
4629 | for (i = 0; i < current_nr_blocks; i++) | |
4630 | if (BB_TO_BLOCK (i) == succ->index) | |
4631 | BB_TO_BLOCK (i) = new_bb->index; | |
4632 | else if (BB_TO_BLOCK (i) == new_bb->index) | |
4633 | BB_TO_BLOCK (i) = succ->index; | |
4634 | ||
4635 | FOR_BB_INSNS (new_bb, insn) | |
4636 | if (INSN_P (insn)) | |
4637 | EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = new_bb->index; | |
4638 | ||
4639 | FOR_BB_INSNS (succ, insn) | |
4640 | if (INSN_P (insn)) | |
4641 | EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = succ->index; | |
4642 | ||
fcaa4ca4 NF |
4643 | if (bitmap_clear_bit (code_motion_visited_blocks, new_bb->index)) |
4644 | bitmap_set_bit (code_motion_visited_blocks, succ->index); | |
b5b8b0ac AO |
4645 | |
4646 | gcc_assert (LABEL_P (BB_HEAD (new_bb)) | |
4647 | && LABEL_P (BB_HEAD (succ))); | |
4648 | ||
4649 | if (sched_verbose >= 4) | |
4650 | sel_print ("Swapping code labels %i and %i\n", | |
4651 | CODE_LABEL_NUMBER (BB_HEAD (new_bb)), | |
4652 | CODE_LABEL_NUMBER (BB_HEAD (succ))); | |
4653 | ||
4654 | i = CODE_LABEL_NUMBER (BB_HEAD (new_bb)); | |
4655 | CODE_LABEL_NUMBER (BB_HEAD (new_bb)) | |
4656 | = CODE_LABEL_NUMBER (BB_HEAD (succ)); | |
4657 | CODE_LABEL_NUMBER (BB_HEAD (succ)) = i; | |
4658 | } | |
4659 | } | |
4660 | } | |
4661 | ||
e855c69d AB |
4662 | return bb; |
4663 | } | |
4664 | ||
4665 | /* Return insn after which we must insert bookkeeping code for path(s) incoming | |
4666 | into E2->dest, except from E1->src. */ | |
4667 | static insn_t | |
4668 | find_place_for_bookkeeping (edge e1, edge e2) | |
4669 | { | |
4670 | insn_t place_to_insert; | |
4671 | /* Find a basic block that can hold bookkeeping. If it can be found, do not | |
4672 | create new basic block, but insert bookkeeping there. */ | |
b5b8b0ac | 4673 | basic_block book_block = find_block_for_bookkeeping (e1, e2, FALSE); |
e855c69d | 4674 | |
b5b8b0ac AO |
4675 | if (book_block) |
4676 | { | |
4677 | place_to_insert = BB_END (book_block); | |
4678 | ||
4679 | /* Don't use a block containing only debug insns for | |
4680 | bookkeeping, this causes scheduling differences between debug | |
4681 | and non-debug compilations, for the block would have been | |
4682 | removed already. */ | |
4683 | if (DEBUG_INSN_P (place_to_insert)) | |
4684 | { | |
4685 | rtx insn = sel_bb_head (book_block); | |
e855c69d | 4686 | |
b5b8b0ac AO |
4687 | while (insn != place_to_insert && |
4688 | (DEBUG_INSN_P (insn) || NOTE_P (insn))) | |
4689 | insn = NEXT_INSN (insn); | |
4690 | ||
4691 | if (insn == place_to_insert) | |
4692 | book_block = NULL; | |
4693 | } | |
4694 | } | |
4695 | ||
4696 | if (!book_block) | |
4697 | { | |
4698 | book_block = create_block_for_bookkeeping (e1, e2); | |
4699 | place_to_insert = BB_END (book_block); | |
4700 | if (sched_verbose >= 9) | |
4701 | sel_print ("New block is %i, split from bookkeeping block %i\n", | |
4702 | EDGE_SUCC (book_block, 0)->dest->index, book_block->index); | |
4703 | } | |
4704 | else | |
4705 | { | |
4706 | if (sched_verbose >= 9) | |
4707 | sel_print ("Pre-existing bookkeeping block is %i\n", book_block->index); | |
4708 | } | |
e855c69d AB |
4709 | |
4710 | /* If basic block ends with a jump, insert bookkeeping code right before it. */ | |
4711 | if (INSN_P (place_to_insert) && control_flow_insn_p (place_to_insert)) | |
4712 | place_to_insert = PREV_INSN (place_to_insert); | |
4713 | ||
4714 | return place_to_insert; | |
4715 | } | |
4716 | ||
4717 | /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT | |
4718 | for JOIN_POINT. */ | |
4719 | static int | |
4720 | find_seqno_for_bookkeeping (insn_t place_to_insert, insn_t join_point) | |
4721 | { | |
4722 | int seqno; | |
4723 | rtx next; | |
4724 | ||
4725 | /* Check if we are about to insert bookkeeping copy before a jump, and use | |
4726 | jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */ | |
4727 | next = NEXT_INSN (place_to_insert); | |
b8698a0f | 4728 | if (INSN_P (next) |
e855c69d AB |
4729 | && JUMP_P (next) |
4730 | && BLOCK_FOR_INSN (next) == BLOCK_FOR_INSN (place_to_insert)) | |
da7ba240 AB |
4731 | { |
4732 | gcc_assert (INSN_SCHED_TIMES (next) == 0); | |
4733 | seqno = INSN_SEQNO (next); | |
4734 | } | |
e855c69d AB |
4735 | else if (INSN_SEQNO (join_point) > 0) |
4736 | seqno = INSN_SEQNO (join_point); | |
4737 | else | |
da7ba240 AB |
4738 | { |
4739 | seqno = get_seqno_by_preds (place_to_insert); | |
4740 | ||
b8698a0f L |
4741 | /* Sometimes the fences can move in such a way that there will be |
4742 | no instructions with positive seqno around this bookkeeping. | |
da7ba240 AB |
4743 | This means that there will be no way to get to it by a regular |
4744 | fence movement. Never mind because we pick up such pieces for | |
4745 | rescheduling anyways, so any positive value will do for now. */ | |
4746 | if (seqno < 0) | |
4747 | { | |
4748 | gcc_assert (pipelining_p); | |
4749 | seqno = 1; | |
4750 | } | |
4751 | } | |
b8698a0f | 4752 | |
e855c69d AB |
4753 | gcc_assert (seqno > 0); |
4754 | return seqno; | |
4755 | } | |
4756 | ||
4757 | /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning | |
4758 | NEW_SEQNO to it. Return created insn. */ | |
4759 | static insn_t | |
4760 | emit_bookkeeping_insn (insn_t place_to_insert, expr_t c_expr, int new_seqno) | |
4761 | { | |
4762 | rtx new_insn_rtx = create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr)); | |
4763 | ||
4764 | vinsn_t new_vinsn | |
4765 | = create_vinsn_from_insn_rtx (new_insn_rtx, | |
4766 | VINSN_UNIQUE_P (EXPR_VINSN (c_expr))); | |
4767 | ||
4768 | insn_t new_insn = emit_insn_from_expr_after (c_expr, new_vinsn, new_seqno, | |
4769 | place_to_insert); | |
4770 | ||
4771 | INSN_SCHED_TIMES (new_insn) = 0; | |
4772 | bitmap_set_bit (current_copies, INSN_UID (new_insn)); | |
4773 | ||
4774 | return new_insn; | |
4775 | } | |
4776 | ||
4777 | /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to | |
4778 | E2->dest, except from E1->src (there may be a sequence of empty blocks | |
4779 | between E1->src and E2->dest). Return block containing the copy. | |
4780 | All scheduler data is initialized for the newly created insn. */ | |
4781 | static basic_block | |
4782 | generate_bookkeeping_insn (expr_t c_expr, edge e1, edge e2) | |
4783 | { | |
4784 | insn_t join_point, place_to_insert, new_insn; | |
4785 | int new_seqno; | |
4786 | bool need_to_exchange_data_sets; | |
4787 | ||
4788 | if (sched_verbose >= 4) | |
4789 | sel_print ("Generating bookkeeping insn (%d->%d)\n", e1->src->index, | |
4790 | e2->dest->index); | |
4791 | ||
4792 | join_point = sel_bb_head (e2->dest); | |
4793 | place_to_insert = find_place_for_bookkeeping (e1, e2); | |
b5b8b0ac AO |
4794 | if (!place_to_insert) |
4795 | return NULL; | |
e855c69d AB |
4796 | new_seqno = find_seqno_for_bookkeeping (place_to_insert, join_point); |
4797 | need_to_exchange_data_sets | |
4798 | = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert)); | |
4799 | ||
4800 | new_insn = emit_bookkeeping_insn (place_to_insert, c_expr, new_seqno); | |
4801 | ||
4802 | /* When inserting bookkeeping insn in new block, av sets should be | |
4803 | following: old basic block (that now holds bookkeeping) data sets are | |
4804 | the same as was before generation of bookkeeping, and new basic block | |
4805 | (that now hold all other insns of old basic block) data sets are | |
4806 | invalid. So exchange data sets for these basic blocks as sel_split_block | |
4807 | mistakenly exchanges them in this case. Cannot do it earlier because | |
4808 | when single instruction is added to new basic block it should hold NULL | |
4809 | lv_set. */ | |
4810 | if (need_to_exchange_data_sets) | |
4811 | exchange_data_sets (BLOCK_FOR_INSN (new_insn), | |
4812 | BLOCK_FOR_INSN (join_point)); | |
4813 | ||
4814 | stat_bookkeeping_copies++; | |
4815 | return BLOCK_FOR_INSN (new_insn); | |
4816 | } | |
4817 | ||
b8698a0f | 4818 | /* Remove from AV_PTR all insns that may need bookkeeping when scheduling |
e855c69d AB |
4819 | on FENCE, but we are unable to copy them. */ |
4820 | static void | |
4821 | remove_insns_that_need_bookkeeping (fence_t fence, av_set_t *av_ptr) | |
4822 | { | |
4823 | expr_t expr; | |
4824 | av_set_iterator i; | |
4825 | ||
b8698a0f L |
4826 | /* An expression does not need bookkeeping if it is available on all paths |
4827 | from current block to original block and current block dominates | |
4828 | original block. We check availability on all paths by examining | |
4829 | EXPR_SPEC; this is not equivalent, because it may be positive even | |
4830 | if expr is available on all paths (but if expr is not available on | |
e855c69d AB |
4831 | any path, EXPR_SPEC will be positive). */ |
4832 | ||
4833 | FOR_EACH_EXPR_1 (expr, i, av_ptr) | |
4834 | { | |
4835 | if (!control_flow_insn_p (EXPR_INSN_RTX (expr)) | |
4836 | && (!bookkeeping_p || VINSN_UNIQUE_P (EXPR_VINSN (expr))) | |
4837 | && (EXPR_SPEC (expr) | |
4838 | || !EXPR_ORIG_BB_INDEX (expr) | |
4839 | || !dominated_by_p (CDI_DOMINATORS, | |
4840 | BASIC_BLOCK (EXPR_ORIG_BB_INDEX (expr)), | |
4841 | BLOCK_FOR_INSN (FENCE_INSN (fence))))) | |
4842 | { | |
4843 | if (sched_verbose >= 4) | |
4844 | sel_print ("Expr %d removed because it would need bookkeeping, which " | |
4845 | "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr))); | |
4846 | av_set_iter_remove (&i); | |
4847 | } | |
4848 | } | |
4849 | } | |
4850 | ||
4851 | /* Moving conditional jump through some instructions. | |
4852 | ||
4853 | Consider example: | |
4854 | ||
4855 | ... <- current scheduling point | |
4856 | NOTE BASIC BLOCK: <- bb header | |
4857 | (p8) add r14=r14+0x9;; | |
4858 | (p8) mov [r14]=r23 | |
4859 | (!p8) jump L1;; | |
4860 | NOTE BASIC BLOCK: | |
4861 | ... | |
4862 | ||
b8698a0f | 4863 | We can schedule jump one cycle earlier, than mov, because they cannot be |
e855c69d AB |
4864 | executed together as their predicates are mutually exclusive. |
4865 | ||
b8698a0f L |
4866 | This is done in this way: first, new fallthrough basic block is created |
4867 | after jump (it is always can be done, because there already should be a | |
e855c69d | 4868 | fallthrough block, where control flow goes in case of predicate being true - |
b8698a0f L |
4869 | in our example; otherwise there should be a dependence between those |
4870 | instructions and jump and we cannot schedule jump right now); | |
4871 | next, all instructions between jump and current scheduling point are moved | |
e855c69d AB |
4872 | to this new block. And the result is this: |
4873 | ||
4874 | NOTE BASIC BLOCK: | |
4875 | (!p8) jump L1 <- current scheduling point | |
4876 | NOTE BASIC BLOCK: <- bb header | |
4877 | (p8) add r14=r14+0x9;; | |
4878 | (p8) mov [r14]=r23 | |
4879 | NOTE BASIC BLOCK: | |
4880 | ... | |
4881 | */ | |
4882 | static void | |
4883 | move_cond_jump (rtx insn, bnd_t bnd) | |
4884 | { | |
4885 | edge ft_edge; | |
324d3f45 AM |
4886 | basic_block block_from, block_next, block_new, block_bnd, bb; |
4887 | rtx next, prev, link, head; | |
e855c69d | 4888 | |
e855c69d | 4889 | block_from = BLOCK_FOR_INSN (insn); |
324d3f45 AM |
4890 | block_bnd = BLOCK_FOR_INSN (BND_TO (bnd)); |
4891 | prev = BND_TO (bnd); | |
e855c69d | 4892 | |
324d3f45 AM |
4893 | #ifdef ENABLE_CHECKING |
4894 | /* Moving of jump should not cross any other jumps or beginnings of new | |
4895 | basic blocks. The only exception is when we move a jump through | |
4896 | mutually exclusive insns along fallthru edges. */ | |
4897 | if (block_from != block_bnd) | |
4898 | { | |
4899 | bb = block_from; | |
4900 | for (link = PREV_INSN (insn); link != PREV_INSN (prev); | |
4901 | link = PREV_INSN (link)) | |
4902 | { | |
4903 | if (INSN_P (link)) | |
4904 | gcc_assert (sched_insns_conditions_mutex_p (insn, link)); | |
4905 | if (BLOCK_FOR_INSN (link) && BLOCK_FOR_INSN (link) != bb) | |
4906 | { | |
4907 | gcc_assert (single_pred (bb) == BLOCK_FOR_INSN (link)); | |
4908 | bb = BLOCK_FOR_INSN (link); | |
4909 | } | |
4910 | } | |
4911 | } | |
4912 | #endif | |
e855c69d AB |
4913 | |
4914 | /* Jump is moved to the boundary. */ | |
e855c69d AB |
4915 | next = PREV_INSN (insn); |
4916 | BND_TO (bnd) = insn; | |
4917 | ||
0fd4b31d | 4918 | ft_edge = find_fallthru_edge_from (block_from); |
e855c69d AB |
4919 | block_next = ft_edge->dest; |
4920 | /* There must be a fallthrough block (or where should go | |
4921 | control flow in case of false jump predicate otherwise?). */ | |
4922 | gcc_assert (block_next); | |
4923 | ||
4924 | /* Create new empty basic block after source block. */ | |
4925 | block_new = sel_split_edge (ft_edge); | |
4926 | gcc_assert (block_new->next_bb == block_next | |
4927 | && block_from->next_bb == block_new); | |
4928 | ||
324d3f45 AM |
4929 | /* Move all instructions except INSN to BLOCK_NEW. */ |
4930 | bb = block_bnd; | |
4931 | head = BB_HEAD (block_new); | |
4932 | while (bb != block_from->next_bb) | |
e855c69d | 4933 | { |
324d3f45 AM |
4934 | rtx from, to; |
4935 | from = bb == block_bnd ? prev : sel_bb_head (bb); | |
4936 | to = bb == block_from ? next : sel_bb_end (bb); | |
e855c69d | 4937 | |
324d3f45 AM |
4938 | /* The jump being moved can be the first insn in the block. |
4939 | In this case we don't have to move anything in this block. */ | |
4940 | if (NEXT_INSN (to) != from) | |
4941 | { | |
4942 | reorder_insns (from, to, head); | |
4943 | ||
4944 | for (link = to; link != head; link = PREV_INSN (link)) | |
4945 | EXPR_ORIG_BB_INDEX (INSN_EXPR (link)) = block_new->index; | |
4946 | head = to; | |
4947 | } | |
e855c69d | 4948 | |
324d3f45 AM |
4949 | /* Cleanup possibly empty blocks left. */ |
4950 | block_next = bb->next_bb; | |
4951 | if (bb != block_from) | |
65592aad | 4952 | tidy_control_flow (bb, false); |
324d3f45 AM |
4953 | bb = block_next; |
4954 | } | |
e855c69d AB |
4955 | |
4956 | /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */ | |
4957 | gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new))); | |
e855c69d AB |
4958 | |
4959 | gcc_assert (!sel_bb_empty_p (block_from) | |
4960 | && !sel_bb_empty_p (block_new)); | |
4961 | ||
4962 | /* Update data sets for BLOCK_NEW to represent that INSN and | |
4963 | instructions from the other branch of INSN is no longer | |
4964 | available at BLOCK_NEW. */ | |
4965 | BB_AV_LEVEL (block_new) = global_level; | |
4966 | gcc_assert (BB_LV_SET (block_new) == NULL); | |
4967 | BB_LV_SET (block_new) = get_clear_regset_from_pool (); | |
4968 | update_data_sets (sel_bb_head (block_new)); | |
4969 | ||
4970 | /* INSN is a new basic block header - so prepare its data | |
4971 | structures and update availability and liveness sets. */ | |
4972 | update_data_sets (insn); | |
4973 | ||
4974 | if (sched_verbose >= 4) | |
4975 | sel_print ("Moving jump %d\n", INSN_UID (insn)); | |
4976 | } | |
4977 | ||
4978 | /* Remove nops generated during move_op for preventing removal of empty | |
4979 | basic blocks. */ | |
4980 | static void | |
b5b8b0ac | 4981 | remove_temp_moveop_nops (bool full_tidying) |
e855c69d AB |
4982 | { |
4983 | int i; | |
4984 | insn_t insn; | |
b8698a0f | 4985 | |
ac47786e | 4986 | FOR_EACH_VEC_ELT (insn_t, vec_temp_moveop_nops, i, insn) |
e855c69d AB |
4987 | { |
4988 | gcc_assert (INSN_NOP_P (insn)); | |
b5b8b0ac | 4989 | return_nop_to_pool (insn, full_tidying); |
e855c69d AB |
4990 | } |
4991 | ||
4992 | /* Empty the vector. */ | |
4993 | if (VEC_length (insn_t, vec_temp_moveop_nops) > 0) | |
b8698a0f | 4994 | VEC_block_remove (insn_t, vec_temp_moveop_nops, 0, |
e855c69d AB |
4995 | VEC_length (insn_t, vec_temp_moveop_nops)); |
4996 | } | |
4997 | ||
4998 | /* Records the maximal UID before moving up an instruction. Used for | |
4999 | distinguishing between bookkeeping copies and original insns. */ | |
5000 | static int max_uid_before_move_op = 0; | |
5001 | ||
5002 | /* Remove from AV_VLIW_P all instructions but next when debug counter | |
5003 | tells us so. Next instruction is fetched from BNDS. */ | |
5004 | static void | |
5005 | remove_insns_for_debug (blist_t bnds, av_set_t *av_vliw_p) | |
5006 | { | |
5007 | if (! dbg_cnt (sel_sched_insn_cnt)) | |
5008 | /* Leave only the next insn in av_vliw. */ | |
5009 | { | |
5010 | av_set_iterator av_it; | |
5011 | expr_t expr; | |
5012 | bnd_t bnd = BLIST_BND (bnds); | |
5013 | insn_t next = BND_TO (bnd); | |
5014 | ||
5015 | gcc_assert (BLIST_NEXT (bnds) == NULL); | |
5016 | ||
5017 | FOR_EACH_EXPR_1 (expr, av_it, av_vliw_p) | |
5018 | if (EXPR_INSN_RTX (expr) != next) | |
5019 | av_set_iter_remove (&av_it); | |
5020 | } | |
5021 | } | |
5022 | ||
b8698a0f | 5023 | /* Compute available instructions on BNDS. FENCE is the current fence. Write |
e855c69d AB |
5024 | the computed set to *AV_VLIW_P. */ |
5025 | static void | |
5026 | compute_av_set_on_boundaries (fence_t fence, blist_t bnds, av_set_t *av_vliw_p) | |
5027 | { | |
5028 | if (sched_verbose >= 2) | |
5029 | { | |
5030 | sel_print ("Boundaries: "); | |
5031 | dump_blist (bnds); | |
5032 | sel_print ("\n"); | |
5033 | } | |
5034 | ||
5035 | for (; bnds; bnds = BLIST_NEXT (bnds)) | |
5036 | { | |
5037 | bnd_t bnd = BLIST_BND (bnds); | |
5038 | av_set_t av1_copy; | |
5039 | insn_t bnd_to = BND_TO (bnd); | |
5040 | ||
5041 | /* Rewind BND->TO to the basic block header in case some bookkeeping | |
5042 | instructions were inserted before BND->TO and it needs to be | |
5043 | adjusted. */ | |
5044 | if (sel_bb_head_p (bnd_to)) | |
5045 | gcc_assert (INSN_SCHED_TIMES (bnd_to) == 0); | |
5046 | else | |
5047 | while (INSN_SCHED_TIMES (PREV_INSN (bnd_to)) == 0) | |
5048 | { | |
5049 | bnd_to = PREV_INSN (bnd_to); | |
5050 | if (sel_bb_head_p (bnd_to)) | |
5051 | break; | |
5052 | } | |
5053 | ||
5054 | if (BND_TO (bnd) != bnd_to) | |
5055 | { | |
5056 | gcc_assert (FENCE_INSN (fence) == BND_TO (bnd)); | |
5057 | FENCE_INSN (fence) = bnd_to; | |
5058 | BND_TO (bnd) = bnd_to; | |
5059 | } | |
5060 | ||
5061 | av_set_clear (&BND_AV (bnd)); | |
5062 | BND_AV (bnd) = compute_av_set (BND_TO (bnd), NULL, 0, true); | |
5063 | ||
5064 | av_set_clear (&BND_AV1 (bnd)); | |
5065 | BND_AV1 (bnd) = av_set_copy (BND_AV (bnd)); | |
5066 | ||
5067 | moveup_set_inside_insn_group (&BND_AV1 (bnd), NULL); | |
b8698a0f | 5068 | |
e855c69d AB |
5069 | av1_copy = av_set_copy (BND_AV1 (bnd)); |
5070 | av_set_union_and_clear (av_vliw_p, &av1_copy, NULL); | |
5071 | } | |
5072 | ||
5073 | if (sched_verbose >= 2) | |
5074 | { | |
5075 | sel_print ("Available exprs (vliw form): "); | |
5076 | dump_av_set (*av_vliw_p); | |
5077 | sel_print ("\n"); | |
5078 | } | |
5079 | } | |
5080 | ||
b8698a0f L |
5081 | /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW |
5082 | expression. When FOR_MOVEOP is true, also replace the register of | |
e855c69d AB |
5083 | expressions found with the register from EXPR_VLIW. */ |
5084 | static av_set_t | |
5085 | find_sequential_best_exprs (bnd_t bnd, expr_t expr_vliw, bool for_moveop) | |
5086 | { | |
5087 | av_set_t expr_seq = NULL; | |
5088 | expr_t expr; | |
5089 | av_set_iterator i; | |
b8698a0f | 5090 | |
e855c69d AB |
5091 | FOR_EACH_EXPR (expr, i, BND_AV (bnd)) |
5092 | { | |
5093 | if (equal_after_moveup_path_p (expr, NULL, expr_vliw)) | |
5094 | { | |
5095 | if (for_moveop) | |
5096 | { | |
b8698a0f L |
5097 | /* The sequential expression has the right form to pass |
5098 | to move_op except when renaming happened. Put the | |
e855c69d AB |
5099 | correct register in EXPR then. */ |
5100 | if (EXPR_SEPARABLE_P (expr) && REG_P (EXPR_LHS (expr))) | |
5101 | { | |
5102 | if (expr_dest_regno (expr) != expr_dest_regno (expr_vliw)) | |
5103 | { | |
5104 | replace_dest_with_reg_in_expr (expr, EXPR_LHS (expr_vliw)); | |
5105 | stat_renamed_scheduled++; | |
5106 | } | |
b8698a0f L |
5107 | /* Also put the correct TARGET_AVAILABLE bit on the expr. |
5108 | This is needed when renaming came up with original | |
e855c69d | 5109 | register. */ |
b8698a0f | 5110 | else if (EXPR_TARGET_AVAILABLE (expr) |
e855c69d AB |
5111 | != EXPR_TARGET_AVAILABLE (expr_vliw)) |
5112 | { | |
5113 | gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw) == 1); | |
5114 | EXPR_TARGET_AVAILABLE (expr) = 1; | |
5115 | } | |
5116 | } | |
5117 | if (EXPR_WAS_SUBSTITUTED (expr)) | |
5118 | stat_substitutions_total++; | |
5119 | } | |
5120 | ||
5121 | av_set_add (&expr_seq, expr); | |
b8698a0f L |
5122 | |
5123 | /* With substitution inside insn group, it is possible | |
5124 | that more than one expression in expr_seq will correspond | |
5125 | to expr_vliw. In this case, choose one as the attempt to | |
e855c69d AB |
5126 | move both leads to miscompiles. */ |
5127 | break; | |
5128 | } | |
5129 | } | |
5130 | ||
5131 | if (for_moveop && sched_verbose >= 2) | |
5132 | { | |
5133 | sel_print ("Best expression(s) (sequential form): "); | |
5134 | dump_av_set (expr_seq); | |
5135 | sel_print ("\n"); | |
5136 | } | |
b8698a0f | 5137 | |
e855c69d AB |
5138 | return expr_seq; |
5139 | } | |
5140 | ||
5141 | ||
5142 | /* Move nop to previous block. */ | |
5143 | static void ATTRIBUTE_UNUSED | |
5144 | move_nop_to_previous_block (insn_t nop, basic_block prev_bb) | |
5145 | { | |
5146 | insn_t prev_insn, next_insn, note; | |
5147 | ||
b8698a0f | 5148 | gcc_assert (sel_bb_head_p (nop) |
e855c69d AB |
5149 | && prev_bb == BLOCK_FOR_INSN (nop)->prev_bb); |
5150 | note = bb_note (BLOCK_FOR_INSN (nop)); | |
5151 | prev_insn = sel_bb_end (prev_bb); | |
5152 | next_insn = NEXT_INSN (nop); | |
5153 | gcc_assert (prev_insn != NULL_RTX | |
5154 | && PREV_INSN (note) == prev_insn); | |
5155 | ||
5156 | NEXT_INSN (prev_insn) = nop; | |
5157 | PREV_INSN (nop) = prev_insn; | |
5158 | ||
5159 | PREV_INSN (note) = nop; | |
5160 | NEXT_INSN (note) = next_insn; | |
5161 | ||
5162 | NEXT_INSN (nop) = note; | |
5163 | PREV_INSN (next_insn) = note; | |
5164 | ||
5165 | BB_END (prev_bb) = nop; | |
5166 | BLOCK_FOR_INSN (nop) = prev_bb; | |
5167 | } | |
5168 | ||
5169 | /* Prepare a place to insert the chosen expression on BND. */ | |
5170 | static insn_t | |
5171 | prepare_place_to_insert (bnd_t bnd) | |
5172 | { | |
5173 | insn_t place_to_insert; | |
5174 | ||
5175 | /* Init place_to_insert before calling move_op, as the later | |
5176 | can possibly remove BND_TO (bnd). */ | |
5177 | if (/* If this is not the first insn scheduled. */ | |
5178 | BND_PTR (bnd)) | |
5179 | { | |
5180 | /* Add it after last scheduled. */ | |
5181 | place_to_insert = ILIST_INSN (BND_PTR (bnd)); | |
b5b8b0ac AO |
5182 | if (DEBUG_INSN_P (place_to_insert)) |
5183 | { | |
5184 | ilist_t l = BND_PTR (bnd); | |
5185 | while ((l = ILIST_NEXT (l)) && | |
5186 | DEBUG_INSN_P (ILIST_INSN (l))) | |
5187 | ; | |
5188 | if (!l) | |
5189 | place_to_insert = NULL; | |
5190 | } | |
e855c69d AB |
5191 | } |
5192 | else | |
b5b8b0ac AO |
5193 | place_to_insert = NULL; |
5194 | ||
5195 | if (!place_to_insert) | |
e855c69d AB |
5196 | { |
5197 | /* Add it before BND_TO. The difference is in the | |
5198 | basic block, where INSN will be added. */ | |
5199 | place_to_insert = get_nop_from_pool (BND_TO (bnd)); | |
5200 | gcc_assert (BLOCK_FOR_INSN (place_to_insert) | |
5201 | == BLOCK_FOR_INSN (BND_TO (bnd))); | |
5202 | } | |
5203 | ||
5204 | return place_to_insert; | |
5205 | } | |
5206 | ||
b8698a0f | 5207 | /* Find original instructions for EXPR_SEQ and move it to BND boundary. |
e855c69d | 5208 | Return the expression to emit in C_EXPR. */ |
72a54528 | 5209 | static bool |
b8698a0f | 5210 | move_exprs_to_boundary (bnd_t bnd, expr_t expr_vliw, |
e855c69d AB |
5211 | av_set_t expr_seq, expr_t c_expr) |
5212 | { | |
72a54528 | 5213 | bool b, should_move; |
e855c69d AB |
5214 | unsigned book_uid; |
5215 | bitmap_iterator bi; | |
5216 | int n_bookkeeping_copies_before_moveop; | |
5217 | ||
5218 | /* Make a move. This call will remove the original operation, | |
5219 | insert all necessary bookkeeping instructions and update the | |
5220 | data sets. After that all we have to do is add the operation | |
5221 | at before BND_TO (BND). */ | |
5222 | n_bookkeeping_copies_before_moveop = stat_bookkeeping_copies; | |
5223 | max_uid_before_move_op = get_max_uid (); | |
5224 | bitmap_clear (current_copies); | |
5225 | bitmap_clear (current_originators); | |
5226 | ||
b8698a0f | 5227 | b = move_op (BND_TO (bnd), expr_seq, expr_vliw, |
72a54528 | 5228 | get_dest_from_orig_ops (expr_seq), c_expr, &should_move); |
e855c69d | 5229 | |
b8698a0f | 5230 | /* We should be able to find the expression we've chosen for |
e855c69d | 5231 | scheduling. */ |
72a54528 | 5232 | gcc_assert (b); |
b8698a0f | 5233 | |
e855c69d AB |
5234 | if (stat_bookkeeping_copies > n_bookkeeping_copies_before_moveop) |
5235 | stat_insns_needed_bookkeeping++; | |
b8698a0f | 5236 | |
e855c69d AB |
5237 | EXECUTE_IF_SET_IN_BITMAP (current_copies, 0, book_uid, bi) |
5238 | { | |
14f30b87 AM |
5239 | unsigned uid; |
5240 | bitmap_iterator bi; | |
5241 | ||
e855c69d AB |
5242 | /* We allocate these bitmaps lazily. */ |
5243 | if (! INSN_ORIGINATORS_BY_UID (book_uid)) | |
5244 | INSN_ORIGINATORS_BY_UID (book_uid) = BITMAP_ALLOC (NULL); | |
b8698a0f L |
5245 | |
5246 | bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid), | |
e855c69d | 5247 | current_originators); |
14f30b87 AM |
5248 | |
5249 | /* Transitively add all originators' originators. */ | |
5250 | EXECUTE_IF_SET_IN_BITMAP (current_originators, 0, uid, bi) | |
5251 | if (INSN_ORIGINATORS_BY_UID (uid)) | |
5252 | bitmap_ior_into (INSN_ORIGINATORS_BY_UID (book_uid), | |
5253 | INSN_ORIGINATORS_BY_UID (uid)); | |
e855c69d | 5254 | } |
72a54528 AM |
5255 | |
5256 | return should_move; | |
e855c69d AB |
5257 | } |
5258 | ||
5259 | ||
5260 | /* Debug a DFA state as an array of bytes. */ | |
5261 | static void | |
5262 | debug_state (state_t state) | |
5263 | { | |
5264 | unsigned char *p; | |
5265 | unsigned int i, size = dfa_state_size; | |
5266 | ||
5267 | sel_print ("state (%u):", size); | |
5268 | for (i = 0, p = (unsigned char *) state; i < size; i++) | |
5269 | sel_print (" %d", p[i]); | |
5270 | sel_print ("\n"); | |
5271 | } | |
5272 | ||
b8698a0f | 5273 | /* Advance state on FENCE with INSN. Return true if INSN is |
e855c69d AB |
5274 | an ASM, and we should advance state once more. */ |
5275 | static bool | |
5276 | advance_state_on_fence (fence_t fence, insn_t insn) | |
5277 | { | |
5278 | bool asm_p; | |
5279 | ||
5280 | if (recog_memoized (insn) >= 0) | |
5281 | { | |
5282 | int res; | |
5283 | state_t temp_state = alloca (dfa_state_size); | |
b8698a0f | 5284 | |
e855c69d AB |
5285 | gcc_assert (!INSN_ASM_P (insn)); |
5286 | asm_p = false; | |
5287 | ||
5288 | memcpy (temp_state, FENCE_STATE (fence), dfa_state_size); | |
5289 | res = state_transition (FENCE_STATE (fence), insn); | |
5290 | gcc_assert (res < 0); | |
5291 | ||
5292 | if (memcmp (temp_state, FENCE_STATE (fence), dfa_state_size)) | |
5293 | { | |
5294 | FENCE_ISSUED_INSNS (fence)++; | |
5295 | ||
5296 | /* We should never issue more than issue_rate insns. */ | |
5297 | if (FENCE_ISSUED_INSNS (fence) > issue_rate) | |
5298 | gcc_unreachable (); | |
5299 | } | |
b8698a0f | 5300 | } |
e855c69d AB |
5301 | else |
5302 | { | |
b8698a0f | 5303 | /* This could be an ASM insn which we'd like to schedule |
e855c69d AB |
5304 | on the next cycle. */ |
5305 | asm_p = INSN_ASM_P (insn); | |
5306 | if (!FENCE_STARTS_CYCLE_P (fence) && asm_p) | |
5307 | advance_one_cycle (fence); | |
5308 | } | |
5309 | ||
5310 | if (sched_verbose >= 2) | |
5311 | debug_state (FENCE_STATE (fence)); | |
b5b8b0ac AO |
5312 | if (!DEBUG_INSN_P (insn)) |
5313 | FENCE_STARTS_CYCLE_P (fence) = 0; | |
136e01a3 | 5314 | FENCE_ISSUE_MORE (fence) = can_issue_more; |
e855c69d AB |
5315 | return asm_p; |
5316 | } | |
5317 | ||
5318 | /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL | |
5319 | is nonzero if we need to stall after issuing INSN. */ | |
5320 | static void | |
5321 | update_fence_and_insn (fence_t fence, insn_t insn, int need_stall) | |
5322 | { | |
5323 | bool asm_p; | |
b8698a0f | 5324 | |
e855c69d AB |
5325 | /* First, reflect that something is scheduled on this fence. */ |
5326 | asm_p = advance_state_on_fence (fence, insn); | |
5327 | FENCE_LAST_SCHEDULED_INSN (fence) = insn; | |
5328 | VEC_safe_push (rtx, gc, FENCE_EXECUTING_INSNS (fence), insn); | |
5329 | if (SCHED_GROUP_P (insn)) | |
5330 | { | |
5331 | FENCE_SCHED_NEXT (fence) = INSN_SCHED_NEXT (insn); | |
5332 | SCHED_GROUP_P (insn) = 0; | |
5333 | } | |
5334 | else | |
5335 | FENCE_SCHED_NEXT (fence) = NULL_RTX; | |
5336 | if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence)) | |
5337 | FENCE_READY_TICKS (fence) [INSN_UID (insn)] = 0; | |
5338 | ||
5339 | /* Set instruction scheduling info. This will be used in bundling, | |
5340 | pipelining, tick computations etc. */ | |
5341 | ++INSN_SCHED_TIMES (insn); | |
5342 | EXPR_TARGET_AVAILABLE (INSN_EXPR (insn)) = true; | |
5343 | EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn)) = FENCE_CYCLE (fence); | |
5344 | INSN_AFTER_STALL_P (insn) = FENCE_AFTER_STALL_P (fence); | |
5345 | INSN_SCHED_CYCLE (insn) = FENCE_CYCLE (fence); | |
5346 | ||
5347 | /* This does not account for adjust_cost hooks, just add the biggest | |
b8698a0f | 5348 | constant the hook may add to the latency. TODO: make this |
e855c69d | 5349 | a target dependent constant. */ |
b8698a0f L |
5350 | INSN_READY_CYCLE (insn) |
5351 | = INSN_SCHED_CYCLE (insn) + (INSN_CODE (insn) < 0 | |
e855c69d AB |
5352 | ? 1 |
5353 | : maximal_insn_latency (insn) + 1); | |
5354 | ||
5355 | /* Change these fields last, as they're used above. */ | |
5356 | FENCE_AFTER_STALL_P (fence) = 0; | |
5357 | if (asm_p || need_stall) | |
5358 | advance_one_cycle (fence); | |
b8698a0f | 5359 | |
e855c69d AB |
5360 | /* Indicate that we've scheduled something on this fence. */ |
5361 | FENCE_SCHEDULED_P (fence) = true; | |
5362 | scheduled_something_on_previous_fence = true; | |
5363 | ||
5364 | /* Print debug information when insn's fields are updated. */ | |
5365 | if (sched_verbose >= 2) | |
5366 | { | |
5367 | sel_print ("Scheduling insn: "); | |
5368 | dump_insn_1 (insn, 1); | |
5369 | sel_print ("\n"); | |
5370 | } | |
5371 | } | |
5372 | ||
b5b8b0ac AO |
5373 | /* Update boundary BND (and, if needed, FENCE) with INSN, remove the |
5374 | old boundary from BNDSP, add new boundaries to BNDS_TAIL_P and | |
5375 | return it. */ | |
e855c69d | 5376 | static blist_t * |
b5b8b0ac | 5377 | update_boundaries (fence_t fence, bnd_t bnd, insn_t insn, blist_t *bndsp, |
e855c69d AB |
5378 | blist_t *bnds_tailp) |
5379 | { | |
5380 | succ_iterator si; | |
5381 | insn_t succ; | |
5382 | ||
5383 | advance_deps_context (BND_DC (bnd), insn); | |
b8698a0f | 5384 | FOR_EACH_SUCC_1 (succ, si, insn, |
e855c69d AB |
5385 | SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS) |
5386 | { | |
5387 | ilist_t ptr = ilist_copy (BND_PTR (bnd)); | |
b8698a0f | 5388 | |
e855c69d | 5389 | ilist_add (&ptr, insn); |
b5b8b0ac AO |
5390 | |
5391 | if (DEBUG_INSN_P (insn) && sel_bb_end_p (insn) | |
5392 | && is_ineligible_successor (succ, ptr)) | |
5393 | { | |
5394 | ilist_clear (&ptr); | |
5395 | continue; | |
5396 | } | |
5397 | ||
5398 | if (FENCE_INSN (fence) == insn && !sel_bb_end_p (insn)) | |
5399 | { | |
5400 | if (sched_verbose >= 9) | |
5401 | sel_print ("Updating fence insn from %i to %i\n", | |
5402 | INSN_UID (insn), INSN_UID (succ)); | |
5403 | FENCE_INSN (fence) = succ; | |
5404 | } | |
e855c69d AB |
5405 | blist_add (bnds_tailp, succ, ptr, BND_DC (bnd)); |
5406 | bnds_tailp = &BLIST_NEXT (*bnds_tailp); | |
5407 | } | |
b8698a0f | 5408 | |
e855c69d AB |
5409 | blist_remove (bndsp); |
5410 | return bnds_tailp; | |
5411 | } | |
5412 | ||
5413 | /* Schedule EXPR_VLIW on BND. Return the insn emitted. */ | |
5414 | static insn_t | |
5415 | schedule_expr_on_boundary (bnd_t bnd, expr_t expr_vliw, int seqno) | |
5416 | { | |
5417 | av_set_t expr_seq; | |
5418 | expr_t c_expr = XALLOCA (expr_def); | |
5419 | insn_t place_to_insert; | |
5420 | insn_t insn; | |
72a54528 | 5421 | bool should_move; |
e855c69d AB |
5422 | |
5423 | expr_seq = find_sequential_best_exprs (bnd, expr_vliw, true); | |
5424 | ||
5425 | /* In case of scheduling a jump skipping some other instructions, | |
b8698a0f | 5426 | prepare CFG. After this, jump is at the boundary and can be |
e855c69d AB |
5427 | scheduled as usual insn by MOVE_OP. */ |
5428 | if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw))) | |
5429 | { | |
5430 | insn = EXPR_INSN_RTX (expr_vliw); | |
b8698a0f | 5431 | |
e855c69d | 5432 | /* Speculative jumps are not handled. */ |
b8698a0f | 5433 | if (insn != BND_TO (bnd) |
e855c69d AB |
5434 | && !sel_insn_is_speculation_check (insn)) |
5435 | move_cond_jump (insn, bnd); | |
5436 | } | |
5437 | ||
e855c69d AB |
5438 | /* Find a place for C_EXPR to schedule. */ |
5439 | place_to_insert = prepare_place_to_insert (bnd); | |
72a54528 | 5440 | should_move = move_exprs_to_boundary (bnd, expr_vliw, expr_seq, c_expr); |
e855c69d | 5441 | clear_expr (c_expr); |
b8698a0f L |
5442 | |
5443 | /* Add the instruction. The corner case to care about is when | |
5444 | the expr_seq set has more than one expr, and we chose the one that | |
5445 | is not equal to expr_vliw. Then expr_vliw may be insn in stream, and | |
e855c69d AB |
5446 | we can't use it. Generate the new vinsn. */ |
5447 | if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw))) | |
5448 | { | |
5449 | vinsn_t vinsn_new; | |
b8698a0f | 5450 | |
e855c69d AB |
5451 | vinsn_new = vinsn_copy (EXPR_VINSN (expr_vliw), false); |
5452 | change_vinsn_in_expr (expr_vliw, vinsn_new); | |
72a54528 | 5453 | should_move = false; |
e855c69d | 5454 | } |
72a54528 AM |
5455 | if (should_move) |
5456 | insn = sel_move_insn (expr_vliw, seqno, place_to_insert); | |
5457 | else | |
b8698a0f | 5458 | insn = emit_insn_from_expr_after (expr_vliw, NULL, seqno, |
e855c69d | 5459 | place_to_insert); |
e855c69d AB |
5460 | |
5461 | /* Return the nops generated for preserving of data sets back | |
5462 | into pool. */ | |
5463 | if (INSN_NOP_P (place_to_insert)) | |
b5b8b0ac AO |
5464 | return_nop_to_pool (place_to_insert, !DEBUG_INSN_P (insn)); |
5465 | remove_temp_moveop_nops (!DEBUG_INSN_P (insn)); | |
e855c69d AB |
5466 | |
5467 | av_set_clear (&expr_seq); | |
b8698a0f L |
5468 | |
5469 | /* Save the expression scheduled so to reset target availability if we'll | |
e855c69d AB |
5470 | meet it later on the same fence. */ |
5471 | if (EXPR_WAS_RENAMED (expr_vliw)) | |
5472 | vinsn_vec_add (&vec_target_unavailable_vinsns, INSN_EXPR (insn)); | |
5473 | ||
5474 | /* Check that the recent movement didn't destroyed loop | |
5475 | structure. */ | |
5476 | gcc_assert (!pipelining_p | |
5477 | || current_loop_nest == NULL | |
5478 | || loop_latch_edge (current_loop_nest)); | |
5479 | return insn; | |
5480 | } | |
5481 | ||
5482 | /* Stall for N cycles on FENCE. */ | |
5483 | static void | |
5484 | stall_for_cycles (fence_t fence, int n) | |
5485 | { | |
5486 | int could_more; | |
b8698a0f | 5487 | |
e855c69d AB |
5488 | could_more = n > 1 || FENCE_ISSUED_INSNS (fence) < issue_rate; |
5489 | while (n--) | |
5490 | advance_one_cycle (fence); | |
5491 | if (could_more) | |
5492 | FENCE_AFTER_STALL_P (fence) = 1; | |
5493 | } | |
5494 | ||
b8698a0f L |
5495 | /* Gather a parallel group of insns at FENCE and assign their seqno |
5496 | to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP | |
e855c69d AB |
5497 | list for later recalculation of seqnos. */ |
5498 | static void | |
5499 | fill_insns (fence_t fence, int seqno, ilist_t **scheduled_insns_tailpp) | |
5500 | { | |
5501 | blist_t bnds = NULL, *bnds_tailp; | |
5502 | av_set_t av_vliw = NULL; | |
5503 | insn_t insn = FENCE_INSN (fence); | |
5504 | ||
5505 | if (sched_verbose >= 2) | |
b8698a0f | 5506 | sel_print ("Starting fill_insns for insn %d, cycle %d\n", |
e855c69d AB |
5507 | INSN_UID (insn), FENCE_CYCLE (fence)); |
5508 | ||
5509 | blist_add (&bnds, insn, NULL, FENCE_DC (fence)); | |
5510 | bnds_tailp = &BLIST_NEXT (bnds); | |
5511 | set_target_context (FENCE_TC (fence)); | |
136e01a3 | 5512 | can_issue_more = FENCE_ISSUE_MORE (fence); |
e855c69d AB |
5513 | target_bb = INSN_BB (insn); |
5514 | ||
5515 | /* Do while we can add any operation to the current group. */ | |
5516 | do | |
5517 | { | |
5518 | blist_t *bnds_tailp1, *bndsp; | |
5519 | expr_t expr_vliw; | |
5520 | int need_stall; | |
06f0c25f | 5521 | int was_stall = 0, scheduled_insns = 0; |
e855c69d AB |
5522 | int max_insns = pipelining_p ? issue_rate : 2 * issue_rate; |
5523 | int max_stall = pipelining_p ? 1 : 3; | |
b5b8b0ac AO |
5524 | bool last_insn_was_debug = false; |
5525 | bool was_debug_bb_end_p = false; | |
5526 | ||
e855c69d AB |
5527 | compute_av_set_on_boundaries (fence, bnds, &av_vliw); |
5528 | remove_insns_that_need_bookkeeping (fence, &av_vliw); | |
5529 | remove_insns_for_debug (bnds, &av_vliw); | |
5530 | ||
5531 | /* Return early if we have nothing to schedule. */ | |
5532 | if (av_vliw == NULL) | |
5533 | break; | |
5534 | ||
5535 | /* Choose the best expression and, if needed, destination register | |
5536 | for it. */ | |
5537 | do | |
5538 | { | |
5539 | expr_vliw = find_best_expr (&av_vliw, bnds, fence, &need_stall); | |
06f0c25f | 5540 | if (! expr_vliw && need_stall) |
e855c69d AB |
5541 | { |
5542 | /* All expressions required a stall. Do not recompute av sets | |
5543 | as we'll get the same answer (modulo the insns between | |
5544 | the fence and its boundary, which will not be available for | |
06f0c25f AB |
5545 | pipelining). |
5546 | If we are going to stall for too long, break to recompute av | |
e855c69d | 5547 | sets and bring more insns for pipelining. */ |
06f0c25f | 5548 | was_stall++; |
e855c69d AB |
5549 | if (need_stall <= 3) |
5550 | stall_for_cycles (fence, need_stall); | |
5551 | else | |
5552 | { | |
5553 | stall_for_cycles (fence, 1); | |
5554 | break; | |
5555 | } | |
5556 | } | |
5557 | } | |
5558 | while (! expr_vliw && need_stall); | |
b8698a0f | 5559 | |
e855c69d AB |
5560 | /* Now either we've selected expr_vliw or we have nothing to schedule. */ |
5561 | if (!expr_vliw) | |
5562 | { | |
5563 | av_set_clear (&av_vliw); | |
5564 | break; | |
5565 | } | |
5566 | ||
5567 | bndsp = &bnds; | |
5568 | bnds_tailp1 = bnds_tailp; | |
5569 | ||
5570 | do | |
b8698a0f | 5571 | /* This code will be executed only once until we'd have several |
e855c69d AB |
5572 | boundaries per fence. */ |
5573 | { | |
5574 | bnd_t bnd = BLIST_BND (*bndsp); | |
5575 | ||
5576 | if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr_vliw))) | |
5577 | { | |
5578 | bndsp = &BLIST_NEXT (*bndsp); | |
5579 | continue; | |
5580 | } | |
b8698a0f | 5581 | |
e855c69d | 5582 | insn = schedule_expr_on_boundary (bnd, expr_vliw, seqno); |
b5b8b0ac AO |
5583 | last_insn_was_debug = DEBUG_INSN_P (insn); |
5584 | if (last_insn_was_debug) | |
5585 | was_debug_bb_end_p = (insn == BND_TO (bnd) && sel_bb_end_p (insn)); | |
e855c69d | 5586 | update_fence_and_insn (fence, insn, need_stall); |
b5b8b0ac | 5587 | bnds_tailp = update_boundaries (fence, bnd, insn, bndsp, bnds_tailp); |
e855c69d AB |
5588 | |
5589 | /* Add insn to the list of scheduled on this cycle instructions. */ | |
5590 | ilist_add (*scheduled_insns_tailpp, insn); | |
5591 | *scheduled_insns_tailpp = &ILIST_NEXT (**scheduled_insns_tailpp); | |
5592 | } | |
5593 | while (*bndsp != *bnds_tailp1); | |
5594 | ||
5595 | av_set_clear (&av_vliw); | |
b5b8b0ac AO |
5596 | if (!last_insn_was_debug) |
5597 | scheduled_insns++; | |
e855c69d AB |
5598 | |
5599 | /* We currently support information about candidate blocks only for | |
5600 | one 'target_bb' block. Hence we can't schedule after jump insn, | |
5601 | as this will bring two boundaries and, hence, necessity to handle | |
5602 | information for two or more blocks concurrently. */ | |
b5b8b0ac | 5603 | if ((last_insn_was_debug ? was_debug_bb_end_p : sel_bb_end_p (insn)) |
b8698a0f L |
5604 | || (was_stall |
5605 | && (was_stall >= max_stall | |
e855c69d AB |
5606 | || scheduled_insns >= max_insns))) |
5607 | break; | |
5608 | } | |
5609 | while (bnds); | |
5610 | ||
5611 | gcc_assert (!FENCE_BNDS (fence)); | |
b8698a0f | 5612 | |
e855c69d AB |
5613 | /* Update boundaries of the FENCE. */ |
5614 | while (bnds) | |
5615 | { | |
5616 | ilist_t ptr = BND_PTR (BLIST_BND (bnds)); | |
5617 | ||
5618 | if (ptr) | |
5619 | { | |
5620 | insn = ILIST_INSN (ptr); | |
5621 | ||
5622 | if (!ilist_is_in_p (FENCE_BNDS (fence), insn)) | |
5623 | ilist_add (&FENCE_BNDS (fence), insn); | |
5624 | } | |
b8698a0f | 5625 | |
e855c69d AB |
5626 | blist_remove (&bnds); |
5627 | } | |
5628 | ||
5629 | /* Update target context on the fence. */ | |
5630 | reset_target_context (FENCE_TC (fence), false); | |
5631 | } | |
5632 | ||
5633 | /* All exprs in ORIG_OPS must have the same destination register or memory. | |
5634 | Return that destination. */ | |
5635 | static rtx | |
5636 | get_dest_from_orig_ops (av_set_t orig_ops) | |
5637 | { | |
5638 | rtx dest = NULL_RTX; | |
5639 | av_set_iterator av_it; | |
5640 | expr_t expr; | |
5641 | bool first_p = true; | |
5642 | ||
5643 | FOR_EACH_EXPR (expr, av_it, orig_ops) | |
5644 | { | |
5645 | rtx x = EXPR_LHS (expr); | |
5646 | ||
5647 | if (first_p) | |
5648 | { | |
5649 | first_p = false; | |
5650 | dest = x; | |
5651 | } | |
5652 | else | |
5653 | gcc_assert (dest == x | |
5654 | || (dest != NULL_RTX && x != NULL_RTX | |
5655 | && rtx_equal_p (dest, x))); | |
5656 | } | |
5657 | ||
5658 | return dest; | |
5659 | } | |
5660 | ||
5661 | /* Update data sets for the bookkeeping block and record those expressions | |
5662 | which become no longer available after inserting this bookkeeping. */ | |
5663 | static void | |
5664 | update_and_record_unavailable_insns (basic_block book_block) | |
5665 | { | |
5666 | av_set_iterator i; | |
5667 | av_set_t old_av_set = NULL; | |
5668 | expr_t cur_expr; | |
5669 | rtx bb_end = sel_bb_end (book_block); | |
5670 | ||
b8698a0f | 5671 | /* First, get correct liveness in the bookkeeping block. The problem is |
e855c69d AB |
5672 | the range between the bookeeping insn and the end of block. */ |
5673 | update_liveness_on_insn (bb_end); | |
5674 | if (control_flow_insn_p (bb_end)) | |
5675 | update_liveness_on_insn (PREV_INSN (bb_end)); | |
5676 | ||
5677 | /* If there's valid av_set on BOOK_BLOCK, then there might exist another | |
5678 | fence above, where we may choose to schedule an insn which is | |
5679 | actually blocked from moving up with the bookkeeping we create here. */ | |
5680 | if (AV_SET_VALID_P (sel_bb_head (book_block))) | |
5681 | { | |
5682 | old_av_set = av_set_copy (BB_AV_SET (book_block)); | |
5683 | update_data_sets (sel_bb_head (book_block)); | |
b8698a0f | 5684 | |
e855c69d AB |
5685 | /* Traverse all the expressions in the old av_set and check whether |
5686 | CUR_EXPR is in new AV_SET. */ | |
5687 | FOR_EACH_EXPR (cur_expr, i, old_av_set) | |
5688 | { | |
b8698a0f | 5689 | expr_t new_expr = av_set_lookup (BB_AV_SET (book_block), |
e855c69d AB |
5690 | EXPR_VINSN (cur_expr)); |
5691 | ||
b8698a0f L |
5692 | if (! new_expr |
5693 | /* In this case, we can just turn off the E_T_A bit, but we can't | |
e855c69d | 5694 | represent this information with the current vector. */ |
b8698a0f | 5695 | || EXPR_TARGET_AVAILABLE (new_expr) |
e855c69d AB |
5696 | != EXPR_TARGET_AVAILABLE (cur_expr)) |
5697 | /* Unfortunately, the below code could be also fired up on | |
5698 | separable insns. | |
5699 | FIXME: add an example of how this could happen. */ | |
5700 | vinsn_vec_add (&vec_bookkeeping_blocked_vinsns, cur_expr); | |
5701 | } | |
5702 | ||
5703 | av_set_clear (&old_av_set); | |
5704 | } | |
5705 | } | |
5706 | ||
b8698a0f | 5707 | /* The main effect of this function is that sparams->c_expr is merged |
e855c69d AB |
5708 | with (or copied to) lparams->c_expr_merged. If there's only one successor, |
5709 | we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged. | |
b8698a0f L |
5710 | lparams->c_expr_merged is copied back to sparams->c_expr after all |
5711 | successors has been traversed. lparams->c_expr_local is an expr allocated | |
5712 | on stack in the caller function, and is used if there is more than one | |
5713 | successor. | |
e855c69d AB |
5714 | |
5715 | SUCC is one of the SUCCS_NORMAL successors of INSN, | |
5716 | MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ, | |
5717 | LPARAMS and STATIC_PARAMS contain the parameters described above. */ | |
5718 | static void | |
b8698a0f L |
5719 | move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED, |
5720 | insn_t succ ATTRIBUTE_UNUSED, | |
5721 | int moveop_drv_call_res, | |
e855c69d AB |
5722 | cmpd_local_params_p lparams, void *static_params) |
5723 | { | |
5724 | moveop_static_params_p sparams = (moveop_static_params_p) static_params; | |
5725 | ||
5726 | /* Nothing to do, if original expr wasn't found below. */ | |
5727 | if (moveop_drv_call_res != 1) | |
5728 | return; | |
5729 | ||
5730 | /* If this is a first successor. */ | |
5731 | if (!lparams->c_expr_merged) | |
5732 | { | |
5733 | lparams->c_expr_merged = sparams->c_expr; | |
5734 | sparams->c_expr = lparams->c_expr_local; | |
5735 | } | |
5736 | else | |
5737 | { | |
5738 | /* We must merge all found expressions to get reasonable | |
5739 | EXPR_SPEC_DONE_DS for the resulting insn. If we don't | |
5740 | do so then we can first find the expr with epsilon | |
5741 | speculation success probability and only then with the | |
5742 | good probability. As a result the insn will get epsilon | |
5743 | probability and will never be scheduled because of | |
5744 | weakness_cutoff in find_best_expr. | |
5745 | ||
b8698a0f | 5746 | We call merge_expr_data here instead of merge_expr |
e855c69d AB |
5747 | because due to speculation C_EXPR and X may have the |
5748 | same insns with different speculation types. And as of | |
b8698a0f | 5749 | now such insns are considered non-equal. |
e855c69d | 5750 | |
b8698a0f L |
5751 | However, EXPR_SCHED_TIMES is different -- we must get |
5752 | SCHED_TIMES from a real insn, not a bookkeeping copy. | |
e855c69d | 5753 | We force this here. Instead, we may consider merging |
b8698a0f | 5754 | SCHED_TIMES to the maximum instead of minimum in the |
e855c69d AB |
5755 | below function. */ |
5756 | int old_times = EXPR_SCHED_TIMES (lparams->c_expr_merged); | |
5757 | ||
5758 | merge_expr_data (lparams->c_expr_merged, sparams->c_expr, NULL); | |
5759 | if (EXPR_SCHED_TIMES (sparams->c_expr) == 0) | |
5760 | EXPR_SCHED_TIMES (lparams->c_expr_merged) = old_times; | |
5761 | ||
5762 | clear_expr (sparams->c_expr); | |
5763 | } | |
5764 | } | |
5765 | ||
5766 | /* Add used regs for the successor SUCC into SPARAMS->USED_REGS. | |
5767 | ||
5768 | SUCC is one of the SUCCS_NORMAL successors of INSN, | |
5769 | MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0, | |
5770 | if SUCC is one of SUCCS_BACK or SUCCS_OUT. | |
5771 | STATIC_PARAMS contain USED_REGS set. */ | |
5772 | static void | |
b8698a0f L |
5773 | fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED, insn_t succ, |
5774 | int moveop_drv_call_res, | |
5775 | cmpd_local_params_p lparams ATTRIBUTE_UNUSED, | |
e855c69d AB |
5776 | void *static_params) |
5777 | { | |
5778 | regset succ_live; | |
5779 | fur_static_params_p sparams = (fur_static_params_p) static_params; | |
5780 | ||
5781 | /* Here we compute live regsets only for branches that do not lie | |
b8698a0f | 5782 | on the code motion paths. These branches correspond to value |
e855c69d AB |
5783 | MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though |
5784 | for such branches code_motion_path_driver is not called. */ | |
5785 | if (moveop_drv_call_res != 0) | |
5786 | return; | |
5787 | ||
5788 | /* Mark all registers that do not meet the following condition: | |
5789 | (3) not live on the other path of any conditional branch | |
5790 | that is passed by the operation, in case original | |
5791 | operations are not present on both paths of the | |
5792 | conditional branch. */ | |
5793 | succ_live = compute_live (succ); | |
5794 | IOR_REG_SET (sparams->used_regs, succ_live); | |
5795 | } | |
5796 | ||
5797 | /* This function is called after the last successor. Copies LP->C_EXPR_MERGED | |
5798 | into SP->CEXPR. */ | |
5799 | static void | |
5800 | move_op_after_merge_succs (cmpd_local_params_p lp, void *sparams) | |
b8698a0f | 5801 | { |
e855c69d AB |
5802 | moveop_static_params_p sp = (moveop_static_params_p) sparams; |
5803 | ||
5804 | sp->c_expr = lp->c_expr_merged; | |
5805 | } | |
5806 | ||
5807 | /* Track bookkeeping copies created, insns scheduled, and blocks for | |
5808 | rescheduling when INSN is found by move_op. */ | |
5809 | static void | |
5810 | track_scheduled_insns_and_blocks (rtx insn) | |
5811 | { | |
5812 | /* Even if this insn can be a copy that will be removed during current move_op, | |
5813 | we still need to count it as an originator. */ | |
5814 | bitmap_set_bit (current_originators, INSN_UID (insn)); | |
5815 | ||
fcaa4ca4 | 5816 | if (!bitmap_clear_bit (current_copies, INSN_UID (insn))) |
e855c69d AB |
5817 | { |
5818 | /* Note that original block needs to be rescheduled, as we pulled an | |
5819 | instruction out of it. */ | |
5820 | if (INSN_SCHED_TIMES (insn) > 0) | |
5821 | bitmap_set_bit (blocks_to_reschedule, BLOCK_FOR_INSN (insn)->index); | |
b5b8b0ac | 5822 | else if (INSN_UID (insn) < first_emitted_uid && !DEBUG_INSN_P (insn)) |
e855c69d AB |
5823 | num_insns_scheduled++; |
5824 | } | |
e855c69d AB |
5825 | |
5826 | /* For instructions we must immediately remove insn from the | |
5827 | stream, so subsequent update_data_sets () won't include this | |
5828 | insn into av_set. | |
5829 | For expr we must make insn look like "INSN_REG (insn) := c_expr". */ | |
5830 | if (INSN_UID (insn) > max_uid_before_move_op) | |
5831 | stat_bookkeeping_copies--; | |
5832 | } | |
5833 | ||
b8698a0f | 5834 | /* Emit a register-register copy for INSN if needed. Return true if |
e855c69d AB |
5835 | emitted one. PARAMS is the move_op static parameters. */ |
5836 | static bool | |
b8698a0f | 5837 | maybe_emit_renaming_copy (rtx insn, |
e855c69d AB |
5838 | moveop_static_params_p params) |
5839 | { | |
5840 | bool insn_emitted = false; | |
f07013eb | 5841 | rtx cur_reg; |
e855c69d | 5842 | |
f07013eb AM |
5843 | /* Bail out early when expression can not be renamed at all. */ |
5844 | if (!EXPR_SEPARABLE_P (params->c_expr)) | |
5845 | return false; | |
5846 | ||
5847 | cur_reg = expr_dest_reg (params->c_expr); | |
5848 | gcc_assert (cur_reg && params->dest && REG_P (params->dest)); | |
e855c69d AB |
5849 | |
5850 | /* If original operation has expr and the register chosen for | |
5851 | that expr is not original operation's dest reg, substitute | |
5852 | operation's right hand side with the register chosen. */ | |
f07013eb | 5853 | if (REGNO (params->dest) != REGNO (cur_reg)) |
e855c69d AB |
5854 | { |
5855 | insn_t reg_move_insn, reg_move_insn_rtx; | |
b8698a0f L |
5856 | |
5857 | reg_move_insn_rtx = create_insn_rtx_with_rhs (INSN_VINSN (insn), | |
e855c69d | 5858 | params->dest); |
b8698a0f L |
5859 | reg_move_insn = sel_gen_insn_from_rtx_after (reg_move_insn_rtx, |
5860 | INSN_EXPR (insn), | |
5861 | INSN_SEQNO (insn), | |
e855c69d AB |
5862 | insn); |
5863 | EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn)) = 0; | |
5864 | replace_dest_with_reg_in_expr (params->c_expr, params->dest); | |
b8698a0f | 5865 | |
e855c69d AB |
5866 | insn_emitted = true; |
5867 | params->was_renamed = true; | |
5868 | } | |
b8698a0f | 5869 | |
e855c69d AB |
5870 | return insn_emitted; |
5871 | } | |
5872 | ||
b8698a0f L |
5873 | /* Emit a speculative check for INSN speculated as EXPR if needed. |
5874 | Return true if we've emitted one. PARAMS is the move_op static | |
e855c69d AB |
5875 | parameters. */ |
5876 | static bool | |
5877 | maybe_emit_speculative_check (rtx insn, expr_t expr, | |
5878 | moveop_static_params_p params) | |
5879 | { | |
5880 | bool insn_emitted = false; | |
5881 | insn_t x; | |
5882 | ds_t check_ds; | |
5883 | ||
5884 | check_ds = get_spec_check_type_for_insn (insn, expr); | |
5885 | if (check_ds != 0) | |
5886 | { | |
5887 | /* A speculation check should be inserted. */ | |
5888 | x = create_speculation_check (params->c_expr, check_ds, insn); | |
5889 | insn_emitted = true; | |
5890 | } | |
5891 | else | |
5892 | { | |
5893 | EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0; | |
5894 | x = insn; | |
5895 | } | |
b8698a0f | 5896 | |
e855c69d AB |
5897 | gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x)) == 0 |
5898 | && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x)) == 0); | |
5899 | return insn_emitted; | |
5900 | } | |
5901 | ||
b8698a0f L |
5902 | /* Handle transformations that leave an insn in place of original |
5903 | insn such as renaming/speculation. Return true if one of such | |
e855c69d AB |
5904 | transformations actually happened, and we have emitted this insn. */ |
5905 | static bool | |
b8698a0f | 5906 | handle_emitting_transformations (rtx insn, expr_t expr, |
e855c69d AB |
5907 | moveop_static_params_p params) |
5908 | { | |
5909 | bool insn_emitted = false; | |
5910 | ||
5911 | insn_emitted = maybe_emit_renaming_copy (insn, params); | |
5912 | insn_emitted |= maybe_emit_speculative_check (insn, expr, params); | |
5913 | ||
5914 | return insn_emitted; | |
b8698a0f | 5915 | } |
e855c69d | 5916 | |
b5b8b0ac AO |
5917 | /* If INSN is the only insn in the basic block (not counting JUMP, |
5918 | which may be a jump to next insn, and DEBUG_INSNs), we want to | |
5919 | leave a NOP there till the return to fill_insns. */ | |
5920 | ||
5921 | static bool | |
5922 | need_nop_to_preserve_insn_bb (rtx insn) | |
e855c69d | 5923 | { |
b5b8b0ac | 5924 | insn_t bb_head, bb_end, bb_next, in_next; |
e855c69d AB |
5925 | basic_block bb = BLOCK_FOR_INSN (insn); |
5926 | ||
e855c69d AB |
5927 | bb_head = sel_bb_head (bb); |
5928 | bb_end = sel_bb_end (bb); | |
e855c69d | 5929 | |
b5b8b0ac AO |
5930 | if (bb_head == bb_end) |
5931 | return true; | |
5932 | ||
5933 | while (bb_head != bb_end && DEBUG_INSN_P (bb_head)) | |
5934 | bb_head = NEXT_INSN (bb_head); | |
5935 | ||
5936 | if (bb_head == bb_end) | |
5937 | return true; | |
5938 | ||
5939 | while (bb_head != bb_end && DEBUG_INSN_P (bb_end)) | |
5940 | bb_end = PREV_INSN (bb_end); | |
5941 | ||
5942 | if (bb_head == bb_end) | |
5943 | return true; | |
5944 | ||
5945 | bb_next = NEXT_INSN (bb_head); | |
5946 | while (bb_next != bb_end && DEBUG_INSN_P (bb_next)) | |
5947 | bb_next = NEXT_INSN (bb_next); | |
5948 | ||
5949 | if (bb_next == bb_end && JUMP_P (bb_end)) | |
5950 | return true; | |
5951 | ||
5952 | in_next = NEXT_INSN (insn); | |
5953 | while (DEBUG_INSN_P (in_next)) | |
5954 | in_next = NEXT_INSN (in_next); | |
5955 | ||
5956 | if (IN_CURRENT_FENCE_P (in_next)) | |
5957 | return true; | |
5958 | ||
5959 | return false; | |
5960 | } | |
5961 | ||
5962 | /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data | |
5963 | is not removed but reused when INSN is re-emitted. */ | |
5964 | static void | |
5965 | remove_insn_from_stream (rtx insn, bool only_disconnect) | |
5966 | { | |
e855c69d AB |
5967 | /* If there's only one insn in the BB, make sure that a nop is |
5968 | inserted into it, so the basic block won't disappear when we'll | |
5969 | delete INSN below with sel_remove_insn. It should also survive | |
b8698a0f | 5970 | till the return to fill_insns. */ |
b5b8b0ac | 5971 | if (need_nop_to_preserve_insn_bb (insn)) |
e855c69d | 5972 | { |
b5b8b0ac | 5973 | insn_t nop = get_nop_from_pool (insn); |
e855c69d AB |
5974 | gcc_assert (INSN_NOP_P (nop)); |
5975 | VEC_safe_push (insn_t, heap, vec_temp_moveop_nops, nop); | |
5976 | } | |
5977 | ||
5978 | sel_remove_insn (insn, only_disconnect, false); | |
5979 | } | |
5980 | ||
5981 | /* This function is called when original expr is found. | |
b8698a0f | 5982 | INSN - current insn traversed, EXPR - the corresponding expr found. |
e855c69d AB |
5983 | LPARAMS is the local parameters of code modion driver, STATIC_PARAMS |
5984 | is static parameters of move_op. */ | |
5985 | static void | |
b8698a0f L |
5986 | move_op_orig_expr_found (insn_t insn, expr_t expr, |
5987 | cmpd_local_params_p lparams ATTRIBUTE_UNUSED, | |
e855c69d AB |
5988 | void *static_params) |
5989 | { | |
5990 | bool only_disconnect, insn_emitted; | |
5991 | moveop_static_params_p params = (moveop_static_params_p) static_params; | |
b8698a0f | 5992 | |
e855c69d AB |
5993 | copy_expr_onside (params->c_expr, INSN_EXPR (insn)); |
5994 | track_scheduled_insns_and_blocks (insn); | |
5995 | insn_emitted = handle_emitting_transformations (insn, expr, params); | |
5996 | only_disconnect = (params->uid == INSN_UID (insn) | |
5997 | && ! insn_emitted && ! EXPR_WAS_CHANGED (expr)); | |
72a54528 AM |
5998 | |
5999 | /* Mark that we've disconnected an insn. */ | |
6000 | if (only_disconnect) | |
6001 | params->uid = -1; | |
e855c69d AB |
6002 | remove_insn_from_stream (insn, only_disconnect); |
6003 | } | |
6004 | ||
6005 | /* The function is called when original expr is found. | |
6006 | INSN - current insn traversed, EXPR - the corresponding expr found, | |
6007 | crosses_call and original_insns in STATIC_PARAMS are updated. */ | |
6008 | static void | |
6009 | fur_orig_expr_found (insn_t insn, expr_t expr ATTRIBUTE_UNUSED, | |
6010 | cmpd_local_params_p lparams ATTRIBUTE_UNUSED, | |
6011 | void *static_params) | |
6012 | { | |
6013 | fur_static_params_p params = (fur_static_params_p) static_params; | |
6014 | regset tmp; | |
6015 | ||
6016 | if (CALL_P (insn)) | |
6017 | params->crosses_call = true; | |
6018 | ||
6019 | def_list_add (params->original_insns, insn, params->crosses_call); | |
6020 | ||
6021 | /* Mark the registers that do not meet the following condition: | |
b8698a0f L |
6022 | (2) not among the live registers of the point |
6023 | immediately following the first original operation on | |
e855c69d AB |
6024 | a given downward path, except for the original target |
6025 | register of the operation. */ | |
6026 | tmp = get_clear_regset_from_pool (); | |
6027 | compute_live_below_insn (insn, tmp); | |
6028 | AND_COMPL_REG_SET (tmp, INSN_REG_SETS (insn)); | |
6029 | AND_COMPL_REG_SET (tmp, INSN_REG_CLOBBERS (insn)); | |
6030 | IOR_REG_SET (params->used_regs, tmp); | |
6031 | return_regset_to_pool (tmp); | |
6032 | ||
6033 | /* (*1) We need to add to USED_REGS registers that are read by | |
6034 | INSN's lhs. This may lead to choosing wrong src register. | |
6035 | E.g. (scheduling const expr enabled): | |
6036 | ||
6037 | 429: ax=0x0 <- Can't use AX for this expr (0x0) | |
6038 | 433: dx=[bp-0x18] | |
6039 | 427: [ax+dx+0x1]=ax | |
6040 | REG_DEAD: ax | |
6041 | 168: di=dx | |
6042 | REG_DEAD: dx | |
6043 | */ | |
b8698a0f | 6044 | /* FIXME: see comment above and enable MEM_P |
e855c69d AB |
6045 | in vinsn_separable_p. */ |
6046 | gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn)) | |
6047 | || !MEM_P (INSN_LHS (insn))); | |
6048 | } | |
6049 | ||
6050 | /* This function is called on the ascending pass, before returning from | |
6051 | current basic block. */ | |
6052 | static void | |
b8698a0f | 6053 | move_op_at_first_insn (insn_t insn, cmpd_local_params_p lparams, |
e855c69d AB |
6054 | void *static_params) |
6055 | { | |
6056 | moveop_static_params_p sparams = (moveop_static_params_p) static_params; | |
6057 | basic_block book_block = NULL; | |
6058 | ||
b8698a0f | 6059 | /* When we have removed the boundary insn for scheduling, which also |
e855c69d | 6060 | happened to be the end insn in its bb, we don't need to update sets. */ |
b8698a0f | 6061 | if (!lparams->removed_last_insn |
e855c69d AB |
6062 | && lparams->e1 |
6063 | && sel_bb_head_p (insn)) | |
6064 | { | |
6065 | /* We should generate bookkeeping code only if we are not at the | |
6066 | top level of the move_op. */ | |
6067 | if (sel_num_cfg_preds_gt_1 (insn)) | |
6068 | book_block = generate_bookkeeping_insn (sparams->c_expr, | |
6069 | lparams->e1, lparams->e2); | |
6070 | /* Update data sets for the current insn. */ | |
6071 | update_data_sets (insn); | |
6072 | } | |
b8698a0f | 6073 | |
e855c69d | 6074 | /* If bookkeeping code was inserted, we need to update av sets of basic |
b8698a0f | 6075 | block that received bookkeeping. After generation of bookkeeping insn, |
e855c69d | 6076 | bookkeeping block does not contain valid av set because we are not following |
b8698a0f | 6077 | the original algorithm in every detail with regards to e.g. renaming |
e855c69d | 6078 | simple reg-reg copies. Consider example: |
b8698a0f | 6079 | |
e855c69d AB |
6080 | bookkeeping block scheduling fence |
6081 | \ / | |
6082 | \ join / | |
6083 | ---------- | |
6084 | | | | |
6085 | ---------- | |
6086 | / \ | |
6087 | / \ | |
6088 | r1 := r2 r1 := r3 | |
6089 | ||
b8698a0f | 6090 | We try to schedule insn "r1 := r3" on the current |
e855c69d AB |
6091 | scheduling fence. Also, note that av set of bookkeeping block |
6092 | contain both insns "r1 := r2" and "r1 := r3". When the insn has | |
6093 | been scheduled, the CFG is as follows: | |
6094 | ||
6095 | r1 := r3 r1 := r3 | |
6096 | bookkeeping block scheduling fence | |
6097 | \ / | |
6098 | \ join / | |
6099 | ---------- | |
6100 | | | | |
6101 | ---------- | |
6102 | / \ | |
6103 | / \ | |
6104 | r1 := r2 | |
6105 | ||
6106 | Here, insn "r1 := r3" was scheduled at the current scheduling point | |
6107 | and bookkeeping code was generated at the bookeeping block. This | |
6108 | way insn "r1 := r2" is no longer available as a whole instruction | |
6109 | (but only as expr) ahead of insn "r1 := r3" in bookkeeping block. | |
b8698a0f | 6110 | This situation is handled by calling update_data_sets. |
e855c69d AB |
6111 | |
6112 | Since update_data_sets is called only on the bookkeeping block, and | |
b8698a0f | 6113 | it also may have predecessors with av_sets, containing instructions that |
e855c69d AB |
6114 | are no longer available, we save all such expressions that become |
6115 | unavailable during data sets update on the bookkeeping block in | |
b8698a0f L |
6116 | VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such |
6117 | expressions for scheduling. This allows us to avoid recomputation of | |
e855c69d | 6118 | av_sets outside the code motion path. */ |
b8698a0f | 6119 | |
e855c69d AB |
6120 | if (book_block) |
6121 | update_and_record_unavailable_insns (book_block); | |
6122 | ||
6123 | /* If INSN was previously marked for deletion, it's time to do it. */ | |
6124 | if (lparams->removed_last_insn) | |
6125 | insn = PREV_INSN (insn); | |
b8698a0f | 6126 | |
e855c69d AB |
6127 | /* Do not tidy control flow at the topmost moveop, as we can erroneously |
6128 | kill a block with a single nop in which the insn should be emitted. */ | |
6129 | if (lparams->e1) | |
6130 | tidy_control_flow (BLOCK_FOR_INSN (insn), true); | |
6131 | } | |
6132 | ||
6133 | /* This function is called on the ascending pass, before returning from the | |
6134 | current basic block. */ | |
6135 | static void | |
b8698a0f L |
6136 | fur_at_first_insn (insn_t insn, |
6137 | cmpd_local_params_p lparams ATTRIBUTE_UNUSED, | |
e855c69d AB |
6138 | void *static_params ATTRIBUTE_UNUSED) |
6139 | { | |
6140 | gcc_assert (!sel_bb_head_p (insn) || AV_SET_VALID_P (insn) | |
6141 | || AV_LEVEL (insn) == -1); | |
6142 | } | |
6143 | ||
6144 | /* Called on the backward stage of recursion to call moveup_expr for insn | |
6145 | and sparams->c_expr. */ | |
6146 | static void | |
6147 | move_op_ascend (insn_t insn, void *static_params) | |
6148 | { | |
6149 | enum MOVEUP_EXPR_CODE res; | |
6150 | moveop_static_params_p sparams = (moveop_static_params_p) static_params; | |
6151 | ||
6152 | if (! INSN_NOP_P (insn)) | |
6153 | { | |
6154 | res = moveup_expr_cached (sparams->c_expr, insn, false); | |
6155 | gcc_assert (res != MOVEUP_EXPR_NULL); | |
6156 | } | |
6157 | ||
6158 | /* Update liveness for this insn as it was invalidated. */ | |
6159 | update_liveness_on_insn (insn); | |
6160 | } | |
6161 | ||
b8698a0f L |
6162 | /* This function is called on enter to the basic block. |
6163 | Returns TRUE if this block already have been visited and | |
e855c69d AB |
6164 | code_motion_path_driver should return 1, FALSE otherwise. */ |
6165 | static int | |
b8698a0f | 6166 | fur_on_enter (insn_t insn ATTRIBUTE_UNUSED, cmpd_local_params_p local_params, |
e855c69d AB |
6167 | void *static_params, bool visited_p) |
6168 | { | |
6169 | fur_static_params_p sparams = (fur_static_params_p) static_params; | |
6170 | ||
6171 | if (visited_p) | |
6172 | { | |
6173 | /* If we have found something below this block, there should be at | |
6174 | least one insn in ORIGINAL_INSNS. */ | |
6175 | gcc_assert (*sparams->original_insns); | |
6176 | ||
6177 | /* Adjust CROSSES_CALL, since we may have come to this block along | |
6178 | different path. */ | |
6179 | DEF_LIST_DEF (*sparams->original_insns)->crosses_call | |
6180 | |= sparams->crosses_call; | |
6181 | } | |
6182 | else | |
6183 | local_params->old_original_insns = *sparams->original_insns; | |
6184 | ||
6185 | return 1; | |
6186 | } | |
6187 | ||
6188 | /* Same as above but for move_op. */ | |
6189 | static int | |
b8698a0f L |
6190 | move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED, |
6191 | cmpd_local_params_p local_params ATTRIBUTE_UNUSED, | |
e855c69d AB |
6192 | void *static_params ATTRIBUTE_UNUSED, bool visited_p) |
6193 | { | |
6194 | if (visited_p) | |
6195 | return -1; | |
6196 | return 1; | |
6197 | } | |
6198 | ||
b8698a0f | 6199 | /* This function is called while descending current basic block if current |
e855c69d AB |
6200 | insn is not the original EXPR we're searching for. |
6201 | ||
b8698a0f | 6202 | Return value: FALSE, if code_motion_path_driver should perform a local |
e855c69d AB |
6203 | cleanup and return 0 itself; |
6204 | TRUE, if code_motion_path_driver should continue. */ | |
6205 | static bool | |
6206 | move_op_orig_expr_not_found (insn_t insn, av_set_t orig_ops ATTRIBUTE_UNUSED, | |
6207 | void *static_params) | |
6208 | { | |
6209 | moveop_static_params_p sparams = (moveop_static_params_p) static_params; | |
6210 | ||
6211 | #ifdef ENABLE_CHECKING | |
6212 | sparams->failed_insn = insn; | |
6213 | #endif | |
6214 | ||
6215 | /* If we're scheduling separate expr, in order to generate correct code | |
b8698a0f | 6216 | we need to stop the search at bookkeeping code generated with the |
e855c69d AB |
6217 | same destination register or memory. */ |
6218 | if (lhs_of_insn_equals_to_dest_p (insn, sparams->dest)) | |
6219 | return false; | |
6220 | return true; | |
6221 | } | |
6222 | ||
b8698a0f | 6223 | /* This function is called while descending current basic block if current |
e855c69d AB |
6224 | insn is not the original EXPR we're searching for. |
6225 | ||
6226 | Return value: TRUE (code_motion_path_driver should continue). */ | |
6227 | static bool | |
6228 | fur_orig_expr_not_found (insn_t insn, av_set_t orig_ops, void *static_params) | |
6229 | { | |
6230 | bool mutexed; | |
6231 | expr_t r; | |
6232 | av_set_iterator avi; | |
6233 | fur_static_params_p sparams = (fur_static_params_p) static_params; | |
6234 | ||
6235 | if (CALL_P (insn)) | |
6236 | sparams->crosses_call = true; | |
b5b8b0ac AO |
6237 | else if (DEBUG_INSN_P (insn)) |
6238 | return true; | |
e855c69d AB |
6239 | |
6240 | /* If current insn we are looking at cannot be executed together | |
6241 | with original insn, then we can skip it safely. | |
6242 | ||
6243 | Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); } | |
6244 | INSN = (!p6) r14 = r14 + 1; | |
6245 | ||
6246 | Here we can schedule ORIG_OP with lhs = r14, though only | |
6247 | looking at the set of used and set registers of INSN we must | |
6248 | forbid it. So, add set/used in INSN registers to the | |
6249 | untouchable set only if there is an insn in ORIG_OPS that can | |
6250 | affect INSN. */ | |
6251 | mutexed = true; | |
6252 | FOR_EACH_EXPR (r, avi, orig_ops) | |
6253 | if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (r))) | |
6254 | { | |
6255 | mutexed = false; | |
6256 | break; | |
6257 | } | |
6258 | ||
6259 | /* Mark all registers that do not meet the following condition: | |
6260 | (1) Not set or read on any path from xi to an instance of the | |
6261 | original operation. */ | |
6262 | if (!mutexed) | |
6263 | { | |
6264 | IOR_REG_SET (sparams->used_regs, INSN_REG_SETS (insn)); | |
6265 | IOR_REG_SET (sparams->used_regs, INSN_REG_USES (insn)); | |
6266 | IOR_REG_SET (sparams->used_regs, INSN_REG_CLOBBERS (insn)); | |
6267 | } | |
6268 | ||
6269 | return true; | |
6270 | } | |
6271 | ||
6272 | /* Hooks and data to perform move_op operations with code_motion_path_driver. */ | |
6273 | struct code_motion_path_driver_info_def move_op_hooks = { | |
6274 | move_op_on_enter, | |
6275 | move_op_orig_expr_found, | |
6276 | move_op_orig_expr_not_found, | |
6277 | move_op_merge_succs, | |
6278 | move_op_after_merge_succs, | |
6279 | move_op_ascend, | |
6280 | move_op_at_first_insn, | |
6281 | SUCCS_NORMAL, | |
6282 | "move_op" | |
6283 | }; | |
6284 | ||
b8698a0f | 6285 | /* Hooks and data to perform find_used_regs operations |
e855c69d AB |
6286 | with code_motion_path_driver. */ |
6287 | struct code_motion_path_driver_info_def fur_hooks = { | |
6288 | fur_on_enter, | |
6289 | fur_orig_expr_found, | |
6290 | fur_orig_expr_not_found, | |
6291 | fur_merge_succs, | |
6292 | NULL, /* fur_after_merge_succs */ | |
6293 | NULL, /* fur_ascend */ | |
6294 | fur_at_first_insn, | |
6295 | SUCCS_ALL, | |
6296 | "find_used_regs" | |
6297 | }; | |
6298 | ||
6299 | /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL | |
b8698a0f L |
6300 | code_motion_path_driver is called recursively. Original operation |
6301 | was found at least on one path that is starting with one of INSN's | |
e855c69d AB |
6302 | successors (this fact is asserted). ORIG_OPS is expressions we're looking |
6303 | for, PATH is the path we've traversed, STATIC_PARAMS is the parameters | |
b8698a0f | 6304 | of either move_op or find_used_regs depending on the caller. |
e855c69d AB |
6305 | |
6306 | Return 0 if we haven't found expression, 1 if we found it, -1 if we don't | |
6307 | know for sure at this point. */ | |
6308 | static int | |
b8698a0f | 6309 | code_motion_process_successors (insn_t insn, av_set_t orig_ops, |
e855c69d AB |
6310 | ilist_t path, void *static_params) |
6311 | { | |
6312 | int res = 0; | |
6313 | succ_iterator succ_i; | |
6314 | rtx succ; | |
6315 | basic_block bb; | |
6316 | int old_index; | |
6317 | unsigned old_succs; | |
6318 | ||
6319 | struct cmpd_local_params lparams; | |
6320 | expr_def _x; | |
6321 | ||
6322 | lparams.c_expr_local = &_x; | |
6323 | lparams.c_expr_merged = NULL; | |
6324 | ||
6325 | /* We need to process only NORMAL succs for move_op, and collect live | |
b8698a0f L |
6326 | registers from ALL branches (including those leading out of the |
6327 | region) for find_used_regs. | |
e855c69d AB |
6328 | |
6329 | In move_op, there can be a case when insn's bb number has changed | |
b8698a0f L |
6330 | due to created bookkeeping. This happens very rare, as we need to |
6331 | move expression from the beginning to the end of the same block. | |
6332 | Rescan successors in this case. */ | |
e855c69d AB |
6333 | |
6334 | rescan: | |
6335 | bb = BLOCK_FOR_INSN (insn); | |
b8698a0f | 6336 | old_index = bb->index; |
e855c69d | 6337 | old_succs = EDGE_COUNT (bb->succs); |
b8698a0f | 6338 | |
e855c69d AB |
6339 | FOR_EACH_SUCC_1 (succ, succ_i, insn, code_motion_path_driver_info->succ_flags) |
6340 | { | |
6341 | int b; | |
6342 | ||
6343 | lparams.e1 = succ_i.e1; | |
6344 | lparams.e2 = succ_i.e2; | |
6345 | ||
6346 | /* Go deep into recursion only for NORMAL edges (non-backedges within the | |
6347 | current region). */ | |
6348 | if (succ_i.current_flags == SUCCS_NORMAL) | |
b8698a0f | 6349 | b = code_motion_path_driver (succ, orig_ops, path, &lparams, |
e855c69d AB |
6350 | static_params); |
6351 | else | |
6352 | b = 0; | |
6353 | ||
6354 | /* Merge c_expres found or unify live register sets from different | |
6355 | successors. */ | |
6356 | code_motion_path_driver_info->merge_succs (insn, succ, b, &lparams, | |
6357 | static_params); | |
6358 | if (b == 1) | |
6359 | res = b; | |
6360 | else if (b == -1 && res != 1) | |
6361 | res = b; | |
6362 | ||
6363 | /* We have simplified the control flow below this point. In this case, | |
6364 | the iterator becomes invalid. We need to try again. */ | |
6365 | if (BLOCK_FOR_INSN (insn)->index != old_index | |
6366 | || EDGE_COUNT (bb->succs) != old_succs) | |
7c1f0b40 DM |
6367 | { |
6368 | insn = sel_bb_end (BLOCK_FOR_INSN (insn)); | |
6369 | goto rescan; | |
6370 | } | |
e855c69d AB |
6371 | } |
6372 | ||
cefb375a | 6373 | #ifdef ENABLE_CHECKING |
b8698a0f | 6374 | /* Here, RES==1 if original expr was found at least for one of the |
e855c69d | 6375 | successors. After the loop, RES may happen to have zero value |
b8698a0f L |
6376 | only if at some point the expr searched is present in av_set, but is |
6377 | not found below. In most cases, this situation is an error. | |
e855c69d AB |
6378 | The exception is when the original operation is blocked by |
6379 | bookkeeping generated for another fence or for another path in current | |
6380 | move_op. */ | |
cefb375a NF |
6381 | gcc_assert (res == 1 |
6382 | || (res == 0 | |
6383 | && av_set_could_be_blocked_by_bookkeeping_p (orig_ops, | |
6384 | static_params)) | |
6385 | || res == -1); | |
6386 | #endif | |
b8698a0f | 6387 | |
e855c69d | 6388 | /* Merge data, clean up, etc. */ |
72a54528 | 6389 | if (res != -1 && code_motion_path_driver_info->after_merge_succs) |
e855c69d AB |
6390 | code_motion_path_driver_info->after_merge_succs (&lparams, static_params); |
6391 | ||
6392 | return res; | |
6393 | } | |
6394 | ||
6395 | ||
b8698a0f L |
6396 | /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P |
6397 | is the pointer to the av set with expressions we were looking for, | |
e855c69d AB |
6398 | PATH_P is the pointer to the traversed path. */ |
6399 | static inline void | |
6400 | code_motion_path_driver_cleanup (av_set_t *orig_ops_p, ilist_t *path_p) | |
6401 | { | |
6402 | ilist_remove (path_p); | |
6403 | av_set_clear (orig_ops_p); | |
6404 | } | |
6405 | ||
b8698a0f L |
6406 | /* The driver function that implements move_op or find_used_regs |
6407 | functionality dependent whether code_motion_path_driver_INFO is set to | |
6408 | &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts | |
e855c69d AB |
6409 | of code (CFG traversal etc) that are shared among both functions. INSN |
6410 | is the insn we're starting the search from, ORIG_OPS are the expressions | |
6411 | we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local | |
6412 | parameters of the driver, and STATIC_PARAMS are static parameters of | |
b8698a0f | 6413 | the caller. |
e855c69d AB |
6414 | |
6415 | Returns whether original instructions were found. Note that top-level | |
6416 | code_motion_path_driver always returns true. */ | |
72a54528 | 6417 | static int |
b8698a0f L |
6418 | code_motion_path_driver (insn_t insn, av_set_t orig_ops, ilist_t path, |
6419 | cmpd_local_params_p local_params_in, | |
e855c69d AB |
6420 | void *static_params) |
6421 | { | |
6422 | expr_t expr = NULL; | |
6423 | basic_block bb = BLOCK_FOR_INSN (insn); | |
6424 | insn_t first_insn, bb_tail, before_first; | |
6425 | bool removed_last_insn = false; | |
6426 | ||
6427 | if (sched_verbose >= 6) | |
6428 | { | |
6429 | sel_print ("%s (", code_motion_path_driver_info->routine_name); | |
6430 | dump_insn (insn); | |
6431 | sel_print (","); | |
6432 | dump_av_set (orig_ops); | |
6433 | sel_print (")\n"); | |
6434 | } | |
6435 | ||
6436 | gcc_assert (orig_ops); | |
6437 | ||
6438 | /* If no original operations exist below this insn, return immediately. */ | |
6439 | if (is_ineligible_successor (insn, path)) | |
6440 | { | |
6441 | if (sched_verbose >= 6) | |
6442 | sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn)); | |
6443 | return false; | |
6444 | } | |
b8698a0f | 6445 | |
e855c69d AB |
6446 | /* The block can have invalid av set, in which case it was created earlier |
6447 | during move_op. Return immediately. */ | |
6448 | if (sel_bb_head_p (insn)) | |
6449 | { | |
6450 | if (! AV_SET_VALID_P (insn)) | |
6451 | { | |
6452 | if (sched_verbose >= 6) | |
6453 | sel_print ("Returned from block %d as it had invalid av set\n", | |
6454 | bb->index); | |
6455 | return false; | |
6456 | } | |
6457 | ||
6458 | if (bitmap_bit_p (code_motion_visited_blocks, bb->index)) | |
6459 | { | |
6460 | /* We have already found an original operation on this branch, do not | |
6461 | go any further and just return TRUE here. If we don't stop here, | |
b8698a0f | 6462 | function can have exponential behaviour even on the small code |
e855c69d AB |
6463 | with many different paths (e.g. with data speculation and |
6464 | recovery blocks). */ | |
6465 | if (sched_verbose >= 6) | |
6466 | sel_print ("Block %d already visited in this traversal\n", bb->index); | |
6467 | if (code_motion_path_driver_info->on_enter) | |
b8698a0f | 6468 | return code_motion_path_driver_info->on_enter (insn, |
e855c69d | 6469 | local_params_in, |
b8698a0f | 6470 | static_params, |
e855c69d AB |
6471 | true); |
6472 | } | |
6473 | } | |
b8698a0f | 6474 | |
e855c69d AB |
6475 | if (code_motion_path_driver_info->on_enter) |
6476 | code_motion_path_driver_info->on_enter (insn, local_params_in, | |
6477 | static_params, false); | |
6478 | orig_ops = av_set_copy (orig_ops); | |
6479 | ||
6480 | /* Filter the orig_ops set. */ | |
6481 | if (AV_SET_VALID_P (insn)) | |
5d369d58 | 6482 | av_set_code_motion_filter (&orig_ops, AV_SET (insn)); |
e855c69d AB |
6483 | |
6484 | /* If no more original ops, return immediately. */ | |
6485 | if (!orig_ops) | |
6486 | { | |
6487 | if (sched_verbose >= 6) | |
6488 | sel_print ("No intersection with av set of block %d\n", bb->index); | |
6489 | return false; | |
6490 | } | |
6491 | ||
6492 | /* For non-speculative insns we have to leave only one form of the | |
b8698a0f | 6493 | original operation, because if we don't, we may end up with |
e855c69d AB |
6494 | different C_EXPRes and, consequently, with bookkeepings for different |
6495 | expression forms along the same code motion path. That may lead to | |
b8698a0f L |
6496 | generation of incorrect code. So for each code motion we stick to |
6497 | the single form of the instruction, except for speculative insns | |
6498 | which we need to keep in different forms with all speculation | |
e855c69d AB |
6499 | types. */ |
6500 | av_set_leave_one_nonspec (&orig_ops); | |
6501 | ||
6502 | /* It is not possible that all ORIG_OPS are filtered out. */ | |
6503 | gcc_assert (orig_ops); | |
6504 | ||
6505 | /* It is enough to place only heads and tails of visited basic blocks into | |
6506 | the PATH. */ | |
6507 | ilist_add (&path, insn); | |
6508 | first_insn = insn; | |
6509 | bb_tail = sel_bb_end (bb); | |
6510 | ||
6511 | /* Descend the basic block in search of the original expr; this part | |
b8698a0f | 6512 | corresponds to the part of the original move_op procedure executed |
e855c69d AB |
6513 | before the recursive call. */ |
6514 | for (;;) | |
6515 | { | |
6516 | /* Look at the insn and decide if it could be an ancestor of currently | |
6517 | scheduling operation. If it is so, then the insn "dest = op" could | |
6518 | either be replaced with "dest = reg", because REG now holds the result | |
6519 | of OP, or just removed, if we've scheduled the insn as a whole. | |
6520 | ||
6521 | If this insn doesn't contain currently scheduling OP, then proceed | |
6522 | with searching and look at its successors. Operations we're searching | |
b8698a0f | 6523 | for could have changed when moving up through this insn via |
e855c69d AB |
6524 | substituting. In this case, perform unsubstitution on them first. |
6525 | ||
6526 | When traversing the DAG below this insn is finished, insert | |
6527 | bookkeeping code, if the insn is a joint point, and remove | |
6528 | leftovers. */ | |
6529 | ||
6530 | expr = av_set_lookup (orig_ops, INSN_VINSN (insn)); | |
6531 | if (expr) | |
6532 | { | |
6533 | insn_t last_insn = PREV_INSN (insn); | |
6534 | ||
6535 | /* We have found the original operation. */ | |
6536 | if (sched_verbose >= 6) | |
6537 | sel_print ("Found original operation at insn %d\n", INSN_UID (insn)); | |
6538 | ||
b8698a0f | 6539 | code_motion_path_driver_info->orig_expr_found |
e855c69d AB |
6540 | (insn, expr, local_params_in, static_params); |
6541 | ||
6542 | /* Step back, so on the way back we'll start traversing from the | |
b8698a0f | 6543 | previous insn (or we'll see that it's bb_note and skip that |
e855c69d AB |
6544 | loop). */ |
6545 | if (insn == first_insn) | |
6546 | { | |
6547 | first_insn = NEXT_INSN (last_insn); | |
6548 | removed_last_insn = sel_bb_end_p (last_insn); | |
6549 | } | |
6550 | insn = last_insn; | |
6551 | break; | |
6552 | } | |
6553 | else | |
6554 | { | |
6555 | /* We haven't found the original expr, continue descending the basic | |
6556 | block. */ | |
b8698a0f | 6557 | if (code_motion_path_driver_info->orig_expr_not_found |
e855c69d AB |
6558 | (insn, orig_ops, static_params)) |
6559 | { | |
b8698a0f | 6560 | /* Av set ops could have been changed when moving through this |
e855c69d AB |
6561 | insn. To find them below it, we have to un-substitute them. */ |
6562 | undo_transformations (&orig_ops, insn); | |
6563 | } | |
6564 | else | |
6565 | { | |
6566 | /* Clean up and return, if the hook tells us to do so. It may | |
b8698a0f | 6567 | happen if we've encountered the previously created |
e855c69d AB |
6568 | bookkeeping. */ |
6569 | code_motion_path_driver_cleanup (&orig_ops, &path); | |
6570 | return -1; | |
6571 | } | |
6572 | ||
6573 | gcc_assert (orig_ops); | |
6574 | } | |
6575 | ||
6576 | /* Stop at insn if we got to the end of BB. */ | |
6577 | if (insn == bb_tail) | |
6578 | break; | |
6579 | ||
6580 | insn = NEXT_INSN (insn); | |
6581 | } | |
6582 | ||
b8698a0f | 6583 | /* Here INSN either points to the insn before the original insn (may be |
e855c69d AB |
6584 | bb_note, if original insn was a bb_head) or to the bb_end. */ |
6585 | if (!expr) | |
6586 | { | |
6587 | int res; | |
7c1f0b40 DM |
6588 | rtx last_insn = PREV_INSN (insn); |
6589 | bool added_to_path; | |
e855c69d AB |
6590 | |
6591 | gcc_assert (insn == sel_bb_end (bb)); | |
6592 | ||
6593 | /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head - | |
6594 | it's already in PATH then). */ | |
6595 | if (insn != first_insn) | |
7c1f0b40 DM |
6596 | { |
6597 | ilist_add (&path, insn); | |
6598 | added_to_path = true; | |
6599 | } | |
6600 | else | |
6601 | added_to_path = false; | |
e855c69d | 6602 | |
b8698a0f L |
6603 | /* Process_successors should be able to find at least one |
6604 | successor for which code_motion_path_driver returns TRUE. */ | |
6605 | res = code_motion_process_successors (insn, orig_ops, | |
e855c69d AB |
6606 | path, static_params); |
6607 | ||
7c1f0b40 DM |
6608 | /* Jump in the end of basic block could have been removed or replaced |
6609 | during code_motion_process_successors, so recompute insn as the | |
6610 | last insn in bb. */ | |
6611 | if (NEXT_INSN (last_insn) != insn) | |
6612 | { | |
6613 | insn = sel_bb_end (bb); | |
6614 | first_insn = sel_bb_head (bb); | |
6615 | } | |
6616 | ||
e855c69d | 6617 | /* Remove bb tail from path. */ |
7c1f0b40 | 6618 | if (added_to_path) |
e855c69d AB |
6619 | ilist_remove (&path); |
6620 | ||
6621 | if (res != 1) | |
6622 | { | |
6623 | /* This is the case when one of the original expr is no longer available | |
b8698a0f | 6624 | due to bookkeeping created on this branch with the same register. |
e855c69d | 6625 | In the original algorithm, which doesn't have update_data_sets call |
b8698a0f L |
6626 | on a bookkeeping block, it would simply result in returning |
6627 | FALSE when we've encountered a previously generated bookkeeping | |
e855c69d AB |
6628 | insn in moveop_orig_expr_not_found. */ |
6629 | code_motion_path_driver_cleanup (&orig_ops, &path); | |
6630 | return res; | |
6631 | } | |
6632 | } | |
6633 | ||
6634 | /* Don't need it any more. */ | |
6635 | av_set_clear (&orig_ops); | |
6636 | ||
b8698a0f | 6637 | /* Backward pass: now, when we have C_EXPR computed, we'll drag it to |
e855c69d AB |
6638 | the beginning of the basic block. */ |
6639 | before_first = PREV_INSN (first_insn); | |
6640 | while (insn != before_first) | |
b8698a0f | 6641 | { |
e855c69d AB |
6642 | if (code_motion_path_driver_info->ascend) |
6643 | code_motion_path_driver_info->ascend (insn, static_params); | |
6644 | ||
6645 | insn = PREV_INSN (insn); | |
6646 | } | |
b8698a0f | 6647 | |
e855c69d AB |
6648 | /* Now we're at the bb head. */ |
6649 | insn = first_insn; | |
6650 | ilist_remove (&path); | |
6651 | local_params_in->removed_last_insn = removed_last_insn; | |
6652 | code_motion_path_driver_info->at_first_insn (insn, local_params_in, static_params); | |
b8698a0f | 6653 | |
e855c69d AB |
6654 | /* This should be the very last operation as at bb head we could change |
6655 | the numbering by creating bookkeeping blocks. */ | |
6656 | if (removed_last_insn) | |
6657 | insn = PREV_INSN (insn); | |
6658 | bitmap_set_bit (code_motion_visited_blocks, BLOCK_FOR_INSN (insn)->index); | |
6659 | return true; | |
6660 | } | |
6661 | ||
b8698a0f | 6662 | /* Move up the operations from ORIG_OPS set traversing the dag starting |
e855c69d AB |
6663 | from INSN. PATH represents the edges traversed so far. |
6664 | DEST is the register chosen for scheduling the current expr. Insert | |
6665 | bookkeeping code in the join points. EXPR_VLIW is the chosen expression, | |
b8698a0f | 6666 | C_EXPR is how it looks like at the given cfg point. |
72a54528 AM |
6667 | Set *SHOULD_MOVE to indicate whether we have only disconnected |
6668 | one of the insns found. | |
e855c69d | 6669 | |
b8698a0f | 6670 | Returns whether original instructions were found, which is asserted |
e855c69d AB |
6671 | to be true in the caller. */ |
6672 | static bool | |
6673 | move_op (insn_t insn, av_set_t orig_ops, expr_t expr_vliw, | |
72a54528 | 6674 | rtx dest, expr_t c_expr, bool *should_move) |
e855c69d AB |
6675 | { |
6676 | struct moveop_static_params sparams; | |
6677 | struct cmpd_local_params lparams; | |
6678 | bool res; | |
6679 | ||
b8698a0f | 6680 | /* Init params for code_motion_path_driver. */ |
e855c69d AB |
6681 | sparams.dest = dest; |
6682 | sparams.c_expr = c_expr; | |
6683 | sparams.uid = INSN_UID (EXPR_INSN_RTX (expr_vliw)); | |
6684 | #ifdef ENABLE_CHECKING | |
6685 | sparams.failed_insn = NULL; | |
6686 | #endif | |
6687 | sparams.was_renamed = false; | |
6688 | lparams.e1 = NULL; | |
6689 | ||
6690 | /* We haven't visited any blocks yet. */ | |
6691 | bitmap_clear (code_motion_visited_blocks); | |
b8698a0f | 6692 | |
e855c69d AB |
6693 | /* Set appropriate hooks and data. */ |
6694 | code_motion_path_driver_info = &move_op_hooks; | |
6695 | res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams); | |
6696 | ||
6697 | if (sparams.was_renamed) | |
6698 | EXPR_WAS_RENAMED (expr_vliw) = true; | |
6699 | ||
72a54528 AM |
6700 | *should_move = (sparams.uid == -1); |
6701 | ||
e855c69d AB |
6702 | return res; |
6703 | } | |
6704 | \f | |
6705 | ||
6706 | /* Functions that work with regions. */ | |
6707 | ||
6708 | /* Current number of seqno used in init_seqno and init_seqno_1. */ | |
6709 | static int cur_seqno; | |
6710 | ||
b8698a0f L |
6711 | /* A helper for init_seqno. Traverse the region starting from BB and |
6712 | compute seqnos for visited insns, marking visited bbs in VISITED_BBS. | |
e855c69d AB |
6713 | Clear visited blocks from BLOCKS_TO_RESCHEDULE. */ |
6714 | static void | |
6715 | init_seqno_1 (basic_block bb, sbitmap visited_bbs, bitmap blocks_to_reschedule) | |
6716 | { | |
6717 | int bbi = BLOCK_TO_BB (bb->index); | |
6718 | insn_t insn, note = bb_note (bb); | |
6719 | insn_t succ_insn; | |
6720 | succ_iterator si; | |
6721 | ||
6722 | SET_BIT (visited_bbs, bbi); | |
6723 | if (blocks_to_reschedule) | |
6724 | bitmap_clear_bit (blocks_to_reschedule, bb->index); | |
6725 | ||
b8698a0f | 6726 | FOR_EACH_SUCC_1 (succ_insn, si, BB_END (bb), |
e855c69d AB |
6727 | SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS) |
6728 | { | |
6729 | basic_block succ = BLOCK_FOR_INSN (succ_insn); | |
6730 | int succ_bbi = BLOCK_TO_BB (succ->index); | |
6731 | ||
6732 | gcc_assert (in_current_region_p (succ)); | |
6733 | ||
6734 | if (!TEST_BIT (visited_bbs, succ_bbi)) | |
6735 | { | |
6736 | gcc_assert (succ_bbi > bbi); | |
6737 | ||
6738 | init_seqno_1 (succ, visited_bbs, blocks_to_reschedule); | |
6739 | } | |
06f0c25f AB |
6740 | else if (blocks_to_reschedule) |
6741 | bitmap_set_bit (forced_ebb_heads, succ->index); | |
e855c69d AB |
6742 | } |
6743 | ||
6744 | for (insn = BB_END (bb); insn != note; insn = PREV_INSN (insn)) | |
6745 | INSN_SEQNO (insn) = cur_seqno--; | |
6746 | } | |
6747 | ||
1f3b2b4e AM |
6748 | /* Initialize seqnos for the current region. BLOCKS_TO_RESCHEDULE contains |
6749 | blocks on which we're rescheduling when pipelining, FROM is the block where | |
e855c69d | 6750 | traversing region begins (it may not be the head of the region when |
b8698a0f | 6751 | pipelining, but the head of the loop instead). |
e855c69d AB |
6752 | |
6753 | Returns the maximal seqno found. */ | |
6754 | static int | |
1f3b2b4e | 6755 | init_seqno (bitmap blocks_to_reschedule, basic_block from) |
e855c69d AB |
6756 | { |
6757 | sbitmap visited_bbs; | |
6758 | bitmap_iterator bi; | |
6759 | unsigned bbi; | |
6760 | ||
6761 | visited_bbs = sbitmap_alloc (current_nr_blocks); | |
6762 | ||
6763 | if (blocks_to_reschedule) | |
6764 | { | |
6765 | sbitmap_ones (visited_bbs); | |
6766 | EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule, 0, bbi, bi) | |
6767 | { | |
6768 | gcc_assert (BLOCK_TO_BB (bbi) < current_nr_blocks); | |
6769 | RESET_BIT (visited_bbs, BLOCK_TO_BB (bbi)); | |
6770 | } | |
6771 | } | |
6772 | else | |
6773 | { | |
6774 | sbitmap_zero (visited_bbs); | |
6775 | from = EBB_FIRST_BB (0); | |
6776 | } | |
6777 | ||
1f3b2b4e | 6778 | cur_seqno = sched_max_luid - 1; |
e855c69d | 6779 | init_seqno_1 (from, visited_bbs, blocks_to_reschedule); |
1f3b2b4e AM |
6780 | |
6781 | /* cur_seqno may be positive if the number of instructions is less than | |
6782 | sched_max_luid - 1 (when rescheduling or if some instructions have been | |
6783 | removed by the call to purge_empty_blocks in sel_sched_region_1). */ | |
6784 | gcc_assert (cur_seqno >= 0); | |
e855c69d AB |
6785 | |
6786 | sbitmap_free (visited_bbs); | |
6787 | return sched_max_luid - 1; | |
6788 | } | |
6789 | ||
6790 | /* Initialize scheduling parameters for current region. */ | |
6791 | static void | |
6792 | sel_setup_region_sched_flags (void) | |
6793 | { | |
6794 | enable_schedule_as_rhs_p = 1; | |
6795 | bookkeeping_p = 1; | |
b8698a0f | 6796 | pipelining_p = (bookkeeping_p |
e855c69d | 6797 | && (flag_sel_sched_pipelining != 0) |
07643d76 AM |
6798 | && current_loop_nest != NULL |
6799 | && loop_has_exit_edges (current_loop_nest)); | |
e855c69d AB |
6800 | max_insns_to_rename = PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME); |
6801 | max_ws = MAX_WS; | |
6802 | } | |
6803 | ||
6804 | /* Return true if all basic blocks of current region are empty. */ | |
6805 | static bool | |
6806 | current_region_empty_p (void) | |
6807 | { | |
6808 | int i; | |
6809 | for (i = 0; i < current_nr_blocks; i++) | |
6810 | if (! sel_bb_empty_p (BASIC_BLOCK (BB_TO_BLOCK (i)))) | |
6811 | return false; | |
6812 | ||
6813 | return true; | |
6814 | } | |
6815 | ||
6816 | /* Prepare and verify loop nest for pipelining. */ | |
6817 | static void | |
ea4d630f | 6818 | setup_current_loop_nest (int rgn, bb_vec_t *bbs) |
e855c69d AB |
6819 | { |
6820 | current_loop_nest = get_loop_nest_for_rgn (rgn); | |
6821 | ||
6822 | if (!current_loop_nest) | |
6823 | return; | |
6824 | ||
6825 | /* If this loop has any saved loop preheaders from nested loops, | |
6826 | add these basic blocks to the current region. */ | |
ea4d630f | 6827 | sel_add_loop_preheaders (bbs); |
e855c69d AB |
6828 | |
6829 | /* Check that we're starting with a valid information. */ | |
6830 | gcc_assert (loop_latch_edge (current_loop_nest)); | |
6831 | gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest)); | |
6832 | } | |
6833 | ||
e855c69d AB |
6834 | /* Compute instruction priorities for current region. */ |
6835 | static void | |
6836 | sel_compute_priorities (int rgn) | |
6837 | { | |
6838 | sched_rgn_compute_dependencies (rgn); | |
6839 | ||
6840 | /* Compute insn priorities in haifa style. Then free haifa style | |
6841 | dependencies that we've calculated for this. */ | |
6842 | compute_priorities (); | |
6843 | ||
6844 | if (sched_verbose >= 5) | |
6845 | debug_rgn_dependencies (0); | |
6846 | ||
6847 | free_rgn_deps (); | |
6848 | } | |
6849 | ||
6850 | /* Init scheduling data for RGN. Returns true when this region should not | |
6851 | be scheduled. */ | |
6852 | static bool | |
6853 | sel_region_init (int rgn) | |
6854 | { | |
6855 | int i; | |
6856 | bb_vec_t bbs; | |
6857 | ||
6858 | rgn_setup_region (rgn); | |
6859 | ||
b8698a0f | 6860 | /* Even if sched_is_disabled_for_current_region_p() is true, we still |
e855c69d AB |
6861 | do region initialization here so the region can be bundled correctly, |
6862 | but we'll skip the scheduling in sel_sched_region (). */ | |
6863 | if (current_region_empty_p ()) | |
6864 | return true; | |
6865 | ||
e855c69d AB |
6866 | bbs = VEC_alloc (basic_block, heap, current_nr_blocks); |
6867 | ||
6868 | for (i = 0; i < current_nr_blocks; i++) | |
6869 | VEC_quick_push (basic_block, bbs, BASIC_BLOCK (BB_TO_BLOCK (i))); | |
6870 | ||
6871 | sel_init_bbs (bbs, NULL); | |
6872 | ||
ea4d630f AM |
6873 | if (flag_sel_sched_pipelining) |
6874 | setup_current_loop_nest (rgn, &bbs); | |
6875 | ||
9d40778b AM |
6876 | sel_setup_region_sched_flags (); |
6877 | ||
e855c69d AB |
6878 | /* Initialize luids and dependence analysis which both sel-sched and haifa |
6879 | need. */ | |
6880 | sched_init_luids (bbs, NULL, NULL, NULL); | |
6881 | sched_deps_init (false); | |
6882 | ||
6883 | /* Initialize haifa data. */ | |
6884 | rgn_setup_sched_infos (); | |
6885 | sel_set_sched_flags (); | |
6886 | haifa_init_h_i_d (bbs, NULL, NULL, NULL); | |
6887 | ||
6888 | sel_compute_priorities (rgn); | |
6889 | init_deps_global (); | |
6890 | ||
6891 | /* Main initialization. */ | |
6892 | sel_setup_sched_infos (); | |
6893 | sel_init_global_and_expr (bbs); | |
6894 | ||
6895 | VEC_free (basic_block, heap, bbs); | |
6896 | ||
6897 | blocks_to_reschedule = BITMAP_ALLOC (NULL); | |
6898 | ||
6899 | /* Init correct liveness sets on each instruction of a single-block loop. | |
6900 | This is the only situation when we can't update liveness when calling | |
6901 | compute_live for the first insn of the loop. */ | |
6902 | if (current_loop_nest) | |
6903 | { | |
6904 | int header = (sel_is_loop_preheader_p (BASIC_BLOCK (BB_TO_BLOCK (0))) | |
6905 | ? 1 | |
6906 | : 0); | |
6907 | ||
6908 | if (current_nr_blocks == header + 1) | |
b8698a0f | 6909 | update_liveness_on_insn |
e855c69d AB |
6910 | (sel_bb_head (BASIC_BLOCK (BB_TO_BLOCK (header)))); |
6911 | } | |
b8698a0f | 6912 | |
e855c69d AB |
6913 | /* Set hooks so that no newly generated insn will go out unnoticed. */ |
6914 | sel_register_cfg_hooks (); | |
6915 | ||
38f8b050 JR |
6916 | /* !!! We call target.sched.init () for the whole region, but we invoke |
6917 | targetm.sched.finish () for every ebb. */ | |
6918 | if (targetm.sched.init) | |
e855c69d | 6919 | /* None of the arguments are actually used in any target. */ |
38f8b050 | 6920 | targetm.sched.init (sched_dump, sched_verbose, -1); |
e855c69d AB |
6921 | |
6922 | first_emitted_uid = get_max_uid () + 1; | |
6923 | preheader_removed = false; | |
6924 | ||
6925 | /* Reset register allocation ticks array. */ | |
6926 | memset (reg_rename_tick, 0, sizeof reg_rename_tick); | |
6927 | reg_rename_this_tick = 0; | |
6928 | ||
6929 | bitmap_initialize (forced_ebb_heads, 0); | |
6930 | bitmap_clear (forced_ebb_heads); | |
6931 | ||
6932 | setup_nop_vinsn (); | |
6933 | current_copies = BITMAP_ALLOC (NULL); | |
6934 | current_originators = BITMAP_ALLOC (NULL); | |
6935 | code_motion_visited_blocks = BITMAP_ALLOC (NULL); | |
6936 | ||
6937 | return false; | |
6938 | } | |
6939 | ||
6940 | /* Simplify insns after the scheduling. */ | |
6941 | static void | |
6942 | simplify_changed_insns (void) | |
6943 | { | |
6944 | int i; | |
6945 | ||
6946 | for (i = 0; i < current_nr_blocks; i++) | |
6947 | { | |
6948 | basic_block bb = BASIC_BLOCK (BB_TO_BLOCK (i)); | |
6949 | rtx insn; | |
6950 | ||
6951 | FOR_BB_INSNS (bb, insn) | |
6952 | if (INSN_P (insn)) | |
6953 | { | |
6954 | expr_t expr = INSN_EXPR (insn); | |
6955 | ||
b8698a0f | 6956 | if (EXPR_WAS_SUBSTITUTED (expr)) |
e855c69d AB |
6957 | validate_simplify_insn (insn); |
6958 | } | |
6959 | } | |
6960 | } | |
6961 | ||
6962 | /* Find boundaries of the EBB starting from basic block BB, marking blocks of | |
6963 | this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL, | |
6964 | PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */ | |
6965 | static void | |
6966 | find_ebb_boundaries (basic_block bb, bitmap scheduled_blocks) | |
6967 | { | |
6968 | insn_t head, tail; | |
6969 | basic_block bb1 = bb; | |
6970 | if (sched_verbose >= 2) | |
6971 | sel_print ("Finishing schedule in bbs: "); | |
6972 | ||
6973 | do | |
6974 | { | |
6975 | bitmap_set_bit (scheduled_blocks, BLOCK_TO_BB (bb1->index)); | |
6976 | ||
6977 | if (sched_verbose >= 2) | |
6978 | sel_print ("%d; ", bb1->index); | |
6979 | } | |
6980 | while (!bb_ends_ebb_p (bb1) && (bb1 = bb_next_bb (bb1))); | |
6981 | ||
6982 | if (sched_verbose >= 2) | |
6983 | sel_print ("\n"); | |
6984 | ||
6985 | get_ebb_head_tail (bb, bb1, &head, &tail); | |
6986 | ||
6987 | current_sched_info->head = head; | |
6988 | current_sched_info->tail = tail; | |
6989 | current_sched_info->prev_head = PREV_INSN (head); | |
6990 | current_sched_info->next_tail = NEXT_INSN (tail); | |
6991 | } | |
6992 | ||
6993 | /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */ | |
6994 | static void | |
6995 | reset_sched_cycles_in_current_ebb (void) | |
6996 | { | |
6997 | int last_clock = 0; | |
6998 | int haifa_last_clock = -1; | |
6999 | int haifa_clock = 0; | |
06f0c25f | 7000 | int issued_insns = 0; |
e855c69d AB |
7001 | insn_t insn; |
7002 | ||
38f8b050 | 7003 | if (targetm.sched.init) |
e855c69d AB |
7004 | { |
7005 | /* None of the arguments are actually used in any target. | |
7006 | NB: We should have md_reset () hook for cases like this. */ | |
38f8b050 | 7007 | targetm.sched.init (sched_dump, sched_verbose, -1); |
e855c69d AB |
7008 | } |
7009 | ||
7010 | state_reset (curr_state); | |
7011 | advance_state (curr_state); | |
b8698a0f | 7012 | |
e855c69d AB |
7013 | for (insn = current_sched_info->head; |
7014 | insn != current_sched_info->next_tail; | |
7015 | insn = NEXT_INSN (insn)) | |
7016 | { | |
7017 | int cost, haifa_cost; | |
7018 | int sort_p; | |
9b0f04e7 | 7019 | bool asm_p, real_insn, after_stall, all_issued; |
e855c69d AB |
7020 | int clock; |
7021 | ||
7022 | if (!INSN_P (insn)) | |
7023 | continue; | |
7024 | ||
7025 | asm_p = false; | |
7026 | real_insn = recog_memoized (insn) >= 0; | |
7027 | clock = INSN_SCHED_CYCLE (insn); | |
7028 | ||
7029 | cost = clock - last_clock; | |
7030 | ||
7031 | /* Initialize HAIFA_COST. */ | |
7032 | if (! real_insn) | |
7033 | { | |
7034 | asm_p = INSN_ASM_P (insn); | |
7035 | ||
7036 | if (asm_p) | |
7037 | /* This is asm insn which *had* to be scheduled first | |
7038 | on the cycle. */ | |
7039 | haifa_cost = 1; | |
7040 | else | |
b8698a0f | 7041 | /* This is a use/clobber insn. It should not change |
e855c69d AB |
7042 | cost. */ |
7043 | haifa_cost = 0; | |
7044 | } | |
7045 | else | |
7046 | haifa_cost = estimate_insn_cost (insn, curr_state); | |
7047 | ||
7048 | /* Stall for whatever cycles we've stalled before. */ | |
7049 | after_stall = 0; | |
7050 | if (INSN_AFTER_STALL_P (insn) && cost > haifa_cost) | |
7051 | { | |
7052 | haifa_cost = cost; | |
7053 | after_stall = 1; | |
7054 | } | |
9b0f04e7 AB |
7055 | all_issued = issued_insns == issue_rate; |
7056 | if (haifa_cost == 0 && all_issued) | |
06f0c25f | 7057 | haifa_cost = 1; |
e855c69d AB |
7058 | if (haifa_cost > 0) |
7059 | { | |
7060 | int i = 0; | |
7061 | ||
7062 | while (haifa_cost--) | |
7063 | { | |
7064 | advance_state (curr_state); | |
06f0c25f | 7065 | issued_insns = 0; |
e855c69d AB |
7066 | i++; |
7067 | ||
7068 | if (sched_verbose >= 2) | |
7069 | { | |
7070 | sel_print ("advance_state (state_transition)\n"); | |
7071 | debug_state (curr_state); | |
7072 | } | |
7073 | ||
b8698a0f L |
7074 | /* The DFA may report that e.g. insn requires 2 cycles to be |
7075 | issued, but on the next cycle it says that insn is ready | |
e855c69d AB |
7076 | to go. Check this here. */ |
7077 | if (!after_stall | |
b8698a0f | 7078 | && real_insn |
e855c69d AB |
7079 | && haifa_cost > 0 |
7080 | && estimate_insn_cost (insn, curr_state) == 0) | |
7081 | break; | |
d7f672ec AB |
7082 | |
7083 | /* When the data dependency stall is longer than the DFA stall, | |
9b0f04e7 AB |
7084 | and when we have issued exactly issue_rate insns and stalled, |
7085 | it could be that after this longer stall the insn will again | |
d7f672ec AB |
7086 | become unavailable to the DFA restrictions. Looks strange |
7087 | but happens e.g. on x86-64. So recheck DFA on the last | |
7088 | iteration. */ | |
9b0f04e7 | 7089 | if ((after_stall || all_issued) |
d7f672ec AB |
7090 | && real_insn |
7091 | && haifa_cost == 0) | |
7092 | haifa_cost = estimate_insn_cost (insn, curr_state); | |
7093 | } | |
e855c69d AB |
7094 | |
7095 | haifa_clock += i; | |
06f0c25f AB |
7096 | if (sched_verbose >= 2) |
7097 | sel_print ("haifa clock: %d\n", haifa_clock); | |
e855c69d AB |
7098 | } |
7099 | else | |
7100 | gcc_assert (haifa_cost == 0); | |
7101 | ||
7102 | if (sched_verbose >= 2) | |
7103 | sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn), haifa_cost); | |
7104 | ||
7105 | if (targetm.sched.dfa_new_cycle) | |
7106 | while (targetm.sched.dfa_new_cycle (sched_dump, sched_verbose, insn, | |
7107 | haifa_last_clock, haifa_clock, | |
7108 | &sort_p)) | |
7109 | { | |
7110 | advance_state (curr_state); | |
06f0c25f | 7111 | issued_insns = 0; |
e855c69d AB |
7112 | haifa_clock++; |
7113 | if (sched_verbose >= 2) | |
7114 | { | |
7115 | sel_print ("advance_state (dfa_new_cycle)\n"); | |
7116 | debug_state (curr_state); | |
06f0c25f | 7117 | sel_print ("haifa clock: %d\n", haifa_clock + 1); |
e855c69d AB |
7118 | } |
7119 | } | |
7120 | ||
7121 | if (real_insn) | |
7122 | { | |
7123 | cost = state_transition (curr_state, insn); | |
06f0c25f | 7124 | issued_insns++; |
e855c69d AB |
7125 | |
7126 | if (sched_verbose >= 2) | |
06f0c25f AB |
7127 | { |
7128 | sel_print ("scheduled insn %d, clock %d\n", INSN_UID (insn), | |
7129 | haifa_clock + 1); | |
7130 | debug_state (curr_state); | |
7131 | } | |
e855c69d AB |
7132 | gcc_assert (cost < 0); |
7133 | } | |
7134 | ||
7135 | if (targetm.sched.variable_issue) | |
7136 | targetm.sched.variable_issue (sched_dump, sched_verbose, insn, 0); | |
7137 | ||
7138 | INSN_SCHED_CYCLE (insn) = haifa_clock; | |
7139 | ||
7140 | last_clock = clock; | |
7141 | haifa_last_clock = haifa_clock; | |
7142 | } | |
7143 | } | |
7144 | ||
7145 | /* Put TImode markers on insns starting a new issue group. */ | |
7146 | static void | |
7147 | put_TImodes (void) | |
7148 | { | |
7149 | int last_clock = -1; | |
7150 | insn_t insn; | |
7151 | ||
7152 | for (insn = current_sched_info->head; insn != current_sched_info->next_tail; | |
7153 | insn = NEXT_INSN (insn)) | |
7154 | { | |
7155 | int cost, clock; | |
7156 | ||
7157 | if (!INSN_P (insn)) | |
7158 | continue; | |
7159 | ||
7160 | clock = INSN_SCHED_CYCLE (insn); | |
7161 | cost = (last_clock == -1) ? 1 : clock - last_clock; | |
7162 | ||
7163 | gcc_assert (cost >= 0); | |
7164 | ||
7165 | if (issue_rate > 1 | |
7166 | && GET_CODE (PATTERN (insn)) != USE | |
7167 | && GET_CODE (PATTERN (insn)) != CLOBBER) | |
7168 | { | |
7169 | if (reload_completed && cost > 0) | |
7170 | PUT_MODE (insn, TImode); | |
7171 | ||
7172 | last_clock = clock; | |
7173 | } | |
7174 | ||
7175 | if (sched_verbose >= 2) | |
7176 | sel_print ("Cost for insn %d is %d\n", INSN_UID (insn), cost); | |
7177 | } | |
7178 | } | |
7179 | ||
b8698a0f | 7180 | /* Perform MD_FINISH on EBBs comprising current region. When |
e855c69d AB |
7181 | RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler |
7182 | to produce correct sched cycles on insns. */ | |
7183 | static void | |
7184 | sel_region_target_finish (bool reset_sched_cycles_p) | |
7185 | { | |
7186 | int i; | |
7187 | bitmap scheduled_blocks = BITMAP_ALLOC (NULL); | |
7188 | ||
7189 | for (i = 0; i < current_nr_blocks; i++) | |
7190 | { | |
7191 | if (bitmap_bit_p (scheduled_blocks, i)) | |
7192 | continue; | |
7193 | ||
7194 | /* While pipelining outer loops, skip bundling for loop | |
7195 | preheaders. Those will be rescheduled in the outer loop. */ | |
7196 | if (sel_is_loop_preheader_p (EBB_FIRST_BB (i))) | |
7197 | continue; | |
7198 | ||
7199 | find_ebb_boundaries (EBB_FIRST_BB (i), scheduled_blocks); | |
7200 | ||
7201 | if (no_real_insns_p (current_sched_info->head, current_sched_info->tail)) | |
7202 | continue; | |
7203 | ||
7204 | if (reset_sched_cycles_p) | |
7205 | reset_sched_cycles_in_current_ebb (); | |
7206 | ||
38f8b050 JR |
7207 | if (targetm.sched.init) |
7208 | targetm.sched.init (sched_dump, sched_verbose, -1); | |
e855c69d AB |
7209 | |
7210 | put_TImodes (); | |
7211 | ||
38f8b050 | 7212 | if (targetm.sched.finish) |
e855c69d | 7213 | { |
38f8b050 | 7214 | targetm.sched.finish (sched_dump, sched_verbose); |
e855c69d AB |
7215 | |
7216 | /* Extend luids so that insns generated by the target will | |
7217 | get zero luid. */ | |
7218 | sched_init_luids (NULL, NULL, NULL, NULL); | |
7219 | } | |
7220 | } | |
7221 | ||
7222 | BITMAP_FREE (scheduled_blocks); | |
7223 | } | |
7224 | ||
7225 | /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P | |
b8698a0f | 7226 | is true, make an additional pass emulating scheduler to get correct insn |
e855c69d AB |
7227 | cycles for md_finish calls. */ |
7228 | static void | |
7229 | sel_region_finish (bool reset_sched_cycles_p) | |
7230 | { | |
7231 | simplify_changed_insns (); | |
7232 | sched_finish_ready_list (); | |
7233 | free_nop_pool (); | |
7234 | ||
7235 | /* Free the vectors. */ | |
7236 | if (vec_av_set) | |
7237 | VEC_free (expr_t, heap, vec_av_set); | |
7238 | BITMAP_FREE (current_copies); | |
7239 | BITMAP_FREE (current_originators); | |
7240 | BITMAP_FREE (code_motion_visited_blocks); | |
7241 | vinsn_vec_free (&vec_bookkeeping_blocked_vinsns); | |
7242 | vinsn_vec_free (&vec_target_unavailable_vinsns); | |
7243 | ||
7244 | /* If LV_SET of the region head should be updated, do it now because | |
7245 | there will be no other chance. */ | |
7246 | { | |
7247 | succ_iterator si; | |
7248 | insn_t insn; | |
7249 | ||
7250 | FOR_EACH_SUCC_1 (insn, si, bb_note (EBB_FIRST_BB (0)), | |
7251 | SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS) | |
7252 | { | |
7253 | basic_block bb = BLOCK_FOR_INSN (insn); | |
7254 | ||
7255 | if (!BB_LV_SET_VALID_P (bb)) | |
7256 | compute_live (insn); | |
7257 | } | |
7258 | } | |
7259 | ||
7260 | /* Emulate the Haifa scheduler for bundling. */ | |
7261 | if (reload_completed) | |
7262 | sel_region_target_finish (reset_sched_cycles_p); | |
7263 | ||
7264 | sel_finish_global_and_expr (); | |
7265 | ||
7266 | bitmap_clear (forced_ebb_heads); | |
7267 | ||
7268 | free_nop_vinsn (); | |
7269 | ||
7270 | finish_deps_global (); | |
7271 | sched_finish_luids (); | |
7272 | ||
7273 | sel_finish_bbs (); | |
7274 | BITMAP_FREE (blocks_to_reschedule); | |
7275 | ||
7276 | sel_unregister_cfg_hooks (); | |
7277 | ||
7278 | max_issue_size = 0; | |
7279 | } | |
7280 | \f | |
7281 | ||
7282 | /* Functions that implement the scheduler driver. */ | |
7283 | ||
7284 | /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO | |
7285 | is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list | |
7286 | of insns scheduled -- these would be postprocessed later. */ | |
7287 | static void | |
7288 | schedule_on_fences (flist_t fences, int max_seqno, | |
7289 | ilist_t **scheduled_insns_tailpp) | |
7290 | { | |
7291 | flist_t old_fences = fences; | |
7292 | ||
7293 | if (sched_verbose >= 1) | |
7294 | { | |
7295 | sel_print ("\nScheduling on fences: "); | |
7296 | dump_flist (fences); | |
7297 | sel_print ("\n"); | |
7298 | } | |
7299 | ||
7300 | scheduled_something_on_previous_fence = false; | |
7301 | for (; fences; fences = FLIST_NEXT (fences)) | |
7302 | { | |
7303 | fence_t fence = NULL; | |
7304 | int seqno = 0; | |
7305 | flist_t fences2; | |
7306 | bool first_p = true; | |
b8698a0f | 7307 | |
e855c69d AB |
7308 | /* Choose the next fence group to schedule. |
7309 | The fact that insn can be scheduled only once | |
7310 | on the cycle is guaranteed by two properties: | |
7311 | 1. seqnos of parallel groups decrease with each iteration. | |
7312 | 2. If is_ineligible_successor () sees the larger seqno, it | |
7313 | checks if candidate insn is_in_current_fence_p (). */ | |
7314 | for (fences2 = old_fences; fences2; fences2 = FLIST_NEXT (fences2)) | |
7315 | { | |
7316 | fence_t f = FLIST_FENCE (fences2); | |
7317 | ||
7318 | if (!FENCE_PROCESSED_P (f)) | |
7319 | { | |
7320 | int i = INSN_SEQNO (FENCE_INSN (f)); | |
7321 | ||
7322 | if (first_p || i > seqno) | |
7323 | { | |
7324 | seqno = i; | |
7325 | fence = f; | |
7326 | first_p = false; | |
7327 | } | |
7328 | else | |
7329 | /* ??? Seqnos of different groups should be different. */ | |
7330 | gcc_assert (1 || i != seqno); | |
7331 | } | |
7332 | } | |
7333 | ||
7334 | gcc_assert (fence); | |
7335 | ||
7336 | /* As FENCE is nonnull, SEQNO is initialized. */ | |
7337 | seqno -= max_seqno + 1; | |
7338 | fill_insns (fence, seqno, scheduled_insns_tailpp); | |
7339 | FENCE_PROCESSED_P (fence) = true; | |
7340 | } | |
7341 | ||
7342 | /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we | |
b8698a0f | 7343 | don't need to keep bookkeeping-invalidated and target-unavailable |
e855c69d AB |
7344 | vinsns any more. */ |
7345 | vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns); | |
7346 | vinsn_vec_clear (&vec_target_unavailable_vinsns); | |
7347 | } | |
7348 | ||
7349 | /* Calculate MIN_SEQNO and MAX_SEQNO. */ | |
7350 | static void | |
7351 | find_min_max_seqno (flist_t fences, int *min_seqno, int *max_seqno) | |
7352 | { | |
7353 | *min_seqno = *max_seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences))); | |
7354 | ||
7355 | /* The first element is already processed. */ | |
7356 | while ((fences = FLIST_NEXT (fences))) | |
7357 | { | |
7358 | int seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences))); | |
b8698a0f | 7359 | |
e855c69d AB |
7360 | if (*min_seqno > seqno) |
7361 | *min_seqno = seqno; | |
7362 | else if (*max_seqno < seqno) | |
7363 | *max_seqno = seqno; | |
7364 | } | |
7365 | } | |
7366 | ||
7367 | /* Calculate new fences from FENCES. */ | |
b8698a0f | 7368 | static flist_t |
e855c69d AB |
7369 | calculate_new_fences (flist_t fences, int orig_max_seqno) |
7370 | { | |
7371 | flist_t old_fences = fences; | |
7372 | struct flist_tail_def _new_fences, *new_fences = &_new_fences; | |
7373 | ||
7374 | flist_tail_init (new_fences); | |
7375 | for (; fences; fences = FLIST_NEXT (fences)) | |
7376 | { | |
7377 | fence_t fence = FLIST_FENCE (fences); | |
7378 | insn_t insn; | |
b8698a0f | 7379 | |
e855c69d AB |
7380 | if (!FENCE_BNDS (fence)) |
7381 | { | |
7382 | /* This fence doesn't have any successors. */ | |
7383 | if (!FENCE_SCHEDULED_P (fence)) | |
7384 | { | |
7385 | /* Nothing was scheduled on this fence. */ | |
7386 | int seqno; | |
7387 | ||
7388 | insn = FENCE_INSN (fence); | |
7389 | seqno = INSN_SEQNO (insn); | |
7390 | gcc_assert (seqno > 0 && seqno <= orig_max_seqno); | |
7391 | ||
7392 | if (sched_verbose >= 1) | |
b8698a0f | 7393 | sel_print ("Fence %d[%d] has not changed\n", |
e855c69d AB |
7394 | INSN_UID (insn), |
7395 | BLOCK_NUM (insn)); | |
7396 | move_fence_to_fences (fences, new_fences); | |
7397 | } | |
7398 | } | |
7399 | else | |
7400 | extract_new_fences_from (fences, new_fences, orig_max_seqno); | |
7401 | } | |
7402 | ||
7403 | flist_clear (&old_fences); | |
7404 | return FLIST_TAIL_HEAD (new_fences); | |
7405 | } | |
7406 | ||
7407 | /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO | |
7408 | are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is | |
7409 | the highest seqno used in a region. Return the updated highest seqno. */ | |
7410 | static int | |
b8698a0f L |
7411 | update_seqnos_and_stage (int min_seqno, int max_seqno, |
7412 | int highest_seqno_in_use, | |
e855c69d AB |
7413 | ilist_t *pscheduled_insns) |
7414 | { | |
7415 | int new_hs; | |
7416 | ilist_iterator ii; | |
7417 | insn_t insn; | |
b8698a0f | 7418 | |
e855c69d AB |
7419 | /* Actually, new_hs is the seqno of the instruction, that was |
7420 | scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */ | |
7421 | if (*pscheduled_insns) | |
7422 | { | |
7423 | new_hs = (INSN_SEQNO (ILIST_INSN (*pscheduled_insns)) | |
7424 | + highest_seqno_in_use + max_seqno - min_seqno + 2); | |
7425 | gcc_assert (new_hs > highest_seqno_in_use); | |
7426 | } | |
7427 | else | |
7428 | new_hs = highest_seqno_in_use; | |
7429 | ||
7430 | FOR_EACH_INSN (insn, ii, *pscheduled_insns) | |
7431 | { | |
7432 | gcc_assert (INSN_SEQNO (insn) < 0); | |
7433 | INSN_SEQNO (insn) += highest_seqno_in_use + max_seqno - min_seqno + 2; | |
7434 | gcc_assert (INSN_SEQNO (insn) <= new_hs); | |
bcf33775 AB |
7435 | |
7436 | /* When not pipelining, purge unneeded insn info on the scheduled insns. | |
7437 | For example, having reg_last array of INSN_DEPS_CONTEXT in memory may | |
7438 | require > 1GB of memory e.g. on limit-fnargs.c. */ | |
7439 | if (! pipelining_p) | |
7440 | free_data_for_scheduled_insn (insn); | |
e855c69d AB |
7441 | } |
7442 | ||
7443 | ilist_clear (pscheduled_insns); | |
7444 | global_level++; | |
7445 | ||
7446 | return new_hs; | |
7447 | } | |
7448 | ||
b8698a0f L |
7449 | /* The main driver for scheduling a region. This function is responsible |
7450 | for correct propagation of fences (i.e. scheduling points) and creating | |
7451 | a group of parallel insns at each of them. It also supports | |
e855c69d AB |
7452 | pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass |
7453 | of scheduling. */ | |
7454 | static void | |
7455 | sel_sched_region_2 (int orig_max_seqno) | |
7456 | { | |
7457 | int highest_seqno_in_use = orig_max_seqno; | |
7458 | ||
7459 | stat_bookkeeping_copies = 0; | |
7460 | stat_insns_needed_bookkeeping = 0; | |
7461 | stat_renamed_scheduled = 0; | |
7462 | stat_substitutions_total = 0; | |
7463 | num_insns_scheduled = 0; | |
7464 | ||
7465 | while (fences) | |
7466 | { | |
7467 | int min_seqno, max_seqno; | |
7468 | ilist_t scheduled_insns = NULL; | |
7469 | ilist_t *scheduled_insns_tailp = &scheduled_insns; | |
7470 | ||
7471 | find_min_max_seqno (fences, &min_seqno, &max_seqno); | |
7472 | schedule_on_fences (fences, max_seqno, &scheduled_insns_tailp); | |
7473 | fences = calculate_new_fences (fences, orig_max_seqno); | |
7474 | highest_seqno_in_use = update_seqnos_and_stage (min_seqno, max_seqno, | |
7475 | highest_seqno_in_use, | |
7476 | &scheduled_insns); | |
7477 | } | |
7478 | ||
7479 | if (sched_verbose >= 1) | |
7480 | sel_print ("Scheduled %d bookkeeping copies, %d insns needed " | |
7481 | "bookkeeping, %d insns renamed, %d insns substituted\n", | |
7482 | stat_bookkeeping_copies, | |
7483 | stat_insns_needed_bookkeeping, | |
7484 | stat_renamed_scheduled, | |
7485 | stat_substitutions_total); | |
7486 | } | |
7487 | ||
b8698a0f L |
7488 | /* Schedule a region. When pipelining, search for possibly never scheduled |
7489 | bookkeeping code and schedule it. Reschedule pipelined code without | |
e855c69d AB |
7490 | pipelining after. */ |
7491 | static void | |
7492 | sel_sched_region_1 (void) | |
7493 | { | |
e855c69d AB |
7494 | int orig_max_seqno; |
7495 | ||
1f3b2b4e | 7496 | /* Remove empty blocks that might be in the region from the beginning. */ |
e855c69d AB |
7497 | purge_empty_blocks (); |
7498 | ||
1f3b2b4e | 7499 | orig_max_seqno = init_seqno (NULL, NULL); |
e855c69d AB |
7500 | gcc_assert (orig_max_seqno >= 1); |
7501 | ||
7502 | /* When pipelining outer loops, create fences on the loop header, | |
7503 | not preheader. */ | |
7504 | fences = NULL; | |
7505 | if (current_loop_nest) | |
7506 | init_fences (BB_END (EBB_FIRST_BB (0))); | |
7507 | else | |
7508 | init_fences (bb_note (EBB_FIRST_BB (0))); | |
7509 | global_level = 1; | |
7510 | ||
7511 | sel_sched_region_2 (orig_max_seqno); | |
7512 | ||
7513 | gcc_assert (fences == NULL); | |
7514 | ||
7515 | if (pipelining_p) | |
7516 | { | |
7517 | int i; | |
7518 | basic_block bb; | |
7519 | struct flist_tail_def _new_fences; | |
7520 | flist_tail_t new_fences = &_new_fences; | |
7521 | bool do_p = true; | |
7522 | ||
7523 | pipelining_p = false; | |
7524 | max_ws = MIN (max_ws, issue_rate * 3 / 2); | |
7525 | bookkeeping_p = false; | |
7526 | enable_schedule_as_rhs_p = false; | |
7527 | ||
7528 | /* Schedule newly created code, that has not been scheduled yet. */ | |
7529 | do_p = true; | |
7530 | ||
7531 | while (do_p) | |
7532 | { | |
7533 | do_p = false; | |
7534 | ||
7535 | for (i = 0; i < current_nr_blocks; i++) | |
7536 | { | |
7537 | basic_block bb = EBB_FIRST_BB (i); | |
7538 | ||
e855c69d AB |
7539 | if (bitmap_bit_p (blocks_to_reschedule, bb->index)) |
7540 | { | |
d7f672ec AB |
7541 | if (! bb_ends_ebb_p (bb)) |
7542 | bitmap_set_bit (blocks_to_reschedule, bb_next_bb (bb)->index); | |
7543 | if (sel_bb_empty_p (bb)) | |
7544 | { | |
7545 | bitmap_clear_bit (blocks_to_reschedule, bb->index); | |
7546 | continue; | |
7547 | } | |
e855c69d AB |
7548 | clear_outdated_rtx_info (bb); |
7549 | if (sel_insn_is_speculation_check (BB_END (bb)) | |
7550 | && JUMP_P (BB_END (bb))) | |
7551 | bitmap_set_bit (blocks_to_reschedule, | |
7552 | BRANCH_EDGE (bb)->dest->index); | |
7553 | } | |
d7f672ec AB |
7554 | else if (! sel_bb_empty_p (bb) |
7555 | && INSN_SCHED_TIMES (sel_bb_head (bb)) <= 0) | |
e855c69d AB |
7556 | bitmap_set_bit (blocks_to_reschedule, bb->index); |
7557 | } | |
7558 | ||
7559 | for (i = 0; i < current_nr_blocks; i++) | |
7560 | { | |
7561 | bb = EBB_FIRST_BB (i); | |
7562 | ||
b8698a0f | 7563 | /* While pipelining outer loops, skip bundling for loop |
e855c69d AB |
7564 | preheaders. Those will be rescheduled in the outer |
7565 | loop. */ | |
7566 | if (sel_is_loop_preheader_p (bb)) | |
7567 | { | |
7568 | clear_outdated_rtx_info (bb); | |
7569 | continue; | |
7570 | } | |
b8698a0f | 7571 | |
06f0c25f | 7572 | if (bitmap_bit_p (blocks_to_reschedule, bb->index)) |
e855c69d AB |
7573 | { |
7574 | flist_tail_init (new_fences); | |
7575 | ||
1f3b2b4e | 7576 | orig_max_seqno = init_seqno (blocks_to_reschedule, bb); |
e855c69d AB |
7577 | |
7578 | /* Mark BB as head of the new ebb. */ | |
7579 | bitmap_set_bit (forced_ebb_heads, bb->index); | |
7580 | ||
e855c69d AB |
7581 | gcc_assert (fences == NULL); |
7582 | ||
7583 | init_fences (bb_note (bb)); | |
b8698a0f | 7584 | |
e855c69d | 7585 | sel_sched_region_2 (orig_max_seqno); |
b8698a0f | 7586 | |
e855c69d AB |
7587 | do_p = true; |
7588 | break; | |
7589 | } | |
7590 | } | |
7591 | } | |
7592 | } | |
7593 | } | |
7594 | ||
7595 | /* Schedule the RGN region. */ | |
7596 | void | |
7597 | sel_sched_region (int rgn) | |
7598 | { | |
7599 | bool schedule_p; | |
7600 | bool reset_sched_cycles_p; | |
7601 | ||
7602 | if (sel_region_init (rgn)) | |
7603 | return; | |
7604 | ||
7605 | if (sched_verbose >= 1) | |
7606 | sel_print ("Scheduling region %d\n", rgn); | |
7607 | ||
7608 | schedule_p = (!sched_is_disabled_for_current_region_p () | |
7609 | && dbg_cnt (sel_sched_region_cnt)); | |
7610 | reset_sched_cycles_p = pipelining_p; | |
7611 | if (schedule_p) | |
7612 | sel_sched_region_1 (); | |
7613 | else | |
7614 | /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */ | |
7615 | reset_sched_cycles_p = true; | |
b8698a0f | 7616 | |
e855c69d AB |
7617 | sel_region_finish (reset_sched_cycles_p); |
7618 | } | |
7619 | ||
7620 | /* Perform global init for the scheduler. */ | |
7621 | static void | |
7622 | sel_global_init (void) | |
7623 | { | |
7624 | calculate_dominance_info (CDI_DOMINATORS); | |
7625 | alloc_sched_pools (); | |
7626 | ||
7627 | /* Setup the infos for sched_init. */ | |
7628 | sel_setup_sched_infos (); | |
7629 | setup_sched_dump (); | |
7630 | ||
7631 | sched_rgn_init (false); | |
7632 | sched_init (); | |
7633 | ||
7634 | sched_init_bbs (); | |
7635 | /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */ | |
7636 | after_recovery = 0; | |
b8698a0f | 7637 | can_issue_more = issue_rate; |
e855c69d AB |
7638 | |
7639 | sched_extend_target (); | |
7640 | sched_deps_init (true); | |
7641 | setup_nop_and_exit_insns (); | |
7642 | sel_extend_global_bb_info (); | |
7643 | init_lv_sets (); | |
7644 | init_hard_regs_data (); | |
7645 | } | |
7646 | ||
7647 | /* Free the global data of the scheduler. */ | |
7648 | static void | |
7649 | sel_global_finish (void) | |
7650 | { | |
7651 | free_bb_note_pool (); | |
7652 | free_lv_sets (); | |
7653 | sel_finish_global_bb_info (); | |
7654 | ||
7655 | free_regset_pool (); | |
7656 | free_nop_and_exit_insns (); | |
7657 | ||
7658 | sched_rgn_finish (); | |
7659 | sched_deps_finish (); | |
7660 | sched_finish (); | |
7661 | ||
7662 | if (current_loops) | |
7663 | sel_finish_pipelining (); | |
7664 | ||
7665 | free_sched_pools (); | |
7666 | free_dominance_info (CDI_DOMINATORS); | |
7667 | } | |
7668 | ||
7669 | /* Return true when we need to skip selective scheduling. Used for debugging. */ | |
7670 | bool | |
7671 | maybe_skip_selective_scheduling (void) | |
7672 | { | |
7673 | return ! dbg_cnt (sel_sched_cnt); | |
7674 | } | |
7675 | ||
7676 | /* The entry point. */ | |
7677 | void | |
7678 | run_selective_scheduling (void) | |
7679 | { | |
7680 | int rgn; | |
7681 | ||
7682 | if (n_basic_blocks == NUM_FIXED_BLOCKS) | |
7683 | return; | |
7684 | ||
7685 | sel_global_init (); | |
7686 | ||
7687 | for (rgn = 0; rgn < nr_regions; rgn++) | |
7688 | sel_sched_region (rgn); | |
7689 | ||
7690 | sel_global_finish (); | |
7691 | } | |
7692 | ||
7693 | #endif |