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df35c271 | 1 | /* Store motion via Lazy Code Motion on the reverse CFG. |
818ab71a | 2 | Copyright (C) 1997-2016 Free Software Foundation, Inc. |
df35c271 SB |
3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify it under | |
7 | the terms of the GNU General Public License as published by the Free | |
8 | Software Foundation; either version 3, or (at your option) any later | |
9 | version. | |
10 | ||
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GCC; see the file COPYING3. If not see | |
18 | <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "config.h" | |
21 | #include "system.h" | |
22 | #include "coretypes.h" | |
c7131fb2 | 23 | #include "backend.h" |
c7131fb2 | 24 | #include "rtl.h" |
957060b5 AM |
25 | #include "tree.h" |
26 | #include "predict.h" | |
c7131fb2 | 27 | #include "df.h" |
df35c271 SB |
28 | #include "toplev.h" |
29 | ||
60393bbc AM |
30 | #include "cfgrtl.h" |
31 | #include "cfganal.h" | |
32 | #include "lcm.h" | |
33 | #include "cfgcleanup.h" | |
df35c271 | 34 | #include "expr.h" |
df35c271 | 35 | #include "tree-pass.h" |
df35c271 | 36 | #include "dbgcnt.h" |
638e18a4 | 37 | #include "rtl-iter.h" |
df35c271 | 38 | |
6c5d4d1a SB |
39 | /* This pass implements downward store motion. |
40 | As of May 1, 2009, the pass is not enabled by default on any target, | |
41 | but bootstrap completes on ia64 and x86_64 with the pass enabled. */ | |
42 | ||
43 | /* TODO: | |
44 | - remove_reachable_equiv_notes is an incomprehensible pile of goo and | |
45 | a compile time hog that needs a rewrite (maybe cache st_exprs to | |
46 | invalidate REG_EQUAL/REG_EQUIV notes for?). | |
47 | - pattern_regs in st_expr should be a regset (on its own obstack). | |
48 | - antic_stores and avail_stores should be VECs instead of lists. | |
9771b263 | 49 | - store_motion_mems should be a vec instead of a list. |
6c5d4d1a SB |
50 | - there should be an alloc pool for struct st_expr objects. |
51 | - investigate whether it is helpful to make the address of an st_expr | |
52 | a cselib VALUE. | |
53 | - when GIMPLE alias information is exported, the effectiveness of this | |
54 | pass should be re-evaluated. | |
55 | */ | |
56 | ||
57 | /* This is a list of store expressions (MEMs). The structure is used | |
58 | as an expression table to track stores which look interesting, and | |
59 | might be moveable towards the exit block. */ | |
60 | ||
61 | struct st_expr | |
df35c271 | 62 | { |
6c5d4d1a SB |
63 | /* Pattern of this mem. */ |
64 | rtx pattern; | |
65 | /* List of registers mentioned by the mem. */ | |
66 | rtx pattern_regs; | |
67 | /* INSN list of stores that are locally anticipatable. */ | |
3dc99c19 | 68 | rtx_insn_list *antic_stores; |
6c5d4d1a | 69 | /* INSN list of stores that are locally available. */ |
3dc99c19 | 70 | rtx_insn_list *avail_stores; |
6c5d4d1a SB |
71 | /* Next in the list. */ |
72 | struct st_expr * next; | |
73 | /* Store ID in the dataflow bitmaps. */ | |
74 | int index; | |
75 | /* Hash value for the hash table. */ | |
76 | unsigned int hash_index; | |
77 | /* Register holding the stored expression when a store is moved. | |
78 | This field is also used as a cache in find_moveable_store, see | |
79 | LAST_AVAIL_CHECK_FAILURE below. */ | |
80 | rtx reaching_reg; | |
df35c271 SB |
81 | }; |
82 | ||
83 | /* Head of the list of load/store memory refs. */ | |
6c5d4d1a | 84 | static struct st_expr * store_motion_mems = NULL; |
df35c271 | 85 | |
6c5d4d1a SB |
86 | /* These bitmaps will hold the local dataflow properties per basic block. */ |
87 | static sbitmap *st_kill, *st_avloc, *st_antloc, *st_transp; | |
df35c271 SB |
88 | |
89 | /* Nonzero for expressions which should be inserted on a specific edge. */ | |
6c5d4d1a | 90 | static sbitmap *st_insert_map; |
df35c271 SB |
91 | |
92 | /* Nonzero for expressions which should be deleted in a specific block. */ | |
6c5d4d1a SB |
93 | static sbitmap *st_delete_map; |
94 | ||
95 | /* Global holding the number of store expressions we are dealing with. */ | |
96 | static int num_stores; | |
df35c271 SB |
97 | |
98 | /* Contains the edge_list returned by pre_edge_lcm. */ | |
99 | static struct edge_list *edge_list; | |
100 | ||
4a8fb1a1 LC |
101 | /* Hashtable helpers. */ |
102 | ||
8d67ee55 | 103 | struct st_expr_hasher : nofree_ptr_hash <st_expr> |
4a8fb1a1 | 104 | { |
67f58944 TS |
105 | static inline hashval_t hash (const st_expr *); |
106 | static inline bool equal (const st_expr *, const st_expr *); | |
4a8fb1a1 LC |
107 | }; |
108 | ||
109 | inline hashval_t | |
67f58944 | 110 | st_expr_hasher::hash (const st_expr *x) |
df35c271 SB |
111 | { |
112 | int do_not_record_p = 0; | |
df35c271 SB |
113 | return hash_rtx (x->pattern, GET_MODE (x->pattern), &do_not_record_p, NULL, false); |
114 | } | |
115 | ||
4a8fb1a1 | 116 | inline bool |
67f58944 | 117 | st_expr_hasher::equal (const st_expr *ptr1, const st_expr *ptr2) |
df35c271 | 118 | { |
df35c271 SB |
119 | return exp_equiv_p (ptr1->pattern, ptr2->pattern, 0, true); |
120 | } | |
121 | ||
4a8fb1a1 | 122 | /* Hashtable for the load/store memory refs. */ |
c203e8a7 | 123 | static hash_table<st_expr_hasher> *store_motion_mems_table; |
4a8fb1a1 | 124 | |
6c5d4d1a | 125 | /* This will search the st_expr list for a matching expression. If it |
df35c271 SB |
126 | doesn't find one, we create one and initialize it. */ |
127 | ||
6c5d4d1a SB |
128 | static struct st_expr * |
129 | st_expr_entry (rtx x) | |
df35c271 SB |
130 | { |
131 | int do_not_record_p = 0; | |
6c5d4d1a | 132 | struct st_expr * ptr; |
df35c271 | 133 | unsigned int hash; |
4a8fb1a1 | 134 | st_expr **slot; |
6c5d4d1a | 135 | struct st_expr e; |
df35c271 SB |
136 | |
137 | hash = hash_rtx (x, GET_MODE (x), &do_not_record_p, | |
138 | NULL, /*have_reg_qty=*/false); | |
139 | ||
140 | e.pattern = x; | |
c203e8a7 | 141 | slot = store_motion_mems_table->find_slot_with_hash (&e, hash, INSERT); |
df35c271 | 142 | if (*slot) |
4a8fb1a1 | 143 | return *slot; |
df35c271 | 144 | |
6c5d4d1a | 145 | ptr = XNEW (struct st_expr); |
df35c271 | 146 | |
6c5d4d1a | 147 | ptr->next = store_motion_mems; |
df35c271 SB |
148 | ptr->pattern = x; |
149 | ptr->pattern_regs = NULL_RTX; | |
3dc99c19 DM |
150 | ptr->antic_stores = NULL; |
151 | ptr->avail_stores = NULL; | |
df35c271 | 152 | ptr->reaching_reg = NULL_RTX; |
df35c271 SB |
153 | ptr->index = 0; |
154 | ptr->hash_index = hash; | |
6c5d4d1a | 155 | store_motion_mems = ptr; |
df35c271 SB |
156 | *slot = ptr; |
157 | ||
158 | return ptr; | |
159 | } | |
160 | ||
6c5d4d1a | 161 | /* Free up an individual st_expr entry. */ |
df35c271 SB |
162 | |
163 | static void | |
6c5d4d1a | 164 | free_st_expr_entry (struct st_expr * ptr) |
df35c271 | 165 | { |
6c5d4d1a SB |
166 | free_INSN_LIST_list (& ptr->antic_stores); |
167 | free_INSN_LIST_list (& ptr->avail_stores); | |
df35c271 SB |
168 | |
169 | free (ptr); | |
170 | } | |
171 | ||
6c5d4d1a | 172 | /* Free up all memory associated with the st_expr list. */ |
df35c271 SB |
173 | |
174 | static void | |
6c5d4d1a | 175 | free_store_motion_mems (void) |
df35c271 | 176 | { |
c203e8a7 TS |
177 | delete store_motion_mems_table; |
178 | store_motion_mems_table = NULL; | |
df35c271 | 179 | |
6c5d4d1a | 180 | while (store_motion_mems) |
df35c271 | 181 | { |
6c5d4d1a SB |
182 | struct st_expr * tmp = store_motion_mems; |
183 | store_motion_mems = store_motion_mems->next; | |
184 | free_st_expr_entry (tmp); | |
df35c271 | 185 | } |
6c5d4d1a | 186 | store_motion_mems = NULL; |
df35c271 SB |
187 | } |
188 | ||
189 | /* Assign each element of the list of mems a monotonically increasing value. */ | |
190 | ||
191 | static int | |
6c5d4d1a | 192 | enumerate_store_motion_mems (void) |
df35c271 | 193 | { |
6c5d4d1a | 194 | struct st_expr * ptr; |
df35c271 SB |
195 | int n = 0; |
196 | ||
6c5d4d1a | 197 | for (ptr = store_motion_mems; ptr != NULL; ptr = ptr->next) |
df35c271 SB |
198 | ptr->index = n++; |
199 | ||
200 | return n; | |
201 | } | |
202 | ||
203 | /* Return first item in the list. */ | |
204 | ||
6c5d4d1a SB |
205 | static inline struct st_expr * |
206 | first_st_expr (void) | |
df35c271 | 207 | { |
6c5d4d1a | 208 | return store_motion_mems; |
df35c271 SB |
209 | } |
210 | ||
211 | /* Return the next item in the list after the specified one. */ | |
212 | ||
6c5d4d1a SB |
213 | static inline struct st_expr * |
214 | next_st_expr (struct st_expr * ptr) | |
df35c271 SB |
215 | { |
216 | return ptr->next; | |
217 | } | |
218 | ||
6c5d4d1a | 219 | /* Dump debugging info about the store_motion_mems list. */ |
df35c271 SB |
220 | |
221 | static void | |
6c5d4d1a | 222 | print_store_motion_mems (FILE * file) |
df35c271 | 223 | { |
6c5d4d1a | 224 | struct st_expr * ptr; |
df35c271 | 225 | |
6c5d4d1a | 226 | fprintf (dump_file, "STORE_MOTION list of MEM exprs considered:\n"); |
df35c271 | 227 | |
6c5d4d1a | 228 | for (ptr = first_st_expr (); ptr != NULL; ptr = next_st_expr (ptr)) |
df35c271 SB |
229 | { |
230 | fprintf (file, " Pattern (%3d): ", ptr->index); | |
231 | ||
232 | print_rtl (file, ptr->pattern); | |
233 | ||
6c5d4d1a | 234 | fprintf (file, "\n ANTIC stores : "); |
df35c271 | 235 | |
6c5d4d1a SB |
236 | if (ptr->antic_stores) |
237 | print_rtl (file, ptr->antic_stores); | |
df35c271 SB |
238 | else |
239 | fprintf (file, "(nil)"); | |
240 | ||
6c5d4d1a | 241 | fprintf (file, "\n AVAIL stores : "); |
df35c271 | 242 | |
6c5d4d1a SB |
243 | if (ptr->avail_stores) |
244 | print_rtl (file, ptr->avail_stores); | |
df35c271 SB |
245 | else |
246 | fprintf (file, "(nil)"); | |
247 | ||
248 | fprintf (file, "\n\n"); | |
249 | } | |
250 | ||
251 | fprintf (file, "\n"); | |
252 | } | |
253 | \f | |
df35c271 SB |
254 | /* Return zero if some of the registers in list X are killed |
255 | due to set of registers in bitmap REGS_SET. */ | |
256 | ||
257 | static bool | |
258 | store_ops_ok (const_rtx x, int *regs_set) | |
259 | { | |
260 | const_rtx reg; | |
261 | ||
262 | for (; x; x = XEXP (x, 1)) | |
263 | { | |
264 | reg = XEXP (x, 0); | |
c3284718 | 265 | if (regs_set[REGNO (reg)]) |
df35c271 SB |
266 | return false; |
267 | } | |
268 | ||
269 | return true; | |
270 | } | |
271 | ||
6c5d4d1a SB |
272 | /* Returns a list of registers mentioned in X. |
273 | FIXME: A regset would be prettier and less expensive. */ | |
274 | ||
e67d1102 | 275 | static rtx_expr_list * |
df35c271 SB |
276 | extract_mentioned_regs (rtx x) |
277 | { | |
e67d1102 | 278 | rtx_expr_list *mentioned_regs = NULL; |
638e18a4 RS |
279 | subrtx_var_iterator::array_type array; |
280 | FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST) | |
281 | { | |
282 | rtx x = *iter; | |
283 | if (REG_P (x)) | |
284 | mentioned_regs = alloc_EXPR_LIST (0, x, mentioned_regs); | |
285 | } | |
6c5d4d1a | 286 | return mentioned_regs; |
df35c271 SB |
287 | } |
288 | ||
289 | /* Check to see if the load X is aliased with STORE_PATTERN. | |
290 | AFTER is true if we are checking the case when STORE_PATTERN occurs | |
291 | after the X. */ | |
292 | ||
293 | static bool | |
294 | load_kills_store (const_rtx x, const_rtx store_pattern, int after) | |
295 | { | |
296 | if (after) | |
297 | return anti_dependence (x, store_pattern); | |
298 | else | |
53d9622b | 299 | return true_dependence (store_pattern, GET_MODE (store_pattern), x); |
df35c271 SB |
300 | } |
301 | ||
6c5d4d1a | 302 | /* Go through the entire rtx X, looking for any loads which might alias |
df35c271 SB |
303 | STORE_PATTERN. Return true if found. |
304 | AFTER is true if we are checking the case when STORE_PATTERN occurs | |
305 | after the insn X. */ | |
306 | ||
307 | static bool | |
308 | find_loads (const_rtx x, const_rtx store_pattern, int after) | |
309 | { | |
310 | const char * fmt; | |
311 | int i, j; | |
312 | int ret = false; | |
313 | ||
314 | if (!x) | |
315 | return false; | |
316 | ||
317 | if (GET_CODE (x) == SET) | |
318 | x = SET_SRC (x); | |
319 | ||
320 | if (MEM_P (x)) | |
321 | { | |
322 | if (load_kills_store (x, store_pattern, after)) | |
323 | return true; | |
324 | } | |
325 | ||
326 | /* Recursively process the insn. */ | |
327 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
328 | ||
329 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0 && !ret; i--) | |
330 | { | |
331 | if (fmt[i] == 'e') | |
332 | ret |= find_loads (XEXP (x, i), store_pattern, after); | |
333 | else if (fmt[i] == 'E') | |
334 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
335 | ret |= find_loads (XVECEXP (x, i, j), store_pattern, after); | |
336 | } | |
337 | return ret; | |
338 | } | |
339 | ||
340 | /* Go through pattern PAT looking for any loads which might kill the | |
341 | store in X. Return true if found. | |
342 | AFTER is true if we are checking the case when loads kill X occurs | |
343 | after the insn for PAT. */ | |
344 | ||
345 | static inline bool | |
346 | store_killed_in_pat (const_rtx x, const_rtx pat, int after) | |
347 | { | |
348 | if (GET_CODE (pat) == SET) | |
349 | { | |
350 | rtx dest = SET_DEST (pat); | |
351 | ||
352 | if (GET_CODE (dest) == ZERO_EXTRACT) | |
353 | dest = XEXP (dest, 0); | |
354 | ||
355 | /* Check for memory stores to aliased objects. */ | |
356 | if (MEM_P (dest) | |
357 | && !exp_equiv_p (dest, x, 0, true)) | |
358 | { | |
359 | if (after) | |
360 | { | |
361 | if (output_dependence (dest, x)) | |
362 | return true; | |
363 | } | |
364 | else | |
365 | { | |
366 | if (output_dependence (x, dest)) | |
367 | return true; | |
368 | } | |
369 | } | |
370 | } | |
371 | ||
372 | if (find_loads (pat, x, after)) | |
373 | return true; | |
374 | ||
375 | return false; | |
376 | } | |
377 | ||
378 | /* Check if INSN kills the store pattern X (is aliased with it). | |
379 | AFTER is true if we are checking the case when store X occurs | |
380 | after the insn. Return true if it does. */ | |
381 | ||
382 | static bool | |
b4b7724e | 383 | store_killed_in_insn (const_rtx x, const_rtx x_regs, const rtx_insn *insn, int after) |
df35c271 | 384 | { |
9e412ca3 | 385 | const_rtx reg, note, pat; |
df35c271 | 386 | |
2ad1dda0 | 387 | if (! NONDEBUG_INSN_P (insn)) |
df35c271 SB |
388 | return false; |
389 | ||
390 | if (CALL_P (insn)) | |
391 | { | |
392 | /* A normal or pure call might read from pattern, | |
393 | but a const call will not. */ | |
394 | if (!RTL_CONST_CALL_P (insn)) | |
395 | return true; | |
396 | ||
397 | /* But even a const call reads its parameters. Check whether the | |
398 | base of some of registers used in mem is stack pointer. */ | |
399 | for (reg = x_regs; reg; reg = XEXP (reg, 1)) | |
9e412ca3 RS |
400 | if (may_be_sp_based_p (XEXP (reg, 0))) |
401 | return true; | |
df35c271 SB |
402 | |
403 | return false; | |
404 | } | |
405 | ||
406 | pat = PATTERN (insn); | |
407 | if (GET_CODE (pat) == SET) | |
408 | { | |
409 | if (store_killed_in_pat (x, pat, after)) | |
410 | return true; | |
411 | } | |
412 | else if (GET_CODE (pat) == PARALLEL) | |
413 | { | |
414 | int i; | |
415 | ||
416 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
417 | if (store_killed_in_pat (x, XVECEXP (pat, 0, i), after)) | |
418 | return true; | |
419 | } | |
420 | else if (find_loads (PATTERN (insn), x, after)) | |
421 | return true; | |
422 | ||
423 | /* If this insn has a REG_EQUAL or REG_EQUIV note referencing a memory | |
424 | location aliased with X, then this insn kills X. */ | |
425 | note = find_reg_equal_equiv_note (insn); | |
426 | if (! note) | |
427 | return false; | |
428 | note = XEXP (note, 0); | |
429 | ||
430 | /* However, if the note represents a must alias rather than a may | |
431 | alias relationship, then it does not kill X. */ | |
432 | if (exp_equiv_p (note, x, 0, true)) | |
433 | return false; | |
434 | ||
435 | /* See if there are any aliased loads in the note. */ | |
436 | return find_loads (note, x, after); | |
437 | } | |
438 | ||
439 | /* Returns true if the expression X is loaded or clobbered on or after INSN | |
440 | within basic block BB. REGS_SET_AFTER is bitmap of registers set in | |
441 | or after the insn. X_REGS is list of registers mentioned in X. If the store | |
442 | is killed, return the last insn in that it occurs in FAIL_INSN. */ | |
443 | ||
444 | static bool | |
b4b7724e DM |
445 | store_killed_after (const_rtx x, const_rtx x_regs, const rtx_insn *insn, |
446 | const_basic_block bb, | |
df35c271 SB |
447 | int *regs_set_after, rtx *fail_insn) |
448 | { | |
b4b7724e | 449 | rtx_insn *last = BB_END (bb), *act; |
df35c271 SB |
450 | |
451 | if (!store_ops_ok (x_regs, regs_set_after)) | |
452 | { | |
453 | /* We do not know where it will happen. */ | |
454 | if (fail_insn) | |
455 | *fail_insn = NULL_RTX; | |
456 | return true; | |
457 | } | |
458 | ||
459 | /* Scan from the end, so that fail_insn is determined correctly. */ | |
460 | for (act = last; act != PREV_INSN (insn); act = PREV_INSN (act)) | |
461 | if (store_killed_in_insn (x, x_regs, act, false)) | |
462 | { | |
463 | if (fail_insn) | |
464 | *fail_insn = act; | |
465 | return true; | |
466 | } | |
467 | ||
468 | return false; | |
469 | } | |
470 | ||
471 | /* Returns true if the expression X is loaded or clobbered on or before INSN | |
472 | within basic block BB. X_REGS is list of registers mentioned in X. | |
473 | REGS_SET_BEFORE is bitmap of registers set before or in this insn. */ | |
474 | static bool | |
b4b7724e DM |
475 | store_killed_before (const_rtx x, const_rtx x_regs, const rtx_insn *insn, |
476 | const_basic_block bb, int *regs_set_before) | |
df35c271 | 477 | { |
b4b7724e | 478 | rtx_insn *first = BB_HEAD (bb); |
df35c271 SB |
479 | |
480 | if (!store_ops_ok (x_regs, regs_set_before)) | |
481 | return true; | |
482 | ||
483 | for ( ; insn != PREV_INSN (first); insn = PREV_INSN (insn)) | |
484 | if (store_killed_in_insn (x, x_regs, insn, true)) | |
485 | return true; | |
486 | ||
487 | return false; | |
488 | } | |
489 | ||
6c5d4d1a SB |
490 | /* The last insn in the basic block that compute_store_table is processing, |
491 | where store_killed_after is true for X. | |
492 | Since we go through the basic block from BB_END to BB_HEAD, this is | |
493 | also the available store at the end of the basic block. Therefore | |
494 | this is in effect a cache, to avoid calling store_killed_after for | |
495 | equivalent aliasing store expressions. | |
496 | This value is only meaningful during the computation of the store | |
497 | table. We hi-jack the REACHING_REG field of struct st_expr to save | |
498 | a bit of memory. */ | |
499 | #define LAST_AVAIL_CHECK_FAILURE(x) ((x)->reaching_reg) | |
500 | ||
df35c271 SB |
501 | /* Determine whether INSN is MEM store pattern that we will consider moving. |
502 | REGS_SET_BEFORE is bitmap of registers set before (and including) the | |
503 | current insn, REGS_SET_AFTER is bitmap of registers set after (and | |
504 | including) the insn in this basic block. We must be passing through BB from | |
505 | head to end, as we are using this fact to speed things up. | |
506 | ||
507 | The results are stored this way: | |
508 | ||
6c5d4d1a | 509 | -- the first anticipatable expression is added into ANTIC_STORES |
df35c271 SB |
510 | -- if the processed expression is not anticipatable, NULL_RTX is added |
511 | there instead, so that we can use it as indicator that no further | |
512 | expression of this type may be anticipatable | |
6c5d4d1a | 513 | -- if the expression is available, it is added as head of AVAIL_STORES; |
df35c271 SB |
514 | consequently, all of them but this head are dead and may be deleted. |
515 | -- if the expression is not available, the insn due to that it fails to be | |
6c5d4d1a | 516 | available is stored in REACHING_REG (via LAST_AVAIL_CHECK_FAILURE). |
df35c271 SB |
517 | |
518 | The things are complicated a bit by fact that there already may be stores | |
519 | to the same MEM from other blocks; also caller must take care of the | |
520 | necessary cleanup of the temporary markers after end of the basic block. | |
521 | */ | |
522 | ||
523 | static void | |
b4b7724e | 524 | find_moveable_store (rtx_insn *insn, int *regs_set_before, int *regs_set_after) |
df35c271 | 525 | { |
6c5d4d1a | 526 | struct st_expr * ptr; |
3dc99c19 | 527 | rtx dest, set; |
df35c271 SB |
528 | int check_anticipatable, check_available; |
529 | basic_block bb = BLOCK_FOR_INSN (insn); | |
530 | ||
531 | set = single_set (insn); | |
532 | if (!set) | |
533 | return; | |
534 | ||
535 | dest = SET_DEST (set); | |
536 | ||
537 | if (! MEM_P (dest) || MEM_VOLATILE_P (dest) | |
538 | || GET_MODE (dest) == BLKmode) | |
539 | return; | |
540 | ||
541 | if (side_effects_p (dest)) | |
542 | return; | |
543 | ||
544 | /* If we are handling exceptions, we must be careful with memory references | |
8f4f502f | 545 | that may trap. If we are not, the behavior is undefined, so we may just |
df35c271 | 546 | continue. */ |
8f4f502f | 547 | if (cfun->can_throw_non_call_exceptions && may_trap_p (dest)) |
df35c271 SB |
548 | return; |
549 | ||
550 | /* Even if the destination cannot trap, the source may. In this case we'd | |
551 | need to handle updating the REG_EH_REGION note. */ | |
552 | if (find_reg_note (insn, REG_EH_REGION, NULL_RTX)) | |
553 | return; | |
554 | ||
555 | /* Make sure that the SET_SRC of this store insns can be assigned to | |
556 | a register, or we will fail later on in replace_store_insn, which | |
557 | assumes that we can do this. But sometimes the target machine has | |
558 | oddities like MEM read-modify-write instruction. See for example | |
559 | PR24257. */ | |
560 | if (!can_assign_to_reg_without_clobbers_p (SET_SRC (set))) | |
561 | return; | |
562 | ||
6c5d4d1a | 563 | ptr = st_expr_entry (dest); |
df35c271 SB |
564 | if (!ptr->pattern_regs) |
565 | ptr->pattern_regs = extract_mentioned_regs (dest); | |
566 | ||
567 | /* Do not check for anticipatability if we either found one anticipatable | |
568 | store already, or tested for one and found out that it was killed. */ | |
569 | check_anticipatable = 0; | |
6c5d4d1a | 570 | if (!ptr->antic_stores) |
df35c271 SB |
571 | check_anticipatable = 1; |
572 | else | |
573 | { | |
3dc99c19 | 574 | rtx_insn *tmp = ptr->antic_stores->insn (); |
df35c271 SB |
575 | if (tmp != NULL_RTX |
576 | && BLOCK_FOR_INSN (tmp) != bb) | |
577 | check_anticipatable = 1; | |
578 | } | |
579 | if (check_anticipatable) | |
580 | { | |
3dc99c19 | 581 | rtx_insn *tmp; |
df35c271 | 582 | if (store_killed_before (dest, ptr->pattern_regs, insn, bb, regs_set_before)) |
3dc99c19 | 583 | tmp = NULL; |
df35c271 SB |
584 | else |
585 | tmp = insn; | |
6c5d4d1a | 586 | ptr->antic_stores = alloc_INSN_LIST (tmp, ptr->antic_stores); |
df35c271 SB |
587 | } |
588 | ||
589 | /* It is not necessary to check whether store is available if we did | |
590 | it successfully before; if we failed before, do not bother to check | |
591 | until we reach the insn that caused us to fail. */ | |
592 | check_available = 0; | |
6c5d4d1a | 593 | if (!ptr->avail_stores) |
df35c271 SB |
594 | check_available = 1; |
595 | else | |
596 | { | |
3dc99c19 | 597 | rtx_insn *tmp = ptr->avail_stores->insn (); |
df35c271 SB |
598 | if (BLOCK_FOR_INSN (tmp) != bb) |
599 | check_available = 1; | |
600 | } | |
601 | if (check_available) | |
602 | { | |
603 | /* Check that we have already reached the insn at that the check | |
604 | failed last time. */ | |
605 | if (LAST_AVAIL_CHECK_FAILURE (ptr)) | |
606 | { | |
3dc99c19 | 607 | rtx_insn *tmp; |
df35c271 SB |
608 | for (tmp = BB_END (bb); |
609 | tmp != insn && tmp != LAST_AVAIL_CHECK_FAILURE (ptr); | |
610 | tmp = PREV_INSN (tmp)) | |
611 | continue; | |
612 | if (tmp == insn) | |
613 | check_available = 0; | |
614 | } | |
615 | else | |
616 | check_available = store_killed_after (dest, ptr->pattern_regs, insn, | |
617 | bb, regs_set_after, | |
618 | &LAST_AVAIL_CHECK_FAILURE (ptr)); | |
619 | } | |
620 | if (!check_available) | |
6c5d4d1a | 621 | ptr->avail_stores = alloc_INSN_LIST (insn, ptr->avail_stores); |
df35c271 SB |
622 | } |
623 | ||
624 | /* Find available and anticipatable stores. */ | |
625 | ||
626 | static int | |
627 | compute_store_table (void) | |
628 | { | |
629 | int ret; | |
630 | basic_block bb; | |
b4b7724e | 631 | rtx_insn *insn; |
3dc99c19 | 632 | rtx_insn *tmp; |
bfac633a | 633 | df_ref def; |
df35c271 | 634 | int *last_set_in, *already_set; |
6c5d4d1a | 635 | struct st_expr * ptr, **prev_next_ptr_ptr; |
df35c271 SB |
636 | unsigned int max_gcse_regno = max_reg_num (); |
637 | ||
6c5d4d1a | 638 | store_motion_mems = NULL; |
c203e8a7 | 639 | store_motion_mems_table = new hash_table<st_expr_hasher> (13); |
df35c271 SB |
640 | last_set_in = XCNEWVEC (int, max_gcse_regno); |
641 | already_set = XNEWVEC (int, max_gcse_regno); | |
642 | ||
643 | /* Find all the stores we care about. */ | |
11cd3bed | 644 | FOR_EACH_BB_FN (bb, cfun) |
df35c271 SB |
645 | { |
646 | /* First compute the registers set in this block. */ | |
df35c271 SB |
647 | FOR_BB_INSNS (bb, insn) |
648 | { | |
6c5d4d1a | 649 | |
2ad1dda0 | 650 | if (! NONDEBUG_INSN_P (insn)) |
df35c271 SB |
651 | continue; |
652 | ||
bfac633a RS |
653 | FOR_EACH_INSN_DEF (def, insn) |
654 | last_set_in[DF_REF_REGNO (def)] = INSN_UID (insn); | |
df35c271 SB |
655 | } |
656 | ||
657 | /* Now find the stores. */ | |
658 | memset (already_set, 0, sizeof (int) * max_gcse_regno); | |
df35c271 SB |
659 | FOR_BB_INSNS (bb, insn) |
660 | { | |
2ad1dda0 | 661 | if (! NONDEBUG_INSN_P (insn)) |
df35c271 SB |
662 | continue; |
663 | ||
bfac633a RS |
664 | FOR_EACH_INSN_DEF (def, insn) |
665 | already_set[DF_REF_REGNO (def)] = INSN_UID (insn); | |
df35c271 SB |
666 | |
667 | /* Now that we've marked regs, look for stores. */ | |
668 | find_moveable_store (insn, already_set, last_set_in); | |
669 | ||
670 | /* Unmark regs that are no longer set. */ | |
bfac633a RS |
671 | FOR_EACH_INSN_DEF (def, insn) |
672 | if (last_set_in[DF_REF_REGNO (def)] == INSN_UID (insn)) | |
673 | last_set_in[DF_REF_REGNO (def)] = 0; | |
df35c271 SB |
674 | } |
675 | ||
b2b29377 MM |
676 | if (flag_checking) |
677 | { | |
678 | /* last_set_in should now be all-zero. */ | |
679 | for (unsigned regno = 0; regno < max_gcse_regno; regno++) | |
680 | gcc_assert (!last_set_in[regno]); | |
681 | } | |
df35c271 SB |
682 | |
683 | /* Clear temporary marks. */ | |
6c5d4d1a | 684 | for (ptr = first_st_expr (); ptr != NULL; ptr = next_st_expr (ptr)) |
df35c271 | 685 | { |
6c5d4d1a SB |
686 | LAST_AVAIL_CHECK_FAILURE (ptr) = NULL_RTX; |
687 | if (ptr->antic_stores | |
3dc99c19 DM |
688 | && (tmp = ptr->antic_stores->insn ()) == NULL_RTX) |
689 | ptr->antic_stores = ptr->antic_stores->next (); | |
df35c271 SB |
690 | } |
691 | } | |
692 | ||
693 | /* Remove the stores that are not available anywhere, as there will | |
694 | be no opportunity to optimize them. */ | |
6c5d4d1a | 695 | for (ptr = store_motion_mems, prev_next_ptr_ptr = &store_motion_mems; |
df35c271 SB |
696 | ptr != NULL; |
697 | ptr = *prev_next_ptr_ptr) | |
698 | { | |
6c5d4d1a | 699 | if (! ptr->avail_stores) |
df35c271 SB |
700 | { |
701 | *prev_next_ptr_ptr = ptr->next; | |
c203e8a7 | 702 | store_motion_mems_table->remove_elt_with_hash (ptr, ptr->hash_index); |
6c5d4d1a | 703 | free_st_expr_entry (ptr); |
df35c271 SB |
704 | } |
705 | else | |
706 | prev_next_ptr_ptr = &ptr->next; | |
707 | } | |
708 | ||
6c5d4d1a | 709 | ret = enumerate_store_motion_mems (); |
df35c271 SB |
710 | |
711 | if (dump_file) | |
6c5d4d1a | 712 | print_store_motion_mems (dump_file); |
df35c271 SB |
713 | |
714 | free (last_set_in); | |
715 | free (already_set); | |
716 | return ret; | |
717 | } | |
718 | ||
6c5d4d1a SB |
719 | /* In all code following after this, REACHING_REG has its original |
720 | meaning again. Avoid confusion, and undef the accessor macro for | |
721 | the temporary marks usage in compute_store_table. */ | |
722 | #undef LAST_AVAIL_CHECK_FAILURE | |
723 | ||
df35c271 SB |
724 | /* Insert an instruction at the beginning of a basic block, and update |
725 | the BB_HEAD if needed. */ | |
726 | ||
727 | static void | |
b4b7724e | 728 | insert_insn_start_basic_block (rtx_insn *insn, basic_block bb) |
df35c271 SB |
729 | { |
730 | /* Insert at start of successor block. */ | |
b4b7724e DM |
731 | rtx_insn *prev = PREV_INSN (BB_HEAD (bb)); |
732 | rtx_insn *before = BB_HEAD (bb); | |
df35c271 SB |
733 | while (before != 0) |
734 | { | |
735 | if (! LABEL_P (before) | |
736 | && !NOTE_INSN_BASIC_BLOCK_P (before)) | |
737 | break; | |
738 | prev = before; | |
739 | if (prev == BB_END (bb)) | |
740 | break; | |
741 | before = NEXT_INSN (before); | |
742 | } | |
743 | ||
744 | insn = emit_insn_after_noloc (insn, prev, bb); | |
745 | ||
746 | if (dump_file) | |
747 | { | |
748 | fprintf (dump_file, "STORE_MOTION insert store at start of BB %d:\n", | |
749 | bb->index); | |
750 | print_inline_rtx (dump_file, insn, 6); | |
751 | fprintf (dump_file, "\n"); | |
752 | } | |
753 | } | |
754 | ||
6c5d4d1a | 755 | /* This routine will insert a store on an edge. EXPR is the st_expr entry for |
df35c271 SB |
756 | the memory reference, and E is the edge to insert it on. Returns nonzero |
757 | if an edge insertion was performed. */ | |
758 | ||
759 | static int | |
6c5d4d1a | 760 | insert_store (struct st_expr * expr, edge e) |
df35c271 | 761 | { |
b4b7724e DM |
762 | rtx reg; |
763 | rtx_insn *insn; | |
df35c271 SB |
764 | basic_block bb; |
765 | edge tmp; | |
766 | edge_iterator ei; | |
767 | ||
768 | /* We did all the deleted before this insert, so if we didn't delete a | |
769 | store, then we haven't set the reaching reg yet either. */ | |
770 | if (expr->reaching_reg == NULL_RTX) | |
771 | return 0; | |
772 | ||
773 | if (e->flags & EDGE_FAKE) | |
774 | return 0; | |
775 | ||
776 | reg = expr->reaching_reg; | |
1476d1bd | 777 | insn = gen_move_insn (copy_rtx (expr->pattern), reg); |
df35c271 SB |
778 | |
779 | /* If we are inserting this expression on ALL predecessor edges of a BB, | |
780 | insert it at the start of the BB, and reset the insert bits on the other | |
781 | edges so we don't try to insert it on the other edges. */ | |
782 | bb = e->dest; | |
783 | FOR_EACH_EDGE (tmp, ei, e->dest->preds) | |
784 | if (!(tmp->flags & EDGE_FAKE)) | |
785 | { | |
786 | int index = EDGE_INDEX (edge_list, tmp->src, tmp->dest); | |
b8698a0f | 787 | |
df35c271 | 788 | gcc_assert (index != EDGE_INDEX_NO_EDGE); |
d7c028c0 | 789 | if (! bitmap_bit_p (st_insert_map[index], expr->index)) |
df35c271 SB |
790 | break; |
791 | } | |
792 | ||
793 | /* If tmp is NULL, we found an insertion on every edge, blank the | |
794 | insertion vector for these edges, and insert at the start of the BB. */ | |
fefa31b5 | 795 | if (!tmp && bb != EXIT_BLOCK_PTR_FOR_FN (cfun)) |
df35c271 SB |
796 | { |
797 | FOR_EACH_EDGE (tmp, ei, e->dest->preds) | |
798 | { | |
799 | int index = EDGE_INDEX (edge_list, tmp->src, tmp->dest); | |
d7c028c0 | 800 | bitmap_clear_bit (st_insert_map[index], expr->index); |
df35c271 SB |
801 | } |
802 | insert_insn_start_basic_block (insn, bb); | |
803 | return 0; | |
804 | } | |
805 | ||
806 | /* We can't put stores in the front of blocks pointed to by abnormal | |
807 | edges since that may put a store where one didn't used to be. */ | |
808 | gcc_assert (!(e->flags & EDGE_ABNORMAL)); | |
809 | ||
810 | insert_insn_on_edge (insn, e); | |
811 | ||
812 | if (dump_file) | |
813 | { | |
814 | fprintf (dump_file, "STORE_MOTION insert insn on edge (%d, %d):\n", | |
815 | e->src->index, e->dest->index); | |
816 | print_inline_rtx (dump_file, insn, 6); | |
817 | fprintf (dump_file, "\n"); | |
818 | } | |
819 | ||
820 | return 1; | |
821 | } | |
822 | ||
823 | /* Remove any REG_EQUAL or REG_EQUIV notes containing a reference to the | |
824 | memory location in SMEXPR set in basic block BB. | |
825 | ||
826 | This could be rather expensive. */ | |
827 | ||
828 | static void | |
6c5d4d1a | 829 | remove_reachable_equiv_notes (basic_block bb, struct st_expr *smexpr) |
df35c271 SB |
830 | { |
831 | edge_iterator *stack, ei; | |
832 | int sp; | |
833 | edge act; | |
8b1c6fd7 | 834 | sbitmap visited = sbitmap_alloc (last_basic_block_for_fn (cfun)); |
b4b7724e DM |
835 | rtx last, note; |
836 | rtx_insn *insn; | |
df35c271 SB |
837 | rtx mem = smexpr->pattern; |
838 | ||
0cae8d31 | 839 | stack = XNEWVEC (edge_iterator, n_basic_blocks_for_fn (cfun)); |
df35c271 SB |
840 | sp = 0; |
841 | ei = ei_start (bb->succs); | |
842 | ||
f61e445a | 843 | bitmap_clear (visited); |
df35c271 SB |
844 | |
845 | act = (EDGE_COUNT (ei_container (ei)) > 0 ? EDGE_I (ei_container (ei), 0) : NULL); | |
846 | while (1) | |
847 | { | |
848 | if (!act) | |
849 | { | |
850 | if (!sp) | |
851 | { | |
852 | free (stack); | |
853 | sbitmap_free (visited); | |
854 | return; | |
855 | } | |
856 | act = ei_edge (stack[--sp]); | |
857 | } | |
858 | bb = act->dest; | |
859 | ||
fefa31b5 | 860 | if (bb == EXIT_BLOCK_PTR_FOR_FN (cfun) |
d7c028c0 | 861 | || bitmap_bit_p (visited, bb->index)) |
df35c271 SB |
862 | { |
863 | if (!ei_end_p (ei)) | |
864 | ei_next (&ei); | |
865 | act = (! ei_end_p (ei)) ? ei_edge (ei) : NULL; | |
866 | continue; | |
867 | } | |
d7c028c0 | 868 | bitmap_set_bit (visited, bb->index); |
df35c271 | 869 | |
d7c028c0 | 870 | if (bitmap_bit_p (st_antloc[bb->index], smexpr->index)) |
df35c271 | 871 | { |
6c5d4d1a | 872 | for (last = smexpr->antic_stores; |
df35c271 SB |
873 | BLOCK_FOR_INSN (XEXP (last, 0)) != bb; |
874 | last = XEXP (last, 1)) | |
875 | continue; | |
876 | last = XEXP (last, 0); | |
877 | } | |
878 | else | |
879 | last = NEXT_INSN (BB_END (bb)); | |
880 | ||
881 | for (insn = BB_HEAD (bb); insn != last; insn = NEXT_INSN (insn)) | |
2ad1dda0 | 882 | if (NONDEBUG_INSN_P (insn)) |
df35c271 SB |
883 | { |
884 | note = find_reg_equal_equiv_note (insn); | |
885 | if (!note || !exp_equiv_p (XEXP (note, 0), mem, 0, true)) | |
886 | continue; | |
887 | ||
888 | if (dump_file) | |
889 | fprintf (dump_file, "STORE_MOTION drop REG_EQUAL note at insn %d:\n", | |
890 | INSN_UID (insn)); | |
891 | remove_note (insn, note); | |
892 | } | |
893 | ||
894 | if (!ei_end_p (ei)) | |
895 | ei_next (&ei); | |
896 | act = (! ei_end_p (ei)) ? ei_edge (ei) : NULL; | |
897 | ||
898 | if (EDGE_COUNT (bb->succs) > 0) | |
899 | { | |
900 | if (act) | |
901 | stack[sp++] = ei; | |
902 | ei = ei_start (bb->succs); | |
903 | act = (EDGE_COUNT (ei_container (ei)) > 0 ? EDGE_I (ei_container (ei), 0) : NULL); | |
904 | } | |
905 | } | |
906 | } | |
907 | ||
908 | /* This routine will replace a store with a SET to a specified register. */ | |
909 | ||
910 | static void | |
e8a54173 DM |
911 | replace_store_insn (rtx reg, rtx_insn *del, basic_block bb, |
912 | struct st_expr *smexpr) | |
df35c271 | 913 | { |
b4b7724e DM |
914 | rtx_insn *insn; |
915 | rtx mem, note, set, ptr; | |
df35c271 SB |
916 | |
917 | mem = smexpr->pattern; | |
1476d1bd | 918 | insn = gen_move_insn (reg, SET_SRC (single_set (del))); |
df35c271 | 919 | |
6c5d4d1a | 920 | for (ptr = smexpr->antic_stores; ptr; ptr = XEXP (ptr, 1)) |
df35c271 SB |
921 | if (XEXP (ptr, 0) == del) |
922 | { | |
923 | XEXP (ptr, 0) = insn; | |
924 | break; | |
925 | } | |
926 | ||
927 | /* Move the notes from the deleted insn to its replacement. */ | |
928 | REG_NOTES (insn) = REG_NOTES (del); | |
929 | ||
930 | /* Emit the insn AFTER all the notes are transferred. | |
931 | This is cheaper since we avoid df rescanning for the note change. */ | |
932 | insn = emit_insn_after (insn, del); | |
933 | ||
934 | if (dump_file) | |
935 | { | |
936 | fprintf (dump_file, | |
937 | "STORE_MOTION delete insn in BB %d:\n ", bb->index); | |
938 | print_inline_rtx (dump_file, del, 6); | |
939 | fprintf (dump_file, "\nSTORE_MOTION replaced with insn:\n "); | |
940 | print_inline_rtx (dump_file, insn, 6); | |
941 | fprintf (dump_file, "\n"); | |
942 | } | |
943 | ||
944 | delete_insn (del); | |
945 | ||
946 | /* Now we must handle REG_EQUAL notes whose contents is equal to the mem; | |
947 | they are no longer accurate provided that they are reached by this | |
948 | definition, so drop them. */ | |
949 | for (; insn != NEXT_INSN (BB_END (bb)); insn = NEXT_INSN (insn)) | |
2ad1dda0 | 950 | if (NONDEBUG_INSN_P (insn)) |
df35c271 SB |
951 | { |
952 | set = single_set (insn); | |
953 | if (!set) | |
954 | continue; | |
955 | if (exp_equiv_p (SET_DEST (set), mem, 0, true)) | |
956 | return; | |
957 | note = find_reg_equal_equiv_note (insn); | |
958 | if (!note || !exp_equiv_p (XEXP (note, 0), mem, 0, true)) | |
959 | continue; | |
960 | ||
961 | if (dump_file) | |
962 | fprintf (dump_file, "STORE_MOTION drop REG_EQUAL note at insn %d:\n", | |
963 | INSN_UID (insn)); | |
964 | remove_note (insn, note); | |
965 | } | |
966 | remove_reachable_equiv_notes (bb, smexpr); | |
967 | } | |
968 | ||
969 | ||
970 | /* Delete a store, but copy the value that would have been stored into | |
971 | the reaching_reg for later storing. */ | |
972 | ||
973 | static void | |
6c5d4d1a | 974 | delete_store (struct st_expr * expr, basic_block bb) |
df35c271 | 975 | { |
e8a54173 | 976 | rtx reg; |
df35c271 SB |
977 | |
978 | if (expr->reaching_reg == NULL_RTX) | |
979 | expr->reaching_reg = gen_reg_rtx_and_attrs (expr->pattern); | |
980 | ||
981 | reg = expr->reaching_reg; | |
982 | ||
e8a54173 | 983 | for (rtx_insn_list *i = expr->avail_stores; i; i = i->next ()) |
df35c271 | 984 | { |
e8a54173 | 985 | rtx_insn *del = i->insn (); |
df35c271 SB |
986 | if (BLOCK_FOR_INSN (del) == bb) |
987 | { | |
988 | /* We know there is only one since we deleted redundant | |
989 | ones during the available computation. */ | |
990 | replace_store_insn (reg, del, bb, expr); | |
991 | break; | |
992 | } | |
993 | } | |
994 | } | |
995 | ||
996 | /* Fill in available, anticipatable, transparent and kill vectors in | |
997 | STORE_DATA, based on lists of available and anticipatable stores. */ | |
998 | static void | |
999 | build_store_vectors (void) | |
1000 | { | |
1001 | basic_block bb; | |
1002 | int *regs_set_in_block; | |
b32d5189 DM |
1003 | rtx_insn *insn; |
1004 | rtx_insn_list *st; | |
6c5d4d1a | 1005 | struct st_expr * ptr; |
df35c271 SB |
1006 | unsigned int max_gcse_regno = max_reg_num (); |
1007 | ||
1008 | /* Build the gen_vector. This is any store in the table which is not killed | |
1009 | by aliasing later in its block. */ | |
8b1c6fd7 DM |
1010 | st_avloc = sbitmap_vector_alloc (last_basic_block_for_fn (cfun), |
1011 | num_stores); | |
1012 | bitmap_vector_clear (st_avloc, last_basic_block_for_fn (cfun)); | |
df35c271 | 1013 | |
8b1c6fd7 DM |
1014 | st_antloc = sbitmap_vector_alloc (last_basic_block_for_fn (cfun), |
1015 | num_stores); | |
1016 | bitmap_vector_clear (st_antloc, last_basic_block_for_fn (cfun)); | |
df35c271 | 1017 | |
6c5d4d1a | 1018 | for (ptr = first_st_expr (); ptr != NULL; ptr = next_st_expr (ptr)) |
df35c271 | 1019 | { |
b32d5189 | 1020 | for (st = ptr->avail_stores; st != NULL; st = st->next ()) |
df35c271 | 1021 | { |
b32d5189 | 1022 | insn = st->insn (); |
df35c271 SB |
1023 | bb = BLOCK_FOR_INSN (insn); |
1024 | ||
1025 | /* If we've already seen an available expression in this block, | |
1026 | we can delete this one (It occurs earlier in the block). We'll | |
1027 | copy the SRC expression to an unused register in case there | |
1028 | are any side effects. */ | |
d7c028c0 | 1029 | if (bitmap_bit_p (st_avloc[bb->index], ptr->index)) |
df35c271 SB |
1030 | { |
1031 | rtx r = gen_reg_rtx_and_attrs (ptr->pattern); | |
1032 | if (dump_file) | |
1033 | fprintf (dump_file, "Removing redundant store:\n"); | |
e8a54173 | 1034 | replace_store_insn (r, st->insn (), bb, ptr); |
df35c271 SB |
1035 | continue; |
1036 | } | |
d7c028c0 | 1037 | bitmap_set_bit (st_avloc[bb->index], ptr->index); |
df35c271 SB |
1038 | } |
1039 | ||
b32d5189 | 1040 | for (st = ptr->antic_stores; st != NULL; st = st->next ()) |
df35c271 | 1041 | { |
b32d5189 | 1042 | insn = st->insn (); |
df35c271 | 1043 | bb = BLOCK_FOR_INSN (insn); |
d7c028c0 | 1044 | bitmap_set_bit (st_antloc[bb->index], ptr->index); |
df35c271 SB |
1045 | } |
1046 | } | |
1047 | ||
8b1c6fd7 DM |
1048 | st_kill = sbitmap_vector_alloc (last_basic_block_for_fn (cfun), num_stores); |
1049 | bitmap_vector_clear (st_kill, last_basic_block_for_fn (cfun)); | |
df35c271 | 1050 | |
8b1c6fd7 DM |
1051 | st_transp = sbitmap_vector_alloc (last_basic_block_for_fn (cfun), num_stores); |
1052 | bitmap_vector_clear (st_transp, last_basic_block_for_fn (cfun)); | |
df35c271 SB |
1053 | regs_set_in_block = XNEWVEC (int, max_gcse_regno); |
1054 | ||
11cd3bed | 1055 | FOR_EACH_BB_FN (bb, cfun) |
df35c271 | 1056 | { |
b114d73a SB |
1057 | memset (regs_set_in_block, 0, sizeof (int) * max_gcse_regno); |
1058 | ||
df35c271 | 1059 | FOR_BB_INSNS (bb, insn) |
2ad1dda0 | 1060 | if (NONDEBUG_INSN_P (insn)) |
df35c271 | 1061 | { |
bfac633a RS |
1062 | df_ref def; |
1063 | FOR_EACH_INSN_DEF (def, insn) | |
df35c271 | 1064 | { |
bfac633a | 1065 | unsigned int ref_regno = DF_REF_REGNO (def); |
df35c271 | 1066 | if (ref_regno < max_gcse_regno) |
bfac633a | 1067 | regs_set_in_block[DF_REF_REGNO (def)] = 1; |
df35c271 SB |
1068 | } |
1069 | } | |
1070 | ||
6c5d4d1a | 1071 | for (ptr = first_st_expr (); ptr != NULL; ptr = next_st_expr (ptr)) |
df35c271 SB |
1072 | { |
1073 | if (store_killed_after (ptr->pattern, ptr->pattern_regs, BB_HEAD (bb), | |
1074 | bb, regs_set_in_block, NULL)) | |
1075 | { | |
1076 | /* It should not be necessary to consider the expression | |
1077 | killed if it is both anticipatable and available. */ | |
d7c028c0 LC |
1078 | if (!bitmap_bit_p (st_antloc[bb->index], ptr->index) |
1079 | || !bitmap_bit_p (st_avloc[bb->index], ptr->index)) | |
1080 | bitmap_set_bit (st_kill[bb->index], ptr->index); | |
df35c271 SB |
1081 | } |
1082 | else | |
d7c028c0 | 1083 | bitmap_set_bit (st_transp[bb->index], ptr->index); |
df35c271 SB |
1084 | } |
1085 | } | |
1086 | ||
1087 | free (regs_set_in_block); | |
1088 | ||
1089 | if (dump_file) | |
1090 | { | |
8b1c6fd7 DM |
1091 | dump_bitmap_vector (dump_file, "st_antloc", "", st_antloc, |
1092 | last_basic_block_for_fn (cfun)); | |
1093 | dump_bitmap_vector (dump_file, "st_kill", "", st_kill, | |
1094 | last_basic_block_for_fn (cfun)); | |
1095 | dump_bitmap_vector (dump_file, "st_transp", "", st_transp, | |
1096 | last_basic_block_for_fn (cfun)); | |
1097 | dump_bitmap_vector (dump_file, "st_avloc", "", st_avloc, | |
1098 | last_basic_block_for_fn (cfun)); | |
df35c271 SB |
1099 | } |
1100 | } | |
1101 | ||
1102 | /* Free memory used by store motion. */ | |
1103 | ||
1104 | static void | |
1105 | free_store_memory (void) | |
1106 | { | |
6c5d4d1a SB |
1107 | free_store_motion_mems (); |
1108 | ||
1109 | if (st_avloc) | |
1110 | sbitmap_vector_free (st_avloc); | |
1111 | if (st_kill) | |
1112 | sbitmap_vector_free (st_kill); | |
1113 | if (st_transp) | |
1114 | sbitmap_vector_free (st_transp); | |
df35c271 SB |
1115 | if (st_antloc) |
1116 | sbitmap_vector_free (st_antloc); | |
6c5d4d1a SB |
1117 | if (st_insert_map) |
1118 | sbitmap_vector_free (st_insert_map); | |
1119 | if (st_delete_map) | |
1120 | sbitmap_vector_free (st_delete_map); | |
df35c271 | 1121 | |
6c5d4d1a SB |
1122 | st_avloc = st_kill = st_transp = st_antloc = NULL; |
1123 | st_insert_map = st_delete_map = NULL; | |
df35c271 SB |
1124 | } |
1125 | ||
1126 | /* Perform store motion. Much like gcse, except we move expressions the | |
1127 | other way by looking at the flowgraph in reverse. | |
1128 | Return non-zero if transformations are performed by the pass. */ | |
1129 | ||
1130 | static int | |
1131 | one_store_motion_pass (void) | |
1132 | { | |
1133 | basic_block bb; | |
1134 | int x; | |
6c5d4d1a SB |
1135 | struct st_expr * ptr; |
1136 | int did_edge_inserts = 0; | |
1137 | int n_stores_deleted = 0; | |
1138 | int n_stores_created = 0; | |
df35c271 SB |
1139 | |
1140 | init_alias_analysis (); | |
1141 | ||
1142 | /* Find all the available and anticipatable stores. */ | |
1143 | num_stores = compute_store_table (); | |
1144 | if (num_stores == 0) | |
1145 | { | |
c203e8a7 TS |
1146 | delete store_motion_mems_table; |
1147 | store_motion_mems_table = NULL; | |
df35c271 SB |
1148 | end_alias_analysis (); |
1149 | return 0; | |
1150 | } | |
1151 | ||
1152 | /* Now compute kill & transp vectors. */ | |
1153 | build_store_vectors (); | |
1154 | add_noreturn_fake_exit_edges (); | |
1155 | connect_infinite_loops_to_exit (); | |
1156 | ||
6c5d4d1a SB |
1157 | edge_list = pre_edge_rev_lcm (num_stores, st_transp, st_avloc, |
1158 | st_antloc, st_kill, &st_insert_map, | |
1159 | &st_delete_map); | |
df35c271 SB |
1160 | |
1161 | /* Now we want to insert the new stores which are going to be needed. */ | |
6c5d4d1a | 1162 | for (ptr = first_st_expr (); ptr != NULL; ptr = next_st_expr (ptr)) |
df35c271 SB |
1163 | { |
1164 | /* If any of the edges we have above are abnormal, we can't move this | |
1165 | store. */ | |
1166 | for (x = NUM_EDGES (edge_list) - 1; x >= 0; x--) | |
d7c028c0 | 1167 | if (bitmap_bit_p (st_insert_map[x], ptr->index) |
df35c271 SB |
1168 | && (INDEX_EDGE (edge_list, x)->flags & EDGE_ABNORMAL)) |
1169 | break; | |
1170 | ||
1171 | if (x >= 0) | |
1172 | { | |
1173 | if (dump_file != NULL) | |
1174 | fprintf (dump_file, | |
1175 | "Can't replace store %d: abnormal edge from %d to %d\n", | |
1176 | ptr->index, INDEX_EDGE (edge_list, x)->src->index, | |
1177 | INDEX_EDGE (edge_list, x)->dest->index); | |
1178 | continue; | |
1179 | } | |
b8698a0f | 1180 | |
df35c271 SB |
1181 | /* Now we want to insert the new stores which are going to be needed. */ |
1182 | ||
11cd3bed | 1183 | FOR_EACH_BB_FN (bb, cfun) |
d7c028c0 | 1184 | if (bitmap_bit_p (st_delete_map[bb->index], ptr->index)) |
df35c271 SB |
1185 | { |
1186 | delete_store (ptr, bb); | |
6c5d4d1a | 1187 | n_stores_deleted++; |
df35c271 SB |
1188 | } |
1189 | ||
1190 | for (x = 0; x < NUM_EDGES (edge_list); x++) | |
d7c028c0 | 1191 | if (bitmap_bit_p (st_insert_map[x], ptr->index)) |
df35c271 | 1192 | { |
6c5d4d1a SB |
1193 | did_edge_inserts |= insert_store (ptr, INDEX_EDGE (edge_list, x)); |
1194 | n_stores_created++; | |
df35c271 SB |
1195 | } |
1196 | } | |
1197 | ||
6c5d4d1a | 1198 | if (did_edge_inserts) |
df35c271 SB |
1199 | commit_edge_insertions (); |
1200 | ||
1201 | free_store_memory (); | |
1202 | free_edge_list (edge_list); | |
1203 | remove_fake_exit_edges (); | |
1204 | end_alias_analysis (); | |
1205 | ||
1206 | if (dump_file) | |
1207 | { | |
1208 | fprintf (dump_file, "STORE_MOTION of %s, %d basic blocks, ", | |
0cae8d31 | 1209 | current_function_name (), n_basic_blocks_for_fn (cfun)); |
6c5d4d1a SB |
1210 | fprintf (dump_file, "%d insns deleted, %d insns created\n", |
1211 | n_stores_deleted, n_stores_created); | |
df35c271 SB |
1212 | } |
1213 | ||
6c5d4d1a | 1214 | return (n_stores_deleted > 0 || n_stores_created > 0); |
df35c271 SB |
1215 | } |
1216 | ||
1217 | \f | |
df35c271 SB |
1218 | static unsigned int |
1219 | execute_rtl_store_motion (void) | |
1220 | { | |
1221 | delete_unreachable_blocks (); | |
df35c271 SB |
1222 | df_analyze (); |
1223 | flag_rerun_cse_after_global_opts |= one_store_motion_pass (); | |
1224 | return 0; | |
1225 | } | |
1226 | ||
27a4cd48 DM |
1227 | namespace { |
1228 | ||
1229 | const pass_data pass_data_rtl_store_motion = | |
df35c271 | 1230 | { |
27a4cd48 DM |
1231 | RTL_PASS, /* type */ |
1232 | "store_motion", /* name */ | |
1233 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
1234 | TV_LSM, /* tv_id */ |
1235 | PROP_cfglayout, /* properties_required */ | |
1236 | 0, /* properties_provided */ | |
1237 | 0, /* properties_destroyed */ | |
1238 | 0, /* todo_flags_start */ | |
3bea341f | 1239 | TODO_df_finish, /* todo_flags_finish */ |
df35c271 | 1240 | }; |
27a4cd48 DM |
1241 | |
1242 | class pass_rtl_store_motion : public rtl_opt_pass | |
1243 | { | |
1244 | public: | |
c3284718 RS |
1245 | pass_rtl_store_motion (gcc::context *ctxt) |
1246 | : rtl_opt_pass (pass_data_rtl_store_motion, ctxt) | |
27a4cd48 DM |
1247 | {} |
1248 | ||
1249 | /* opt_pass methods: */ | |
1a3d085c | 1250 | virtual bool gate (function *); |
be55bfe6 TS |
1251 | virtual unsigned int execute (function *) |
1252 | { | |
1253 | return execute_rtl_store_motion (); | |
1254 | } | |
27a4cd48 DM |
1255 | |
1256 | }; // class pass_rtl_store_motion | |
1257 | ||
1a3d085c TS |
1258 | bool |
1259 | pass_rtl_store_motion::gate (function *fun) | |
1260 | { | |
1261 | return optimize > 0 && flag_gcse_sm | |
1262 | && !fun->calls_setjmp | |
1263 | && optimize_function_for_speed_p (fun) | |
1264 | && dbg_cnt (store_motion); | |
1265 | } | |
1266 | ||
27a4cd48 DM |
1267 | } // anon namespace |
1268 | ||
1269 | rtl_opt_pass * | |
1270 | make_pass_rtl_store_motion (gcc::context *ctxt) | |
1271 | { | |
1272 | return new pass_rtl_store_motion (ctxt); | |
1273 | } |