[thirdparty/gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / pcs / saves_1_be_nowrap.c

/* { dg-do compile } */
/* { dg-options "-O -mbig-endian -fno-shrink-wrap -fno-stack-clash-protection -g" } */
/* { dg-final { check-function-bodies "**" "" } } */

#pragma GCC aarch64 "arm_sve.h"

/*
** test_1:
**	addvl	sp, sp, #-18
**	str	p4, \[sp\]
**	str	p5, \[sp, #1, mul vl\]
**	str	p6, \[sp, #2, mul vl\]
**	str	p7, \[sp, #3, mul vl\]
**	str	p8, \[sp, #4, mul vl\]
**	str	p9, \[sp, #5, mul vl\]
**	str	p10, \[sp, #6, mul vl\]
**	str	p11, \[sp, #7, mul vl\]
**	str	p12, \[sp, #8, mul vl\]
**	str	p13, \[sp, #9, mul vl\]
**	str	p14, \[sp, #10, mul vl\]
**	str	p15, \[sp, #11, mul vl\]
**	ptrue	p1\.b, all
**	st1d	z8\.d, p1, \[sp, #2, mul vl\]
**	st1d	z9\.d, p1, \[sp, #3, mul vl\]
**	st1d	z10\.d, p1, \[sp, #4, mul vl\]
**	st1d	z11\.d, p1, \[sp, #5, mul vl\]
**	st1d	z12\.d, p1, \[sp, #6, mul vl\]
**	st1d	z13\.d, p1, \[sp, #7, mul vl\]
**	addvl	x11, sp, #16
**	st1d	z14\.d, p1, \[x11, #-8, mul vl\]
**	st1d	z15\.d, p1, \[x11, #-7, mul vl\]
**	str	z16, \[sp, #10, mul vl\]
**	str	z17, \[sp, #11, mul vl\]
**	str	z18, \[sp, #12, mul vl\]
**	str	z19, \[sp, #13, mul vl\]
**	str	z20, \[sp, #14, mul vl\]
**	str	z21, \[sp, #15, mul vl\]
**	str	z22, \[sp, #16, mul vl\]
**	str	z23, \[sp, #17, mul vl\]
**	ptrue	p0\.b, all
**	ptrue	p1\.b, all
**	ld1d	z8\.d, p1/z, \[sp, #2, mul vl\]
**	ld1d	z9\.d, p1/z, \[sp, #3, mul vl\]
**	ld1d	z10\.d, p1/z, \[sp, #4, mul vl\]
**	ld1d	z11\.d, p1/z, \[sp, #5, mul vl\]
**	ld1d	z12\.d, p1/z, \[sp, #6, mul vl\]
**	ld1d	z13\.d, p1/z, \[sp, #7, mul vl\]
**	addvl	x11, sp, #16
**	ld1d	z14\.d, p1/z, \[x11, #-8, mul vl\]
**	ld1d	z15\.d, p1/z, \[x11, #-7, mul vl\]
**	ldr	z16, \[sp, #10, mul vl\]
**	ldr	z17, \[sp, #11, mul vl\]
**	ldr	z18, \[sp, #12, mul vl\]
**	ldr	z19, \[sp, #13, mul vl\]
**	ldr	z20, \[sp, #14, mul vl\]
**	ldr	z21, \[sp, #15, mul vl\]
**	ldr	z22, \[sp, #16, mul vl\]
**	ldr	z23, \[sp, #17, mul vl\]
**	ldr	p4, \[sp\]
**	ldr	p5, \[sp, #1, mul vl\]
**	ldr	p6, \[sp, #2, mul vl\]
**	ldr	p7, \[sp, #3, mul vl\]
**	ldr	p8, \[sp, #4, mul vl\]
**	ldr	p9, \[sp, #5, mul vl\]
**	ldr	p10, \[sp, #6, mul vl\]
**	ldr	p11, \[sp, #7, mul vl\]
**	ldr	p12, \[sp, #8, mul vl\]
**	ldr	p13, \[sp, #9, mul vl\]
**	ldr	p14, \[sp, #10, mul vl\]
**	ldr	p15, \[sp, #11, mul vl\]
**	addvl	sp, sp, #18
**	ret
*/
svbool_t
test_1 (void)
{
  asm volatile ("" :::
		"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
		"z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15",
		"z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23",
		"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
		"p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
		"p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15");
  return svptrue_b8 ();
}

/*
** test_2:
**	ptrue	p0\.b, all
**	ret
*/
svbool_t
test_2 (void)
{
  asm volatile ("" :::
		"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
		"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
		"p0", "p1", "p2", "p3");
  return svptrue_b8 ();
}

/*
** test_3:
**	addvl	sp, sp, #-6
**	str	p5, \[sp\]
**	str	p6, \[sp, #1, mul vl\]
**	str	p11, \[sp, #2, mul vl\]
**	ptrue	p1\.b, all
**	st1d	z8\.d, p1, \[sp, #1, mul vl\]
**	st1d	z13\.d, p1, \[sp, #2, mul vl\]
**	str	z19, \[sp, #3, mul vl\]
**	str	z20, \[sp, #4, mul vl\]
**	str	z22, \[sp, #5, mul vl\]
**	ptrue	p0\.b, all
**	ptrue	p1\.b, all
**	ld1d	z8\.d, p1/z, \[sp, #1, mul vl\]
**	ld1d	z13\.d, p1/z, \[sp, #2, mul vl\]
**	ldr	z19, \[sp, #3, mul vl\]
**	ldr	z20, \[sp, #4, mul vl\]
**	ldr	z22, \[sp, #5, mul vl\]
**	ldr	p5, \[sp\]
**	ldr	p6, \[sp, #1, mul vl\]
**	ldr	p11, \[sp, #2, mul vl\]
**	addvl	sp, sp, #6
**	ret
*/
svbool_t
test_3 (void)
{
  asm volatile ("" :::
		"z8", "z13", "z19", "z20", "z22",
		"p5", "p6", "p11");
  return svptrue_b8 ();
}

/*
** test_4:
**	addvl	sp, sp, #-1
**	str	p4, \[sp\]
**	ptrue	p0\.b, all
**	ldr	p4, \[sp\]
**	addvl	sp, sp, #1
**	ret
*/
svbool_t
test_4 (void)
{
  asm volatile ("" ::: "p4");
  return svptrue_b8 ();
}

/*
** test_5:
**	addvl	sp, sp, #-1
**	ptrue	p1\.b, all
**	st1d	z15\.d, p1, \[sp\]
**	ptrue	p0\.b, all
**	ptrue	p1\.b, all
**	ld1d	z15\.d, p1/z, \[sp\]
**	addvl	sp, sp, #1
**	ret
*/
svbool_t
test_5 (void)
{
  asm volatile ("" ::: "z15");
  return svptrue_b8 ();
}

/*
** test_6:
**	addvl	sp, sp, #-2
**	str	p4, \[sp\]
**	ptrue	p4\.b, all
**	st1d	z15\.d, p4, \[sp, #1, mul vl\]
**	mov	z0\.b, #1
**	ptrue	p4\.b, all
**	ld1d	z15\.d, p4/z, \[sp, #1, mul vl\]
**	ldr	p4, \[sp\]
**	addvl	sp, sp, #2
**	ret
*/
svint8_t
test_6 (svbool_t p0, svbool_t p1, svbool_t p2, svbool_t p3)
{
  asm volatile ("" :: "Upa" (p0), "Upa" (p1), "Upa" (p2), "Upa" (p3) : "z15");
  return svdup_s8 (1);
}

/*
** test_7:
**	addvl	sp, sp, #-1
**	str	z16, \[sp\]
**	ptrue	p0\.b, all
**	ldr	z16, \[sp\]
**	addvl	sp, sp, #1
**	ret
*/
svbool_t
test_7 (void)
{
  asm volatile ("" ::: "z16");
  return svptrue_b8 ();
}
Commit	Line	Data
c600df9a RS	1	/* { dg-do compile } */
	2	/* { dg-options "-O -mbig-endian -fno-shrink-wrap -fno-stack-clash-protection -g" } */
	3	/* { dg-final { check-function-bodies "*" "" } } /
	4
	5	#pragma GCC aarch64 "arm_sve.h"
	6
	7	/*
	8	** test_1:
cb26919c	9	** addvl sp, sp, #-18
c600df9a RS	10	** str p4, \[sp\]
	11	** str p5, \[sp, #1, mul vl\]
	12	** str p6, \[sp, #2, mul vl\]
	13	** str p7, \[sp, #3, mul vl\]
	14	** str p8, \[sp, #4, mul vl\]
	15	** str p9, \[sp, #5, mul vl\]
	16	** str p10, \[sp, #6, mul vl\]
	17	** str p11, \[sp, #7, mul vl\]
cb26919c RS	18	** str p12, \[sp, #8, mul vl\]
	19	** str p13, \[sp, #9, mul vl\]
	20	** str p14, \[sp, #10, mul vl\]
	21	** str p15, \[sp, #11, mul vl\]
c600df9a	22	** ptrue p1\.b, all
cb26919c RS	23	** st1d z8\.d, p1, \[sp, #2, mul vl\]
	24	** st1d z9\.d, p1, \[sp, #3, mul vl\]
	25	** st1d z10\.d, p1, \[sp, #4, mul vl\]
	26	** st1d z11\.d, p1, \[sp, #5, mul vl\]
	27	** st1d z12\.d, p1, \[sp, #6, mul vl\]
	28	** st1d z13\.d, p1, \[sp, #7, mul vl\]
c600df9a	29	** addvl x11, sp, #16
cb26919c RS	30	** st1d z14\.d, p1, \[x11, #-8, mul vl\]
	31	** st1d z15\.d, p1, \[x11, #-7, mul vl\]
	32	** str z16, \[sp, #10, mul vl\]
	33	** str z17, \[sp, #11, mul vl\]
	34	** str z18, \[sp, #12, mul vl\]
	35	** str z19, \[sp, #13, mul vl\]
	36	** str z20, \[sp, #14, mul vl\]
	37	** str z21, \[sp, #15, mul vl\]
	38	** str z22, \[sp, #16, mul vl\]
	39	** str z23, \[sp, #17, mul vl\]
c600df9a RS	40	** ptrue p0\.b, all
c600df9a RS	41	** ptrue p1\.b, all
cb26919c RS	42	** ld1d z8\.d, p1/z, \[sp, #2, mul vl\]
	43	** ld1d z9\.d, p1/z, \[sp, #3, mul vl\]
	44	** ld1d z10\.d, p1/z, \[sp, #4, mul vl\]
	45	** ld1d z11\.d, p1/z, \[sp, #5, mul vl\]
	46	** ld1d z12\.d, p1/z, \[sp, #6, mul vl\]
	47	** ld1d z13\.d, p1/z, \[sp, #7, mul vl\]
c600df9a	48	** addvl x11, sp, #16
cb26919c RS	49	** ld1d z14\.d, p1/z, \[x11, #-8, mul vl\]
	50	** ld1d z15\.d, p1/z, \[x11, #-7, mul vl\]
	51	** ldr z16, \[sp, #10, mul vl\]
	52	** ldr z17, \[sp, #11, mul vl\]
	53	** ldr z18, \[sp, #12, mul vl\]
	54	** ldr z19, \[sp, #13, mul vl\]
	55	** ldr z20, \[sp, #14, mul vl\]
	56	** ldr z21, \[sp, #15, mul vl\]
	57	** ldr z22, \[sp, #16, mul vl\]
	58	** ldr z23, \[sp, #17, mul vl\]
c600df9a RS	59	** ldr p4, \[sp\]
	60	** ldr p5, \[sp, #1, mul vl\]
	61	** ldr p6, \[sp, #2, mul vl\]
	62	** ldr p7, \[sp, #3, mul vl\]
	63	** ldr p8, \[sp, #4, mul vl\]
	64	** ldr p9, \[sp, #5, mul vl\]
	65	** ldr p10, \[sp, #6, mul vl\]
	66	** ldr p11, \[sp, #7, mul vl\]
cb26919c RS	67	** ldr p12, \[sp, #8, mul vl\]
	68	** ldr p13, \[sp, #9, mul vl\]
	69	** ldr p14, \[sp, #10, mul vl\]
	70	** ldr p15, \[sp, #11, mul vl\]
	71	** addvl sp, sp, #18
c600df9a RS	72	** ret
	73	*/
	74	svbool_t
	75	test_1 (void)
	76	{
	77	asm volatile ("" :::
	78	"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
	79	"z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15",
	80	"z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23",
	81	"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
	82	"p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
	83	"p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15");
	84	return svptrue_b8 ();
	85	}
	86
	87	/*
	88	** test_2:
	89	** ptrue p0\.b, all
	90	** ret
	91	*/
	92	svbool_t
	93	test_2 (void)
	94	{
	95	asm volatile ("" :::
	96	"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
	97	"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
cb26919c	98	"p0", "p1", "p2", "p3");
c600df9a RS	99	return svptrue_b8 ();
	100	}
	101
	102	/*
	103	** test_3:
	104	** addvl sp, sp, #-6
	105	** str p5, \[sp\]
	106	** str p6, \[sp, #1, mul vl\]
	107	** str p11, \[sp, #2, mul vl\]
	108	** ptrue p1\.b, all
	109	** st1d z8\.d, p1, \[sp, #1, mul vl\]
	110	** st1d z13\.d, p1, \[sp, #2, mul vl\]
	111	** str z19, \[sp, #3, mul vl\]
	112	** str z20, \[sp, #4, mul vl\]
	113	** str z22, \[sp, #5, mul vl\]
	114	** ptrue p0\.b, all
	115	** ptrue p1\.b, all
	116	** ld1d z8\.d, p1/z, \[sp, #1, mul vl\]
	117	** ld1d z13\.d, p1/z, \[sp, #2, mul vl\]
	118	** ldr z19, \[sp, #3, mul vl\]
	119	** ldr z20, \[sp, #4, mul vl\]
	120	** ldr z22, \[sp, #5, mul vl\]
	121	** ldr p5, \[sp\]
	122	** ldr p6, \[sp, #1, mul vl\]
	123	** ldr p11, \[sp, #2, mul vl\]
	124	** addvl sp, sp, #6
	125	** ret
	126	*/
	127	svbool_t
	128	test_3 (void)
	129	{
	130	asm volatile ("" :::
	131	"z8", "z13", "z19", "z20", "z22",
	132	"p5", "p6", "p11");
	133	return svptrue_b8 ();
	134	}
	135
	136	/*
	137	** test_4:
	138	** addvl sp, sp, #-1
	139	** str p4, \[sp\]
	140	** ptrue p0\.b, all
	141	** ldr p4, \[sp\]
	142	** addvl sp, sp, #1
	143	** ret
	144	*/
	145	svbool_t
	146	test_4 (void)
	147	{
	148	asm volatile ("" ::: "p4");
	149	return svptrue_b8 ();
	150	}
	151
	152	/*
	153	** test_5:
	154	** addvl sp, sp, #-1
	155	** ptrue p1\.b, all
	156	** st1d z15\.d, p1, \[sp\]
	157	** ptrue p0\.b, all
	158	** ptrue p1\.b, all
	159	** ld1d z15\.d, p1/z, \[sp\]
	160	** addvl sp, sp, #1
	161	** ret
	162	*/
163	svbool_t
164	test_5 (void)
165	{
166	asm volatile ("" ::: "z15");
167	return svptrue_b8 ();
168	}
169
170	/*
171	** test_6:
172	** addvl sp, sp, #-2
173	** str p4, \[sp\]
174	** ptrue p4\.b, all
175	** st1d z15\.d, p4, \[sp, #1, mul vl\]
176	** mov z0\.b, #1
177	** ptrue p4\.b, all
178	** ld1d z15\.d, p4/z, \[sp, #1, mul vl\]
179	** ldr p4, \[sp\]
180	** addvl sp, sp, #2
181	** ret
182	*/
183	svint8_t
184	test_6 (svbool_t p0, svbool_t p1, svbool_t p2, svbool_t p3)
185	{
186	asm volatile ("" :: "Upa" (p0), "Upa" (p1), "Upa" (p2), "Upa" (p3) : "z15");
187	return svdup_s8 (1);
188	}
189
190	/*
191	** test_7:
192	** addvl sp, sp, #-1
193	** str z16, \[sp\]
194	** ptrue p0\.b, all
195	** ldr z16, \[sp\]
196	** addvl sp, sp, #1
197	** ret
198	*/
199	svbool_t
200	test_7 (void)
201	{
202	asm volatile ("" ::: "z16");
203	return svptrue_b8 ();
204	}