[thirdparty/gcc.git] / gcc / testsuite / gcc.target / arm / neon / vld3Qu32.c

/* Test the `vld3Qu32' ARM Neon intrinsic.  */
/* This file was autogenerated by neon-testgen.  */

/* { dg-do assemble } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O0" } */
/* { dg-add-options arm_neon } */

#include "arm_neon.h"

void test_vld3Qu32 (void)
{
  uint32x4x3_t out_uint32x4x3_t;

  out_uint32x4x3_t = vld3q_u32 (0);
}

/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
Commit	Line	Data
88f77cba JB	1	/* Test the `vld3Qu32' ARM Neon intrinsic. */
	2	/* This file was autogenerated by neon-testgen. */
	3
	4	/* { dg-do assemble } */
	5	/* { dg-require-effective-target arm_neon_ok } */
0c422e74 DJ	6	/* { dg-options "-save-temps -O0" } */
0c422e74 DJ	7	/* { dg-add-options arm_neon } */
88f77cba JB	8
	9	#include "arm_neon.h"
	10
	11	void test_vld3Qu32 (void)
	12	{
	13	uint32x4x3_t out_uint32x4x3_t;
	14
	15	out_uint32x4x3_t = vld3q_u32 (0);
	16	}
	17
6308e208 RS	18	/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)\|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6308e208 RS	19	/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)\|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */