[thirdparty/gcc.git] / gcc / testsuite / gcc.target / riscv / rvv / autovec / vls-vlmax / vec_extract-2.c

/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */

#include <stdint-gcc.h>

typedef int64_t vnx4di __attribute__((vector_size (32)));
typedef int32_t vnx8si __attribute__((vector_size (32)));
typedef int16_t vnx16hi __attribute__((vector_size (32)));
typedef int8_t vnx32qi __attribute__((vector_size (32)));
typedef _Float16 vnx16hf __attribute__((vector_size (32)));
typedef float vnx8sf __attribute__((vector_size (32)));
typedef double vnx4df __attribute__((vector_size (32)));

#define VEC_EXTRACT(S,V,IDX)			\
  S						\
  __attribute__((noipa))			\
  vec_extract_##V##_##IDX (V v)			\
  {						\
    return v[IDX];				\
  }

#define VEC_EXTRACT_VAR2(S,V)			\
  S						\
  __attribute__((noipa))			\
  vec_extract_var_##V (V v, int16_t idx)	\
  {						\
    return v[idx];				\
  }

#define TEST_ALL2(T)				\
  T (_Float16, vnx16hf, 0)			\
  T (_Float16, vnx16hf, 3)			\
  T (_Float16, vnx16hf, 7)			\
  T (_Float16, vnx16hf, 8)			\
  T (_Float16, vnx16hf, 15)			\
  T (float, vnx8sf, 0)				\
  T (float, vnx8sf, 1)				\
  T (float, vnx8sf, 3)				\
  T (float, vnx8sf, 4)				\
  T (float, vnx8sf, 7)				\
  T (double, vnx4df, 0)				\
  T (double, vnx4df, 1)				\
  T (double, vnx4df, 2)				\
  T (double, vnx4df, 3)				\
  T (int64_t, vnx4di, 0)			\
  T (int64_t, vnx4di, 1)			\
  T (int64_t, vnx4di, 2)			\
  T (int64_t, vnx4di, 3)			\
  T (int32_t, vnx8si, 0)			\
  T (int32_t, vnx8si, 1)			\
  T (int32_t, vnx8si, 3)			\
  T (int32_t, vnx8si, 4)			\
  T (int32_t, vnx8si, 7)			\
  T (int16_t, vnx16hi, 0)			\
  T (int16_t, vnx16hi, 1)			\
  T (int16_t, vnx16hi, 7)			\
  T (int16_t, vnx16hi, 8)			\
  T (int16_t, vnx16hi, 15)			\
  T (int8_t, vnx32qi, 0)			\
  T (int8_t, vnx32qi, 1)			\
  T (int8_t, vnx32qi, 15)			\
  T (int8_t, vnx32qi, 16)			\
  T (int8_t, vnx32qi, 31)			\

#define TEST_ALL_VAR2(T)			\
  T (_Float16, vnx16hf)				\
  T (float, vnx8sf)				\
  T (double, vnx4df)				\
  T (int64_t, vnx4di)				\
  T (int32_t, vnx8si)				\
  T (int16_t, vnx16hi)				\
  T (int8_t, vnx32qi)				\

TEST_ALL2 (VEC_EXTRACT)
TEST_ALL_VAR2 (VEC_EXTRACT_VAR2)

/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m2,\s*ta,\s*ma} 6 } } */
/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m2,\s*ta,\s*ma} 12 } } */
/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m2,\s*ta,\s*ma} 12 } } */
/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m2,\s*ta,\s*ma} 10 } } */

/* { dg-final { scan-assembler-times {\tvslidedown.vi} 26 } } */
/* { dg-final { scan-assembler-times {\tvslidedown.vx} 7 } } */

/* { dg-final { scan-assembler-times {\tvfmv.f.s} 17 } } */
/* { dg-final { scan-assembler-times {\tvmv.x.s} 23 } } */

/* { dg-final { scan-assembler-not {\tsext} } } */
Commit	Line	Data
51795b91	1	/* { dg-do compile } */
649c640c	2	/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
51795b91 RD	3
	4	#include <stdint-gcc.h>
	5
	6	typedef int64_t vnx4di __attribute__((vector_size (32)));
	7	typedef int32_t vnx8si __attribute__((vector_size (32)));
	8	typedef int16_t vnx16hi __attribute__((vector_size (32)));
	9	typedef int8_t vnx32qi __attribute__((vector_size (32)));
	10	typedef _Float16 vnx16hf __attribute__((vector_size (32)));
	11	typedef float vnx8sf __attribute__((vector_size (32)));
	12	typedef double vnx4df __attribute__((vector_size (32)));
	13
	14	#define VEC_EXTRACT(S,V,IDX) \
	15	S \
	16	__attribute__((noipa)) \
	17	vec_extract_##V##_##IDX (V v) \
	18	{ \
	19	return v[IDX]; \
	20	}
	21
573bb719 RD	22	#define VEC_EXTRACT_VAR2(S,V) \
	23	S \
	24	__attribute__((noipa)) \
	25	vec_extract_var_##V (V v, int16_t idx) \
	26	{ \
	27	return v[idx]; \
	28	}
	29
51795b91 RD	30	#define TEST_ALL2(T) \
	31	T (_Float16, vnx16hf, 0) \
	32	T (_Float16, vnx16hf, 3) \
	33	T (_Float16, vnx16hf, 7) \
	34	T (_Float16, vnx16hf, 8) \
	35	T (_Float16, vnx16hf, 15) \
	36	T (float, vnx8sf, 0) \
	37	T (float, vnx8sf, 1) \
	38	T (float, vnx8sf, 3) \
	39	T (float, vnx8sf, 4) \
	40	T (float, vnx8sf, 7) \
	41	T (double, vnx4df, 0) \
	42	T (double, vnx4df, 1) \
	43	T (double, vnx4df, 2) \
	44	T (double, vnx4df, 3) \
	45	T (int64_t, vnx4di, 0) \
	46	T (int64_t, vnx4di, 1) \
	47	T (int64_t, vnx4di, 2) \
	48	T (int64_t, vnx4di, 3) \
	49	T (int32_t, vnx8si, 0) \
	50	T (int32_t, vnx8si, 1) \
	51	T (int32_t, vnx8si, 3) \
	52	T (int32_t, vnx8si, 4) \
	53	T (int32_t, vnx8si, 7) \
	54	T (int16_t, vnx16hi, 0) \
	55	T (int16_t, vnx16hi, 1) \
	56	T (int16_t, vnx16hi, 7) \
	57	T (int16_t, vnx16hi, 8) \
	58	T (int16_t, vnx16hi, 15) \
	59	T (int8_t, vnx32qi, 0) \
	60	T (int8_t, vnx32qi, 1) \
	61	T (int8_t, vnx32qi, 15) \
	62	T (int8_t, vnx32qi, 16) \
	63	T (int8_t, vnx32qi, 31) \
	64
573bb719 RD	65	#define TEST_ALL_VAR2(T) \
	66	T (_Float16, vnx16hf) \
	67	T (float, vnx8sf) \
	68	T (double, vnx4df) \
	69	T (int64_t, vnx4di) \
	70	T (int32_t, vnx8si) \
	71	T (int16_t, vnx16hi) \
	72	T (int8_t, vnx32qi) \
	73
51795b91	74	TEST_ALL2 (VEC_EXTRACT)
573bb719	75	TEST_ALL_VAR2 (VEC_EXTRACT_VAR2)
51795b91	76
573bb719 RD	77	/* { dg-final { scan-assembler-times {vset[i]vli\s+[a-z0-9,]+,\se8,\sm2,\sta,\sma} 6 } } /
	78	/* { dg-final { scan-assembler-times {vset[i]vli\s+[a-z0-9,]+,\se16,\sm2,\sta,\sma} 12 } } /
	79	/* { dg-final { scan-assembler-times {vset[i]vli\s+[a-z0-9,]+,\se32,\sm2,\sta,\sma} 12 } } /
	80	/* { dg-final { scan-assembler-times {vset[i]vli\s+[a-z0-9,]+,\se64,\sm2,\sta,\sma} 10 } } /
51795b91 RD	81
51795b91 RD	82	/* { dg-final { scan-assembler-times {\tvslidedown.vi} 26 } } */
573bb719	83	/* { dg-final { scan-assembler-times {\tvslidedown.vx} 7 } } */
51795b91	84
573bb719 RD	85	/* { dg-final { scan-assembler-times {\tvfmv.f.s} 17 } } */
573bb719 RD	86	/* { dg-final { scan-assembler-times {\tvmv.x.s} 23 } } */
9b24611a RD	87
9b24611a RD	88	/* { dg-final { scan-assembler-not {\tsext} } } */