projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| a20b27a3 SR |
1 | /* |
| 2 | * (C) Copyright 2001 | |
| 3 | * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. | |
| 4 | * | |
| 3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| a20b27a3 SR |
6 | */ |
| 7 | ||
| 8 | /* | |
| 9 | * board/config.h - configuration options, board specific | |
| 10 | */ | |
| 11 | ||
| 12 | /************************************************************************* | |
| 13 | * (c) 2004 esd gmbh Hannover | |
| 14 | * | |
| 15 | * | |
| 16 | * from db64360.h file | |
| 17 | * by Reinhard Arlt reinhard.arlt@esd-electronics.com | |
| 18 | * | |
| 19 | ************************************************************************/ | |
| 20 | ||
| 21 | ||
| 22 | #ifndef __CONFIG_H | |
| 23 | #define __CONFIG_H | |
| 24 | ||
| a20b27a3 SR |
25 | /* This define must be before the core.h include */ |
| 26 | #define CONFIG_CPCI750 1 /* this is an CPCI750 board */ | |
| 27 | ||
| 28 | #ifndef __ASSEMBLY__ | |
| 29 | #include <../board/Marvell/include/core.h> | |
| 30 | #endif | |
| 31 | /*-----------------------------------------------------*/ | |
| 32 | ||
| 33 | #include "../board/esd/cpci750/local.h" | |
| 34 | ||
| 35 | /* | |
| 36 | * High Level Configuration Options | |
| 37 | * (easy to change) | |
| 38 | */ | |
| 39 | ||
| 40 | #define CONFIG_750FX /* we have a 750FX (override local.h) */ | |
| 41 | ||
| 42 | #define CONFIG_CPCI750 1 /* this is an CPCI750 board */ | |
| 43 | ||
| 2ae18241 WD |
44 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
| 45 | ||
| bfc81252 | 46 | #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ |
| a20b27a3 | 47 | |
| 0738e24e | 48 | #define CONFIG_MV64360_ECC /* enable ECC support */ |
| a20b27a3 | 49 | |
| 31d82672 BB |
50 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 51 | ||
| a20b27a3 SR |
52 | /* which initialization functions to call for this board */ |
| 53 | #define CONFIG_MISC_INIT_R | |
| 54 | #define CONFIG_BOARD_PRE_INIT | |
| 55 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
| 56 | ||
| 6d0f6bcf | 57 | #define CONFIG_SYS_BOARD_NAME "CPCI750" |
| a20b27a3 SR |
58 | #define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX" |
| 59 | ||
| 6d0f6bcf JCPV |
60 | /*#define CONFIG_SYS_HUSH_PARSER*/ |
| 61 | #define CONFIG_SYS_HUSH_PARSER | |
| a20b27a3 | 62 | |
| a20b27a3 | 63 | |
| 0a14d6b8 SR |
64 | #define CONFIG_CMDLINE_EDITING /* add command line history */ |
| 65 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
| a7b9fb91 | 66 | |
| a20b27a3 | 67 | /* Define which ETH port will be used for connecting the network */ |
| 6d0f6bcf | 68 | #define CONFIG_SYS_ETH_PORT ETH_0 |
| a20b27a3 SR |
69 | |
| 70 | /* | |
| 71 | * The following defines let you select what serial you want to use | |
| 72 | * for your console driver. | |
| 73 | * | |
| 74 | * what to do: | |
| bfc81252 | 75 | * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial |
| 6d0f6bcf | 76 | * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 |
| a20b27a3 SR |
77 | * to 0 below. |
| 78 | * | |
| 79 | * to use the MPSC, #define CONFIG_MPSC. If you have wired up another | |
| 80 | * mpsc channel, change CONFIG_MPSC_PORT to the desired value. | |
| 81 | */ | |
| bfc81252 | 82 | #define CONFIG_MPSC |
| a20b27a3 SR |
83 | #define CONFIG_MPSC_PORT 0 |
| 84 | ||
| 85 | /* to change the default ethernet port, use this define (options: 0, 1, 2) */ | |
| bfc81252 | 86 | #define MV_ETH_DEVS 1 |
| a20b27a3 SR |
87 | #define CONFIG_ETHER_PORT 0 |
| 88 | ||
| 89 | #undef CONFIG_ETHER_PORT_MII /* use RMII */ | |
| 90 | ||
| 91 | #define CONFIG_BOOTDELAY 5 /* autoboot disabled */ | |
| 92 | ||
| 93 | #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ | |
| 94 | ||
| 95 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
| 96 | ||
| 97 | ||
| 98 | #undef CONFIG_BOOTARGS | |
| 99 | ||
| 100 | /* ----------------------------------------------------------------------------- | |
| 101 | * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus | |
| 102 | */ | |
| 103 | ||
| 104 | #define CONFIG_IPADDR "192.168.0.185" | |
| 105 | ||
| 106 | #define CONFIG_SERIAL "AA000001" | |
| 107 | #define CONFIG_SERVERIP "10.0.0.79" | |
| bfc81252 | 108 | #define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" |
| a20b27a3 SR |
109 | |
| 110 | #define CONFIG_TESTDRAMDATA y | |
| bfc81252 | 111 | #define CONFIG_TESTDRAMADDRESS n |
| a20b27a3 SR |
112 | #define CONFIG_TESETDRAMWALK n |
| 113 | ||
| 114 | /* ----------------------------------------------------------------------------- */ | |
| 115 | ||
| 116 | ||
| bfc81252 | 117 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
| 6d0f6bcf | 118 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ |
| a20b27a3 SR |
119 | |
| 120 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| bfc81252 | 121 | #undef CONFIG_ALTIVEC /* undef to disable */ |
| a20b27a3 | 122 | |
| 5d2ebe1b JL |
123 | /* |
| 124 | * BOOTP options | |
| 125 | */ | |
| 126 | #define CONFIG_BOOTP_SUBNETMASK | |
| 127 | #define CONFIG_BOOTP_GATEWAY | |
| 128 | #define CONFIG_BOOTP_HOSTNAME | |
| 129 | #define CONFIG_BOOTP_BOOTPATH | |
| 130 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| a20b27a3 SR |
131 | |
| 132 | ||
| 49cf7e8e JL |
133 | /* |
| 134 | * Command line configuration. | |
| 135 | */ | |
| 136 | #include <config_cmd_default.h> | |
| 137 | ||
| 5728be38 WD |
138 | #define CONFIG_CMD_ASKENV |
| 139 | #define CONFIG_CMD_I2C | |
| 140 | #define CONFIG_CMD_CACHE | |
| 141 | #define CONFIG_CMD_EEPROM | |
| 142 | #define CONFIG_CMD_PCI | |
| 143 | #define CONFIG_CMD_ELF | |
| 144 | #define CONFIG_CMD_DATE | |
| 145 | #define CONFIG_CMD_NET | |
| 146 | #define CONFIG_CMD_PING | |
| 147 | #define CONFIG_CMD_IDE | |
| 148 | #define CONFIG_CMD_FAT | |
| 149 | #define CONFIG_CMD_EXT2 | |
| a20b27a3 | 150 | |
| a20b27a3 | 151 | |
| 49cf7e8e | 152 | #define CONFIG_DOS_PARTITION |
| a20b27a3 | 153 | |
| a7b9fb91 SR |
154 | #define CONFIG_USE_CPCIDVI |
| 155 | ||
| bfc81252 | 156 | #ifdef CONFIG_USE_CPCIDVI |
| a7b9fb91 SR |
157 | #define CONFIG_VIDEO |
| 158 | #define CONFIG_VIDEO_CT69000 | |
| 159 | #define CONFIG_CFB_CONSOLE | |
| 160 | #define CONFIG_VIDEO_SW_CURSOR | |
| 161 | #define CONFIG_VIDEO_LOGO | |
| 162 | #define CONFIG_I8042_KBD | |
| 6d0f6bcf | 163 | #define CONFIG_SYS_ISA_IO 0 |
| a7b9fb91 SR |
164 | #endif |
| 165 | ||
| a20b27a3 SR |
166 | /* |
| 167 | * Miscellaneous configurable options | |
| 168 | */ | |
| 6d0f6bcf JCPV |
169 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
| 170 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
| 171 | #define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed default */ | |
| a20b27a3 | 172 | |
| 2b224609 RA |
173 | #define CONFIG_PRAM 0 |
| 174 | ||
| 6d0f6bcf JCPV |
175 | #define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ |
| 176 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 177 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 49cf7e8e | 178 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 179 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| a20b27a3 | 180 | #else |
| 6d0f6bcf | 181 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| a20b27a3 | 182 | #endif |
| 6d0f6bcf JCPV |
183 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 184 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 185 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| a20b27a3 | 186 | |
| 6d0f6bcf JCPV |
187 | /*#define CONFIG_SYS_MEMTEST_START 0x00400000*/ /* memtest works on */ |
| 188 | /*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ | |
| 189 | /*#define CONFIG_SYS_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ | |
| a20b27a3 SR |
190 | |
| 191 | /* | |
| 6d0f6bcf | 192 | #define CONFIG_SYS_DRAM_TEST |
| a20b27a3 | 193 | * DRAM tests |
| 6d0f6bcf | 194 | * CONFIG_SYS_DRAM_TEST - enables the following tests. |
| a20b27a3 | 195 | * |
| 6d0f6bcf | 196 | * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines |
| bfc81252 WD |
197 | * Environment variable 'test_dram_data' must be |
| 198 | * set to 'y'. | |
| 6d0f6bcf | 199 | * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely |
| bfc81252 WD |
200 | * addressable. Environment variable |
| 201 | * 'test_dram_address' must be set to 'y'. | |
| 6d0f6bcf | 202 | * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. |
| bfc81252 WD |
203 | * This test takes about 6 minutes to test 64 MB. |
| 204 | * Environment variable 'test_dram_walk' must be | |
| 205 | * set to 'y'. | |
| a20b27a3 | 206 | */ |
| 6d0f6bcf JCPV |
207 | #define CONFIG_SYS_DRAM_TEST |
| 208 | #if defined(CONFIG_SYS_DRAM_TEST) | |
| 209 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ | |
| 210 | /*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ | |
| 211 | #define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ | |
| 212 | #define CONFIG_SYS_DRAM_TEST_DATA | |
| 213 | #define CONFIG_SYS_DRAM_TEST_ADDRESS | |
| 214 | #define CONFIG_SYS_DRAM_TEST_WALK | |
| 215 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
| a20b27a3 SR |
216 | |
| 217 | #define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ | |
| 6d0f6bcf | 218 | #undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ |
| a20b27a3 | 219 | |
| 6d0f6bcf | 220 | #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ |
| a20b27a3 | 221 | |
| 6d0f6bcf | 222 | #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ |
| ee80fa7b | 223 | #define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ |
| a20b27a3 | 224 | |
| 6d0f6bcf | 225 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
| a20b27a3 | 226 | |
| 6d0f6bcf | 227 | #define CONFIG_SYS_TCLK 133000000 |
| a20b27a3 | 228 | |
| a20b27a3 SR |
229 | /* |
| 230 | * Low Level Configuration Settings | |
| 231 | * (address mappings, register initial values, etc.) | |
| 232 | * You should know what you are doing if you make changes here. | |
| 233 | */ | |
| 234 | ||
| 235 | /*----------------------------------------------------------------------- | |
| 236 | * Definitions for initial stack pointer and data area | |
| 237 | */ | |
| 238 | ||
| 239 | /* | |
| 6d0f6bcf | 240 | * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS |
| a20b27a3 SR |
241 | * To an unused memory region. The stack will remain in cache until RAM |
| 242 | * is initialized | |
| 243 | */ | |
| 6d0f6bcf JCPV |
244 | #undef CONFIG_SYS_INIT_RAM_LOCK |
| 245 | /* #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ | |
| 246 | /* #define CONFIG_SYS_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ | |
| 247 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ | |
| 553f0982 | 248 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
| 25ddd1fb | 249 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| a20b27a3 SR |
250 | |
| 251 | #define RELOCATE_INTERNAL_RAM_ADDR | |
| 252 | #ifdef RELOCATE_INTERNAL_RAM_ADDR | |
| 6d0f6bcf JCPV |
253 | /*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/ |
| 254 | #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf1080000 | |
| a20b27a3 SR |
255 | #endif |
| 256 | ||
| 257 | /*----------------------------------------------------------------------- | |
| 258 | * Start addresses for the final memory configuration | |
| 259 | * (Set up by the startup code) | |
| 6d0f6bcf | 260 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| a20b27a3 | 261 | */ |
| 6d0f6bcf | 262 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| a20b27a3 | 263 | /* Dummies for BAT 4-7 */ |
| 6d0f6bcf JCPV |
264 | #define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ |
| 265 | #define CONFIG_SYS_SDRAM2_BASE 0x20000000 | |
| 266 | #define CONFIG_SYS_SDRAM3_BASE 0x30000000 | |
| 267 | #define CONFIG_SYS_SDRAM4_BASE 0x40000000 | |
| 268 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 | |
| 269 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 270 | #define CONFIG_SYS_MONITOR_BASE 0xfff00000 | |
| 271 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ | |
| a20b27a3 SR |
272 | |
| 273 | /*----------------------------------------------------------------------- | |
| 274 | * FLASH related | |
| 275 | *----------------------------------------------------------------------*/ | |
| 276 | ||
| 00b1883a | 277 | #define CONFIG_FLASH_CFI_DRIVER |
| 6d0f6bcf JCPV |
278 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
| 279 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ | |
| 280 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
| 281 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of flash banks */ | |
| 282 | #define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ | |
| 283 | #define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* size of flash bank */ | |
| 284 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
| 285 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ | |
| 286 | CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT, \ | |
| 287 | CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT, \ | |
| 288 | CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT } | |
| 289 | #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */ | |
| a20b27a3 SR |
290 | |
| 291 | /* areas to map different things with the GT in physical space */ | |
| 6d0f6bcf | 292 | #define CONFIG_SYS_DRAM_BANKS 4 |
| a20b27a3 SR |
293 | |
| 294 | /* What to put in the bats. */ | |
| 6d0f6bcf | 295 | #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 |
| a20b27a3 SR |
296 | |
| 297 | /* Peripheral Device section */ | |
| 298 | ||
| 299 | /*******************************************************/ | |
| bfc81252 WD |
300 | /* We have on the cpci750 Board : */ |
| 301 | /* GT-Chipset Register Area */ | |
| 302 | /* GT-Chipset internal SRAM 256k */ | |
| 303 | /* SRAM on external device module */ | |
| 304 | /* Real time clock on external device module */ | |
| 305 | /* dobble UART on external device module */ | |
| 306 | /* Data flash on external device module */ | |
| 307 | /* Boot flash on external device module */ | |
| a20b27a3 | 308 | /*******************************************************/ |
| 6d0f6bcf JCPV |
309 | #define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ |
| 310 | #define CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ | |
| a20b27a3 | 311 | |
| bfc81252 WD |
312 | #undef MARVEL_STANDARD_CFG |
| 313 | #ifndef MARVEL_STANDARD_CFG | |
| a20b27a3 | 314 | /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ |
| 6d0f6bcf JCPV |
315 | #define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ |
| 316 | /*#define CONFIG_SYS_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ | |
| 317 | #define CONFIG_SYS_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */ | |
| 318 | ||
| 319 | #define CONFIG_SYS_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */ | |
| 320 | #define CONFIG_SYS_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */ | |
| 321 | #define CONFIG_SYS_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */ | |
| 322 | #define CONFIG_SYS_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ | |
| 323 | #define CONFIG_SYS_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ | |
| 324 | ||
| 325 | #define CONFIG_SYS_BOOT_SIZE _16M /* cpci750 flash 0 */ | |
| 326 | #define CONFIG_SYS_DEV0_SIZE _16M /* cpci750 flash 1 */ | |
| 327 | #define CONFIG_SYS_DEV1_SIZE _16M /* cpci750 flash 2 */ | |
| 328 | #define CONFIG_SYS_DEV2_SIZE _16M /* cpci750 flash 3 */ | |
| 329 | #define CONFIG_SYS_DEV3_SIZE _16M /* cpci750 nvram/can */ | |
| a20b27a3 SR |
330 | |
| 331 | /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ | |
| 332 | #endif | |
| 333 | ||
| 334 | /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ | |
| 6d0f6bcf JCPV |
335 | #define CONFIG_SYS_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ |
| 336 | #define CONFIG_SYS_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ | |
| 337 | #define CONFIG_SYS_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ | |
| 338 | #define CONFIG_SYS_DEV3_PAR 0x8FCFFFFF /* nvram/can */ | |
| 339 | #define CONFIG_SYS_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ | |
| a20b27a3 | 340 | |
| bfc81252 WD |
341 | /* c 4 a 8 2 4 1 c */ |
| 342 | /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ | |
| efe2a4d5 WD |
343 | /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ |
| 344 | /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ | |
| 345 | /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ | |
| a20b27a3 SR |
346 | |
| 347 | ||
| 348 | /* MPP Control MV64360 Appendix P P. 632*/ | |
| 6d0f6bcf JCPV |
349 | #define CONFIG_SYS_MPP_CONTROL_0 0x00002222 /* */ |
| 350 | #define CONFIG_SYS_MPP_CONTROL_1 0x11110000 /* */ | |
| 351 | #define CONFIG_SYS_MPP_CONTROL_2 0x11111111 /* */ | |
| 352 | #define CONFIG_SYS_MPP_CONTROL_3 0x00001111 /* */ | |
| 353 | /* #define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102*/ /* */ | |
| a20b27a3 SR |
354 | |
| 355 | ||
| 6d0f6bcf | 356 | #define CONFIG_SYS_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ |
| a20b27a3 SR |
357 | |
| 358 | /* setup new config_value for MV64360 DDR-RAM To_do !! */ | |
| 6d0f6bcf JCPV |
359 | /*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */ |
| 360 | /*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */ | |
| a20b27a3 SR |
361 | /* GB has high prio. |
| 362 | idma has low prio | |
| 363 | MPSC has low prio | |
| 364 | pci has low prio 1 and 2 | |
| 365 | cpu has high prio | |
| 366 | Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices | |
| 367 | ECC disable | |
| 368 | non registered DRAM */ | |
| 369 | /* 31:26 25:22 21:20 19 18 17 16 */ | |
| bfc81252 | 370 | /* 100001 0000 010 0 0 0 0 */ |
| a20b27a3 SR |
371 | /* refresh_count=0x400 |
| 372 | phisical interleaving disable | |
| 373 | virtual interleaving enable */ | |
| 374 | /* 15 14 13:0 */ | |
| bfc81252 | 375 | /* 0 1 0x400 */ |
| 6d0f6bcf | 376 | # define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ |
| a20b27a3 SR |
377 | |
| 378 | ||
| 379 | /*----------------------------------------------------------------------- | |
| 380 | * PCI stuff | |
| 381 | *----------------------------------------------------------------------- | |
| 382 | */ | |
| 383 | ||
| bfc81252 WD |
384 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
| 385 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
| 386 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
| a20b27a3 | 387 | |
| bfc81252 WD |
388 | #define CONFIG_PCI /* include pci support */ |
| 389 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
| 390 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 391 | #define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ | |
| a20b27a3 SR |
392 | |
| 393 | /* PCI MEMORY MAP section */ | |
| 6d0f6bcf JCPV |
394 | #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 |
| 395 | #define CONFIG_SYS_PCI0_MEM_SIZE _128M | |
| 396 | #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 | |
| 397 | #define CONFIG_SYS_PCI1_MEM_SIZE _128M | |
| a20b27a3 | 398 | |
| 6d0f6bcf JCPV |
399 | #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) |
| 400 | #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) | |
| a20b27a3 | 401 | |
| a20b27a3 | 402 | /* PCI I/O MAP section */ |
| 6d0f6bcf JCPV |
403 | #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 |
| 404 | #define CONFIG_SYS_PCI0_IO_SIZE _16M | |
| 405 | #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 | |
| 406 | #define CONFIG_SYS_PCI1_IO_SIZE _16M | |
| a20b27a3 | 407 | |
| 6d0f6bcf JCPV |
408 | #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) |
| 409 | #define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 | |
| 410 | #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) | |
| 411 | #define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 | |
| a20b27a3 | 412 | |
| 6d0f6bcf | 413 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE) |
| a7b9fb91 | 414 | |
| a20b27a3 | 415 | #if defined (CONFIG_750CX) |
| 6d0f6bcf | 416 | #define CONFIG_SYS_PCI_IDSEL 0x0 |
| a20b27a3 | 417 | #else |
| 6d0f6bcf | 418 | #define CONFIG_SYS_PCI_IDSEL 0x30 |
| a20b27a3 SR |
419 | #endif |
| 420 | ||
| 421 | /*----------------------------------------------------------------------- | |
| 422 | * IDE/ATA stuff | |
| 423 | *----------------------------------------------------------------------- | |
| 424 | */ | |
| bfc81252 WD |
425 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
| 426 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
| 427 | #define CONFIG_IDE_RESET /* no reset for ide supported */ | |
| 428 | #define CONFIG_IDE_PREINIT /* check for units */ | |
| a20b27a3 | 429 | |
| 6d0f6bcf JCPV |
430 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 1 IDE busses */ |
| 431 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ | |
| a20b27a3 | 432 | |
| 6d0f6bcf JCPV |
433 | #define CONFIG_SYS_ATA_BASE_ADDR 0 |
| 434 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
| 435 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0 | |
| a20b27a3 | 436 | |
| 6d0f6bcf JCPV |
437 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
| 438 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
| 439 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
| 2b224609 RA |
440 | #ifndef __ASSEMBLY__ |
| 441 | int ata_device(int dev); | |
| 442 | #endif | |
| 443 | #define ATA_DEVICE(dev) ata_device(dev) | |
| 444 | #define CONFIG_ATAPI 1 | |
| a20b27a3 SR |
445 | |
| 446 | /*---------------------------------------------------------------------- | |
| 447 | * Initial BAT mappings | |
| 448 | */ | |
| 449 | ||
| 450 | /* NOTES: | |
| 451 | * 1) GUARDED and WRITE_THRU not allowed in IBATS | |
| 452 | * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT | |
| 453 | */ | |
| 454 | ||
| 455 | /* SDRAM */ | |
| 6d0f6bcf JCPV |
456 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 457 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 458 | #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 459 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| a20b27a3 SR |
460 | |
| 461 | /* init ram */ | |
| 6d0f6bcf JCPV |
462 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 463 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) | |
| 464 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
| 465 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| a20b27a3 SR |
466 | |
| 467 | /* PCI0, PCI1 in one BAT */ | |
| 6d0f6bcf JCPV |
468 | #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS |
| 469 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
| 470 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
| 471 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| a20b27a3 SR |
472 | |
| 473 | /* GT regs, bootrom, all the devices, PCI I/O */ | |
| 6d0f6bcf JCPV |
474 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) |
| 475 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) | |
| 476 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
| 477 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| a20b27a3 SR |
478 | |
| 479 | /* | |
| 480 | * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7) | |
| 481 | * IBAT4 and DBAT4 | |
| 482 | * FIXME: ingo disable BATs for Linux Kernel | |
| 483 | */ | |
| 2b224609 RA |
484 | /* #undef SETUP_HIGH_BATS_FX750 */ /* don't initialize BATS 4-7 */ |
| 485 | #define SETUP_HIGH_BATS_FX750 /* initialize BATS 4-7 */ | |
| a20b27a3 SR |
486 | |
| 487 | #ifdef SETUP_HIGH_BATS_FX750 | |
| 6d0f6bcf JCPV |
488 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 489 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 490 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 491 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
| a20b27a3 SR |
492 | |
| 493 | /* IBAT5 and DBAT5 */ | |
| 6d0f6bcf JCPV |
494 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 495 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 496 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 497 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
| a20b27a3 SR |
498 | |
| 499 | /* IBAT6 and DBAT6 */ | |
| 6d0f6bcf JCPV |
500 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 501 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 502 | #define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 503 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
| a20b27a3 SR |
504 | |
| 505 | /* IBAT7 and DBAT7 */ | |
| 6d0f6bcf JCPV |
506 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 507 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 508 | #define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 509 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
| a20b27a3 SR |
510 | |
| 511 | #else /* set em out of range for Linux !!!!!!!!!!! */ | |
| 6d0f6bcf JCPV |
512 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 513 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 514 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 515 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
| a20b27a3 SR |
516 | |
| 517 | /* IBAT5 and DBAT5 */ | |
| 6d0f6bcf JCPV |
518 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 519 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 520 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 521 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U | |
| a20b27a3 SR |
522 | |
| 523 | /* IBAT6 and DBAT6 */ | |
| 6d0f6bcf JCPV |
524 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 525 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 526 | #define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 527 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U | |
| a20b27a3 SR |
528 | |
| 529 | /* IBAT7 and DBAT7 */ | |
| 6d0f6bcf JCPV |
530 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 531 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 532 | #define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 533 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U | |
| a20b27a3 SR |
534 | |
| 535 | #endif | |
| 536 | /* FIXME: ingo end: disable BATs for Linux Kernel */ | |
| 537 | ||
| 538 | /* I2C addresses for the two DIMM SPD chips */ | |
| 539 | #define DIMM0_I2C_ADDR 0x51 | |
| 540 | #define DIMM1_I2C_ADDR 0x52 | |
| 541 | ||
| 542 | /* | |
| 543 | * For booting Linux, the board info and command line data | |
| 544 | * have to be in the first 8 MB of memory, since this is | |
| 545 | * the maximum mapped by the Linux kernel during initialization. | |
| 546 | */ | |
| 6d0f6bcf | 547 | #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ |
| a20b27a3 SR |
548 | |
| 549 | /*----------------------------------------------------------------------- | |
| 550 | * FLASH organization | |
| 551 | */ | |
| 6d0f6bcf | 552 | #define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */ |
| a20b27a3 | 553 | |
| 6d0f6bcf JCPV |
554 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 555 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 556 | #define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ | |
| a20b27a3 SR |
557 | |
| 558 | #if 0 | |
| 5a1aceb0 | 559 | #define CONFIG_ENV_IS_IN_FLASH |
| 0e8d1586 JCPV |
560 | #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
| 561 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 562 | #define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ | |
| 6d0f6bcf | 563 | /* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ |
| a20b27a3 SR |
564 | #endif |
| 565 | ||
| bb1f8b4f | 566 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
| 6d0f6bcf JCPV |
567 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 |
| 568 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
| 569 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x050 | |
| 0e8d1586 JCPV |
570 | #define CONFIG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ |
| 571 | #define CONFIG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ | |
| a20b27a3 | 572 | |
| 6d0f6bcf JCPV |
573 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ |
| 574 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
| 575 | #define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40) | |
| a20b27a3 SR |
576 | |
| 577 | /*----------------------------------------------------------------------- | |
| 578 | * Cache Configuration | |
| 579 | */ | |
| 6d0f6bcf | 580 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ |
| 49cf7e8e | 581 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 582 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| a20b27a3 SR |
583 | #endif |
| 584 | ||
| 585 | /*----------------------------------------------------------------------- | |
| 586 | * L2CR setup -- make sure this is right for your board! | |
| 587 | * look in include/mpc74xx.h for the defines used here | |
| 588 | */ | |
| 589 | ||
| 6d0f6bcf JCPV |
590 | /*#define CONFIG_SYS_L2*/ |
| 591 | #undef CONFIG_SYS_L2 | |
| a20b27a3 SR |
592 | |
| 593 | /* #ifdef CONFIG_750CX*/ | |
| 594 | #if defined (CONFIG_750CX) || defined (CONFIG_750FX) | |
| 595 | #define L2_INIT 0 | |
| 596 | #else | |
| bfc81252 | 597 | #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ |
| a20b27a3 SR |
598 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) |
| 599 | #endif | |
| 600 | ||
| 601 | #define L2_ENABLE (L2_INIT | L2CR_L2E) | |
| 602 | ||
| 6d0f6bcf | 603 | #define CONFIG_SYS_BOARD_ASM_INIT 1 |
| a20b27a3 | 604 | |
| 58f10460 | 605 | #define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1) |
| 0738e24e RA |
606 | #define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0) |
| 607 | #define CONFIG_SYS_PLD_VER 0xf0e00000 | |
| 58f10460 | 608 | |
| 2b224609 RA |
609 | #define CONFIG_OF_LIBFDT 1 |
| 610 | ||
| a20b27a3 | 611 | #endif /* __CONFIG_H */ |