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Commit | Line | Data |
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a20b27a3 SR |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
a20b27a3 SR |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | /************************************************************************* | |
13 | * (c) 2004 esd gmbh Hannover | |
14 | * | |
15 | * | |
16 | * from db64360.h file | |
17 | * by Reinhard Arlt reinhard.arlt@esd-electronics.com | |
18 | * | |
19 | ************************************************************************/ | |
20 | ||
21 | ||
22 | #ifndef __CONFIG_H | |
23 | #define __CONFIG_H | |
24 | ||
a20b27a3 SR |
25 | /* This define must be before the core.h include */ |
26 | #define CONFIG_CPCI750 1 /* this is an CPCI750 board */ | |
27 | ||
28 | #ifndef __ASSEMBLY__ | |
29 | #include <../board/Marvell/include/core.h> | |
30 | #endif | |
31 | /*-----------------------------------------------------*/ | |
32 | ||
33 | #include "../board/esd/cpci750/local.h" | |
34 | ||
35 | /* | |
36 | * High Level Configuration Options | |
37 | * (easy to change) | |
38 | */ | |
39 | ||
40 | #define CONFIG_750FX /* we have a 750FX (override local.h) */ | |
41 | ||
42 | #define CONFIG_CPCI750 1 /* this is an CPCI750 board */ | |
43 | ||
2ae18241 WD |
44 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
45 | ||
bfc81252 | 46 | #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ |
a20b27a3 | 47 | |
0738e24e | 48 | #define CONFIG_MV64360_ECC /* enable ECC support */ |
a20b27a3 | 49 | |
31d82672 BB |
50 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
51 | ||
a20b27a3 SR |
52 | /* which initialization functions to call for this board */ |
53 | #define CONFIG_MISC_INIT_R | |
54 | #define CONFIG_BOARD_PRE_INIT | |
55 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
56 | ||
6d0f6bcf | 57 | #define CONFIG_SYS_BOARD_NAME "CPCI750" |
a20b27a3 SR |
58 | #define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX" |
59 | ||
6d0f6bcf JCPV |
60 | /*#define CONFIG_SYS_HUSH_PARSER*/ |
61 | #define CONFIG_SYS_HUSH_PARSER | |
a20b27a3 | 62 | |
a20b27a3 | 63 | |
0a14d6b8 SR |
64 | #define CONFIG_CMDLINE_EDITING /* add command line history */ |
65 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
a7b9fb91 | 66 | |
a20b27a3 | 67 | /* Define which ETH port will be used for connecting the network */ |
6d0f6bcf | 68 | #define CONFIG_SYS_ETH_PORT ETH_0 |
a20b27a3 SR |
69 | |
70 | /* | |
71 | * The following defines let you select what serial you want to use | |
72 | * for your console driver. | |
73 | * | |
74 | * what to do: | |
bfc81252 | 75 | * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial |
6d0f6bcf | 76 | * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 |
a20b27a3 SR |
77 | * to 0 below. |
78 | * | |
79 | * to use the MPSC, #define CONFIG_MPSC. If you have wired up another | |
80 | * mpsc channel, change CONFIG_MPSC_PORT to the desired value. | |
81 | */ | |
bfc81252 | 82 | #define CONFIG_MPSC |
a20b27a3 SR |
83 | #define CONFIG_MPSC_PORT 0 |
84 | ||
85 | /* to change the default ethernet port, use this define (options: 0, 1, 2) */ | |
bfc81252 | 86 | #define MV_ETH_DEVS 1 |
a20b27a3 SR |
87 | #define CONFIG_ETHER_PORT 0 |
88 | ||
89 | #undef CONFIG_ETHER_PORT_MII /* use RMII */ | |
90 | ||
91 | #define CONFIG_BOOTDELAY 5 /* autoboot disabled */ | |
92 | ||
93 | #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ | |
94 | ||
95 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
96 | ||
97 | ||
98 | #undef CONFIG_BOOTARGS | |
99 | ||
100 | /* ----------------------------------------------------------------------------- | |
101 | * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus | |
102 | */ | |
103 | ||
104 | #define CONFIG_IPADDR "192.168.0.185" | |
105 | ||
106 | #define CONFIG_SERIAL "AA000001" | |
107 | #define CONFIG_SERVERIP "10.0.0.79" | |
bfc81252 | 108 | #define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" |
a20b27a3 SR |
109 | |
110 | #define CONFIG_TESTDRAMDATA y | |
bfc81252 | 111 | #define CONFIG_TESTDRAMADDRESS n |
a20b27a3 SR |
112 | #define CONFIG_TESETDRAMWALK n |
113 | ||
114 | /* ----------------------------------------------------------------------------- */ | |
115 | ||
116 | ||
bfc81252 | 117 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
6d0f6bcf | 118 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ |
a20b27a3 SR |
119 | |
120 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
bfc81252 | 121 | #undef CONFIG_ALTIVEC /* undef to disable */ |
a20b27a3 | 122 | |
5d2ebe1b JL |
123 | /* |
124 | * BOOTP options | |
125 | */ | |
126 | #define CONFIG_BOOTP_SUBNETMASK | |
127 | #define CONFIG_BOOTP_GATEWAY | |
128 | #define CONFIG_BOOTP_HOSTNAME | |
129 | #define CONFIG_BOOTP_BOOTPATH | |
130 | #define CONFIG_BOOTP_BOOTFILESIZE | |
a20b27a3 SR |
131 | |
132 | ||
49cf7e8e JL |
133 | /* |
134 | * Command line configuration. | |
135 | */ | |
136 | #include <config_cmd_default.h> | |
137 | ||
5728be38 WD |
138 | #define CONFIG_CMD_ASKENV |
139 | #define CONFIG_CMD_I2C | |
140 | #define CONFIG_CMD_CACHE | |
141 | #define CONFIG_CMD_EEPROM | |
142 | #define CONFIG_CMD_PCI | |
143 | #define CONFIG_CMD_ELF | |
144 | #define CONFIG_CMD_DATE | |
145 | #define CONFIG_CMD_NET | |
146 | #define CONFIG_CMD_PING | |
147 | #define CONFIG_CMD_IDE | |
148 | #define CONFIG_CMD_FAT | |
149 | #define CONFIG_CMD_EXT2 | |
a20b27a3 | 150 | |
a20b27a3 | 151 | |
49cf7e8e | 152 | #define CONFIG_DOS_PARTITION |
a20b27a3 | 153 | |
a7b9fb91 SR |
154 | #define CONFIG_USE_CPCIDVI |
155 | ||
bfc81252 | 156 | #ifdef CONFIG_USE_CPCIDVI |
a7b9fb91 SR |
157 | #define CONFIG_VIDEO |
158 | #define CONFIG_VIDEO_CT69000 | |
159 | #define CONFIG_CFB_CONSOLE | |
160 | #define CONFIG_VIDEO_SW_CURSOR | |
161 | #define CONFIG_VIDEO_LOGO | |
162 | #define CONFIG_I8042_KBD | |
6d0f6bcf | 163 | #define CONFIG_SYS_ISA_IO 0 |
a7b9fb91 SR |
164 | #endif |
165 | ||
a20b27a3 SR |
166 | /* |
167 | * Miscellaneous configurable options | |
168 | */ | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
170 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
171 | #define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed default */ | |
a20b27a3 | 172 | |
2b224609 RA |
173 | #define CONFIG_PRAM 0 |
174 | ||
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ |
176 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
49cf7e8e | 177 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 178 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
a20b27a3 | 179 | #else |
6d0f6bcf | 180 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
a20b27a3 | 181 | #endif |
6d0f6bcf JCPV |
182 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
183 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
184 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
a20b27a3 | 185 | |
6d0f6bcf JCPV |
186 | /*#define CONFIG_SYS_MEMTEST_START 0x00400000*/ /* memtest works on */ |
187 | /*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ | |
188 | /*#define CONFIG_SYS_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ | |
a20b27a3 SR |
189 | |
190 | /* | |
6d0f6bcf | 191 | #define CONFIG_SYS_DRAM_TEST |
a20b27a3 | 192 | * DRAM tests |
6d0f6bcf | 193 | * CONFIG_SYS_DRAM_TEST - enables the following tests. |
a20b27a3 | 194 | * |
6d0f6bcf | 195 | * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines |
bfc81252 WD |
196 | * Environment variable 'test_dram_data' must be |
197 | * set to 'y'. | |
6d0f6bcf | 198 | * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely |
bfc81252 WD |
199 | * addressable. Environment variable |
200 | * 'test_dram_address' must be set to 'y'. | |
6d0f6bcf | 201 | * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. |
bfc81252 WD |
202 | * This test takes about 6 minutes to test 64 MB. |
203 | * Environment variable 'test_dram_walk' must be | |
204 | * set to 'y'. | |
a20b27a3 | 205 | */ |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_DRAM_TEST |
207 | #if defined(CONFIG_SYS_DRAM_TEST) | |
208 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ | |
209 | /*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ | |
210 | #define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ | |
211 | #define CONFIG_SYS_DRAM_TEST_DATA | |
212 | #define CONFIG_SYS_DRAM_TEST_ADDRESS | |
213 | #define CONFIG_SYS_DRAM_TEST_WALK | |
214 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
a20b27a3 SR |
215 | |
216 | #define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ | |
6d0f6bcf | 217 | #undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ |
a20b27a3 | 218 | |
6d0f6bcf | 219 | #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ |
a20b27a3 | 220 | |
ee80fa7b | 221 | #define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ |
a20b27a3 | 222 | |
6d0f6bcf | 223 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
a20b27a3 | 224 | |
6d0f6bcf | 225 | #define CONFIG_SYS_TCLK 133000000 |
a20b27a3 | 226 | |
a20b27a3 SR |
227 | /* |
228 | * Low Level Configuration Settings | |
229 | * (address mappings, register initial values, etc.) | |
230 | * You should know what you are doing if you make changes here. | |
231 | */ | |
232 | ||
233 | /*----------------------------------------------------------------------- | |
234 | * Definitions for initial stack pointer and data area | |
235 | */ | |
236 | ||
237 | /* | |
6d0f6bcf | 238 | * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS |
a20b27a3 SR |
239 | * To an unused memory region. The stack will remain in cache until RAM |
240 | * is initialized | |
241 | */ | |
6d0f6bcf JCPV |
242 | #undef CONFIG_SYS_INIT_RAM_LOCK |
243 | /* #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ | |
244 | /* #define CONFIG_SYS_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ | |
245 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ | |
553f0982 | 246 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
25ddd1fb | 247 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
a20b27a3 SR |
248 | |
249 | #define RELOCATE_INTERNAL_RAM_ADDR | |
250 | #ifdef RELOCATE_INTERNAL_RAM_ADDR | |
6d0f6bcf JCPV |
251 | /*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/ |
252 | #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf1080000 | |
a20b27a3 SR |
253 | #endif |
254 | ||
255 | /*----------------------------------------------------------------------- | |
256 | * Start addresses for the final memory configuration | |
257 | * (Set up by the startup code) | |
6d0f6bcf | 258 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
a20b27a3 | 259 | */ |
6d0f6bcf | 260 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
a20b27a3 | 261 | /* Dummies for BAT 4-7 */ |
6d0f6bcf JCPV |
262 | #define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ |
263 | #define CONFIG_SYS_SDRAM2_BASE 0x20000000 | |
264 | #define CONFIG_SYS_SDRAM3_BASE 0x30000000 | |
265 | #define CONFIG_SYS_SDRAM4_BASE 0x40000000 | |
266 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 | |
267 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
268 | #define CONFIG_SYS_MONITOR_BASE 0xfff00000 | |
269 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ | |
a20b27a3 SR |
270 | |
271 | /*----------------------------------------------------------------------- | |
272 | * FLASH related | |
273 | *----------------------------------------------------------------------*/ | |
274 | ||
00b1883a | 275 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
277 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ | |
278 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
279 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of flash banks */ | |
280 | #define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ | |
281 | #define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* size of flash bank */ | |
282 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
283 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ | |
284 | CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT, \ | |
285 | CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT, \ | |
286 | CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT } | |
287 | #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */ | |
a20b27a3 SR |
288 | |
289 | /* areas to map different things with the GT in physical space */ | |
6d0f6bcf | 290 | #define CONFIG_SYS_DRAM_BANKS 4 |
a20b27a3 SR |
291 | |
292 | /* What to put in the bats. */ | |
6d0f6bcf | 293 | #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 |
a20b27a3 SR |
294 | |
295 | /* Peripheral Device section */ | |
296 | ||
297 | /*******************************************************/ | |
bfc81252 WD |
298 | /* We have on the cpci750 Board : */ |
299 | /* GT-Chipset Register Area */ | |
300 | /* GT-Chipset internal SRAM 256k */ | |
301 | /* SRAM on external device module */ | |
302 | /* Real time clock on external device module */ | |
303 | /* dobble UART on external device module */ | |
304 | /* Data flash on external device module */ | |
305 | /* Boot flash on external device module */ | |
a20b27a3 | 306 | /*******************************************************/ |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ |
308 | #define CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ | |
a20b27a3 | 309 | |
bfc81252 WD |
310 | #undef MARVEL_STANDARD_CFG |
311 | #ifndef MARVEL_STANDARD_CFG | |
a20b27a3 | 312 | /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ |
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ |
314 | /*#define CONFIG_SYS_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ | |
315 | #define CONFIG_SYS_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */ | |
316 | ||
317 | #define CONFIG_SYS_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */ | |
318 | #define CONFIG_SYS_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */ | |
319 | #define CONFIG_SYS_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */ | |
320 | #define CONFIG_SYS_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ | |
321 | #define CONFIG_SYS_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ | |
322 | ||
323 | #define CONFIG_SYS_BOOT_SIZE _16M /* cpci750 flash 0 */ | |
324 | #define CONFIG_SYS_DEV0_SIZE _16M /* cpci750 flash 1 */ | |
325 | #define CONFIG_SYS_DEV1_SIZE _16M /* cpci750 flash 2 */ | |
326 | #define CONFIG_SYS_DEV2_SIZE _16M /* cpci750 flash 3 */ | |
327 | #define CONFIG_SYS_DEV3_SIZE _16M /* cpci750 nvram/can */ | |
a20b27a3 SR |
328 | |
329 | /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ | |
330 | #endif | |
331 | ||
332 | /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ | |
6d0f6bcf JCPV |
333 | #define CONFIG_SYS_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ |
334 | #define CONFIG_SYS_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ | |
335 | #define CONFIG_SYS_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ | |
336 | #define CONFIG_SYS_DEV3_PAR 0x8FCFFFFF /* nvram/can */ | |
337 | #define CONFIG_SYS_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ | |
a20b27a3 | 338 | |
bfc81252 WD |
339 | /* c 4 a 8 2 4 1 c */ |
340 | /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ | |
efe2a4d5 WD |
341 | /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ |
342 | /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ | |
343 | /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ | |
a20b27a3 SR |
344 | |
345 | ||
346 | /* MPP Control MV64360 Appendix P P. 632*/ | |
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_MPP_CONTROL_0 0x00002222 /* */ |
348 | #define CONFIG_SYS_MPP_CONTROL_1 0x11110000 /* */ | |
349 | #define CONFIG_SYS_MPP_CONTROL_2 0x11111111 /* */ | |
350 | #define CONFIG_SYS_MPP_CONTROL_3 0x00001111 /* */ | |
351 | /* #define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102*/ /* */ | |
a20b27a3 SR |
352 | |
353 | ||
6d0f6bcf | 354 | #define CONFIG_SYS_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ |
a20b27a3 SR |
355 | |
356 | /* setup new config_value for MV64360 DDR-RAM To_do !! */ | |
6d0f6bcf JCPV |
357 | /*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */ |
358 | /*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */ | |
a20b27a3 SR |
359 | /* GB has high prio. |
360 | idma has low prio | |
361 | MPSC has low prio | |
362 | pci has low prio 1 and 2 | |
363 | cpu has high prio | |
364 | Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices | |
365 | ECC disable | |
366 | non registered DRAM */ | |
367 | /* 31:26 25:22 21:20 19 18 17 16 */ | |
bfc81252 | 368 | /* 100001 0000 010 0 0 0 0 */ |
a20b27a3 SR |
369 | /* refresh_count=0x400 |
370 | phisical interleaving disable | |
371 | virtual interleaving enable */ | |
372 | /* 15 14 13:0 */ | |
bfc81252 | 373 | /* 0 1 0x400 */ |
6d0f6bcf | 374 | # define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ |
a20b27a3 SR |
375 | |
376 | ||
377 | /*----------------------------------------------------------------------- | |
378 | * PCI stuff | |
379 | *----------------------------------------------------------------------- | |
380 | */ | |
381 | ||
bfc81252 WD |
382 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
383 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
384 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
a20b27a3 | 385 | |
bfc81252 WD |
386 | #define CONFIG_PCI /* include pci support */ |
387 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
388 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
389 | #define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ | |
a20b27a3 SR |
390 | |
391 | /* PCI MEMORY MAP section */ | |
6d0f6bcf JCPV |
392 | #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 |
393 | #define CONFIG_SYS_PCI0_MEM_SIZE _128M | |
394 | #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 | |
395 | #define CONFIG_SYS_PCI1_MEM_SIZE _128M | |
a20b27a3 | 396 | |
6d0f6bcf JCPV |
397 | #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) |
398 | #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) | |
a20b27a3 | 399 | |
a20b27a3 | 400 | /* PCI I/O MAP section */ |
6d0f6bcf JCPV |
401 | #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 |
402 | #define CONFIG_SYS_PCI0_IO_SIZE _16M | |
403 | #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 | |
404 | #define CONFIG_SYS_PCI1_IO_SIZE _16M | |
a20b27a3 | 405 | |
6d0f6bcf JCPV |
406 | #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) |
407 | #define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 | |
408 | #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) | |
409 | #define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 | |
a20b27a3 | 410 | |
6d0f6bcf | 411 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE) |
a7b9fb91 | 412 | |
a20b27a3 | 413 | #if defined (CONFIG_750CX) |
6d0f6bcf | 414 | #define CONFIG_SYS_PCI_IDSEL 0x0 |
a20b27a3 | 415 | #else |
6d0f6bcf | 416 | #define CONFIG_SYS_PCI_IDSEL 0x30 |
a20b27a3 SR |
417 | #endif |
418 | ||
419 | /*----------------------------------------------------------------------- | |
420 | * IDE/ATA stuff | |
421 | *----------------------------------------------------------------------- | |
422 | */ | |
bfc81252 WD |
423 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
424 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
425 | #define CONFIG_IDE_RESET /* no reset for ide supported */ | |
426 | #define CONFIG_IDE_PREINIT /* check for units */ | |
a20b27a3 | 427 | |
6d0f6bcf JCPV |
428 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 1 IDE busses */ |
429 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ | |
a20b27a3 | 430 | |
6d0f6bcf JCPV |
431 | #define CONFIG_SYS_ATA_BASE_ADDR 0 |
432 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
433 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0 | |
a20b27a3 | 434 | |
6d0f6bcf JCPV |
435 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
436 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
437 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
2b224609 RA |
438 | #ifndef __ASSEMBLY__ |
439 | int ata_device(int dev); | |
440 | #endif | |
441 | #define ATA_DEVICE(dev) ata_device(dev) | |
442 | #define CONFIG_ATAPI 1 | |
a20b27a3 SR |
443 | |
444 | /*---------------------------------------------------------------------- | |
445 | * Initial BAT mappings | |
446 | */ | |
447 | ||
448 | /* NOTES: | |
449 | * 1) GUARDED and WRITE_THRU not allowed in IBATS | |
450 | * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT | |
451 | */ | |
452 | ||
453 | /* SDRAM */ | |
6d0f6bcf JCPV |
454 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
455 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
456 | #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
457 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
a20b27a3 SR |
458 | |
459 | /* init ram */ | |
6d0f6bcf JCPV |
460 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
461 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) | |
462 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
463 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
a20b27a3 SR |
464 | |
465 | /* PCI0, PCI1 in one BAT */ | |
6d0f6bcf JCPV |
466 | #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS |
467 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
468 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
469 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
a20b27a3 SR |
470 | |
471 | /* GT regs, bootrom, all the devices, PCI I/O */ | |
6d0f6bcf JCPV |
472 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) |
473 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) | |
474 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
475 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
a20b27a3 SR |
476 | |
477 | /* | |
478 | * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7) | |
479 | * IBAT4 and DBAT4 | |
480 | * FIXME: ingo disable BATs for Linux Kernel | |
481 | */ | |
2b224609 RA |
482 | /* #undef SETUP_HIGH_BATS_FX750 */ /* don't initialize BATS 4-7 */ |
483 | #define SETUP_HIGH_BATS_FX750 /* initialize BATS 4-7 */ | |
a20b27a3 SR |
484 | |
485 | #ifdef SETUP_HIGH_BATS_FX750 | |
6d0f6bcf JCPV |
486 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
487 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
488 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
489 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
a20b27a3 SR |
490 | |
491 | /* IBAT5 and DBAT5 */ | |
6d0f6bcf JCPV |
492 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
493 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
494 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
495 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
a20b27a3 SR |
496 | |
497 | /* IBAT6 and DBAT6 */ | |
6d0f6bcf JCPV |
498 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
499 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
500 | #define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
501 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
a20b27a3 SR |
502 | |
503 | /* IBAT7 and DBAT7 */ | |
6d0f6bcf JCPV |
504 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
505 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
506 | #define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
507 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
a20b27a3 SR |
508 | |
509 | #else /* set em out of range for Linux !!!!!!!!!!! */ | |
6d0f6bcf JCPV |
510 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
511 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
512 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
513 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
a20b27a3 SR |
514 | |
515 | /* IBAT5 and DBAT5 */ | |
6d0f6bcf JCPV |
516 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
517 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
518 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
519 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U | |
a20b27a3 SR |
520 | |
521 | /* IBAT6 and DBAT6 */ | |
6d0f6bcf JCPV |
522 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
523 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
524 | #define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
525 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U | |
a20b27a3 SR |
526 | |
527 | /* IBAT7 and DBAT7 */ | |
6d0f6bcf JCPV |
528 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
529 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
530 | #define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
531 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U | |
a20b27a3 SR |
532 | |
533 | #endif | |
534 | /* FIXME: ingo end: disable BATs for Linux Kernel */ | |
535 | ||
536 | /* I2C addresses for the two DIMM SPD chips */ | |
537 | #define DIMM0_I2C_ADDR 0x51 | |
538 | #define DIMM1_I2C_ADDR 0x52 | |
539 | ||
540 | /* | |
541 | * For booting Linux, the board info and command line data | |
542 | * have to be in the first 8 MB of memory, since this is | |
543 | * the maximum mapped by the Linux kernel during initialization. | |
544 | */ | |
6d0f6bcf | 545 | #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ |
a20b27a3 SR |
546 | |
547 | /*----------------------------------------------------------------------- | |
548 | * FLASH organization | |
549 | */ | |
6d0f6bcf | 550 | #define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */ |
a20b27a3 | 551 | |
6d0f6bcf JCPV |
552 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
553 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
554 | #define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ | |
a20b27a3 SR |
555 | |
556 | #if 0 | |
5a1aceb0 | 557 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
558 | #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
559 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
560 | #define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ | |
6d0f6bcf | 561 | /* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ |
a20b27a3 SR |
562 | #endif |
563 | ||
bb1f8b4f | 564 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
6d0f6bcf JCPV |
565 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 |
566 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
567 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x050 | |
0e8d1586 JCPV |
568 | #define CONFIG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ |
569 | #define CONFIG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ | |
a20b27a3 | 570 | |
6d0f6bcf JCPV |
571 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ |
572 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
573 | #define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40) | |
a20b27a3 SR |
574 | |
575 | /*----------------------------------------------------------------------- | |
576 | * Cache Configuration | |
577 | */ | |
6d0f6bcf | 578 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ |
49cf7e8e | 579 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 580 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
a20b27a3 SR |
581 | #endif |
582 | ||
583 | /*----------------------------------------------------------------------- | |
584 | * L2CR setup -- make sure this is right for your board! | |
585 | * look in include/mpc74xx.h for the defines used here | |
586 | */ | |
587 | ||
6d0f6bcf JCPV |
588 | /*#define CONFIG_SYS_L2*/ |
589 | #undef CONFIG_SYS_L2 | |
a20b27a3 SR |
590 | |
591 | /* #ifdef CONFIG_750CX*/ | |
592 | #if defined (CONFIG_750CX) || defined (CONFIG_750FX) | |
593 | #define L2_INIT 0 | |
594 | #else | |
bfc81252 | 595 | #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ |
a20b27a3 SR |
596 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) |
597 | #endif | |
598 | ||
599 | #define L2_ENABLE (L2_INIT | L2CR_L2E) | |
600 | ||
6d0f6bcf | 601 | #define CONFIG_SYS_BOARD_ASM_INIT 1 |
a20b27a3 | 602 | |
58f10460 | 603 | #define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1) |
0738e24e RA |
604 | #define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0) |
605 | #define CONFIG_SYS_PLD_VER 0xf0e00000 | |
58f10460 | 606 | |
2b224609 RA |
607 | #define CONFIG_OF_LIBFDT 1 |
608 | ||
a20b27a3 | 609 | #endif /* __CONFIG_H */ |