[people/ms/u-boot.git] / include / configs / M52277EVB.h

/*
 * Configuation settings for the Freescale MCF52277 EVB board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M52277EVB_H
#define _M52277EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_M52277EVB	/* M52277EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE			115200

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Command line configuration */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_BMP

#define CONFIG_HOSTNAME			M52277EVB
#define CONFIG_SYS_UBOOT_END		0x3FFFF
#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=loadb ${loadaddr} ${baudrate};"	\
	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:2 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	"save\0"				\
	""
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=loadb ${loadaddr} ${baudrate}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" ${filesize}; save\0"			\
	"updsbf=run loadsbf; run progsbf\0"	\
	"loadsbf=loadb ${loadaddr} ${baudrate};"	\
	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
	"progsbf=sf probe 0:2 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	""
#endif

/* LCD */
#ifdef CONFIG_CMD_BMP
#define CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_LCD_LOGO
#define CONFIG_SHARP_LQ035Q7DH06
#endif

/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION
#define CONFIG_SYS_USB_EHCI_REGS_BASE	0xFC0B0000
#define CONFIG_SYS_USB_EHCI_CPU_INIT
#endif

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_SPI
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE		0x7
#ifdef CONFIG_CMD_SPI
#	define CONFIG_SYS_DSPI_CS2

#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
					 DSPI_CTAR_PCSSCK_1CLK | \
					 DSPI_CTAR_PASC(0) | \
					 DSPI_CTAR_PDT(0) | \
					 DSPI_CTAR_CSSCK(0) | \
					 DSPI_CTAR_ASC(0) | \
					 DSPI_CTAR_DT(1))
#endif

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_SYS_INPUT_CLKSRC	16000000

#define CONFIG_PRAM		2048	/* 2048 KB */

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x43711630
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
#define CONFIG_SYS_SDRAM_EMOD		0x81810000
#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x00

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*
 * Configuration for environment
 * Environment is not embedded in u-boot. First time runing may have env
 * crc error warning if there is no correct environment on the flash.
 */
#ifdef CONFIG_CF_SBF
#	define CONFIG_ENV_IS_IN_SPI_FLASH
#	define CONFIG_ENV_SPI_CS	2
#else
#	define CONFIG_ENV_IS_IN_FLASH	1
#endif
#define CONFIG_ENV_OVERWRITE		1

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_STMICRO_BOOT
#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_ENV_OFFSET	0x30000
#	define CONFIG_ENV_SIZE		0x1000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x1000
#	define CONFIG_ENV_SECT_SIZE	0x8000
#endif

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_FLASH_SPANSION_S29WS_N	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
#endif

#define LDS_BOARD_TEXT \
        arch/m68k/cpu/mcf5227x/built-in.o   (.text*) \
	arch/m68k/lib/built-in.o            (.text*)

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x40000)
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x40000)
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */

#ifdef CONFIG_CF_SBF
#define CONFIG_SYS_CS0_BASE		0x04000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0
#else
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0
#endif

#endif				/* _M52277EVB_H */
Commit	Line	Data
1552af70 TL	1	/*
	2	* Configuation settings for the Freescale MCF52277 EVB board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
1552af70 TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M52277EVB_H
	15	#define _M52277EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
1552af70 TL	21	#define CONFIG_M52277EVB /* M52277EVB board */
1552af70 TL	22
1552af70	23	#define CONFIG_MCFUART
6d0f6bcf	24	#define CONFIG_SYS_UART_PORT (0)
a21d0c2c	25	#define CONFIG_BAUDRATE 115200
1552af70 TL	26
	27	#undef CONFIG_WATCHDOG
	28
	29	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	30
	31	/*
	32	* BOOTP options
	33	*/
	34	#define CONFIG_BOOTP_BOOTFILESIZE
	35	#define CONFIG_BOOTP_BOOTPATH
	36	#define CONFIG_BOOTP_GATEWAY
	37	#define CONFIG_BOOTP_HOSTNAME
	38
	39	/* Command line configuration */
1552af70	40	#define CONFIG_CMD_DATE
1552af70	41	#define CONFIG_CMD_JFFS2
1552af70	42	#define CONFIG_CMD_REGINFO
1552af70	43	#undef CONFIG_CMD_BMP
a21d0c2c TL	44
	45	#define CONFIG_HOSTNAME M52277EVB
	46	#define CONFIG_SYS_UBOOT_END 0x3FFFF
	47	#define CONFIG_SYS_LOAD_ADDR2 0x40010007
	48	#ifdef CONFIG_SYS_STMICRO_BOOT
	49	/* ST Micro serial flash */
1552af70	50	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d	51	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
a21d0c2c TL	52	"loadaddr=0x40010000\0" \
	53	"uboot=u-boot.bin\0" \
	54	"load=loadb ${loadaddr} ${baudrate};" \
5368c55d	55	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
1552af70	56	"upd=run load; run prog\0" \
a21d0c2c TL	57	"prog=sf probe 0:2 10000 1;" \
	58	"sf erase 0 30000;" \
	59	"sf write ${loadaddr} 0 30000;" \
1552af70 TL	60	"save\0" \
1552af70 TL	61	""
a21d0c2c TL	62	#endif
	63	#ifdef CONFIG_SYS_SPANSION_BOOT
	64	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d	65	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
a21d0c2c TL	66	"loadaddr=0x40010000\0" \
	67	"uboot=u-boot.bin\0" \
	68	"load=loadb ${loadaddr} ${baudrate}\0" \
	69	"upd=run load; run prog\0" \
5368c55d MV	70	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
	71	" " __stringify(CONFIG_SYS_UBOOT_END) ";" \
	72	"era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
	73	__stringify(CONFIG_SYS_UBOOT_END) ";" \
	74	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
a21d0c2c TL	75	" ${filesize}; save\0" \
	76	"updsbf=run loadsbf; run progsbf\0" \
	77	"loadsbf=loadb ${loadaddr} ${baudrate};" \
5368c55d	78	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
a21d0c2c TL	79	"progsbf=sf probe 0:2 10000 1;" \
	80	"sf erase 0 30000;" \
	81	"sf write ${loadaddr} 0 30000;" \
	82	""
	83	#endif
1552af70 TL	84
	85	/* LCD */
	86	#ifdef CONFIG_CMD_BMP
	87	#define CONFIG_LCD
	88	#define CONFIG_SPLASH_SCREEN
	89	#define CONFIG_LCD_LOGO
	90	#define CONFIG_SHARP_LQ035Q7DH06
	91	#endif
	92
	93	/* USB */
	94	#ifdef CONFIG_CMD_USB
	95	#define CONFIG_USB_EHCI
	96	#define CONFIG_USB_STORAGE
	97	#define CONFIG_DOS_PARTITION
	98	#define CONFIG_MAC_PARTITION
	99	#define CONFIG_ISO_PARTITION
a21d0c2c	100	#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
6d0f6bcf	101	#define CONFIG_SYS_USB_EHCI_CPU_INIT
1552af70 TL	102	#endif
	103
	104	/* Realtime clock */
	105	#define CONFIG_MCFRTC
	106	#undef RTC_DEBUG
6d0f6bcf	107	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
1552af70 TL	108
	109	/* Timer */
	110	#define CONFIG_MCFTMR
	111	#undef CONFIG_MCFPIT
	112
	113	/* I2c */
00f792e0 HS	114	#define CONFIG_SYS_I2C
	115	#define CONFIG_SYS_I2C_FSL
	116	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	117	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	118	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
a21d0c2c TL	119	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	120
	121	/* DSPI and Serial Flash */
ee0a8462	122	#define CONFIG_CF_SPI
a21d0c2c TL	123	#define CONFIG_CF_DSPI
a21d0c2c TL	124	#define CONFIG_HARD_SPI
a21d0c2c TL	125	#define CONFIG_SYS_SBFHDR_SIZE 0x7
	126	#ifdef CONFIG_CMD_SPI
	127	# define CONFIG_SYS_DSPI_CS2
a21d0c2c	128
ee0a8462 TL	129	# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) \| \
	130	DSPI_CTAR_PCSSCK_1CLK \| \
	131	DSPI_CTAR_PASC(0) \| \
	132	DSPI_CTAR_PDT(0) \| \
	133	DSPI_CTAR_CSSCK(0) \| \
	134	DSPI_CTAR_ASC(0) \| \
	135	DSPI_CTAR_DT(1))
a21d0c2c	136	#endif
1552af70 TL	137
	138	/* Input, PCI, Flexbus, and VCO */
	139	#define CONFIG_EXTRA_CLOCK
	140
6d0f6bcf	141	#define CONFIG_SYS_INPUT_CLKSRC 16000000
1552af70	142
a21d0c2c	143	#define CONFIG_PRAM 2048 /* 2048 KB */
1552af70	144
6d0f6bcf	145	#define CONFIG_SYS_LONGHELP /* undef to save memory */
1552af70 TL	146
1552af70 TL	147	#if defined(CONFIG_CMD_KGDB)
a21d0c2c	148	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
1552af70	149	#else
a21d0c2c	150	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
1552af70	151	#endif
a21d0c2c TL	152	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	153	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	154	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
1552af70	155
a21d0c2c	156	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
1552af70	157
6d0f6bcf	158	#define CONFIG_SYS_MBAR 0xFC000000
1552af70 TL	159
	160	/*
	161	* Low Level Configuration Settings
	162	* (address mappings, register initial values, etc.)
	163	* You should know what you are doing if you make changes here.
	164	*/
	165
a21d0c2c	166	/*
1552af70 TL	167	* Definitions for initial stack pointer and data area (in DPRAM)
1552af70 TL	168	*/
6d0f6bcf	169	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	170	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
a21d0c2c	171	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	172	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
a21d0c2c	173	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
553f0982	174	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
1552af70	175
a21d0c2c	176	/*
1552af70 TL	177	* Start addresses for the final memory configuration
1552af70 TL	178	* (Set up by the startup code)
6d0f6bcf	179	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
1552af70	180	*/
6d0f6bcf JCPV	181	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	182	#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
	183	#define CONFIG_SYS_SDRAM_CFG1 0x43711630
	184	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
	185	#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
	186	#define CONFIG_SYS_SDRAM_EMOD 0x81810000
	187	#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
a21d0c2c	188	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
6d0f6bcf JCPV	189
	190	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	191	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
	192
a21d0c2c	193	#ifdef CONFIG_CF_SBF
14d0a02a	194	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
a21d0c2c TL	195	#else
	196	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
	197	#endif
6d0f6bcf JCPV	198	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	199	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	200	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
1552af70 TL	201
1552af70 TL	202	/* Initial Memory map for Linux */
6d0f6bcf	203	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	204	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
1552af70	205
a21d0c2c TL	206	/*
a21d0c2c TL	207	* Configuration for environment
27f7ae70 JJ	208	* Environment is not embedded in u-boot. First time runing may have env
27f7ae70 JJ	209	* crc error warning if there is no correct environment on the flash.
1552af70	210	*/
a21d0c2c TL	211	#ifdef CONFIG_CF_SBF
	212	# define CONFIG_ENV_IS_IN_SPI_FLASH
	213	# define CONFIG_ENV_SPI_CS 2
	214	#else
	215	# define CONFIG_ENV_IS_IN_FLASH 1
	216	#endif
	217	#define CONFIG_ENV_OVERWRITE 1
1552af70 TL	218
	219	/*-----------------------------------------------------------------------
	220	* FLASH organization
	221	*/
a21d0c2c	222	#ifdef CONFIG_SYS_STMICRO_BOOT
ee0a8462	223	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
27f7ae70	224	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
a21d0c2c TL	225	# define CONFIG_ENV_OFFSET 0x30000
	226	# define CONFIG_ENV_SIZE 0x1000
	227	# define CONFIG_ENV_SECT_SIZE 0x10000
	228	#endif
	229	#ifdef CONFIG_SYS_SPANSION_BOOT
	230	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	231	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
27f7ae70	232	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
a21d0c2c TL	233	# define CONFIG_ENV_SIZE 0x1000
	234	# define CONFIG_ENV_SECT_SIZE 0x8000
	235	#endif
1552af70	236
6d0f6bcf JCPV	237	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	238	#ifdef CONFIG_SYS_FLASH_CFI
00b1883a	239	# define CONFIG_FLASH_CFI_DRIVER 1
bbf6bbff TL	240	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
bbf6bbff TL	241	# define CONFIG_FLASH_SPANSION_S29WS_N 1
6d0f6bcf JCPV	242	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	243	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	244	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	245	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	246	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	247	# define CONFIG_SYS_FLASH_CHECKSUM
a21d0c2c	248	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
1552af70 TL	249	#endif
1552af70 TL	250
5296cb1d	251	#define LDS_BOARD_TEXT \
	252	arch/m68k/cpu/mcf5227x/built-in.o (.text*) \
	253	arch/m68k/lib/built-in.o (.text*)
	254
1552af70 TL	255	/*
	256	* This is setting for JFFS2 support in u-boot.
	257	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	258	*/
	259	#ifdef CONFIG_CMD_JFFS2
	260	# define CONFIG_JFFS2_DEV "nor0"
	261	# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
6d0f6bcf	262	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
1552af70 TL	263	#endif
	264
	265	/*-----------------------------------------------------------------------
	266	* Cache Configuration
	267	*/
a21d0c2c	268	#define CONFIG_SYS_CACHELINE_SIZE 16
1552af70	269
dd9f054e	270	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	271	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	272	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	273	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	274	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	275	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	276	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	277	CF_ACR_EN \| CF_ACR_SM_ALL)
	278	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	279	CF_CACR_DISD \| CF_CACR_INVI \| \
	280	CF_CACR_CEIB \| CF_CACR_DCM \| \
	281	CF_CACR_EUSP)
	282
1552af70 TL	283	/*-----------------------------------------------------------------------
	284	* Memory bank definitions
	285	*/
	286	/*
	287	* CS0 - NOR Flash
	288	* CS1 - Available
	289	* CS2 - Available
	290	* CS3 - Available
	291	* CS4 - Available
	292	* CS5 - Available
	293	*/
	294
a21d0c2c TL	295	#ifdef CONFIG_CF_SBF
	296	#define CONFIG_SYS_CS0_BASE 0x04000000
	297	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	298	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
	299	#else
6d0f6bcf JCPV	300	#define CONFIG_SYS_CS0_BASE 0x00000000
	301	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	302	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
a21d0c2c	303	#endif
1552af70 TL	304
1552af70 TL	305	#endif /* _M52277EVB_H */