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1552af70 TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF52277 EVB board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
1552af70 TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M52277EVB_H | |
15 | #define _M52277EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
1552af70 TL |
21 | #define CONFIG_M52277EVB /* M52277EVB board */ |
22 | ||
1552af70 | 23 | #define CONFIG_MCFUART |
6d0f6bcf | 24 | #define CONFIG_SYS_UART_PORT (0) |
a21d0c2c | 25 | #define CONFIG_BAUDRATE 115200 |
1552af70 TL |
26 | |
27 | #undef CONFIG_WATCHDOG | |
28 | ||
29 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
30 | ||
31 | /* | |
32 | * BOOTP options | |
33 | */ | |
34 | #define CONFIG_BOOTP_BOOTFILESIZE | |
35 | #define CONFIG_BOOTP_BOOTPATH | |
36 | #define CONFIG_BOOTP_GATEWAY | |
37 | #define CONFIG_BOOTP_HOSTNAME | |
38 | ||
39 | /* Command line configuration */ | |
40 | #include <config_cmd_default.h> | |
41 | ||
42 | #define CONFIG_CMD_CACHE | |
43 | #define CONFIG_CMD_DATE | |
44 | #define CONFIG_CMD_ELF | |
45 | #define CONFIG_CMD_FLASH | |
46 | #define CONFIG_CMD_I2C | |
47 | #define CONFIG_CMD_JFFS2 | |
48 | #define CONFIG_CMD_LOADB | |
49 | #define CONFIG_CMD_LOADS | |
50 | #define CONFIG_CMD_MEMORY | |
51 | #define CONFIG_CMD_MISC | |
52 | #undef CONFIG_CMD_NET | |
90fa92dc | 53 | #undef CONFIG_CMD_NFS |
1552af70 TL |
54 | #define CONFIG_CMD_REGINFO |
55 | #undef CONFIG_CMD_USB | |
56 | #undef CONFIG_CMD_BMP | |
a21d0c2c TL |
57 | #define CONFIG_CMD_SPI |
58 | #define CONFIG_CMD_SF | |
59 | ||
60 | #define CONFIG_HOSTNAME M52277EVB | |
61 | #define CONFIG_SYS_UBOOT_END 0x3FFFF | |
62 | #define CONFIG_SYS_LOAD_ADDR2 0x40010007 | |
63 | #ifdef CONFIG_SYS_STMICRO_BOOT | |
64 | /* ST Micro serial flash */ | |
1552af70 | 65 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d | 66 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
a21d0c2c TL |
67 | "loadaddr=0x40010000\0" \ |
68 | "uboot=u-boot.bin\0" \ | |
69 | "load=loadb ${loadaddr} ${baudrate};" \ | |
5368c55d | 70 | "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ |
1552af70 | 71 | "upd=run load; run prog\0" \ |
a21d0c2c TL |
72 | "prog=sf probe 0:2 10000 1;" \ |
73 | "sf erase 0 30000;" \ | |
74 | "sf write ${loadaddr} 0 30000;" \ | |
1552af70 TL |
75 | "save\0" \ |
76 | "" | |
a21d0c2c TL |
77 | #endif |
78 | #ifdef CONFIG_SYS_SPANSION_BOOT | |
79 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5368c55d | 80 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
a21d0c2c TL |
81 | "loadaddr=0x40010000\0" \ |
82 | "uboot=u-boot.bin\0" \ | |
83 | "load=loadb ${loadaddr} ${baudrate}\0" \ | |
84 | "upd=run load; run prog\0" \ | |
5368c55d MV |
85 | "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ |
86 | " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
87 | "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ | |
88 | __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
89 | "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ | |
a21d0c2c TL |
90 | " ${filesize}; save\0" \ |
91 | "updsbf=run loadsbf; run progsbf\0" \ | |
92 | "loadsbf=loadb ${loadaddr} ${baudrate};" \ | |
5368c55d | 93 | "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ |
a21d0c2c TL |
94 | "progsbf=sf probe 0:2 10000 1;" \ |
95 | "sf erase 0 30000;" \ | |
96 | "sf write ${loadaddr} 0 30000;" \ | |
97 | "" | |
98 | #endif | |
1552af70 | 99 | |
a21d0c2c | 100 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
1552af70 TL |
101 | /* LCD */ |
102 | #ifdef CONFIG_CMD_BMP | |
103 | #define CONFIG_LCD | |
104 | #define CONFIG_SPLASH_SCREEN | |
105 | #define CONFIG_LCD_LOGO | |
106 | #define CONFIG_SHARP_LQ035Q7DH06 | |
107 | #endif | |
108 | ||
109 | /* USB */ | |
110 | #ifdef CONFIG_CMD_USB | |
111 | #define CONFIG_USB_EHCI | |
112 | #define CONFIG_USB_STORAGE | |
113 | #define CONFIG_DOS_PARTITION | |
114 | #define CONFIG_MAC_PARTITION | |
115 | #define CONFIG_ISO_PARTITION | |
a21d0c2c | 116 | #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 |
6d0f6bcf | 117 | #define CONFIG_SYS_USB_EHCI_CPU_INIT |
1552af70 TL |
118 | #endif |
119 | ||
120 | /* Realtime clock */ | |
121 | #define CONFIG_MCFRTC | |
122 | #undef RTC_DEBUG | |
6d0f6bcf | 123 | #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) |
1552af70 TL |
124 | |
125 | /* Timer */ | |
126 | #define CONFIG_MCFTMR | |
127 | #undef CONFIG_MCFPIT | |
128 | ||
129 | /* I2c */ | |
00f792e0 HS |
130 | #define CONFIG_SYS_I2C |
131 | #define CONFIG_SYS_I2C_FSL | |
132 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
133 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
134 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
a21d0c2c TL |
135 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
136 | ||
137 | /* DSPI and Serial Flash */ | |
ee0a8462 | 138 | #define CONFIG_CF_SPI |
a21d0c2c TL |
139 | #define CONFIG_CF_DSPI |
140 | #define CONFIG_HARD_SPI | |
a21d0c2c TL |
141 | #define CONFIG_SYS_SBFHDR_SIZE 0x7 |
142 | #ifdef CONFIG_CMD_SPI | |
143 | # define CONFIG_SYS_DSPI_CS2 | |
144 | # define CONFIG_SPI_FLASH | |
145 | # define CONFIG_SPI_FLASH_STMICRO | |
146 | ||
ee0a8462 TL |
147 | # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ |
148 | DSPI_CTAR_PCSSCK_1CLK | \ | |
149 | DSPI_CTAR_PASC(0) | \ | |
150 | DSPI_CTAR_PDT(0) | \ | |
151 | DSPI_CTAR_CSSCK(0) | \ | |
152 | DSPI_CTAR_ASC(0) | \ | |
153 | DSPI_CTAR_DT(1)) | |
a21d0c2c | 154 | #endif |
1552af70 TL |
155 | |
156 | /* Input, PCI, Flexbus, and VCO */ | |
157 | #define CONFIG_EXTRA_CLOCK | |
158 | ||
6d0f6bcf | 159 | #define CONFIG_SYS_INPUT_CLKSRC 16000000 |
1552af70 | 160 | |
a21d0c2c | 161 | #define CONFIG_PRAM 2048 /* 2048 KB */ |
1552af70 | 162 | |
a21d0c2c | 163 | #define CONFIG_SYS_PROMPT "-> " |
6d0f6bcf | 164 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
1552af70 TL |
165 | |
166 | #if defined(CONFIG_CMD_KGDB) | |
a21d0c2c | 167 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
1552af70 | 168 | #else |
a21d0c2c | 169 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
1552af70 | 170 | #endif |
a21d0c2c TL |
171 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
172 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
173 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
1552af70 | 174 | |
a21d0c2c | 175 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) |
1552af70 | 176 | |
6d0f6bcf | 177 | #define CONFIG_SYS_MBAR 0xFC000000 |
1552af70 TL |
178 | |
179 | /* | |
180 | * Low Level Configuration Settings | |
181 | * (address mappings, register initial values, etc.) | |
182 | * You should know what you are doing if you make changes here. | |
183 | */ | |
184 | ||
a21d0c2c | 185 | /* |
1552af70 TL |
186 | * Definitions for initial stack pointer and data area (in DPRAM) |
187 | */ | |
6d0f6bcf | 188 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 189 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
a21d0c2c | 190 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 191 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) |
a21d0c2c | 192 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) |
553f0982 | 193 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) |
1552af70 | 194 | |
a21d0c2c | 195 | /* |
1552af70 TL |
196 | * Start addresses for the final memory configuration |
197 | * (Set up by the startup code) | |
6d0f6bcf | 198 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
1552af70 | 199 | */ |
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
201 | #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ | |
202 | #define CONFIG_SYS_SDRAM_CFG1 0x43711630 | |
203 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 | |
204 | #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 | |
205 | #define CONFIG_SYS_SDRAM_EMOD 0x81810000 | |
206 | #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 | |
a21d0c2c | 207 | #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 |
6d0f6bcf JCPV |
208 | |
209 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
210 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
211 | ||
a21d0c2c | 212 | #ifdef CONFIG_CF_SBF |
14d0a02a | 213 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) |
a21d0c2c TL |
214 | #else |
215 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) | |
216 | #endif | |
6d0f6bcf JCPV |
217 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
218 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
219 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
1552af70 TL |
220 | |
221 | /* Initial Memory map for Linux */ | |
6d0f6bcf | 222 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 223 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
1552af70 | 224 | |
a21d0c2c TL |
225 | /* |
226 | * Configuration for environment | |
27f7ae70 JJ |
227 | * Environment is not embedded in u-boot. First time runing may have env |
228 | * crc error warning if there is no correct environment on the flash. | |
1552af70 | 229 | */ |
a21d0c2c TL |
230 | #ifdef CONFIG_CF_SBF |
231 | # define CONFIG_ENV_IS_IN_SPI_FLASH | |
232 | # define CONFIG_ENV_SPI_CS 2 | |
233 | #else | |
234 | # define CONFIG_ENV_IS_IN_FLASH 1 | |
235 | #endif | |
236 | #define CONFIG_ENV_OVERWRITE 1 | |
1552af70 TL |
237 | |
238 | /*----------------------------------------------------------------------- | |
239 | * FLASH organization | |
240 | */ | |
a21d0c2c | 241 | #ifdef CONFIG_SYS_STMICRO_BOOT |
ee0a8462 | 242 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
27f7ae70 | 243 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE |
a21d0c2c TL |
244 | # define CONFIG_ENV_OFFSET 0x30000 |
245 | # define CONFIG_ENV_SIZE 0x1000 | |
246 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
247 | #endif | |
248 | #ifdef CONFIG_SYS_SPANSION_BOOT | |
249 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
250 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
27f7ae70 | 251 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
a21d0c2c TL |
252 | # define CONFIG_ENV_SIZE 0x1000 |
253 | # define CONFIG_ENV_SECT_SIZE 0x8000 | |
254 | #endif | |
1552af70 | 255 | |
6d0f6bcf JCPV |
256 | #define CONFIG_SYS_FLASH_CFI |
257 | #ifdef CONFIG_SYS_FLASH_CFI | |
00b1883a | 258 | # define CONFIG_FLASH_CFI_DRIVER 1 |
bbf6bbff TL |
259 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
260 | # define CONFIG_FLASH_SPANSION_S29WS_N 1 | |
6d0f6bcf JCPV |
261 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
262 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
263 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
264 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
265 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
266 | # define CONFIG_SYS_FLASH_CHECKSUM | |
a21d0c2c | 267 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } |
1552af70 TL |
268 | #endif |
269 | ||
5296cb1d | 270 | #define LDS_BOARD_TEXT \ |
271 | arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ | |
272 | arch/m68k/lib/built-in.o (.text*) | |
273 | ||
1552af70 TL |
274 | /* |
275 | * This is setting for JFFS2 support in u-boot. | |
276 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
277 | */ | |
278 | #ifdef CONFIG_CMD_JFFS2 | |
279 | # define CONFIG_JFFS2_DEV "nor0" | |
280 | # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) | |
6d0f6bcf | 281 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) |
1552af70 TL |
282 | #endif |
283 | ||
284 | /*----------------------------------------------------------------------- | |
285 | * Cache Configuration | |
286 | */ | |
a21d0c2c | 287 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
1552af70 | 288 | |
dd9f054e | 289 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 290 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 291 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 292 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
293 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
294 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
295 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
296 | CF_ACR_EN | CF_ACR_SM_ALL) | |
297 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ | |
298 | CF_CACR_DISD | CF_CACR_INVI | \ | |
299 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
300 | CF_CACR_EUSP) | |
301 | ||
1552af70 TL |
302 | /*----------------------------------------------------------------------- |
303 | * Memory bank definitions | |
304 | */ | |
305 | /* | |
306 | * CS0 - NOR Flash | |
307 | * CS1 - Available | |
308 | * CS2 - Available | |
309 | * CS3 - Available | |
310 | * CS4 - Available | |
311 | * CS5 - Available | |
312 | */ | |
313 | ||
a21d0c2c TL |
314 | #ifdef CONFIG_CF_SBF |
315 | #define CONFIG_SYS_CS0_BASE 0x04000000 | |
316 | #define CONFIG_SYS_CS0_MASK 0x00FF0001 | |
317 | #define CONFIG_SYS_CS0_CTRL 0x00001FA0 | |
318 | #else | |
6d0f6bcf JCPV |
319 | #define CONFIG_SYS_CS0_BASE 0x00000000 |
320 | #define CONFIG_SYS_CS0_MASK 0x00FF0001 | |
321 | #define CONFIG_SYS_CS0_CTRL 0x00001FA0 | |
a21d0c2c | 322 | #endif |
1552af70 TL |
323 | |
324 | #endif /* _M52277EVB_H */ |