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1552af70 TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF52277 EVB board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
1552af70 TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M52277EVB_H | |
15 | #define _M52277EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
1552af70 TL |
21 | #define CONFIG_M52277EVB /* M52277EVB board */ |
22 | ||
1552af70 | 23 | #define CONFIG_MCFUART |
6d0f6bcf | 24 | #define CONFIG_SYS_UART_PORT (0) |
1552af70 TL |
25 | |
26 | #undef CONFIG_WATCHDOG | |
27 | ||
28 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
29 | ||
30 | /* | |
31 | * BOOTP options | |
32 | */ | |
33 | #define CONFIG_BOOTP_BOOTFILESIZE | |
34 | #define CONFIG_BOOTP_BOOTPATH | |
35 | #define CONFIG_BOOTP_GATEWAY | |
36 | #define CONFIG_BOOTP_HOSTNAME | |
37 | ||
38 | /* Command line configuration */ | |
1552af70 | 39 | #define CONFIG_CMD_REGINFO |
a21d0c2c TL |
40 | |
41 | #define CONFIG_HOSTNAME M52277EVB | |
42 | #define CONFIG_SYS_UBOOT_END 0x3FFFF | |
43 | #define CONFIG_SYS_LOAD_ADDR2 0x40010007 | |
44 | #ifdef CONFIG_SYS_STMICRO_BOOT | |
45 | /* ST Micro serial flash */ | |
1552af70 | 46 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d | 47 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
a21d0c2c TL |
48 | "loadaddr=0x40010000\0" \ |
49 | "uboot=u-boot.bin\0" \ | |
50 | "load=loadb ${loadaddr} ${baudrate};" \ | |
5368c55d | 51 | "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ |
1552af70 | 52 | "upd=run load; run prog\0" \ |
a21d0c2c TL |
53 | "prog=sf probe 0:2 10000 1;" \ |
54 | "sf erase 0 30000;" \ | |
55 | "sf write ${loadaddr} 0 30000;" \ | |
1552af70 TL |
56 | "save\0" \ |
57 | "" | |
a21d0c2c TL |
58 | #endif |
59 | #ifdef CONFIG_SYS_SPANSION_BOOT | |
60 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5368c55d | 61 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
a21d0c2c TL |
62 | "loadaddr=0x40010000\0" \ |
63 | "uboot=u-boot.bin\0" \ | |
64 | "load=loadb ${loadaddr} ${baudrate}\0" \ | |
65 | "upd=run load; run prog\0" \ | |
5368c55d MV |
66 | "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ |
67 | " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
68 | "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ | |
69 | __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
70 | "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ | |
a21d0c2c TL |
71 | " ${filesize}; save\0" \ |
72 | "updsbf=run loadsbf; run progsbf\0" \ | |
73 | "loadsbf=loadb ${loadaddr} ${baudrate};" \ | |
5368c55d | 74 | "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ |
a21d0c2c TL |
75 | "progsbf=sf probe 0:2 10000 1;" \ |
76 | "sf erase 0 30000;" \ | |
77 | "sf write ${loadaddr} 0 30000;" \ | |
78 | "" | |
79 | #endif | |
1552af70 TL |
80 | |
81 | /* LCD */ | |
82 | #ifdef CONFIG_CMD_BMP | |
1552af70 TL |
83 | #define CONFIG_SPLASH_SCREEN |
84 | #define CONFIG_LCD_LOGO | |
85 | #define CONFIG_SHARP_LQ035Q7DH06 | |
86 | #endif | |
87 | ||
88 | /* USB */ | |
89 | #ifdef CONFIG_CMD_USB | |
a21d0c2c | 90 | #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 |
6d0f6bcf | 91 | #define CONFIG_SYS_USB_EHCI_CPU_INIT |
1552af70 TL |
92 | #endif |
93 | ||
94 | /* Realtime clock */ | |
95 | #define CONFIG_MCFRTC | |
96 | #undef RTC_DEBUG | |
6d0f6bcf | 97 | #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) |
1552af70 TL |
98 | |
99 | /* Timer */ | |
100 | #define CONFIG_MCFTMR | |
101 | #undef CONFIG_MCFPIT | |
102 | ||
103 | /* I2c */ | |
00f792e0 HS |
104 | #define CONFIG_SYS_I2C |
105 | #define CONFIG_SYS_I2C_FSL | |
106 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
107 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
108 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
a21d0c2c TL |
109 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
110 | ||
111 | /* DSPI and Serial Flash */ | |
ee0a8462 | 112 | #define CONFIG_CF_SPI |
a21d0c2c TL |
113 | #define CONFIG_CF_DSPI |
114 | #define CONFIG_HARD_SPI | |
a21d0c2c TL |
115 | #define CONFIG_SYS_SBFHDR_SIZE 0x7 |
116 | #ifdef CONFIG_CMD_SPI | |
117 | # define CONFIG_SYS_DSPI_CS2 | |
a21d0c2c | 118 | |
ee0a8462 TL |
119 | # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ |
120 | DSPI_CTAR_PCSSCK_1CLK | \ | |
121 | DSPI_CTAR_PASC(0) | \ | |
122 | DSPI_CTAR_PDT(0) | \ | |
123 | DSPI_CTAR_CSSCK(0) | \ | |
124 | DSPI_CTAR_ASC(0) | \ | |
125 | DSPI_CTAR_DT(1)) | |
a21d0c2c | 126 | #endif |
1552af70 TL |
127 | |
128 | /* Input, PCI, Flexbus, and VCO */ | |
129 | #define CONFIG_EXTRA_CLOCK | |
130 | ||
6d0f6bcf | 131 | #define CONFIG_SYS_INPUT_CLKSRC 16000000 |
1552af70 | 132 | |
a21d0c2c | 133 | #define CONFIG_PRAM 2048 /* 2048 KB */ |
1552af70 | 134 | |
6d0f6bcf | 135 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
1552af70 TL |
136 | |
137 | #if defined(CONFIG_CMD_KGDB) | |
a21d0c2c | 138 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
1552af70 | 139 | #else |
a21d0c2c | 140 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
1552af70 | 141 | #endif |
a21d0c2c TL |
142 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
143 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
144 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
1552af70 | 145 | |
a21d0c2c | 146 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) |
1552af70 | 147 | |
6d0f6bcf | 148 | #define CONFIG_SYS_MBAR 0xFC000000 |
1552af70 TL |
149 | |
150 | /* | |
151 | * Low Level Configuration Settings | |
152 | * (address mappings, register initial values, etc.) | |
153 | * You should know what you are doing if you make changes here. | |
154 | */ | |
155 | ||
a21d0c2c | 156 | /* |
1552af70 TL |
157 | * Definitions for initial stack pointer and data area (in DPRAM) |
158 | */ | |
6d0f6bcf | 159 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 160 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
a21d0c2c | 161 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 162 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) |
a21d0c2c | 163 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) |
553f0982 | 164 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) |
1552af70 | 165 | |
a21d0c2c | 166 | /* |
1552af70 TL |
167 | * Start addresses for the final memory configuration |
168 | * (Set up by the startup code) | |
6d0f6bcf | 169 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
1552af70 | 170 | */ |
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
172 | #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ | |
173 | #define CONFIG_SYS_SDRAM_CFG1 0x43711630 | |
174 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 | |
175 | #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 | |
176 | #define CONFIG_SYS_SDRAM_EMOD 0x81810000 | |
177 | #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 | |
a21d0c2c | 178 | #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 |
6d0f6bcf JCPV |
179 | |
180 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
181 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
182 | ||
a21d0c2c | 183 | #ifdef CONFIG_CF_SBF |
14d0a02a | 184 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) |
a21d0c2c TL |
185 | #else |
186 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) | |
187 | #endif | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
189 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
190 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
1552af70 TL |
191 | |
192 | /* Initial Memory map for Linux */ | |
6d0f6bcf | 193 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 194 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
1552af70 | 195 | |
a21d0c2c TL |
196 | /* |
197 | * Configuration for environment | |
27f7ae70 JJ |
198 | * Environment is not embedded in u-boot. First time runing may have env |
199 | * crc error warning if there is no correct environment on the flash. | |
1552af70 | 200 | */ |
a21d0c2c TL |
201 | #ifdef CONFIG_CF_SBF |
202 | # define CONFIG_ENV_IS_IN_SPI_FLASH | |
203 | # define CONFIG_ENV_SPI_CS 2 | |
204 | #else | |
205 | # define CONFIG_ENV_IS_IN_FLASH 1 | |
206 | #endif | |
207 | #define CONFIG_ENV_OVERWRITE 1 | |
1552af70 TL |
208 | |
209 | /*----------------------------------------------------------------------- | |
210 | * FLASH organization | |
211 | */ | |
a21d0c2c | 212 | #ifdef CONFIG_SYS_STMICRO_BOOT |
ee0a8462 | 213 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
27f7ae70 | 214 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE |
a21d0c2c TL |
215 | # define CONFIG_ENV_OFFSET 0x30000 |
216 | # define CONFIG_ENV_SIZE 0x1000 | |
217 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
218 | #endif | |
219 | #ifdef CONFIG_SYS_SPANSION_BOOT | |
220 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
221 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
27f7ae70 | 222 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
a21d0c2c TL |
223 | # define CONFIG_ENV_SIZE 0x1000 |
224 | # define CONFIG_ENV_SECT_SIZE 0x8000 | |
225 | #endif | |
1552af70 | 226 | |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_FLASH_CFI |
228 | #ifdef CONFIG_SYS_FLASH_CFI | |
00b1883a | 229 | # define CONFIG_FLASH_CFI_DRIVER 1 |
bbf6bbff TL |
230 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
231 | # define CONFIG_FLASH_SPANSION_S29WS_N 1 | |
6d0f6bcf JCPV |
232 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
233 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
234 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
235 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
236 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
237 | # define CONFIG_SYS_FLASH_CHECKSUM | |
a21d0c2c | 238 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } |
1552af70 TL |
239 | #endif |
240 | ||
5296cb1d | 241 | #define LDS_BOARD_TEXT \ |
242 | arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ | |
243 | arch/m68k/lib/built-in.o (.text*) | |
244 | ||
1552af70 TL |
245 | /* |
246 | * This is setting for JFFS2 support in u-boot. | |
247 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
248 | */ | |
249 | #ifdef CONFIG_CMD_JFFS2 | |
250 | # define CONFIG_JFFS2_DEV "nor0" | |
251 | # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) | |
6d0f6bcf | 252 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) |
1552af70 TL |
253 | #endif |
254 | ||
255 | /*----------------------------------------------------------------------- | |
256 | * Cache Configuration | |
257 | */ | |
a21d0c2c | 258 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
1552af70 | 259 | |
dd9f054e | 260 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 261 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 262 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 263 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
264 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
265 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
266 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
267 | CF_ACR_EN | CF_ACR_SM_ALL) | |
268 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ | |
269 | CF_CACR_DISD | CF_CACR_INVI | \ | |
270 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
271 | CF_CACR_EUSP) | |
272 | ||
1552af70 TL |
273 | /*----------------------------------------------------------------------- |
274 | * Memory bank definitions | |
275 | */ | |
276 | /* | |
277 | * CS0 - NOR Flash | |
278 | * CS1 - Available | |
279 | * CS2 - Available | |
280 | * CS3 - Available | |
281 | * CS4 - Available | |
282 | * CS5 - Available | |
283 | */ | |
284 | ||
a21d0c2c TL |
285 | #ifdef CONFIG_CF_SBF |
286 | #define CONFIG_SYS_CS0_BASE 0x04000000 | |
287 | #define CONFIG_SYS_CS0_MASK 0x00FF0001 | |
288 | #define CONFIG_SYS_CS0_CTRL 0x00001FA0 | |
289 | #else | |
6d0f6bcf JCPV |
290 | #define CONFIG_SYS_CS0_BASE 0x00000000 |
291 | #define CONFIG_SYS_CS0_MASK 0x00FF0001 | |
292 | #define CONFIG_SYS_CS0_CTRL 0x00001FA0 | |
a21d0c2c | 293 | #endif |
1552af70 TL |
294 | |
295 | #endif /* _M52277EVB_H */ |