]>
Commit | Line | Data |
---|---|---|
1552af70 TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF52277 EVB board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
1552af70 TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M52277EVB_H | |
15 | #define _M52277EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
1552af70 TL |
21 | #define CONFIG_M52277EVB /* M52277EVB board */ |
22 | ||
1552af70 | 23 | #define CONFIG_MCFUART |
6d0f6bcf | 24 | #define CONFIG_SYS_UART_PORT (0) |
a21d0c2c | 25 | #define CONFIG_BAUDRATE 115200 |
1552af70 TL |
26 | |
27 | #undef CONFIG_WATCHDOG | |
28 | ||
29 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
30 | ||
31 | /* | |
32 | * BOOTP options | |
33 | */ | |
34 | #define CONFIG_BOOTP_BOOTFILESIZE | |
35 | #define CONFIG_BOOTP_BOOTPATH | |
36 | #define CONFIG_BOOTP_GATEWAY | |
37 | #define CONFIG_BOOTP_HOSTNAME | |
38 | ||
39 | /* Command line configuration */ | |
1552af70 TL |
40 | #define CONFIG_CMD_CACHE |
41 | #define CONFIG_CMD_DATE | |
1552af70 TL |
42 | #define CONFIG_CMD_I2C |
43 | #define CONFIG_CMD_JFFS2 | |
1552af70 TL |
44 | #define CONFIG_CMD_REGINFO |
45 | #undef CONFIG_CMD_USB | |
46 | #undef CONFIG_CMD_BMP | |
a21d0c2c TL |
47 | #define CONFIG_CMD_SPI |
48 | #define CONFIG_CMD_SF | |
49 | ||
50 | #define CONFIG_HOSTNAME M52277EVB | |
51 | #define CONFIG_SYS_UBOOT_END 0x3FFFF | |
52 | #define CONFIG_SYS_LOAD_ADDR2 0x40010007 | |
53 | #ifdef CONFIG_SYS_STMICRO_BOOT | |
54 | /* ST Micro serial flash */ | |
1552af70 | 55 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d | 56 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
a21d0c2c TL |
57 | "loadaddr=0x40010000\0" \ |
58 | "uboot=u-boot.bin\0" \ | |
59 | "load=loadb ${loadaddr} ${baudrate};" \ | |
5368c55d | 60 | "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ |
1552af70 | 61 | "upd=run load; run prog\0" \ |
a21d0c2c TL |
62 | "prog=sf probe 0:2 10000 1;" \ |
63 | "sf erase 0 30000;" \ | |
64 | "sf write ${loadaddr} 0 30000;" \ | |
1552af70 TL |
65 | "save\0" \ |
66 | "" | |
a21d0c2c TL |
67 | #endif |
68 | #ifdef CONFIG_SYS_SPANSION_BOOT | |
69 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5368c55d | 70 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
a21d0c2c TL |
71 | "loadaddr=0x40010000\0" \ |
72 | "uboot=u-boot.bin\0" \ | |
73 | "load=loadb ${loadaddr} ${baudrate}\0" \ | |
74 | "upd=run load; run prog\0" \ | |
5368c55d MV |
75 | "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ |
76 | " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
77 | "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ | |
78 | __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
79 | "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ | |
a21d0c2c TL |
80 | " ${filesize}; save\0" \ |
81 | "updsbf=run loadsbf; run progsbf\0" \ | |
82 | "loadsbf=loadb ${loadaddr} ${baudrate};" \ | |
5368c55d | 83 | "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ |
a21d0c2c TL |
84 | "progsbf=sf probe 0:2 10000 1;" \ |
85 | "sf erase 0 30000;" \ | |
86 | "sf write ${loadaddr} 0 30000;" \ | |
87 | "" | |
88 | #endif | |
1552af70 | 89 | |
a21d0c2c | 90 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
1552af70 TL |
91 | /* LCD */ |
92 | #ifdef CONFIG_CMD_BMP | |
93 | #define CONFIG_LCD | |
94 | #define CONFIG_SPLASH_SCREEN | |
95 | #define CONFIG_LCD_LOGO | |
96 | #define CONFIG_SHARP_LQ035Q7DH06 | |
97 | #endif | |
98 | ||
99 | /* USB */ | |
100 | #ifdef CONFIG_CMD_USB | |
101 | #define CONFIG_USB_EHCI | |
102 | #define CONFIG_USB_STORAGE | |
103 | #define CONFIG_DOS_PARTITION | |
104 | #define CONFIG_MAC_PARTITION | |
105 | #define CONFIG_ISO_PARTITION | |
a21d0c2c | 106 | #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 |
6d0f6bcf | 107 | #define CONFIG_SYS_USB_EHCI_CPU_INIT |
1552af70 TL |
108 | #endif |
109 | ||
110 | /* Realtime clock */ | |
111 | #define CONFIG_MCFRTC | |
112 | #undef RTC_DEBUG | |
6d0f6bcf | 113 | #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) |
1552af70 TL |
114 | |
115 | /* Timer */ | |
116 | #define CONFIG_MCFTMR | |
117 | #undef CONFIG_MCFPIT | |
118 | ||
119 | /* I2c */ | |
00f792e0 HS |
120 | #define CONFIG_SYS_I2C |
121 | #define CONFIG_SYS_I2C_FSL | |
122 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
123 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
124 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
a21d0c2c TL |
125 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
126 | ||
127 | /* DSPI and Serial Flash */ | |
ee0a8462 | 128 | #define CONFIG_CF_SPI |
a21d0c2c TL |
129 | #define CONFIG_CF_DSPI |
130 | #define CONFIG_HARD_SPI | |
a21d0c2c TL |
131 | #define CONFIG_SYS_SBFHDR_SIZE 0x7 |
132 | #ifdef CONFIG_CMD_SPI | |
133 | # define CONFIG_SYS_DSPI_CS2 | |
a21d0c2c | 134 | |
ee0a8462 TL |
135 | # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ |
136 | DSPI_CTAR_PCSSCK_1CLK | \ | |
137 | DSPI_CTAR_PASC(0) | \ | |
138 | DSPI_CTAR_PDT(0) | \ | |
139 | DSPI_CTAR_CSSCK(0) | \ | |
140 | DSPI_CTAR_ASC(0) | \ | |
141 | DSPI_CTAR_DT(1)) | |
a21d0c2c | 142 | #endif |
1552af70 TL |
143 | |
144 | /* Input, PCI, Flexbus, and VCO */ | |
145 | #define CONFIG_EXTRA_CLOCK | |
146 | ||
6d0f6bcf | 147 | #define CONFIG_SYS_INPUT_CLKSRC 16000000 |
1552af70 | 148 | |
a21d0c2c | 149 | #define CONFIG_PRAM 2048 /* 2048 KB */ |
1552af70 | 150 | |
6d0f6bcf | 151 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
1552af70 TL |
152 | |
153 | #if defined(CONFIG_CMD_KGDB) | |
a21d0c2c | 154 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
1552af70 | 155 | #else |
a21d0c2c | 156 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
1552af70 | 157 | #endif |
a21d0c2c TL |
158 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
159 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
160 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
1552af70 | 161 | |
a21d0c2c | 162 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) |
1552af70 | 163 | |
6d0f6bcf | 164 | #define CONFIG_SYS_MBAR 0xFC000000 |
1552af70 TL |
165 | |
166 | /* | |
167 | * Low Level Configuration Settings | |
168 | * (address mappings, register initial values, etc.) | |
169 | * You should know what you are doing if you make changes here. | |
170 | */ | |
171 | ||
a21d0c2c | 172 | /* |
1552af70 TL |
173 | * Definitions for initial stack pointer and data area (in DPRAM) |
174 | */ | |
6d0f6bcf | 175 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 176 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
a21d0c2c | 177 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 178 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) |
a21d0c2c | 179 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) |
553f0982 | 180 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) |
1552af70 | 181 | |
a21d0c2c | 182 | /* |
1552af70 TL |
183 | * Start addresses for the final memory configuration |
184 | * (Set up by the startup code) | |
6d0f6bcf | 185 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
1552af70 | 186 | */ |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
188 | #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ | |
189 | #define CONFIG_SYS_SDRAM_CFG1 0x43711630 | |
190 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 | |
191 | #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 | |
192 | #define CONFIG_SYS_SDRAM_EMOD 0x81810000 | |
193 | #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 | |
a21d0c2c | 194 | #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 |
6d0f6bcf JCPV |
195 | |
196 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
197 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
198 | ||
a21d0c2c | 199 | #ifdef CONFIG_CF_SBF |
14d0a02a | 200 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) |
a21d0c2c TL |
201 | #else |
202 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) | |
203 | #endif | |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
205 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
206 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
1552af70 TL |
207 | |
208 | /* Initial Memory map for Linux */ | |
6d0f6bcf | 209 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 210 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
1552af70 | 211 | |
a21d0c2c TL |
212 | /* |
213 | * Configuration for environment | |
27f7ae70 JJ |
214 | * Environment is not embedded in u-boot. First time runing may have env |
215 | * crc error warning if there is no correct environment on the flash. | |
1552af70 | 216 | */ |
a21d0c2c TL |
217 | #ifdef CONFIG_CF_SBF |
218 | # define CONFIG_ENV_IS_IN_SPI_FLASH | |
219 | # define CONFIG_ENV_SPI_CS 2 | |
220 | #else | |
221 | # define CONFIG_ENV_IS_IN_FLASH 1 | |
222 | #endif | |
223 | #define CONFIG_ENV_OVERWRITE 1 | |
1552af70 TL |
224 | |
225 | /*----------------------------------------------------------------------- | |
226 | * FLASH organization | |
227 | */ | |
a21d0c2c | 228 | #ifdef CONFIG_SYS_STMICRO_BOOT |
ee0a8462 | 229 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
27f7ae70 | 230 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE |
a21d0c2c TL |
231 | # define CONFIG_ENV_OFFSET 0x30000 |
232 | # define CONFIG_ENV_SIZE 0x1000 | |
233 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
234 | #endif | |
235 | #ifdef CONFIG_SYS_SPANSION_BOOT | |
236 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
237 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
27f7ae70 | 238 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
a21d0c2c TL |
239 | # define CONFIG_ENV_SIZE 0x1000 |
240 | # define CONFIG_ENV_SECT_SIZE 0x8000 | |
241 | #endif | |
1552af70 | 242 | |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_FLASH_CFI |
244 | #ifdef CONFIG_SYS_FLASH_CFI | |
00b1883a | 245 | # define CONFIG_FLASH_CFI_DRIVER 1 |
bbf6bbff TL |
246 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
247 | # define CONFIG_FLASH_SPANSION_S29WS_N 1 | |
6d0f6bcf JCPV |
248 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
249 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
250 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
251 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
252 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
253 | # define CONFIG_SYS_FLASH_CHECKSUM | |
a21d0c2c | 254 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } |
1552af70 TL |
255 | #endif |
256 | ||
5296cb1d | 257 | #define LDS_BOARD_TEXT \ |
258 | arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ | |
259 | arch/m68k/lib/built-in.o (.text*) | |
260 | ||
1552af70 TL |
261 | /* |
262 | * This is setting for JFFS2 support in u-boot. | |
263 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
264 | */ | |
265 | #ifdef CONFIG_CMD_JFFS2 | |
266 | # define CONFIG_JFFS2_DEV "nor0" | |
267 | # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) | |
6d0f6bcf | 268 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) |
1552af70 TL |
269 | #endif |
270 | ||
271 | /*----------------------------------------------------------------------- | |
272 | * Cache Configuration | |
273 | */ | |
a21d0c2c | 274 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
1552af70 | 275 | |
dd9f054e | 276 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 277 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 278 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 279 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
280 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
281 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
282 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
283 | CF_ACR_EN | CF_ACR_SM_ALL) | |
284 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ | |
285 | CF_CACR_DISD | CF_CACR_INVI | \ | |
286 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
287 | CF_CACR_EUSP) | |
288 | ||
1552af70 TL |
289 | /*----------------------------------------------------------------------- |
290 | * Memory bank definitions | |
291 | */ | |
292 | /* | |
293 | * CS0 - NOR Flash | |
294 | * CS1 - Available | |
295 | * CS2 - Available | |
296 | * CS3 - Available | |
297 | * CS4 - Available | |
298 | * CS5 - Available | |
299 | */ | |
300 | ||
a21d0c2c TL |
301 | #ifdef CONFIG_CF_SBF |
302 | #define CONFIG_SYS_CS0_BASE 0x04000000 | |
303 | #define CONFIG_SYS_CS0_MASK 0x00FF0001 | |
304 | #define CONFIG_SYS_CS0_CTRL 0x00001FA0 | |
305 | #else | |
6d0f6bcf JCPV |
306 | #define CONFIG_SYS_CS0_BASE 0x00000000 |
307 | #define CONFIG_SYS_CS0_MASK 0x00FF0001 | |
308 | #define CONFIG_SYS_CS0_CTRL 0x00001FA0 | |
a21d0c2c | 309 | #endif |
1552af70 TL |
310 | |
311 | #endif /* _M52277EVB_H */ |