]>
Commit | Line | Data |
---|---|---|
536e7dac TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF53017EVB. | |
3 | * | |
4 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
536e7dac TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M53017EVB_H | |
15 | #define _M53017EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
536e7dac TL |
21 | |
22 | #define CONFIG_MCFUART | |
23 | #define CONFIG_SYS_UART_PORT (0) | |
24 | #define CONFIG_BAUDRATE 115200 | |
536e7dac TL |
25 | |
26 | #undef CONFIG_WATCHDOG | |
27 | #define CONFIG_WATCHDOG_TIMEOUT 5000 | |
28 | ||
29 | /* Command line configuration */ | |
536e7dac TL |
30 | #define CONFIG_CMD_CACHE |
31 | #define CONFIG_CMD_DATE | |
536e7dac | 32 | #define CONFIG_CMD_MII |
536e7dac TL |
33 | #define CONFIG_CMD_REGINFO |
34 | ||
35 | #define CONFIG_SYS_UNIFY_CACHE | |
36 | ||
37 | #define CONFIG_MCFFEC | |
38 | #ifdef CONFIG_MCFFEC | |
536e7dac TL |
39 | # define CONFIG_MII 1 |
40 | # define CONFIG_MII_INIT 1 | |
41 | # define CONFIG_SYS_DISCOVER_PHY | |
42 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
9e8e9270 TL |
43 | # define CONFIG_SYS_TX_ETH_BUFFER 8 |
44 | # define CONFIG_SYS_FEC_BUF_USE_SRAM | |
536e7dac TL |
45 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
46 | # define CONFIG_HAS_ETH1 | |
47 | ||
48 | # define CONFIG_SYS_FEC0_PINMUX 0 | |
49 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
50 | # define CONFIG_SYS_FEC1_PINMUX 0 | |
51 | # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE | |
52 | # define MCFFEC_TOUT_LOOP 50000 | |
052c0891 TL |
53 | |
54 | # define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2" | |
55 | ||
536e7dac TL |
56 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
57 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
58 | # define FECDUPLEX FULL | |
59 | # define FECSPEED _100BASET | |
60 | # else | |
61 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
62 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
63 | # endif | |
64 | # endif /* CONFIG_SYS_DISCOVER_PHY */ | |
65 | #endif | |
66 | ||
67 | #define CONFIG_MCFRTC | |
68 | #undef RTC_DEBUG | |
69 | #define CONFIG_SYS_RTC_CNT (0x8000) | |
70 | #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) | |
71 | ||
72 | /* Timer */ | |
73 | #define CONFIG_MCFTMR | |
74 | #undef CONFIG_MCFPIT | |
75 | ||
76 | /* I2C */ | |
00f792e0 HS |
77 | #define CONFIG_SYS_I2C |
78 | #define CONFIG_SYS_I2C_FSL | |
79 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
80 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
81 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
536e7dac TL |
82 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
83 | ||
84 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
85 | #define CONFIG_UDP_CHECKSUM | |
86 | ||
87 | #ifdef CONFIG_MCFFEC | |
536e7dac TL |
88 | # define CONFIG_IPADDR 192.162.1.2 |
89 | # define CONFIG_NETMASK 255.255.255.0 | |
90 | # define CONFIG_SERVERIP 192.162.1.1 | |
91 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
536e7dac TL |
92 | #endif /* FEC_ENET */ |
93 | ||
94 | #define CONFIG_HOSTNAME M53017 | |
95 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
96 | "netdev=eth0\0" \ | |
97 | "loadaddr=40010000\0" \ | |
98 | "u-boot=u-boot.bin\0" \ | |
99 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
100 | "upd=run load; run prog\0" \ | |
101 | "prog=prot off 0 3ffff;" \ | |
102 | "era 0 3ffff;" \ | |
103 | "cp.b ${loadaddr} 0 ${filesize};" \ | |
104 | "save\0" \ | |
105 | "" | |
106 | ||
107 | #define CONFIG_PRAM 512 /* 512 KB */ | |
536e7dac TL |
108 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
109 | ||
110 | #ifdef CONFIG_CMD_KGDB | |
111 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
112 | #else | |
113 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
114 | #endif | |
115 | ||
116 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
117 | #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ | |
118 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ | |
119 | #define CONFIG_SYS_LOAD_ADDR 0x40010000 | |
120 | ||
536e7dac TL |
121 | #define CONFIG_SYS_CLK 80000000 |
122 | #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 | |
123 | ||
124 | #define CONFIG_SYS_MBAR 0xFC000000 | |
125 | ||
126 | /* | |
127 | * Low Level Configuration Settings | |
128 | * (address mappings, register initial values, etc.) | |
129 | * You should know what you are doing if you make changes here. | |
130 | */ | |
131 | /* | |
132 | * Definitions for initial stack pointer and data area (in DPRAM) | |
133 | */ | |
134 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 | |
553f0982 | 135 | #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ |
9e8e9270 | 136 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 137 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) |
536e7dac TL |
138 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
139 | ||
140 | /* | |
141 | * Start addresses for the final memory configuration | |
142 | * (Set up by the startup code) | |
143 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 | |
144 | */ | |
145 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
146 | #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ | |
147 | #define CONFIG_SYS_SDRAM_CFG1 0x43711630 | |
148 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 | |
9e8e9270 | 149 | #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 |
536e7dac TL |
150 | #define CONFIG_SYS_SDRAM_EMOD 0x80010000 |
151 | #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 | |
152 | ||
153 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
154 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
155 | ||
156 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) | |
157 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
158 | ||
159 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
160 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
161 | ||
162 | /* | |
163 | * For booting Linux, the board info and command line data | |
164 | * have to be in the first 8 MB of memory, since this is | |
165 | * the maximum mapped by the Linux kernel during initialization ?? | |
166 | */ | |
167 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) | |
d6e4baf4 | 168 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
536e7dac TL |
169 | |
170 | /*----------------------------------------------------------------------- | |
171 | * FLASH organization | |
172 | */ | |
173 | #define CONFIG_SYS_FLASH_CFI | |
174 | #ifdef CONFIG_SYS_FLASH_CFI | |
175 | # define CONFIG_FLASH_CFI_DRIVER 1 | |
bbf6bbff TL |
176 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
177 | # define CONFIG_FLASH_SPANSION_S29WS_N 1 | |
4567c7bf | 178 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
536e7dac TL |
179 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
180 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
181 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
182 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
183 | #endif | |
184 | ||
185 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
186 | ||
187 | /* Configuration for environment | |
188 | * Environment is embedded in u-boot in the second sector of the flash | |
189 | */ | |
944ab340 | 190 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000) |
536e7dac TL |
191 | #define CONFIG_ENV_SIZE 0x1000 |
192 | #define CONFIG_ENV_SECT_SIZE 0x8000 | |
193 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
194 | ||
5296cb1d | 195 | #define LDS_BOARD_TEXT \ |
196 | . = DEFINED(env_offset) ? env_offset : .; \ | |
197 | common/env_embedded.o (.text*) | |
198 | ||
536e7dac TL |
199 | /*----------------------------------------------------------------------- |
200 | * Cache Configuration | |
201 | */ | |
202 | #define CONFIG_SYS_CACHELINE_SIZE 16 | |
203 | ||
dd9f054e | 204 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 205 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 206 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 207 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
208 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) |
209 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
210 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
211 | CF_ACR_EN | CF_ACR_SM_ALL) | |
212 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ | |
213 | CF_CACR_DCM_P) | |
214 | ||
536e7dac TL |
215 | /*----------------------------------------------------------------------- |
216 | * Chipselect bank definitions | |
217 | */ | |
218 | /* | |
219 | * CS0 - NOR Flash | |
220 | * CS1 - Ext SRAM | |
221 | * CS2 - Available | |
222 | * CS3 - Available | |
223 | * CS4 - Available | |
224 | * CS5 - Available | |
225 | */ | |
226 | #define CONFIG_SYS_CS0_BASE 0 | |
227 | #define CONFIG_SYS_CS0_MASK 0x00FF0001 | |
228 | #define CONFIG_SYS_CS0_CTRL 0x00001FA0 | |
229 | ||
230 | #define CONFIG_SYS_CS1_BASE 0xC0000000 | |
231 | #define CONFIG_SYS_CS1_MASK 0x00070001 | |
232 | #define CONFIG_SYS_CS1_CTRL 0x00001FA0 | |
233 | ||
234 | #endif /* _M53017EVB_H */ |