[people/ms/u-boot.git] / include / configs / M5373EVB.h

/*
 * Configuation settings for the Freescale MCF5373 FireEngine board.
 *
 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5373EVB_H
#define _M5373EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT	3360	/* timeout in ms, max is 3.36 sec */

#define CONFIG_SYS_UNIFY_CACHE

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_MCFRTC
#undef RTC_DEBUG

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

#define CONFIG_UDP_CHECKSUM

#ifdef CONFIG_MCFFEC
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#endif				/* FEC_ENET */

#define CONFIG_HOSTNAME		M5373EVB
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"			\
	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0"	\
	"u-boot=u-boot.bin\0"	\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"	\
	"prog=prot off 0 3ffff;"	\
	"era 0 3ffff;"	\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"	\
	""

#define CONFIG_PRAM		512	/* 512 KB */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#define CONFIG_SYS_LOAD_ADDR		0x40010000

#define CONFIG_SYS_CLK			80000000
#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 3

#define CONFIG_SYS_MBAR		0xFC000000

#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x53722730
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
#define CONFIG_SYS_SDRAM_EMOD		0x40010000
#define CONFIG_SYS_SDRAM_MODE		0x018D0000

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#endif

#ifdef CONFIG_NANDFLASH_SIZE
#	define CONFIG_SYS_MAX_NAND_DEVICE	1
#	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
#	define CONFIG_SYS_NAND_SIZE		1
#	define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#	define NAND_ALLOW_ERASE_ALL	1
#	define CONFIG_JFFS2_NAND	1
#	define CONFIG_JFFS2_DEV		"nand0"
#	define CONFIG_JFFS2_PART_SIZE	(CONFIG_SYS_CS2_MASK & ~1)
#	define CONFIG_JFFS2_PART_OFFSET	0x00000000
#endif

#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	env/embedded.o(.text*);

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
					 CF_CACR_DCM_P)

/*-----------------------------------------------------------------------
 * Chipselect bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - CompactFlash and registers
 * CS2 - NAND Flash 16, 32, or 64MB
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */
#define CONFIG_SYS_CS0_BASE		0
#define CONFIG_SYS_CS0_MASK		0x007f0001
#define CONFIG_SYS_CS0_CTRL		0x00001fa0

#define CONFIG_SYS_CS1_BASE		0x10000000
#define CONFIG_SYS_CS1_MASK		0x001f0001
#define CONFIG_SYS_CS1_CTRL		0x002A3780

#ifdef CONFIG_NANDFLASH_SIZE
#define CONFIG_SYS_CS2_BASE		0x20000000
#define CONFIG_SYS_CS2_MASK		((CONFIG_NANDFLASH_SIZE << 20) | 1)
#define CONFIG_SYS_CS2_CTRL		0x00001f60
#endif

#endif				/* _M5373EVB_H */
Commit	Line	Data
aa5f1f9d TL	1	/*
	2	* Configuation settings for the Freescale MCF5373 FireEngine board.
	3	*
2ee03c6e	4	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
aa5f1f9d TL	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
aa5f1f9d TL	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
aa5f1f9d TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M5373EVB_H
	15	#define _M5373EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
aa5f1f9d	21
aa5f1f9d	22	#define CONFIG_MCFUART
6d0f6bcf	23	#define CONFIG_SYS_UART_PORT (0)
aa5f1f9d TL	24
	25	#undef CONFIG_WATCHDOG
	26	#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
	27
6d0f6bcf	28	#define CONFIG_SYS_UNIFY_CACHE
aa5f1f9d TL	29
	30	#define CONFIG_MCFFEC
	31	#ifdef CONFIG_MCFFEC
aa5f1f9d	32	# define CONFIG_MII 1
0f3ba7e9	33	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	34	# define CONFIG_SYS_DISCOVER_PHY
	35	# define CONFIG_SYS_RX_ETH_BUFFER 8
	36	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
aa5f1f9d	37
6d0f6bcf JCPV	38	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	39	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	40	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	41	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	42	# ifndef CONFIG_SYS_DISCOVER_PHY
aa5f1f9d TL	43	# define FECDUPLEX FULL
	44	# define FECSPEED _100BASET
	45	# else
6d0f6bcf JCPV	46	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	47	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
aa5f1f9d	48	# endif
6d0f6bcf	49	# endif /* CONFIG_SYS_DISCOVER_PHY */
aa5f1f9d TL	50	#endif
	51
	52	#define CONFIG_MCFRTC
	53	#undef RTC_DEBUG
	54
	55	/* Timer */
	56	#define CONFIG_MCFTMR
	57	#undef CONFIG_MCFPIT
	58
	59	/* I2C */
00f792e0 HS	60	#define CONFIG_SYS_I2C
	61	#define CONFIG_SYS_I2C_FSL
	62	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	63	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	64	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
6d0f6bcf	65	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
aa5f1f9d	66
aa5f1f9d TL	67	#define CONFIG_UDP_CHECKSUM
	68
	69	#ifdef CONFIG_MCFFEC
aa5f1f9d TL	70	# define CONFIG_IPADDR 192.162.1.2
	71	# define CONFIG_NETMASK 255.255.255.0
	72	# define CONFIG_SERVERIP 192.162.1.1
	73	# define CONFIG_GATEWAYIP 192.162.1.1
aa5f1f9d TL	74	#endif /* FEC_ENET */
	75
	76	#define CONFIG_HOSTNAME M5373EVB
	77	#define CONFIG_EXTRA_ENV_SETTINGS \
	78	"netdev=eth0\0" \
5368c55d	79	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
aa5f1f9d TL	80	"u-boot=u-boot.bin\0" \
	81	"load=tftp ${loadaddr) ${u-boot}\0" \
	82	"upd=run load; run prog\0" \
09933fb0 JJ	83	"prog=prot off 0 3ffff;" \
09933fb0 JJ	84	"era 0 3ffff;" \
aa5f1f9d TL	85	"cp.b ${loadaddr} 0 ${filesize};" \
	86	"save\0" \
	87	""
	88
	89	#define CONFIG_PRAM 512 /* 512 KB */
6d0f6bcf	90	#define CONFIG_SYS_LONGHELP /* undef to save memory */
aa5f1f9d	91
6d0f6bcf	92	#define CONFIG_SYS_LOAD_ADDR 0x40010000
aa5f1f9d	93
6d0f6bcf JCPV	94	#define CONFIG_SYS_CLK 80000000
6d0f6bcf JCPV	95	#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
aa5f1f9d	96
6d0f6bcf	97	#define CONFIG_SYS_MBAR 0xFC000000
aa5f1f9d	98
6d0f6bcf	99	#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
aa5f1f9d TL	100
	101	/*
	102	* Low Level Configuration Settings
	103	* (address mappings, register initial values, etc.)
	104	* You should know what you are doing if you make changes here.
	105	*/
	106	/*-----------------------------------------------------------------------
	107	* Definitions for initial stack pointer and data area (in DPRAM)
	108	*/
6d0f6bcf	109	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	110	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
6d0f6bcf	111	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	112	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
6d0f6bcf	113	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
aa5f1f9d TL	114
	115	/*-----------------------------------------------------------------------
	116	* Start addresses for the final memory configuration
	117	* (Set up by the startup code)
6d0f6bcf	118	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
aa5f1f9d	119	*/
6d0f6bcf JCPV	120	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	121	#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
	122	#define CONFIG_SYS_SDRAM_CFG1 0x53722730
	123	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
	124	#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
	125	#define CONFIG_SYS_SDRAM_EMOD 0x40010000
	126	#define CONFIG_SYS_SDRAM_MODE 0x018D0000
aa5f1f9d	127
6d0f6bcf JCPV	128	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
6d0f6bcf JCPV	129	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
aa5f1f9d	130
6d0f6bcf JCPV	131	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d0f6bcf JCPV	132	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
aa5f1f9d	133
6d0f6bcf JCPV	134	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	135	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
aa5f1f9d TL	136
	137	/*
	138	* For booting Linux, the board info and command line data
	139	* have to be in the first 8 MB of memory, since this is
	140	* the maximum mapped by the Linux kernel during initialization ??
	141	*/
6d0f6bcf	142	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	143	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
aa5f1f9d TL	144
	145	/*-----------------------------------------------------------------------
	146	* FLASH organization
	147	*/
6d0f6bcf JCPV	148	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	149	#ifdef CONFIG_SYS_FLASH_CFI
00b1883a	150	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	151	# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
	152	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	153	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	154	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	155	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
aa5f1f9d TL	156	#endif
aa5f1f9d TL	157
2ee03c6e	158	#ifdef CONFIG_NANDFLASH_SIZE
6d0f6bcf JCPV	159	# define CONFIG_SYS_MAX_NAND_DEVICE 1
	160	# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
	161	# define CONFIG_SYS_NAND_SIZE 1
	162	# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
aa5f1f9d TL	163	# define NAND_ALLOW_ERASE_ALL 1
	164	# define CONFIG_JFFS2_NAND 1
	165	# define CONFIG_JFFS2_DEV "nand0"
6d0f6bcf	166	# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
aa5f1f9d TL	167	# define CONFIG_JFFS2_PART_OFFSET 0x00000000
	168	#endif
	169
6d0f6bcf	170	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
aa5f1f9d TL	171
	172	/* Configuration for environment
	173	* Environment is embedded in u-boot in the second sector of the flash
	174	*/
0e8d1586 JCPV	175	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	176	#define CONFIG_ENV_SECT_SIZE 0x2000
aa5f1f9d	177
5296cb1d	178	#define LDS_BOARD_TEXT \
0649cd0d SG	179	. = DEFINED(env_offset) ? env_offset : .; \
0649cd0d SG	180	env/embedded.o(.text*);
5296cb1d	181
aa5f1f9d TL	182	/*-----------------------------------------------------------------------
	183	* Cache Configuration
	184	*/
6d0f6bcf	185	#define CONFIG_SYS_CACHELINE_SIZE 16
aa5f1f9d	186
dd9f054e	187	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	188	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	189	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	190	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	191	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
	192	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	193	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	194	CF_ACR_EN \| CF_ACR_SM_ALL)
	195	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC \| CF_CACR_CINVA \| \
	196	CF_CACR_DCM_P)
	197
aa5f1f9d TL	198	/*-----------------------------------------------------------------------
	199	* Chipselect bank definitions
	200	*/
	201	/*
	202	* CS0 - NOR Flash 1, 2, 4, or 8MB
	203	* CS1 - CompactFlash and registers
	204	* CS2 - NAND Flash 16, 32, or 64MB
	205	* CS3 - Available
	206	* CS4 - Available
	207	* CS5 - Available
	208	*/
6d0f6bcf JCPV	209	#define CONFIG_SYS_CS0_BASE 0
	210	#define CONFIG_SYS_CS0_MASK 0x007f0001
	211	#define CONFIG_SYS_CS0_CTRL 0x00001fa0
aa5f1f9d	212
6d0f6bcf JCPV	213	#define CONFIG_SYS_CS1_BASE 0x10000000
	214	#define CONFIG_SYS_CS1_MASK 0x001f0001
	215	#define CONFIG_SYS_CS1_CTRL 0x002A3780
aa5f1f9d	216
2ee03c6e	217	#ifdef CONFIG_NANDFLASH_SIZE
6d0f6bcf	218	#define CONFIG_SYS_CS2_BASE 0x20000000
2ee03c6e	219	#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) \| 1)
6d0f6bcf	220	#define CONFIG_SYS_CS2_CTRL 0x00001f60
aa5f1f9d TL	221	#endif
	222
	223	#endif /* _M5373EVB_H */