]>
Commit | Line | Data |
---|---|---|
8ae158cd TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF54455 EVB board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
8ae158cd TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
e8ee8f3a TL |
14 | #ifndef _M54455EVB_H |
15 | #define _M54455EVB_H | |
8ae158cd TL |
16 | |
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
8ae158cd TL |
21 | #define CONFIG_M54455EVB /* M54455EVB board */ |
22 | ||
1313db48 AW |
23 | #define CONFIG_DISPLAY_BOARDINFO |
24 | ||
8ae158cd | 25 | #define CONFIG_MCFUART |
6d0f6bcf | 26 | #define CONFIG_SYS_UART_PORT (0) |
8ae158cd | 27 | #define CONFIG_BAUDRATE 115200 |
8ae158cd TL |
28 | |
29 | #undef CONFIG_WATCHDOG | |
30 | ||
31 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
32 | ||
33 | /* | |
34 | * BOOTP options | |
35 | */ | |
36 | #define CONFIG_BOOTP_BOOTFILESIZE | |
37 | #define CONFIG_BOOTP_BOOTPATH | |
38 | #define CONFIG_BOOTP_GATEWAY | |
39 | #define CONFIG_BOOTP_HOSTNAME | |
40 | ||
41 | /* Command line configuration */ | |
8ae158cd TL |
42 | #define CONFIG_CMD_CACHE |
43 | #define CONFIG_CMD_DATE | |
44 | #define CONFIG_CMD_DHCP | |
45 | #define CONFIG_CMD_ELF | |
46 | #define CONFIG_CMD_EXT2 | |
47 | #define CONFIG_CMD_FAT | |
8ae158cd TL |
48 | #define CONFIG_CMD_I2C |
49 | #define CONFIG_CMD_IDE | |
50 | #define CONFIG_CMD_JFFS2 | |
8ae158cd | 51 | #define CONFIG_CMD_MII |
e8ee8f3a | 52 | #undef CONFIG_CMD_PCI |
8ae158cd TL |
53 | #define CONFIG_CMD_PING |
54 | #define CONFIG_CMD_REGINFO | |
a7323bba | 55 | #define CONFIG_CMD_SPI |
922cd751 | 56 | #define CONFIG_CMD_SF |
8ae158cd | 57 | |
8ae158cd TL |
58 | |
59 | /* Network configuration */ | |
60 | #define CONFIG_MCFFEC | |
61 | #ifdef CONFIG_MCFFEC | |
8ae158cd | 62 | # define CONFIG_MII 1 |
0f3ba7e9 | 63 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
64 | # define CONFIG_SYS_DISCOVER_PHY |
65 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
66 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
67 | ||
68 | # define CONFIG_SYS_FEC0_PINMUX 0 | |
69 | # define CONFIG_SYS_FEC1_PINMUX 0 | |
70 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
71 | # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
8ae158cd TL |
72 | # define MCFFEC_TOUT_LOOP 50000 |
73 | # define CONFIG_HAS_ETH1 | |
74 | ||
75 | # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
76 | # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" | |
8ae158cd TL |
77 | # define CONFIG_ETHPRIME "FEC0" |
78 | # define CONFIG_IPADDR 192.162.1.2 | |
79 | # define CONFIG_NETMASK 255.255.255.0 | |
80 | # define CONFIG_SERVERIP 192.162.1.1 | |
81 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
8ae158cd | 82 | |
6d0f6bcf JCPV |
83 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
84 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
8ae158cd TL |
85 | # define FECDUPLEX FULL |
86 | # define FECSPEED _100BASET | |
87 | # else | |
6d0f6bcf JCPV |
88 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
89 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
8ae158cd | 90 | # endif |
6d0f6bcf | 91 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
8ae158cd TL |
92 | #endif |
93 | ||
94 | #define CONFIG_HOSTNAME M54455EVB | |
6d0f6bcf | 95 | #ifdef CONFIG_SYS_STMICRO_BOOT |
9f751551 | 96 | /* ST Micro serial flash */ |
6d0f6bcf | 97 | #define CONFIG_SYS_LOAD_ADDR2 0x40010013 |
8ae158cd TL |
98 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
99 | "netdev=eth0\0" \ | |
5368c55d | 100 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
9f751551 TL |
101 | "loadaddr=0x40010000\0" \ |
102 | "sbfhdr=sbfhdr.bin\0" \ | |
103 | "uboot=u-boot.bin\0" \ | |
104 | "load=tftp ${loadaddr} ${sbfhdr};" \ | |
5368c55d | 105 | "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ |
8ae158cd | 106 | "upd=run load; run prog\0" \ |
09933fb0 | 107 | "prog=sf probe 0:1 1000000 3;" \ |
9f751551 TL |
108 | "sf erase 0 30000;" \ |
109 | "sf write ${loadaddr} 0 0x30000;" \ | |
8ae158cd TL |
110 | "save\0" \ |
111 | "" | |
9f751551 TL |
112 | #else |
113 | /* Atmel and Intel */ | |
6d0f6bcf JCPV |
114 | #ifdef CONFIG_SYS_ATMEL_BOOT |
115 | # define CONFIG_SYS_UBOOT_END 0x0403FFFF | |
116 | #elif defined(CONFIG_SYS_INTEL_BOOT) | |
117 | # define CONFIG_SYS_UBOOT_END 0x3FFFF | |
9f751551 TL |
118 | #endif |
119 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
120 | "netdev=eth0\0" \ | |
5368c55d | 121 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
9f751551 TL |
122 | "loadaddr=0x40010000\0" \ |
123 | "uboot=u-boot.bin\0" \ | |
124 | "load=tftp ${loadaddr} ${uboot}\0" \ | |
125 | "upd=run load; run prog\0" \ | |
5368c55d MV |
126 | "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ |
127 | " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
128 | "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ | |
129 | __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
130 | "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ | |
9f751551 TL |
131 | " ${filesize}; save\0" \ |
132 | "" | |
133 | #endif | |
8ae158cd TL |
134 | |
135 | /* ATA configuration */ | |
136 | #define CONFIG_ISO_PARTITION | |
137 | #define CONFIG_DOS_PARTITION | |
138 | #define CONFIG_IDE_RESET 1 | |
139 | #define CONFIG_IDE_PREINIT 1 | |
140 | #define CONFIG_ATAPI | |
141 | #undef CONFIG_LBA48 | |
142 | ||
6d0f6bcf JCPV |
143 | #define CONFIG_SYS_IDE_MAXBUS 1 |
144 | #define CONFIG_SYS_IDE_MAXDEVICE 2 | |
8ae158cd | 145 | |
6d0f6bcf JCPV |
146 | #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 |
147 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
8ae158cd | 148 | |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ |
150 | #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ | |
151 | #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ | |
152 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ | |
8ae158cd TL |
153 | |
154 | /* Realtime clock */ | |
155 | #define CONFIG_MCFRTC | |
156 | #undef RTC_DEBUG | |
6d0f6bcf | 157 | #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) |
8ae158cd TL |
158 | |
159 | /* Timer */ | |
160 | #define CONFIG_MCFTMR | |
161 | #undef CONFIG_MCFPIT | |
162 | ||
163 | /* I2c */ | |
00f792e0 HS |
164 | #define CONFIG_SYS_I2C |
165 | #define CONFIG_SYS_I2C_FSL | |
166 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
167 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
6af3a0ea | 168 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 |
6d0f6bcf | 169 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
8ae158cd | 170 | |
bae61eef | 171 | /* DSPI and Serial Flash */ |
ee0a8462 | 172 | #define CONFIG_CF_SPI |
bae61eef | 173 | #define CONFIG_CF_DSPI |
a7323bba | 174 | #define CONFIG_HARD_SPI |
6d0f6bcf | 175 | #define CONFIG_SYS_SBFHDR_SIZE 0x13 |
a7323bba | 176 | #ifdef CONFIG_CMD_SPI |
922cd751 TL |
177 | # define CONFIG_SPI_FLASH_STMICRO |
178 | ||
ee0a8462 TL |
179 | # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ |
180 | DSPI_CTAR_PCSSCK_1CLK | \ | |
181 | DSPI_CTAR_PASC(0) | \ | |
182 | DSPI_CTAR_PDT(0) | \ | |
183 | DSPI_CTAR_CSSCK(0) | \ | |
184 | DSPI_CTAR_ASC(0) | \ | |
185 | DSPI_CTAR_DT(1)) | |
a7323bba | 186 | #endif |
bae61eef | 187 | |
8ae158cd | 188 | /* PCI */ |
e8ee8f3a | 189 | #ifdef CONFIG_CMD_PCI |
8ae158cd | 190 | #define CONFIG_PCI 1 |
2e72ad06 | 191 | #define CONFIG_PCI_PNP 1 |
f33fca22 | 192 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
2e72ad06 | 193 | |
6d0f6bcf | 194 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 |
8ae158cd | 195 | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 |
197 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS | |
198 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 | |
8ae158cd | 199 | |
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 |
201 | #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS | |
202 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 | |
8ae158cd | 203 | |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 |
205 | #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS | |
206 | #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 | |
e8ee8f3a | 207 | #endif |
8ae158cd TL |
208 | |
209 | /* FPGA - Spartan 2 */ | |
210 | /* experiment | |
b03b25ca | 211 | #define CONFIG_FPGA |
8ae158cd | 212 | #define CONFIG_FPGA_COUNT 1 |
6d0f6bcf JCPV |
213 | #define CONFIG_SYS_FPGA_PROG_FEEDBACK |
214 | #define CONFIG_SYS_FPGA_CHECK_CTRLC | |
8ae158cd TL |
215 | */ |
216 | ||
217 | /* Input, PCI, Flexbus, and VCO */ | |
218 | #define CONFIG_EXTRA_CLOCK | |
219 | ||
9f751551 | 220 | #define CONFIG_PRAM 2048 /* 2048 KB */ |
8ae158cd | 221 | |
6d0f6bcf | 222 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
8ae158cd TL |
223 | |
224 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 225 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8ae158cd | 226 | #else |
6d0f6bcf | 227 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8ae158cd | 228 | #endif |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
230 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
231 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8ae158cd | 232 | |
6d0f6bcf | 233 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) |
8ae158cd | 234 | |
6d0f6bcf | 235 | #define CONFIG_SYS_MBAR 0xFC000000 |
8ae158cd TL |
236 | |
237 | /* | |
238 | * Low Level Configuration Settings | |
239 | * (address mappings, register initial values, etc.) | |
240 | * You should know what you are doing if you make changes here. | |
241 | */ | |
242 | ||
243 | /*----------------------------------------------------------------------- | |
244 | * Definitions for initial stack pointer and data area (in DPRAM) | |
245 | */ | |
6d0f6bcf | 246 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 247 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
6d0f6bcf | 248 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 249 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) |
6d0f6bcf | 250 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
553f0982 | 251 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) |
8ae158cd TL |
252 | |
253 | /*----------------------------------------------------------------------- | |
254 | * Start addresses for the final memory configuration | |
255 | * (Set up by the startup code) | |
6d0f6bcf | 256 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
8ae158cd | 257 | */ |
6d0f6bcf JCPV |
258 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
259 | #define CONFIG_SYS_SDRAM_BASE1 0x48000000 | |
260 | #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ | |
261 | #define CONFIG_SYS_SDRAM_CFG1 0x65311610 | |
262 | #define CONFIG_SYS_SDRAM_CFG2 0x59670000 | |
263 | #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 | |
264 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 | |
265 | #define CONFIG_SYS_SDRAM_MODE 0x00010033 | |
266 | #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA | |
267 | ||
268 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
269 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
8ae158cd | 270 | |
9f751551 | 271 | #ifdef CONFIG_CF_SBF |
09933fb0 | 272 | # define CONFIG_SERIAL_BOOT |
14d0a02a | 273 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) |
9f751551 | 274 | #else |
6d0f6bcf | 275 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
9f751551 | 276 | #endif |
6d0f6bcf JCPV |
277 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
278 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
09933fb0 JJ |
279 | |
280 | /* Reserve 256 kB for malloc() */ | |
281 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
8ae158cd TL |
282 | |
283 | /* | |
284 | * For booting Linux, the board info and command line data | |
285 | * have to be in the first 8 MB of memory, since this is | |
286 | * the maximum mapped by the Linux kernel during initialization ?? | |
287 | */ | |
288 | /* Initial Memory map for Linux */ | |
6d0f6bcf | 289 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
8ae158cd | 290 | |
9f751551 TL |
291 | /* |
292 | * Configuration for environment | |
09933fb0 JJ |
293 | * Environment is not embedded in u-boot. First time runing may have env |
294 | * crc error warning if there is no correct environment on the flash. | |
8ae158cd | 295 | */ |
9f751551 | 296 | #ifdef CONFIG_CF_SBF |
0b5099a8 | 297 | # define CONFIG_ENV_IS_IN_SPI_FLASH |
0e8d1586 | 298 | # define CONFIG_ENV_SPI_CS 1 |
9f751551 | 299 | #else |
5a1aceb0 | 300 | # define CONFIG_ENV_IS_IN_FLASH 1 |
9f751551 TL |
301 | #endif |
302 | #undef CONFIG_ENV_OVERWRITE | |
8ae158cd TL |
303 | |
304 | /*----------------------------------------------------------------------- | |
305 | * FLASH organization | |
306 | */ | |
6d0f6bcf | 307 | #ifdef CONFIG_SYS_STMICRO_BOOT |
ee0a8462 TL |
308 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
309 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE | |
0e8d1586 JCPV |
310 | # define CONFIG_ENV_OFFSET 0x30000 |
311 | # define CONFIG_ENV_SIZE 0x2000 | |
312 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
9f751551 | 313 | #endif |
6d0f6bcf JCPV |
314 | #ifdef CONFIG_SYS_ATMEL_BOOT |
315 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
316 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
317 | # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE | |
09933fb0 JJ |
318 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
319 | # define CONFIG_ENV_SIZE 0x2000 | |
320 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
9f751551 | 321 | #endif |
6d0f6bcf JCPV |
322 | #ifdef CONFIG_SYS_INTEL_BOOT |
323 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
324 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
325 | # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE | |
326 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) | |
0e8d1586 JCPV |
327 | # define CONFIG_ENV_SIZE 0x2000 |
328 | # define CONFIG_ENV_SECT_SIZE 0x20000 | |
8ae158cd TL |
329 | #endif |
330 | ||
6d0f6bcf JCPV |
331 | #define CONFIG_SYS_FLASH_CFI |
332 | #ifdef CONFIG_SYS_FLASH_CFI | |
8ae158cd | 333 | |
00b1883a | 334 | # define CONFIG_FLASH_CFI_DRIVER 1 |
bbf6bbff | 335 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
6d0f6bcf JCPV |
336 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
337 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
338 | # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
339 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
340 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
341 | # define CONFIG_SYS_FLASH_CHECKSUM | |
342 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } | |
b2d022d1 | 343 | # define CONFIG_FLASH_CFI_LEGACY |
8ae158cd | 344 | |
b2d022d1 | 345 | #ifdef CONFIG_FLASH_CFI_LEGACY |
6d0f6bcf JCPV |
346 | # define CONFIG_SYS_ATMEL_REGION 4 |
347 | # define CONFIG_SYS_ATMEL_TOTALSECT 11 | |
348 | # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} | |
349 | # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} | |
bae61eef | 350 | #endif |
8ae158cd TL |
351 | #endif |
352 | ||
353 | /* | |
354 | * This is setting for JFFS2 support in u-boot. | |
355 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
356 | */ | |
9f751551 TL |
357 | #ifdef CONFIG_CMD_JFFS2 |
358 | #ifdef CF_STMICRO_BOOT | |
359 | # define CONFIG_JFFS2_DEV "nor1" | |
360 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 | |
6d0f6bcf | 361 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) |
9f751551 | 362 | #endif |
6d0f6bcf | 363 | #ifdef CONFIG_SYS_ATMEL_BOOT |
e8ee8f3a | 364 | # define CONFIG_JFFS2_DEV "nor1" |
8ae158cd | 365 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 |
6d0f6bcf | 366 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) |
9f751551 | 367 | #endif |
6d0f6bcf | 368 | #ifdef CONFIG_SYS_INTEL_BOOT |
8ae158cd TL |
369 | # define CONFIG_JFFS2_DEV "nor0" |
370 | # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) | |
6d0f6bcf | 371 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) |
8ae158cd | 372 | #endif |
9f751551 | 373 | #endif |
8ae158cd TL |
374 | |
375 | /*----------------------------------------------------------------------- | |
376 | * Cache Configuration | |
377 | */ | |
6d0f6bcf | 378 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
8ae158cd | 379 | |
dd9f054e | 380 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 381 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 382 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 383 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
384 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) |
385 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) | |
386 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ | |
387 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
388 | CF_ACR_EN | CF_ACR_SM_ALL) | |
389 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ | |
390 | CF_CACR_ICINVA | CF_CACR_EUSP) | |
391 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ | |
392 | CF_CACR_DEC | CF_CACR_DDCM_P | \ | |
393 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) | |
394 | ||
8ae158cd TL |
395 | /*----------------------------------------------------------------------- |
396 | * Memory bank definitions | |
397 | */ | |
398 | /* | |
399 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
400 | * CS1 - CompactFlash and registers | |
401 | * CS2 - CPLD | |
402 | * CS3 - FPGA | |
403 | * CS4 - Available | |
404 | * CS5 - Available | |
405 | */ | |
406 | ||
6d0f6bcf | 407 | #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) |
8ae158cd | 408 | /* Atmel Flash */ |
6d0f6bcf JCPV |
409 | #define CONFIG_SYS_CS0_BASE 0x04000000 |
410 | #define CONFIG_SYS_CS0_MASK 0x00070001 | |
411 | #define CONFIG_SYS_CS0_CTRL 0x00001140 | |
8ae158cd | 412 | /* Intel Flash */ |
6d0f6bcf JCPV |
413 | #define CONFIG_SYS_CS1_BASE 0x00000000 |
414 | #define CONFIG_SYS_CS1_MASK 0x01FF0001 | |
415 | #define CONFIG_SYS_CS1_CTRL 0x00000D60 | |
8ae158cd | 416 | |
6d0f6bcf | 417 | #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE |
8ae158cd TL |
418 | #else |
419 | /* Intel Flash */ | |
6d0f6bcf JCPV |
420 | #define CONFIG_SYS_CS0_BASE 0x00000000 |
421 | #define CONFIG_SYS_CS0_MASK 0x01FF0001 | |
422 | #define CONFIG_SYS_CS0_CTRL 0x00000D60 | |
8ae158cd | 423 | /* Atmel Flash */ |
6d0f6bcf JCPV |
424 | #define CONFIG_SYS_CS1_BASE 0x04000000 |
425 | #define CONFIG_SYS_CS1_MASK 0x00070001 | |
426 | #define CONFIG_SYS_CS1_CTRL 0x00001140 | |
8ae158cd | 427 | |
6d0f6bcf | 428 | #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE |
8ae158cd TL |
429 | #endif |
430 | ||
431 | /* CPLD */ | |
6d0f6bcf JCPV |
432 | #define CONFIG_SYS_CS2_BASE 0x08000000 |
433 | #define CONFIG_SYS_CS2_MASK 0x00070001 | |
434 | #define CONFIG_SYS_CS2_CTRL 0x003f1140 | |
8ae158cd TL |
435 | |
436 | /* FPGA */ | |
6d0f6bcf JCPV |
437 | #define CONFIG_SYS_CS3_BASE 0x09000000 |
438 | #define CONFIG_SYS_CS3_MASK 0x00070001 | |
439 | #define CONFIG_SYS_CS3_CTRL 0x00000020 | |
8ae158cd | 440 | |
e8ee8f3a | 441 | #endif /* _M54455EVB_H */ |