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8ae158cd TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF54455 EVB board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
8ae158cd TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
e8ee8f3a TL |
14 | #ifndef _M54455EVB_H |
15 | #define _M54455EVB_H | |
8ae158cd TL |
16 | |
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
21 | #define CONFIG_MCF5445x /* define processor family */ | |
22 | #define CONFIG_M54455 /* define processor type */ | |
23 | #define CONFIG_M54455EVB /* M54455EVB board */ | |
24 | ||
1313db48 AW |
25 | #define CONFIG_DISPLAY_BOARDINFO |
26 | ||
8ae158cd | 27 | #define CONFIG_MCFUART |
6d0f6bcf | 28 | #define CONFIG_SYS_UART_PORT (0) |
8ae158cd | 29 | #define CONFIG_BAUDRATE 115200 |
8ae158cd TL |
30 | |
31 | #undef CONFIG_WATCHDOG | |
32 | ||
33 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
34 | ||
35 | /* | |
36 | * BOOTP options | |
37 | */ | |
38 | #define CONFIG_BOOTP_BOOTFILESIZE | |
39 | #define CONFIG_BOOTP_BOOTPATH | |
40 | #define CONFIG_BOOTP_GATEWAY | |
41 | #define CONFIG_BOOTP_HOSTNAME | |
42 | ||
43 | /* Command line configuration */ | |
44 | #include <config_cmd_default.h> | |
45 | ||
46 | #define CONFIG_CMD_BOOTD | |
47 | #define CONFIG_CMD_CACHE | |
48 | #define CONFIG_CMD_DATE | |
49 | #define CONFIG_CMD_DHCP | |
50 | #define CONFIG_CMD_ELF | |
51 | #define CONFIG_CMD_EXT2 | |
52 | #define CONFIG_CMD_FAT | |
53 | #define CONFIG_CMD_FLASH | |
54 | #define CONFIG_CMD_I2C | |
55 | #define CONFIG_CMD_IDE | |
56 | #define CONFIG_CMD_JFFS2 | |
57 | #define CONFIG_CMD_MEMORY | |
58 | #define CONFIG_CMD_MISC | |
59 | #define CONFIG_CMD_MII | |
60 | #define CONFIG_CMD_NET | |
e8ee8f3a | 61 | #undef CONFIG_CMD_PCI |
8ae158cd TL |
62 | #define CONFIG_CMD_PING |
63 | #define CONFIG_CMD_REGINFO | |
a7323bba | 64 | #define CONFIG_CMD_SPI |
922cd751 | 65 | #define CONFIG_CMD_SF |
8ae158cd TL |
66 | |
67 | #undef CONFIG_CMD_LOADB | |
68 | #undef CONFIG_CMD_LOADS | |
69 | ||
70 | /* Network configuration */ | |
71 | #define CONFIG_MCFFEC | |
72 | #ifdef CONFIG_MCFFEC | |
8ae158cd | 73 | # define CONFIG_MII 1 |
0f3ba7e9 | 74 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
75 | # define CONFIG_SYS_DISCOVER_PHY |
76 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
77 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
78 | ||
79 | # define CONFIG_SYS_FEC0_PINMUX 0 | |
80 | # define CONFIG_SYS_FEC1_PINMUX 0 | |
81 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
82 | # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
8ae158cd TL |
83 | # define MCFFEC_TOUT_LOOP 50000 |
84 | # define CONFIG_HAS_ETH1 | |
85 | ||
86 | # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
87 | # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" | |
88 | # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 | |
89 | # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 | |
90 | # define CONFIG_ETHPRIME "FEC0" | |
91 | # define CONFIG_IPADDR 192.162.1.2 | |
92 | # define CONFIG_NETMASK 255.255.255.0 | |
93 | # define CONFIG_SERVERIP 192.162.1.1 | |
94 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
95 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
96 | ||
6d0f6bcf JCPV |
97 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
98 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
8ae158cd TL |
99 | # define FECDUPLEX FULL |
100 | # define FECSPEED _100BASET | |
101 | # else | |
6d0f6bcf JCPV |
102 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
103 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
8ae158cd | 104 | # endif |
6d0f6bcf | 105 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
8ae158cd TL |
106 | #endif |
107 | ||
108 | #define CONFIG_HOSTNAME M54455EVB | |
6d0f6bcf | 109 | #ifdef CONFIG_SYS_STMICRO_BOOT |
9f751551 | 110 | /* ST Micro serial flash */ |
6d0f6bcf | 111 | #define CONFIG_SYS_LOAD_ADDR2 0x40010013 |
8ae158cd TL |
112 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
113 | "netdev=eth0\0" \ | |
5368c55d | 114 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
9f751551 TL |
115 | "loadaddr=0x40010000\0" \ |
116 | "sbfhdr=sbfhdr.bin\0" \ | |
117 | "uboot=u-boot.bin\0" \ | |
118 | "load=tftp ${loadaddr} ${sbfhdr};" \ | |
5368c55d | 119 | "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ |
8ae158cd | 120 | "upd=run load; run prog\0" \ |
09933fb0 | 121 | "prog=sf probe 0:1 1000000 3;" \ |
9f751551 TL |
122 | "sf erase 0 30000;" \ |
123 | "sf write ${loadaddr} 0 0x30000;" \ | |
8ae158cd TL |
124 | "save\0" \ |
125 | "" | |
9f751551 TL |
126 | #else |
127 | /* Atmel and Intel */ | |
6d0f6bcf JCPV |
128 | #ifdef CONFIG_SYS_ATMEL_BOOT |
129 | # define CONFIG_SYS_UBOOT_END 0x0403FFFF | |
130 | #elif defined(CONFIG_SYS_INTEL_BOOT) | |
131 | # define CONFIG_SYS_UBOOT_END 0x3FFFF | |
9f751551 TL |
132 | #endif |
133 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
134 | "netdev=eth0\0" \ | |
5368c55d | 135 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
9f751551 TL |
136 | "loadaddr=0x40010000\0" \ |
137 | "uboot=u-boot.bin\0" \ | |
138 | "load=tftp ${loadaddr} ${uboot}\0" \ | |
139 | "upd=run load; run prog\0" \ | |
5368c55d MV |
140 | "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ |
141 | " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
142 | "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ | |
143 | __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
144 | "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ | |
9f751551 TL |
145 | " ${filesize}; save\0" \ |
146 | "" | |
147 | #endif | |
8ae158cd TL |
148 | |
149 | /* ATA configuration */ | |
150 | #define CONFIG_ISO_PARTITION | |
151 | #define CONFIG_DOS_PARTITION | |
152 | #define CONFIG_IDE_RESET 1 | |
153 | #define CONFIG_IDE_PREINIT 1 | |
154 | #define CONFIG_ATAPI | |
155 | #undef CONFIG_LBA48 | |
156 | ||
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_IDE_MAXBUS 1 |
158 | #define CONFIG_SYS_IDE_MAXDEVICE 2 | |
8ae158cd | 159 | |
6d0f6bcf JCPV |
160 | #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 |
161 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
8ae158cd | 162 | |
6d0f6bcf JCPV |
163 | #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ |
164 | #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ | |
165 | #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ | |
166 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ | |
8ae158cd TL |
167 | |
168 | /* Realtime clock */ | |
169 | #define CONFIG_MCFRTC | |
170 | #undef RTC_DEBUG | |
6d0f6bcf | 171 | #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) |
8ae158cd TL |
172 | |
173 | /* Timer */ | |
174 | #define CONFIG_MCFTMR | |
175 | #undef CONFIG_MCFPIT | |
176 | ||
177 | /* I2c */ | |
00f792e0 HS |
178 | #define CONFIG_SYS_I2C |
179 | #define CONFIG_SYS_I2C_FSL | |
180 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
181 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
6af3a0ea | 182 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 |
6d0f6bcf | 183 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
8ae158cd | 184 | |
bae61eef | 185 | /* DSPI and Serial Flash */ |
ee0a8462 | 186 | #define CONFIG_CF_SPI |
bae61eef | 187 | #define CONFIG_CF_DSPI |
a7323bba | 188 | #define CONFIG_HARD_SPI |
6d0f6bcf | 189 | #define CONFIG_SYS_SBFHDR_SIZE 0x13 |
a7323bba | 190 | #ifdef CONFIG_CMD_SPI |
922cd751 TL |
191 | # define CONFIG_SPI_FLASH |
192 | # define CONFIG_SPI_FLASH_STMICRO | |
193 | ||
ee0a8462 TL |
194 | # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ |
195 | DSPI_CTAR_PCSSCK_1CLK | \ | |
196 | DSPI_CTAR_PASC(0) | \ | |
197 | DSPI_CTAR_PDT(0) | \ | |
198 | DSPI_CTAR_CSSCK(0) | \ | |
199 | DSPI_CTAR_ASC(0) | \ | |
200 | DSPI_CTAR_DT(1)) | |
a7323bba | 201 | #endif |
bae61eef | 202 | |
8ae158cd | 203 | /* PCI */ |
e8ee8f3a | 204 | #ifdef CONFIG_CMD_PCI |
8ae158cd | 205 | #define CONFIG_PCI 1 |
2e72ad06 | 206 | #define CONFIG_PCI_PNP 1 |
f33fca22 | 207 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
2e72ad06 | 208 | |
6d0f6bcf | 209 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 |
8ae158cd | 210 | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 |
212 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS | |
213 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 | |
8ae158cd | 214 | |
6d0f6bcf JCPV |
215 | #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 |
216 | #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS | |
217 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 | |
8ae158cd | 218 | |
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 |
220 | #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS | |
221 | #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 | |
e8ee8f3a | 222 | #endif |
8ae158cd TL |
223 | |
224 | /* FPGA - Spartan 2 */ | |
225 | /* experiment | |
b03b25ca | 226 | #define CONFIG_FPGA |
8ae158cd | 227 | #define CONFIG_FPGA_COUNT 1 |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_FPGA_PROG_FEEDBACK |
229 | #define CONFIG_SYS_FPGA_CHECK_CTRLC | |
8ae158cd TL |
230 | */ |
231 | ||
232 | /* Input, PCI, Flexbus, and VCO */ | |
233 | #define CONFIG_EXTRA_CLOCK | |
234 | ||
9f751551 | 235 | #define CONFIG_PRAM 2048 /* 2048 KB */ |
8ae158cd | 236 | |
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_PROMPT "-> " |
238 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
8ae158cd TL |
239 | |
240 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 241 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8ae158cd | 242 | #else |
6d0f6bcf | 243 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8ae158cd | 244 | #endif |
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
246 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
247 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8ae158cd | 248 | |
6d0f6bcf | 249 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) |
8ae158cd | 250 | |
6d0f6bcf | 251 | #define CONFIG_SYS_MBAR 0xFC000000 |
8ae158cd TL |
252 | |
253 | /* | |
254 | * Low Level Configuration Settings | |
255 | * (address mappings, register initial values, etc.) | |
256 | * You should know what you are doing if you make changes here. | |
257 | */ | |
258 | ||
259 | /*----------------------------------------------------------------------- | |
260 | * Definitions for initial stack pointer and data area (in DPRAM) | |
261 | */ | |
6d0f6bcf | 262 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 263 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
6d0f6bcf | 264 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 265 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) |
6d0f6bcf | 266 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
553f0982 | 267 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) |
8ae158cd TL |
268 | |
269 | /*----------------------------------------------------------------------- | |
270 | * Start addresses for the final memory configuration | |
271 | * (Set up by the startup code) | |
6d0f6bcf | 272 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
8ae158cd | 273 | */ |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
275 | #define CONFIG_SYS_SDRAM_BASE1 0x48000000 | |
276 | #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ | |
277 | #define CONFIG_SYS_SDRAM_CFG1 0x65311610 | |
278 | #define CONFIG_SYS_SDRAM_CFG2 0x59670000 | |
279 | #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 | |
280 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 | |
281 | #define CONFIG_SYS_SDRAM_MODE 0x00010033 | |
282 | #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA | |
283 | ||
284 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
285 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
8ae158cd | 286 | |
9f751551 | 287 | #ifdef CONFIG_CF_SBF |
09933fb0 | 288 | # define CONFIG_SERIAL_BOOT |
14d0a02a | 289 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) |
9f751551 | 290 | #else |
6d0f6bcf | 291 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
9f751551 | 292 | #endif |
6d0f6bcf JCPV |
293 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
294 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
09933fb0 JJ |
295 | |
296 | /* Reserve 256 kB for malloc() */ | |
297 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
8ae158cd TL |
298 | |
299 | /* | |
300 | * For booting Linux, the board info and command line data | |
301 | * have to be in the first 8 MB of memory, since this is | |
302 | * the maximum mapped by the Linux kernel during initialization ?? | |
303 | */ | |
304 | /* Initial Memory map for Linux */ | |
6d0f6bcf | 305 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
8ae158cd | 306 | |
9f751551 TL |
307 | /* |
308 | * Configuration for environment | |
09933fb0 JJ |
309 | * Environment is not embedded in u-boot. First time runing may have env |
310 | * crc error warning if there is no correct environment on the flash. | |
8ae158cd | 311 | */ |
9f751551 | 312 | #ifdef CONFIG_CF_SBF |
0b5099a8 | 313 | # define CONFIG_ENV_IS_IN_SPI_FLASH |
0e8d1586 | 314 | # define CONFIG_ENV_SPI_CS 1 |
9f751551 | 315 | #else |
5a1aceb0 | 316 | # define CONFIG_ENV_IS_IN_FLASH 1 |
9f751551 TL |
317 | #endif |
318 | #undef CONFIG_ENV_OVERWRITE | |
8ae158cd TL |
319 | |
320 | /*----------------------------------------------------------------------- | |
321 | * FLASH organization | |
322 | */ | |
6d0f6bcf | 323 | #ifdef CONFIG_SYS_STMICRO_BOOT |
ee0a8462 TL |
324 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
325 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE | |
0e8d1586 JCPV |
326 | # define CONFIG_ENV_OFFSET 0x30000 |
327 | # define CONFIG_ENV_SIZE 0x2000 | |
328 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
9f751551 | 329 | #endif |
6d0f6bcf JCPV |
330 | #ifdef CONFIG_SYS_ATMEL_BOOT |
331 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
332 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
333 | # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE | |
09933fb0 JJ |
334 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
335 | # define CONFIG_ENV_SIZE 0x2000 | |
336 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
9f751551 | 337 | #endif |
6d0f6bcf JCPV |
338 | #ifdef CONFIG_SYS_INTEL_BOOT |
339 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
340 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
341 | # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE | |
342 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) | |
0e8d1586 JCPV |
343 | # define CONFIG_ENV_SIZE 0x2000 |
344 | # define CONFIG_ENV_SECT_SIZE 0x20000 | |
8ae158cd TL |
345 | #endif |
346 | ||
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_FLASH_CFI |
348 | #ifdef CONFIG_SYS_FLASH_CFI | |
8ae158cd | 349 | |
00b1883a | 350 | # define CONFIG_FLASH_CFI_DRIVER 1 |
bbf6bbff | 351 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
6d0f6bcf JCPV |
352 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
353 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
354 | # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
355 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
356 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
357 | # define CONFIG_SYS_FLASH_CHECKSUM | |
358 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } | |
b2d022d1 | 359 | # define CONFIG_FLASH_CFI_LEGACY |
8ae158cd | 360 | |
b2d022d1 | 361 | #ifdef CONFIG_FLASH_CFI_LEGACY |
6d0f6bcf JCPV |
362 | # define CONFIG_SYS_ATMEL_REGION 4 |
363 | # define CONFIG_SYS_ATMEL_TOTALSECT 11 | |
364 | # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} | |
365 | # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} | |
bae61eef | 366 | #endif |
8ae158cd TL |
367 | #endif |
368 | ||
369 | /* | |
370 | * This is setting for JFFS2 support in u-boot. | |
371 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
372 | */ | |
9f751551 TL |
373 | #ifdef CONFIG_CMD_JFFS2 |
374 | #ifdef CF_STMICRO_BOOT | |
375 | # define CONFIG_JFFS2_DEV "nor1" | |
376 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 | |
6d0f6bcf | 377 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) |
9f751551 | 378 | #endif |
6d0f6bcf | 379 | #ifdef CONFIG_SYS_ATMEL_BOOT |
e8ee8f3a | 380 | # define CONFIG_JFFS2_DEV "nor1" |
8ae158cd | 381 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 |
6d0f6bcf | 382 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) |
9f751551 | 383 | #endif |
6d0f6bcf | 384 | #ifdef CONFIG_SYS_INTEL_BOOT |
8ae158cd TL |
385 | # define CONFIG_JFFS2_DEV "nor0" |
386 | # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) | |
6d0f6bcf | 387 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) |
8ae158cd | 388 | #endif |
9f751551 | 389 | #endif |
8ae158cd TL |
390 | |
391 | /*----------------------------------------------------------------------- | |
392 | * Cache Configuration | |
393 | */ | |
6d0f6bcf | 394 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
8ae158cd | 395 | |
dd9f054e | 396 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 397 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 398 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 399 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
400 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) |
401 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) | |
402 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ | |
403 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
404 | CF_ACR_EN | CF_ACR_SM_ALL) | |
405 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ | |
406 | CF_CACR_ICINVA | CF_CACR_EUSP) | |
407 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ | |
408 | CF_CACR_DEC | CF_CACR_DDCM_P | \ | |
409 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) | |
410 | ||
8ae158cd TL |
411 | /*----------------------------------------------------------------------- |
412 | * Memory bank definitions | |
413 | */ | |
414 | /* | |
415 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
416 | * CS1 - CompactFlash and registers | |
417 | * CS2 - CPLD | |
418 | * CS3 - FPGA | |
419 | * CS4 - Available | |
420 | * CS5 - Available | |
421 | */ | |
422 | ||
6d0f6bcf | 423 | #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) |
8ae158cd | 424 | /* Atmel Flash */ |
6d0f6bcf JCPV |
425 | #define CONFIG_SYS_CS0_BASE 0x04000000 |
426 | #define CONFIG_SYS_CS0_MASK 0x00070001 | |
427 | #define CONFIG_SYS_CS0_CTRL 0x00001140 | |
8ae158cd | 428 | /* Intel Flash */ |
6d0f6bcf JCPV |
429 | #define CONFIG_SYS_CS1_BASE 0x00000000 |
430 | #define CONFIG_SYS_CS1_MASK 0x01FF0001 | |
431 | #define CONFIG_SYS_CS1_CTRL 0x00000D60 | |
8ae158cd | 432 | |
6d0f6bcf | 433 | #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE |
8ae158cd TL |
434 | #else |
435 | /* Intel Flash */ | |
6d0f6bcf JCPV |
436 | #define CONFIG_SYS_CS0_BASE 0x00000000 |
437 | #define CONFIG_SYS_CS0_MASK 0x01FF0001 | |
438 | #define CONFIG_SYS_CS0_CTRL 0x00000D60 | |
8ae158cd | 439 | /* Atmel Flash */ |
6d0f6bcf JCPV |
440 | #define CONFIG_SYS_CS1_BASE 0x04000000 |
441 | #define CONFIG_SYS_CS1_MASK 0x00070001 | |
442 | #define CONFIG_SYS_CS1_CTRL 0x00001140 | |
8ae158cd | 443 | |
6d0f6bcf | 444 | #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE |
8ae158cd TL |
445 | #endif |
446 | ||
447 | /* CPLD */ | |
6d0f6bcf JCPV |
448 | #define CONFIG_SYS_CS2_BASE 0x08000000 |
449 | #define CONFIG_SYS_CS2_MASK 0x00070001 | |
450 | #define CONFIG_SYS_CS2_CTRL 0x003f1140 | |
8ae158cd TL |
451 | |
452 | /* FPGA */ | |
6d0f6bcf JCPV |
453 | #define CONFIG_SYS_CS3_BASE 0x09000000 |
454 | #define CONFIG_SYS_CS3_MASK 0x00070001 | |
455 | #define CONFIG_SYS_CS3_CTRL 0x00000020 | |
8ae158cd | 456 | |
e8ee8f3a | 457 | #endif /* _M54455EVB_H */ |