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8ae158cd TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF54455 EVB board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
8ae158cd TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
e8ee8f3a TL |
14 | #ifndef _M54455EVB_H |
15 | #define _M54455EVB_H | |
8ae158cd TL |
16 | |
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
8ae158cd TL |
21 | #define CONFIG_M54455EVB /* M54455EVB board */ |
22 | ||
1313db48 AW |
23 | #define CONFIG_DISPLAY_BOARDINFO |
24 | ||
8ae158cd | 25 | #define CONFIG_MCFUART |
6d0f6bcf | 26 | #define CONFIG_SYS_UART_PORT (0) |
8ae158cd | 27 | #define CONFIG_BAUDRATE 115200 |
8ae158cd TL |
28 | |
29 | #undef CONFIG_WATCHDOG | |
30 | ||
31 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
32 | ||
33 | /* | |
34 | * BOOTP options | |
35 | */ | |
36 | #define CONFIG_BOOTP_BOOTFILESIZE | |
37 | #define CONFIG_BOOTP_BOOTPATH | |
38 | #define CONFIG_BOOTP_GATEWAY | |
39 | #define CONFIG_BOOTP_HOSTNAME | |
40 | ||
41 | /* Command line configuration */ | |
8ae158cd TL |
42 | #define CONFIG_CMD_CACHE |
43 | #define CONFIG_CMD_DATE | |
44 | #define CONFIG_CMD_DHCP | |
8ae158cd TL |
45 | #define CONFIG_CMD_EXT2 |
46 | #define CONFIG_CMD_FAT | |
8ae158cd TL |
47 | #define CONFIG_CMD_I2C |
48 | #define CONFIG_CMD_IDE | |
49 | #define CONFIG_CMD_JFFS2 | |
8ae158cd | 50 | #define CONFIG_CMD_MII |
e8ee8f3a | 51 | #undef CONFIG_CMD_PCI |
8ae158cd TL |
52 | #define CONFIG_CMD_PING |
53 | #define CONFIG_CMD_REGINFO | |
a7323bba | 54 | #define CONFIG_CMD_SPI |
922cd751 | 55 | #define CONFIG_CMD_SF |
8ae158cd | 56 | |
8ae158cd TL |
57 | |
58 | /* Network configuration */ | |
59 | #define CONFIG_MCFFEC | |
60 | #ifdef CONFIG_MCFFEC | |
8ae158cd | 61 | # define CONFIG_MII 1 |
0f3ba7e9 | 62 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
63 | # define CONFIG_SYS_DISCOVER_PHY |
64 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
65 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
66 | ||
67 | # define CONFIG_SYS_FEC0_PINMUX 0 | |
68 | # define CONFIG_SYS_FEC1_PINMUX 0 | |
69 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
70 | # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
8ae158cd TL |
71 | # define MCFFEC_TOUT_LOOP 50000 |
72 | # define CONFIG_HAS_ETH1 | |
73 | ||
74 | # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
75 | # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" | |
8ae158cd TL |
76 | # define CONFIG_ETHPRIME "FEC0" |
77 | # define CONFIG_IPADDR 192.162.1.2 | |
78 | # define CONFIG_NETMASK 255.255.255.0 | |
79 | # define CONFIG_SERVERIP 192.162.1.1 | |
80 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
8ae158cd | 81 | |
6d0f6bcf JCPV |
82 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
83 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
8ae158cd TL |
84 | # define FECDUPLEX FULL |
85 | # define FECSPEED _100BASET | |
86 | # else | |
6d0f6bcf JCPV |
87 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
88 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
8ae158cd | 89 | # endif |
6d0f6bcf | 90 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
8ae158cd TL |
91 | #endif |
92 | ||
93 | #define CONFIG_HOSTNAME M54455EVB | |
6d0f6bcf | 94 | #ifdef CONFIG_SYS_STMICRO_BOOT |
9f751551 | 95 | /* ST Micro serial flash */ |
6d0f6bcf | 96 | #define CONFIG_SYS_LOAD_ADDR2 0x40010013 |
8ae158cd TL |
97 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
98 | "netdev=eth0\0" \ | |
5368c55d | 99 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
9f751551 TL |
100 | "loadaddr=0x40010000\0" \ |
101 | "sbfhdr=sbfhdr.bin\0" \ | |
102 | "uboot=u-boot.bin\0" \ | |
103 | "load=tftp ${loadaddr} ${sbfhdr};" \ | |
5368c55d | 104 | "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ |
8ae158cd | 105 | "upd=run load; run prog\0" \ |
09933fb0 | 106 | "prog=sf probe 0:1 1000000 3;" \ |
9f751551 TL |
107 | "sf erase 0 30000;" \ |
108 | "sf write ${loadaddr} 0 0x30000;" \ | |
8ae158cd TL |
109 | "save\0" \ |
110 | "" | |
9f751551 TL |
111 | #else |
112 | /* Atmel and Intel */ | |
6d0f6bcf JCPV |
113 | #ifdef CONFIG_SYS_ATMEL_BOOT |
114 | # define CONFIG_SYS_UBOOT_END 0x0403FFFF | |
115 | #elif defined(CONFIG_SYS_INTEL_BOOT) | |
116 | # define CONFIG_SYS_UBOOT_END 0x3FFFF | |
9f751551 TL |
117 | #endif |
118 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
119 | "netdev=eth0\0" \ | |
5368c55d | 120 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
9f751551 TL |
121 | "loadaddr=0x40010000\0" \ |
122 | "uboot=u-boot.bin\0" \ | |
123 | "load=tftp ${loadaddr} ${uboot}\0" \ | |
124 | "upd=run load; run prog\0" \ | |
5368c55d MV |
125 | "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ |
126 | " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
127 | "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ | |
128 | __stringify(CONFIG_SYS_UBOOT_END) ";" \ | |
129 | "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ | |
9f751551 TL |
130 | " ${filesize}; save\0" \ |
131 | "" | |
132 | #endif | |
8ae158cd TL |
133 | |
134 | /* ATA configuration */ | |
135 | #define CONFIG_ISO_PARTITION | |
136 | #define CONFIG_DOS_PARTITION | |
137 | #define CONFIG_IDE_RESET 1 | |
138 | #define CONFIG_IDE_PREINIT 1 | |
139 | #define CONFIG_ATAPI | |
140 | #undef CONFIG_LBA48 | |
141 | ||
6d0f6bcf JCPV |
142 | #define CONFIG_SYS_IDE_MAXBUS 1 |
143 | #define CONFIG_SYS_IDE_MAXDEVICE 2 | |
8ae158cd | 144 | |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 |
146 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
8ae158cd | 147 | |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ |
149 | #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ | |
150 | #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ | |
151 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ | |
8ae158cd TL |
152 | |
153 | /* Realtime clock */ | |
154 | #define CONFIG_MCFRTC | |
155 | #undef RTC_DEBUG | |
6d0f6bcf | 156 | #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) |
8ae158cd TL |
157 | |
158 | /* Timer */ | |
159 | #define CONFIG_MCFTMR | |
160 | #undef CONFIG_MCFPIT | |
161 | ||
162 | /* I2c */ | |
00f792e0 HS |
163 | #define CONFIG_SYS_I2C |
164 | #define CONFIG_SYS_I2C_FSL | |
165 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
166 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
6af3a0ea | 167 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 |
6d0f6bcf | 168 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
8ae158cd | 169 | |
bae61eef | 170 | /* DSPI and Serial Flash */ |
ee0a8462 | 171 | #define CONFIG_CF_SPI |
bae61eef | 172 | #define CONFIG_CF_DSPI |
a7323bba | 173 | #define CONFIG_HARD_SPI |
6d0f6bcf | 174 | #define CONFIG_SYS_SBFHDR_SIZE 0x13 |
a7323bba | 175 | #ifdef CONFIG_CMD_SPI |
922cd751 | 176 | |
ee0a8462 TL |
177 | # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ |
178 | DSPI_CTAR_PCSSCK_1CLK | \ | |
179 | DSPI_CTAR_PASC(0) | \ | |
180 | DSPI_CTAR_PDT(0) | \ | |
181 | DSPI_CTAR_CSSCK(0) | \ | |
182 | DSPI_CTAR_ASC(0) | \ | |
183 | DSPI_CTAR_DT(1)) | |
a7323bba | 184 | #endif |
bae61eef | 185 | |
8ae158cd | 186 | /* PCI */ |
e8ee8f3a | 187 | #ifdef CONFIG_CMD_PCI |
8ae158cd | 188 | #define CONFIG_PCI 1 |
2e72ad06 | 189 | #define CONFIG_PCI_PNP 1 |
f33fca22 | 190 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
2e72ad06 | 191 | |
6d0f6bcf | 192 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 |
8ae158cd | 193 | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 |
195 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS | |
196 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 | |
8ae158cd | 197 | |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 |
199 | #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS | |
200 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 | |
8ae158cd | 201 | |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 |
203 | #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS | |
204 | #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 | |
e8ee8f3a | 205 | #endif |
8ae158cd TL |
206 | |
207 | /* FPGA - Spartan 2 */ | |
208 | /* experiment | |
b03b25ca | 209 | #define CONFIG_FPGA |
8ae158cd | 210 | #define CONFIG_FPGA_COUNT 1 |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_FPGA_PROG_FEEDBACK |
212 | #define CONFIG_SYS_FPGA_CHECK_CTRLC | |
8ae158cd TL |
213 | */ |
214 | ||
215 | /* Input, PCI, Flexbus, and VCO */ | |
216 | #define CONFIG_EXTRA_CLOCK | |
217 | ||
9f751551 | 218 | #define CONFIG_PRAM 2048 /* 2048 KB */ |
8ae158cd | 219 | |
6d0f6bcf | 220 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
8ae158cd TL |
221 | |
222 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 223 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8ae158cd | 224 | #else |
6d0f6bcf | 225 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8ae158cd | 226 | #endif |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
228 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
229 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8ae158cd | 230 | |
6d0f6bcf | 231 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) |
8ae158cd | 232 | |
6d0f6bcf | 233 | #define CONFIG_SYS_MBAR 0xFC000000 |
8ae158cd TL |
234 | |
235 | /* | |
236 | * Low Level Configuration Settings | |
237 | * (address mappings, register initial values, etc.) | |
238 | * You should know what you are doing if you make changes here. | |
239 | */ | |
240 | ||
241 | /*----------------------------------------------------------------------- | |
242 | * Definitions for initial stack pointer and data area (in DPRAM) | |
243 | */ | |
6d0f6bcf | 244 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 245 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
6d0f6bcf | 246 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 247 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) |
6d0f6bcf | 248 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
553f0982 | 249 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) |
8ae158cd TL |
250 | |
251 | /*----------------------------------------------------------------------- | |
252 | * Start addresses for the final memory configuration | |
253 | * (Set up by the startup code) | |
6d0f6bcf | 254 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
8ae158cd | 255 | */ |
6d0f6bcf JCPV |
256 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
257 | #define CONFIG_SYS_SDRAM_BASE1 0x48000000 | |
258 | #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ | |
259 | #define CONFIG_SYS_SDRAM_CFG1 0x65311610 | |
260 | #define CONFIG_SYS_SDRAM_CFG2 0x59670000 | |
261 | #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 | |
262 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 | |
263 | #define CONFIG_SYS_SDRAM_MODE 0x00010033 | |
264 | #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA | |
265 | ||
266 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
267 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
8ae158cd | 268 | |
9f751551 | 269 | #ifdef CONFIG_CF_SBF |
09933fb0 | 270 | # define CONFIG_SERIAL_BOOT |
14d0a02a | 271 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) |
9f751551 | 272 | #else |
6d0f6bcf | 273 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
9f751551 | 274 | #endif |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
276 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
09933fb0 JJ |
277 | |
278 | /* Reserve 256 kB for malloc() */ | |
279 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
8ae158cd TL |
280 | |
281 | /* | |
282 | * For booting Linux, the board info and command line data | |
283 | * have to be in the first 8 MB of memory, since this is | |
284 | * the maximum mapped by the Linux kernel during initialization ?? | |
285 | */ | |
286 | /* Initial Memory map for Linux */ | |
6d0f6bcf | 287 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
8ae158cd | 288 | |
9f751551 TL |
289 | /* |
290 | * Configuration for environment | |
09933fb0 JJ |
291 | * Environment is not embedded in u-boot. First time runing may have env |
292 | * crc error warning if there is no correct environment on the flash. | |
8ae158cd | 293 | */ |
9f751551 | 294 | #ifdef CONFIG_CF_SBF |
0b5099a8 | 295 | # define CONFIG_ENV_IS_IN_SPI_FLASH |
0e8d1586 | 296 | # define CONFIG_ENV_SPI_CS 1 |
9f751551 | 297 | #else |
5a1aceb0 | 298 | # define CONFIG_ENV_IS_IN_FLASH 1 |
9f751551 TL |
299 | #endif |
300 | #undef CONFIG_ENV_OVERWRITE | |
8ae158cd TL |
301 | |
302 | /*----------------------------------------------------------------------- | |
303 | * FLASH organization | |
304 | */ | |
6d0f6bcf | 305 | #ifdef CONFIG_SYS_STMICRO_BOOT |
ee0a8462 TL |
306 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
307 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE | |
0e8d1586 JCPV |
308 | # define CONFIG_ENV_OFFSET 0x30000 |
309 | # define CONFIG_ENV_SIZE 0x2000 | |
310 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
9f751551 | 311 | #endif |
6d0f6bcf JCPV |
312 | #ifdef CONFIG_SYS_ATMEL_BOOT |
313 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
314 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
315 | # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE | |
09933fb0 JJ |
316 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
317 | # define CONFIG_ENV_SIZE 0x2000 | |
318 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
9f751551 | 319 | #endif |
6d0f6bcf JCPV |
320 | #ifdef CONFIG_SYS_INTEL_BOOT |
321 | # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
322 | # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE | |
323 | # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE | |
324 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) | |
0e8d1586 JCPV |
325 | # define CONFIG_ENV_SIZE 0x2000 |
326 | # define CONFIG_ENV_SECT_SIZE 0x20000 | |
8ae158cd TL |
327 | #endif |
328 | ||
6d0f6bcf JCPV |
329 | #define CONFIG_SYS_FLASH_CFI |
330 | #ifdef CONFIG_SYS_FLASH_CFI | |
8ae158cd | 331 | |
00b1883a | 332 | # define CONFIG_FLASH_CFI_DRIVER 1 |
bbf6bbff | 333 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
6d0f6bcf JCPV |
334 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
335 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
336 | # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
337 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
338 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
339 | # define CONFIG_SYS_FLASH_CHECKSUM | |
340 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } | |
b2d022d1 | 341 | # define CONFIG_FLASH_CFI_LEGACY |
8ae158cd | 342 | |
b2d022d1 | 343 | #ifdef CONFIG_FLASH_CFI_LEGACY |
6d0f6bcf JCPV |
344 | # define CONFIG_SYS_ATMEL_REGION 4 |
345 | # define CONFIG_SYS_ATMEL_TOTALSECT 11 | |
346 | # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} | |
347 | # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} | |
bae61eef | 348 | #endif |
8ae158cd TL |
349 | #endif |
350 | ||
351 | /* | |
352 | * This is setting for JFFS2 support in u-boot. | |
353 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
354 | */ | |
9f751551 TL |
355 | #ifdef CONFIG_CMD_JFFS2 |
356 | #ifdef CF_STMICRO_BOOT | |
357 | # define CONFIG_JFFS2_DEV "nor1" | |
358 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 | |
6d0f6bcf | 359 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) |
9f751551 | 360 | #endif |
6d0f6bcf | 361 | #ifdef CONFIG_SYS_ATMEL_BOOT |
e8ee8f3a | 362 | # define CONFIG_JFFS2_DEV "nor1" |
8ae158cd | 363 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 |
6d0f6bcf | 364 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) |
9f751551 | 365 | #endif |
6d0f6bcf | 366 | #ifdef CONFIG_SYS_INTEL_BOOT |
8ae158cd TL |
367 | # define CONFIG_JFFS2_DEV "nor0" |
368 | # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) | |
6d0f6bcf | 369 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) |
8ae158cd | 370 | #endif |
9f751551 | 371 | #endif |
8ae158cd TL |
372 | |
373 | /*----------------------------------------------------------------------- | |
374 | * Cache Configuration | |
375 | */ | |
6d0f6bcf | 376 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
8ae158cd | 377 | |
dd9f054e | 378 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 379 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 380 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 381 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
382 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) |
383 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) | |
384 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ | |
385 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
386 | CF_ACR_EN | CF_ACR_SM_ALL) | |
387 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ | |
388 | CF_CACR_ICINVA | CF_CACR_EUSP) | |
389 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ | |
390 | CF_CACR_DEC | CF_CACR_DDCM_P | \ | |
391 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) | |
392 | ||
8ae158cd TL |
393 | /*----------------------------------------------------------------------- |
394 | * Memory bank definitions | |
395 | */ | |
396 | /* | |
397 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
398 | * CS1 - CompactFlash and registers | |
399 | * CS2 - CPLD | |
400 | * CS3 - FPGA | |
401 | * CS4 - Available | |
402 | * CS5 - Available | |
403 | */ | |
404 | ||
6d0f6bcf | 405 | #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) |
8ae158cd | 406 | /* Atmel Flash */ |
6d0f6bcf JCPV |
407 | #define CONFIG_SYS_CS0_BASE 0x04000000 |
408 | #define CONFIG_SYS_CS0_MASK 0x00070001 | |
409 | #define CONFIG_SYS_CS0_CTRL 0x00001140 | |
8ae158cd | 410 | /* Intel Flash */ |
6d0f6bcf JCPV |
411 | #define CONFIG_SYS_CS1_BASE 0x00000000 |
412 | #define CONFIG_SYS_CS1_MASK 0x01FF0001 | |
413 | #define CONFIG_SYS_CS1_CTRL 0x00000D60 | |
8ae158cd | 414 | |
6d0f6bcf | 415 | #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE |
8ae158cd TL |
416 | #else |
417 | /* Intel Flash */ | |
6d0f6bcf JCPV |
418 | #define CONFIG_SYS_CS0_BASE 0x00000000 |
419 | #define CONFIG_SYS_CS0_MASK 0x01FF0001 | |
420 | #define CONFIG_SYS_CS0_CTRL 0x00000D60 | |
8ae158cd | 421 | /* Atmel Flash */ |
6d0f6bcf JCPV |
422 | #define CONFIG_SYS_CS1_BASE 0x04000000 |
423 | #define CONFIG_SYS_CS1_MASK 0x00070001 | |
424 | #define CONFIG_SYS_CS1_CTRL 0x00001140 | |
8ae158cd | 425 | |
6d0f6bcf | 426 | #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE |
8ae158cd TL |
427 | #endif |
428 | ||
429 | /* CPLD */ | |
6d0f6bcf JCPV |
430 | #define CONFIG_SYS_CS2_BASE 0x08000000 |
431 | #define CONFIG_SYS_CS2_MASK 0x00070001 | |
432 | #define CONFIG_SYS_CS2_CTRL 0x003f1140 | |
8ae158cd TL |
433 | |
434 | /* FPGA */ | |
6d0f6bcf JCPV |
435 | #define CONFIG_SYS_CS3_BASE 0x09000000 |
436 | #define CONFIG_SYS_CS3_MASK 0x00070001 | |
437 | #define CONFIG_SYS_CS3_CTRL 0x00000020 | |
8ae158cd | 438 | |
e8ee8f3a | 439 | #endif /* _M54455EVB_H */ |