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24c3aca3 DL |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation; either version 2 of | |
7 | * the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
ae0b05df | 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
24c3aca3 DL |
12 | * GNU General Public License for more details. |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | * MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #ifndef __CONFIG_H | |
21 | #define __CONFIG_H | |
22 | ||
24c3aca3 DL |
23 | /* |
24 | * High Level Configuration Options | |
25 | */ | |
26 | #define CONFIG_E300 1 /* E300 family */ | |
27 | #define CONFIG_QE 1 /* Has QE */ | |
0f898604 | 28 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
2c7920af | 29 | #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ |
24c3aca3 | 30 | #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ |
2ae18241 WD |
31 | |
32 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 | |
24c3aca3 DL |
33 | |
34 | /* | |
35 | * System Clock Setup | |
36 | */ | |
37 | #ifdef CONFIG_PCISLAVE | |
38 | #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ | |
39 | #else | |
40 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
41 | #endif | |
42 | ||
43 | #ifndef CONFIG_SYS_CLK_FREQ | |
44 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
45 | #endif | |
46 | ||
47 | /* | |
48 | * Hardware Reset Configuration Word | |
49 | */ | |
6d0f6bcf | 50 | #define CONFIG_SYS_HRCW_LOW (\ |
24c3aca3 DL |
51 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
52 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
53 | HRCWL_VCO_1X2 |\ | |
54 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
55 | HRCWL_CORE_TO_CSB_2X1 |\ | |
56 | HRCWL_CE_PLL_VCO_DIV_2 |\ | |
57 | HRCWL_CE_PLL_DIV_1X1 |\ | |
58 | HRCWL_CE_TO_PLL_1X3) | |
59 | ||
60 | #ifdef CONFIG_PCISLAVE | |
6d0f6bcf | 61 | #define CONFIG_SYS_HRCW_HIGH (\ |
24c3aca3 DL |
62 | HRCWH_PCI_AGENT |\ |
63 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
64 | HRCWH_CORE_ENABLE |\ | |
65 | HRCWH_FROM_0XFFF00100 |\ | |
66 | HRCWH_BOOTSEQ_DISABLE |\ | |
67 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
68 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
69 | HRCWH_BIG_ENDIAN |\ | |
70 | HRCWH_LALE_NORMAL) | |
71 | #else | |
6d0f6bcf | 72 | #define CONFIG_SYS_HRCW_HIGH (\ |
24c3aca3 DL |
73 | HRCWH_PCI_HOST |\ |
74 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
75 | HRCWH_CORE_ENABLE |\ | |
76 | HRCWH_FROM_0X00000100 |\ | |
77 | HRCWH_BOOTSEQ_DISABLE |\ | |
78 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
79 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
80 | HRCWH_BIG_ENDIAN |\ | |
81 | HRCWH_LALE_NORMAL) | |
82 | #endif | |
83 | ||
84 | /* | |
85 | * System IO Config | |
86 | */ | |
6d0f6bcf | 87 | #define CONFIG_SYS_SICRL 0x00000000 |
24c3aca3 DL |
88 | |
89 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
14778585 | 90 | #define CONFIG_BOARD_EARLY_INIT_R |
24c3aca3 DL |
91 | |
92 | /* | |
93 | * IMMR new address | |
94 | */ | |
6d0f6bcf | 95 | #define CONFIG_SYS_IMMR 0xE0000000 |
24c3aca3 DL |
96 | |
97 | /* | |
98 | * DDR Setup | |
99 | */ | |
989091ac JH |
100 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
101 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
6d0f6bcf | 102 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
989091ac | 103 | #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ |
24c3aca3 DL |
104 | |
105 | #undef CONFIG_SPD_EEPROM | |
106 | #if defined(CONFIG_SPD_EEPROM) | |
107 | /* Determine DDR configuration from I2C interface | |
108 | */ | |
109 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ | |
110 | #else | |
111 | /* Manually set up DDR parameters | |
112 | */ | |
6d0f6bcf | 113 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
2fef4020 JH |
114 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
115 | | CSCONFIG_AP \ | |
116 | | CSCONFIG_ODT_WR_CFG \ | |
117 | | CSCONFIG_ROW_BIT_13 \ | |
118 | | CSCONFIG_COL_BIT_10) | |
119 | /* 0x80840102 */ | |
120 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | |
121 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
122 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
123 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
124 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
125 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
126 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
127 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
128 | /* 0x00220802 */ | |
129 | #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ | |
130 | | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
131 | | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
132 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
133 | | (13 << TIMING_CFG1_REFREC_SHIFT) \ | |
134 | | (3 << TIMING_CFG1_WRREC_SHIFT) \ | |
135 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
136 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
137 | /* 0x3935D322 */ | |
138 | #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ | |
139 | | (31 << TIMING_CFG2_CPO_SHIFT) \ | |
140 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
141 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
142 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
143 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
144 | | (10 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
145 | /* 0x0F9048CA */ | |
989091ac | 146 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
2fef4020 JH |
147 | #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
148 | /* 0x02000000 */ | |
149 | #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ | |
150 | | (0x0232 << SDRAM_MODE_SD_SHIFT)) | |
151 | /* 0x44400232 */ | |
6d0f6bcf | 152 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 |
2fef4020 JH |
153 | #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
154 | | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
155 | /* 0x03200064 */ | |
989091ac | 156 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 |
2fef4020 JH |
157 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
158 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | |
159 | | SDRAM_CFG_32_BE) | |
160 | /* 0x43080000 */ | |
6d0f6bcf | 161 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 |
24c3aca3 DL |
162 | #endif |
163 | ||
164 | /* | |
165 | * Memory test | |
166 | */ | |
6d0f6bcf JCPV |
167 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
168 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ | |
169 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
24c3aca3 DL |
170 | |
171 | /* | |
172 | * The reserved memory | |
173 | */ | |
14d0a02a | 174 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
24c3aca3 | 175 | |
6d0f6bcf JCPV |
176 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
177 | #define CONFIG_SYS_RAMBOOT | |
24c3aca3 | 178 | #else |
6d0f6bcf | 179 | #undef CONFIG_SYS_RAMBOOT |
24c3aca3 DL |
180 | #endif |
181 | ||
6d0f6bcf | 182 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
989091ac JH |
183 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
184 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
24c3aca3 DL |
185 | |
186 | /* | |
187 | * Initial RAM Base Address Setup | |
188 | */ | |
6d0f6bcf | 189 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
989091ac JH |
190 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */ |
191 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ | |
192 | #define CONFIG_SYS_GBL_DATA_OFFSET \ | |
193 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
24c3aca3 DL |
194 | |
195 | /* | |
196 | * Local Bus Configuration & Clock Setup | |
197 | */ | |
c7190f02 KP |
198 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
199 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 | |
6d0f6bcf | 200 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
24c3aca3 DL |
201 | |
202 | /* | |
203 | * FLASH on the Local Bus | |
204 | */ | |
6d0f6bcf | 205 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
989091ac JH |
206 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
207 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ | |
208 | #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ | |
209 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
24c3aca3 | 210 | |
989091ac JH |
211 | /* Window base at flash base */ |
212 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 213 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
24c3aca3 | 214 | |
989091ac | 215 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
216 | | BR_PS_16 /* 16 bit port */ \ |
217 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
218 | | BR_V) /* valid */ | |
219 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
220 | | OR_GPCM_XAM \ | |
221 | | OR_GPCM_CSNT \ | |
222 | | OR_GPCM_ACS_DIV2 \ | |
223 | | OR_GPCM_XACS \ | |
224 | | OR_GPCM_SCY_15 \ | |
225 | | OR_GPCM_TRLX_SET \ | |
226 | | OR_GPCM_EHTR_SET \ | |
227 | | OR_GPCM_EAD) | |
228 | /* 0xfe006ff7 */ | |
24c3aca3 | 229 | |
989091ac JH |
230 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
231 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
24c3aca3 | 232 | |
6d0f6bcf | 233 | #undef CONFIG_SYS_FLASH_CHECKSUM |
24c3aca3 DL |
234 | |
235 | /* | |
236 | * BCSR on the Local Bus | |
237 | */ | |
989091ac JH |
238 | #define CONFIG_SYS_BCSR 0xF8000000 |
239 | /* Access window base at BCSR base */ | |
240 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR | |
7d6a0982 JH |
241 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
242 | ||
243 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | |
244 | | BR_PS_8 \ | |
245 | | BR_MS_GPCM \ | |
246 | | BR_V) | |
247 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | |
248 | | OR_GPCM_XAM \ | |
249 | | OR_GPCM_CSNT \ | |
250 | | OR_GPCM_XACS \ | |
251 | | OR_GPCM_SCY_15 \ | |
252 | | OR_GPCM_TRLX_SET \ | |
253 | | OR_GPCM_EHTR_SET \ | |
254 | | OR_GPCM_EAD) | |
255 | /* 0xFFFFE9F7 */ | |
24c3aca3 DL |
256 | |
257 | /* | |
258 | * Windows to access PIB via local bus | |
259 | */ | |
7d6a0982 JH |
260 | /* PIB window base 0xF8008000 */ |
261 | #define CONFIG_SYS_PIB_BASE 0xF8008000 | |
262 | #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) | |
263 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE | |
264 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) | |
24c3aca3 DL |
265 | |
266 | /* | |
267 | * CS2 on Local Bus, to PIB | |
268 | */ | |
7d6a0982 JH |
269 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \ |
270 | | BR_PS_8 \ | |
271 | | BR_MS_GPCM \ | |
272 | | BR_V) | |
273 | /* 0xF8008801 */ | |
274 | #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ | |
275 | | OR_GPCM_XAM \ | |
276 | | OR_GPCM_CSNT \ | |
277 | | OR_GPCM_XACS \ | |
278 | | OR_GPCM_SCY_15 \ | |
279 | | OR_GPCM_TRLX_SET \ | |
280 | | OR_GPCM_EHTR_SET \ | |
281 | | OR_GPCM_EAD) | |
282 | /* 0xffffe9f7 */ | |
24c3aca3 DL |
283 | |
284 | /* | |
285 | * CS3 on Local Bus, to PIB | |
286 | */ | |
7d6a0982 JH |
287 | #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \ |
288 | CONFIG_SYS_PIB_WINDOW_SIZE) \ | |
289 | | BR_PS_8 \ | |
290 | | BR_MS_GPCM \ | |
291 | | BR_V) | |
292 | /* 0xF8010801 */ | |
293 | #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ | |
294 | | OR_GPCM_XAM \ | |
295 | | OR_GPCM_CSNT \ | |
296 | | OR_GPCM_XACS \ | |
297 | | OR_GPCM_SCY_15 \ | |
298 | | OR_GPCM_TRLX_SET \ | |
299 | | OR_GPCM_EHTR_SET \ | |
300 | | OR_GPCM_EAD) | |
301 | /* 0xffffe9f7 */ | |
24c3aca3 DL |
302 | |
303 | /* | |
304 | * Serial Port | |
305 | */ | |
306 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_NS16550 |
308 | #define CONFIG_SYS_NS16550_SERIAL | |
309 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
310 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
24c3aca3 | 311 | |
6d0f6bcf | 312 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
989091ac | 313 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
24c3aca3 | 314 | |
6d0f6bcf JCPV |
315 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
316 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
24c3aca3 | 317 | |
22d71a71 | 318 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
a059e90e | 319 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
24c3aca3 | 320 | /* Use the HUSH parser */ |
6d0f6bcf JCPV |
321 | #define CONFIG_SYS_HUSH_PARSER |
322 | #ifdef CONFIG_SYS_HUSH_PARSER | |
323 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
24c3aca3 DL |
324 | #endif |
325 | ||
326 | /* pass open firmware flat tree */ | |
35cc4e48 | 327 | #define CONFIG_OF_LIBFDT 1 |
24c3aca3 | 328 | #define CONFIG_OF_BOARD_SETUP 1 |
5b8bc606 | 329 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
24c3aca3 DL |
330 | |
331 | /* I2C */ | |
332 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
333 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
334 | #define CONFIG_FSL_I2C | |
6d0f6bcf JCPV |
335 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
336 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
337 | #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ | |
338 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
24c3aca3 DL |
339 | |
340 | /* | |
341 | * Config on-board RTC | |
342 | */ | |
343 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 344 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
24c3aca3 DL |
345 | |
346 | /* | |
347 | * General PCI | |
348 | * Addresses are mapped 1-1. | |
349 | */ | |
9993e196 KP |
350 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
351 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
352 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
353 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
354 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
355 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
356 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
357 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 | |
358 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
24c3aca3 | 359 | |
6d0f6bcf JCPV |
360 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE |
361 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
362 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
24c3aca3 DL |
363 | |
364 | ||
365 | #ifdef CONFIG_PCI | |
366 | ||
24c3aca3 | 367 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
9993e196 | 368 | #define CONFIG_83XX_PCI_STREAMING |
24c3aca3 DL |
369 | |
370 | #undef CONFIG_EEPRO100 | |
371 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 372 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
24c3aca3 DL |
373 | |
374 | #endif /* CONFIG_PCI */ | |
375 | ||
24c3aca3 DL |
376 | /* |
377 | * QE UEC ethernet configuration | |
378 | */ | |
379 | #define CONFIG_UEC_ETH | |
78b7a8ef | 380 | #define CONFIG_ETHPRIME "UEC0" |
24c3aca3 DL |
381 | |
382 | #define CONFIG_UEC_ETH1 /* ETH3 */ | |
383 | ||
384 | #ifdef CONFIG_UEC_ETH1 | |
6d0f6bcf JCPV |
385 | #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ |
386 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 | |
387 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 | |
388 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
389 | #define CONFIG_SYS_UEC1_PHY_ADDR 3 | |
865ff856 | 390 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII |
582c55a0 | 391 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 |
24c3aca3 DL |
392 | #endif |
393 | ||
394 | #define CONFIG_UEC_ETH2 /* ETH4 */ | |
395 | ||
396 | #ifdef CONFIG_UEC_ETH2 | |
6d0f6bcf JCPV |
397 | #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */ |
398 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7 | |
399 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 | |
400 | #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH | |
401 | #define CONFIG_SYS_UEC2_PHY_ADDR 4 | |
865ff856 | 402 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII |
582c55a0 | 403 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 |
24c3aca3 DL |
404 | #endif |
405 | ||
406 | /* | |
407 | * Environment | |
408 | */ | |
6d0f6bcf | 409 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 410 | #define CONFIG_ENV_IS_IN_FLASH 1 |
989091ac JH |
411 | #define CONFIG_ENV_ADDR \ |
412 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
413 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
414 | #define CONFIG_ENV_SIZE 0x2000 | |
24c3aca3 | 415 | #else |
989091ac | 416 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 417 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 418 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 419 | #define CONFIG_ENV_SIZE 0x2000 |
24c3aca3 DL |
420 | #endif |
421 | ||
422 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 423 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
24c3aca3 | 424 | |
079a136c JL |
425 | /* |
426 | * BOOTP options | |
427 | */ | |
428 | #define CONFIG_BOOTP_BOOTFILESIZE | |
429 | #define CONFIG_BOOTP_BOOTPATH | |
430 | #define CONFIG_BOOTP_GATEWAY | |
431 | #define CONFIG_BOOTP_HOSTNAME | |
432 | ||
433 | ||
8ea5499a JL |
434 | /* |
435 | * Command line configuration. | |
436 | */ | |
437 | #include <config_cmd_default.h> | |
438 | ||
439 | #define CONFIG_CMD_PING | |
440 | #define CONFIG_CMD_I2C | |
441 | #define CONFIG_CMD_ASKENV | |
442 | ||
24c3aca3 | 443 | #if defined(CONFIG_PCI) |
8ea5499a | 444 | #define CONFIG_CMD_PCI |
24c3aca3 | 445 | #endif |
8ea5499a | 446 | |
6d0f6bcf | 447 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 448 | #undef CONFIG_CMD_SAVEENV |
8ea5499a | 449 | #undef CONFIG_CMD_LOADS |
24c3aca3 DL |
450 | #endif |
451 | ||
24c3aca3 DL |
452 | |
453 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
454 | ||
455 | /* | |
456 | * Miscellaneous configurable options | |
457 | */ | |
989091ac JH |
458 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
459 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
460 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
24c3aca3 | 461 | |
8ea5499a | 462 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 463 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
24c3aca3 | 464 | #else |
6d0f6bcf | 465 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
24c3aca3 DL |
466 | #endif |
467 | ||
989091ac JH |
468 | /* Print Buffer Size */ |
469 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
470 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
471 | /* Boot Argument Buffer Size */ | |
472 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
473 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
24c3aca3 DL |
474 | |
475 | /* | |
476 | * For booting Linux, the board info and command line data | |
9f530d59 | 477 | * have to be in the first 256 MB of memory, since this is |
24c3aca3 DL |
478 | * the maximum mapped by the Linux kernel during initialization. |
479 | */ | |
989091ac JH |
480 | /* Initial Memory map for Linux */ |
481 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
24c3aca3 DL |
482 | |
483 | /* | |
484 | * Core HID Setup | |
485 | */ | |
1a2e203b KP |
486 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
487 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
488 | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 489 | #define CONFIG_SYS_HID2 HID2_HBE |
24c3aca3 | 490 | |
24c3aca3 DL |
491 | /* |
492 | * MMU Setup | |
493 | */ | |
494 | ||
31d82672 BB |
495 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
496 | ||
24c3aca3 | 497 | /* DDR: cache cacheable */ |
989091ac | 498 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 499 | | BATL_PP_RW \ |
989091ac JH |
500 | | BATL_MEMCOHERENCE) |
501 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
502 | | BATU_BL_256M \ | |
503 | | BATU_VS \ | |
504 | | BATU_VP) | |
6d0f6bcf JCPV |
505 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
506 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
24c3aca3 DL |
507 | |
508 | /* IMMRBAR & PCI IO: cache-inhibit and guarded */ | |
989091ac | 509 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ |
72cd4087 | 510 | | BATL_PP_RW \ |
989091ac JH |
511 | | BATL_CACHEINHIBIT \ |
512 | | BATL_GUARDEDSTORAGE) | |
513 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ | |
514 | | BATU_BL_4M \ | |
515 | | BATU_VS \ | |
516 | | BATU_VP) | |
6d0f6bcf JCPV |
517 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
518 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
24c3aca3 DL |
519 | |
520 | /* BCSR: cache-inhibit and guarded */ | |
989091ac | 521 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ |
72cd4087 | 522 | | BATL_PP_RW \ |
989091ac JH |
523 | | BATL_CACHEINHIBIT \ |
524 | | BATL_GUARDEDSTORAGE) | |
525 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ | |
526 | | BATU_BL_128K \ | |
527 | | BATU_VS \ | |
528 | | BATU_VP) | |
6d0f6bcf JCPV |
529 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
530 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
24c3aca3 DL |
531 | |
532 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
989091ac | 533 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 534 | | BATL_PP_RW \ |
989091ac JH |
535 | | BATL_MEMCOHERENCE) |
536 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ | |
537 | | BATU_BL_32M \ | |
538 | | BATU_VS \ | |
539 | | BATU_VP) | |
540 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 541 | | BATL_PP_RW \ |
989091ac JH |
542 | | BATL_CACHEINHIBIT \ |
543 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 544 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
24c3aca3 | 545 | |
6d0f6bcf JCPV |
546 | #define CONFIG_SYS_IBAT4L (0) |
547 | #define CONFIG_SYS_IBAT4U (0) | |
548 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
549 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
24c3aca3 DL |
550 | |
551 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 552 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
989091ac JH |
553 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ |
554 | | BATU_BL_128K \ | |
555 | | BATU_VS \ | |
556 | | BATU_VP) | |
6d0f6bcf JCPV |
557 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
558 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
24c3aca3 DL |
559 | |
560 | #ifdef CONFIG_PCI | |
561 | /* PCI MEM space: cacheable */ | |
989091ac | 562 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ |
72cd4087 | 563 | | BATL_PP_RW \ |
989091ac JH |
564 | | BATL_MEMCOHERENCE) |
565 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ | |
566 | | BATU_BL_256M \ | |
567 | | BATU_VS \ | |
568 | | BATU_VP) | |
6d0f6bcf JCPV |
569 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
570 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
24c3aca3 | 571 | /* PCI MMIO space: cache-inhibit and guarded */ |
989091ac | 572 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ |
72cd4087 | 573 | | BATL_PP_RW \ |
989091ac JH |
574 | | BATL_CACHEINHIBIT \ |
575 | | BATL_GUARDEDSTORAGE) | |
576 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ | |
577 | | BATU_BL_256M \ | |
578 | | BATU_VS \ | |
579 | | BATU_VP) | |
6d0f6bcf JCPV |
580 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
581 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
24c3aca3 | 582 | #else |
6d0f6bcf JCPV |
583 | #define CONFIG_SYS_IBAT6L (0) |
584 | #define CONFIG_SYS_IBAT6U (0) | |
585 | #define CONFIG_SYS_IBAT7L (0) | |
586 | #define CONFIG_SYS_IBAT7U (0) | |
587 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
588 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
589 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
590 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
24c3aca3 DL |
591 | #endif |
592 | ||
8ea5499a | 593 | #if defined(CONFIG_CMD_KGDB) |
24c3aca3 DL |
594 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
595 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
596 | #endif | |
597 | ||
598 | /* | |
599 | * Environment Configuration | |
9993e196 | 600 | */ #define CONFIG_ENV_OVERWRITE |
24c3aca3 DL |
601 | |
602 | #if defined(CONFIG_UEC_ETH) | |
977b5758 | 603 | #define CONFIG_HAS_ETH0 |
24c3aca3 | 604 | #define CONFIG_HAS_ETH1 |
24c3aca3 DL |
605 | #endif |
606 | ||
607 | #define CONFIG_BAUDRATE 115200 | |
608 | ||
79f516bc | 609 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
24c3aca3 | 610 | |
53677ef1 | 611 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
24c3aca3 DL |
612 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
613 | ||
614 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
989091ac JH |
615 | "netdev=eth0\0" \ |
616 | "consoledev=ttyS0\0" \ | |
617 | "ramdiskaddr=1000000\0" \ | |
618 | "ramdiskfile=ramfs.83xx\0" \ | |
619 | "fdtaddr=780000\0" \ | |
620 | "fdtfile=mpc832x_mds.dtb\0" \ | |
621 | "" | |
24c3aca3 DL |
622 | |
623 | #define CONFIG_NFSBOOTCOMMAND \ | |
989091ac JH |
624 | "setenv bootargs root=/dev/nfs rw " \ |
625 | "nfsroot=$serverip:$rootpath " \ | |
626 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
627 | "$netdev:off " \ | |
628 | "console=$consoledev,$baudrate $othbootargs;" \ | |
629 | "tftp $loadaddr $bootfile;" \ | |
630 | "tftp $fdtaddr $fdtfile;" \ | |
631 | "bootm $loadaddr - $fdtaddr" | |
24c3aca3 DL |
632 | |
633 | #define CONFIG_RAMBOOTCOMMAND \ | |
989091ac JH |
634 | "setenv bootargs root=/dev/ram rw " \ |
635 | "console=$consoledev,$baudrate $othbootargs;" \ | |
636 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
637 | "tftp $loadaddr $bootfile;" \ | |
638 | "tftp $fdtaddr $fdtfile;" \ | |
639 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
24c3aca3 DL |
640 | |
641 | ||
642 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
643 | ||
644 | #endif /* __CONFIG_H */ |