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Commit | Line | Data |
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2ad6b513 | 1 | /* |
4c2e3da8 | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. |
2ad6b513 | 3 | * |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
2ad6b513 TT |
5 | */ |
6 | ||
7 | /* | |
7a78f148 | 8 | MPC8349E-mITX and MPC8349E-mITX-GP board configuration file |
2ad6b513 TT |
9 | |
10 | Memory map: | |
11 | ||
12 | 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) | |
13 | 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) | |
14 | 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) | |
15 | 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) | |
16 | 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) | |
17 | 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) | |
7a78f148 | 18 | 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) |
2ad6b513 | 19 | 0xF001_0000-0xF001_FFFF Local bus expansion slot |
7a78f148 TT |
20 | 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) |
21 | 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory | |
22 | 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) | |
2ad6b513 TT |
23 | |
24 | I2C address list: | |
dd520bf3 WD |
25 | Align. Board |
26 | Bus Addr Part No. Description Length Location | |
2ad6b513 | 27 | ---------------------------------------------------------------- |
dd520bf3 | 28 | I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 |
2ad6b513 | 29 | |
dd520bf3 WD |
30 | I2C1 0x20 PCF8574 I2C Expander 0 U8 |
31 | I2C1 0x21 PCF8574 I2C Expander 0 U10 | |
32 | I2C1 0x38 PCF8574A I2C Expander 0 U8 | |
33 | I2C1 0x39 PCF8574A I2C Expander 0 U10 | |
34 | I2C1 0x51 (DDR) DDR EEPROM 1 U1 | |
35 | I2C1 0x68 DS1339 RTC 1 U68 | |
2ad6b513 TT |
36 | |
37 | Note that a given board has *either* a pair of 8574s or a pair of 8574As. | |
38 | */ | |
39 | ||
40 | #ifndef __CONFIG_H | |
41 | #define __CONFIG_H | |
42 | ||
14d0a02a | 43 | #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) |
6d0f6bcf | 44 | #define CONFIG_SYS_LOWBOOT |
7a78f148 | 45 | #endif |
2ad6b513 TT |
46 | |
47 | /* | |
48 | * High Level Configuration Options | |
49 | */ | |
2c7920af | 50 | #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ |
2ad6b513 TT |
51 | #define CONFIG_MPC8349 /* MPC8349 specific */ |
52 | ||
2ae18241 WD |
53 | #ifndef CONFIG_SYS_TEXT_BASE |
54 | #define CONFIG_SYS_TEXT_BASE 0xFEF00000 | |
55 | #endif | |
56 | ||
396abba2 | 57 | #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ |
7a78f148 | 58 | |
89c7784e TT |
59 | #define CONFIG_MISC_INIT_F |
60 | #define CONFIG_MISC_INIT_R | |
7a78f148 | 61 | |
89c7784e TT |
62 | /* |
63 | * On-board devices | |
64 | */ | |
2ad6b513 | 65 | |
7a78f148 | 66 | #ifdef CONFIG_MPC8349ITX |
396abba2 JH |
67 | /* The CF card interface on the back of the board */ |
68 | #define CONFIG_COMPACT_FLASH | |
89c7784e | 69 | #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ |
c9e34fe2 | 70 | #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ |
c31e1326 | 71 | #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ |
7a78f148 | 72 | #endif |
2ad6b513 | 73 | |
7a78f148 | 74 | #define CONFIG_RTC_DS1337 |
00f792e0 | 75 | #define CONFIG_SYS_I2C |
7a78f148 | 76 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ |
2ad6b513 | 77 | |
7a78f148 TT |
78 | /* |
79 | * Device configurations | |
80 | */ | |
81 | ||
82 | /* I2C */ | |
00f792e0 HS |
83 | #ifdef CONFIG_SYS_I2C |
84 | #define CONFIG_SYS_I2C_FSL | |
85 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
86 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
87 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
88 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
89 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
90 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
2ad6b513 | 91 | |
6d0f6bcf | 92 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ |
b7be63ab | 93 | #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ |
6d0f6bcf JCPV |
94 | |
95 | #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ | |
96 | #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ | |
97 | #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ | |
98 | #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ | |
99 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ | |
396abba2 JH |
100 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ |
101 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ | |
2ad6b513 | 102 | |
2ad6b513 | 103 | /* Don't probe these addresses: */ |
396abba2 | 104 | #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ |
6d0f6bcf JCPV |
105 | {1, CONFIG_SYS_I2C_8574_ADDR2}, \ |
106 | {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ | |
396abba2 | 107 | {1, CONFIG_SYS_I2C_8574A_ADDR2} } |
2ad6b513 | 108 | /* Bit definitions for the 8574[A] I2C expander */ |
396abba2 JH |
109 | /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ |
110 | #define I2C_8574_REVISION 0x03 | |
2ad6b513 TT |
111 | #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ |
112 | #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ | |
113 | #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ | |
114 | #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ | |
115 | ||
2ad6b513 TT |
116 | #endif |
117 | ||
7a78f148 TT |
118 | /* Compact Flash */ |
119 | #ifdef CONFIG_COMPACT_FLASH | |
2ad6b513 | 120 | |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_IDE_MAXBUS 1 |
122 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
2ad6b513 | 123 | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
125 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE | |
126 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 | |
127 | #define CONFIG_SYS_ATA_REG_OFFSET 0 | |
128 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 | |
129 | #define CONFIG_SYS_ATA_STRIDE 2 | |
2ad6b513 | 130 | |
396abba2 JH |
131 | /* If a CF card is not inserted, time out quickly */ |
132 | #define ATA_RESET_TIME 1 | |
2ad6b513 | 133 | |
c9e34fe2 VG |
134 | #endif |
135 | ||
136 | /* | |
137 | * SATA | |
138 | */ | |
139 | #ifdef CONFIG_SATA_SIL3114 | |
140 | ||
141 | #define CONFIG_SYS_SATA_MAX_DEVICE 4 | |
142 | #define CONFIG_LIBATA | |
143 | #define CONFIG_LBA48 | |
2ad6b513 | 144 | |
7a78f148 | 145 | #endif |
2ad6b513 | 146 | |
c31e1326 VG |
147 | #ifdef CONFIG_SYS_USB_HOST |
148 | /* | |
149 | * Support USB | |
150 | */ | |
c31e1326 VG |
151 | #define CONFIG_USB_EHCI |
152 | #define CONFIG_USB_EHCI_FSL | |
153 | ||
154 | /* Current USB implementation supports the only USB controller, | |
155 | * so we have to choose between the MPH or the DR ones */ | |
156 | #if 1 | |
157 | #define CONFIG_HAS_FSL_MPH_USB | |
158 | #else | |
159 | #define CONFIG_HAS_FSL_DR_USB | |
160 | #endif | |
161 | ||
162 | #endif | |
163 | ||
2ad6b513 | 164 | /* |
7a78f148 | 165 | * DDR Setup |
2ad6b513 | 166 | */ |
396abba2 | 167 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
169 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
170 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
396abba2 | 171 | #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_MEMTEST_END 0x2000 |
173 | ||
396abba2 JH |
174 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
175 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) | |
f64702b7 | 176 | |
b7be63ab VG |
177 | #define CONFIG_VERY_BIG_RAM |
178 | #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) | |
179 | ||
00f792e0 | 180 | #ifdef CONFIG_SYS_I2C |
7a78f148 TT |
181 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
182 | #endif | |
183 | ||
396abba2 JH |
184 | /* No SPD? Then manually set up DDR parameters */ |
185 | #ifndef CONFIG_SPD_EEPROM | |
186 | #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ | |
2e651b24 | 187 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
396abba2 JH |
188 | | CSCONFIG_ROW_BIT_13 \ |
189 | | CSCONFIG_COL_BIT_10) | |
2ad6b513 | 190 | |
6d0f6bcf JCPV |
191 | #define CONFIG_SYS_DDR_TIMING_1 0x26242321 |
192 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ | |
2ad6b513 TT |
193 | #endif |
194 | ||
7a78f148 TT |
195 | /* |
196 | *Flash on the Local Bus | |
197 | */ | |
198 | ||
396abba2 JH |
199 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
200 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
202 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
396abba2 JH |
203 | /* 127 64KB sectors + 8 8KB sectors per device */ |
204 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
206 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
207 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
7a78f148 TT |
208 | |
209 | /* The ITX has two flash chips, but the ITX-GP has only one. To support both | |
210 | boards, we say we have two, but don't display a message if we find only one. */ | |
6d0f6bcf | 211 | #define CONFIG_SYS_FLASH_QUIET_TEST |
396abba2 JH |
212 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
213 | #define CONFIG_SYS_FLASH_BANKS_LIST \ | |
214 | {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} | |
215 | #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ | |
396abba2 | 216 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
7a78f148 | 217 | |
89c7784e TT |
218 | /* Vitesse 7385 */ |
219 | ||
220 | #ifdef CONFIG_VSC7385_ENET | |
221 | ||
222 | #define CONFIG_TSEC2 | |
223 | ||
224 | /* The flash address and size of the VSC7385 firmware image */ | |
225 | #define CONFIG_VSC7385_IMAGE 0xFEFFE000 | |
226 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
227 | ||
228 | #endif | |
229 | ||
7a78f148 TT |
230 | /* |
231 | * BRx, ORx, LBLAWBARx, and LBLAWARx | |
232 | */ | |
233 | ||
234 | /* Flash */ | |
2ad6b513 | 235 | |
7d6a0982 JH |
236 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
237 | | BR_PS_16 \ | |
238 | | BR_MS_GPCM \ | |
239 | | BR_V) | |
240 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
396abba2 JH |
241 | | OR_UPM_XAM \ |
242 | | OR_GPCM_CSNT \ | |
243 | | OR_GPCM_ACS_DIV2 \ | |
244 | | OR_GPCM_XACS \ | |
245 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
246 | | OR_GPCM_TRLX_SET \ |
247 | | OR_GPCM_EHTR_SET \ | |
396abba2 | 248 | | OR_GPCM_EAD) |
6d0f6bcf | 249 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
7d6a0982 | 250 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) |
2ad6b513 | 251 | |
7a78f148 | 252 | /* Vitesse 7385 */ |
2ad6b513 | 253 | |
6d0f6bcf | 254 | #define CONFIG_SYS_VSC7385_BASE 0xF8000000 |
2ad6b513 | 255 | |
89c7784e TT |
256 | #ifdef CONFIG_VSC7385_ENET |
257 | ||
7d6a0982 JH |
258 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ |
259 | | BR_PS_8 \ | |
260 | | BR_MS_GPCM \ | |
261 | | BR_V) | |
396abba2 JH |
262 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ |
263 | | OR_GPCM_CSNT \ | |
264 | | OR_GPCM_XACS \ | |
265 | | OR_GPCM_SCY_15 \ | |
266 | | OR_GPCM_SETA \ | |
7d6a0982 JH |
267 | | OR_GPCM_TRLX_SET \ |
268 | | OR_GPCM_EHTR_SET \ | |
396abba2 | 269 | | OR_GPCM_EAD) |
2ad6b513 | 270 | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE |
272 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) | |
2ad6b513 | 273 | |
7a78f148 | 274 | #endif |
2ad6b513 | 275 | |
7a78f148 TT |
276 | /* LED */ |
277 | ||
396abba2 | 278 | #define CONFIG_SYS_LED_BASE 0xF9000000 |
7d6a0982 JH |
279 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ |
280 | | BR_PS_8 \ | |
281 | | BR_MS_GPCM \ | |
282 | | BR_V) | |
396abba2 JH |
283 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ |
284 | | OR_GPCM_CSNT \ | |
285 | | OR_GPCM_ACS_DIV2 \ | |
286 | | OR_GPCM_XACS \ | |
287 | | OR_GPCM_SCY_9 \ | |
7d6a0982 JH |
288 | | OR_GPCM_TRLX_SET \ |
289 | | OR_GPCM_EHTR_SET \ | |
396abba2 | 290 | | OR_GPCM_EAD) |
7a78f148 TT |
291 | |
292 | /* Compact Flash */ | |
2ad6b513 TT |
293 | |
294 | #ifdef CONFIG_COMPACT_FLASH | |
295 | ||
396abba2 | 296 | #define CONFIG_SYS_CF_BASE 0xF0000000 |
2ad6b513 | 297 | |
396abba2 JH |
298 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ |
299 | | BR_PS_16 \ | |
300 | | BR_MS_UPMA \ | |
301 | | BR_V) | |
302 | #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) | |
2ad6b513 | 303 | |
6d0f6bcf JCPV |
304 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE |
305 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) | |
2ad6b513 TT |
306 | |
307 | #endif | |
308 | ||
7a78f148 TT |
309 | /* |
310 | * U-Boot memory configuration | |
311 | */ | |
14d0a02a | 312 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
2ad6b513 | 313 | |
6d0f6bcf JCPV |
314 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
315 | #define CONFIG_SYS_RAMBOOT | |
2ad6b513 | 316 | #else |
6d0f6bcf | 317 | #undef CONFIG_SYS_RAMBOOT |
2ad6b513 TT |
318 | #endif |
319 | ||
6d0f6bcf | 320 | #define CONFIG_SYS_INIT_RAM_LOCK |
396abba2 JH |
321 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ |
322 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
2ad6b513 | 323 | |
396abba2 JH |
324 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
325 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 326 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
2ad6b513 | 327 | |
6d0f6bcf | 328 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
16c8c170 | 329 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
c8a90646 | 330 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
2ad6b513 TT |
331 | |
332 | /* | |
333 | * Local Bus LCRR and LBCR regs | |
334 | * LCRR: DLL bypass, Clock divider is 4 | |
335 | * External Local Bus rate is | |
336 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
337 | */ | |
c7190f02 KP |
338 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
339 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 340 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
2ad6b513 | 341 | |
396abba2 JH |
342 | /* LB sdram refresh timer, about 6us */ |
343 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
344 | /* LB refresh timer prescal, 266MHz/32*/ | |
345 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
2ad6b513 | 346 | |
2ad6b513 TT |
347 | /* |
348 | * Serial Port | |
349 | */ | |
350 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
351 | #define CONFIG_SYS_NS16550_SERIAL |
352 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
353 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
2ad6b513 | 354 | |
6d0f6bcf | 355 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
396abba2 | 356 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
7a78f148 | 357 | |
83302fb8 | 358 | #define CONSOLE ttyS0 |
7a78f148 | 359 | #define CONFIG_BAUDRATE 115200 |
2ad6b513 | 360 | |
6d0f6bcf JCPV |
361 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
362 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
2ad6b513 | 363 | |
7a78f148 TT |
364 | /* |
365 | * PCI | |
366 | */ | |
2ad6b513 | 367 | #ifdef CONFIG_PCI |
842033e6 | 368 | #define CONFIG_PCI_INDIRECT_BRIDGE |
2ad6b513 TT |
369 | |
370 | #define CONFIG_MPC83XX_PCI2 | |
371 | ||
372 | /* | |
373 | * General PCI | |
374 | * Addresses are mapped 1-1. | |
375 | */ | |
6d0f6bcf JCPV |
376 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
377 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
378 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
379 | #define CONFIG_SYS_PCI1_MMIO_BASE \ |
380 | (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) | |
6d0f6bcf JCPV |
381 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE |
382 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
383 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
384 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
385 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ | |
2ad6b513 TT |
386 | |
387 | #ifdef CONFIG_MPC83XX_PCI2 | |
396abba2 JH |
388 | #define CONFIG_SYS_PCI2_MEM_BASE \ |
389 | (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) | |
6d0f6bcf JCPV |
390 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE |
391 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
392 | #define CONFIG_SYS_PCI2_MMIO_BASE \ |
393 | (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) | |
6d0f6bcf JCPV |
394 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE |
395 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
396 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
397 | #define CONFIG_SYS_PCI2_IO_PHYS \ | |
398 | (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) | |
399 | #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ | |
2ad6b513 TT |
400 | #endif |
401 | ||
2ad6b513 TT |
402 | #ifndef CONFIG_PCI_PNP |
403 | #define PCI_ENET0_IOADDR 0x00000000 | |
6d0f6bcf | 404 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE |
2ad6b513 TT |
405 | #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ |
406 | #endif | |
407 | ||
408 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
409 | ||
410 | #endif | |
411 | ||
2ae18241 WD |
412 | #define CONFIG_PCI_66M |
413 | #ifdef CONFIG_PCI_66M | |
7a78f148 TT |
414 | #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ |
415 | #else | |
416 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ | |
417 | #endif | |
418 | ||
2ad6b513 TT |
419 | /* TSEC */ |
420 | ||
421 | #ifdef CONFIG_TSEC_ENET | |
422 | ||
2ad6b513 | 423 | #define CONFIG_MII |
659e2f67 | 424 | #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ |
2ad6b513 | 425 | |
255a3577 | 426 | #define CONFIG_TSEC1 |
2ad6b513 | 427 | |
255a3577 | 428 | #ifdef CONFIG_TSEC1 |
10327dc5 | 429 | #define CONFIG_HAS_ETH0 |
255a3577 | 430 | #define CONFIG_TSEC1_NAME "TSEC0" |
6d0f6bcf | 431 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
dd520bf3 | 432 | #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ |
2ad6b513 | 433 | #define TSEC1_PHYIDX 0 |
3a79013e | 434 | #define TSEC1_FLAGS TSEC_GIGABIT |
2ad6b513 TT |
435 | #endif |
436 | ||
255a3577 | 437 | #ifdef CONFIG_TSEC2 |
7a78f148 | 438 | #define CONFIG_HAS_ETH1 |
255a3577 | 439 | #define CONFIG_TSEC2_NAME "TSEC1" |
6d0f6bcf | 440 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
89c7784e | 441 | |
2ad6b513 TT |
442 | #define TSEC2_PHY_ADDR 4 |
443 | #define TSEC2_PHYIDX 0 | |
3a79013e | 444 | #define TSEC2_FLAGS TSEC_GIGABIT |
2ad6b513 TT |
445 | #endif |
446 | ||
447 | #define CONFIG_ETHPRIME "Freescale TSEC" | |
448 | ||
449 | #endif | |
450 | ||
2ad6b513 TT |
451 | /* |
452 | * Environment | |
453 | */ | |
7a78f148 TT |
454 | #define CONFIG_ENV_OVERWRITE |
455 | ||
6d0f6bcf | 456 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 457 | #define CONFIG_ENV_IS_IN_FLASH |
396abba2 JH |
458 | #define CONFIG_ENV_ADDR \ |
459 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 | 460 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ |
396abba2 | 461 | #define CONFIG_ENV_SIZE 0x2000 |
2ad6b513 | 462 | #else |
396abba2 | 463 | #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ |
00b1883a | 464 | #undef CONFIG_FLASH_CFI_DRIVER |
93f6d725 | 465 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
396abba2 JH |
466 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
467 | #define CONFIG_ENV_SIZE 0x2000 | |
2ad6b513 TT |
468 | #endif |
469 | ||
470 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
6d0f6bcf | 471 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
2ad6b513 | 472 | |
659e2f67 JL |
473 | /* |
474 | * BOOTP options | |
475 | */ | |
476 | #define CONFIG_BOOTP_BOOTFILESIZE | |
477 | #define CONFIG_BOOTP_BOOTPATH | |
478 | #define CONFIG_BOOTP_GATEWAY | |
479 | #define CONFIG_BOOTP_HOSTNAME | |
480 | ||
8ea5499a JL |
481 | /* |
482 | * Command line configuration. | |
483 | */ | |
8ea5499a JL |
484 | #define CONFIG_CMD_DATE |
485 | #define CONFIG_CMD_IRQ | |
8ea5499a | 486 | #define CONFIG_CMD_SDRAM |
2ad6b513 | 487 | |
c31e1326 | 488 | #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ |
396abba2 | 489 | || defined(CONFIG_USB_STORAGE) |
396abba2 | 490 | #define CONFIG_SUPPORT_VFAT |
c9e34fe2 VG |
491 | #endif |
492 | ||
2ad6b513 | 493 | #ifdef CONFIG_COMPACT_FLASH |
396abba2 | 494 | #define CONFIG_CMD_IDE |
c9e34fe2 VG |
495 | #endif |
496 | ||
497 | #ifdef CONFIG_SATA_SIL3114 | |
396abba2 | 498 | #define CONFIG_CMD_SATA |
c31e1326 VG |
499 | #endif |
500 | ||
501 | #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) | |
2ad6b513 TT |
502 | #endif |
503 | ||
504 | #ifdef CONFIG_PCI | |
396abba2 | 505 | #define CONFIG_CMD_PCI |
2ad6b513 TT |
506 | #endif |
507 | ||
2ad6b513 | 508 | /* Watchdog */ |
2ad6b513 | 509 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
2ad6b513 TT |
510 | |
511 | /* | |
512 | * Miscellaneous configurable options | |
513 | */ | |
396abba2 JH |
514 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
515 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
516 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
7a78f148 | 517 | |
6d0f6bcf | 518 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
05f91a65 | 519 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
7a78f148 | 520 | |
8ea5499a | 521 | #if defined(CONFIG_CMD_KGDB) |
396abba2 | 522 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
2ad6b513 | 523 | #else |
396abba2 | 524 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
2ad6b513 TT |
525 | #endif |
526 | ||
396abba2 JH |
527 | /* Print Buffer Size */ |
528 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
529 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
530 | /* Boot Argument Buffer Size */ | |
531 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
2ad6b513 TT |
532 | |
533 | /* | |
534 | * For booting Linux, the board info and command line data | |
9f530d59 | 535 | * have to be in the first 256 MB of memory, since this is |
2ad6b513 TT |
536 | * the maximum mapped by the Linux kernel during initialization. |
537 | */ | |
396abba2 JH |
538 | /* Initial Memory map for Linux*/ |
539 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
63865278 | 540 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
2ad6b513 | 541 | |
6d0f6bcf | 542 | #define CONFIG_SYS_HRCW_LOW (\ |
2ad6b513 TT |
543 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
544 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
545 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
546 | HRCWL_VCO_1X2 |\ | |
547 | HRCWL_CORE_TO_CSB_2X1) | |
548 | ||
6d0f6bcf JCPV |
549 | #ifdef CONFIG_SYS_LOWBOOT |
550 | #define CONFIG_SYS_HRCW_HIGH (\ | |
2ad6b513 | 551 | HRCWH_PCI_HOST |\ |
7a78f148 | 552 | HRCWH_32_BIT_PCI |\ |
2ad6b513 | 553 | HRCWH_PCI1_ARBITER_ENABLE |\ |
7a78f148 | 554 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
555 | HRCWH_CORE_ENABLE |\ |
556 | HRCWH_FROM_0X00000100 |\ | |
557 | HRCWH_BOOTSEQ_DISABLE |\ | |
558 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
559 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
560 | HRCWH_TSEC1M_IN_GMII |\ | |
396abba2 | 561 | HRCWH_TSEC2M_IN_GMII) |
2ad6b513 | 562 | #else |
6d0f6bcf | 563 | #define CONFIG_SYS_HRCW_HIGH (\ |
2ad6b513 TT |
564 | HRCWH_PCI_HOST |\ |
565 | HRCWH_32_BIT_PCI |\ | |
566 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
7a78f148 | 567 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
568 | HRCWH_CORE_ENABLE |\ |
569 | HRCWH_FROM_0XFFF00100 |\ | |
570 | HRCWH_BOOTSEQ_DISABLE |\ | |
571 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
572 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
573 | HRCWH_TSEC1M_IN_GMII |\ | |
396abba2 | 574 | HRCWH_TSEC2M_IN_GMII) |
2ad6b513 TT |
575 | #endif |
576 | ||
7a78f148 TT |
577 | /* |
578 | * System performance | |
579 | */ | |
6d0f6bcf | 580 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
396abba2 | 581 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
6d0f6bcf JCPV |
582 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
583 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
584 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
585 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
c31e1326 VG |
586 | #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ |
587 | #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ | |
2ad6b513 | 588 | |
7a78f148 TT |
589 | /* |
590 | * System IO Config | |
591 | */ | |
396abba2 JH |
592 | /* Needed for gigabit to work on TSEC 1 */ |
593 | #define CONFIG_SYS_SICRH SICRH_TSOBI1 | |
594 | /* USB DR as device + USB MPH as host */ | |
595 | #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) | |
2ad6b513 | 596 | |
1a2e203b KP |
597 | #define CONFIG_SYS_HID0_INIT 0x00000000 |
598 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE | |
2ad6b513 | 599 | |
6d0f6bcf | 600 | #define CONFIG_SYS_HID2 HID2_HBE |
31d82672 | 601 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
2ad6b513 | 602 | |
7a78f148 | 603 | /* DDR */ |
396abba2 | 604 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 605 | | BATL_PP_RW \ |
396abba2 JH |
606 | | BATL_MEMCOHERENCE) |
607 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
608 | | BATU_BL_256M \ | |
609 | | BATU_VS \ | |
610 | | BATU_VP) | |
2ad6b513 | 611 | |
7a78f148 | 612 | /* PCI */ |
2ad6b513 | 613 | #ifdef CONFIG_PCI |
396abba2 | 614 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
72cd4087 | 615 | | BATL_PP_RW \ |
396abba2 JH |
616 | | BATL_MEMCOHERENCE) |
617 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
618 | | BATU_BL_256M \ | |
619 | | BATU_VS \ | |
620 | | BATU_VP) | |
621 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 622 | | BATL_PP_RW \ |
396abba2 JH |
623 | | BATL_CACHEINHIBIT \ |
624 | | BATL_GUARDEDSTORAGE) | |
625 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
626 | | BATU_BL_256M \ | |
627 | | BATU_VS \ | |
628 | | BATU_VP) | |
2ad6b513 | 629 | #else |
6d0f6bcf JCPV |
630 | #define CONFIG_SYS_IBAT1L 0 |
631 | #define CONFIG_SYS_IBAT1U 0 | |
632 | #define CONFIG_SYS_IBAT2L 0 | |
633 | #define CONFIG_SYS_IBAT2U 0 | |
2ad6b513 TT |
634 | #endif |
635 | ||
636 | #ifdef CONFIG_MPC83XX_PCI2 | |
396abba2 | 637 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
72cd4087 | 638 | | BATL_PP_RW \ |
396abba2 JH |
639 | | BATL_MEMCOHERENCE) |
640 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | |
641 | | BATU_BL_256M \ | |
642 | | BATU_VS \ | |
643 | | BATU_VP) | |
644 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ | |
72cd4087 | 645 | | BATL_PP_RW \ |
396abba2 JH |
646 | | BATL_CACHEINHIBIT \ |
647 | | BATL_GUARDEDSTORAGE) | |
648 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ | |
649 | | BATU_BL_256M \ | |
650 | | BATU_VS \ | |
651 | | BATU_VP) | |
2ad6b513 | 652 | #else |
6d0f6bcf JCPV |
653 | #define CONFIG_SYS_IBAT3L 0 |
654 | #define CONFIG_SYS_IBAT3U 0 | |
655 | #define CONFIG_SYS_IBAT4L 0 | |
656 | #define CONFIG_SYS_IBAT4U 0 | |
2ad6b513 TT |
657 | #endif |
658 | ||
659 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
396abba2 | 660 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
72cd4087 | 661 | | BATL_PP_RW \ |
396abba2 JH |
662 | | BATL_CACHEINHIBIT \ |
663 | | BATL_GUARDEDSTORAGE) | |
664 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
665 | | BATU_BL_256M \ | |
666 | | BATU_VS \ | |
667 | | BATU_VP) | |
2ad6b513 TT |
668 | |
669 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
396abba2 | 670 | #define CONFIG_SYS_IBAT6L (0xF0000000 \ |
72cd4087 | 671 | | BATL_PP_RW \ |
396abba2 JH |
672 | | BATL_MEMCOHERENCE \ |
673 | | BATL_GUARDEDSTORAGE) | |
674 | #define CONFIG_SYS_IBAT6U (0xF0000000 \ | |
675 | | BATU_BL_256M \ | |
676 | | BATU_VS \ | |
677 | | BATU_VP) | |
6d0f6bcf JCPV |
678 | |
679 | #define CONFIG_SYS_IBAT7L 0 | |
680 | #define CONFIG_SYS_IBAT7U 0 | |
681 | ||
682 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
683 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
684 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
685 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
686 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
687 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
688 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
689 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
690 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
691 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
692 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
693 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
694 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
695 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
696 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
697 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
2ad6b513 | 698 | |
8ea5499a | 699 | #if defined(CONFIG_CMD_KGDB) |
2ad6b513 | 700 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
2ad6b513 TT |
701 | #endif |
702 | ||
2ad6b513 TT |
703 | /* |
704 | * Environment Configuration | |
705 | */ | |
706 | #define CONFIG_ENV_OVERWRITE | |
707 | ||
396abba2 | 708 | #define CONFIG_NETDEV "eth0" |
2ad6b513 | 709 | |
7a78f148 | 710 | #ifdef CONFIG_MPC8349ITX |
396abba2 | 711 | #define CONFIG_HOSTNAME "mpc8349emitx" |
7a78f148 | 712 | #else |
396abba2 | 713 | #define CONFIG_HOSTNAME "mpc8349emitxgp" |
be5e6181 TT |
714 | #endif |
715 | ||
7a78f148 | 716 | /* Default path and filenames */ |
8b3637c6 | 717 | #define CONFIG_ROOTPATH "/nfsroot/rootfs" |
b3f44c21 | 718 | #define CONFIG_BOOTFILE "uImage" |
396abba2 JH |
719 | /* U-Boot image on TFTP server */ |
720 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
2ad6b513 | 721 | |
7a78f148 | 722 | #ifdef CONFIG_MPC8349ITX |
396abba2 | 723 | #define CONFIG_FDTFILE "mpc8349emitx.dtb" |
2ad6b513 | 724 | #else |
396abba2 | 725 | #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" |
2ad6b513 TT |
726 | #endif |
727 | ||
7a78f148 | 728 | |
98883332 TT |
729 | #define CONFIG_BOOTARGS \ |
730 | "root=/dev/nfs rw" \ | |
5368c55d MV |
731 | " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ |
732 | " ip=" __stringify(CONFIG_IPADDR) ":" \ | |
733 | __stringify(CONFIG_SERVERIP) ":" \ | |
734 | __stringify(CONFIG_GATEWAYIP) ":" \ | |
735 | __stringify(CONFIG_NETMASK) ":" \ | |
396abba2 | 736 | CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ |
83302fb8 | 737 | " console=" __stringify(CONSOLE) "," __stringify(CONFIG_BAUDRATE) |
98883332 | 738 | |
dd520bf3 | 739 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
83302fb8 | 740 | "console=" __stringify(CONSOLE) "\0" \ |
396abba2 JH |
741 | "netdev=" CONFIG_NETDEV "\0" \ |
742 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
53677ef1 | 743 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
5368c55d MV |
744 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
745 | " +$filesize; " \ | |
746 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
747 | " +$filesize; " \ | |
748 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
749 | " $filesize; " \ | |
750 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
751 | " +$filesize; " \ | |
752 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
753 | " $filesize\0" \ | |
05f91a65 | 754 | "fdtaddr=780000\0" \ |
396abba2 | 755 | "fdtfile=" CONFIG_FDTFILE "\0" |
bf0b542d | 756 | |
dd520bf3 | 757 | #define CONFIG_NFSBOOTCOMMAND \ |
7a78f148 | 758 | "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ |
396abba2 | 759 | " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ |
7a78f148 TT |
760 | " console=$console,$baudrate $othbootargs; " \ |
761 | "tftp $loadaddr $bootfile;" \ | |
762 | "tftp $fdtaddr $fdtfile;" \ | |
763 | "bootm $loadaddr - $fdtaddr" | |
bf0b542d | 764 | |
dd520bf3 | 765 | #define CONFIG_RAMBOOTCOMMAND \ |
7a78f148 TT |
766 | "setenv bootargs root=/dev/ram rw" \ |
767 | " console=$console,$baudrate $othbootargs; " \ | |
768 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
769 | "tftp $loadaddr $bootfile;" \ | |
770 | "tftp $fdtaddr $fdtfile;" \ | |
771 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
2ad6b513 | 772 | |
2ad6b513 | 773 | #endif |