projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 2ad6b513 | 1 | /* |
| 4c2e3da8 | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. |
| 2ad6b513 | 3 | * |
| 3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 2ad6b513 TT |
5 | */ |
| 6 | ||
| 7 | /* | |
| 7a78f148 | 8 | MPC8349E-mITX and MPC8349E-mITX-GP board configuration file |
| 2ad6b513 TT |
9 | |
| 10 | Memory map: | |
| 11 | ||
| 12 | 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) | |
| 13 | 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) | |
| 14 | 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) | |
| 15 | 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) | |
| 16 | 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) | |
| 17 | 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) | |
| 7a78f148 | 18 | 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) |
| 2ad6b513 | 19 | 0xF001_0000-0xF001_FFFF Local bus expansion slot |
| 7a78f148 TT |
20 | 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) |
| 21 | 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory | |
| 22 | 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) | |
| 2ad6b513 TT |
23 | |
| 24 | I2C address list: | |
| dd520bf3 WD |
25 | Align. Board |
| 26 | Bus Addr Part No. Description Length Location | |
| 2ad6b513 | 27 | ---------------------------------------------------------------- |
| dd520bf3 | 28 | I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 |
| 2ad6b513 | 29 | |
| dd520bf3 WD |
30 | I2C1 0x20 PCF8574 I2C Expander 0 U8 |
| 31 | I2C1 0x21 PCF8574 I2C Expander 0 U10 | |
| 32 | I2C1 0x38 PCF8574A I2C Expander 0 U8 | |
| 33 | I2C1 0x39 PCF8574A I2C Expander 0 U10 | |
| 34 | I2C1 0x51 (DDR) DDR EEPROM 1 U1 | |
| 35 | I2C1 0x68 DS1339 RTC 1 U68 | |
| 2ad6b513 TT |
36 | |
| 37 | Note that a given board has *either* a pair of 8574s or a pair of 8574As. | |
| 38 | */ | |
| 39 | ||
| 40 | #ifndef __CONFIG_H | |
| 41 | #define __CONFIG_H | |
| 42 | ||
| 14d0a02a | 43 | #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) |
| 6d0f6bcf | 44 | #define CONFIG_SYS_LOWBOOT |
| 7a78f148 | 45 | #endif |
| 2ad6b513 TT |
46 | |
| 47 | /* | |
| 48 | * High Level Configuration Options | |
| 49 | */ | |
| 2c7920af | 50 | #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ |
| 2ad6b513 TT |
51 | #define CONFIG_MPC8349 /* MPC8349 specific */ |
| 52 | ||
| 2ae18241 WD |
53 | #ifndef CONFIG_SYS_TEXT_BASE |
| 54 | #define CONFIG_SYS_TEXT_BASE 0xFEF00000 | |
| 55 | #endif | |
| 56 | ||
| 396abba2 | 57 | #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ |
| 7a78f148 | 58 | |
| 89c7784e TT |
59 | #define CONFIG_MISC_INIT_F |
| 60 | #define CONFIG_MISC_INIT_R | |
| 7a78f148 | 61 | |
| 89c7784e TT |
62 | /* |
| 63 | * On-board devices | |
| 64 | */ | |
| 2ad6b513 | 65 | |
| 7a78f148 | 66 | #ifdef CONFIG_MPC8349ITX |
| 396abba2 JH |
67 | /* The CF card interface on the back of the board */ |
| 68 | #define CONFIG_COMPACT_FLASH | |
| 89c7784e | 69 | #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ |
| c9e34fe2 | 70 | #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ |
| c31e1326 | 71 | #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ |
| 7a78f148 | 72 | #endif |
| 2ad6b513 | 73 | |
| 7a78f148 | 74 | #define CONFIG_RTC_DS1337 |
| 00f792e0 | 75 | #define CONFIG_SYS_I2C |
| 7a78f148 | 76 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ |
| 2ad6b513 | 77 | |
| 7a78f148 TT |
78 | /* |
| 79 | * Device configurations | |
| 80 | */ | |
| 81 | ||
| 82 | /* I2C */ | |
| 00f792e0 HS |
83 | #ifdef CONFIG_SYS_I2C |
| 84 | #define CONFIG_SYS_I2C_FSL | |
| 85 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 86 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 87 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 88 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 89 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 90 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| 2ad6b513 | 91 | |
| 6d0f6bcf | 92 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ |
| b7be63ab | 93 | #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ |
| 6d0f6bcf JCPV |
94 | |
| 95 | #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ | |
| 96 | #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ | |
| 97 | #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ | |
| 98 | #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ | |
| 99 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ | |
| 396abba2 JH |
100 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ |
| 101 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ | |
| 2ad6b513 | 102 | |
| 2ad6b513 | 103 | /* Don't probe these addresses: */ |
| 396abba2 | 104 | #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ |
| 6d0f6bcf JCPV |
105 | {1, CONFIG_SYS_I2C_8574_ADDR2}, \ |
| 106 | {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ | |
| 396abba2 | 107 | {1, CONFIG_SYS_I2C_8574A_ADDR2} } |
| 2ad6b513 | 108 | /* Bit definitions for the 8574[A] I2C expander */ |
| 396abba2 JH |
109 | /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ |
| 110 | #define I2C_8574_REVISION 0x03 | |
| 2ad6b513 TT |
111 | #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ |
| 112 | #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ | |
| 113 | #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ | |
| 114 | #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ | |
| 115 | ||
| 2ad6b513 TT |
116 | #endif |
| 117 | ||
| 7a78f148 TT |
118 | /* Compact Flash */ |
| 119 | #ifdef CONFIG_COMPACT_FLASH | |
| 2ad6b513 | 120 | |
| 6d0f6bcf JCPV |
121 | #define CONFIG_SYS_IDE_MAXBUS 1 |
| 122 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
| 2ad6b513 | 123 | |
| 6d0f6bcf JCPV |
124 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
| 125 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE | |
| 126 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 | |
| 127 | #define CONFIG_SYS_ATA_REG_OFFSET 0 | |
| 128 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 | |
| 129 | #define CONFIG_SYS_ATA_STRIDE 2 | |
| 2ad6b513 | 130 | |
| 396abba2 JH |
131 | /* If a CF card is not inserted, time out quickly */ |
| 132 | #define ATA_RESET_TIME 1 | |
| 2ad6b513 | 133 | |
| c9e34fe2 VG |
134 | #endif |
| 135 | ||
| 136 | /* | |
| 137 | * SATA | |
| 138 | */ | |
| 139 | #ifdef CONFIG_SATA_SIL3114 | |
| 140 | ||
| 141 | #define CONFIG_SYS_SATA_MAX_DEVICE 4 | |
| 142 | #define CONFIG_LIBATA | |
| 143 | #define CONFIG_LBA48 | |
| 2ad6b513 | 144 | |
| 7a78f148 | 145 | #endif |
| 2ad6b513 | 146 | |
| c31e1326 VG |
147 | #ifdef CONFIG_SYS_USB_HOST |
| 148 | /* | |
| 149 | * Support USB | |
| 150 | */ | |
| c31e1326 VG |
151 | #define CONFIG_USB_EHCI_FSL |
| 152 | ||
| 153 | /* Current USB implementation supports the only USB controller, | |
| 154 | * so we have to choose between the MPH or the DR ones */ | |
| 155 | #if 1 | |
| 156 | #define CONFIG_HAS_FSL_MPH_USB | |
| 157 | #else | |
| 158 | #define CONFIG_HAS_FSL_DR_USB | |
| 159 | #endif | |
| 160 | ||
| 161 | #endif | |
| 162 | ||
| 2ad6b513 | 163 | /* |
| 7a78f148 | 164 | * DDR Setup |
| 2ad6b513 | 165 | */ |
| 396abba2 | 166 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
| 6d0f6bcf JCPV |
167 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
| 168 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 169 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
| 396abba2 | 170 | #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ |
| 6d0f6bcf JCPV |
171 | #define CONFIG_SYS_MEMTEST_END 0x2000 |
| 172 | ||
| 396abba2 JH |
173 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
| 174 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) | |
| f64702b7 | 175 | |
| b7be63ab VG |
176 | #define CONFIG_VERY_BIG_RAM |
| 177 | #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) | |
| 178 | ||
| 00f792e0 | 179 | #ifdef CONFIG_SYS_I2C |
| 7a78f148 TT |
180 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
| 181 | #endif | |
| 182 | ||
| 396abba2 JH |
183 | /* No SPD? Then manually set up DDR parameters */ |
| 184 | #ifndef CONFIG_SPD_EEPROM | |
| 185 | #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ | |
| 2e651b24 | 186 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
| 396abba2 JH |
187 | | CSCONFIG_ROW_BIT_13 \ |
| 188 | | CSCONFIG_COL_BIT_10) | |
| 2ad6b513 | 189 | |
| 6d0f6bcf JCPV |
190 | #define CONFIG_SYS_DDR_TIMING_1 0x26242321 |
| 191 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ | |
| 2ad6b513 TT |
192 | #endif |
| 193 | ||
| 7a78f148 TT |
194 | /* |
| 195 | *Flash on the Local Bus | |
| 196 | */ | |
| 197 | ||
| 396abba2 JH |
198 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
| 199 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
| 6d0f6bcf JCPV |
200 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
| 201 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 396abba2 JH |
202 | /* 127 64KB sectors + 8 8KB sectors per device */ |
| 203 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
| 6d0f6bcf JCPV |
204 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 205 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 206 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
| 7a78f148 TT |
207 | |
| 208 | /* The ITX has two flash chips, but the ITX-GP has only one. To support both | |
| 209 | boards, we say we have two, but don't display a message if we find only one. */ | |
| 6d0f6bcf | 210 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 396abba2 JH |
211 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 212 | #define CONFIG_SYS_FLASH_BANKS_LIST \ | |
| 213 | {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} | |
| 214 | #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ | |
| 396abba2 | 215 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
| 7a78f148 | 216 | |
| 89c7784e TT |
217 | /* Vitesse 7385 */ |
| 218 | ||
| 219 | #ifdef CONFIG_VSC7385_ENET | |
| 220 | ||
| 221 | #define CONFIG_TSEC2 | |
| 222 | ||
| 223 | /* The flash address and size of the VSC7385 firmware image */ | |
| 224 | #define CONFIG_VSC7385_IMAGE 0xFEFFE000 | |
| 225 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
| 226 | ||
| 227 | #endif | |
| 228 | ||
| 7a78f148 TT |
229 | /* |
| 230 | * BRx, ORx, LBLAWBARx, and LBLAWARx | |
| 231 | */ | |
| 232 | ||
| 233 | /* Flash */ | |
| 2ad6b513 | 234 | |
| 7d6a0982 JH |
235 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
| 236 | | BR_PS_16 \ | |
| 237 | | BR_MS_GPCM \ | |
| 238 | | BR_V) | |
| 239 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
| 396abba2 JH |
240 | | OR_UPM_XAM \ |
| 241 | | OR_GPCM_CSNT \ | |
| 242 | | OR_GPCM_ACS_DIV2 \ | |
| 243 | | OR_GPCM_XACS \ | |
| 244 | | OR_GPCM_SCY_15 \ | |
| 7d6a0982 JH |
245 | | OR_GPCM_TRLX_SET \ |
| 246 | | OR_GPCM_EHTR_SET \ | |
| 396abba2 | 247 | | OR_GPCM_EAD) |
| 6d0f6bcf | 248 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
| 7d6a0982 | 249 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) |
| 2ad6b513 | 250 | |
| 7a78f148 | 251 | /* Vitesse 7385 */ |
| 2ad6b513 | 252 | |
| 6d0f6bcf | 253 | #define CONFIG_SYS_VSC7385_BASE 0xF8000000 |
| 2ad6b513 | 254 | |
| 89c7784e TT |
255 | #ifdef CONFIG_VSC7385_ENET |
| 256 | ||
| 7d6a0982 JH |
257 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ |
| 258 | | BR_PS_8 \ | |
| 259 | | BR_MS_GPCM \ | |
| 260 | | BR_V) | |
| 396abba2 JH |
261 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ |
| 262 | | OR_GPCM_CSNT \ | |
| 263 | | OR_GPCM_XACS \ | |
| 264 | | OR_GPCM_SCY_15 \ | |
| 265 | | OR_GPCM_SETA \ | |
| 7d6a0982 JH |
266 | | OR_GPCM_TRLX_SET \ |
| 267 | | OR_GPCM_EHTR_SET \ | |
| 396abba2 | 268 | | OR_GPCM_EAD) |
| 2ad6b513 | 269 | |
| 6d0f6bcf JCPV |
270 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE |
| 271 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) | |
| 2ad6b513 | 272 | |
| 7a78f148 | 273 | #endif |
| 2ad6b513 | 274 | |
| 7a78f148 TT |
275 | /* LED */ |
| 276 | ||
| 396abba2 | 277 | #define CONFIG_SYS_LED_BASE 0xF9000000 |
| 7d6a0982 JH |
278 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ |
| 279 | | BR_PS_8 \ | |
| 280 | | BR_MS_GPCM \ | |
| 281 | | BR_V) | |
| 396abba2 JH |
282 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ |
| 283 | | OR_GPCM_CSNT \ | |
| 284 | | OR_GPCM_ACS_DIV2 \ | |
| 285 | | OR_GPCM_XACS \ | |
| 286 | | OR_GPCM_SCY_9 \ | |
| 7d6a0982 JH |
287 | | OR_GPCM_TRLX_SET \ |
| 288 | | OR_GPCM_EHTR_SET \ | |
| 396abba2 | 289 | | OR_GPCM_EAD) |
| 7a78f148 TT |
290 | |
| 291 | /* Compact Flash */ | |
| 2ad6b513 TT |
292 | |
| 293 | #ifdef CONFIG_COMPACT_FLASH | |
| 294 | ||
| 396abba2 | 295 | #define CONFIG_SYS_CF_BASE 0xF0000000 |
| 2ad6b513 | 296 | |
| 396abba2 JH |
297 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ |
| 298 | | BR_PS_16 \ | |
| 299 | | BR_MS_UPMA \ | |
| 300 | | BR_V) | |
| 301 | #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) | |
| 2ad6b513 | 302 | |
| 6d0f6bcf JCPV |
303 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE |
| 304 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) | |
| 2ad6b513 TT |
305 | |
| 306 | #endif | |
| 307 | ||
| 7a78f148 TT |
308 | /* |
| 309 | * U-Boot memory configuration | |
| 310 | */ | |
| 14d0a02a | 311 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 2ad6b513 | 312 | |
| 6d0f6bcf JCPV |
313 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 314 | #define CONFIG_SYS_RAMBOOT | |
| 2ad6b513 | 315 | #else |
| 6d0f6bcf | 316 | #undef CONFIG_SYS_RAMBOOT |
| 2ad6b513 TT |
317 | #endif |
| 318 | ||
| 6d0f6bcf | 319 | #define CONFIG_SYS_INIT_RAM_LOCK |
| 396abba2 JH |
320 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ |
| 321 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
| 2ad6b513 | 322 | |
| 396abba2 JH |
323 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| 324 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
| 6d0f6bcf | 325 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 2ad6b513 | 326 | |
| 6d0f6bcf | 327 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
| 16c8c170 | 328 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
| c8a90646 | 329 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
| 2ad6b513 TT |
330 | |
| 331 | /* | |
| 332 | * Local Bus LCRR and LBCR regs | |
| 333 | * LCRR: DLL bypass, Clock divider is 4 | |
| 334 | * External Local Bus rate is | |
| 335 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
| 336 | */ | |
| c7190f02 KP |
337 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
| 338 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
| 6d0f6bcf | 339 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
| 2ad6b513 | 340 | |
| 396abba2 JH |
341 | /* LB sdram refresh timer, about 6us */ |
| 342 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
| 343 | /* LB refresh timer prescal, 266MHz/32*/ | |
| 344 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
| 2ad6b513 | 345 | |
| 2ad6b513 TT |
346 | /* |
| 347 | * Serial Port | |
| 348 | */ | |
| 349 | #define CONFIG_CONS_INDEX 1 | |
| 6d0f6bcf JCPV |
350 | #define CONFIG_SYS_NS16550_SERIAL |
| 351 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 352 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 2ad6b513 | 353 | |
| 6d0f6bcf | 354 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 396abba2 | 355 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
| 7a78f148 | 356 | |
| 83302fb8 | 357 | #define CONSOLE ttyS0 |
| 2ad6b513 | 358 | |
| 6d0f6bcf JCPV |
359 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
| 360 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
| 2ad6b513 | 361 | |
| 7a78f148 TT |
362 | /* |
| 363 | * PCI | |
| 364 | */ | |
| 2ad6b513 | 365 | #ifdef CONFIG_PCI |
| 842033e6 | 366 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| 2ad6b513 TT |
367 | |
| 368 | #define CONFIG_MPC83XX_PCI2 | |
| 369 | ||
| 370 | /* | |
| 371 | * General PCI | |
| 372 | * Addresses are mapped 1-1. | |
| 373 | */ | |
| 6d0f6bcf JCPV |
374 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
| 375 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
| 376 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
| 396abba2 JH |
377 | #define CONFIG_SYS_PCI1_MMIO_BASE \ |
| 378 | (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) | |
| 6d0f6bcf JCPV |
379 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE |
| 380 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
| 396abba2 JH |
381 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
| 382 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
| 383 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ | |
| 2ad6b513 TT |
384 | |
| 385 | #ifdef CONFIG_MPC83XX_PCI2 | |
| 396abba2 JH |
386 | #define CONFIG_SYS_PCI2_MEM_BASE \ |
| 387 | (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) | |
| 6d0f6bcf JCPV |
388 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE |
| 389 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
| 396abba2 JH |
390 | #define CONFIG_SYS_PCI2_MMIO_BASE \ |
| 391 | (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) | |
| 6d0f6bcf JCPV |
392 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE |
| 393 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
| 396abba2 JH |
394 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
| 395 | #define CONFIG_SYS_PCI2_IO_PHYS \ | |
| 396 | (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) | |
| 397 | #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ | |
| 2ad6b513 TT |
398 | #endif |
| 399 | ||
| 2ad6b513 TT |
400 | #ifndef CONFIG_PCI_PNP |
| 401 | #define PCI_ENET0_IOADDR 0x00000000 | |
| 6d0f6bcf | 402 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE |
| 2ad6b513 TT |
403 | #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ |
| 404 | #endif | |
| 405 | ||
| 406 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 407 | ||
| 408 | #endif | |
| 409 | ||
| 2ae18241 WD |
410 | #define CONFIG_PCI_66M |
| 411 | #ifdef CONFIG_PCI_66M | |
| 7a78f148 TT |
412 | #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ |
| 413 | #else | |
| 414 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ | |
| 415 | #endif | |
| 416 | ||
| 2ad6b513 TT |
417 | /* TSEC */ |
| 418 | ||
| 419 | #ifdef CONFIG_TSEC_ENET | |
| 420 | ||
| 2ad6b513 | 421 | #define CONFIG_MII |
| 659e2f67 | 422 | #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ |
| 2ad6b513 | 423 | |
| 255a3577 | 424 | #define CONFIG_TSEC1 |
| 2ad6b513 | 425 | |
| 255a3577 | 426 | #ifdef CONFIG_TSEC1 |
| 10327dc5 | 427 | #define CONFIG_HAS_ETH0 |
| 255a3577 | 428 | #define CONFIG_TSEC1_NAME "TSEC0" |
| 6d0f6bcf | 429 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
| dd520bf3 | 430 | #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ |
| 2ad6b513 | 431 | #define TSEC1_PHYIDX 0 |
| 3a79013e | 432 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 2ad6b513 TT |
433 | #endif |
| 434 | ||
| 255a3577 | 435 | #ifdef CONFIG_TSEC2 |
| 7a78f148 | 436 | #define CONFIG_HAS_ETH1 |
| 255a3577 | 437 | #define CONFIG_TSEC2_NAME "TSEC1" |
| 6d0f6bcf | 438 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
| 89c7784e | 439 | |
| 2ad6b513 TT |
440 | #define TSEC2_PHY_ADDR 4 |
| 441 | #define TSEC2_PHYIDX 0 | |
| 3a79013e | 442 | #define TSEC2_FLAGS TSEC_GIGABIT |
| 2ad6b513 TT |
443 | #endif |
| 444 | ||
| 445 | #define CONFIG_ETHPRIME "Freescale TSEC" | |
| 446 | ||
| 447 | #endif | |
| 448 | ||
| 2ad6b513 TT |
449 | /* |
| 450 | * Environment | |
| 451 | */ | |
| 7a78f148 TT |
452 | #define CONFIG_ENV_OVERWRITE |
| 453 | ||
| 6d0f6bcf | 454 | #ifndef CONFIG_SYS_RAMBOOT |
| 5a1aceb0 | 455 | #define CONFIG_ENV_IS_IN_FLASH |
| 396abba2 JH |
456 | #define CONFIG_ENV_ADDR \ |
| 457 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
| 0e8d1586 | 458 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ |
| 396abba2 | 459 | #define CONFIG_ENV_SIZE 0x2000 |
| 2ad6b513 | 460 | #else |
| 00b1883a | 461 | #undef CONFIG_FLASH_CFI_DRIVER |
| 93f6d725 | 462 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
| 396abba2 JH |
463 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 464 | #define CONFIG_ENV_SIZE 0x2000 | |
| 2ad6b513 TT |
465 | #endif |
| 466 | ||
| 467 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 6d0f6bcf | 468 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
| 2ad6b513 | 469 | |
| 659e2f67 JL |
470 | /* |
| 471 | * BOOTP options | |
| 472 | */ | |
| 473 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 474 | #define CONFIG_BOOTP_BOOTPATH | |
| 475 | #define CONFIG_BOOTP_GATEWAY | |
| 476 | #define CONFIG_BOOTP_HOSTNAME | |
| 477 | ||
| 8ea5499a JL |
478 | /* |
| 479 | * Command line configuration. | |
| 480 | */ | |
| 8ea5499a | 481 | #define CONFIG_CMD_IRQ |
| 8ea5499a | 482 | #define CONFIG_CMD_SDRAM |
| 2ad6b513 | 483 | |
| c31e1326 | 484 | #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ |
| 396abba2 | 485 | || defined(CONFIG_USB_STORAGE) |
| 396abba2 | 486 | #define CONFIG_SUPPORT_VFAT |
| c9e34fe2 VG |
487 | #endif |
| 488 | ||
| c9e34fe2 | 489 | #ifdef CONFIG_SATA_SIL3114 |
| 396abba2 | 490 | #define CONFIG_CMD_SATA |
| c31e1326 VG |
491 | #endif |
| 492 | ||
| 493 | #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) | |
| 2ad6b513 TT |
494 | #endif |
| 495 | ||
| 496 | #ifdef CONFIG_PCI | |
| 396abba2 | 497 | #define CONFIG_CMD_PCI |
| 2ad6b513 TT |
498 | #endif |
| 499 | ||
| 2ad6b513 | 500 | /* Watchdog */ |
| 2ad6b513 | 501 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 2ad6b513 TT |
502 | |
| 503 | /* | |
| 504 | * Miscellaneous configurable options | |
| 505 | */ | |
| 396abba2 JH |
506 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 507 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 508 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
| 7a78f148 | 509 | |
| 6d0f6bcf | 510 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 05f91a65 | 511 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
| 7a78f148 | 512 | |
| 8ea5499a | 513 | #if defined(CONFIG_CMD_KGDB) |
| 396abba2 | 514 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 2ad6b513 | 515 | #else |
| 396abba2 | 516 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 2ad6b513 TT |
517 | #endif |
| 518 | ||
| 396abba2 JH |
519 | /* Print Buffer Size */ |
| 520 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 521 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 522 | /* Boot Argument Buffer Size */ | |
| 523 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 2ad6b513 TT |
524 | |
| 525 | /* | |
| 526 | * For booting Linux, the board info and command line data | |
| 9f530d59 | 527 | * have to be in the first 256 MB of memory, since this is |
| 2ad6b513 TT |
528 | * the maximum mapped by the Linux kernel during initialization. |
| 529 | */ | |
| 396abba2 JH |
530 | /* Initial Memory map for Linux*/ |
| 531 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
| 63865278 | 532 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 2ad6b513 | 533 | |
| 6d0f6bcf | 534 | #define CONFIG_SYS_HRCW_LOW (\ |
| 2ad6b513 TT |
535 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 536 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 537 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
| 538 | HRCWL_VCO_1X2 |\ | |
| 539 | HRCWL_CORE_TO_CSB_2X1) | |
| 540 | ||
| 6d0f6bcf JCPV |
541 | #ifdef CONFIG_SYS_LOWBOOT |
| 542 | #define CONFIG_SYS_HRCW_HIGH (\ | |
| 2ad6b513 | 543 | HRCWH_PCI_HOST |\ |
| 7a78f148 | 544 | HRCWH_32_BIT_PCI |\ |
| 2ad6b513 | 545 | HRCWH_PCI1_ARBITER_ENABLE |\ |
| 7a78f148 | 546 | HRCWH_PCI2_ARBITER_ENABLE |\ |
| 2ad6b513 TT |
547 | HRCWH_CORE_ENABLE |\ |
| 548 | HRCWH_FROM_0X00000100 |\ | |
| 549 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 550 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 551 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 552 | HRCWH_TSEC1M_IN_GMII |\ | |
| 396abba2 | 553 | HRCWH_TSEC2M_IN_GMII) |
| 2ad6b513 | 554 | #else |
| 6d0f6bcf | 555 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 2ad6b513 TT |
556 | HRCWH_PCI_HOST |\ |
| 557 | HRCWH_32_BIT_PCI |\ | |
| 558 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 7a78f148 | 559 | HRCWH_PCI2_ARBITER_ENABLE |\ |
| 2ad6b513 TT |
560 | HRCWH_CORE_ENABLE |\ |
| 561 | HRCWH_FROM_0XFFF00100 |\ | |
| 562 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 563 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 564 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 565 | HRCWH_TSEC1M_IN_GMII |\ | |
| 396abba2 | 566 | HRCWH_TSEC2M_IN_GMII) |
| 2ad6b513 TT |
567 | #endif |
| 568 | ||
| 7a78f148 TT |
569 | /* |
| 570 | * System performance | |
| 571 | */ | |
| 6d0f6bcf | 572 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
| 396abba2 | 573 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
| 6d0f6bcf JCPV |
574 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
| 575 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
| 576 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
| 577 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
| c31e1326 VG |
578 | #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ |
| 579 | #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ | |
| 2ad6b513 | 580 | |
| 7a78f148 TT |
581 | /* |
| 582 | * System IO Config | |
| 583 | */ | |
| 396abba2 JH |
584 | /* Needed for gigabit to work on TSEC 1 */ |
| 585 | #define CONFIG_SYS_SICRH SICRH_TSOBI1 | |
| 586 | /* USB DR as device + USB MPH as host */ | |
| 587 | #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) | |
| 2ad6b513 | 588 | |
| 1a2e203b KP |
589 | #define CONFIG_SYS_HID0_INIT 0x00000000 |
| 590 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE | |
| 2ad6b513 | 591 | |
| 6d0f6bcf | 592 | #define CONFIG_SYS_HID2 HID2_HBE |
| 31d82672 | 593 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 2ad6b513 | 594 | |
| 7a78f148 | 595 | /* DDR */ |
| 396abba2 | 596 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
| 72cd4087 | 597 | | BATL_PP_RW \ |
| 396abba2 JH |
598 | | BATL_MEMCOHERENCE) |
| 599 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
| 600 | | BATU_BL_256M \ | |
| 601 | | BATU_VS \ | |
| 602 | | BATU_VP) | |
| 2ad6b513 | 603 | |
| 7a78f148 | 604 | /* PCI */ |
| 2ad6b513 | 605 | #ifdef CONFIG_PCI |
| 396abba2 | 606 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
| 72cd4087 | 607 | | BATL_PP_RW \ |
| 396abba2 JH |
608 | | BATL_MEMCOHERENCE) |
| 609 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
| 610 | | BATU_BL_256M \ | |
| 611 | | BATU_VS \ | |
| 612 | | BATU_VP) | |
| 613 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
| 72cd4087 | 614 | | BATL_PP_RW \ |
| 396abba2 JH |
615 | | BATL_CACHEINHIBIT \ |
| 616 | | BATL_GUARDEDSTORAGE) | |
| 617 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
| 618 | | BATU_BL_256M \ | |
| 619 | | BATU_VS \ | |
| 620 | | BATU_VP) | |
| 2ad6b513 | 621 | #else |
| 6d0f6bcf JCPV |
622 | #define CONFIG_SYS_IBAT1L 0 |
| 623 | #define CONFIG_SYS_IBAT1U 0 | |
| 624 | #define CONFIG_SYS_IBAT2L 0 | |
| 625 | #define CONFIG_SYS_IBAT2U 0 | |
| 2ad6b513 TT |
626 | #endif |
| 627 | ||
| 628 | #ifdef CONFIG_MPC83XX_PCI2 | |
| 396abba2 | 629 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
| 72cd4087 | 630 | | BATL_PP_RW \ |
| 396abba2 JH |
631 | | BATL_MEMCOHERENCE) |
| 632 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | |
| 633 | | BATU_BL_256M \ | |
| 634 | | BATU_VS \ | |
| 635 | | BATU_VP) | |
| 636 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ | |
| 72cd4087 | 637 | | BATL_PP_RW \ |
| 396abba2 JH |
638 | | BATL_CACHEINHIBIT \ |
| 639 | | BATL_GUARDEDSTORAGE) | |
| 640 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ | |
| 641 | | BATU_BL_256M \ | |
| 642 | | BATU_VS \ | |
| 643 | | BATU_VP) | |
| 2ad6b513 | 644 | #else |
| 6d0f6bcf JCPV |
645 | #define CONFIG_SYS_IBAT3L 0 |
| 646 | #define CONFIG_SYS_IBAT3U 0 | |
| 647 | #define CONFIG_SYS_IBAT4L 0 | |
| 648 | #define CONFIG_SYS_IBAT4U 0 | |
| 2ad6b513 TT |
649 | #endif |
| 650 | ||
| 651 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
| 396abba2 | 652 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
| 72cd4087 | 653 | | BATL_PP_RW \ |
| 396abba2 JH |
654 | | BATL_CACHEINHIBIT \ |
| 655 | | BATL_GUARDEDSTORAGE) | |
| 656 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
| 657 | | BATU_BL_256M \ | |
| 658 | | BATU_VS \ | |
| 659 | | BATU_VP) | |
| 2ad6b513 TT |
660 | |
| 661 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
| 396abba2 | 662 | #define CONFIG_SYS_IBAT6L (0xF0000000 \ |
| 72cd4087 | 663 | | BATL_PP_RW \ |
| 396abba2 JH |
664 | | BATL_MEMCOHERENCE \ |
| 665 | | BATL_GUARDEDSTORAGE) | |
| 666 | #define CONFIG_SYS_IBAT6U (0xF0000000 \ | |
| 667 | | BATU_BL_256M \ | |
| 668 | | BATU_VS \ | |
| 669 | | BATU_VP) | |
| 6d0f6bcf JCPV |
670 | |
| 671 | #define CONFIG_SYS_IBAT7L 0 | |
| 672 | #define CONFIG_SYS_IBAT7U 0 | |
| 673 | ||
| 674 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
| 675 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| 676 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
| 677 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| 678 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
| 679 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
| 680 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
| 681 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| 682 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
| 683 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
| 684 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
| 685 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
| 686 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
| 687 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
| 688 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
| 689 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
| 2ad6b513 | 690 | |
| 8ea5499a | 691 | #if defined(CONFIG_CMD_KGDB) |
| 2ad6b513 | 692 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
| 2ad6b513 TT |
693 | #endif |
| 694 | ||
| 2ad6b513 TT |
695 | /* |
| 696 | * Environment Configuration | |
| 697 | */ | |
| 698 | #define CONFIG_ENV_OVERWRITE | |
| 699 | ||
| 396abba2 | 700 | #define CONFIG_NETDEV "eth0" |
| 2ad6b513 | 701 | |
| 7a78f148 | 702 | #ifdef CONFIG_MPC8349ITX |
| 396abba2 | 703 | #define CONFIG_HOSTNAME "mpc8349emitx" |
| 7a78f148 | 704 | #else |
| 396abba2 | 705 | #define CONFIG_HOSTNAME "mpc8349emitxgp" |
| be5e6181 TT |
706 | #endif |
| 707 | ||
| 7a78f148 | 708 | /* Default path and filenames */ |
| 8b3637c6 | 709 | #define CONFIG_ROOTPATH "/nfsroot/rootfs" |
| b3f44c21 | 710 | #define CONFIG_BOOTFILE "uImage" |
| 396abba2 JH |
711 | /* U-Boot image on TFTP server */ |
| 712 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
| 2ad6b513 | 713 | |
| 7a78f148 | 714 | #ifdef CONFIG_MPC8349ITX |
| 396abba2 | 715 | #define CONFIG_FDTFILE "mpc8349emitx.dtb" |
| 2ad6b513 | 716 | #else |
| 396abba2 | 717 | #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" |
| 2ad6b513 TT |
718 | #endif |
| 719 | ||
| 7a78f148 | 720 | |
| 98883332 TT |
721 | #define CONFIG_BOOTARGS \ |
| 722 | "root=/dev/nfs rw" \ | |
| 5368c55d MV |
723 | " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ |
| 724 | " ip=" __stringify(CONFIG_IPADDR) ":" \ | |
| 725 | __stringify(CONFIG_SERVERIP) ":" \ | |
| 726 | __stringify(CONFIG_GATEWAYIP) ":" \ | |
| 727 | __stringify(CONFIG_NETMASK) ":" \ | |
| 396abba2 | 728 | CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ |
| 83302fb8 | 729 | " console=" __stringify(CONSOLE) "," __stringify(CONFIG_BAUDRATE) |
| 98883332 | 730 | |
| dd520bf3 | 731 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 83302fb8 | 732 | "console=" __stringify(CONSOLE) "\0" \ |
| 396abba2 JH |
733 | "netdev=" CONFIG_NETDEV "\0" \ |
| 734 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
| 53677ef1 | 735 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 5368c55d MV |
736 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 737 | " +$filesize; " \ | |
| 738 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 739 | " +$filesize; " \ | |
| 740 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 741 | " $filesize; " \ | |
| 742 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 743 | " +$filesize; " \ | |
| 744 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 745 | " $filesize\0" \ | |
| 05f91a65 | 746 | "fdtaddr=780000\0" \ |
| 396abba2 | 747 | "fdtfile=" CONFIG_FDTFILE "\0" |
| bf0b542d | 748 | |
| dd520bf3 | 749 | #define CONFIG_NFSBOOTCOMMAND \ |
| 7a78f148 | 750 | "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ |
| 396abba2 | 751 | " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ |
| 7a78f148 TT |
752 | " console=$console,$baudrate $othbootargs; " \ |
| 753 | "tftp $loadaddr $bootfile;" \ | |
| 754 | "tftp $fdtaddr $fdtfile;" \ | |
| 755 | "bootm $loadaddr - $fdtaddr" | |
| bf0b542d | 756 | |
| dd520bf3 | 757 | #define CONFIG_RAMBOOTCOMMAND \ |
| 7a78f148 TT |
758 | "setenv bootargs root=/dev/ram rw" \ |
| 759 | " console=$console,$baudrate $othbootargs; " \ | |
| 760 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 761 | "tftp $loadaddr $bootfile;" \ | |
| 762 | "tftp $fdtaddr $fdtfile;" \ | |
| 763 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 2ad6b513 | 764 | |
| 2ad6b513 | 765 | #endif |