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Commit | Line | Data |
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fab6f556 AV |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. | |
3 | * Dave Liu <daveliu@freescale.com> | |
4 | * | |
5 | * Copyright (C) 2007 Logic Product Development, Inc. | |
6 | * Peter Barada <peterb@logicpd.com> | |
7 | * | |
8 | * Copyright (C) 2007 MontaVista Software, Inc. | |
9 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | */ | |
16 | ||
17 | #ifndef __CONFIG_H | |
18 | #define __CONFIG_H | |
19 | ||
fab6f556 AV |
20 | /* |
21 | * High Level Configuration Options | |
22 | */ | |
23 | #define CONFIG_E300 1 /* E300 family */ | |
24 | #define CONFIG_QE 1 /* Has QE */ | |
0f898604 | 25 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
fab6f556 AV |
26 | #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ |
27 | #define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */ | |
28 | ||
2ae18241 WD |
29 | #define CONFIG_SYS_TEXT_BASE 0xFF800000 |
30 | ||
fab6f556 AV |
31 | /* |
32 | * System Clock Setup | |
33 | */ | |
34 | #ifdef CONFIG_CLKIN_33MHZ | |
f700e7df AV |
35 | #define CONFIG_83XX_CLKIN 33333333 |
36 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
2ae18241 | 37 | #define CONFIG_PCI_33M 1 |
fab6f556 AV |
38 | #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1 |
39 | #else | |
40 | #define CONFIG_83XX_CLKIN 66000000 | |
41 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
2ae18241 | 42 | #define CONFIG_PCI_66M 1 |
fab6f556 AV |
43 | #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1 |
44 | #endif /* CONFIG_CLKIN_33MHZ */ | |
45 | ||
46 | /* | |
47 | * Hardware Reset Configuration Word | |
48 | */ | |
6d0f6bcf | 49 | #define CONFIG_SYS_HRCW_LOW (\ |
fab6f556 AV |
50 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
51 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
52 | HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\ | |
53 | HRCWL_CORE_TO_CSB_2X1 |\ | |
54 | HRCWL_CE_TO_PLL_1X15) | |
55 | ||
6d0f6bcf | 56 | #define CONFIG_SYS_HRCW_HIGH (\ |
fab6f556 AV |
57 | HRCWH_PCI_HOST |\ |
58 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
59 | HRCWH_PCICKDRV_ENABLE |\ | |
60 | HRCWH_CORE_ENABLE |\ | |
61 | HRCWH_FROM_0X00000100 |\ | |
62 | HRCWH_BOOTSEQ_DISABLE |\ | |
63 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
64 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
65 | HRCWH_SECONDARY_DDR_DISABLE |\ | |
66 | HRCWH_BIG_ENDIAN |\ | |
67 | HRCWH_LALE_EARLY) | |
68 | ||
69 | /* | |
70 | * System IO Config | |
71 | */ | |
6d0f6bcf JCPV |
72 | #define CONFIG_SYS_SICRH 0x00000000 |
73 | #define CONFIG_SYS_SICRL 0x40000000 | |
fab6f556 | 74 | |
fab6f556 AV |
75 | #define CONFIG_BOARD_EARLY_INIT_R |
76 | ||
77 | /* | |
78 | * IMMR new address | |
79 | */ | |
6d0f6bcf | 80 | #define CONFIG_SYS_IMMR 0xE0000000 |
fab6f556 AV |
81 | |
82 | /* | |
83 | * DDR Setup | |
84 | */ | |
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
86 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
87 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
9a986550 JH |
88 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
89 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
fab6f556 | 90 | |
6d0f6bcf | 91 | #define CONFIG_SYS_83XX_DDR_USES_CS0 |
fab6f556 | 92 | |
d892b2db AV |
93 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
94 | #define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
fab6f556 AV |
95 | |
96 | /* | |
97 | * DDRCDR - DDR Control Driver Register | |
98 | */ | |
2fef4020 JH |
99 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ |
100 | | DDRCDR_ODT \ | |
101 | | DDRCDR_Q_DRN) | |
102 | /* 0x80080001 */ | |
fab6f556 AV |
103 | |
104 | #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ | |
105 | ||
106 | /* | |
107 | * Manually set up DDR parameters | |
108 | */ | |
109 | #define CONFIG_DDR_II | |
6d0f6bcf | 110 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
2fef4020 | 111 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
9a986550 JH |
112 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
113 | | CSCONFIG_ROW_BIT_13 \ | |
114 | | CSCONFIG_COL_BIT_10 \ | |
2fef4020 | 115 | | CSCONFIG_ODT_WR_ONLY_CURRENT) |
9a986550 JH |
116 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
117 | | SDRAM_CFG_ECC_EN) | |
6d0f6bcf | 118 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 |
9a986550 JH |
119 | #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
120 | #define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \ | |
121 | | (1115 << SDRAM_INTERVAL_REFINT_SHIFT)) | |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_DDR_MODE 0x47800432 |
123 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 | |
d892b2db | 124 | |
6d0f6bcf | 125 | #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ |
d892b2db AV |
126 | (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ |
127 | (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ | |
128 | (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ | |
129 | (0 << TIMING_CFG0_WWT_SHIFT) | \ | |
130 | (0 << TIMING_CFG0_RRT_SHIFT) | \ | |
131 | (0 << TIMING_CFG0_WRT_SHIFT) | \ | |
132 | (0 << TIMING_CFG0_RWT_SHIFT)) | |
133 | ||
9a986550 JH |
134 | #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \ |
135 | (2 << TIMING_CFG1_WRTORD_SHIFT) | \ | |
136 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ | |
137 | (3 << TIMING_CFG1_WRREC_SHIFT) | \ | |
d892b2db | 138 | (10 << TIMING_CFG1_REFREC_SHIFT) | \ |
9a986550 JH |
139 | (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ |
140 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ | |
141 | (3 << TIMING_CFG1_PRETOACT_SHIFT)) | |
d892b2db | 142 | |
6d0f6bcf | 143 | #define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ |
d892b2db AV |
144 | (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \ |
145 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ | |
146 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ | |
147 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ | |
148 | (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ | |
149 | (0 << TIMING_CFG2_CPO_SHIFT)) | |
150 | ||
6d0f6bcf | 151 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
fab6f556 AV |
152 | |
153 | /* | |
154 | * Memory test | |
155 | */ | |
6d0f6bcf JCPV |
156 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
157 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ | |
158 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
fab6f556 AV |
159 | |
160 | /* | |
161 | * The reserved memory | |
162 | */ | |
14d0a02a | 163 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
6d0f6bcf | 164 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */ |
fab6f556 | 165 | |
6d0f6bcf JCPV |
166 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
167 | #define CONFIG_SYS_RAMBOOT | |
fab6f556 | 168 | #else |
6d0f6bcf | 169 | #undef CONFIG_SYS_RAMBOOT |
fab6f556 AV |
170 | #endif |
171 | ||
9a986550 | 172 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
c8a90646 | 173 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
fab6f556 AV |
174 | |
175 | /* | |
176 | * Initial RAM Base Address Setup | |
177 | */ | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
179 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 180 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
9a986550 JH |
181 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
182 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
fab6f556 AV |
183 | |
184 | /* | |
185 | * Local Bus Configuration & Clock Setup | |
186 | */ | |
c7190f02 KP |
187 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
188 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
9a986550 | 189 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
fab6f556 AV |
190 | |
191 | /* | |
192 | * FLASH on the Local Bus | |
193 | */ | |
6d0f6bcf | 194 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
9a986550 | 195 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ |
197 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */ | |
fab6f556 | 198 | |
9a986550 JH |
199 | /* Window base at flash base */ |
200 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 201 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
fab6f556 | 202 | |
9a986550 | 203 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
204 | | BR_PS_16 /* 16 bit port */ \ |
205 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
206 | | BR_V) /* valid */ | |
207 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
9a986550 JH |
208 | | OR_UPM_XAM \ |
209 | | OR_GPCM_CSNT \ | |
210 | | OR_GPCM_ACS_DIV2 \ | |
211 | | OR_GPCM_XACS \ | |
212 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
213 | | OR_GPCM_TRLX_SET \ |
214 | | OR_GPCM_EHTR_SET \ | |
9a986550 | 215 | | OR_GPCM_EAD) |
fab6f556 | 216 | |
6d0f6bcf JCPV |
217 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
218 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
fab6f556 | 219 | |
6d0f6bcf | 220 | #undef CONFIG_SYS_FLASH_CHECKSUM |
fab6f556 AV |
221 | |
222 | /* | |
223 | * NAND flash on the local bus | |
224 | */ | |
6d0f6bcf | 225 | #define CONFIG_SYS_NAND_BASE 0x60000000 |
7ad95949 AV |
226 | #define CONFIG_CMD_NAND 1 |
227 | #define CONFIG_NAND_FSL_UPM 1 | |
6d0f6bcf | 228 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
7ad95949 | 229 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
fab6f556 | 230 | |
6d0f6bcf | 231 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 JH |
232 | /* |
233 | * [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB | |
234 | * ... What's correct? | |
235 | */ | |
236 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) | |
fab6f556 AV |
237 | |
238 | /* Port size 8 bit, UPMA */ | |
7d6a0982 JH |
239 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ |
240 | | BR_PS_8 \ | |
241 | | BR_MS_UPMA \ | |
242 | | BR_V) | |
243 | /* 0x60000881 */ | |
244 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD) | |
245 | /* 0xFC000001 */ | |
fab6f556 AV |
246 | |
247 | /* | |
248 | * Fujitsu MB86277 (MINT) graphics controller | |
249 | */ | |
6d0f6bcf | 250 | #define CONFIG_SYS_VIDEO_BASE 0x70000000 |
fab6f556 | 251 | |
6d0f6bcf | 252 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE |
7d6a0982 | 253 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) |
fab6f556 AV |
254 | |
255 | /* Port size 32 bit, UPMB */ | |
7d6a0982 JH |
256 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \ |
257 | | BR_PS_32 \ | |
258 | | BR_MS_UPMB \ | |
259 | | BR_V) | |
260 | /* 0x000018a1 */ | |
261 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD) | |
262 | /* 0xFC000001 */ | |
fab6f556 AV |
263 | |
264 | /* | |
265 | * Serial Port | |
266 | */ | |
267 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
268 | #define CONFIG_SYS_NS16550 |
269 | #define CONFIG_SYS_NS16550_SERIAL | |
270 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
271 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
fab6f556 | 272 | |
6d0f6bcf | 273 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
9a986550 | 274 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
fab6f556 | 275 | |
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
277 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
fab6f556 AV |
278 | |
279 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
9a986550 | 280 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
fab6f556 | 281 | /* Use the HUSH parser */ |
6d0f6bcf | 282 | #define CONFIG_SYS_HUSH_PARSER |
fab6f556 AV |
283 | |
284 | /* Pass open firmware flat tree */ | |
285 | #define CONFIG_OF_LIBFDT 1 | |
286 | #define CONFIG_OF_BOARD_SETUP 1 | |
3a0cfdd5 | 287 | #define CONFIG_OF_STDOUT_VIA_ALIAS |
fab6f556 AV |
288 | |
289 | /* I2C */ | |
00f792e0 HS |
290 | #define CONFIG_SYS_I2C |
291 | #define CONFIG_SYS_I2C_FSL | |
292 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
293 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
294 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
295 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
296 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
297 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
298 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } | |
fab6f556 AV |
299 | |
300 | /* | |
301 | * General PCI | |
302 | * Addresses are mapped 1-1. | |
303 | */ | |
304 | #define CONFIG_PCI | |
fab6f556 | 305 | |
6d0f6bcf JCPV |
306 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
307 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
308 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
309 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
310 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
311 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
9a986550 JH |
312 | #define CONFIG_SYS_PCI1_IO_BASE 0xE0300000 |
313 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 | |
314 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
fab6f556 AV |
315 | |
316 | #ifdef CONFIG_PCI | |
842033e6 | 317 | #define CONFIG_PCI_INDIRECT_BRIDGE |
fab6f556 | 318 | |
fab6f556 AV |
319 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
320 | ||
321 | #undef CONFIG_EEPRO100 | |
322 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 323 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
fab6f556 AV |
324 | |
325 | #endif /* CONFIG_PCI */ | |
326 | ||
fab6f556 AV |
327 | /* |
328 | * QE UEC ethernet configuration | |
329 | */ | |
330 | #define CONFIG_UEC_ETH | |
78b7a8ef | 331 | #define CONFIG_ETHPRIME "UEC0" |
fab6f556 AV |
332 | |
333 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
334 | ||
335 | #ifdef CONFIG_UEC_ETH1 | |
6d0f6bcf JCPV |
336 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ |
337 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE | |
338 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 | |
339 | #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH | |
340 | #define CONFIG_SYS_UEC1_PHY_ADDR 2 | |
9a986550 JH |
341 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID |
342 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 | |
fab6f556 AV |
343 | #endif |
344 | ||
345 | #define CONFIG_UEC_ETH2 /* GETH2 */ | |
346 | ||
347 | #ifdef CONFIG_UEC_ETH2 | |
6d0f6bcf JCPV |
348 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
349 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE | |
350 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 | |
351 | #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH | |
352 | #define CONFIG_SYS_UEC2_PHY_ADDR 4 | |
9a986550 JH |
353 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID |
354 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 | |
fab6f556 AV |
355 | #endif |
356 | ||
357 | /* | |
358 | * Environment | |
359 | */ | |
360 | ||
6d0f6bcf | 361 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 362 | #define CONFIG_ENV_IS_IN_FLASH 1 |
9a986550 | 363 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
364 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
365 | #define CONFIG_ENV_SIZE 0x20000 | |
6d0f6bcf | 366 | #else /* CONFIG_SYS_RAMBOOT */ |
9a986550 | 367 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 368 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 369 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 370 | #define CONFIG_ENV_SIZE 0x2000 |
6d0f6bcf | 371 | #endif /* CONFIG_SYS_RAMBOOT */ |
fab6f556 AV |
372 | |
373 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 374 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
fab6f556 AV |
375 | |
376 | /* | |
377 | * BOOTP options | |
378 | */ | |
379 | #define CONFIG_BOOTP_BOOTFILESIZE | |
380 | #define CONFIG_BOOTP_BOOTPATH | |
381 | #define CONFIG_BOOTP_GATEWAY | |
382 | #define CONFIG_BOOTP_HOSTNAME | |
383 | ||
384 | ||
385 | /* | |
386 | * Command line configuration. | |
387 | */ | |
388 | #include <config_cmd_default.h> | |
389 | ||
390 | #define CONFIG_CMD_PING | |
391 | #define CONFIG_CMD_I2C | |
392 | #define CONFIG_CMD_ASKENV | |
3419eb62 | 393 | #define CONFIG_CMD_DHCP |
fab6f556 AV |
394 | |
395 | #if defined(CONFIG_PCI) | |
396 | #define CONFIG_CMD_PCI | |
397 | #endif | |
398 | ||
6d0f6bcf | 399 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 400 | #undef CONFIG_CMD_SAVEENV |
fab6f556 AV |
401 | #undef CONFIG_CMD_LOADS |
402 | #endif | |
403 | ||
404 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
405 | ||
406 | /* | |
407 | * Miscellaneous configurable options | |
408 | */ | |
6d0f6bcf JCPV |
409 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
410 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
411 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
fab6f556 AV |
412 | |
413 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 414 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
fab6f556 | 415 | #else |
6d0f6bcf | 416 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
fab6f556 AV |
417 | #endif |
418 | ||
9a986550 JH |
419 | /* Print Buffer Size */ |
420 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
421 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
422 | /* Boot Argument Buffer Size */ | |
423 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
424 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
fab6f556 AV |
425 | |
426 | /* | |
427 | * For booting Linux, the board info and command line data | |
9f530d59 | 428 | * have to be in the first 256 MB of memory, since this is |
fab6f556 AV |
429 | * the maximum mapped by the Linux kernel during initialization. |
430 | */ | |
9a986550 | 431 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
fab6f556 AV |
432 | |
433 | /* | |
434 | * Core HID Setup | |
435 | */ | |
1a2e203b KP |
436 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
437 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
438 | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 439 | #define CONFIG_SYS_HID2 HID2_HBE |
fab6f556 | 440 | |
fab6f556 AV |
441 | /* |
442 | * MMU Setup | |
443 | */ | |
444 | ||
31d82672 BB |
445 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
446 | ||
fab6f556 | 447 | /* DDR: cache cacheable */ |
9a986550 | 448 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 449 | | BATL_PP_RW \ |
9a986550 JH |
450 | | BATL_MEMCOHERENCE) |
451 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
452 | | BATU_BL_256M \ | |
453 | | BATU_VS \ | |
454 | | BATU_VP) | |
6d0f6bcf JCPV |
455 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
456 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
fab6f556 AV |
457 | |
458 | /* IMMRBAR & PCI IO: cache-inhibit and guarded */ | |
9a986550 | 459 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ |
72cd4087 | 460 | | BATL_PP_RW \ |
9a986550 JH |
461 | | BATL_CACHEINHIBIT \ |
462 | | BATL_GUARDEDSTORAGE) | |
463 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ | |
464 | | BATU_BL_4M \ | |
465 | | BATU_VS \ | |
466 | | BATU_VP) | |
6d0f6bcf JCPV |
467 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
468 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
fab6f556 AV |
469 | |
470 | /* NAND: cache-inhibit and guarded */ | |
9a986550 | 471 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \ |
72cd4087 | 472 | | BATL_PP_RW \ |
9a986550 JH |
473 | | BATL_CACHEINHIBIT \ |
474 | | BATL_GUARDEDSTORAGE) | |
475 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \ | |
476 | | BATU_BL_64M \ | |
477 | | BATU_VS \ | |
478 | | BATU_VP) | |
6d0f6bcf JCPV |
479 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
480 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
fab6f556 AV |
481 | |
482 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
9a986550 | 483 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 484 | | BATL_PP_RW \ |
9a986550 JH |
485 | | BATL_MEMCOHERENCE) |
486 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ | |
487 | | BATU_BL_32M \ | |
488 | | BATU_VS \ | |
489 | | BATU_VP) | |
490 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 491 | | BATL_PP_RW \ |
9a986550 JH |
492 | | BATL_CACHEINHIBIT \ |
493 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 494 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
fab6f556 AV |
495 | |
496 | /* Stack in dcache: cacheable, no memory coherence */ | |
9a986550 | 497 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \ |
72cd4087 | 498 | | BATL_PP_RW) |
9a986550 JH |
499 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ |
500 | | BATU_BL_128K \ | |
501 | | BATU_VS \ | |
502 | | BATU_VP) | |
6d0f6bcf JCPV |
503 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
504 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
fab6f556 | 505 | |
9a986550 | 506 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \ |
72cd4087 | 507 | | BATL_PP_RW \ |
9a986550 JH |
508 | | BATL_CACHEINHIBIT \ |
509 | | BATL_GUARDEDSTORAGE) | |
510 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \ | |
511 | | BATU_BL_64M \ | |
512 | | BATU_VS \ | |
513 | | BATU_VP) | |
6d0f6bcf JCPV |
514 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
515 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
fab6f556 AV |
516 | |
517 | #ifdef CONFIG_PCI | |
518 | /* PCI MEM space: cacheable */ | |
9a986550 | 519 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ |
72cd4087 | 520 | | BATL_PP_RW \ |
9a986550 JH |
521 | | BATL_MEMCOHERENCE) |
522 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ | |
523 | | BATU_BL_256M \ | |
524 | | BATU_VS \ | |
525 | | BATU_VP) | |
6d0f6bcf JCPV |
526 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
527 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
fab6f556 | 528 | /* PCI MMIO space: cache-inhibit and guarded */ |
9a986550 | 529 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ |
72cd4087 | 530 | | BATL_PP_RW \ |
9a986550 JH |
531 | | BATL_CACHEINHIBIT \ |
532 | | BATL_GUARDEDSTORAGE) | |
533 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ | |
534 | | BATU_BL_256M \ | |
535 | | BATU_VS \ | |
536 | | BATU_VP) | |
6d0f6bcf JCPV |
537 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
538 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
fab6f556 | 539 | #else /* CONFIG_PCI */ |
6d0f6bcf JCPV |
540 | #define CONFIG_SYS_IBAT6L (0) |
541 | #define CONFIG_SYS_IBAT6U (0) | |
542 | #define CONFIG_SYS_IBAT7L (0) | |
543 | #define CONFIG_SYS_IBAT7U (0) | |
544 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
545 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
546 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
547 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
fab6f556 AV |
548 | #endif /* CONFIG_PCI */ |
549 | ||
fab6f556 AV |
550 | #if defined(CONFIG_CMD_KGDB) |
551 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
552 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
553 | #endif | |
554 | ||
555 | /* | |
556 | * Environment Configuration | |
557 | */ | |
558 | #define CONFIG_ENV_OVERWRITE | |
559 | ||
560 | #if defined(CONFIG_UEC_ETH) | |
561 | #define CONFIG_HAS_ETH0 | |
562 | #define CONFIG_HAS_ETH1 | |
563 | #define CONFIG_HAS_ETH2 | |
564 | #define CONFIG_HAS_ETH3 | |
fab6f556 AV |
565 | #endif |
566 | ||
567 | #define CONFIG_BAUDRATE 115200 | |
568 | ||
569 | #define CONFIG_LOADADDR a00000 | |
570 | #define CONFIG_HOSTNAME mpc8360erdk | |
b3f44c21 | 571 | #define CONFIG_BOOTFILE "uImage" |
fab6f556 | 572 | |
8b3637c6 | 573 | #define CONFIG_ROOTPATH "/nfsroot/" |
fab6f556 AV |
574 | |
575 | #define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ | |
576 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
577 | ||
578 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
9a986550 JH |
579 | "netdev=eth0\0" \ |
580 | "consoledev=ttyS0\0" \ | |
581 | "loadaddr=a00000\0" \ | |
582 | "fdtaddr=900000\0" \ | |
583 | "fdtfile=mpc836x_rdk.dtb\0" \ | |
584 | "fsfile=fs\0" \ | |
585 | "ubootfile=u-boot.bin\0" \ | |
586 | "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\ | |
587 | "-(rootfs)\0" \ | |
588 | "setbootargs=setenv bootargs console=$consoledev,$baudrate " \ | |
589 | "$mtdparts panic=1\0" \ | |
590 | "adddhcpargs=setenv bootargs $bootargs ip=on\0" \ | |
591 | "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \ | |
592 | "$gatewayip:$netmask:$hostname:$netdev:off " \ | |
593 | "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \ | |
594 | "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \ | |
595 | "rootfstype=jffs2 rw\0" \ | |
596 | "tftp_get_uboot=tftp 100000 $ubootfile\0" \ | |
597 | "tftp_get_kernel=tftp $loadaddr $bootfile\0" \ | |
598 | "tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \ | |
599 | "tftp_get_fs=tftp c00000 $fsfile\0" \ | |
600 | "nand_erase_kernel=nand erase 0 400000\0" \ | |
601 | "nand_erase_dtb=nand erase 400000 20000\0" \ | |
602 | "nand_erase_fs=nand erase 420000 3be0000\0" \ | |
603 | "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \ | |
604 | "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \ | |
605 | "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \ | |
606 | "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \ | |
607 | "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \ | |
608 | "nor_reflash=protect off ff800000 ff87ffff ; " \ | |
609 | "erase ff800000 ff87ffff ; " \ | |
610 | "cp.b 100000 ff800000 $filesize\0" \ | |
611 | "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \ | |
612 | "nand_write_kernel\0" \ | |
613 | "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\ | |
614 | "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \ | |
615 | "nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \ | |
616 | "nand_reflash_fs\0" \ | |
617 | "boot_m=bootm $loadaddr - $fdtaddr\0" \ | |
618 | "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\ | |
619 | "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\ | |
620 | "boot_m\0" \ | |
621 | "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\ | |
622 | "boot_m\0" \ | |
623 | "" | |
fab6f556 AV |
624 | |
625 | #define CONFIG_BOOTCOMMAND "run dhcpboot" | |
626 | ||
627 | #endif /* __CONFIG_H */ |