[people/ms/u-boot.git] / include / configs / MPC8540EVAL.h

/*
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Modified by Lunsheng Wang, lunsheng@sohu.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* mpc8540eval board configuration file */
/* please refer to doc/README.mpc85xxads for more info */
/* make sure you change the MAC address and other network params first,
 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
 */

#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_BOOKE		1	    /* BOOKE			*/
#define CONFIG_E500		1	    /* BOOKE e500 family	*/
#define CONFIG_MPC85xx		1	    /* MPC8540/MPC8560		*/
#define CONFIG_MPC8540		1	    /* MPC8540 specific	        */
#define CONFIG_MPC8540EVAL	1	    /* MPC8540EVAL board specific */

#undef  CONFIG_PCI			    /* pci ethernet support	*/
#define CONFIG_TSEC_ENET		    /* tsec ethernet support  */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

/* Using Localbus SDRAM to emulate flash before we can program the flash,
 * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
 * Not availabe for EVAL board
 */
#undef CONFIG_RAM_AS_FLASH

/* sysclk for MPC8540EVAL */
#if defined(CONFIG_SYSCLK_66M)
	/*
	 * the oscillator on board is 66Mhz
	 * can also get 66M clock from external PCI
	 */
	#define CONFIG_SYS_CLK_FREQ   66000000
#else
	#define CONFIG_SYS_CLK_FREQ   33000000   /* most pci cards are 33Mhz */
#endif

/* below can be toggled for performance analysis. otherwise use default */
#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
#undef  CONFIG_BTB			    /* toggle branch predition */
#undef  CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */

#define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/

#undef	CFG_DRAM_TEST			    /* memory test, takes time  */
#define CFG_MEMTEST_START	0x00200000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x00400000

#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
#endif

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR	*/
#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/

#define CFG_SDRAM_SIZE		256             /* DDR is now 256MB     */

#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
#else
#define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
#endif
#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 0MB	*/

#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_FLASH_BASE          0xf8000000      /* start of FLASH  16M  */
#define CFG_BR0_PRELIM          0xf8001801      /* port size 32bit */
#else /* Boot from real Flash */
#define CFG_FLASH_BASE		0xff800000	/* start of FLASH 8M    */
#define CFG_BR0_PRELIM		0xff801001	/* port size 16bit	*/
#endif

#define	CFG_OR0_PRELIM		0xff806f67	/* 8MB Flash		*/
#define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
#define CFG_MAX_FLASH_SECT	64		/* sectors per device   */
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)*/
#define CFG_FLASH_CFI		1

#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef  CFG_RAMBOOT
#endif

/* DDR Setup */
#define CONFIG_FSL_DDR1
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_DDR_DLL                      /* possible DLL fix needed */

#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CFG_DDR_SDRAM_BASE	0x00000000
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

#undef CONFIG_CLOCKS_IN_MHZ

/* local bus definitions */
#define CFG_BR2_PRELIM		0xf0001861	/* 64MB localbus SDRAM  */
#define CFG_OR2_PRELIM		0xfc006901
#define CFG_LBC_LCRR		0x00030004	/* local bus freq divider*/
#define CFG_LBC_LBCR		0x00000000
#define CFG_LBC_LSRT		0x20000000
#define CFG_LBC_MRTPR		0x20000000
#define CFG_LBC_LSDMR_1		0x2861b723
#define CFG_LBC_LSDMR_2		0x0861b723
#define CFG_LBC_LSDMR_3		0x0861b723
#define CFG_LBC_LSDMR_4		0x1861b723
#define CFG_LBC_LSDMR_5		0x4061b723

#if defined(CONFIG_RAM_AS_FLASH)
#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
#else
#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
#endif
#define CFG_OR4_PRELIM          0xffffe1f1
#define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	0x40000000	/* Initial RAM address	*/
#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */

#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE    1
#define CFG_NS16550_CLK		get_bus_freq(0)
#define CONFIG_BAUDRATE		115200

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef  CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
#define CFG_I2C_OFFSET		0x3000

/* General PCI */
#define CFG_PCI_MEM_BASE	0x80000000
#define CFG_PCI_MEM_PHYS	0x80000000
#define CFG_PCI_MEM_SIZE	0x20000000
#define CFG_PCI_IO_BASE         0xe2000000

#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#undef CONFIG_EEPRO100
#define CONFIG_TULIP
#define CONFIG_PCI_PNP			/* do pci plug-and-play */
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR      0xe0000000
#define PCI_ENET0_MEMADDR     0xe0000000
#define PCI_IDSEL_NUMBER      0x0c	/*slot0->3(IDSEL)=12->15*/
#endif
#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
#define CFG_PCI_SUBSYS_DEVICEID 0x0008
#elif defined(CONFIG_TSEC_ENET)
#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1	/* MII PHY management	*/
#define CONFIG_TSEC1    1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME      "TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME      "TSEC1"
#define CONFIG_MPC85XX_FEC      1
#define CONFIG_HAS_ETH2
#define CONFIG_MPC85XX_FEC_NAME                "FEC"
#define TSEC1_PHY_ADDR          7
#define	TSEC2_PHY_ADDR		4
#define FEC_PHY_ADDR            2
#define TSEC1_PHYIDX            0
#define TSEC2_PHYIDX            0
#define FEC_PHYIDX              0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT
#define FEC_FLAGS		0

/* Options are: TSEC[0-1], FEC */
#define CONFIG_ETHPRIME                "TSEC0"

#define CONFIG_PHY_M88E1011     1       /* GigaBit Ether PHY    */
#define INTEL_LXT971_PHY	1
#endif

/* Environment */
#ifndef CFG_RAMBOOT
#if defined(CONFIG_RAM_AS_FLASH)
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x100000)
#define CONFIG_ENV_SIZE		0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
#endif
#define CONFIG_ENV_SIZE		0x2000
#else
/* #define CFG_NO_FLASH		1 */	/* Flash is not usable now	*/
#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_BOOTARGS	"root=/dev/ram rw console=ttyS0,115200"
#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
    #undef CONFIG_CMD_ENV
    #undef CONFIG_CMD_LOADS
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_LOAD_ADDR   0x2000000       /* default load address */
#define CFG_PROMPT	"MPC8540EVAL=> "/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot		*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*****************************/
/* Environment Configuration */
/*****************************/
/* The mac addresses for all ethernet interface */
/* NOTE: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR  00:01:af:07:9b:8a
#define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
#define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
#endif

#define CONFIG_ROOTPATH  /nfsroot
#define CONFIG_BOOTFILE  your.uImage

#define CONFIG_SERVERIP         192.168.101.1
#define CONFIG_IPADDR           192.168.101.11
#define CONFIG_GATEWAYIP        192.168.101.0
#define CONFIG_NETMASK          255.255.255.0

#define CONFIG_LOADADDR  200000   /* default location for tftp and bootm */

#define CONFIG_HOSTNAME         MPC8540EVAL

#endif	/* __CONFIG_H */
Commit	Line	Data
b0e32949 LW	1	/*
	2	* (C) Copyright 2002,2003 Motorola,Inc.
	3	* Modified by Lunsheng Wang, lunsheng@sohu.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/* mpc8540eval board configuration file */
	25	/* please refer to doc/README.mpc85xxads for more info */
	26	/* make sure you change the MAC address and other network params first,
	27	* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32	/* High Level Configuration Options */
53677ef1	33	#define CONFIG_BOOKE 1 /* BOOKE */
b0e32949 LW	34	#define CONFIG_E500 1 /* BOOKE e500 family */
	35	#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
	36	#define CONFIG_MPC8540 1 /* MPC8540 specific */
	37	#define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */
	38
53677ef1 WD	39	#undef CONFIG_PCI /* pci ethernet support */
53677ef1 WD	40	#define CONFIG_TSEC_ENET /* tsec ethernet support */
b0e32949	41	#define CONFIG_ENV_OVERWRITE
b0e32949	42
4d3521cc KG	43	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
4d3521cc KG	44
b0e32949 LW	45	/* Using Localbus SDRAM to emulate flash before we can program the flash,
	46	* normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
	47	* Not availabe for EVAL board
	48	*/
	49	#undef CONFIG_RAM_AS_FLASH
	50
	51	/* sysclk for MPC8540EVAL */
	52	#if defined(CONFIG_SYSCLK_66M)
de1d0a69 JL	53	/*
	54	* the oscillator on board is 66Mhz
	55	* can also get 66M clock from external PCI
	56	*/
	57	#define CONFIG_SYS_CLK_FREQ 66000000
b0e32949	58	#else
de1d0a69	59	#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
b0e32949 LW	60	#endif
	61
	62	/* below can be toggled for performance analysis. otherwise use default */
53677ef1	63	#define CONFIG_L2_CACHE /* toggle L2 cache */
b0e32949 LW	64	#undef CONFIG_BTB /* toggle branch predition */
	65	#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
	66
	67	#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
	68
	69	#undef CFG_DRAM_TEST /* memory test, takes time */
	70	#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
	71	#define CFG_MEMTEST_END 0x00400000
	72
	73	#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
	74	#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
	75	#endif
	76
	77	/*
	78	* Base addresses -- Note these are effective addresses where the
	79	* actual resources get mapped (not physical addresses)
	80	*/
53677ef1 WD	81	#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
53677ef1 WD	82	#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
f69766e4	83	#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
b0e32949 LW	84	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
b0e32949 LW	85
b0e32949 LW	86	#define CFG_SDRAM_SIZE 256 /* DDR is now 256MB */
	87
	88	#if defined(CONFIG_RAM_AS_FLASH)
	89	#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
	90	#else
	91	#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
	92	#endif
	93	#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 0MB */
	94
	95	#if defined(CONFIG_RAM_AS_FLASH)
	96	#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
	97	#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
	98	#else /* Boot from real Flash */
	99	#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
	100	#define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */
	101	#endif
	102
	103	#define CFG_OR0_PRELIM 0xff806f67 /* 8MB Flash */
	104	#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
	105	#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
	106	#undef CFG_FLASH_CHECKSUM
	107	#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/
	108	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/
	109	#define CFG_FLASH_CFI 1
	110
53677ef1	111	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
b0e32949 LW	112
	113	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	114	#define CFG_RAMBOOT
	115	#else
	116	#undef CFG_RAMBOOT
	117	#endif
	118
9658bec2 KG	119	/* DDR Setup */
	120	#define CONFIG_FSL_DDR1
	121	#undef CONFIG_FSL_DDR_INTERACTIVE
	122	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	123	#define CONFIG_DDR_SPD
	124	#define CONFIG_DDR_DLL /* possible DLL fix needed */
	125
	126	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	127	#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
	128	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	129
	130	#define CFG_DDR_SDRAM_BASE 0x00000000
	131	#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
	132	#define CONFIG_VERY_BIG_RAM
b0e32949	133
9658bec2 KG	134	#define CONFIG_NUM_DDR_CONTROLLERS 1
	135	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	136	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
b0e32949	137
9658bec2 KG	138	/* I2C addresses of SPD EEPROMs */
9658bec2 KG	139	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
b0e32949 LW	140
	141	#undef CONFIG_CLOCKS_IN_MHZ
	142
	143	/* local bus definitions */
	144	#define CFG_BR2_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
	145	#define CFG_OR2_PRELIM 0xfc006901
	146	#define CFG_LBC_LCRR 0x00030004 /* local bus freq divider*/
	147	#define CFG_LBC_LBCR 0x00000000
	148	#define CFG_LBC_LSRT 0x20000000
	149	#define CFG_LBC_MRTPR 0x20000000
	150	#define CFG_LBC_LSDMR_1 0x2861b723
	151	#define CFG_LBC_LSDMR_2 0x0861b723
	152	#define CFG_LBC_LSDMR_3 0x0861b723
	153	#define CFG_LBC_LSDMR_4 0x1861b723
	154	#define CFG_LBC_LSDMR_5 0x4061b723
	155
	156	#if defined(CONFIG_RAM_AS_FLASH)
	157	#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
	158	#else
	159	#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
	160	#endif
	161	#define CFG_OR4_PRELIM 0xffffe1f1
	162	#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
	163
	164	#define CONFIG_L1_INIT_RAM
53677ef1 WD	165	#define CFG_INIT_RAM_LOCK 1
	166	#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
	167	#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
b0e32949	168
53677ef1	169	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
b0e32949 LW	170	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	171	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	172
53677ef1 WD	173	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
53677ef1 WD	174	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
b0e32949 LW	175
	176	/* Serial Port */
	177	#define CONFIG_CONS_INDEX 1
	178	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	179	#define CFG_NS16550
	180	#define CFG_NS16550_SERIAL
	181	#define CFG_NS16550_REG_SIZE 1
	182	#define CFG_NS16550_CLK get_bus_freq(0)
53677ef1	183	#define CONFIG_BAUDRATE 115200
b0e32949 LW	184
	185	#define CFG_BAUDRATE_TABLE \
	186	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	187
	188	#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
	189	#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
	190
	191	/* Use the HUSH parser */
	192	#define CFG_HUSH_PARSER
	193	#ifdef CFG_HUSH_PARSER
	194	#define CFG_PROMPT_HUSH_PS2 "> "
	195	#endif
	196
20476726 JL	197	/*
	198	* I2C
	199	*/
	200	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	201	#define CONFIG_HARD_I2C /* I2C with hardware support*/
b0e32949 LW	202	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	203	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	204	#define CFG_I2C_SLAVE 0x7F
	205	#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
20476726	206	#define CFG_I2C_OFFSET 0x3000
b0e32949 LW	207
	208	/* General PCI */
	209	#define CFG_PCI_MEM_BASE 0x80000000
	210	#define CFG_PCI_MEM_PHYS 0x80000000
	211	#define CFG_PCI_MEM_SIZE 0x20000000
	212	#define CFG_PCI_IO_BASE 0xe2000000
	213
	214	#if defined(CONFIG_PCI)
	215	#define CONFIG_NET_MULTI
	216	#undef CONFIG_EEPRO100
	217	#define CONFIG_TULIP
53677ef1	218	#define CONFIG_PCI_PNP /* do pci plug-and-play */
de1d0a69 JL	219	#if !defined(CONFIG_PCI_PNP)
	220	#define PCI_ENET0_IOADDR 0xe0000000
	221	#define PCI_ENET0_MEMADDR 0xe0000000
53677ef1	222	#define PCI_IDSEL_NUMBER 0x0c /slot0->3(IDSEL)=12->15/
de1d0a69	223	#endif
b0e32949 LW	224	#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
	225	#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
	226	#define CFG_PCI_SUBSYS_DEVICEID 0x0008
	227	#elif defined(CONFIG_TSEC_ENET)
53677ef1	228	#define CONFIG_NET_MULTI 1
b0e32949	229	#define CONFIG_MII 1 /* MII PHY management */
255a3577	230	#define CONFIG_TSEC1 1
10327dc5	231	#define CONFIG_HAS_ETH0
255a3577 KP	232	#define CONFIG_TSEC1_NAME "TSEC0"
255a3577 KP	233	#define CONFIG_TSEC2 1
10327dc5	234	#define CONFIG_HAS_ETH1
255a3577	235	#define CONFIG_TSEC2_NAME "TSEC1"
b0e32949	236	#define CONFIG_MPC85XX_FEC 1
10327dc5	237	#define CONFIG_HAS_ETH2
b0e32949 LW	238	#define CONFIG_MPC85XX_FEC_NAME "FEC"
	239	#define TSEC1_PHY_ADDR 7
	240	#define TSEC2_PHY_ADDR 4
	241	#define FEC_PHY_ADDR 2
	242	#define TSEC1_PHYIDX 0
	243	#define TSEC2_PHYIDX 0
	244	#define FEC_PHYIDX 0
3a79013e AF	245	#define TSEC1_FLAGS TSEC_GIGABIT
	246	#define TSEC2_FLAGS TSEC_GIGABIT
	247	#define FEC_FLAGS 0
	248
b0e32949 LW	249	/* Options are: TSEC[0-1], FEC */
	250	#define CONFIG_ETHPRIME "TSEC0"
	251
	252	#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
de1d0a69	253	#define INTEL_LXT971_PHY 1
b0e32949 LW	254	#endif
b0e32949 LW	255
b0e32949 LW	256	/* Environment */
b0e32949 LW	257	#ifndef CFG_RAMBOOT
de1d0a69	258	#if defined(CONFIG_RAM_AS_FLASH)
93f6d725	259	#define CONFIG_ENV_IS_NOWHERE
0e8d1586 JCPV	260	#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
0e8d1586 JCPV	261	#define CONFIG_ENV_SIZE 0x2000
de1d0a69	262	#else
5a1aceb0	263	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	264	#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
0e8d1586 JCPV	265	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
de1d0a69	266	#endif
0e8d1586	267	#define CONFIG_ENV_SIZE 0x2000
b0e32949 LW	268	#else
b0e32949 LW	269	/* #define CFG_NO_FLASH 1 / / Flash is not usable now */
93f6d725	270	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
0e8d1586 JCPV	271	#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
0e8d1586 JCPV	272	#define CONFIG_ENV_SIZE 0x2000
b0e32949 LW	273	#endif
b0e32949 LW	274
b0e32949 LW	275	#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
b0e32949 LW	276	#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
53677ef1	277	#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
b0e32949 LW	278
	279	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	280	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	281
2835e518	282
659e2f67 JL	283	/*
	284	* BOOTP options
	285	*/
	286	#define CONFIG_BOOTP_BOOTFILESIZE
	287	#define CONFIG_BOOTP_BOOTPATH
	288	#define CONFIG_BOOTP_GATEWAY
	289	#define CONFIG_BOOTP_HOSTNAME
	290
	291
2835e518 JL	292	/*
	293	* Command line configuration.
	294	*/
	295	#include <config_cmd_default.h>
	296
	297	#define CONFIG_CMD_PING
	298	#define CONFIG_CMD_I2C
	299
de1d0a69	300	#if defined(CONFIG_PCI)
2835e518	301	#define CONFIG_CMD_PCI
de1d0a69	302	#endif
2835e518 JL	303
	304	#if defined(CFG_RAMBOOT) \|\| defined(CONFIG_RAM_AS_FLASH)
	305	#undef CONFIG_CMD_ENV
	306	#undef CONFIG_CMD_LOADS
de1d0a69 JL	307	#endif
de1d0a69 JL	308
b0e32949 LW	309
	310	#undef CONFIG_WATCHDOG /* watchdog disabled */
	311
	312	/*
	313	* Miscellaneous configurable options
	314	*/
	315	#define CFG_LONGHELP /* undef to save memory */
	316	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
	317	#define CFG_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */
2835e518	318	#if defined(CONFIG_CMD_KGDB)
b0e32949 LW	319	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	320	#else
	321	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	322	#endif
	323	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	324	#define CFG_MAXARGS 16 /* max number of command args */
	325	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	326	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	327
	328	/*
	329	* For booting Linux, the board info and command line data
	330	* have to be in the first 8 MB of memory, since this is
	331	* the maximum mapped by the Linux kernel during initialization.
	332	*/
53677ef1	333	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
b0e32949	334
b0e32949 LW	335	/*
	336	* Internal Definitions
	337	*
	338	* Boot Flags
	339	*/
	340	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	341	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	342
2835e518	343	#if defined(CONFIG_CMD_KGDB)
b0e32949 LW	344	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	345	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	346	#endif
	347
	348	/*****************************/
	349	/* Environment Configuration */
	350	/*****************************/
	351	/* The mac addresses for all ethernet interface */
	352	/* NOTE: change below for your network setting!!! */
	353	#if defined(CONFIG_TSEC_ENET)
	354	#define CONFIG_ETHADDR 00:01:af:07:9b:8a
	355	#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
	356	#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
	357	#endif
	358
	359	#define CONFIG_ROOTPATH /nfsroot
	360	#define CONFIG_BOOTFILE your.uImage
	361
	362	#define CONFIG_SERVERIP 192.168.101.1
	363	#define CONFIG_IPADDR 192.168.101.11
	364	#define CONFIG_GATEWAYIP 192.168.101.0
	365	#define CONFIG_NETMASK 255.255.255.0
	366
	367	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	368
	369	#define CONFIG_HOSTNAME MPC8540EVAL
	370
	371	#endif /* __CONFIG_H */