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0cde4b00 | 1 | /* |
7c57f3e8 | 2 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. |
0cde4b00 JL |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * mpc8544ds board configuration file | |
25 | * | |
26 | */ | |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* High Level Configuration Options */ | |
31 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
32 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
33 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
34 | #define CONFIG_MPC8544 1 | |
35 | #define CONFIG_MPC8544DS 1 | |
36 | ||
2ae18241 WD |
37 | #ifndef CONFIG_SYS_TEXT_BASE |
38 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
39 | #endif | |
40 | ||
837f1ba0 ES |
41 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
42 | #define CONFIG_PCI1 1 /* PCI controller 1 */ | |
43 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
44 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
45 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
46 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
8ff3de61 | 47 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
0151cbac | 48 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
837f1ba0 | 49 | |
4bcae9c9 | 50 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
f6155c6f | 51 | #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ |
4bcae9c9 | 52 | |
837f1ba0 | 53 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
0cde4b00 | 54 | #define CONFIG_ENV_OVERWRITE |
837f1ba0 | 55 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
0cde4b00 | 56 | |
0cde4b00 JL |
57 | #ifndef __ASSEMBLY__ |
58 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
59 | #endif | |
60 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
61 | ||
62 | /* | |
63 | * These can be toggled for performance analysis, otherwise use default. | |
64 | */ | |
837f1ba0 | 65 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
0cde4b00 | 66 | #define CONFIG_BTB /* toggle branch predition */ |
0cde4b00 JL |
67 | |
68 | /* | |
69 | * Only possible on E500 Version 2 or newer cores. | |
70 | */ | |
71 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
72 | ||
6d0f6bcf JCPV |
73 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
74 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
837f1ba0 | 75 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
0cde4b00 JL |
76 | |
77 | /* | |
78 | * Base addresses -- Note these are effective addresses where the | |
79 | * actual resources get mapped (not physical addresses) | |
80 | */ | |
6d0f6bcf JCPV |
81 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
82 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ | |
83 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
84 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
0cde4b00 | 85 | |
1167a2fd KG |
86 | /* DDR Setup */ |
87 | #define CONFIG_FSL_DDR2 | |
88 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
89 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
90 | #define CONFIG_DDR_SPD | |
91 | ||
9b0ad1b1 | 92 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
1167a2fd KG |
93 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
94 | ||
6d0f6bcf JCPV |
95 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
96 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
1167a2fd KG |
97 | #define CONFIG_VERY_BIG_RAM |
98 | ||
99 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
100 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
101 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
0cde4b00 | 102 | |
1167a2fd | 103 | /* I2C addresses of SPD EEPROMs */ |
0cde4b00 JL |
104 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
105 | ||
1167a2fd | 106 | /* Make sure required options are set */ |
0cde4b00 JL |
107 | #ifndef CONFIG_SPD_EEPROM |
108 | #error ("CONFIG_SPD_EEPROM is required") | |
109 | #endif | |
110 | ||
111 | #undef CONFIG_CLOCKS_IN_MHZ | |
112 | ||
113 | /* | |
114 | * Memory map | |
115 | * | |
116 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
117 | * | |
118 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
119 | * | |
120 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
121 | * | |
122 | * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable | |
123 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
124 | * | |
125 | * Localbus cacheable | |
126 | * | |
127 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable | |
128 | * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 | |
129 | * | |
130 | * Localbus non-cacheable | |
131 | * | |
132 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable | |
133 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable | |
134 | * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable | |
135 | * | |
136 | */ | |
137 | ||
138 | /* | |
139 | * Local Bus Definitions | |
140 | */ | |
6d0f6bcf | 141 | #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ |
0cde4b00 | 142 | |
6d0f6bcf | 143 | #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ |
0cde4b00 | 144 | |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 |
146 | #define CONFIG_SYS_BR1_PRELIM 0xfe801001 | |
0cde4b00 | 147 | |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
149 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
0cde4b00 | 150 | |
6d0f6bcf | 151 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
0cde4b00 | 152 | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_FLASH_QUIET_TEST |
154 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
155 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
156 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
157 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
158 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
81e56e9a | 159 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
0cde4b00 | 160 | |
14d0a02a | 161 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
0cde4b00 | 162 | |
00b1883a | 163 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_FLASH_CFI |
165 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
0cde4b00 | 166 | |
6d0f6bcf | 167 | #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 |
0cde4b00 | 168 | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ |
170 | #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ | |
0cde4b00 | 171 | |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ |
173 | #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ | |
0cde4b00 | 174 | |
7608d75f | 175 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
0cde4b00 JL |
176 | #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ |
177 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
178 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
179 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
180 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
181 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch | |
182 | * register */ | |
183 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
184 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
185 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
186 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
187 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
6bb5b412 KG |
188 | #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ |
189 | #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ | |
0cde4b00 JL |
190 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
191 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
192 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
193 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
5a8a163a | 194 | #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ |
6d0f6bcf | 195 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
5a8a163a AF |
196 | #define PIXIS_VSPEED2_TSEC1SER 0x2 |
197 | #define PIXIS_VSPEED2_TSEC3SER 0x1 | |
198 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 | |
199 | #define PIXIS_VCFGEN1_TSEC3SER 0x40 | |
bff188ba LY |
200 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) |
201 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) | |
0cde4b00 JL |
202 | |
203 | ||
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
205 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ | |
553f0982 | 206 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
1107014e | 207 | |
0cde4b00 | 208 | |
25ddd1fb | 209 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 210 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
0cde4b00 | 211 | |
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
213 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
0cde4b00 JL |
214 | |
215 | /* Serial Port - controlled on board with jumper J8 | |
216 | * open - index 2 | |
217 | * shorted - index 1 | |
218 | */ | |
219 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_NS16550 |
221 | #define CONFIG_SYS_NS16550_SERIAL | |
222 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
223 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
0cde4b00 | 224 | |
6d0f6bcf | 225 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
0cde4b00 JL |
226 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
227 | ||
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
229 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
0cde4b00 JL |
230 | |
231 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
232 | #define CONFIG_SYS_HUSH_PARSER |
233 | #ifdef CONFIG_SYS_HUSH_PARSER | |
234 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
0cde4b00 JL |
235 | #endif |
236 | ||
237 | /* pass open firmware flat tree */ | |
addce57e KG |
238 | #define CONFIG_OF_LIBFDT 1 |
239 | #define CONFIG_OF_BOARD_SETUP 1 | |
240 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
0cde4b00 JL |
241 | |
242 | /* I2C */ | |
243 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
244 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
245 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
247 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
248 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
249 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
250 | #define CONFIG_SYS_I2C_OFFSET 0x3100 | |
0cde4b00 JL |
251 | |
252 | /* | |
253 | * General PCI | |
254 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
255 | */ | |
5af0fdd8 | 256 | #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ |
6d0f6bcf | 257 | #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ |
5af0fdd8 | 258 | #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ |
6d0f6bcf | 259 | #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ |
0cde4b00 | 260 | |
5af0fdd8 | 261 | #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 |
10795f42 | 262 | #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 |
5af0fdd8 | 263 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 |
6d0f6bcf | 264 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 265 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 |
5f91ef6a | 266 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
267 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 |
268 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ | |
0cde4b00 | 269 | |
0cde4b00 | 270 | /* controller 2, Slot 1, tgtid 1, Base address 9000 */ |
64a1686a | 271 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
5af0fdd8 | 272 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 |
10795f42 | 273 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 |
5af0fdd8 | 274 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 |
6d0f6bcf | 275 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 276 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 |
5f91ef6a | 277 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
278 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 |
279 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
0cde4b00 JL |
280 | |
281 | /* controller 1, Slot 2,tgtid 2, Base address a000 */ | |
64a1686a | 282 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
5af0fdd8 | 283 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
10795f42 | 284 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
5af0fdd8 | 285 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
6d0f6bcf | 286 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ |
aca5f018 | 287 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 |
5f91ef6a | 288 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
289 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 |
290 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
0cde4b00 JL |
291 | |
292 | /* controller 3, direct to uli, tgtid 3, Base address b000 */ | |
64a1686a | 293 | #define CONFIG_SYS_PCIE3_NAME "ULI" |
5af0fdd8 | 294 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 |
10795f42 | 295 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 |
5af0fdd8 | 296 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 |
6d0f6bcf | 297 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ |
aca5f018 | 298 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ |
5f91ef6a | 299 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ |
301 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ | |
5af0fdd8 | 302 | #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 |
10795f42 | 303 | #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 |
5af0fdd8 | 304 | #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 |
6d0f6bcf | 305 | #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ |
0cde4b00 JL |
306 | |
307 | #if defined(CONFIG_PCI) | |
308 | ||
630d9bfc | 309 | /*PCIE video card used*/ |
aca5f018 | 310 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT |
630d9bfc KG |
311 | |
312 | /*PCI video card used*/ | |
aca5f018 | 313 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ |
630d9bfc KG |
314 | |
315 | /* video */ | |
316 | #define CONFIG_VIDEO | |
317 | ||
318 | #if defined(CONFIG_VIDEO) | |
319 | #define CONFIG_BIOSEMU | |
320 | #define CONFIG_CFB_CONSOLE | |
321 | #define CONFIG_VIDEO_SW_CURSOR | |
322 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
323 | #define CONFIG_ATI_RADEON_FB | |
324 | #define CONFIG_VIDEO_LOGO | |
325 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
6d0f6bcf | 326 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
630d9bfc KG |
327 | #endif |
328 | ||
0cde4b00 JL |
329 | #define CONFIG_NET_MULTI |
330 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
331 | ||
332 | #undef CONFIG_EEPRO100 | |
333 | #undef CONFIG_TULIP | |
334 | #define CONFIG_RTL8139 | |
335 | ||
0cde4b00 | 336 | #ifndef CONFIG_PCI_PNP |
5f91ef6a KG |
337 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS |
338 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS | |
0cde4b00 JL |
339 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
340 | #endif | |
341 | ||
342 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
343 | #define CONFIG_DOS_PARTITION | |
344 | #define CONFIG_SCSI_AHCI | |
345 | ||
346 | #ifdef CONFIG_SCSI_AHCI | |
347 | #define CONFIG_SATA_ULI5288 | |
6d0f6bcf JCPV |
348 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
349 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
350 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
351 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
0cde4b00 JL |
352 | #endif /* SCSCI */ |
353 | ||
354 | #endif /* CONFIG_PCI */ | |
355 | ||
356 | ||
357 | #if defined(CONFIG_TSEC_ENET) | |
358 | ||
359 | #ifndef CONFIG_NET_MULTI | |
837f1ba0 | 360 | #define CONFIG_NET_MULTI 1 |
0cde4b00 JL |
361 | #endif |
362 | ||
363 | #define CONFIG_MII 1 /* MII PHY management */ | |
364 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
255a3577 KP |
365 | #define CONFIG_TSEC1 1 |
366 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
367 | #define CONFIG_TSEC3 1 | |
368 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
837f1ba0 | 369 | |
bff188ba | 370 | #define CONFIG_PIXIS_SGMII_CMD |
652f7c2e AF |
371 | #define CONFIG_FSL_SGMII_RISER 1 |
372 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
373 | ||
0cde4b00 JL |
374 | #define TSEC1_PHY_ADDR 0 |
375 | #define TSEC3_PHY_ADDR 1 | |
376 | ||
3a79013e AF |
377 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
378 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
379 | ||
0cde4b00 JL |
380 | #define TSEC1_PHYIDX 0 |
381 | #define TSEC3_PHYIDX 0 | |
382 | ||
383 | #define CONFIG_ETHPRIME "eTSEC1" | |
384 | ||
385 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
0cde4b00 JL |
386 | #endif /* CONFIG_TSEC_ENET */ |
387 | ||
388 | /* | |
389 | * Environment | |
390 | */ | |
5a1aceb0 | 391 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 392 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
0e8d1586 | 393 | #define CONFIG_ENV_ADDR 0xfff80000 |
0cde4b00 | 394 | #else |
6d0f6bcf | 395 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) |
0cde4b00 | 396 | #endif |
0e8d1586 JCPV |
397 | #define CONFIG_ENV_SIZE 0x2000 |
398 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ | |
0cde4b00 JL |
399 | |
400 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 401 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
0cde4b00 | 402 | |
659e2f67 JL |
403 | /* |
404 | * BOOTP options | |
405 | */ | |
406 | #define CONFIG_BOOTP_BOOTFILESIZE | |
407 | #define CONFIG_BOOTP_BOOTPATH | |
408 | #define CONFIG_BOOTP_GATEWAY | |
409 | #define CONFIG_BOOTP_HOSTNAME | |
410 | ||
411 | ||
2835e518 JL |
412 | /* |
413 | * Command line configuration. | |
414 | */ | |
415 | #include <config_cmd_default.h> | |
416 | ||
417 | #define CONFIG_CMD_PING | |
418 | #define CONFIG_CMD_I2C | |
419 | #define CONFIG_CMD_MII | |
82ac8c97 | 420 | #define CONFIG_CMD_ELF |
1c9aa76b KG |
421 | #define CONFIG_CMD_IRQ |
422 | #define CONFIG_CMD_SETEXPR | |
199e262e | 423 | #define CONFIG_CMD_REGINFO |
2835e518 | 424 | |
0cde4b00 | 425 | #if defined(CONFIG_PCI) |
2835e518 | 426 | #define CONFIG_CMD_PCI |
2835e518 | 427 | #define CONFIG_CMD_NET |
837f1ba0 ES |
428 | #define CONFIG_CMD_SCSI |
429 | #define CONFIG_CMD_EXT2 | |
0cde4b00 | 430 | #endif |
2835e518 | 431 | |
0cde4b00 JL |
432 | |
433 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
434 | ||
435 | /* | |
436 | * Miscellaneous configurable options | |
437 | */ | |
6d0f6bcf | 438 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
439 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
440 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf JCPV |
441 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
442 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
2835e518 | 443 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 444 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
0cde4b00 | 445 | #else |
6d0f6bcf | 446 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
0cde4b00 | 447 | #endif |
6d0f6bcf JCPV |
448 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
449 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
450 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
451 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
0cde4b00 JL |
452 | |
453 | /* | |
454 | * For booting Linux, the board info and command line data | |
a832ac41 | 455 | * have to be in the first 64 MB of memory, since this is |
0cde4b00 JL |
456 | * the maximum mapped by the Linux kernel during initialization. |
457 | */ | |
a832ac41 KG |
458 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
459 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
0cde4b00 | 460 | |
2835e518 | 461 | #if defined(CONFIG_CMD_KGDB) |
0cde4b00 JL |
462 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
463 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
464 | #endif | |
465 | ||
466 | /* | |
467 | * Environment Configuration | |
468 | */ | |
469 | ||
470 | /* The mac addresses for all ethernet interface */ | |
471 | #if defined(CONFIG_TSEC_ENET) | |
ea5877e3 | 472 | #define CONFIG_HAS_ETH0 |
0cde4b00 JL |
473 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD |
474 | #define CONFIG_HAS_ETH1 | |
475 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD | |
0cde4b00 JL |
476 | #endif |
477 | ||
478 | #define CONFIG_IPADDR 192.168.1.251 | |
479 | ||
480 | #define CONFIG_HOSTNAME 8544ds_unknown | |
481 | #define CONFIG_ROOTPATH /nfs/mpc85xx | |
837f1ba0 ES |
482 | #define CONFIG_BOOTFILE 8544ds/uImage.uboot |
483 | #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ | |
0cde4b00 | 484 | |
50c03c8c KG |
485 | #define CONFIG_SERVERIP 192.168.1.1 |
486 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
0cde4b00 JL |
487 | #define CONFIG_NETMASK 255.255.0.0 |
488 | ||
489 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ | |
490 | ||
491 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
837f1ba0 | 492 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
0cde4b00 JL |
493 | |
494 | #define CONFIG_BAUDRATE 115200 | |
495 | ||
837f1ba0 ES |
496 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
497 | "netdev=eth0\0" \ | |
498 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
499 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
14d0a02a WD |
500 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
501 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
502 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
503 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
504 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
0cde4b00 JL |
505 | "consoledev=ttyS0\0" \ |
506 | "ramdiskaddr=2000000\0" \ | |
837f1ba0 | 507 | "ramdiskfile=8544ds/ramdisk.uboot\0" \ |
50c03c8c KG |
508 | "fdtaddr=c00000\0" \ |
509 | "fdtfile=8544ds/mpc8544ds.dtb\0" \ | |
510 | "bdev=sda3\0" | |
0cde4b00 JL |
511 | |
512 | #define CONFIG_NFSBOOTCOMMAND \ | |
513 | "setenv bootargs root=/dev/nfs rw " \ | |
514 | "nfsroot=$serverip:$rootpath " \ | |
515 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
516 | "console=$consoledev,$baudrate $othbootargs;" \ | |
517 | "tftp $loadaddr $bootfile;" \ | |
50c03c8c KG |
518 | "tftp $fdtaddr $fdtfile;" \ |
519 | "bootm $loadaddr - $fdtaddr" | |
0cde4b00 | 520 | |
837f1ba0 | 521 | #define CONFIG_RAMBOOTCOMMAND \ |
0cde4b00 JL |
522 | "setenv bootargs root=/dev/ram rw " \ |
523 | "console=$consoledev,$baudrate $othbootargs;" \ | |
524 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
525 | "tftp $loadaddr $bootfile;" \ | |
50c03c8c KG |
526 | "tftp $fdtaddr $fdtfile;" \ |
527 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
0cde4b00 | 528 | |
837f1ba0 ES |
529 | #define CONFIG_BOOTCOMMAND \ |
530 | "setenv bootargs root=/dev/$bdev rw " \ | |
0cde4b00 JL |
531 | "console=$consoledev,$baudrate $othbootargs;" \ |
532 | "tftp $loadaddr $bootfile;" \ | |
50c03c8c KG |
533 | "tftp $fdtaddr $fdtfile;" \ |
534 | "bootm $loadaddr - $fdtaddr" | |
0cde4b00 JL |
535 | |
536 | #endif /* __CONFIG_H */ |