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Commit | Line | Data |
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0cde4b00 | 1 | /* |
7c57f3e8 | 2 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. |
0cde4b00 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
0cde4b00 JL |
5 | */ |
6 | ||
7 | /* | |
8 | * mpc8544ds board configuration file | |
9 | * | |
10 | */ | |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* High Level Configuration Options */ | |
15 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
16 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
0cde4b00 JL |
17 | #define CONFIG_MPC8544DS 1 |
18 | ||
2ae18241 WD |
19 | #ifndef CONFIG_SYS_TEXT_BASE |
20 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
21 | #endif | |
22 | ||
837f1ba0 | 23 | #define CONFIG_PCI1 1 /* PCI controller 1 */ |
b38eaec5 RD |
24 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ |
25 | #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ | |
26 | #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ | |
837f1ba0 | 27 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
842033e6 | 28 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
8ff3de61 | 29 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
0151cbac | 30 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
837f1ba0 | 31 | |
4bcae9c9 KG |
32 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
33 | ||
837f1ba0 | 34 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
0cde4b00 | 35 | #define CONFIG_ENV_OVERWRITE |
837f1ba0 | 36 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
0cde4b00 | 37 | |
0cde4b00 JL |
38 | #ifndef __ASSEMBLY__ |
39 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
40 | #endif | |
41 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
42 | ||
43 | /* | |
44 | * These can be toggled for performance analysis, otherwise use default. | |
45 | */ | |
837f1ba0 | 46 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
0cde4b00 | 47 | #define CONFIG_BTB /* toggle branch predition */ |
0cde4b00 JL |
48 | |
49 | /* | |
50 | * Only possible on E500 Version 2 or newer cores. | |
51 | */ | |
52 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
53 | ||
6d0f6bcf JCPV |
54 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
55 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
837f1ba0 | 56 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
0cde4b00 | 57 | |
e46fedfe TT |
58 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
59 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
0cde4b00 | 60 | |
1167a2fd | 61 | /* DDR Setup */ |
5614e71b | 62 | #define CONFIG_SYS_FSL_DDR2 |
1167a2fd KG |
63 | #undef CONFIG_FSL_DDR_INTERACTIVE |
64 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
65 | #define CONFIG_DDR_SPD | |
66 | ||
9b0ad1b1 | 67 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
1167a2fd KG |
68 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
69 | ||
6d0f6bcf JCPV |
70 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
71 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
1167a2fd KG |
72 | #define CONFIG_VERY_BIG_RAM |
73 | ||
74 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
75 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
76 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
0cde4b00 | 77 | |
1167a2fd | 78 | /* I2C addresses of SPD EEPROMs */ |
0cde4b00 JL |
79 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
80 | ||
1167a2fd | 81 | /* Make sure required options are set */ |
0cde4b00 JL |
82 | #ifndef CONFIG_SPD_EEPROM |
83 | #error ("CONFIG_SPD_EEPROM is required") | |
84 | #endif | |
85 | ||
86 | #undef CONFIG_CLOCKS_IN_MHZ | |
87 | ||
88 | /* | |
89 | * Memory map | |
90 | * | |
91 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
92 | * | |
93 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
94 | * | |
95 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
96 | * | |
97 | * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable | |
98 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
99 | * | |
100 | * Localbus cacheable | |
101 | * | |
102 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable | |
103 | * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 | |
104 | * | |
105 | * Localbus non-cacheable | |
106 | * | |
107 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable | |
108 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable | |
109 | * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable | |
110 | * | |
111 | */ | |
112 | ||
113 | /* | |
114 | * Local Bus Definitions | |
115 | */ | |
6d0f6bcf | 116 | #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ |
0cde4b00 | 117 | |
6d0f6bcf | 118 | #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ |
0cde4b00 | 119 | |
6d0f6bcf JCPV |
120 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 |
121 | #define CONFIG_SYS_BR1_PRELIM 0xfe801001 | |
0cde4b00 | 122 | |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
124 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
0cde4b00 | 125 | |
6d0f6bcf | 126 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
0cde4b00 | 127 | |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_FLASH_QUIET_TEST |
129 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
130 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
131 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
132 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
133 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
81e56e9a | 134 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
0cde4b00 | 135 | |
14d0a02a | 136 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
0cde4b00 | 137 | |
00b1883a | 138 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_FLASH_CFI |
140 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
0cde4b00 | 141 | |
6d0f6bcf | 142 | #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 |
0cde4b00 | 143 | |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ |
145 | #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ | |
0cde4b00 | 146 | |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ |
148 | #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ | |
0cde4b00 | 149 | |
7608d75f | 150 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
0cde4b00 JL |
151 | #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ |
152 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
153 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
154 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
155 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
156 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch | |
157 | * register */ | |
158 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
159 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
160 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
161 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
162 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
6bb5b412 KG |
163 | #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ |
164 | #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ | |
0cde4b00 JL |
165 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
166 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
167 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
168 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
5a8a163a | 169 | #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ |
6d0f6bcf | 170 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
5a8a163a AF |
171 | #define PIXIS_VSPEED2_TSEC1SER 0x2 |
172 | #define PIXIS_VSPEED2_TSEC3SER 0x1 | |
173 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 | |
174 | #define PIXIS_VCFGEN1_TSEC3SER 0x40 | |
bff188ba LY |
175 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) |
176 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) | |
0cde4b00 | 177 | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
179 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ | |
553f0982 | 180 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
1107014e | 181 | |
25ddd1fb | 182 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 183 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
0cde4b00 | 184 | |
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
186 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
0cde4b00 JL |
187 | |
188 | /* Serial Port - controlled on board with jumper J8 | |
189 | * open - index 2 | |
190 | * shorted - index 1 | |
191 | */ | |
192 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_NS16550_SERIAL |
194 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
195 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
0cde4b00 | 196 | |
6d0f6bcf | 197 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
0cde4b00 JL |
198 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
199 | ||
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
201 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
0cde4b00 | 202 | |
0cde4b00 | 203 | /* I2C */ |
00f792e0 HS |
204 | #define CONFIG_SYS_I2C |
205 | #define CONFIG_SYS_I2C_FSL | |
206 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
207 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
7f25fdc7 | 208 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 |
00f792e0 | 209 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } |
6d0f6bcf | 210 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
0cde4b00 JL |
211 | |
212 | /* | |
213 | * General PCI | |
214 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
215 | */ | |
5af0fdd8 | 216 | #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ |
6d0f6bcf | 217 | #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ |
5af0fdd8 | 218 | #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ |
6d0f6bcf | 219 | #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ |
0cde4b00 | 220 | |
5af0fdd8 | 221 | #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 |
10795f42 | 222 | #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 |
5af0fdd8 | 223 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 |
6d0f6bcf | 224 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 225 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 |
5f91ef6a | 226 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 |
228 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ | |
0cde4b00 | 229 | |
0cde4b00 | 230 | /* controller 2, Slot 1, tgtid 1, Base address 9000 */ |
64a1686a | 231 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
5af0fdd8 | 232 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 |
10795f42 | 233 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 |
5af0fdd8 | 234 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 |
6d0f6bcf | 235 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 236 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 |
5f91ef6a | 237 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
238 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 |
239 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
0cde4b00 JL |
240 | |
241 | /* controller 1, Slot 2,tgtid 2, Base address a000 */ | |
64a1686a | 242 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
5af0fdd8 | 243 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
10795f42 | 244 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
5af0fdd8 | 245 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
6d0f6bcf | 246 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ |
aca5f018 | 247 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 |
5f91ef6a | 248 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 |
250 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
0cde4b00 JL |
251 | |
252 | /* controller 3, direct to uli, tgtid 3, Base address b000 */ | |
64a1686a | 253 | #define CONFIG_SYS_PCIE3_NAME "ULI" |
5af0fdd8 | 254 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 |
10795f42 | 255 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 |
5af0fdd8 | 256 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 |
6d0f6bcf | 257 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ |
aca5f018 | 258 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ |
5f91ef6a | 259 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ |
261 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ | |
5af0fdd8 | 262 | #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 |
10795f42 | 263 | #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 |
5af0fdd8 | 264 | #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 |
6d0f6bcf | 265 | #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ |
0cde4b00 JL |
266 | |
267 | #if defined(CONFIG_PCI) | |
268 | ||
630d9bfc | 269 | /*PCIE video card used*/ |
aca5f018 | 270 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT |
630d9bfc KG |
271 | |
272 | /*PCI video card used*/ | |
aca5f018 | 273 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ |
630d9bfc KG |
274 | |
275 | /* video */ | |
630d9bfc KG |
276 | |
277 | #if defined(CONFIG_VIDEO) | |
278 | #define CONFIG_BIOSEMU | |
630d9bfc KG |
279 | #define CONFIG_ATI_RADEON_FB |
280 | #define CONFIG_VIDEO_LOGO | |
6d0f6bcf | 281 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
630d9bfc KG |
282 | #endif |
283 | ||
0cde4b00 JL |
284 | #undef CONFIG_EEPRO100 |
285 | #undef CONFIG_TULIP | |
0cde4b00 | 286 | |
0cde4b00 | 287 | #ifndef CONFIG_PCI_PNP |
5f91ef6a KG |
288 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS |
289 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS | |
0cde4b00 JL |
290 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
291 | #endif | |
292 | ||
293 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
294 | #define CONFIG_DOS_PARTITION | |
295 | #define CONFIG_SCSI_AHCI | |
296 | ||
297 | #ifdef CONFIG_SCSI_AHCI | |
344ca0b4 | 298 | #define CONFIG_LIBATA |
0cde4b00 | 299 | #define CONFIG_SATA_ULI5288 |
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
301 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
302 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
303 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
0cde4b00 JL |
304 | #endif /* SCSCI */ |
305 | ||
306 | #endif /* CONFIG_PCI */ | |
307 | ||
0cde4b00 JL |
308 | #if defined(CONFIG_TSEC_ENET) |
309 | ||
0cde4b00 JL |
310 | #define CONFIG_MII 1 /* MII PHY management */ |
311 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
255a3577 KP |
312 | #define CONFIG_TSEC1 1 |
313 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
314 | #define CONFIG_TSEC3 1 | |
315 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
837f1ba0 | 316 | |
bff188ba | 317 | #define CONFIG_PIXIS_SGMII_CMD |
652f7c2e AF |
318 | #define CONFIG_FSL_SGMII_RISER 1 |
319 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
320 | ||
0cde4b00 JL |
321 | #define TSEC1_PHY_ADDR 0 |
322 | #define TSEC3_PHY_ADDR 1 | |
323 | ||
3a79013e AF |
324 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
325 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
326 | ||
0cde4b00 JL |
327 | #define TSEC1_PHYIDX 0 |
328 | #define TSEC3_PHYIDX 0 | |
329 | ||
330 | #define CONFIG_ETHPRIME "eTSEC1" | |
331 | ||
332 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
0cde4b00 JL |
333 | #endif /* CONFIG_TSEC_ENET */ |
334 | ||
335 | /* | |
336 | * Environment | |
337 | */ | |
5a1aceb0 | 338 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 339 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
0e8d1586 | 340 | #define CONFIG_ENV_ADDR 0xfff80000 |
0cde4b00 | 341 | #else |
6d0f6bcf | 342 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) |
0cde4b00 | 343 | #endif |
0e8d1586 JCPV |
344 | #define CONFIG_ENV_SIZE 0x2000 |
345 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ | |
0cde4b00 JL |
346 | |
347 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 348 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
0cde4b00 | 349 | |
659e2f67 JL |
350 | /* |
351 | * BOOTP options | |
352 | */ | |
353 | #define CONFIG_BOOTP_BOOTFILESIZE | |
354 | #define CONFIG_BOOTP_BOOTPATH | |
355 | #define CONFIG_BOOTP_GATEWAY | |
356 | #define CONFIG_BOOTP_HOSTNAME | |
357 | ||
2835e518 JL |
358 | /* |
359 | * Command line configuration. | |
360 | */ | |
1c9aa76b | 361 | #define CONFIG_CMD_IRQ |
199e262e | 362 | #define CONFIG_CMD_REGINFO |
2835e518 | 363 | |
0cde4b00 | 364 | #if defined(CONFIG_PCI) |
2835e518 | 365 | #define CONFIG_CMD_PCI |
c649e3c9 | 366 | #define CONFIG_SCSI |
0cde4b00 | 367 | #endif |
2835e518 | 368 | |
86a194b7 HJ |
369 | /* |
370 | * USB | |
371 | */ | |
372 | #define CONFIG_USB_EHCI | |
373 | ||
374 | #ifdef CONFIG_USB_EHCI | |
86a194b7 HJ |
375 | #define CONFIG_USB_EHCI_PCI |
376 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
86a194b7 HJ |
377 | #define CONFIG_PCI_EHCI_DEVICE 0 |
378 | #endif | |
0cde4b00 JL |
379 | |
380 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
381 | ||
382 | /* | |
383 | * Miscellaneous configurable options | |
384 | */ | |
6d0f6bcf | 385 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
386 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
387 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf | 388 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
2835e518 | 389 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 390 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
0cde4b00 | 391 | #else |
6d0f6bcf | 392 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
0cde4b00 | 393 | #endif |
6d0f6bcf JCPV |
394 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
395 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
396 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
0cde4b00 JL |
397 | |
398 | /* | |
399 | * For booting Linux, the board info and command line data | |
a832ac41 | 400 | * have to be in the first 64 MB of memory, since this is |
0cde4b00 JL |
401 | * the maximum mapped by the Linux kernel during initialization. |
402 | */ | |
a832ac41 KG |
403 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
404 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
0cde4b00 | 405 | |
2835e518 | 406 | #if defined(CONFIG_CMD_KGDB) |
0cde4b00 | 407 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
0cde4b00 JL |
408 | #endif |
409 | ||
410 | /* | |
411 | * Environment Configuration | |
412 | */ | |
413 | ||
414 | /* The mac addresses for all ethernet interface */ | |
415 | #if defined(CONFIG_TSEC_ENET) | |
ea5877e3 | 416 | #define CONFIG_HAS_ETH0 |
0cde4b00 | 417 | #define CONFIG_HAS_ETH1 |
0cde4b00 JL |
418 | #endif |
419 | ||
420 | #define CONFIG_IPADDR 192.168.1.251 | |
421 | ||
422 | #define CONFIG_HOSTNAME 8544ds_unknown | |
8b3637c6 | 423 | #define CONFIG_ROOTPATH "/nfs/mpc85xx" |
b3f44c21 | 424 | #define CONFIG_BOOTFILE "8544ds/uImage.uboot" |
837f1ba0 | 425 | #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ |
0cde4b00 | 426 | |
50c03c8c KG |
427 | #define CONFIG_SERVERIP 192.168.1.1 |
428 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
0cde4b00 JL |
429 | #define CONFIG_NETMASK 255.255.0.0 |
430 | ||
431 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ | |
432 | ||
837f1ba0 | 433 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
0cde4b00 JL |
434 | |
435 | #define CONFIG_BAUDRATE 115200 | |
436 | ||
837f1ba0 | 437 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d MV |
438 | "netdev=eth0\0" \ |
439 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
440 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
441 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
442 | " +$filesize; " \ | |
443 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
444 | " +$filesize; " \ | |
445 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
446 | " $filesize; " \ | |
447 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
448 | " +$filesize; " \ | |
449 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
450 | " $filesize\0" \ | |
451 | "consoledev=ttyS0\0" \ | |
452 | "ramdiskaddr=2000000\0" \ | |
453 | "ramdiskfile=8544ds/ramdisk.uboot\0" \ | |
b24a4f62 | 454 | "fdtaddr=1e00000\0" \ |
5368c55d MV |
455 | "fdtfile=8544ds/mpc8544ds.dtb\0" \ |
456 | "bdev=sda3\0" | |
0cde4b00 JL |
457 | |
458 | #define CONFIG_NFSBOOTCOMMAND \ | |
459 | "setenv bootargs root=/dev/nfs rw " \ | |
460 | "nfsroot=$serverip:$rootpath " \ | |
461 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
462 | "console=$consoledev,$baudrate $othbootargs;" \ | |
463 | "tftp $loadaddr $bootfile;" \ | |
50c03c8c KG |
464 | "tftp $fdtaddr $fdtfile;" \ |
465 | "bootm $loadaddr - $fdtaddr" | |
0cde4b00 | 466 | |
837f1ba0 | 467 | #define CONFIG_RAMBOOTCOMMAND \ |
0cde4b00 JL |
468 | "setenv bootargs root=/dev/ram rw " \ |
469 | "console=$consoledev,$baudrate $othbootargs;" \ | |
470 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
471 | "tftp $loadaddr $bootfile;" \ | |
50c03c8c KG |
472 | "tftp $fdtaddr $fdtfile;" \ |
473 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
0cde4b00 | 474 | |
837f1ba0 ES |
475 | #define CONFIG_BOOTCOMMAND \ |
476 | "setenv bootargs root=/dev/$bdev rw " \ | |
0cde4b00 JL |
477 | "console=$consoledev,$baudrate $othbootargs;" \ |
478 | "tftp $loadaddr $bootfile;" \ | |
50c03c8c KG |
479 | "tftp $fdtaddr $fdtfile;" \ |
480 | "bootm $loadaddr - $fdtaddr" | |
0cde4b00 JL |
481 | |
482 | #endif /* __CONFIG_H */ |