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remove _IO_BASE and KSEG1ADDR from board configuration files
[people/ms/u-boot.git] / include / configs / MPC8544DS.h
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1/*
2 * Copyright 2007 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8544ds board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/* High Level Configuration Options */
31#define CONFIG_BOOKE 1 /* BOOKE */
32#define CONFIG_E500 1 /* BOOKE e500 family */
33#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
34#define CONFIG_MPC8544 1
35#define CONFIG_MPC8544DS 1
36
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37#define CONFIG_PCI 1 /* Enable PCI/PCIE */
38#define CONFIG_PCI1 1 /* PCI controller 1 */
39#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
40#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
41#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
42#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
8ff3de61 43#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
0151cbac 44#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
837f1ba0 45
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46#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
47
837f1ba0 48#define CONFIG_TSEC_ENET /* tsec ethernet support */
0cde4b00 49#define CONFIG_ENV_OVERWRITE
837f1ba0 50#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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51
52/*
53 * When initializing flash, if we cannot find the manufacturer ID,
54 * assume this is the AMD flash associated with the CDS board.
55 * This allows booting from a promjet.
56 */
57#define CONFIG_ASSUME_AMD_FLASH
58
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59#ifndef __ASSEMBLY__
60extern unsigned long get_board_sys_clk(unsigned long dummy);
61#endif
62#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
63
64/*
65 * These can be toggled for performance analysis, otherwise use default.
66 */
837f1ba0 67#define CONFIG_L2_CACHE /* toggle L2 cache */
0cde4b00 68#define CONFIG_BTB /* toggle branch predition */
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69
70/*
71 * Only possible on E500 Version 2 or newer cores.
72 */
73#define CONFIG_ENABLE_36BIT_PHYS 1
74
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75#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
76#define CONFIG_SYS_MEMTEST_END 0x00400000
837f1ba0 77#define CONFIG_PANIC_HANG /* do not reset board on panic */
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78
79/*
80 * Base addresses -- Note these are effective addresses where the
81 * actual resources get mapped (not physical addresses)
82 */
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83#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
84#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
85#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
86#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
0cde4b00 87
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88#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
89#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
90#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
91#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
0cde4b00 92
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93/* DDR Setup */
94#define CONFIG_FSL_DDR2
95#undef CONFIG_FSL_DDR_INTERACTIVE
96#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
97#define CONFIG_DDR_SPD
98
9b0ad1b1 99#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
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100#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
101
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102#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
103#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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104#define CONFIG_VERY_BIG_RAM
105
106#define CONFIG_NUM_DDR_CONTROLLERS 1
107#define CONFIG_DIMM_SLOTS_PER_CTLR 1
108#define CONFIG_CHIP_SELECTS_PER_CTRL 2
0cde4b00 109
1167a2fd 110/* I2C addresses of SPD EEPROMs */
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111#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
112
1167a2fd 113/* Make sure required options are set */
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114#ifndef CONFIG_SPD_EEPROM
115#error ("CONFIG_SPD_EEPROM is required")
116#endif
117
118#undef CONFIG_CLOCKS_IN_MHZ
119
120/*
121 * Memory map
122 *
123 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
124 *
125 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
126 *
127 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
128 *
129 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
130 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
131 *
132 * Localbus cacheable
133 *
134 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
135 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
136 *
137 * Localbus non-cacheable
138 *
139 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
140 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
141 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
142 *
143 */
144
145/*
146 * Local Bus Definitions
147 */
6d0f6bcf 148#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
0cde4b00 149
6d0f6bcf 150#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
0cde4b00 151
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152#define CONFIG_SYS_BR0_PRELIM 0xff801001
153#define CONFIG_SYS_BR1_PRELIM 0xfe801001
0cde4b00 154
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155#define CONFIG_SYS_OR0_PRELIM 0xff806e65
156#define CONFIG_SYS_OR1_PRELIM 0xff806e65
0cde4b00 157
6d0f6bcf 158#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
0cde4b00 159
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160#define CONFIG_SYS_FLASH_QUIET_TEST
161#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
162#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
163#undef CONFIG_SYS_FLASH_CHECKSUM
164#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
165#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
81e56e9a 166#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
0cde4b00 167
6d0f6bcf 168#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
0cde4b00 169
00b1883a 170#define CONFIG_FLASH_CFI_DRIVER
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171#define CONFIG_SYS_FLASH_CFI
172#define CONFIG_SYS_FLASH_EMPTY_INFO
0cde4b00 173
6d0f6bcf 174#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
0cde4b00 175
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176#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
177#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
0cde4b00 178
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179#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
180#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
0cde4b00 181
7608d75f 182#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
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183#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
184#define PIXIS_ID 0x0 /* Board ID at offset 0 */
185#define PIXIS_VER 0x1 /* Board version at offset 1 */
186#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
187#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
188#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
189 * register */
190#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
191#define PIXIS_VCTL 0x10 /* VELA Control Register */
192#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
193#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
194#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
195#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
196#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
197#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
198#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
5a8a163a 199#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
6d0f6bcf 200#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
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201#define PIXIS_VSPEED2_TSEC1SER 0x2
202#define PIXIS_VSPEED2_TSEC3SER 0x1
203#define PIXIS_VCFGEN1_TSEC1SER 0x20
204#define PIXIS_VCFGEN1_TSEC3SER 0x40
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205#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
206#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
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207
208
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209#define CONFIG_SYS_INIT_RAM_LOCK 1
210#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
211#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
1107014e 212
0cde4b00 213
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214#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
215#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
216#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0cde4b00 217
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218#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
219#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
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220
221/* Serial Port - controlled on board with jumper J8
222 * open - index 2
223 * shorted - index 1
224 */
225#define CONFIG_CONS_INDEX 1
226#undef CONFIG_SERIAL_SOFTWARE_FIFO
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227#define CONFIG_SYS_NS16550
228#define CONFIG_SYS_NS16550_SERIAL
229#define CONFIG_SYS_NS16550_REG_SIZE 1
230#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
0cde4b00 231
6d0f6bcf 232#define CONFIG_SYS_BAUDRATE_TABLE \
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233 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
234
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235#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
236#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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237
238/* Use the HUSH parser */
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239#define CONFIG_SYS_HUSH_PARSER
240#ifdef CONFIG_SYS_HUSH_PARSER
241#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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242#endif
243
244/* pass open firmware flat tree */
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245#define CONFIG_OF_LIBFDT 1
246#define CONFIG_OF_BOARD_SETUP 1
247#define CONFIG_OF_STDOUT_VIA_ALIAS 1
0cde4b00 248
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249#define CONFIG_SYS_64BIT_STRTOUL 1
250#define CONFIG_SYS_64BIT_VSPRINTF 1
1167a2fd 251
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252/* I2C */
253#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
254#define CONFIG_HARD_I2C /* I2C with hardware support */
255#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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256#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
257#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
258#define CONFIG_SYS_I2C_SLAVE 0x7F
259#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
260#define CONFIG_SYS_I2C_OFFSET 0x3100
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261
262/*
263 * General PCI
264 * Memory space is mapped 1-1, but I/O space must start from 0.
265 */
5af0fdd8 266#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
6d0f6bcf 267#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
5af0fdd8 268#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
6d0f6bcf 269#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
0cde4b00 270
5af0fdd8 271#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
10795f42 272#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
5af0fdd8 273#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
6d0f6bcf 274#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018 275#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
5f91ef6a 276#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
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277#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
278#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
0cde4b00 279
0cde4b00 280/* controller 2, Slot 1, tgtid 1, Base address 9000 */
5af0fdd8 281#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
10795f42 282#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
5af0fdd8 283#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
6d0f6bcf 284#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
aca5f018 285#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
5f91ef6a 286#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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287#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
288#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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289
290/* controller 1, Slot 2,tgtid 2, Base address a000 */
5af0fdd8 291#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
10795f42 292#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
5af0fdd8 293#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
6d0f6bcf 294#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
aca5f018 295#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
5f91ef6a 296#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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297#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
298#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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299
300/* controller 3, direct to uli, tgtid 3, Base address b000 */
5af0fdd8 301#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
10795f42 302#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
5af0fdd8 303#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
6d0f6bcf 304#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
aca5f018 305#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
5f91ef6a 306#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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307#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
308#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
5af0fdd8 309#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
10795f42 310#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
5af0fdd8 311#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
6d0f6bcf 312#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
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313
314#if defined(CONFIG_PCI)
315
630d9bfc 316/*PCIE video card used*/
aca5f018 317#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
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318
319/*PCI video card used*/
aca5f018 320/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
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321
322/* video */
323#define CONFIG_VIDEO
324
325#if defined(CONFIG_VIDEO)
326#define CONFIG_BIOSEMU
327#define CONFIG_CFB_CONSOLE
328#define CONFIG_VIDEO_SW_CURSOR
329#define CONFIG_VGA_AS_SINGLE_DEVICE
330#define CONFIG_ATI_RADEON_FB
331#define CONFIG_VIDEO_LOGO
332/*#define CONFIG_CONSOLE_CURSOR*/
6d0f6bcf 333#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
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334#endif
335
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336#define CONFIG_NET_MULTI
337#define CONFIG_PCI_PNP /* do pci plug-and-play */
338
339#undef CONFIG_EEPRO100
340#undef CONFIG_TULIP
341#define CONFIG_RTL8139
342
0cde4b00 343#ifndef CONFIG_PCI_PNP
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344 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
345 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
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346 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
347#endif
348
349#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
350#define CONFIG_DOS_PARTITION
351#define CONFIG_SCSI_AHCI
352
353#ifdef CONFIG_SCSI_AHCI
354#define CONFIG_SATA_ULI5288
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355#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
356#define CONFIG_SYS_SCSI_MAX_LUN 1
357#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
358#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
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359#endif /* SCSCI */
360
361#endif /* CONFIG_PCI */
362
363
364#if defined(CONFIG_TSEC_ENET)
365
366#ifndef CONFIG_NET_MULTI
837f1ba0 367#define CONFIG_NET_MULTI 1
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368#endif
369
370#define CONFIG_MII 1 /* MII PHY management */
371#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
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372#define CONFIG_TSEC1 1
373#define CONFIG_TSEC1_NAME "eTSEC1"
374#define CONFIG_TSEC3 1
375#define CONFIG_TSEC3_NAME "eTSEC3"
837f1ba0 376
bff188ba 377#define CONFIG_PIXIS_SGMII_CMD
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378#define CONFIG_FSL_SGMII_RISER 1
379#define SGMII_RISER_PHY_OFFSET 0x1c
380
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381#define TSEC1_PHY_ADDR 0
382#define TSEC3_PHY_ADDR 1
383
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384#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
385#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
386
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387#define TSEC1_PHYIDX 0
388#define TSEC3_PHYIDX 0
389
390#define CONFIG_ETHPRIME "eTSEC1"
391
392#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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393#endif /* CONFIG_TSEC_ENET */
394
395/*
396 * Environment
397 */
5a1aceb0 398#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf 399#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
0e8d1586 400#define CONFIG_ENV_ADDR 0xfff80000
0cde4b00 401#else
6d0f6bcf 402#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
0cde4b00 403#endif
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404#define CONFIG_ENV_SIZE 0x2000
405#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
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406
407#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf 408#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
0cde4b00 409
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410/*
411 * BOOTP options
412 */
413#define CONFIG_BOOTP_BOOTFILESIZE
414#define CONFIG_BOOTP_BOOTPATH
415#define CONFIG_BOOTP_GATEWAY
416#define CONFIG_BOOTP_HOSTNAME
417
418
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419/*
420 * Command line configuration.
421 */
422#include <config_cmd_default.h>
423
424#define CONFIG_CMD_PING
425#define CONFIG_CMD_I2C
426#define CONFIG_CMD_MII
82ac8c97 427#define CONFIG_CMD_ELF
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428#define CONFIG_CMD_IRQ
429#define CONFIG_CMD_SETEXPR
2835e518 430
0cde4b00 431#if defined(CONFIG_PCI)
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432 #define CONFIG_CMD_PCI
433 #define CONFIG_CMD_BEDBUG
434 #define CONFIG_CMD_NET
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435 #define CONFIG_CMD_SCSI
436 #define CONFIG_CMD_EXT2
0cde4b00 437#endif
2835e518 438
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439
440#undef CONFIG_WATCHDOG /* watchdog disabled */
441
442/*
443 * Miscellaneous configurable options
444 */
6d0f6bcf 445#define CONFIG_SYS_LONGHELP /* undef to save memory */
50c03c8c 446#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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447#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
448#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
2835e518 449#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 450#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
0cde4b00 451#else
6d0f6bcf 452#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0cde4b00 453#endif
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454#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
455#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
456#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
457#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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458
459/*
460 * For booting Linux, the board info and command line data
461 * have to be in the first 8 MB of memory, since this is
462 * the maximum mapped by the Linux kernel during initialization.
463 */
6d0f6bcf 464#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
0cde4b00 465
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466/*
467 * Internal Definitions
468 *
469 * Boot Flags
470 */
471#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
472#define BOOTFLAG_WARM 0x02 /* Software reboot */
473
2835e518 474#if defined(CONFIG_CMD_KGDB)
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475#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
476#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
477#endif
478
479/*
480 * Environment Configuration
481 */
482
483/* The mac addresses for all ethernet interface */
484#if defined(CONFIG_TSEC_ENET)
ea5877e3 485#define CONFIG_HAS_ETH0
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486#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
487#define CONFIG_HAS_ETH1
488#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
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489#endif
490
491#define CONFIG_IPADDR 192.168.1.251
492
493#define CONFIG_HOSTNAME 8544ds_unknown
494#define CONFIG_ROOTPATH /nfs/mpc85xx
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495#define CONFIG_BOOTFILE 8544ds/uImage.uboot
496#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
0cde4b00 497
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498#define CONFIG_SERVERIP 192.168.1.1
499#define CONFIG_GATEWAYIP 192.168.1.1
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500#define CONFIG_NETMASK 255.255.0.0
501
502#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
503
504#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
837f1ba0 505#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
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506
507#define CONFIG_BAUDRATE 115200
508
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509#define CONFIG_EXTRA_ENV_SETTINGS \
510 "netdev=eth0\0" \
511 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
512 "tftpflash=tftpboot $loadaddr $uboot; " \
513 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
514 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
515 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
516 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
517 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
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518 "consoledev=ttyS0\0" \
519 "ramdiskaddr=2000000\0" \
837f1ba0 520 "ramdiskfile=8544ds/ramdisk.uboot\0" \
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521 "fdtaddr=c00000\0" \
522 "fdtfile=8544ds/mpc8544ds.dtb\0" \
523 "bdev=sda3\0"
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524
525#define CONFIG_NFSBOOTCOMMAND \
526 "setenv bootargs root=/dev/nfs rw " \
527 "nfsroot=$serverip:$rootpath " \
528 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
529 "console=$consoledev,$baudrate $othbootargs;" \
530 "tftp $loadaddr $bootfile;" \
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531 "tftp $fdtaddr $fdtfile;" \
532 "bootm $loadaddr - $fdtaddr"
0cde4b00 533
837f1ba0 534#define CONFIG_RAMBOOTCOMMAND \
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535 "setenv bootargs root=/dev/ram rw " \
536 "console=$consoledev,$baudrate $othbootargs;" \
537 "tftp $ramdiskaddr $ramdiskfile;" \
538 "tftp $loadaddr $bootfile;" \
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539 "tftp $fdtaddr $fdtfile;" \
540 "bootm $loadaddr $ramdiskaddr $fdtaddr"
0cde4b00 541
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542#define CONFIG_BOOTCOMMAND \
543 "setenv bootargs root=/dev/$bdev rw " \
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544 "console=$consoledev,$baudrate $othbootargs;" \
545 "tftp $loadaddr $bootfile;" \
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546 "tftp $fdtaddr $fdtfile;" \
547 "bootm $loadaddr - $fdtaddr"
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548
549#endif /* __CONFIG_H */