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Commit | Line | Data |
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0cde4b00 | 1 | /* |
7c57f3e8 | 2 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. |
0cde4b00 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
0cde4b00 JL |
5 | */ |
6 | ||
7 | /* | |
8 | * mpc8544ds board configuration file | |
9 | * | |
10 | */ | |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
9ae14ca2 YS |
14 | #define CONFIG_DISPLAY_BOARDINFO |
15 | ||
0cde4b00 JL |
16 | /* High Level Configuration Options */ |
17 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
18 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
0cde4b00 JL |
19 | #define CONFIG_MPC8544 1 |
20 | #define CONFIG_MPC8544DS 1 | |
21 | ||
2ae18241 WD |
22 | #ifndef CONFIG_SYS_TEXT_BASE |
23 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
24 | #endif | |
25 | ||
837f1ba0 ES |
26 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
27 | #define CONFIG_PCI1 1 /* PCI controller 1 */ | |
28 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
29 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
30 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
31 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
842033e6 | 32 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
8ff3de61 | 33 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
0151cbac | 34 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
837f1ba0 | 35 | |
4bcae9c9 KG |
36 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
37 | ||
837f1ba0 | 38 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
0cde4b00 | 39 | #define CONFIG_ENV_OVERWRITE |
837f1ba0 | 40 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
0cde4b00 | 41 | |
0cde4b00 JL |
42 | #ifndef __ASSEMBLY__ |
43 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
44 | #endif | |
45 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
46 | ||
47 | /* | |
48 | * These can be toggled for performance analysis, otherwise use default. | |
49 | */ | |
837f1ba0 | 50 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
0cde4b00 | 51 | #define CONFIG_BTB /* toggle branch predition */ |
0cde4b00 JL |
52 | |
53 | /* | |
54 | * Only possible on E500 Version 2 or newer cores. | |
55 | */ | |
56 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
57 | ||
6d0f6bcf JCPV |
58 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
59 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
837f1ba0 | 60 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
0cde4b00 | 61 | |
e46fedfe TT |
62 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
63 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
0cde4b00 | 64 | |
1167a2fd | 65 | /* DDR Setup */ |
5614e71b | 66 | #define CONFIG_SYS_FSL_DDR2 |
1167a2fd KG |
67 | #undef CONFIG_FSL_DDR_INTERACTIVE |
68 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
69 | #define CONFIG_DDR_SPD | |
70 | ||
9b0ad1b1 | 71 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
1167a2fd KG |
72 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
73 | ||
6d0f6bcf JCPV |
74 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
75 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
1167a2fd KG |
76 | #define CONFIG_VERY_BIG_RAM |
77 | ||
78 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
79 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
80 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
0cde4b00 | 81 | |
1167a2fd | 82 | /* I2C addresses of SPD EEPROMs */ |
0cde4b00 JL |
83 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
84 | ||
1167a2fd | 85 | /* Make sure required options are set */ |
0cde4b00 JL |
86 | #ifndef CONFIG_SPD_EEPROM |
87 | #error ("CONFIG_SPD_EEPROM is required") | |
88 | #endif | |
89 | ||
90 | #undef CONFIG_CLOCKS_IN_MHZ | |
91 | ||
92 | /* | |
93 | * Memory map | |
94 | * | |
95 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
96 | * | |
97 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
98 | * | |
99 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
100 | * | |
101 | * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable | |
102 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
103 | * | |
104 | * Localbus cacheable | |
105 | * | |
106 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable | |
107 | * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 | |
108 | * | |
109 | * Localbus non-cacheable | |
110 | * | |
111 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable | |
112 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable | |
113 | * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable | |
114 | * | |
115 | */ | |
116 | ||
117 | /* | |
118 | * Local Bus Definitions | |
119 | */ | |
6d0f6bcf | 120 | #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ |
0cde4b00 | 121 | |
6d0f6bcf | 122 | #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ |
0cde4b00 | 123 | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 |
125 | #define CONFIG_SYS_BR1_PRELIM 0xfe801001 | |
0cde4b00 | 126 | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
128 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
0cde4b00 | 129 | |
6d0f6bcf | 130 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
0cde4b00 | 131 | |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_FLASH_QUIET_TEST |
133 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
134 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
135 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
136 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
137 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
81e56e9a | 138 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
0cde4b00 | 139 | |
14d0a02a | 140 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
0cde4b00 | 141 | |
00b1883a | 142 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
143 | #define CONFIG_SYS_FLASH_CFI |
144 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
0cde4b00 | 145 | |
6d0f6bcf | 146 | #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 |
0cde4b00 | 147 | |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ |
149 | #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ | |
0cde4b00 | 150 | |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ |
152 | #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ | |
0cde4b00 | 153 | |
7608d75f | 154 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
0cde4b00 JL |
155 | #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ |
156 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
157 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
158 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
159 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
160 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch | |
161 | * register */ | |
162 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
163 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
164 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
165 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
166 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
6bb5b412 KG |
167 | #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ |
168 | #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ | |
0cde4b00 JL |
169 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
170 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
171 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
172 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
5a8a163a | 173 | #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ |
6d0f6bcf | 174 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
5a8a163a AF |
175 | #define PIXIS_VSPEED2_TSEC1SER 0x2 |
176 | #define PIXIS_VSPEED2_TSEC3SER 0x1 | |
177 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 | |
178 | #define PIXIS_VCFGEN1_TSEC3SER 0x40 | |
bff188ba LY |
179 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) |
180 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) | |
0cde4b00 JL |
181 | |
182 | ||
6d0f6bcf JCPV |
183 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
184 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ | |
553f0982 | 185 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
1107014e | 186 | |
0cde4b00 | 187 | |
25ddd1fb | 188 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 189 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
0cde4b00 | 190 | |
6d0f6bcf JCPV |
191 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
192 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
0cde4b00 JL |
193 | |
194 | /* Serial Port - controlled on board with jumper J8 | |
195 | * open - index 2 | |
196 | * shorted - index 1 | |
197 | */ | |
198 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
199 | #define CONFIG_SYS_NS16550_SERIAL |
200 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
201 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
0cde4b00 | 202 | |
6d0f6bcf | 203 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
0cde4b00 JL |
204 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
205 | ||
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
207 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
0cde4b00 JL |
208 | |
209 | /* Use the HUSH parser */ | |
6d0f6bcf | 210 | #define CONFIG_SYS_HUSH_PARSER |
0cde4b00 JL |
211 | |
212 | /* pass open firmware flat tree */ | |
addce57e KG |
213 | #define CONFIG_OF_LIBFDT 1 |
214 | #define CONFIG_OF_BOARD_SETUP 1 | |
215 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
0cde4b00 JL |
216 | |
217 | /* I2C */ | |
00f792e0 HS |
218 | #define CONFIG_SYS_I2C |
219 | #define CONFIG_SYS_I2C_FSL | |
220 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
221 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
222 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
223 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
6d0f6bcf | 224 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
0cde4b00 JL |
225 | |
226 | /* | |
227 | * General PCI | |
228 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
229 | */ | |
5af0fdd8 | 230 | #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ |
6d0f6bcf | 231 | #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ |
5af0fdd8 | 232 | #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ |
6d0f6bcf | 233 | #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ |
0cde4b00 | 234 | |
5af0fdd8 | 235 | #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 |
10795f42 | 236 | #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 |
5af0fdd8 | 237 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 |
6d0f6bcf | 238 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 239 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 |
5f91ef6a | 240 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 |
242 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ | |
0cde4b00 | 243 | |
0cde4b00 | 244 | /* controller 2, Slot 1, tgtid 1, Base address 9000 */ |
64a1686a | 245 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
5af0fdd8 | 246 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 |
10795f42 | 247 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 |
5af0fdd8 | 248 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 |
6d0f6bcf | 249 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 250 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 |
5f91ef6a | 251 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
252 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 |
253 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
0cde4b00 JL |
254 | |
255 | /* controller 1, Slot 2,tgtid 2, Base address a000 */ | |
64a1686a | 256 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
5af0fdd8 | 257 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
10795f42 | 258 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
5af0fdd8 | 259 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
6d0f6bcf | 260 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ |
aca5f018 | 261 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 |
5f91ef6a | 262 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
263 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 |
264 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
0cde4b00 JL |
265 | |
266 | /* controller 3, direct to uli, tgtid 3, Base address b000 */ | |
64a1686a | 267 | #define CONFIG_SYS_PCIE3_NAME "ULI" |
5af0fdd8 | 268 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 |
10795f42 | 269 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 |
5af0fdd8 | 270 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 |
6d0f6bcf | 271 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ |
aca5f018 | 272 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ |
5f91ef6a | 273 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ |
275 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ | |
5af0fdd8 | 276 | #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 |
10795f42 | 277 | #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 |
5af0fdd8 | 278 | #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 |
6d0f6bcf | 279 | #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ |
0cde4b00 JL |
280 | |
281 | #if defined(CONFIG_PCI) | |
282 | ||
630d9bfc | 283 | /*PCIE video card used*/ |
aca5f018 | 284 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT |
630d9bfc KG |
285 | |
286 | /*PCI video card used*/ | |
aca5f018 | 287 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ |
630d9bfc KG |
288 | |
289 | /* video */ | |
290 | #define CONFIG_VIDEO | |
291 | ||
292 | #if defined(CONFIG_VIDEO) | |
293 | #define CONFIG_BIOSEMU | |
294 | #define CONFIG_CFB_CONSOLE | |
295 | #define CONFIG_VIDEO_SW_CURSOR | |
296 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
297 | #define CONFIG_ATI_RADEON_FB | |
298 | #define CONFIG_VIDEO_LOGO | |
6d0f6bcf | 299 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
630d9bfc KG |
300 | #endif |
301 | ||
0cde4b00 JL |
302 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
303 | ||
304 | #undef CONFIG_EEPRO100 | |
305 | #undef CONFIG_TULIP | |
306 | #define CONFIG_RTL8139 | |
307 | ||
0cde4b00 | 308 | #ifndef CONFIG_PCI_PNP |
5f91ef6a KG |
309 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS |
310 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS | |
0cde4b00 JL |
311 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
312 | #endif | |
313 | ||
314 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
315 | #define CONFIG_DOS_PARTITION | |
316 | #define CONFIG_SCSI_AHCI | |
317 | ||
318 | #ifdef CONFIG_SCSI_AHCI | |
344ca0b4 | 319 | #define CONFIG_LIBATA |
0cde4b00 | 320 | #define CONFIG_SATA_ULI5288 |
6d0f6bcf JCPV |
321 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
322 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
323 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
324 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
0cde4b00 JL |
325 | #endif /* SCSCI */ |
326 | ||
327 | #endif /* CONFIG_PCI */ | |
328 | ||
329 | ||
330 | #if defined(CONFIG_TSEC_ENET) | |
331 | ||
0cde4b00 JL |
332 | #define CONFIG_MII 1 /* MII PHY management */ |
333 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
255a3577 KP |
334 | #define CONFIG_TSEC1 1 |
335 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
336 | #define CONFIG_TSEC3 1 | |
337 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
837f1ba0 | 338 | |
bff188ba | 339 | #define CONFIG_PIXIS_SGMII_CMD |
652f7c2e AF |
340 | #define CONFIG_FSL_SGMII_RISER 1 |
341 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
342 | ||
0cde4b00 JL |
343 | #define TSEC1_PHY_ADDR 0 |
344 | #define TSEC3_PHY_ADDR 1 | |
345 | ||
3a79013e AF |
346 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
347 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
348 | ||
0cde4b00 JL |
349 | #define TSEC1_PHYIDX 0 |
350 | #define TSEC3_PHYIDX 0 | |
351 | ||
352 | #define CONFIG_ETHPRIME "eTSEC1" | |
353 | ||
354 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
0cde4b00 JL |
355 | #endif /* CONFIG_TSEC_ENET */ |
356 | ||
357 | /* | |
358 | * Environment | |
359 | */ | |
5a1aceb0 | 360 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 361 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
0e8d1586 | 362 | #define CONFIG_ENV_ADDR 0xfff80000 |
0cde4b00 | 363 | #else |
6d0f6bcf | 364 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) |
0cde4b00 | 365 | #endif |
0e8d1586 JCPV |
366 | #define CONFIG_ENV_SIZE 0x2000 |
367 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ | |
0cde4b00 JL |
368 | |
369 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 370 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
0cde4b00 | 371 | |
659e2f67 JL |
372 | /* |
373 | * BOOTP options | |
374 | */ | |
375 | #define CONFIG_BOOTP_BOOTFILESIZE | |
376 | #define CONFIG_BOOTP_BOOTPATH | |
377 | #define CONFIG_BOOTP_GATEWAY | |
378 | #define CONFIG_BOOTP_HOSTNAME | |
379 | ||
380 | ||
2835e518 JL |
381 | /* |
382 | * Command line configuration. | |
383 | */ | |
2835e518 JL |
384 | #define CONFIG_CMD_PING |
385 | #define CONFIG_CMD_I2C | |
386 | #define CONFIG_CMD_MII | |
1c9aa76b | 387 | #define CONFIG_CMD_IRQ |
199e262e | 388 | #define CONFIG_CMD_REGINFO |
2835e518 | 389 | |
0cde4b00 | 390 | #if defined(CONFIG_PCI) |
2835e518 | 391 | #define CONFIG_CMD_PCI |
837f1ba0 ES |
392 | #define CONFIG_CMD_SCSI |
393 | #define CONFIG_CMD_EXT2 | |
0cde4b00 | 394 | #endif |
2835e518 | 395 | |
86a194b7 HJ |
396 | /* |
397 | * USB | |
398 | */ | |
399 | #define CONFIG_USB_EHCI | |
400 | ||
401 | #ifdef CONFIG_USB_EHCI | |
402 | #define CONFIG_CMD_USB | |
403 | #define CONFIG_USB_EHCI_PCI | |
404 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
405 | #define CONFIG_USB_STORAGE | |
406 | #define CONFIG_PCI_EHCI_DEVICE 0 | |
407 | #endif | |
0cde4b00 JL |
408 | |
409 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
410 | ||
411 | /* | |
412 | * Miscellaneous configurable options | |
413 | */ | |
6d0f6bcf | 414 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
415 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
416 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf | 417 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
2835e518 | 418 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 419 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
0cde4b00 | 420 | #else |
6d0f6bcf | 421 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
0cde4b00 | 422 | #endif |
6d0f6bcf JCPV |
423 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
424 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
425 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
0cde4b00 JL |
426 | |
427 | /* | |
428 | * For booting Linux, the board info and command line data | |
a832ac41 | 429 | * have to be in the first 64 MB of memory, since this is |
0cde4b00 JL |
430 | * the maximum mapped by the Linux kernel during initialization. |
431 | */ | |
a832ac41 KG |
432 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
433 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
0cde4b00 | 434 | |
2835e518 | 435 | #if defined(CONFIG_CMD_KGDB) |
0cde4b00 | 436 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
0cde4b00 JL |
437 | #endif |
438 | ||
439 | /* | |
440 | * Environment Configuration | |
441 | */ | |
442 | ||
443 | /* The mac addresses for all ethernet interface */ | |
444 | #if defined(CONFIG_TSEC_ENET) | |
ea5877e3 | 445 | #define CONFIG_HAS_ETH0 |
0cde4b00 | 446 | #define CONFIG_HAS_ETH1 |
0cde4b00 JL |
447 | #endif |
448 | ||
449 | #define CONFIG_IPADDR 192.168.1.251 | |
450 | ||
451 | #define CONFIG_HOSTNAME 8544ds_unknown | |
8b3637c6 | 452 | #define CONFIG_ROOTPATH "/nfs/mpc85xx" |
b3f44c21 | 453 | #define CONFIG_BOOTFILE "8544ds/uImage.uboot" |
837f1ba0 | 454 | #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ |
0cde4b00 | 455 | |
50c03c8c KG |
456 | #define CONFIG_SERVERIP 192.168.1.1 |
457 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
0cde4b00 JL |
458 | #define CONFIG_NETMASK 255.255.0.0 |
459 | ||
460 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ | |
461 | ||
462 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
837f1ba0 | 463 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
0cde4b00 JL |
464 | |
465 | #define CONFIG_BAUDRATE 115200 | |
466 | ||
837f1ba0 | 467 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d MV |
468 | "netdev=eth0\0" \ |
469 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
470 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
471 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
472 | " +$filesize; " \ | |
473 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
474 | " +$filesize; " \ | |
475 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
476 | " $filesize; " \ | |
477 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
478 | " +$filesize; " \ | |
479 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
480 | " $filesize\0" \ | |
481 | "consoledev=ttyS0\0" \ | |
482 | "ramdiskaddr=2000000\0" \ | |
483 | "ramdiskfile=8544ds/ramdisk.uboot\0" \ | |
484 | "fdtaddr=c00000\0" \ | |
485 | "fdtfile=8544ds/mpc8544ds.dtb\0" \ | |
486 | "bdev=sda3\0" | |
0cde4b00 JL |
487 | |
488 | #define CONFIG_NFSBOOTCOMMAND \ | |
489 | "setenv bootargs root=/dev/nfs rw " \ | |
490 | "nfsroot=$serverip:$rootpath " \ | |
491 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
492 | "console=$consoledev,$baudrate $othbootargs;" \ | |
493 | "tftp $loadaddr $bootfile;" \ | |
50c03c8c KG |
494 | "tftp $fdtaddr $fdtfile;" \ |
495 | "bootm $loadaddr - $fdtaddr" | |
0cde4b00 | 496 | |
837f1ba0 | 497 | #define CONFIG_RAMBOOTCOMMAND \ |
0cde4b00 JL |
498 | "setenv bootargs root=/dev/ram rw " \ |
499 | "console=$consoledev,$baudrate $othbootargs;" \ | |
500 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
501 | "tftp $loadaddr $bootfile;" \ | |
50c03c8c KG |
502 | "tftp $fdtaddr $fdtfile;" \ |
503 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
0cde4b00 | 504 | |
837f1ba0 ES |
505 | #define CONFIG_BOOTCOMMAND \ |
506 | "setenv bootargs root=/dev/$bdev rw " \ | |
0cde4b00 JL |
507 | "console=$consoledev,$baudrate $othbootargs;" \ |
508 | "tftp $loadaddr $bootfile;" \ | |
50c03c8c KG |
509 | "tftp $fdtaddr $fdtfile;" \ |
510 | "bootm $loadaddr - $fdtaddr" | |
0cde4b00 JL |
511 | |
512 | #endif /* __CONFIG_H */ |