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1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * mpc8568mds board configuration file | |
25 | */ | |
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | /* High Level Configuration Options */ | |
30 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
31 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
32 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ | |
33 | #define CONFIG_MPC8568 1 /* MPC8568 specific */ | |
34 | #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ | |
35 | ||
36 | #undef CONFIG_PCI | |
37 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
38 | #define CONFIG_ENV_OVERWRITE | |
39 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
40 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ | |
41 | /*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */ | |
42 | ||
43 | /*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */ | |
44 | /*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ | |
45 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
46 | ||
47 | ||
48 | /* | |
49 | * When initializing flash, if we cannot find the manufacturer ID, | |
50 | * assume this is the AMD flash associated with the MDS board. | |
51 | * This allows booting from a promjet. | |
52 | */ | |
53 | #define CONFIG_ASSUME_AMD_FLASH | |
54 | ||
55 | #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ | |
56 | ||
57 | #ifndef __ASSEMBLY__ | |
58 | extern unsigned long get_clock_freq(void); | |
59 | #endif /*Replace a call to get_clock_freq (after it is implemented)*/ | |
60 | #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ | |
61 | ||
62 | /* | |
63 | * These can be toggled for performance analysis, otherwise use default. | |
64 | */ | |
65 | /*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */ | |
66 | #define CONFIG_BTB /* toggle branch predition */ | |
67 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
68 | ||
69 | /* | |
70 | * Only possible on E500 Version 2 or newer cores. | |
71 | */ | |
72 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
73 | ||
74 | ||
75 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
76 | ||
77 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
78 | #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ | |
79 | #define CFG_MEMTEST_END 0x00400000 | |
80 | ||
81 | /* | |
82 | * Base addresses -- Note these are effective addresses where the | |
83 | * actual resources get mapped (not physical addresses) | |
84 | */ | |
85 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
86 | #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ | |
87 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ | |
88 | ||
89 | /* | |
90 | * DDR Setup | |
91 | */ | |
92 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
93 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE | |
94 | ||
95 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
96 | ||
97 | /* | |
98 | * Make sure required options are set | |
99 | */ | |
100 | #ifndef CONFIG_SPD_EEPROM | |
101 | #error ("CONFIG_SPD_EEPROM is required") | |
102 | #endif | |
103 | ||
104 | #undef CONFIG_CLOCKS_IN_MHZ | |
105 | ||
106 | ||
107 | /* | |
108 | * Local Bus Definitions | |
109 | */ | |
110 | ||
111 | /* | |
112 | * FLASH on the Local Bus | |
113 | * Two banks, 8M each, using the CFI driver. | |
114 | * Boot from BR0/OR0 bank at 0xff00_0000 | |
115 | * Alternate BR1/OR1 bank at 0xff80_0000 | |
116 | * | |
117 | * BR0, BR1: | |
118 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 | |
119 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 | |
120 | * Port Size = 16 bits = BRx[19:20] = 10 | |
121 | * Use GPCM = BRx[24:26] = 000 | |
122 | * Valid = BRx[31] = 1 | |
123 | * | |
124 | * 0 4 8 12 16 20 24 28 | |
125 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
126 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
127 | * | |
128 | * OR0, OR1: | |
129 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 | |
130 | * Reserved ORx[17:18] = 11, confusion here? | |
131 | * CSNT = ORx[20] = 1 | |
132 | * ACS = half cycle delay = ORx[21:22] = 11 | |
133 | * SCY = 6 = ORx[24:27] = 0110 | |
134 | * TRLX = use relaxed timing = ORx[29] = 1 | |
135 | * EAD = use external address latch delay = OR[31] = 1 | |
136 | * | |
137 | * 0 4 8 12 16 20 24 28 | |
138 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
139 | */ | |
140 | #define CFG_BCSR_BASE 0xf8000000 | |
141 | ||
142 | #define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ | |
143 | ||
144 | /*Chip select 0 - Flash*/ | |
145 | #define CFG_BR0_PRELIM 0xfe001001 | |
146 | #define CFG_OR0_PRELIM 0xfe006ff7 | |
147 | ||
148 | /*Chip slelect 1 - BCSR*/ | |
149 | #define CFG_BR1_PRELIM 0xf8000801 | |
150 | #define CFG_OR1_PRELIM 0xffffe9f7 | |
151 | ||
152 | //#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} | |
153 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
154 | #define CFG_MAX_FLASH_SECT 512 /* sectors per device */ | |
155 | #undef CFG_FLASH_CHECKSUM | |
156 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
157 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
158 | ||
159 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
160 | ||
161 | #define CFG_FLASH_CFI_DRIVER | |
162 | #define CFG_FLASH_CFI | |
163 | #define CFG_FLASH_EMPTY_INFO | |
164 | ||
165 | ||
166 | /* | |
167 | * SDRAM on the LocalBus | |
168 | */ | |
169 | #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ | |
170 | #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
171 | ||
172 | ||
173 | /*Chip select 2 - SDRAM*/ | |
174 | #define CFG_BR2_PRELIM 0xf0001861 | |
175 | #define CFG_OR2_PRELIM 0xfc006901 | |
176 | ||
177 | #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ | |
178 | #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ | |
179 | #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
180 | #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
181 | ||
182 | /* | |
183 | * LSDMR masks | |
184 | */ | |
185 | #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) | |
186 | #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) | |
187 | #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) | |
188 | #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) | |
189 | #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) | |
190 | #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) | |
191 | #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) | |
192 | #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) | |
193 | #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) | |
194 | #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) | |
195 | ||
196 | #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) | |
197 | #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) | |
198 | #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) | |
199 | #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) | |
200 | #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) | |
201 | #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) | |
202 | #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) | |
203 | #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) | |
204 | ||
205 | /* | |
206 | * Common settings for all Local Bus SDRAM commands. | |
207 | * At run time, either BSMA1516 (for CPU 1.1) | |
208 | * or BSMA1617 (for CPU 1.0) (old) | |
209 | * is OR'ed in too. | |
210 | */ | |
211 | #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ | |
212 | | CFG_LBC_LSDMR_PRETOACT7 \ | |
213 | | CFG_LBC_LSDMR_ACTTORW7 \ | |
214 | | CFG_LBC_LSDMR_BL8 \ | |
215 | | CFG_LBC_LSDMR_WRC4 \ | |
216 | | CFG_LBC_LSDMR_CL3 \ | |
217 | | CFG_LBC_LSDMR_RFEN \ | |
218 | ) | |
219 | ||
220 | /* | |
221 | * The bcsr registers are connected to CS3 on MDS. | |
222 | * The new memory map places bcsr at 0xf8000000. | |
223 | * | |
224 | * For BR3, need: | |
225 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
226 | * port-size = 8-bits = BR[19:20] = 01 | |
227 | * no parity checking = BR[21:22] = 00 | |
228 | * GPMC for MSEL = BR[24:26] = 000 | |
229 | * Valid = BR[31] = 1 | |
230 | * | |
231 | * 0 4 8 12 16 20 24 28 | |
232 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 | |
233 | * | |
234 | * For OR3, need: | |
235 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 | |
236 | * disable buffer ctrl OR[19] = 0 | |
237 | * CSNT OR[20] = 1 | |
238 | * ACS OR[21:22] = 11 | |
239 | * XACS OR[23] = 1 | |
240 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe | |
241 | * SETA OR[28] = 0 | |
242 | * TRLX OR[29] = 1 | |
243 | * EHTR OR[30] = 1 | |
244 | * EAD extra time OR[31] = 1 | |
245 | * | |
246 | * 0 4 8 12 16 20 24 28 | |
247 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 | |
248 | */ | |
249 | #define CFG_BCSR (0xf8000000) | |
250 | ||
251 | /*Chip slelect 4 - PIB*/ | |
252 | #define CFG_BR4_PRELIM 0xf8008801 | |
253 | #define CFG_OR4_PRELIM 0xffffe9f7 | |
254 | ||
255 | /*Chip select 5 - PIB*/ | |
256 | #define CFG_BR5_PRELIM 0xf8010801 | |
257 | #define CFG_OR5_PRELIM 0xffff69f7 | |
258 | ||
259 | #define CONFIG_L1_INIT_RAM | |
260 | #define CFG_INIT_RAM_LOCK 1 | |
261 | #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
262 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
263 | ||
264 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
265 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
266 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
267 | ||
268 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
269 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
270 | ||
271 | /* Serial Port */ | |
272 | #define CONFIG_CONS_INDEX 1 | |
273 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
274 | #define CFG_NS16550 | |
275 | #define CFG_NS16550_SERIAL | |
276 | #define CFG_NS16550_REG_SIZE 1 | |
277 | #define CFG_NS16550_CLK get_bus_freq(0) | |
278 | ||
279 | #define CFG_BAUDRATE_TABLE \ | |
280 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
281 | ||
282 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) | |
283 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) | |
284 | ||
285 | /* Use the HUSH parser*/ | |
286 | #define CFG_HUSH_PARSER | |
287 | #ifdef CFG_HUSH_PARSER | |
288 | #define CFG_PROMPT_HUSH_PS2 "> " | |
289 | #endif | |
290 | ||
291 | /* pass open firmware flat tree */ | |
292 | #define CONFIG_OF_FLAT_TREE 1 | |
293 | #define CONFIG_OF_BOARD_SETUP 1 | |
294 | ||
295 | /* maximum size of the flat tree (8K) */ | |
296 | #define OF_FLAT_TREE_MAX_SIZE 8192 | |
297 | ||
298 | #define OF_CPU "PowerPC,8568@0" | |
299 | #define OF_SOC "soc8568@e0000000" | |
300 | #define OF_TBCLK (bd->bi_busfreq / 8) | |
301 | #define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600" | |
302 | ||
303 | /* | |
304 | * I2C | |
305 | */ | |
306 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
307 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
308 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
309 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
310 | #define CFG_I2C_EEPROM_ADDR 0x57 | |
311 | #define CFG_I2C_SLAVE 0x7F | |
312 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
313 | #define CFG_I2C_OFFSET 0x3000 | |
314 | ||
315 | /* | |
316 | * General PCI | |
317 | * Memory Addresses are mapped 1-1. I/O is mapped from 0 | |
318 | */ | |
319 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
320 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
321 | #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
322 | #define CFG_PCI1_IO_BASE 0x00000000 | |
323 | #define CFG_PCI1_IO_PHYS 0xe2000000 | |
324 | #define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ | |
325 | ||
326 | #define CFG_PEX_MEM_BASE 0xa0000000 | |
327 | #define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE | |
328 | #define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */ | |
329 | #define CFG_PEX_IO_BASE 0x00000000 | |
330 | #define CFG_PEX_IO_PHYS 0xe2800000 | |
331 | #define CFG_PEX_IO_SIZE 0x00800000 /* 8M */ | |
332 | ||
333 | #define CFG_SRIO_MEM_BASE 0xc0000000 | |
334 | ||
335 | #if defined(CONFIG_PCI) | |
336 | ||
337 | #define CONFIG_NET_MULTI | |
338 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
339 | ||
340 | #undef CONFIG_EEPRO100 | |
341 | #undef CONFIG_TULIP | |
342 | ||
343 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
344 | #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
345 | ||
346 | #endif /* CONFIG_PCI */ | |
347 | ||
348 | ||
349 | #if defined(CONFIG_TSEC_ENET) | |
350 | ||
351 | #ifndef CONFIG_NET_MULTI | |
352 | #define CONFIG_NET_MULTI 1 | |
353 | #endif | |
354 | ||
355 | #define CONFIG_MII 1 /* MII PHY management */ | |
356 | #define CONFIG_MPC85XX_TSEC1 1 | |
357 | #define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" | |
358 | #define CONFIG_MPC85XX_TSEC2 1 | |
359 | #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" | |
360 | #undef CONFIG_MPC85XX_TSEC3 | |
361 | #undef CONFIG_MPC85XX_TSEC4 | |
362 | #undef CONFIG_MPC85XX_FEC | |
363 | ||
364 | #define TSEC1_PHY_ADDR 2 | |
365 | #define TSEC2_PHY_ADDR 3 | |
366 | ||
367 | #define TSEC1_PHYIDX 0 | |
368 | #define TSEC2_PHYIDX 0 | |
369 | ||
370 | /* Options are: eTSEC[0-3] */ | |
371 | #define CONFIG_ETHPRIME "eTSEC0" | |
372 | ||
373 | #endif /* CONFIG_TSEC_ENET */ | |
374 | ||
375 | /* | |
376 | * Environment | |
377 | */ | |
378 | #define CFG_ENV_IS_IN_FLASH 1 | |
379 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) | |
380 | #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ | |
381 | #define CFG_ENV_SIZE 0x2000 | |
382 | ||
383 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
384 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
385 | ||
386 | #if defined(CONFIG_PCI) | |
387 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | |
388 | | CFG_CMD_PCI \ | |
389 | | CFG_CMD_PING \ | |
390 | | CFG_CMD_I2C \ | |
391 | | CFG_CMD_MII) | |
392 | #else | |
393 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | |
394 | | CFG_CMD_PING \ | |
395 | | CFG_CMD_I2C \ | |
396 | | CFG_CMD_MII) | |
397 | #endif | |
398 | #include <cmd_confdefs.h> | |
399 | ||
400 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
401 | ||
402 | /* | |
403 | * Miscellaneous configurable options | |
404 | */ | |
405 | #define CFG_LONGHELP /* undef to save memory */ | |
406 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
407 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
408 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
409 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
410 | #else | |
411 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
412 | #endif | |
413 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
414 | #define CFG_MAXARGS 16 /* max number of command args */ | |
415 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
416 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
417 | ||
418 | /* | |
419 | * For booting Linux, the board info and command line data | |
420 | * have to be in the first 8 MB of memory, since this is | |
421 | * the maximum mapped by the Linux kernel during initialization. | |
422 | */ | |
423 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
424 | ||
425 | /* Cache Configuration */ | |
426 | #define CFG_DCACHE_SIZE 32768 | |
427 | #define CFG_CACHELINE_SIZE 32 | |
428 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
429 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ | |
430 | #endif | |
431 | ||
432 | /* | |
433 | * Internal Definitions | |
434 | * | |
435 | * Boot Flags | |
436 | */ | |
437 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
438 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
439 | ||
440 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
441 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
442 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
443 | #endif | |
444 | ||
445 | /* | |
446 | * Environment Configuration | |
447 | */ | |
448 | ||
449 | /* The mac addresses for all ethernet interface */ | |
450 | #if defined(CONFIG_TSEC_ENET) | |
451 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD | |
452 | #define CONFIG_HAS_ETH1 | |
453 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD | |
454 | #define CONFIG_HAS_ETH2 | |
455 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD | |
456 | #endif | |
457 | ||
458 | #define CONFIG_IPADDR 192.168.1.253 | |
459 | ||
460 | #define CONFIG_HOSTNAME unknown | |
461 | #define CONFIG_ROOTPATH /nfsroot | |
462 | #define CONFIG_BOOTFILE your.uImage | |
463 | ||
464 | #define CONFIG_SERVERIP 192.168.1.1 | |
465 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
466 | #define CONFIG_NETMASK 255.255.255.0 | |
467 | ||
468 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
469 | ||
470 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
471 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
472 | ||
473 | #define CONFIG_BAUDRATE 115200 | |
474 | ||
475 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
476 | "netdev=eth0\0" \ | |
477 | "consoledev=ttyS0\0" \ | |
478 | "ramdiskaddr=600000\0" \ | |
479 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
480 | "fdtaddr=400000\0" \ | |
481 | "fdtfile=your.fdt.dtb\0" \ | |
482 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
483 | "nfsroot=$serverip:$rootpath " \ | |
484 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
485 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
486 | "ramargs=setenv bootargs root=/dev/ram rw " \ | |
487 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
488 | ||
489 | ||
490 | #define CONFIG_NFSBOOTCOMMAND \ | |
491 | "run nfsargs;" \ | |
492 | "tftp $loadaddr $bootfile;" \ | |
493 | "tftp $fdtaddr $fdtfile;" \ | |
494 | "bootm $loadaddr - $fdtaddr" | |
495 | ||
496 | ||
497 | #define CONFIG_RAMBOOTCOMMAND \ | |
498 | "run ramargs;" \ | |
499 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
500 | "tftp $loadaddr $bootfile;" \ | |
501 | "bootm $loadaddr $ramdiskaddr" | |
502 | ||
503 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
504 | ||
505 | #endif /* __CONFIG_H */ |