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67431059 | 1 | /* |
5f7bbd13 | 2 | * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. |
67431059 | 3 | * |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
67431059 AF |
5 | */ |
6 | ||
7 | /* | |
8 | * mpc8568mds board configuration file | |
9 | */ | |
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
5f7bbd13 KG |
13 | #define CONFIG_SYS_SRIO |
14 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
15 | ||
1563f56e HW |
16 | #define CONFIG_PCI1 1 /* PCI controller */ |
17 | #define CONFIG_PCIE1 1 /* PCIE controller */ | |
18 | #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ | |
842033e6 | 19 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
8ff3de61 | 20 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
0151cbac | 21 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
53677ef1 | 22 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
b96c83d4 | 23 | #define CONFIG_QE /* Enable QE */ |
67431059 | 24 | #define CONFIG_ENV_OVERWRITE |
67431059 | 25 | |
67431059 AF |
26 | #ifndef __ASSEMBLY__ |
27 | extern unsigned long get_clock_freq(void); | |
28 | #endif /*Replace a call to get_clock_freq (after it is implemented)*/ | |
29 | #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ | |
30 | ||
31 | /* | |
32 | * These can be toggled for performance analysis, otherwise use default. | |
33 | */ | |
53677ef1 | 34 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
7a1ac419 | 35 | #define CONFIG_BTB /* toggle branch predition */ |
67431059 AF |
36 | |
37 | /* | |
38 | * Only possible on E500 Version 2 or newer cores. | |
39 | */ | |
40 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
41 | ||
6d0f6bcf JCPV |
42 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
43 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
67431059 | 44 | |
e46fedfe TT |
45 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
46 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
67431059 | 47 | |
e6f5b35b | 48 | /* DDR Setup */ |
e6f5b35b JL |
49 | #undef CONFIG_FSL_DDR_INTERACTIVE |
50 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
51 | #define CONFIG_DDR_SPD | |
9b0ad1b1 | 52 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
e6f5b35b JL |
53 | |
54 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
55 | ||
6d0f6bcf JCPV |
56 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
57 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
67431059 | 58 | |
e6f5b35b JL |
59 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
60 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
67431059 | 61 | |
e6f5b35b JL |
62 | /* I2C addresses of SPD EEPROMs */ |
63 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
64 | ||
65 | /* Make sure required options are set */ | |
67431059 AF |
66 | #ifndef CONFIG_SPD_EEPROM |
67 | #error ("CONFIG_SPD_EEPROM is required") | |
68 | #endif | |
69 | ||
70 | #undef CONFIG_CLOCKS_IN_MHZ | |
71 | ||
67431059 AF |
72 | /* |
73 | * Local Bus Definitions | |
74 | */ | |
75 | ||
76 | /* | |
77 | * FLASH on the Local Bus | |
78 | * Two banks, 8M each, using the CFI driver. | |
79 | * Boot from BR0/OR0 bank at 0xff00_0000 | |
80 | * Alternate BR1/OR1 bank at 0xff80_0000 | |
81 | * | |
82 | * BR0, BR1: | |
83 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 | |
84 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 | |
85 | * Port Size = 16 bits = BRx[19:20] = 10 | |
86 | * Use GPCM = BRx[24:26] = 000 | |
87 | * Valid = BRx[31] = 1 | |
88 | * | |
89 | * 0 4 8 12 16 20 24 28 | |
90 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
91 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
92 | * | |
93 | * OR0, OR1: | |
94 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 | |
95 | * Reserved ORx[17:18] = 11, confusion here? | |
96 | * CSNT = ORx[20] = 1 | |
97 | * ACS = half cycle delay = ORx[21:22] = 11 | |
98 | * SCY = 6 = ORx[24:27] = 0110 | |
99 | * TRLX = use relaxed timing = ORx[29] = 1 | |
100 | * EAD = use external address latch delay = OR[31] = 1 | |
101 | * | |
102 | * 0 4 8 12 16 20 24 28 | |
103 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
104 | */ | |
6d0f6bcf | 105 | #define CONFIG_SYS_BCSR_BASE 0xf8000000 |
67431059 | 106 | |
6d0f6bcf | 107 | #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ |
67431059 AF |
108 | |
109 | /*Chip select 0 - Flash*/ | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_BR0_PRELIM 0xfe001001 |
111 | #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 | |
67431059 AF |
112 | |
113 | /*Chip slelect 1 - BCSR*/ | |
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_BR1_PRELIM 0xf8000801 |
115 | #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 | |
67431059 | 116 | |
6d0f6bcf JCPV |
117 | /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ |
118 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
119 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ | |
120 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
121 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
122 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
67431059 | 123 | |
14d0a02a | 124 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
67431059 | 125 | |
00b1883a | 126 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_FLASH_CFI |
128 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
67431059 | 129 | |
67431059 AF |
130 | /* |
131 | * SDRAM on the LocalBus | |
132 | */ | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
134 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
67431059 | 135 | |
67431059 | 136 | /*Chip select 2 - SDRAM*/ |
6d0f6bcf JCPV |
137 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
138 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 | |
67431059 | 139 | |
6d0f6bcf JCPV |
140 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
141 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
142 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
143 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
67431059 | 144 | |
67431059 AF |
145 | /* |
146 | * Common settings for all Local Bus SDRAM commands. | |
147 | * At run time, either BSMA1516 (for CPU 1.1) | |
148 | * or BSMA1617 (for CPU 1.0) (old) | |
149 | * is OR'ed in too. | |
150 | */ | |
b0fe93ed KG |
151 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
152 | | LSDMR_PRETOACT7 \ | |
153 | | LSDMR_ACTTORW7 \ | |
154 | | LSDMR_BL8 \ | |
155 | | LSDMR_WRC4 \ | |
156 | | LSDMR_CL3 \ | |
157 | | LSDMR_RFEN \ | |
67431059 AF |
158 | ) |
159 | ||
160 | /* | |
161 | * The bcsr registers are connected to CS3 on MDS. | |
162 | * The new memory map places bcsr at 0xf8000000. | |
163 | * | |
164 | * For BR3, need: | |
165 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
166 | * port-size = 8-bits = BR[19:20] = 01 | |
167 | * no parity checking = BR[21:22] = 00 | |
168 | * GPMC for MSEL = BR[24:26] = 000 | |
169 | * Valid = BR[31] = 1 | |
170 | * | |
171 | * 0 4 8 12 16 20 24 28 | |
172 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 | |
173 | * | |
174 | * For OR3, need: | |
175 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 | |
176 | * disable buffer ctrl OR[19] = 0 | |
177 | * CSNT OR[20] = 1 | |
178 | * ACS OR[21:22] = 11 | |
179 | * XACS OR[23] = 1 | |
180 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe | |
181 | * SETA OR[28] = 0 | |
182 | * TRLX OR[29] = 1 | |
183 | * EHTR OR[30] = 1 | |
184 | * EAD extra time OR[31] = 1 | |
185 | * | |
186 | * 0 4 8 12 16 20 24 28 | |
187 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 | |
188 | */ | |
6d0f6bcf | 189 | #define CONFIG_SYS_BCSR (0xf8000000) |
67431059 AF |
190 | |
191 | /*Chip slelect 4 - PIB*/ | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_BR4_PRELIM 0xf8008801 |
193 | #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 | |
67431059 AF |
194 | |
195 | /*Chip select 5 - PIB*/ | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_BR5_PRELIM 0xf8010801 |
197 | #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 | |
67431059 | 198 | |
6d0f6bcf JCPV |
199 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
200 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 201 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
67431059 | 202 | |
25ddd1fb | 203 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 204 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
67431059 | 205 | |
6d0f6bcf | 206 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
cdab5e90 | 207 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
67431059 AF |
208 | |
209 | /* Serial Port */ | |
210 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_NS16550_SERIAL |
212 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
213 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
67431059 | 214 | |
6d0f6bcf | 215 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
67431059 AF |
216 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
217 | ||
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
219 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
67431059 | 220 | |
67431059 AF |
221 | /* |
222 | * I2C | |
223 | */ | |
00f792e0 HS |
224 | #define CONFIG_SYS_I2C |
225 | #define CONFIG_SYS_I2C_FSL | |
226 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
227 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
228 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
229 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
230 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
231 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
232 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
6d0f6bcf | 233 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
67431059 AF |
234 | |
235 | /* | |
236 | * General PCI | |
237 | * Memory Addresses are mapped 1-1. I/O is mapped from 0 | |
238 | */ | |
5af0fdd8 | 239 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
10795f42 | 240 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 241 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
6d0f6bcf | 242 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 243 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 244 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
246 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ | |
247 | ||
3f6f9d76 | 248 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
5af0fdd8 | 249 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
10795f42 | 250 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
5af0fdd8 | 251 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
6d0f6bcf | 252 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 253 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 |
5f91ef6a | 254 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
255 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 |
256 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
257 | ||
5f7bbd13 KG |
258 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 |
259 | #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 | |
260 | #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS | |
261 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ | |
67431059 | 262 | |
da9d4610 AF |
263 | #ifdef CONFIG_QE |
264 | /* | |
265 | * QE UEC ethernet configuration | |
266 | */ | |
267 | #define CONFIG_UEC_ETH | |
268 | #ifndef CONFIG_TSEC_ENET | |
78b7a8ef | 269 | #define CONFIG_ETHPRIME "UEC0" |
da9d4610 AF |
270 | #endif |
271 | #define CONFIG_PHY_MODE_NEED_CHANGE | |
272 | #define CONFIG_eTSEC_MDIO_BUS | |
273 | ||
274 | #ifdef CONFIG_eTSEC_MDIO_BUS | |
53677ef1 | 275 | #define CONFIG_MIIM_ADDRESS 0xE0024520 |
da9d4610 AF |
276 | #endif |
277 | ||
278 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
279 | ||
280 | #ifdef CONFIG_UEC_ETH1 | |
6d0f6bcf JCPV |
281 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ |
282 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE | |
283 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 | |
284 | #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH | |
285 | #define CONFIG_SYS_UEC1_PHY_ADDR 7 | |
865ff856 | 286 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 287 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 |
da9d4610 AF |
288 | #endif |
289 | ||
290 | #define CONFIG_UEC_ETH2 /* GETH2 */ | |
291 | ||
292 | #ifdef CONFIG_UEC_ETH2 | |
6d0f6bcf JCPV |
293 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
294 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE | |
295 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 | |
296 | #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH | |
297 | #define CONFIG_SYS_UEC2_PHY_ADDR 1 | |
865ff856 | 298 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 299 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 |
da9d4610 AF |
300 | #endif |
301 | #endif /* CONFIG_QE */ | |
302 | ||
f30ad49b | 303 | #if defined(CONFIG_PCI) |
67431059 AF |
304 | #undef CONFIG_EEPRO100 |
305 | #undef CONFIG_TULIP | |
306 | ||
307 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 308 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
67431059 AF |
309 | |
310 | #endif /* CONFIG_PCI */ | |
311 | ||
da9d4610 AF |
312 | #if defined(CONFIG_TSEC_ENET) |
313 | ||
67431059 | 314 | #define CONFIG_MII 1 /* MII PHY management */ |
255a3577 KP |
315 | #define CONFIG_TSEC1 1 |
316 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
317 | #define CONFIG_TSEC2 1 | |
318 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
67431059 AF |
319 | |
320 | #define TSEC1_PHY_ADDR 2 | |
321 | #define TSEC2_PHY_ADDR 3 | |
322 | ||
323 | #define TSEC1_PHYIDX 0 | |
324 | #define TSEC2_PHYIDX 0 | |
325 | ||
3a79013e AF |
326 | #define TSEC1_FLAGS TSEC_GIGABIT |
327 | #define TSEC2_FLAGS TSEC_GIGABIT | |
328 | ||
b96c83d4 | 329 | /* Options are: eTSEC[0-1] */ |
67431059 AF |
330 | #define CONFIG_ETHPRIME "eTSEC0" |
331 | ||
332 | #endif /* CONFIG_TSEC_ENET */ | |
333 | ||
334 | /* | |
335 | * Environment | |
336 | */ | |
cdab5e90 | 337 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
0e8d1586 | 338 | #define CONFIG_ENV_SIZE 0x2000 |
cdab5e90 | 339 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
67431059 AF |
340 | |
341 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 342 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
67431059 | 343 | |
079a136c JL |
344 | /* |
345 | * BOOTP options | |
346 | */ | |
347 | #define CONFIG_BOOTP_BOOTFILESIZE | |
079a136c | 348 | |
67431059 AF |
349 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
350 | ||
351 | /* | |
352 | * Miscellaneous configurable options | |
353 | */ | |
6d0f6bcf | 354 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
67431059 AF |
355 | |
356 | /* | |
357 | * For booting Linux, the board info and command line data | |
a832ac41 | 358 | * have to be in the first 64 MB of memory, since this is |
67431059 AF |
359 | * the maximum mapped by the Linux kernel during initialization. |
360 | */ | |
a832ac41 KG |
361 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
362 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
67431059 | 363 | |
2835e518 | 364 | #if defined(CONFIG_CMD_KGDB) |
67431059 | 365 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
67431059 AF |
366 | #endif |
367 | ||
368 | /* | |
369 | * Environment Configuration | |
370 | */ | |
371 | ||
372 | /* The mac addresses for all ethernet interface */ | |
da9d4610 AF |
373 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) |
374 | #define CONFIG_HAS_ETH0 | |
67431059 | 375 | #define CONFIG_HAS_ETH1 |
67431059 | 376 | #define CONFIG_HAS_ETH2 |
da9d4610 | 377 | #define CONFIG_HAS_ETH3 |
67431059 AF |
378 | #endif |
379 | ||
380 | #define CONFIG_IPADDR 192.168.1.253 | |
381 | ||
382 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 383 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 384 | #define CONFIG_BOOTFILE "your.uImage" |
67431059 AF |
385 | |
386 | #define CONFIG_SERVERIP 192.168.1.1 | |
387 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
388 | #define CONFIG_NETMASK 255.255.255.0 | |
389 | ||
390 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
391 | ||
67431059 AF |
392 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
393 | "netdev=eth0\0" \ | |
394 | "consoledev=ttyS0\0" \ | |
395 | "ramdiskaddr=600000\0" \ | |
396 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
397 | "fdtaddr=400000\0" \ | |
398 | "fdtfile=your.fdt.dtb\0" \ | |
399 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
400 | "nfsroot=$serverip:$rootpath " \ | |
401 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
402 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
403 | "ramargs=setenv bootargs root=/dev/ram rw " \ | |
404 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
405 | ||
67431059 AF |
406 | #define CONFIG_NFSBOOTCOMMAND \ |
407 | "run nfsargs;" \ | |
408 | "tftp $loadaddr $bootfile;" \ | |
409 | "tftp $fdtaddr $fdtfile;" \ | |
410 | "bootm $loadaddr - $fdtaddr" | |
411 | ||
67431059 AF |
412 | #define CONFIG_RAMBOOTCOMMAND \ |
413 | "run ramargs;" \ | |
414 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
415 | "tftp $loadaddr $bootfile;" \ | |
416 | "bootm $loadaddr $ramdiskaddr" | |
417 | ||
418 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
419 | ||
420 | #endif /* __CONFIG_H */ |