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5c9efb36 | 1 | /* |
1b77ca8a | 2 | * Copyright 2006, 2010-2011 Freescale Semiconductor. |
5c9efb36 | 3 | * |
debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /* | |
5c9efb36 | 26 | * MPC8641HPCN board configuration file |
debb7354 JL |
27 | * |
28 | * Make sure you change the MAC address and other network params first, | |
29 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. | |
30 | */ | |
31 | ||
32 | #ifndef __CONFIG_H | |
33 | #define __CONFIG_H | |
34 | ||
35 | /* High Level Configuration Options */ | |
36 | #define CONFIG_MPC86xx 1 /* MPC86xx */ | |
37 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ | |
38 | #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ | |
7649a590 | 39 | #define CONFIG_MP 1 /* support multiple processors */ |
53677ef1 | 40 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
3111d32c | 41 | /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ |
d591a80e | 42 | #define CONFIG_ADDR_MAP 1 /* Use addr map */ |
debb7354 | 43 | |
2ae18241 WD |
44 | /* |
45 | * default CCSRBAR is at 0xff700000 | |
46 | * assume U-Boot is less than 0.5MB | |
47 | */ | |
48 | #define CONFIG_SYS_TEXT_BASE 0xeff00000 | |
49 | ||
debb7354 | 50 | #ifdef RUN_DIAG |
6bf98b13 | 51 | #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE |
debb7354 | 52 | #endif |
5c9efb36 | 53 | |
1266df88 BB |
54 | /* |
55 | * virtual address to be used for temporary mappings. There | |
56 | * should be 128k free at this VA. | |
57 | */ | |
58 | #define CONFIG_SYS_SCRATCH_VA 0xe0000000 | |
59 | ||
1b77ca8a KG |
60 | #define CONFIG_SYS_SRIO |
61 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
af5d100e | 62 | |
63cec581 | 63 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
46f3e385 KG |
64 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ |
65 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ | |
63cec581 | 66 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
8ba93f68 | 67 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
4933b91f | 68 | #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ |
5c9efb36 | 69 | |
53677ef1 | 70 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
debb7354 | 71 | #define CONFIG_ENV_OVERWRITE |
debb7354 | 72 | |
4bbfd3e2 | 73 | #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ |
31d82672 | 74 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ |
d591a80e | 75 | #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ |
debb7354 | 76 | |
53677ef1 | 77 | #define CONFIG_ALTIVEC 1 |
debb7354 | 78 | |
5c9efb36 | 79 | /* |
debb7354 JL |
80 | * L2CR setup -- make sure this is right for your board! |
81 | */ | |
6d0f6bcf | 82 | #define CONFIG_SYS_L2 |
debb7354 JL |
83 | #define L2_INIT 0 |
84 | #define L2_ENABLE (L2CR_L2E) | |
85 | ||
86 | #ifndef CONFIG_SYS_CLK_FREQ | |
63cec581 ES |
87 | #ifndef __ASSEMBLY__ |
88 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
89 | #endif | |
53677ef1 | 90 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
debb7354 JL |
91 | #endif |
92 | ||
debb7354 JL |
93 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
94 | ||
6d0f6bcf JCPV |
95 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
96 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
debb7354 | 97 | |
3111d32c BB |
98 | /* |
99 | * With the exception of PCI Memory and Rapid IO, most devices will simply | |
100 | * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA | |
101 | * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. | |
102 | */ | |
103 | #ifdef CONFIG_PHYS_64BIT | |
104 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL | |
105 | #else | |
106 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0 | |
107 | #endif | |
108 | ||
debb7354 JL |
109 | /* |
110 | * Base addresses -- Note these are effective addresses where the | |
111 | * actual resources get mapped (not physical addresses) | |
112 | */ | |
6d0f6bcf | 113 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
c759a01a | 114 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
6d0f6bcf | 115 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
debb7354 | 116 | |
3111d32c BB |
117 | /* Physical addresses */ |
118 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
119 | #ifdef CONFIG_PHYS_64BIT | |
120 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf | |
d52082b1 BB |
121 | #define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \ |
122 | | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32)) | |
3111d32c BB |
123 | #else |
124 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 | |
d52082b1 | 125 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW |
3111d32c BB |
126 | #endif |
127 | ||
076bff8f YS |
128 | #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ |
129 | ||
debb7354 JL |
130 | /* |
131 | * DDR Setup | |
132 | */ | |
6a8e5692 KG |
133 | #define CONFIG_FSL_DDR2 |
134 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
135 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
136 | #define CONFIG_DDR_SPD | |
137 | ||
138 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
139 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
140 | ||
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
142 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
1266df88 | 143 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
fcb28e76 | 144 | #define CONFIG_VERY_BIG_RAM |
debb7354 | 145 | |
6a8e5692 KG |
146 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
147 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
148 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
149 | ||
150 | /* | |
151 | * I2C addresses of SPD EEPROMs | |
152 | */ | |
153 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ | |
154 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ | |
155 | #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ | |
156 | #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ | |
157 | ||
158 | ||
159 | /* | |
160 | * These are used when DDR doesn't use SPD. | |
161 | */ | |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
163 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F | |
164 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ | |
165 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
166 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
167 | #define CONFIG_SYS_DDR_TIMING_1 0x39357322 | |
168 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
169 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
170 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
171 | #define CONFIG_SYS_DDR_INTERVAL 0x06090100 | |
172 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
173 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
174 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
175 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
176 | #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ | |
177 | #define CONFIG_SYS_DDR_CONTROL2 0x04400000 | |
6a8e5692 | 178 | |
ad8f8687 | 179 | #define CONFIG_ID_EEPROM |
6d0f6bcf | 180 | #define CONFIG_SYS_I2C_EEPROM_NXID |
32628c50 | 181 | #define CONFIG_ID_EEPROM |
6d0f6bcf JCPV |
182 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
183 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
debb7354 | 184 | |
c759a01a | 185 | #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ |
3111d32c BB |
186 | #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ |
187 | | CONFIG_SYS_PHYS_ADDR_HIGH) | |
188 | ||
b81b773e | 189 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
debb7354 | 190 | |
3111d32c BB |
191 | #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
192 | | 0x00001001) /* port size 16bit */ | |
193 | #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ | |
debb7354 | 194 | |
3111d32c BB |
195 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ |
196 | | 0x00001001) /* port size 16bit */ | |
197 | #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ | |
debb7354 | 198 | |
3111d32c BB |
199 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ |
200 | | 0x00000801) /* port size 8bit */ | |
201 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ | |
debb7354 | 202 | |
c759a01a BB |
203 | /* |
204 | * The LBC_BASE is the base of the region that contains the PIXIS and the CF. | |
205 | * The PIXIS and CF by themselves aren't large enough to take up the 128k | |
206 | * required for the smallest BAT mapping, so there's a 64k hole. | |
207 | */ | |
208 | #define CONFIG_SYS_LBC_BASE 0xffde0000 | |
3111d32c BB |
209 | #define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \ |
210 | | CONFIG_SYS_PHYS_ADDR_HIGH) | |
debb7354 | 211 | |
7608d75f | 212 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
c759a01a | 213 | #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) |
3111d32c | 214 | #define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000) |
c759a01a | 215 | #define PIXIS_SIZE 0x00008000 /* 32k */ |
5c9efb36 JL |
216 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
217 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
218 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
219 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
220 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ | |
221 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
222 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
223 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
224 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
225 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
9af9c6bd KG |
226 | #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ |
227 | #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ | |
5c9efb36 JL |
228 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
229 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
230 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
231 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
6d0f6bcf | 232 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
debb7354 | 233 | |
b5431560 | 234 | /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ |
c759a01a | 235 | #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) |
3111d32c | 236 | #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) |
b5431560 | 237 | |
170deacb | 238 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
6d0f6bcf | 239 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
debb7354 | 240 | |
6d0f6bcf JCPV |
241 | #undef CONFIG_SYS_FLASH_CHECKSUM |
242 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
243 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
14d0a02a | 244 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
bf9a8c34 | 245 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ |
debb7354 | 246 | |
00b1883a | 247 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
248 | #define CONFIG_SYS_FLASH_CFI |
249 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
debb7354 | 250 | |
6d0f6bcf JCPV |
251 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
252 | #define CONFIG_SYS_RAMBOOT | |
debb7354 | 253 | #else |
6d0f6bcf | 254 | #undef CONFIG_SYS_RAMBOOT |
debb7354 JL |
255 | #endif |
256 | ||
6d0f6bcf | 257 | #if defined(CONFIG_SYS_RAMBOOT) |
fa7db9c3 | 258 | #undef CONFIG_SPD_EEPROM |
6d0f6bcf | 259 | #define CONFIG_SYS_SDRAM_SIZE 256 |
debb7354 JL |
260 | #endif |
261 | ||
262 | #undef CONFIG_CLOCKS_IN_MHZ | |
263 | ||
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
265 | #ifndef CONFIG_SYS_INIT_RAM_LOCK | |
266 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
debb7354 | 267 | #else |
6d0f6bcf | 268 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
debb7354 | 269 | #endif |
553f0982 | 270 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
debb7354 | 271 | |
25ddd1fb | 272 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 273 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
debb7354 | 274 | |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
276 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
debb7354 JL |
277 | |
278 | /* Serial Port */ | |
279 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_NS16550 |
281 | #define CONFIG_SYS_NS16550_SERIAL | |
282 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
283 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
debb7354 | 284 | |
6d0f6bcf | 285 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
debb7354 JL |
286 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
287 | ||
6d0f6bcf JCPV |
288 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
289 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
debb7354 JL |
290 | |
291 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
292 | #define CONFIG_SYS_HUSH_PARSER |
293 | #ifdef CONFIG_SYS_HUSH_PARSER | |
294 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
debb7354 JL |
295 | #endif |
296 | ||
5c9efb36 JL |
297 | /* |
298 | * Pass open firmware flat tree to kernel | |
299 | */ | |
ea9f7395 JL |
300 | #define CONFIG_OF_LIBFDT 1 |
301 | #define CONFIG_OF_BOARD_SETUP 1 | |
302 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
debb7354 | 303 | |
586d1d5a JL |
304 | /* |
305 | * I2C | |
306 | */ | |
20476726 JL |
307 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
308 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
debb7354 | 309 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
311 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
312 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
313 | #define CONFIG_SYS_I2C_OFFSET 0x3100 | |
debb7354 | 314 | |
586d1d5a JL |
315 | /* |
316 | * RapidIO MMU | |
317 | */ | |
1b77ca8a | 318 | #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ |
3111d32c | 319 | #ifdef CONFIG_PHYS_64BIT |
1b77ca8a | 320 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0x0000000c00000000ULL |
3111d32c | 321 | #else |
1b77ca8a | 322 | #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE |
3111d32c | 323 | #endif |
1b77ca8a | 324 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ |
debb7354 JL |
325 | |
326 | /* | |
327 | * General PCI | |
328 | * Addresses are mapped 1-1. | |
329 | */ | |
49f46f3b | 330 | |
64e55d5e | 331 | #define CONFIG_SYS_PCIE1_NAME "ULI" |
46f3e385 | 332 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
3111d32c | 333 | #ifdef CONFIG_PHYS_64BIT |
46f3e385 KG |
334 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
335 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x0000000c00000000ULL | |
3111d32c | 336 | #else |
46f3e385 KG |
337 | #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT |
338 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT | |
3111d32c | 339 | #endif |
46f3e385 KG |
340 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
341 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
342 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
343 | #define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_PCIE1_IO_VIRT \ | |
3111d32c | 344 | | CONFIG_SYS_PHYS_ADDR_HIGH) |
46f3e385 | 345 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ |
debb7354 | 346 | |
4c78d4a6 BB |
347 | #ifdef CONFIG_PHYS_64BIT |
348 | /* | |
46f3e385 | 349 | * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. |
4c78d4a6 BB |
350 | * This will increase the amount of PCI address space available for |
351 | * for mapping RAM. | |
352 | */ | |
46f3e385 | 353 | #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS |
4c78d4a6 | 354 | #else |
46f3e385 KG |
355 | #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ |
356 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
4c78d4a6 | 357 | #endif |
46f3e385 KG |
358 | #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ |
359 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
360 | #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ | |
361 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
362 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
363 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
364 | #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ | |
365 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
366 | #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ | |
367 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
368 | #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE | |
debb7354 | 369 | |
debb7354 JL |
370 | #if defined(CONFIG_PCI) |
371 | ||
53677ef1 | 372 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
debb7354 | 373 | |
6d0f6bcf | 374 | #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE |
debb7354 JL |
375 | |
376 | #define CONFIG_NET_MULTI | |
53677ef1 | 377 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
debb7354 JL |
378 | |
379 | #define CONFIG_RTL8139 | |
380 | ||
debb7354 JL |
381 | #undef CONFIG_EEPRO100 |
382 | #undef CONFIG_TULIP | |
383 | ||
a81d1c0b ZW |
384 | /************************************************************ |
385 | * USB support | |
386 | ************************************************************/ | |
53677ef1 | 387 | #define CONFIG_PCI_OHCI 1 |
a81d1c0b | 388 | #define CONFIG_USB_OHCI_NEW 1 |
53677ef1 | 389 | #define CONFIG_USB_KEYBOARD 1 |
52cb4d4f | 390 | #define CONFIG_SYS_STDIO_DEREGISTER |
6d0f6bcf JCPV |
391 | #define CONFIG_SYS_USB_EVENT_POLL 1 |
392 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
393 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
394 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 | |
a81d1c0b | 395 | |
0f460a1e | 396 | /*PCIE video card used*/ |
46f3e385 | 397 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT |
0f460a1e JJ |
398 | |
399 | /*PCI video card used*/ | |
46f3e385 | 400 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ |
0f460a1e JJ |
401 | |
402 | /* video */ | |
403 | #define CONFIG_VIDEO | |
404 | ||
405 | #if defined(CONFIG_VIDEO) | |
406 | #define CONFIG_BIOSEMU | |
407 | #define CONFIG_CFB_CONSOLE | |
408 | #define CONFIG_VIDEO_SW_CURSOR | |
409 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
410 | #define CONFIG_ATI_RADEON_FB | |
411 | #define CONFIG_VIDEO_LOGO | |
412 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
46f3e385 | 413 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT |
0f460a1e JJ |
414 | #endif |
415 | ||
debb7354 | 416 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
debb7354 | 417 | |
dabf9ef8 JZ |
418 | #define CONFIG_DOS_PARTITION |
419 | #define CONFIG_SCSI_AHCI | |
420 | ||
421 | #ifdef CONFIG_SCSI_AHCI | |
422 | #define CONFIG_SATA_ULI5288 | |
6d0f6bcf JCPV |
423 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
424 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
425 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
426 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
dabf9ef8 JZ |
427 | #endif |
428 | ||
debb7354 JL |
429 | #endif /* CONFIG_PCI */ |
430 | ||
debb7354 JL |
431 | #if defined(CONFIG_TSEC_ENET) |
432 | ||
433 | #ifndef CONFIG_NET_MULTI | |
53677ef1 | 434 | #define CONFIG_NET_MULTI 1 |
debb7354 JL |
435 | #endif |
436 | ||
437 | #define CONFIG_MII 1 /* MII PHY management */ | |
438 | ||
53677ef1 WD |
439 | #define CONFIG_TSEC1 1 |
440 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
441 | #define CONFIG_TSEC2 1 | |
442 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
443 | #define CONFIG_TSEC3 1 | |
444 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
445 | #define CONFIG_TSEC4 1 | |
446 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
debb7354 | 447 | |
debb7354 JL |
448 | #define TSEC1_PHY_ADDR 0 |
449 | #define TSEC2_PHY_ADDR 1 | |
450 | #define TSEC3_PHY_ADDR 2 | |
451 | #define TSEC4_PHY_ADDR 3 | |
452 | #define TSEC1_PHYIDX 0 | |
453 | #define TSEC2_PHYIDX 0 | |
454 | #define TSEC3_PHYIDX 0 | |
455 | #define TSEC4_PHYIDX 0 | |
3a79013e AF |
456 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
457 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
458 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
459 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
debb7354 JL |
460 | |
461 | #define CONFIG_ETHPRIME "eTSEC1" | |
462 | ||
463 | #endif /* CONFIG_TSEC_ENET */ | |
464 | ||
3111d32c BB |
465 | /* Contort an addr into the format needed for BATs */ |
466 | #ifdef CONFIG_PHYS_64BIT | |
467 | #define BAT_PHYS_ADDR(x) ((unsigned long) \ | |
468 | ((x & 0x00000000ffffffffULL) | \ | |
469 | ((x & 0x0000000e00000000ULL) >> 24) | \ | |
470 | ((x & 0x0000000100000000ULL) >> 30))) | |
471 | #else | |
472 | #define BAT_PHYS_ADDR(x) (x) | |
473 | #endif | |
474 | ||
475 | ||
476 | /* Put high physical address bits into the BAT format */ | |
477 | #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) | |
478 | #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) | |
479 | ||
586d1d5a | 480 | /* |
c759a01a | 481 | * BAT0 DDR |
debb7354 | 482 | */ |
6d0f6bcf | 483 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
9ff32d8c | 484 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
debb7354 | 485 | |
586d1d5a | 486 | /* |
c759a01a | 487 | * BAT1 LBC (PIXIS/CF) |
af5d100e | 488 | */ |
3111d32c BB |
489 | #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ |
490 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ | |
491 | BATL_GUARDEDSTORAGE) | |
c759a01a BB |
492 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ |
493 | | BATU_VS | BATU_VP) | |
3111d32c BB |
494 | #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ |
495 | | BATL_PP_RW | BATL_MEMCOHERENCE) | |
c759a01a | 496 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U |
af5d100e BB |
497 | |
498 | /* if CONFIG_PCI: | |
46f3e385 | 499 | * BAT2 PCIE1 and PCIE1 MEM |
af5d100e | 500 | * if CONFIG_RIO |
c759a01a | 501 | * BAT2 Rapidio Memory |
debb7354 | 502 | */ |
af5d100e | 503 | #ifdef CONFIG_PCI |
46f3e385 | 504 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ |
3111d32c BB |
505 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
506 | | BATL_GUARDEDSTORAGE) | |
46f3e385 | 507 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ |
af5d100e | 508 | | BATU_VS | BATU_VP) |
46f3e385 | 509 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ |
3111d32c | 510 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
af5d100e BB |
511 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
512 | #else /* CONFIG_RIO */ | |
1b77ca8a | 513 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ |
3111d32c BB |
514 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ |
515 | BATL_GUARDEDSTORAGE) | |
1b77ca8a | 516 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ |
3111d32c | 517 | | BATU_VS | BATU_VP) |
1b77ca8a | 518 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ |
3111d32c BB |
519 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
520 | ||
1b77ca8a | 521 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW \ |
5c9efb36 | 522 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
1b77ca8a KG |
523 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) |
524 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
6d0f6bcf | 525 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
af5d100e | 526 | #endif |
debb7354 | 527 | |
586d1d5a | 528 | /* |
c759a01a | 529 | * BAT3 CCSR Space |
3111d32c BB |
530 | * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs |
531 | * instead. The assembler chokes on ULL. | |
debb7354 | 532 | */ |
3111d32c BB |
533 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ |
534 | | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
535 | | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
536 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
537 | | BATL_GUARDEDSTORAGE) | |
c759a01a BB |
538 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ |
539 | | BATU_VP) | |
3111d32c BB |
540 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ |
541 | | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
542 | | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
543 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
6d0f6bcf | 544 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U |
debb7354 | 545 | |
3111d32c BB |
546 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
547 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
548 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
549 | | BATL_GUARDEDSTORAGE) | |
550 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
551 | | BATU_BL_1M | BATU_VS | BATU_VP) | |
552 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
553 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
554 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
555 | #endif | |
556 | ||
586d1d5a | 557 | /* |
46f3e385 | 558 | * BAT4 PCIE1_IO and PCIE2_IO |
debb7354 | 559 | */ |
46f3e385 | 560 | #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ |
3111d32c BB |
561 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
562 | | BATL_GUARDEDSTORAGE) | |
46f3e385 | 563 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ |
c759a01a | 564 | | BATU_VS | BATU_VP) |
46f3e385 | 565 | #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ |
3111d32c | 566 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
6d0f6bcf | 567 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
debb7354 | 568 | |
586d1d5a | 569 | /* |
c759a01a | 570 | * BAT5 Init RAM for stack in the CPU DCache (no backing memory) |
debb7354 | 571 | */ |
6d0f6bcf JCPV |
572 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
573 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
574 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
575 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
debb7354 | 576 | |
586d1d5a | 577 | /* |
c759a01a | 578 | * BAT6 FLASH |
debb7354 | 579 | */ |
3111d32c BB |
580 | #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
581 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
582 | | BATL_GUARDEDSTORAGE) | |
170deacb BB |
583 | #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ |
584 | | BATU_VP) | |
3111d32c BB |
585 | #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
586 | | BATL_PP_RW | BATL_MEMCOHERENCE) | |
6d0f6bcf | 587 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U |
debb7354 | 588 | |
bf9a8c34 BB |
589 | /* Map the last 1M of flash where we're running from reset */ |
590 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
591 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
14d0a02a | 592 | #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
bf9a8c34 BB |
593 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
594 | | BATL_MEMCOHERENCE) | |
595 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
596 | ||
c759a01a BB |
597 | /* |
598 | * BAT7 FREE - used later for tmp mappings | |
599 | */ | |
6d0f6bcf JCPV |
600 | #define CONFIG_SYS_DBAT7L 0x00000000 |
601 | #define CONFIG_SYS_DBAT7U 0x00000000 | |
602 | #define CONFIG_SYS_IBAT7L 0x00000000 | |
603 | #define CONFIG_SYS_IBAT7U 0x00000000 | |
debb7354 | 604 | |
debb7354 JL |
605 | /* |
606 | * Environment | |
607 | */ | |
6d0f6bcf | 608 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 609 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 610 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) |
0e8d1586 | 611 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
5c9efb36 | 612 | #else |
93f6d725 | 613 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 614 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
5c9efb36 | 615 | #endif |
0f2d6602 | 616 | #define CONFIG_ENV_SIZE 0x2000 |
debb7354 JL |
617 | |
618 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 619 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
debb7354 | 620 | |
2f9c19e4 | 621 | |
659e2f67 JL |
622 | /* |
623 | * BOOTP options | |
624 | */ | |
625 | #define CONFIG_BOOTP_BOOTFILESIZE | |
626 | #define CONFIG_BOOTP_BOOTPATH | |
627 | #define CONFIG_BOOTP_GATEWAY | |
628 | #define CONFIG_BOOTP_HOSTNAME | |
629 | ||
630 | ||
2f9c19e4 JL |
631 | /* |
632 | * Command line configuration. | |
633 | */ | |
634 | #include <config_cmd_default.h> | |
635 | ||
636 | #define CONFIG_CMD_PING | |
637 | #define CONFIG_CMD_I2C | |
4f93f8b1 | 638 | #define CONFIG_CMD_REGINFO |
2f9c19e4 | 639 | |
6d0f6bcf | 640 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 641 | #undef CONFIG_CMD_SAVEENV |
2f9c19e4 JL |
642 | #endif |
643 | ||
644 | #if defined(CONFIG_PCI) | |
645 | #define CONFIG_CMD_PCI | |
646 | #define CONFIG_CMD_SCSI | |
647 | #define CONFIG_CMD_EXT2 | |
bbf4796f | 648 | #define CONFIG_CMD_USB |
debb7354 JL |
649 | #endif |
650 | ||
debb7354 JL |
651 | |
652 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
653 | ||
654 | /* | |
655 | * Miscellaneous configurable options | |
656 | */ | |
6d0f6bcf | 657 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
53677ef1 | 658 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
6d0f6bcf JCPV |
659 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
660 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
debb7354 | 661 | |
2f9c19e4 | 662 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 663 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
debb7354 | 664 | #else |
6d0f6bcf | 665 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
debb7354 JL |
666 | #endif |
667 | ||
6d0f6bcf JCPV |
668 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
669 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
670 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
671 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
debb7354 JL |
672 | |
673 | /* | |
674 | * For booting Linux, the board info and command line data | |
675 | * have to be in the first 8 MB of memory, since this is | |
676 | * the maximum mapped by the Linux kernel during initialization. | |
677 | */ | |
6d0f6bcf | 678 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
debb7354 | 679 | |
2f9c19e4 JL |
680 | #if defined(CONFIG_CMD_KGDB) |
681 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
682 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
debb7354 JL |
683 | #endif |
684 | ||
debb7354 JL |
685 | /* |
686 | * Environment Configuration | |
687 | */ | |
688 | ||
689 | /* The mac addresses for all ethernet interface */ | |
690 | #if defined(CONFIG_TSEC_ENET) | |
53677ef1 | 691 | #define CONFIG_ETHADDR 00:E0:0C:00:00:01 |
debb7354 JL |
692 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
693 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD | |
694 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD | |
695 | #endif | |
696 | ||
10327dc5 | 697 | #define CONFIG_HAS_ETH0 1 |
5c9efb36 JL |
698 | #define CONFIG_HAS_ETH1 1 |
699 | #define CONFIG_HAS_ETH2 1 | |
700 | #define CONFIG_HAS_ETH3 1 | |
debb7354 | 701 | |
18b6c8cd | 702 | #define CONFIG_IPADDR 192.168.1.100 |
debb7354 JL |
703 | |
704 | #define CONFIG_HOSTNAME unknown | |
705 | #define CONFIG_ROOTPATH /opt/nfsroot | |
706 | #define CONFIG_BOOTFILE uImage | |
32922cdc | 707 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
debb7354 | 708 | |
5c9efb36 | 709 | #define CONFIG_SERVERIP 192.168.1.1 |
18b6c8cd | 710 | #define CONFIG_GATEWAYIP 192.168.1.1 |
5c9efb36 | 711 | #define CONFIG_NETMASK 255.255.255.0 |
debb7354 | 712 | |
5c9efb36 JL |
713 | /* default location for tftp and bootm */ |
714 | #define CONFIG_LOADADDR 1000000 | |
debb7354 JL |
715 | |
716 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
53677ef1 | 717 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
debb7354 JL |
718 | |
719 | #define CONFIG_BAUDRATE 115200 | |
720 | ||
53677ef1 WD |
721 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
722 | "netdev=eth0\0" \ | |
723 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
724 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
14d0a02a WD |
725 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
726 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
727 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
728 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
729 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
53677ef1 WD |
730 | "consoledev=ttyS0\0" \ |
731 | "ramdiskaddr=2000000\0" \ | |
732 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
733 | "fdtaddr=c00000\0" \ | |
734 | "fdtfile=mpc8641_hpcn.dtb\0" \ | |
3111d32c BB |
735 | "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ |
736 | "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ | |
53677ef1 WD |
737 | "maxcpus=2" |
738 | ||
739 | ||
740 | #define CONFIG_NFSBOOTCOMMAND \ | |
741 | "setenv bootargs root=/dev/nfs rw " \ | |
742 | "nfsroot=$serverip:$rootpath " \ | |
743 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
744 | "console=$consoledev,$baudrate $othbootargs;" \ | |
745 | "tftp $loadaddr $bootfile;" \ | |
746 | "tftp $fdtaddr $fdtfile;" \ | |
747 | "bootm $loadaddr - $fdtaddr" | |
748 | ||
749 | #define CONFIG_RAMBOOTCOMMAND \ | |
750 | "setenv bootargs root=/dev/ram rw " \ | |
751 | "console=$consoledev,$baudrate $othbootargs;" \ | |
752 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
753 | "tftp $loadaddr $bootfile;" \ | |
754 | "tftp $fdtaddr $fdtfile;" \ | |
755 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
debb7354 JL |
756 | |
757 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
758 | ||
759 | #endif /* __CONFIG_H */ |